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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule |
module uart2_tx #(parameter WIDTH = 8, parameter real BAUD = 9600) (
input reset,
input clk,
//input [1:0] baud_rate,
input ld_tx_data,
input [WIDTH-1:0] tx_data,
input tx_enable,
(* IOB = "TRUE" *) output reg tx_out = 1'b1,
output reg tx_empty = 1'b1
);
//parameter ML505 = 0; //default to 0 if not specified
`ifdef ML505 localparam real CLK_FREQ = 100e6;
`else localparam real CLK_FREQ = 40e6;
`endif
localparam BAUD_CNT_SIZE = bits_to_fit(CLK_FREQ/BAUD);
localparam BIT_CNT_SIZE = bits_to_fit(WIDTH+2);
localparam [BAUD_CNT_SIZE-1:0] FRAME_WIDTH = CLK_FREQ/BAUD;
// Internal registers
reg [WIDTH-1:0] tx_reg = {WIDTH{1'b0}};
reg [BIT_CNT_SIZE-1:0] tx_cnt = {BIT_CNT_SIZE{1'b0}};
reg [BAUD_CNT_SIZE-1:0] baud_cnt = {BAUD_CNT_SIZE{1'b0}};
reg baud_clk = 1'b0;
// UART TX Logic
always @ (posedge clk) begin
if (reset) begin
baud_clk <= 1'b0;
baud_cnt <= {BAUD_CNT_SIZE{1'b0}};
tx_reg <= {WIDTH{1'b0}};
tx_empty <= 1'b1;
tx_out <= 1'b1;
tx_cnt <= {BIT_CNT_SIZE{1'b0}};
end else begin // if (reset)
if (baud_cnt == FRAME_WIDTH) begin
baud_clk <= 1'b1;
baud_cnt <= {BAUD_CNT_SIZE{1'b0}};
end else begin
baud_clk <= 1'b0;
baud_cnt <= baud_cnt + 1'b1;
end
if (tx_enable && baud_clk) begin
if (ld_tx_data && tx_empty) begin
tx_reg <= tx_data;
tx_empty <= 1'b0;
tx_out <= 1'b0; //Send start bit immediately
tx_cnt <= tx_cnt;
end else if (!tx_empty) begin
tx_reg <= tx_reg;
if (tx_cnt == 4'd8) begin
tx_cnt <= 4'd0;
tx_out <= 1'b1;
tx_empty <= 1'b1;
end else begin
tx_cnt <= tx_cnt + 1;
tx_out <= tx_reg[tx_cnt];
tx_empty <= tx_empty;
end
end else begin
tx_reg <= tx_reg;
tx_cnt <= tx_cnt;
tx_out <= tx_out;
tx_empty <= tx_empty;
end
end else begin
tx_reg <= tx_reg;
tx_cnt <= tx_cnt;
tx_out <= tx_out;
tx_empty <= tx_empty;
end //if (~(tx_enable && baud_clk))
end //if (~reset)
end //always
function integer bits_to_fit;
input [31:0] value;
for (bits_to_fit=0; value>0; bits_to_fit=bits_to_fit+1)
value = value >> 1;
endfunction
endmodule |
module or1200_ic_fsm(
// Clock and reset
clk, rst,
// Internal i/f to top level IC
ic_en, icqmem_cycstb_i, icqmem_ci_i,
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
burst, tag_we
);
//
// I/O
//
input clk;
input rst;
input ic_en;
input icqmem_cycstb_i;
input icqmem_ci_i;
input tagcomp_miss;
input biudata_valid;
input biudata_error;
input [31:0] start_addr;
output [31:0] saved_addr;
output [3:0] icram_we;
output biu_read;
output first_hit_ack;
output first_miss_ack;
output first_miss_err;
output burst;
output tag_we;
//
// Internal wires and regs
//
reg [31:0] saved_addr_r;
reg [1:0] state;
reg [2:0] cnt;
reg hitmiss_eval;
reg load;
reg cache_inhibit;
//
// Generate of ICRAM write enables
//
assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
assign saved_addr = saved_addr_r;
//
// Assert for cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icqmem_ci_i;
assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit
| (state == `OR1200_ICFSM_LREFILL3);
//
// Main IC FSM
//
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= #1 `OR1200_ICFSM_IDLE;
saved_addr_r <= #1 32'b0;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cnt <= #1 3'b000;
cache_inhibit <= #1 1'b0;
end
else
case (state) // synopsys parallel_case
`OR1200_ICFSM_IDLE :
if (ic_en & icqmem_cycstb_i) begin // fetch
state <= #1 `OR1200_ICFSM_CFETCH;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b1;
load <= #1 1'b1;
cache_inhibit <= #1 1'b0;
end
else begin // idle
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
`OR1200_ICFSM_CFETCH: begin // fetch
if (icqmem_cycstb_i & icqmem_ci_i)
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if ((!ic_en) ||
(hitmiss_eval & !icqmem_cycstb_i) || // fetch aborted (usually caused by IMMU)
(biudata_error) || // fetch terminated with an error
(cache_inhibit & biudata_valid)) begin // fetch from cache-inhibited page
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill
state <= #1 `OR1200_ICFSM_LREFILL3;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
hitmiss_eval <= #1 1'b0;
cnt <= #1 `OR1200_ICLS-2;
cache_inhibit <= #1 1'b0;
end
else if (!tagcomp_miss & !icqmem_ci_i) begin // fetch hit, finish immediately
saved_addr_r <= #1 start_addr;
cache_inhibit <= #1 1'b0;
end
else if (!icqmem_cycstb_i) begin // fetch aborted (usually caused by exception)
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else // fetch in-progress
hitmiss_eval <= #1 1'b0;
end
`OR1200_ICFSM_LREFILL3 : begin
if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
cnt <= #1 cnt - 3'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
end
else if (biudata_valid) begin // last fetch of line refill
state <= #1 `OR1200_ICFSM_IDLE;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
end
end
default:
state <= #1 `OR1200_ICFSM_IDLE;
endcase
end
endmodule |
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__busdrivernovlp2 dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule |
module spu_mamul (
/*outputs*/
spu_mamul_memren,
spu_mamul_memwen,
spu_mamul_rst_iptr,
spu_mamul_rst_jptr,
spu_mamul_incr_iptr,
spu_mamul_incr_jptr,
spu_mamul_a_rd_oprnd_sel,
spu_mamul_ax_rd_oprnd_sel,
spu_mamul_b_rd_oprnd_sel,
spu_mamul_ba_rd_oprnd_sel,
spu_mamul_m_rd_oprnd_sel,
spu_mamul_me_rd_oprnd_sel,
spu_mamul_n_rd_oprnd_sel,
spu_mamul_m_wr_oprnd_sel,
spu_mamul_me_wr_oprnd_sel,
spu_mamul_i_ptr_sel,
spu_mamul_iminus1_ptr_sel,
spu_mamul_j_ptr_sel,
spu_mamul_iminusj_ptr_sel,
spu_mamul_iminuslenminus1_sel,
spu_mamul_jjptr_wen,
spu_mamul_oprnd2_wen,
spu_mamul_oprnd2_bypass,
spu_mamul_oprnd1_mxsel_l,
spu_mamul_oprnd1_wen,
spu_mul_req_vld,
spu_mul_areg_shf,
spu_mul_acc,
spu_mul_areg_rst,
spu_mamul_mul_done,
spu_mamul_jjptr_sel,
spu_mamul_rst,
/*inputs*/
spu_maaeqb_jjptr_sel,
spu_mactl_mulop,
spu_maaddr_iequtwolenplus2,
spu_maaddr_iequtwolenplus1,
spu_maaddr_jequiminus1,
spu_maaddr_jequlen,
spu_maaddr_halfpnt_set,
spu_mactl_iss_pulse_dly,
spu_mared_oprnd2_wen,
mul_spu_ack,
mul_spu_shf_ack,
spu_maexp_start_mulred_anoteqb,
spu_mactl_expop,
spu_maaddr_aequb,
spu_maaeqb_rst_iptr,
spu_maaeqb_rst_jptr,
spu_maaeqb_incr_iptr,
spu_maaeqb_incr_jptr,
spu_maaeqb_a_rd_oprnd_sel,
spu_maaeqb_ax_rd_oprnd_sel,
spu_maaeqb_m_rd_oprnd_sel,
spu_maaeqb_me_rd_oprnd_sel,
spu_maaeqb_n_rd_oprnd_sel,
spu_maaeqb_m_wr_oprnd_sel,
spu_maaeqb_me_wr_oprnd_sel,
spu_maaeqb_iminus1_ptr_sel,
spu_maaeqb_j_ptr_sel,
spu_maaeqb_iminusj_ptr_sel,
spu_maaeqb_iminuslenminus1_sel,
spu_maaeqb_jjptr_wen,
spu_maaeqb_oprnd2_wen,
spu_maaeqb_oprnd2_bypass,
spu_maaeqb_mul_req_vld,
spu_maaeqb_mul_areg_shf,
spu_maaeqb_mul_acc,
spu_maaeqb_mul_areg_rst,
spu_maaeqb_mul_done,
spu_maaeqb_oprnd1_mxsel,
spu_maaeqb_oprnd1_wen,
spu_mactl_kill_op,
spu_mactl_stxa_force_abort,
se,
reset,
rclk);
// ---------------------------------------------------------------
input reset;
input rclk;
input se;
input spu_maaddr_iequtwolenplus2;
input spu_maaddr_iequtwolenplus1;
input spu_maaddr_jequiminus1;
input spu_maaddr_jequlen;
input spu_maaddr_halfpnt_set;
input mul_spu_ack;
input mul_spu_shf_ack;
input spu_mactl_mulop;
input spu_mactl_iss_pulse_dly;
input spu_mared_oprnd2_wen;
input spu_maexp_start_mulred_anoteqb;
input spu_mactl_expop;
input spu_maaddr_aequb;
input spu_maaeqb_rst_iptr;
input spu_maaeqb_rst_jptr;
input spu_maaeqb_incr_iptr;
input spu_maaeqb_incr_jptr;
input spu_maaeqb_a_rd_oprnd_sel;
input spu_maaeqb_ax_rd_oprnd_sel;
input spu_maaeqb_m_rd_oprnd_sel;
input spu_maaeqb_me_rd_oprnd_sel;
input spu_maaeqb_n_rd_oprnd_sel;
input spu_maaeqb_m_wr_oprnd_sel;
input spu_maaeqb_me_wr_oprnd_sel;
input spu_maaeqb_iminus1_ptr_sel;
input spu_maaeqb_j_ptr_sel;
input spu_maaeqb_iminusj_ptr_sel;
input spu_maaeqb_iminuslenminus1_sel;
input spu_maaeqb_jjptr_wen;
input spu_maaeqb_oprnd2_wen;
input spu_maaeqb_oprnd2_bypass;
input spu_maaeqb_mul_req_vld;
input spu_maaeqb_mul_areg_shf;
input spu_maaeqb_mul_acc;
input spu_maaeqb_mul_areg_rst;
input spu_maaeqb_mul_done;
input [1:0] spu_maaeqb_oprnd1_mxsel;
input spu_maaeqb_oprnd1_wen;
input spu_maaeqb_jjptr_sel;
input spu_mactl_kill_op;
input spu_mactl_stxa_force_abort;
// ---------------------------------------------------------------
output spu_mamul_memwen;
output spu_mamul_memren;
output spu_mamul_rst_iptr;
output spu_mamul_rst_jptr;
output spu_mamul_incr_iptr;
output spu_mamul_incr_jptr;
output spu_mamul_a_rd_oprnd_sel;
output spu_mamul_ax_rd_oprnd_sel;
output spu_mamul_b_rd_oprnd_sel;
output spu_mamul_ba_rd_oprnd_sel;
output spu_mamul_m_rd_oprnd_sel;
output spu_mamul_me_rd_oprnd_sel;
output spu_mamul_n_rd_oprnd_sel;
output spu_mamul_m_wr_oprnd_sel;
output spu_mamul_me_wr_oprnd_sel;
output spu_mamul_i_ptr_sel;
output spu_mamul_iminus1_ptr_sel;
output spu_mamul_j_ptr_sel;
output spu_mamul_iminusj_ptr_sel;
output spu_mamul_iminuslenminus1_sel;
output spu_mamul_jjptr_wen;
output spu_mamul_oprnd2_wen;
output spu_mamul_oprnd2_bypass;
output [2:0] spu_mamul_oprnd1_mxsel_l;
output spu_mamul_oprnd1_wen;
output spu_mul_req_vld;
output spu_mul_areg_shf;
output spu_mul_acc;
output spu_mul_areg_rst;
output spu_mamul_mul_done;
output spu_mamul_jjptr_sel;
output spu_mamul_rst;
// ---------------------------------------------------------------
wire tr2mwrite_frm_accumshft_pre;
wire tr2mwrite_frm_accumshft,tr2iloopa_frm_jloopn;
wire spu_mamul_rd_aj,spu_mamul_rd_biminusj,spu_mamul_rd_mj,
spu_mamul_rd_niminusj,spu_mamul_rd_ai,spu_mamul_rd_b0,
spu_mamul_wr_mi,spu_mamul_wr_miminuslenminus1,
spu_mamul_rd_n0;
wire tr2accumshft_frm_mwrite;
wire tr2accumshft_frm_iloopn;
wire nxt_mwrite_state;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
//wire local_stxa_abort = cur_mwrite_state & spu_mactl_stxa_force_abort;// this causes x to in perr_set
wire local_stxa_abort = nxt_mwrite_state & spu_mactl_stxa_force_abort;
wire state_reset = reset | spu_mactl_kill_op | local_stxa_abort;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
dff_s #(1) idle_state_ff (
.din(nxt_idle_state) ,
.q(cur_idle_state),
.clk (rclk), .se(se), .si(), .so());
dffr_s #(1) jloopa_state_ff (
.din(nxt_jloopa_state) ,
.q(cur_jloopa_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) jloopb_state_ff (
.din(nxt_jloopb_state) ,
.q(cur_jloopb_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) jloopn_state_ff (
.din(nxt_jloopn_state) ,
.q(cur_jloopn_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) jloopm_state_ff (
.din(nxt_jloopm_state) ,
.q(cur_jloopm_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) iloopa_state_ff (
.din(nxt_iloopa_state) ,
.q(cur_iloopa_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) iloopb_state_ff (
.din(nxt_iloopb_state) ,
.q(cur_iloopb_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) nprime_state_ff (
.din(nxt_nprime_state) ,
.q(cur_nprime_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) mwrite_state_ff (
.din(nxt_mwrite_state) ,
.q(cur_mwrite_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) iloopn_state_ff (
.din(nxt_iloopn_state) ,
.q(cur_iloopn_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) accumshft_state_ff (
.din(nxt_accumshft_state) ,
.q(cur_accumshft_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
// ---------------------------------------------------------------
wire spu_maaddr_aequb_q;
dff_s #(1) spu_maaddr_aequb_ff (
.din(spu_maaddr_aequb) ,
.q(spu_maaddr_aequb_q),
.clk (rclk), .se(se), .si(), .so());
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// 4 cycle delay for mul result coming back.
// ---------------------------------------------------------------
wire tr2mwrite_frm_jloopn = cur_jloopn_state & mul_spu_ack & spu_maaddr_halfpnt_set &
spu_maaddr_jequlen;
wire mul_result_c0,mul_result_c1,mul_result_c2,mul_result_c3,mul_result_c4,mul_result_c5;
//assign mul_result_c0 = (cur_nprime_state & mul_spu_ack & ~spu_maaddr_halfpnt_set) |
assign mul_result_c0 = (cur_nprime_state & mul_spu_ack) |
( tr2mwrite_frm_jloopn );
dffr_s #(5) mul_res_ff (
.din({mul_result_c0,mul_result_c1,mul_result_c2,mul_result_c3,mul_result_c4}) ,
.q({mul_result_c1,mul_result_c2,mul_result_c3,mul_result_c4,mul_result_c5}),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
wire tr2idle_frm_accumshft = cur_accumshft_state & spu_maaddr_iequtwolenplus2 &
mul_spu_shf_ack;
wire spu_mamul_mul_done_pre = tr2idle_frm_accumshft;
wire spu_mamul_mul_done_q;
dff_s #(1) muldone_dly_ff (
.din(spu_mamul_mul_done_pre) ,
.q(spu_mamul_mul_done_q),
.clk (rclk), .se(se), .si(), .so());
assign spu_mamul_mul_done = spu_mamul_mul_done_q | spu_maaeqb_mul_done | local_stxa_abort;
assign spu_mamul_rst_iptr = tr2idle_frm_accumshft | spu_maaeqb_rst_iptr;
// the following is to reset jptr on the 1st half.
wire tr2iloopa_frm_jloopn_dly;
dff_s #(1) tr2iloopa_frm_jloopn_dly_ff (
.din(tr2iloopa_frm_jloopn) ,
.q(tr2iloopa_frm_jloopn_dly),
.clk (rclk), .se(se), .si(), .so());
// ---------------------------------------------------------------
wire mulop_start = (spu_mactl_iss_pulse_dly & spu_mactl_mulop & ~spu_maaddr_aequb_q) |
spu_maexp_start_mulred_anoteqb;
assign spu_mul_areg_rst = mulop_start | spu_maaeqb_mul_areg_rst;
assign spu_mamul_rst = spu_mul_areg_rst;
assign nxt_idle_state = (
state_reset |
tr2idle_frm_accumshft |
(cur_idle_state & ~mulop_start));
// ---------------------------------------------------------------
wire tr2jloopa_frm_accumshft = cur_accumshft_state & ~spu_maaddr_iequtwolenplus2 &
~spu_maaddr_iequtwolenplus1 & mul_spu_shf_ack;
wire tr2jloopa_frm_accumshft_dly;
dffr_s #(1) tr2jloopa_frm_accumshft_dly_ff (
.din(tr2jloopa_frm_accumshft) ,
.q(tr2jloopa_frm_accumshft_dly),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
wire tr2jloopa_frm_jloopn = cur_jloopn_state & mul_spu_ack &
((~spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set) |
(~spu_maaddr_jequlen & spu_maaddr_halfpnt_set)) ;
assign nxt_jloopa_state = (
tr2jloopa_frm_jloopn |
tr2jloopa_frm_accumshft_dly );
assign spu_mamul_jjptr_wen = cur_jloopm_state | spu_maaeqb_jjptr_wen;
assign spu_mamul_incr_jptr = tr2jloopa_frm_jloopn | spu_maaeqb_incr_jptr;
assign spu_mamul_jjptr_sel = cur_jloopn_state | spu_maaeqb_jjptr_sel;
//assign spu_mamul_rd_aj = nxt_jloopa_state;
assign spu_mamul_rd_aj =
(cur_jloopn_state & ((~spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set) |
(~spu_maaddr_jequlen & spu_maaddr_halfpnt_set))) |
tr2jloopa_frm_accumshft_dly;
// ---------------------------------------------------------------
assign nxt_jloopb_state = (
cur_jloopa_state |
(cur_jloopb_state & ~mul_spu_ack));
//assign spu_mamul_rd_biminusj = nxt_jloopb_state | cur_jloopb_state;
assign spu_mamul_rd_biminusj = cur_jloopa_state;
// ---------------------------------------------------------------
assign nxt_jloopm_state = (
(cur_jloopb_state & mul_spu_ack));
//assign spu_mamul_rd_mj = nxt_jloopm_state;
assign spu_mamul_rd_mj = cur_jloopb_state;
// ---------------------------------------------------------------
assign nxt_jloopn_state = (
cur_jloopm_state |
(cur_jloopn_state & ~mul_spu_ack));
//assign spu_mamul_rd_niminusj = nxt_jloopn_state;
assign spu_mamul_rd_niminusj = cur_jloopm_state;
// ---------------------------------------------------------------
assign tr2iloopa_frm_jloopn = cur_jloopn_state & mul_spu_ack &
spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set;
wire tr2iloopa_frm_idle = cur_idle_state & mulop_start;
wire tr2iloopa_frm_idle_dly;
dff_s #(1) tr2iloopa_frm_idle_ff (
.din(tr2iloopa_frm_idle) ,
.q(tr2iloopa_frm_idle_dly),
.clk (rclk), .se(se), .si(), .so());
assign nxt_iloopa_state = (
(tr2iloopa_frm_idle_dly) |
(tr2iloopa_frm_jloopn));
// iloop reads are done in cur_* state where as the jloop reads
// are done in nxt_* and cur_* state(this to hold the rd indx during
// requests. Due to read of the iloop in cur_* state the spu_mul_req_vld
// is delayed by a cycle.
//assign spu_mamul_rd_ai = nxt_iloopa_state;
assign spu_mamul_rd_ai =
(cur_jloopn_state & (spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set)) | tr2iloopa_frm_idle_dly;
// ---------------------------------------------------------------
assign nxt_iloopb_state = (
(cur_iloopa_state) |
(cur_iloopb_state & ~mul_spu_ack));
//assign spu_mamul_rd_b0 = nxt_iloopb_state;
assign spu_mamul_rd_b0 = cur_iloopa_state;
// ---------------------------------------------------------------
assign nxt_nprime_state = (
(cur_iloopb_state & mul_spu_ack) |
(cur_nprime_state & ~mul_spu_ack));
// ---------------------------------------------------------------
// assign tr2mwrite_frm_accumshft = cur_accumshft_state & mul_spu_shf_ack &
// spu_maaddr_iequtwolenplus1;
assign tr2mwrite_frm_accumshft_pre = cur_accumshft_state & mul_spu_shf_ack &
spu_maaddr_iequtwolenplus1;
// delaying for one cycle to allow time to do i ptr increment
// and calculate i-len-1(M[i-len-1]).This is due to skipping jloop on last
// i iteration, not enough time to do both.
dffr_s #(1) tr2mwrite_frm_accumshft_ff (
.din(tr2mwrite_frm_accumshft_pre) ,
.q(tr2mwrite_frm_accumshft),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
assign nxt_mwrite_state = (
tr2mwrite_frm_accumshft |
(mul_result_c5));
// assign spu_mamul_memwen = nxt_mwrite_state;
//need the following to capture mul data into flop.
wire spu_mamul_wr_mi_oprnd2_wenbyp = nxt_mwrite_state & ~spu_maaddr_halfpnt_set;
wire spu_mamul_wr_miminuslenminus1_oprnd2_wenbyp = nxt_mwrite_state & spu_maaddr_halfpnt_set;
// ---------------------------------------------------------------
assign nxt_iloopn_state = (
(cur_mwrite_state & ~spu_maaddr_halfpnt_set) |
(cur_iloopn_state & ~mul_spu_ack));
//assign spu_mamul_rd_n0 = nxt_iloopn_state | cur_iloopn_state;
assign spu_mamul_rd_n0 = cur_mwrite_state;
// ---------------------------------------------------------------
assign tr2accumshft_frm_mwrite = cur_mwrite_state & spu_maaddr_halfpnt_set;
assign tr2accumshft_frm_iloopn = cur_iloopn_state & mul_spu_ack;
assign nxt_accumshft_state = (
tr2accumshft_frm_mwrite |
tr2accumshft_frm_iloopn |
(cur_accumshft_state & ~mul_spu_shf_ack));
wire mamul_incr_iptr = tr2accumshft_frm_mwrite | tr2accumshft_frm_iloopn;
assign spu_mamul_incr_iptr = mamul_incr_iptr | spu_maaeqb_incr_iptr;
dff_s #(1) memwen_dly_ff (
.din(mamul_incr_iptr) ,
.q(spu_mamul_memwen),
.clk (rclk), .se(se), .si(), .so());
assign spu_mamul_wr_mi = spu_mamul_memwen & ~spu_maaddr_halfpnt_set;
assign spu_mamul_wr_miminuslenminus1 = spu_mamul_memwen & spu_maaddr_halfpnt_set;
// ---------------------------------------------------------------
wire cur_accumshft_pulse,cur_accumshft_q;
dff_s #(1) cur_accumshft_pulse_ff (
.din(cur_accumshft_state) ,
.q(cur_accumshft_q),
.clk (rclk), .se(se), .si(), .so());
assign cur_accumshft_pulse = ~cur_accumshft_q & cur_accumshft_state;
wire mamul_rst_jptr = mulop_start | tr2iloopa_frm_jloopn_dly | (cur_accumshft_pulse &
spu_maaddr_halfpnt_set & ~spu_maaddr_iequtwolenplus2 &
~spu_maaddr_iequtwolenplus1);
assign spu_mamul_rst_jptr = mamul_rst_jptr | spu_maaeqb_rst_jptr;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// send selects to spu_maaddr.v
// ---------------------------------------------------------------
// ---------------------------------------------------------------
assign spu_mamul_memren = spu_mamul_rd_aj |
spu_mamul_rd_biminusj |
spu_mamul_rd_mj |
spu_mamul_rd_niminusj |
spu_mamul_rd_ai | spu_mamul_rd_b0 | spu_mamul_rd_n0;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
wire mamul_a_rd_oprnd_sel = (spu_mamul_rd_aj | spu_mamul_rd_ai) & ~spu_mactl_expop;
assign spu_mamul_a_rd_oprnd_sel = mamul_a_rd_oprnd_sel | spu_maaeqb_a_rd_oprnd_sel;
wire mamul_ax_rd_oprnd_sel = (spu_mamul_rd_aj | spu_mamul_rd_ai) & spu_mactl_expop;
assign spu_mamul_ax_rd_oprnd_sel = mamul_ax_rd_oprnd_sel | spu_maaeqb_ax_rd_oprnd_sel;
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//assign spu_mamul_b_rd_oprnd_sel = ((spu_mamul_rd_biminusj & ~spu_mamul_rd_aj & ~spu_mamul_rd_mj) |
assign spu_mamul_b_rd_oprnd_sel = (spu_mamul_rd_biminusj |
spu_mamul_rd_b0) & ~spu_mactl_expop;
// bx should be removed, since xxnm does not start mamul, instead it starts maaeqb.
// assign spu_mamul_bx_rd_oprnd_sel = ((spu_mamul_rd_biminusj & ~spu_mamul_rd_aj & ~spu_mamul_rd_mj) |
// spu_mamul_rd_b0) & spu_maexp_b_to_x_sel & spu_mactl_expop;
//assign spu_mamul_ba_rd_oprnd_sel = ((spu_mamul_rd_biminusj & ~spu_mamul_rd_aj & ~spu_mamul_rd_mj) |
assign spu_mamul_ba_rd_oprnd_sel = (spu_mamul_rd_biminusj |
spu_mamul_rd_b0) & spu_mactl_expop;
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
wire mamul_m_rd_oprnd_sel = spu_mamul_rd_mj & ~spu_mactl_expop ;
assign spu_mamul_m_rd_oprnd_sel = mamul_m_rd_oprnd_sel | spu_maaeqb_m_rd_oprnd_sel ;
wire mamul_me_rd_oprnd_sel = spu_mamul_rd_mj & spu_mactl_expop ;
assign spu_mamul_me_rd_oprnd_sel = mamul_me_rd_oprnd_sel | spu_maaeqb_me_rd_oprnd_sel ;
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//wire mamul_n_rd_oprnd_sel = (spu_mamul_rd_niminusj & ~spu_mamul_rd_aj & ~spu_mamul_rd_mj) | spu_mamul_rd_n0;
wire mamul_n_rd_oprnd_sel = spu_mamul_rd_niminusj | spu_mamul_rd_n0;
assign spu_mamul_n_rd_oprnd_sel = mamul_n_rd_oprnd_sel | spu_maaeqb_n_rd_oprnd_sel;
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
wire mamul_m_wr_oprnd_sel = (spu_mamul_wr_mi | spu_mamul_wr_miminuslenminus1) &
~spu_mactl_expop;
assign spu_mamul_m_wr_oprnd_sel = mamul_m_wr_oprnd_sel | spu_maaeqb_m_wr_oprnd_sel;
wire mamul_me_wr_oprnd_sel = (spu_mamul_wr_mi | spu_mamul_wr_miminuslenminus1) &
spu_mactl_expop;
assign spu_mamul_me_wr_oprnd_sel = mamul_me_wr_oprnd_sel | spu_maaeqb_me_wr_oprnd_sel;
wire mamul_m_wr_oprnd2_wen = (spu_mamul_wr_mi_oprnd2_wenbyp |
spu_mamul_wr_miminuslenminus1_oprnd2_wenbyp) &
~spu_mactl_expop;
wire mamul_me_wr_oprnd2_wen = (spu_mamul_wr_mi_oprnd2_wenbyp |
spu_mamul_wr_miminuslenminus1_oprnd2_wenbyp) &
spu_mactl_expop;
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//assign spu_mamul_i_ptr_sel = (spu_mamul_rd_ai | spu_mamul_wr_mi) | spu_maaeqb_i_ptr_sel;
assign spu_mamul_i_ptr_sel = spu_mamul_rd_ai ;
assign spu_mamul_iminus1_ptr_sel = spu_mamul_wr_mi | spu_maaeqb_iminus1_ptr_sel ;
assign spu_mamul_j_ptr_sel = (spu_mamul_rd_aj | spu_mamul_rd_mj) | spu_maaeqb_j_ptr_sel;
wire mamul_iminusj_ptr_sel =
//(spu_mamul_rd_biminusj | spu_mamul_rd_niminusj) & ~(spu_mamul_rd_aj | spu_mamul_rd_mj);
(spu_mamul_rd_biminusj | spu_mamul_rd_niminusj) ;
assign spu_mamul_iminusj_ptr_sel = mamul_iminusj_ptr_sel | spu_maaeqb_iminusj_ptr_sel;
assign spu_mamul_iminuslenminus1_sel = spu_mamul_wr_miminuslenminus1 | spu_maaeqb_iminuslenminus1_sel;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// request to mul unit when asserted
/*
wire iloop_or_req_d;
wire iloop_or_req = (cur_iloopb_state | cur_nprime_state | cur_iloopn_state)&
~mul_spu_ack;
dff_s #(1) iloop_dly_req_ff (
.din(iloop_or_req) ,
.q(iloop_or_req_d),
.clk (rclk), .se(se), .si(), .so());
assign spu_mul_req_vld = (cur_jloopb_state | cur_jloopn_state | iloop_or_req_d) ;
*/
wire mamul_mul_req_vld_pre = nxt_jloopb_state | nxt_jloopn_state | nxt_iloopb_state |
nxt_nprime_state | nxt_iloopn_state ;
dffr_s #(1) mamul_mul_req_vld_ff (
.din(mamul_mul_req_vld_pre) ,
.q(mamul_mul_req_vld),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
/*
wire mamul_mul_req_vld = cur_jloopb_state | cur_jloopn_state | cur_iloopb_state |
cur_nprime_state | cur_iloopn_state ;
*/
assign spu_mul_req_vld = mamul_mul_req_vld | spu_maaeqb_mul_req_vld;
// ---------------------------------------------------------------
assign spu_mul_areg_shf = cur_accumshft_state | spu_maaeqb_mul_areg_shf;
// ---------------------------------------------------------------
/*
wire oprnd2_sel = mamul_a_rd_oprnd_sel | mamul_ax_rd_oprnd_sel |
mamul_m_rd_oprnd_sel | mamul_me_rd_oprnd_sel) &
*/
wire oprnd2_sel = nxt_jloopa_state | nxt_iloopa_state | nxt_jloopm_state ;
wire oprnd2_sel_q;
dff_s #(1) oprnd2_wen_ff (
.din(oprnd2_sel) ,
.q(oprnd2_sel_q),
.clk (rclk), .se(se), .si(), .so());
assign spu_mamul_oprnd2_wen = oprnd2_sel_q | mamul_m_wr_oprnd2_wen | mamul_me_wr_oprnd2_wen |
spu_mared_oprnd2_wen |
spu_maaeqb_oprnd2_wen;
assign spu_mamul_oprnd2_bypass = mamul_m_wr_oprnd2_wen | mamul_me_wr_oprnd2_wen |
spu_maaeqb_oprnd2_bypass;
//assign spu_mamul_oprnd1_sel = cur_nprime_state | spu_maaeqb_oprnd1_sel; // only select nprime if set
// ---------------------------------------------------------------
assign spu_mul_acc = (mamul_mul_req_vld & ~cur_nprime_state) | spu_maaeqb_mul_acc;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
wire select_mamul = ~cur_idle_state;
wire spu_mamul_memrd4op1 = spu_mamul_rd_biminusj | spu_mamul_rd_b0 | spu_mamul_rd_n0 |
spu_mamul_rd_niminusj;
wire spu_mamul_memrd4op1_q;
dff_s #(1) spu_mamul_memrd4op1_ff (
.din(spu_mamul_memrd4op1) ,
.q(spu_mamul_memrd4op1_q),
.clk (rclk), .se(se), .si(), .so());
wire [1:0] spu_mamul_oprnd1_mxsel;
assign spu_mamul_oprnd1_mxsel[0] = (select_mamul & (~cur_nprime_state & ~spu_mamul_memrd4op1_q)) |
(~select_mamul & spu_maaeqb_oprnd1_mxsel[0]) ;
assign spu_mamul_oprnd1_mxsel[1] = (select_mamul & (~cur_nprime_state & spu_mamul_memrd4op1_q)) |
(~select_mamul & spu_maaeqb_oprnd1_mxsel[1]);
//assign spu_mamul_oprnd1_mxsel[2] = (select_mamul & cur_nprime_state) | (~select_mamul & spu_maaeqb_oprnd1_mxsel[2]);
wire [2:0] spu_mamul_oprnd1_mxsel_ps;
assign spu_mamul_oprnd1_mxsel_ps[0] = spu_mamul_oprnd1_mxsel[0];
assign spu_mamul_oprnd1_mxsel_ps[1] = ~spu_mamul_oprnd1_mxsel[0] & spu_mamul_oprnd1_mxsel[1];
assign spu_mamul_oprnd1_mxsel_ps[2] = ~spu_mamul_oprnd1_mxsel[0] & ~spu_mamul_oprnd1_mxsel[1];
assign spu_mamul_oprnd1_mxsel_l = ~spu_mamul_oprnd1_mxsel_ps;
assign spu_mamul_oprnd1_wen = spu_mamul_memrd4op1_q | spu_maaeqb_oprnd1_wen;
endmodule |
module cpu (
input wire clk_in, // 100MHz system clock
input wire rst_in, // reset signal
input wire ready_in, // ready signal
// Interrupt lines.
input wire nnmi_in, // /nmi interrupt signal (active low)
input wire nres_in, // /res interrupt signal (console reset, active low)
input wire nirq_in, // /irq intterupt signal (active low)
// Memory bus.
input wire [ 7:0] d_in, // data input bus
output wire [ 7:0] d_out, // data output bus
output wire [15:0] a_out, // address bus
output reg r_nw_out, // R/!W signal
// Debug support.
input wire [ 3:0] dbgreg_sel_in, // dbg reg select
input wire [ 7:0] dbgreg_in, // dbg reg write input
input wire dbgreg_wr_in, // dbg reg rd/wr select
output reg [ 7:0] dbgreg_out, // dbg reg read output
output reg brk_out // debug break signal
);
// dbgreg_sel defines. Selects register for read/write through the debugger block.
`define REGSEL_PCL 0
`define REGSEL_PCH 1
`define REGSEL_AC 2
`define REGSEL_X 3
`define REGSEL_Y 4
`define REGSEL_P 5
`define REGSEL_S 6
// Opcodes.
localparam [7:0] ADC_ABS = 8'h6D, ADC_ABSX = 8'h7D, ADC_ABSY = 8'h79, ADC_IMM = 8'h69,
ADC_INDX = 8'h61, ADC_INDY = 8'h71, ADC_ZP = 8'h65,
ADC_ZPX = 8'h75,
AND_ABS = 8'h2D, AND_ABSX = 8'h3D, AND_ABSY = 8'h39, AND_IMM = 8'h29,
AND_INDX = 8'h21, AND_INDY = 8'h31, AND_ZP = 8'h25,
AND_ZPX = 8'h35,
ASL_ABS = 8'h0E, ASL_ABSX = 8'h1E, ASL_ACC = 8'h0A, ASL_ZP = 8'h06,
ASL_ZPX = 8'h16,
BCC = 8'h90,
BCS = 8'hB0,
BEQ = 8'hF0,
BIT_ABS = 8'h2C, BIT_ZP = 8'h24,
BMI = 8'h30,
BNE = 8'hD0,
BPL = 8'h10,
BRK = 8'h00,
BVC = 8'h50,
BVS = 8'h70,
CLC = 8'h18,
CLD = 8'hD8,
CLI = 8'h58,
CLV = 8'hB8,
CMP_ABS = 8'hCD, CMP_ABSX = 8'hDD, CMP_ABSY = 8'hD9, CMP_IMM = 8'hC9,
CMP_INDX = 8'hC1, CMP_INDY = 8'hD1, CMP_ZP = 8'hC5,
CMP_ZPX = 8'hD5,
CPX_ABS = 8'hEC, CPX_IMM = 8'hE0, CPX_ZP = 8'hE4,
CPY_ABS = 8'hCC, CPY_IMM = 8'hC0, CPY_ZP = 8'hC4,
DEC_ABS = 8'hCE, DEC_ABSX = 8'hDE, DEC_ZP = 8'hC6, DEC_ZPX = 8'hD6,
DEX = 8'hCA,
DEY = 8'h88,
EOR_ABS = 8'h4D, EOR_ABSX = 8'h5D, EOR_ABSY = 8'h59, EOR_IMM = 8'h49,
EOR_INDX = 8'h41, EOR_INDY = 8'h51, EOR_ZP = 8'h45,
EOR_ZPX = 8'h55,
HLT = 8'h02,
INC_ABS = 8'hEE, INC_ABSX = 8'hFE, INC_ZP = 8'hE6, INC_ZPX = 8'hF6,
INX = 8'hE8,
INY = 8'hC8,
JMP_ABS = 8'h4C, JMP_IND = 8'h6C,
JSR = 8'h20,
LDA_ABS = 8'hAD, LDA_ABSX = 8'hBD, LDA_ABSY = 8'hB9, LDA_IMM = 8'hA9,
LDA_INDX = 8'hA1, LDA_INDY = 8'hB1, LDA_ZP = 8'hA5,
LDA_ZPX = 8'hB5,
LDX_ABS = 8'hAE, LDX_ABSY = 8'hBE, LDX_IMM = 8'hA2, LDX_ZP = 8'hA6,
LDX_ZPY = 8'hB6,
LDY_ABS = 8'hAC, LDY_ABSX = 8'hBC, LDY_IMM = 8'hA0, LDY_ZP = 8'hA4,
LDY_ZPX = 8'hB4,
LSR_ABS = 8'h4E, LSR_ABSX = 8'h5E, LSR_ACC = 8'h4A, LSR_ZP = 8'h46,
LSR_ZPX = 8'h56,
NOP = 8'hEA,
ORA_ABS = 8'h0D, ORA_ABSX = 8'h1D, ORA_ABSY = 8'h19, ORA_IMM = 8'h09,
ORA_INDX = 8'h01, ORA_INDY = 8'h11, ORA_ZP = 8'h05,
ORA_ZPX = 8'h15,
PHA = 8'h48,
PHP = 8'h08,
PLA = 8'h68,
PLP = 8'h28,
ROL_ABS = 8'h2E, ROL_ABSX = 8'h3E, ROL_ACC = 8'h2A, ROL_ZP = 8'h26,
ROL_ZPX = 8'h36,
ROR_ABS = 8'h6E, ROR_ABSX = 8'h7E, ROR_ACC = 8'h6A, ROR_ZP = 8'h66,
ROR_ZPX = 8'h76,
RTI = 8'h40,
RTS = 8'h60,
SAX_ABS = 8'h8F, SAX_INDX = 8'h83, SAX_ZP = 8'h87, SAX_ZPY = 8'h97,
SBC_ABS = 8'hED, SBC_ABSX = 8'hFD, SBC_ABSY = 8'hF9, SBC_IMM = 8'hE9,
SBC_INDX = 8'hE1, SBC_INDY = 8'hF1, SBC_ZP = 8'hE5,
SBC_ZPX = 8'hF5,
SEC = 8'h38,
SED = 8'hF8,
SEI = 8'h78,
STA_ABS = 8'h8D, STA_ABSX = 8'h9D, STA_ABSY = 8'h99, STA_INDX = 8'h81,
STA_INDY = 8'h91, STA_ZP = 8'h85, STA_ZPX = 8'h95,
STX_ABS = 8'h8E, STX_ZP = 8'h86, STX_ZPY = 8'h96,
STY_ABS = 8'h8C, STY_ZP = 8'h84, STY_ZPX = 8'h94,
TAX = 8'hAA,
TAY = 8'hA8,
TSX = 8'hBA,
TXA = 8'h8A,
TXS = 8'h9A,
TYA = 8'h98;
// Macro to check if a value is a valid opcode.
`define IS_VALID_OPCODE(op) \
(((op) == ADC_ABS ) || ((op) == ADC_ABSX) || ((op) == ADC_ABSY) || ((op) == ADC_IMM ) || \
((op) == ADC_INDX) || ((op) == ADC_INDY) || ((op) == ADC_ZP ) || ((op) == ADC_ZPX ) || \
((op) == AND_ABS ) || ((op) == AND_ABSX) || ((op) == AND_ABSY) || ((op) == AND_IMM ) || \
((op) == AND_INDX) || ((op) == AND_INDY) || ((op) == AND_ZP ) || ((op) == AND_ZPX ) || \
((op) == ASL_ABS ) || ((op) == ASL_ABSX) || ((op) == ASL_ACC ) || ((op) == ASL_ZP ) || \
((op) == ASL_ZPX ) || ((op) == BCC ) || ((op) == BCS ) || ((op) == BEQ ) || \
((op) == BIT_ABS ) || ((op) == BIT_ZP ) || ((op) == BMI ) || ((op) == BNE ) || \
((op) == BPL ) || ((op) == BRK ) || ((op) == BVC ) || ((op) == BVS ) || \
((op) == CLC ) || ((op) == CLD ) || ((op) == CLI ) || ((op) == CLV ) || \
((op) == CMP_ABS ) || ((op) == CMP_ABSX) || ((op) == CMP_ABSY) || ((op) == CMP_IMM ) || \
((op) == CMP_INDX) || ((op) == CMP_INDY) || ((op) == CMP_ZP ) || ((op) == CMP_ZPX ) || \
((op) == CPX_ABS ) || ((op) == CPX_IMM ) || ((op) == CPX_ZP ) || ((op) == CPY_ABS ) || \
((op) == CPY_IMM ) || ((op) == CPY_ZP ) || ((op) == DEC_ABS ) || ((op) == DEC_ABSX) || \
((op) == DEC_ZP ) || ((op) == DEC_ZPX ) || ((op) == DEX ) || ((op) == DEY ) || \
((op) == EOR_ABS ) || ((op) == EOR_ABSX) || ((op) == EOR_ABSY) || ((op) == EOR_IMM ) || \
((op) == EOR_INDX) || ((op) == EOR_INDY) || ((op) == EOR_ZP ) || ((op) == EOR_ZPX ) || \
((op) == HLT ) || ((op) == INC_ABS ) || ((op) == INC_ABSX) || ((op) == INC_ZP ) || \
((op) == INC_ZPX ) || ((op) == INX ) || ((op) == INY ) || ((op) == JMP_ABS ) || \
((op) == JMP_IND ) || ((op) == JSR ) || ((op) == LDA_ABS ) || ((op) == LDA_ABSX) || \
((op) == LDA_ABSY) || ((op) == LDA_IMM ) || ((op) == LDA_INDX) || ((op) == LDA_INDY) || \
((op) == LDA_ZP ) || ((op) == LDA_ZPX ) || ((op) == LDX_ABS ) || ((op) == LDX_ABSY) || \
((op) == LDX_IMM ) || ((op) == LDX_ZP ) || ((op) == LDX_ZPY ) || ((op) == LDY_ABS ) || \
((op) == LDY_ABSX) || ((op) == LDY_IMM ) || ((op) == LDY_ZP ) || ((op) == LDY_ZPX ) || \
((op) == LSR_ABS ) || ((op) == LSR_ABSX) || ((op) == LSR_ACC ) || ((op) == LSR_ZP ) || \
((op) == LSR_ZPX ) || ((op) == NOP ) || ((op) == ORA_ABS ) || ((op) == ORA_ABSX) || \
((op) == ORA_ABSY) || ((op) == ORA_IMM ) || ((op) == ORA_INDX) || ((op) == ORA_INDY) || \
((op) == ORA_ZP ) || ((op) == ORA_ZPX ) || ((op) == PHA ) || ((op) == PHP ) || \
((op) == PLA ) || ((op) == PLP ) || ((op) == ROL_ABS ) || ((op) == ROL_ABSX) || \
((op) == ROL_ACC ) || ((op) == ROL_ZP ) || ((op) == ROL_ZPX ) || ((op) == ROR_ABS ) || \
((op) == ROR_ABSX) || ((op) == ROR_ACC ) || ((op) == ROR_ZP ) || ((op) == ROR_ZPX ) || \
((op) == RTI ) || ((op) == RTS ) || ((op) == SAX_ABS ) || ((op) == SAX_INDX) || \
((op) == SAX_ZP ) || ((op) == SAX_ZPY ) || ((op) == SBC_ABS ) || ((op) == SBC_ABSX) || \
((op) == SBC_ABSY) || ((op) == SBC_IMM ) || ((op) == SBC_INDX) || ((op) == SBC_INDY) || \
((op) == SBC_ZP ) || ((op) == SBC_ZPX ) || ((op) == SEC ) || ((op) == SED ) || \
((op) == SEI ) || ((op) == STA_ABS ) || ((op) == STA_ABSX) || ((op) == STA_ABSY) || \
((op) == STA_INDX) || ((op) == STA_INDY) || ((op) == STA_ZP ) || ((op) == STA_ZPX ) || \
((op) == STX_ABS ) || ((op) == STX_ZP ) || ((op) == STX_ZPY ) || ((op) == STY_ABS ) || \
((op) == STY_ZP ) || ((op) == STY_ZPX ) || ((op) == TAX ) || ((op) == TAY ) || \
((op) == TSX ) || ((op) == TXA ) || ((op) == TXS ) || ((op) == TYA ))
// Timing generation cycle states.
localparam [2:0] T0 = 3'h0,
T1 = 3'h1,
T2 = 3'h2,
T3 = 3'h3,
T4 = 3'h4,
T5 = 3'h5,
T6 = 3'h6;
// Interrupt types.
localparam [1:0] INTERRUPT_RST = 2'h0,
INTERRUPT_NMI = 2'h1,
INTERRUPT_IRQ = 2'h2,
INTERRUPT_BRK = 2'h3;
// User registers.
reg [7:0] q_ac; // accumulator register
wire [7:0] d_ac;
reg [7:0] q_x; // x index register
wire [7:0] d_x;
reg [7:0] q_y; // y index register
wire [7:0] d_y;
// Processor status register.
wire [7:0] p; // full processor status reg, grouped from the following FFs
reg q_c; // carry flag
wire d_c;
reg q_d; // decimal mode flag
wire d_d;
reg q_i; // interrupt disable flag
wire d_i;
reg q_n; // negative flag
wire d_n;
reg q_v; // overflow flag
wire d_v;
reg q_z; // zero flag
wire d_z;
// Internal registers.
reg [7:0] q_abh; // address bus high register
wire [7:0] d_abh;
reg [7:0] q_abl; // address bus low register
wire [7:0] d_abl;
reg q_acr; // internal carry latch
reg [7:0] q_add; // adder hold register
reg [7:0] d_add;
reg [7:0] q_ai; // alu input register a
wire [7:0] d_ai;
reg [7:0] q_bi; // alu input register b
wire [7:0] d_bi;
reg [7:0] q_dl; // input data latch
wire [7:0] d_dl;
reg [7:0] q_dor; // data output register
wire [7:0] d_dor;
reg [7:0] q_ir; // instruction register
reg [7:0] d_ir;
reg [7:0] q_pch; // program counter high register
wire [7:0] d_pch;
reg [7:0] q_pcl; // program counter low register
wire [7:0] d_pcl;
reg [7:0] q_pchs; // program counter high select register
wire [7:0] d_pchs;
reg [7:0] q_pcls; // program counter low select register
wire [7:0] d_pcls;
reg [7:0] q_pd; // pre-decode register
wire [7:0] d_pd;
reg [7:0] q_s; // stack pointer register
wire [7:0] d_s;
reg [2:0] q_t; // timing cycle register
reg [2:0] d_t;
// Internal buses.
wire [7:0] adl; // ADL bus
wire [7:0] adh_in, // ADH bus
adh_out;
wire [7:0] db_in, // DB bus
db_out;
wire [7:0] sb_in, // SB bus
sb_out;
//
// Internal control signals. These names are all taken directly from the original 6502 block
// diagram.
//
wire zero_adl0;
wire zero_adl1;
wire zero_adl2;
// ADL bus drive enables.
wire add_adl; // output adder hold register to adl bus
wire dl_adl; // output dl reg to adl bus
wire pcl_adl; // output pcl reg to adl bus
wire s_adl; // output s reg to adl bus
// ADH bus drive enables.
wire dl_adh; // output dl reg to adh bus
wire pch_adh; // output pch reg to adh bus
wire zero_adh0; // output 0 to bit 0 of adh bus
wire zero_adh17; // output 0 to bits 1-7 of adh bus
// DB bus drive enables.
wire ac_db; // output ac reg to db bus
wire dl_db; // output dl reg to db bus
wire p_db; // output p reg to db bus
wire pch_db; // output pch reg to db bus
wire pcl_db; // output pcl reg to db bus
// SB bus drive enables.
wire ac_sb; // output ac reg to sb bus
wire add_sb; // output add reg to sb bus
wire x_sb; // output x reg to sb bus
wire y_sb; // output y reg to sb bus
wire s_sb; // output s reg to sb bus
// Pass MOSFET controls.
wire sb_adh; // controls sb/adh pass mosfet
wire sb_db; // controls sb/db pass mosfet
// Register LOAD controls.
wire adh_abh; // latch adh bus value in abh reg
wire adl_abl; // latch adl bus value in abl reg
wire sb_ac; // latch sb bus value in ac reg
wire adl_add; // latch adl bus value in bi reg
wire db_add; // latch db bus value in bi reg
wire invdb_add; // latch ~db value in bi reg
wire sb_add; // latch sb bus value in ai reg
wire zero_add; // latch 0 into ai reg
wire adh_pch; // latch adh bus value in pch reg
wire adl_pcl; // latch adl bus value in pcl reg
wire sb_s; // latch sb bus value in s reg
wire sb_x; // latch sb bus value in x reg
wire sb_y; // latch sb bus value in y reg
// Processor status controls.
wire acr_c; // latch acr into c status reg
wire db0_c; // latch db[0] into c status reg
wire ir5_c; // latch ir[5] into c status reg
wire db3_d; // latch db[3] into d status reg
wire ir5_d; // latch ir[5] into d status reg
wire db2_i; // latch db[2] into i status reg
wire ir5_i; // latch ir[5] into i status reg
wire db7_n; // latch db[7] into n status reg
wire avr_v; // latch avr into v status reg
wire db6_v; // latch db[6] into v status reg
wire zero_v; // latch 0 into v status reg
wire db1_z; // latch db[1] into z status reg
wire dbz_z; // latch ~|db into z status reg
// Misc. controls.
wire i_pc; // increment pc
// ALU controls, signals.
wire ands; // perform bitwise and on alu
wire eors; // perform bitwise xor on alu
wire ors; // perform bitwise or on alu
wire sums; // perform addition on alu
wire srs; // perform right bitshift
wire addc; // carry in
reg acr; // carry out
reg avr; // overflow out
//
// Ready Control.
//
wire rdy; // internal, modified ready signal.
reg q_ready; // latch external ready signal to delay 1 clk so top-level addr muxing can complete
always @(posedge clk_in)
begin
if (rst_in)
q_ready <= 1'b0;
else
q_ready <= ready_in;
end
assign rdy = ready_in && q_ready;
//
// Clock phase generation logic.
//
reg [5:0] q_clk_phase;
wire [5:0] d_clk_phase;
always @(posedge clk_in)
begin
if (rst_in)
q_clk_phase <= 6'h01;
else if (rdy)
q_clk_phase <= d_clk_phase;
// If the debugger writes a PC register, this is a partial reset: the cycle is set to
// T0, and the clock phase should be set to the beginning of the 4 clock cycle.
else if (dbgreg_wr_in && ((dbgreg_sel_in == `REGSEL_PCH) || (dbgreg_sel_in == `REGSEL_PCL)))
q_clk_phase <= 6'h01;
end
assign d_clk_phase = (q_clk_phase == 6'h37) ? 6'h00 : q_clk_phase + 6'h01;
//
// Interrupt and Reset Control.
//
reg [1:0] q_irq_sel, d_irq_sel; // interrupt selected for service
reg q_rst; // rst interrupt needs to be serviced
wire d_rst;
reg q_nres; // latch last nres input signal for falling edge detection
reg q_nmi; // nmi interrupt needs to be serviced
wire d_nmi;
reg q_nnmi; // latch last nnmi input signal for falling edge detection
reg clear_rst; // clear rst interrupt
reg clear_nmi; // clear nmi interrupt
reg force_noinc_pc; // override stage-0 PC increment
always @(posedge clk_in)
begin
if (rst_in)
begin
q_irq_sel <= INTERRUPT_RST;
q_rst <= 1'b0;
q_nres <= 1'b1;
q_nmi <= 1'b0;
q_nnmi <= 1'b1;
end
else if (q_clk_phase == 6'h00)
begin
q_irq_sel <= d_irq_sel;
q_rst <= d_rst;
q_nres <= nres_in;
q_nmi <= d_nmi;
q_nnmi <= nnmi_in;
end
end
assign d_rst = (clear_rst) ? 1'b0 :
(!nres_in && q_nres) ? 1'b1 :
q_rst;
assign d_nmi = (clear_nmi) ? 1'b0 :
(!nnmi_in && q_nnmi) ? 1'b1 :
q_nmi;
//
// Update phase-1 clocked registers.
//
always @(posedge clk_in)
begin
if (rst_in)
begin
q_ac <= 8'h00;
q_x <= 8'h00;
q_y <= 8'h00;
q_c <= 1'b0;
q_d <= 1'b0;
q_i <= 1'b0;
q_n <= 1'b0;
q_v <= 1'b0;
q_z <= 1'b0;
q_abh <= 8'h80;
q_abl <= 8'h00;
q_acr <= 1'b0;
q_ai <= 8'h00;
q_bi <= 8'h00;
q_dor <= 8'h00;
q_ir <= NOP;
q_pchs <= 8'h80;
q_pcls <= 8'h00;
q_s <= 8'hFF;
q_t <= T1;
end
else if (rdy && (q_clk_phase == 6'h00))
begin
q_ac <= d_ac;
q_x <= d_x;
q_y <= d_y;
q_c <= d_c;
q_d <= d_d;
q_i <= d_i;
q_n <= d_n;
q_v <= d_v;
q_z <= d_z;
q_abh <= d_abh;
q_abl <= d_abl;
q_acr <= acr;
q_ai <= d_ai;
q_bi <= d_bi;
q_dor <= d_dor;
q_ir <= d_ir;
q_pchs <= d_pchs;
q_pcls <= d_pcls;
q_s <= d_s;
q_t <= d_t;
end
else if (!rdy)
begin
// Update registers based on debug register write packets.
if (dbgreg_wr_in)
begin
q_ac <= (dbgreg_sel_in == `REGSEL_AC) ? dbgreg_in : q_ac;
q_x <= (dbgreg_sel_in == `REGSEL_X) ? dbgreg_in : q_x;
q_y <= (dbgreg_sel_in == `REGSEL_Y) ? dbgreg_in : q_y;
q_c <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[0] : q_c;
q_d <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[3] : q_d;
q_i <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[2] : q_i;
q_n <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[7] : q_n;
q_v <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[6] : q_v;
q_z <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[1] : q_z;
// Treat the debugger writing PC registers as a partial reset. Set the cycle to T0,
// and setup the address bus so the first opcode fill be fetched as soon as rdy is
// asserted again.
q_pchs <= (dbgreg_sel_in == `REGSEL_PCH) ? dbgreg_in : q_pchs;
q_pcls <= (dbgreg_sel_in == `REGSEL_PCL) ? dbgreg_in : q_pcls;
q_abh <= (dbgreg_sel_in == `REGSEL_PCH) ? dbgreg_in : q_abh;
q_abl <= (dbgreg_sel_in == `REGSEL_PCL) ? dbgreg_in : q_abl;
q_t <= ((dbgreg_sel_in == `REGSEL_PCH) || (dbgreg_sel_in == `REGSEL_PCL)) ? T0 : q_t;
end
end
end
//
// Update phase-2 clocked registers.
//
always @(posedge clk_in)
begin
if (rst_in)
begin
q_pcl <= 8'h00;
q_pch <= 8'h80;
q_dl <= 8'h00;
q_pd <= 8'h00;
q_add <= 8'h00;
end
else if (rdy && (q_clk_phase == 6'h1C))
begin
q_pcl <= d_pcl;
q_pch <= d_pch;
q_dl <= d_dl;
q_pd <= d_pd;
q_add <= d_add;
end
else if (!rdy && dbgreg_wr_in)
begin
// Update registers based on debug register write packets.
q_pcl <= (dbgreg_sel_in == `REGSEL_PCL) ? dbgreg_in : q_pcl;
q_pch <= (dbgreg_sel_in == `REGSEL_PCH) ? dbgreg_in : q_pch;
end
end
//
// Timing Generation Logic
//
always @*
begin
d_t = T0;
d_irq_sel = q_irq_sel;
force_noinc_pc = 1'b0;
case (q_t)
T0:
d_t = T1;
T1:
begin
// These instructions are in their last cycle but do not prefetch.
if ((q_ir == CLC) || (q_ir == CLD) || (q_ir == CLI) || (q_ir == CLV) ||
(q_ir == HLT) || (q_ir == LDA_IMM) || (q_ir == LDX_IMM) || (q_ir == LDY_IMM) ||
(q_ir == NOP) || (q_ir == SEC) || (q_ir == SED) || (q_ir == SEI) ||
(q_ir == TAX) || (q_ir == TAY) || (q_ir == TSX) || (q_ir == TXA) ||
(q_ir == TXS) || (q_ir == TYA))
begin
d_t = T0;
end
// Check for not-taken branches. These instructions must setup the not-taken PC during
// T1, and we can move to T0 of the next instruction.
else if (((q_ir == BCC) && q_c) || ((q_ir == BCS) && !q_c) ||
((q_ir == BPL) && q_n) || ((q_ir == BMI) && !q_n) ||
((q_ir == BVC) && q_v) || ((q_ir == BVS) && !q_v) ||
((q_ir == BNE) && q_z) || ((q_ir == BEQ) && !q_z))
begin
d_t = T0;
end
else
begin
d_t = T2;
end
end
T2:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_IMM) || (q_ir == AND_IMM) || (q_ir == ASL_ACC) || (q_ir == CMP_IMM) ||
(q_ir == CPX_IMM) || (q_ir == CPY_IMM) || (q_ir == DEX) || (q_ir == DEY) ||
(q_ir == EOR_IMM) || (q_ir == INX) || (q_ir == INY) || (q_ir == LSR_ACC) ||
(q_ir == ORA_IMM) || (q_ir == ROL_ACC) || (q_ir == ROR_ACC) || (q_ir == SBC_IMM))
begin
d_t = T1;
end
// These instructions are in their last cycle but do not prefetch.
else if ((q_ir == JMP_ABS) || (q_ir == LDA_ZP) || (q_ir == LDX_ZP) || (q_ir == LDY_ZP) ||
(q_ir == SAX_ZP) || (q_ir == STA_ZP) || (q_ir == STX_ZP) || (q_ir == STY_ZP))
begin
d_t = T0;
end
// For ops using relative absolute addressing modes, we can skip stage 3 if the result
// doesn't cross a page boundary (i.e., don't need to add 1 to the high byte).
else if (!acr && ((q_ir == ADC_ABSX) || (q_ir == ADC_ABSY) || (q_ir == AND_ABSX) ||
(q_ir == AND_ABSY) || (q_ir == CMP_ABSX) || (q_ir == CMP_ABSY) ||
(q_ir == EOR_ABSX) || (q_ir == EOR_ABSY) || (q_ir == LDA_ABSX) ||
(q_ir == LDA_ABSY) || (q_ir == ORA_ABSX) || (q_ir == ORA_ABSY) ||
(q_ir == SBC_ABSX) || (q_ir == SBC_ABSY)))
begin
d_t = T4;
end
// For relative addressing ops (branches), we can skip stage 3 if the new PC doesn't
// cross a page boundary (forward or backward).
else if ((acr == q_ai[7]) && ((q_ir == BCC) || (q_ir == BCS) || (q_ir == BEQ) ||
(q_ir == BMI) || (q_ir == BNE) || (q_ir == BPL) ||
(q_ir == BVC) || (q_ir == BVS)))
begin
d_t = T0;
end
else
begin
d_t = T3;
end
end
T3:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_ZP) || (q_ir == AND_ZP) || (q_ir == BIT_ZP) || (q_ir == CMP_ZP) ||
(q_ir == CPX_ZP) || (q_ir == CPY_ZP) || (q_ir == EOR_ZP) || (q_ir == ORA_ZP) ||
(q_ir == PHA) || (q_ir == PHP) || (q_ir == SBC_ZP))
begin
d_t = T1;
end
// These instructions are in their last cycle but do not prefetch.
else if ((q_ir == BCC) || (q_ir == BCS) || (q_ir == BEQ) ||
(q_ir == BMI) || (q_ir == BNE) || (q_ir == BPL) ||
(q_ir == BVC) || (q_ir == BVS) || (q_ir == LDA_ABS) ||
(q_ir == LDA_ZPX) || (q_ir == LDX_ABS) || (q_ir == LDX_ZPY) ||
(q_ir == LDY_ABS) || (q_ir == LDY_ZPX) || (q_ir == PLA) ||
(q_ir == PLP) || (q_ir == SAX_ABS) || (q_ir == SAX_ZPY) ||
(q_ir == STA_ABS) || (q_ir == STA_ZPX) || (q_ir == STX_ABS) ||
(q_ir == STX_ZPY) || (q_ir == STY_ABS) || (q_ir == STY_ZPX))
begin
d_t = T0;
end
// For loads using (indirect),Y addressing modes, we can skip stage 4 if the result
// doesn't cross a page boundary (i.e., don't need to add 1 to the high byte).
else if (!acr && ((q_ir == ADC_INDY) || (q_ir == AND_INDY) || (q_ir == CMP_INDY) ||
(q_ir == EOR_INDY) || (q_ir == LDA_INDY) ||
(q_ir == ORA_INDY) || (q_ir == SBC_INDY)))
begin
d_t = T5;
end
else
begin
d_t = T4;
end
end
T4:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_ABS) || (q_ir == ADC_ZPX) || (q_ir == AND_ABS) || (q_ir == AND_ZPX) ||
(q_ir == BIT_ABS) || (q_ir == CMP_ABS) || (q_ir == CMP_ZPX) || (q_ir == CPX_ABS) ||
(q_ir == CPY_ABS) || (q_ir == EOR_ABS) || (q_ir == EOR_ZPX) || (q_ir == ORA_ABS) ||
(q_ir == ORA_ZPX) || (q_ir == SBC_ABS) || (q_ir == SBC_ZPX))
begin
d_t = T1;
end
// These instructions are in their last cycle but do not prefetch.
else if ((q_ir == ASL_ZP) || (q_ir == DEC_ZP) || (q_ir == INC_ZP) ||
(q_ir == JMP_IND) || (q_ir == LDA_ABSX) || (q_ir == LDA_ABSY) ||
(q_ir == LDX_ABSY) || (q_ir == LDY_ABSX) || (q_ir == LSR_ZP) ||
(q_ir == ROL_ZP) || (q_ir == ROR_ZP) || (q_ir == STA_ABSX) ||
(q_ir == STA_ABSY))
begin
d_t = T0;
end
else
begin
d_t = T5;
end
end
T5:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_ABSX) || (q_ir == ADC_ABSY) || (q_ir == AND_ABSX) ||
(q_ir == AND_ABSY) || (q_ir == CMP_ABSX) || (q_ir == CMP_ABSY) ||
(q_ir == EOR_ABSX) || (q_ir == EOR_ABSY) || (q_ir == ORA_ABSX) ||
(q_ir == ORA_ABSY) || (q_ir == SBC_ABSX) || (q_ir == SBC_ABSY))
begin
d_t = T1;
end
// These instructions are in their last cycle but do not prefetch.
else if ((q_ir == ASL_ABS) || (q_ir == ASL_ZPX) || (q_ir == DEC_ABS) ||
(q_ir == DEC_ZPX) || (q_ir == INC_ABS) || (q_ir == INC_ZPX) ||
(q_ir == JSR) || (q_ir == LDA_INDX) || (q_ir == LDA_INDY) ||
(q_ir == LSR_ABS) || (q_ir == LSR_ZPX) || (q_ir == ROL_ABS) ||
(q_ir == ROL_ZPX) || (q_ir == ROR_ABS) || (q_ir == ROR_ZPX) ||
(q_ir == RTI) || (q_ir == RTS) || (q_ir == SAX_INDX) ||
(q_ir == STA_INDX) || (q_ir == STA_INDY))
begin
d_t = T0;
end
else
begin
d_t = T6;
end
end
T6:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_INDX) || (q_ir == ADC_INDY) || (q_ir == AND_INDX) ||
(q_ir == AND_INDY) || (q_ir == CMP_INDX) || (q_ir == CMP_INDY) ||
(q_ir == EOR_INDX) || (q_ir == EOR_INDY) || (q_ir == ORA_INDX) ||
(q_ir == ORA_INDY) || (q_ir == SBC_INDX) || (q_ir == SBC_INDY))
begin
d_t = T1;
end
else
begin
d_t = T0;
end
end
endcase
// Update IR register on cycle 1, otherwise retain current IR.
if (d_t == T1)
begin
if (q_rst || q_nmi || !nirq_in)
begin
d_ir = BRK;
force_noinc_pc = 1'b1;
if (q_rst)
d_irq_sel = INTERRUPT_RST;
else if (q_nmi)
d_irq_sel = INTERRUPT_NMI;
else
d_irq_sel = INTERRUPT_IRQ;
end
else
begin
d_ir = q_pd;
d_irq_sel = INTERRUPT_BRK;
end
end
else
begin
d_ir = q_ir;
end
end
//
// Decode ROM output signals. Corresponds to 130 bit bus coming out of the Decode ROM in the
// block diagram, although the details of implementation will differ.
//
// PC and program stream controls.
reg load_prg_byte; // put PC on addr bus and increment PC (adh, adl)
reg load_prg_byte_noinc; // put PC on addr bus only (adh, adl)
reg incpc_noload; // increment PC only (-)
reg alusum_to_pch; // load pch with ai+bi (adh, sb)
reg dl_to_pch; // load pch with current data latch register (adh)
reg alusum_to_pcl; // load pcl with ai+bi (adl)
reg s_to_pcl; // load pcl with s (adl)
// Instruction-specific controls. Typically triggers the meat of a particular operation that
// occurs regardless of addressing mode.
reg adc_op; // final cycle of an adc inst (db, sb)
reg and_op; // final cycle of an and inst (db, sb)
reg asl_acc_op; // perform asl_acc inst (db, sb)
reg asl_mem_op; // perform meat of asl inst for memory addressing modes (db, sb)
reg bit_op; // final cycle of a bit inst (db, sb)
reg cmp_op; // final cycle of a cmp inst (db, sb)
reg clc_op; // clear carry bit (-)
reg cld_op; // clear decimal mode bit (-)
reg cli_op; // clear interrupt disable bit (-)
reg clv_op; // clear overflow bit (-)
reg dec_op; // perform meat of dec inst (db, sb)
reg dex_op; // final cycle of a dex inst (db, sb)
reg dey_op; // final cycle of a dey inst (db, sb)
reg eor_op; // final cycle of an eor inst (db, sb)
reg inc_op; // perform meat of inc inst (db, sb)
reg inx_op; // final cycle of an inx inst (db, sb)
reg iny_op; // final cycle of an iny inst (db, sb)
reg lda_op; // final cycle of an lda inst (db, sb)
reg ldx_op; // final cycle of an ldx inst (db, sb)
reg ldy_op; // final cycle of an ldy inst (db, sb)
reg lsr_acc_op; // perform lsr_acc inst (db, sb)
reg lsr_mem_op; // perform meat of lsr inst for memory addressing modes (db, sb)
reg ora_op; // final cycle of an ora inst (db, sb)
reg rol_acc_op; // perform rol_acc inst (db, sb)
reg rol_mem_op; // perform meat of rol inst for memory addressing modes (db, sb)
reg ror_acc_op; // perform ror_acc inst (db, sb)
reg ror_mem_op; // perform meat of ror inst for memory addressing modes (db, sb)
reg sec_op; // set carry bit (-)
reg sed_op; // set decimal mode bit (-)
reg sei_op; // set interrupt disable bit (-)
reg tax_op; // transfer ac to x (db, sb)
reg tay_op; // transfer ac to y (db, sb)
reg tsx_op; // transfer s to x (db, sb)
reg txa_op; // transfer x to z (db, sb)
reg txs_op; // transfer x to s (db, sb)
reg tya_op; // transfer y to a (db, sb)
// DOR (data output register) load controls.
reg ac_to_dor; // load current ac value into dor (db)
reg p_to_dor; // load current p value into dor (db)
reg pch_to_dor; // load current pch value into dor (db)
reg pcl_to_dor; // load current pcl value into dor (db)
reg x_to_dor; // load current x value into dor (db, sb)
reg y_to_dor; // load current y value into dor (db, sb)
// AB (address bus hold registers) load controls.
reg aluinc_to_abh; // load abh with ai+bi+1 (adh, sb)
reg alusum_to_abh; // load abh with ai+bi (adh, sb)
reg dl_to_abh; // load abh with dl (adh)
reg ff_to_abh; // load abh with 8'hff (adh)
reg one_to_abh; // load abh with 8'h01 (adh)
reg zero_to_abh; // load abh with 8'h00 (adh)
reg aluinc_to_abl; // load abl with ai+bi+1 (adl)
reg alusum_to_abl; // load abl with ai+bi (adl)
reg dl_to_abl; // load abl with dl (adl)
reg fa_to_abl; // load abl with 8'hfa (adl)
reg fb_to_abl; // load abl with 8'hfb (adl)
reg fc_to_abl; // load abl with 8'hfc (adl)
reg fd_to_abl; // load abl with 8'hfd (adl)
reg fe_to_abl; // load abl with 8'hfe (adl)
reg ff_to_abl; // load abl with 8'hff (adl)
reg s_to_abl; // load abl with s (adl)
// AI/BI (ALU input registers) load controls.
reg ac_to_ai; // load ai with ac (sb)
reg dl_to_ai; // load ai with dl (db, sb)
reg one_to_ai; // load ai with 1 (adh, sb)
reg neg1_to_ai; // load ai with -1 (sb)
reg s_to_ai; // load ai with s (sb)
reg x_to_ai; // load ai with x (sb)
reg y_to_ai; // load ai with y (sb)
reg zero_to_ai; // load ai with 0 (sb)
reg ac_to_bi; // load bi with ac (db)
reg aluinc_to_bi; // load bi with ai+bi+1 (adl)
reg alusum_to_bi; // load bi with ai+bi (adl)
reg dl_to_bi; // load bi with dl (db)
reg invdl_to_bi; // load bi with ~dl (db)
reg neg1_to_bi; // load bi with -1 (db)
reg pch_to_bi; // load bi with pch (db)
reg pcl_to_bi; // load bi with pcl (adl)
reg s_to_bi; // load bi with s (adl)
reg x_to_bi; // load bi with x (db, sb)
reg y_to_bi; // load bi with y (db, sb)
// Stack related controls.
reg aluinc_to_s; // load ai+bi+1 into s (sb)
reg alusum_to_s; // load ai+bi into s (sb)
reg dl_to_s; // load s with current data latch register (db, sb)
// Process status register controls.
reg dl_bits67_to_p; // latch bits 6 and 7 into P V and N bits (db)
reg dl_to_p; // load dl into p (db)
reg one_to_i; // used to supress irqs while processing an interrupt
// Sets all decode ROM output signals to the specified value (0 for init, X for con't care states.
`define SET_ALL_CONTROL_SIGNALS(val) \
load_prg_byte = (val); \
load_prg_byte_noinc = (val); \
incpc_noload = (val); \
alusum_to_pch = (val); \
dl_to_pch = (val); \
alusum_to_pcl = (val); \
s_to_pcl = (val); \
\
adc_op = (val); \
and_op = (val); \
asl_acc_op = (val); \
asl_mem_op = (val); \
bit_op = (val); \
cmp_op = (val); \
clc_op = (val); \
cld_op = (val); \
cli_op = (val); \
clv_op = (val); \
dec_op = (val); \
dex_op = (val); \
dey_op = (val); \
eor_op = (val); \
inc_op = (val); \
inx_op = (val); \
iny_op = (val); \
lda_op = (val); \
ldx_op = (val); \
ldy_op = (val); \
lsr_acc_op = (val); \
lsr_mem_op = (val); \
ora_op = (val); \
rol_acc_op = (val); \
rol_mem_op = (val); \
ror_acc_op = (val); \
ror_mem_op = (val); \
sec_op = (val); \
sed_op = (val); \
sei_op = (val); \
tax_op = (val); \
tay_op = (val); \
tsx_op = (val); \
txa_op = (val); \
txs_op = (val); \
tya_op = (val); \
\
ac_to_dor = (val); \
p_to_dor = (val); \
pch_to_dor = (val); \
pcl_to_dor = (val); \
x_to_dor = (val); \
y_to_dor = (val); \
\
aluinc_to_abh = (val); \
alusum_to_abh = (val); \
dl_to_abh = (val); \
ff_to_abh = (val); \
one_to_abh = (val); \
zero_to_abh = (val); \
aluinc_to_abl = (val); \
alusum_to_abl = (val); \
dl_to_abl = (val); \
fa_to_abl = (val); \
fb_to_abl = (val); \
fc_to_abl = (val); \
fd_to_abl = (val); \
fe_to_abl = (val); \
ff_to_abl = (val); \
s_to_abl = (val); \
\
ac_to_ai = (val); \
dl_to_ai = (val); \
one_to_ai = (val); \
neg1_to_ai = (val); \
s_to_ai = (val); \
x_to_ai = (val); \
y_to_ai = (val); \
zero_to_ai = (val); \
ac_to_bi = (val); \
aluinc_to_bi = (val); \
alusum_to_bi = (val); \
dl_to_bi = (val); \
invdl_to_bi = (val); \
neg1_to_bi = (val); \
pch_to_bi = (val); \
pcl_to_bi = (val); \
s_to_bi = (val); \
x_to_bi = (val); \
y_to_bi = (val); \
\
aluinc_to_s = (val); \
alusum_to_s = (val); \
dl_to_s = (val); \
\
dl_to_p = (val); \
dl_bits67_to_p = (val); \
one_to_i = (val);
//
// Decode ROM logic.
//
always @*
begin
// Default all control signals to 0.
`SET_ALL_CONTROL_SIGNALS(1'b0)
// Defaults for output signals.
r_nw_out = 1'b1;
brk_out = 1'b0;
clear_rst = 1'b0;
clear_nmi = 1'b0;
if (q_t == T0)
begin
load_prg_byte = 1'b1;
end
else if (q_t == T1)
begin
case (q_ir)
ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS,
INC_ABS, JMP_ABS, JMP_IND, LDA_ABS, LDX_ABS, LDY_ABS, LSR_ABS,
ORA_ABS, ROL_ABS, ROR_ABS, SAX_ABS, SBC_ABS,
STA_ABS, STX_ABS, STY_ABS:
begin
load_prg_byte = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ABSX, AND_ABSX, ASL_ABSX, CMP_ABSX, DEC_ABSX, EOR_ABSX, INC_ABSX,
LDA_ABSX, LDY_ABSX, LSR_ABSX, ORA_ABSX, ROL_ABSX,
ROR_ABSX, SBC_ABSX, STA_ABSX:
begin
load_prg_byte = 1'b1;
x_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ABSY, AND_ABSY, CMP_ABSY, EOR_ABSY, LDA_ABSY, LDX_ABSY,
ORA_ABSY, SBC_ABSY, STA_ABSY:
begin
load_prg_byte = 1'b1;
y_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_IMM, AND_IMM, EOR_IMM, ORA_IMM:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_INDX, AND_INDX, CMP_INDX, EOR_INDX, LDA_INDX, ORA_INDX,
SAX_INDX, SBC_INDX, STA_INDX,
ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX,
EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX,
LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX, SBC_ZPX,
STA_ZPX, STY_ZPX:
begin
x_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_INDY, AND_INDY, CMP_INDY, EOR_INDY, LDA_INDY, ORA_INDY,
SBC_INDY, STA_INDY:
begin
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ZP, AND_ZP, ASL_ZP, BIT_ZP, CMP_ZP, CPX_ZP, CPY_ZP, DEC_ZP,
EOR_ZP, INC_ZP, LDA_ZP, LDX_ZP, LDY_ZP, LSR_ZP, ORA_ZP,
ROL_ZP, ROR_ZP, SBC_ZP:
begin
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC:
begin
ac_to_ai = 1'b1;
ac_to_bi = 1'b1;
end
BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS:
begin
load_prg_byte = 1'b1;
dl_to_ai = 1'b1;
pcl_to_bi = 1'b1;
end
BRK:
begin
if (q_irq_sel == INTERRUPT_BRK)
incpc_noload = 1'b1;
pch_to_dor = 1'b1;
one_to_abh = 1'b1;
s_to_abl = 1'b1;
neg1_to_ai = 1'b1;
s_to_bi = 1'b1;
end
CLC:
clc_op = 1'b1;
CLD:
cld_op = 1'b1;
CLI:
cli_op = 1'b1;
CLV:
clv_op = 1'b1;
CMP_IMM, SBC_IMM:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPX_IMM:
begin
load_prg_byte = 1'b1;
x_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPY_IMM:
begin
load_prg_byte = 1'b1;
y_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEX:
begin
x_to_ai = 1'b1;
neg1_to_bi = 1'b1;
end
DEY:
begin
y_to_ai = 1'b1;
neg1_to_bi = 1'b1;
end
HLT:
begin
// The HLT instruction asks hci to deassert the rdy signal, effectively pausing the
// cpu and allowing the debug block to inspect the internal state.
brk_out = (q_clk_phase == 6'h01) && rdy;
end
INX:
begin
zero_to_ai = 1'b1;
x_to_bi = 1'b1;
end
INY:
begin
zero_to_ai = 1'b1;
y_to_bi = 1'b1;
end
JSR:
begin
incpc_noload = 1'b1;
one_to_abh = 1'b1;
s_to_abl = 1'b1;
s_to_bi = 1'b1;
dl_to_s = 1'b1;
end
LDX_ZPY, SAX_ZPY, STX_ZPY:
begin
y_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
LDA_IMM:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LDX_IMM:
begin
load_prg_byte = 1'b1;
ldx_op = 1'b1;
end
LDY_IMM:
begin
load_prg_byte = 1'b1;
ldy_op = 1'b1;
end
PHA:
begin
ac_to_dor = 1'b1;
one_to_abh = 1'b1;
s_to_abl = 1'b1;
end
PHP:
begin
p_to_dor = 1'b1;
one_to_abh = 1'b1;
s_to_abl = 1'b1;
end
PLA, PLP, RTI, RTS:
begin
zero_to_ai = 1'b1;
s_to_bi = 1'b1;
end
SEC:
sec_op = 1'b1;
SED:
sed_op = 1'b1;
SEI:
sei_op = 1'b1;
SAX_ZP:
begin
ac_to_dor = 1'b1;
x_to_dor = 1'b1;
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
STA_ZP:
begin
ac_to_dor = 1'b1;
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
STX_ZP:
begin
x_to_dor = 1'b1;
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
STY_ZP:
begin
y_to_dor = 1'b1;
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
TAX:
tax_op = 1'b1;
TAY:
tay_op = 1'b1;
TSX:
tsx_op = 1'b1;
TXA:
txa_op = 1'b1;
TXS:
txs_op = 1'b1;
TYA:
tya_op = 1'b1;
endcase
end
else if (q_t == T2)
begin
case (q_ir)
ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS,
INC_ABS, LDA_ABS, LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS,
ROL_ABS, ROR_ABS, SBC_ABS,
JMP_IND:
begin
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
ADC_ABSX, AND_ABSX, ASL_ABSX, CMP_ABSX, DEC_ABSX, EOR_ABSX, INC_ABSX,
LDA_ABSX, LDY_ABSX, LSR_ABSX, ORA_ABSX, ROL_ABSX,
ROR_ABSX, SBC_ABSX, STA_ABSX,
ADC_ABSY, AND_ABSY, CMP_ABSY, EOR_ABSY, LDA_ABSY,
LDX_ABSY, ORA_ABSY, SBC_ABSY,
STA_ABSY:
begin
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_IMM, SBC_IMM:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
ADC_INDX, AND_INDX, CMP_INDX, EOR_INDX, LDA_INDX, ORA_INDX,
SAX_INDX, SBC_INDX, STA_INDX,
ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX,
EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX,
LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX, SBC_ZPX,
LDX_ZPY:
begin
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
ADC_INDY, AND_INDY, CMP_INDY, EOR_INDY, LDA_INDY, ORA_INDY,
SBC_INDY, STA_INDY:
begin
zero_to_abh = 1'b1;
aluinc_to_abl = 1'b1;
y_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ZP, AND_ZP, EOR_ZP, ORA_ZP:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
AND_IMM:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ACC:
begin
load_prg_byte = 1'b1;
asl_acc_op = 1'b1;
end
ASL_ZP, LSR_ZP, ROL_ZP, ROR_ZP:
begin
dl_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
LSR_ACC:
begin
load_prg_byte = 1'b1;
lsr_acc_op = 1'b1;
end
BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS:
begin
alusum_to_pcl = 1'b1;
alusum_to_abl = 1'b1;
if (q_ai[7])
neg1_to_ai = 1'b1;
else
one_to_ai = 1'b1;
pch_to_bi = 1'b1;
end
BIT_ZP:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
dl_bits67_to_p = 1'b1;
end
BRK:
begin
pcl_to_dor = 1'b1;
alusum_to_abl = 1'b1;
alusum_to_bi = 1'b1;
r_nw_out = 1'b0;
end
CMP_IMM, CPX_IMM, CPY_IMM:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
CMP_ZP, SBC_ZP:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPX_ZP:
begin
load_prg_byte = 1'b1;
x_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPY_ZP:
begin
load_prg_byte = 1'b1;
y_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEC_ZP:
begin
neg1_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
DEX:
begin
load_prg_byte = 1'b1;
dex_op = 1'b1;
end
DEY:
begin
load_prg_byte = 1'b1;
dey_op = 1'b1;
end
EOR_IMM:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
INC_ZP:
begin
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
INX:
begin
load_prg_byte = 1'b1;
inx_op = 1'b1;
end
INY:
begin
load_prg_byte = 1'b1;
iny_op = 1'b1;
end
JMP_ABS:
begin
dl_to_pch = 1'b1;
alusum_to_pcl = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
JSR:
begin
pch_to_dor = 1'b1;
neg1_to_ai = 1'b1;
end
LDA_ZP:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LDX_ZP:
begin
load_prg_byte = 1'b1;
ldx_op = 1'b1;
end
LDY_ZP:
begin
load_prg_byte = 1'b1;
ldy_op = 1'b1;
end
ORA_IMM:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
PHA, PHP:
begin
load_prg_byte_noinc = 1'b1;
s_to_ai = 1'b1;
neg1_to_bi = 1'b1;
r_nw_out = 1'b0;
end
PLA, PLP:
begin
one_to_abh = 1'b1;
aluinc_to_abl = 1'b1;
aluinc_to_s = 1'b1;
end
ROL_ACC:
begin
load_prg_byte = 1'b1;
rol_acc_op = 1'b1;
end
ROR_ACC:
begin
load_prg_byte = 1'b1;
ror_acc_op = 1'b1;
end
RTI, RTS:
begin
one_to_abh = 1'b1;
aluinc_to_abl = 1'b1;
aluinc_to_bi = 1'b1;
end
SAX_ABS:
begin
ac_to_dor = 1'b1;
x_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
SAX_ZP, STA_ZP, STX_ZP, STY_ZP:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
SAX_ZPY:
begin
ac_to_dor = 1'b1;
x_to_dor = 1'b1;
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STA_ABS:
begin
ac_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STA_ZPX:
begin
ac_to_dor = 1'b1;
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STX_ABS:
begin
x_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STX_ZPY:
begin
x_to_dor = 1'b1;
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STY_ABS:
begin
y_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STY_ZPX:
begin
y_to_dor = 1'b1;
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
endcase
end
else if (q_t == T3)
begin
case (q_ir)
ADC_ABS, AND_ABS, EOR_ABS, ORA_ABS,
ADC_ZPX, AND_ZPX, EOR_ZPX, ORA_ZPX:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ABSX, AND_ABSX, ASL_ABSX, CMP_ABSX, DEC_ABSX, EOR_ABSX, INC_ABSX,
LDA_ABSX, LDY_ABSX, LSR_ABSX, ORA_ABSX, ROL_ABSX,
ROR_ABSX, SBC_ABSX,
ADC_ABSY, AND_ABSY, CMP_ABSY, EOR_ABSY, LDA_ABSY,
LDX_ABSY, ORA_ABSY, SBC_ABSY:
begin
aluinc_to_abh = q_acr;
end
ADC_INDX, AND_INDX, CMP_INDX, EOR_INDX, LDA_INDX, ORA_INDX,
SAX_INDX, STA_INDX, SBC_INDX:
begin
zero_to_abh = 1'b1;
aluinc_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_INDY, AND_INDY, CMP_INDY, EOR_INDY, LDA_INDY, ORA_INDY,
SBC_INDY, STA_INDY:
begin
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ZP, SBC_ZP:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
AND_ZP:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ABS, LSR_ABS, ROL_ABS, ROR_ABS,
ASL_ZPX, LSR_ZPX, ROL_ZPX, ROR_ZPX:
begin
dl_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ASL_ZP:
asl_mem_op = 1'b1;
BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS:
begin
alusum_to_pch = 1'b1;
alusum_to_abh = 1'b1;
end
BIT_ABS:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
dl_bits67_to_p = 1'b1;
end
BIT_ZP:
begin
load_prg_byte = 1'b1;
bit_op = 1'b1;
end
BRK:
begin
p_to_dor = 1'b1;
alusum_to_abl = 1'b1;
alusum_to_bi = 1'b1;
r_nw_out = 1'b0;
end
CMP_ABS, SBC_ABS,
CMP_ZPX, SBC_ZPX:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CMP_ZP, CPX_ZP, CPY_ZP:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
CPX_ABS:
begin
load_prg_byte = 1'b1;
x_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPY_ABS:
begin
load_prg_byte = 1'b1;
y_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEC_ABS,
DEC_ZPX:
begin
neg1_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
DEC_ZP:
dec_op = 1'b1;
EOR_ZP:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
INC_ABS,
INC_ZPX:
begin
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
INC_ZP:
inc_op = 1'b1;
JMP_IND:
begin
aluinc_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
JSR:
begin
pcl_to_dor = 1'b1;
alusum_to_abl = 1'b1;
alusum_to_bi = 1'b1;
r_nw_out = 1'b0;
end
LDA_ABS, LDA_ZPX:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LDX_ABS, LDX_ZPY:
begin
load_prg_byte = 1'b1;
ldx_op = 1'b1;
end
LDY_ABS, LDY_ZPX:
begin
load_prg_byte = 1'b1;
ldy_op = 1'b1;
end
LSR_ZP:
lsr_mem_op = 1'b1;
ORA_ZP:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
PHA, PHP:
begin
load_prg_byte = 1'b1;
alusum_to_s = 1'b1;
end
PLA:
begin
load_prg_byte_noinc = 1'b1;
lda_op = 1'b1;
end
PLP:
begin
load_prg_byte_noinc = 1'b1;
dl_to_p = 1'b1;
end
ROL_ZP:
rol_mem_op = 1'b1;
ROR_ZP:
ror_mem_op = 1'b1;
RTI:
begin
aluinc_to_abl = 1'b1;
aluinc_to_bi = 1'b1;
dl_to_p = 1'b1;
end
RTS:
begin
aluinc_to_abl = 1'b1;
dl_to_s = 1'b1;
end
SAX_ABS, STA_ABS, STX_ABS, STY_ABS,
STA_ZPX, STY_ZPX,
SAX_ZPY, STX_ZPY:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
STA_ABSX,
STA_ABSY:
begin
ac_to_dor = 1'b1;
aluinc_to_abh = q_acr;
end
endcase
end
else if (q_t == T4)
begin
case (q_ir)
ADC_ABS, SBC_ABS,
ADC_ZPX, SBC_ZPX:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
ADC_ABSX, AND_ABSX, EOR_ABSX, ORA_ABSX,
ADC_ABSY, AND_ABSY, EOR_ABSY, ORA_ABSY:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_INDX, AND_INDX, CMP_INDX, EOR_INDX, LDA_INDX, ORA_INDX,
SBC_INDX:
begin
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
ADC_INDY, AND_INDY, CMP_INDY, EOR_INDY, LDA_INDY, ORA_INDY,
SBC_INDY:
begin
aluinc_to_abh = q_acr;
end
AND_ABS,
AND_ZPX:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ABS,
ASL_ZPX:
asl_mem_op = 1'b1;
ASL_ZP, DEC_ZP, INC_ZP, LSR_ZP, ROL_ZP, ROR_ZP,
STA_ABSX,
STA_ABSY:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
ASL_ABSX, LSR_ABSX, ROL_ABSX, ROR_ABSX:
begin
dl_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
BIT_ABS:
begin
load_prg_byte = 1'b1;
bit_op = 1'b1;
end
BRK:
begin
ff_to_abh = 1'b1;
r_nw_out = 1'b0;
one_to_i = 1'b1;
case (q_irq_sel)
INTERRUPT_RST: fc_to_abl = 1'b1;
INTERRUPT_NMI: fa_to_abl = 1'b1;
INTERRUPT_IRQ, INTERRUPT_BRK: fe_to_abl = 1'b1;
endcase
end
CMP_ABS, CPX_ABS, CPY_ABS,
CMP_ZPX:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
CMP_ABSX, SBC_ABSX,
CMP_ABSY, SBC_ABSY:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEC_ABS,
DEC_ZPX:
dec_op = 1'b1;
DEC_ABSX:
begin
neg1_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
EOR_ABS,
EOR_ZPX:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
INC_ABS,
INC_ZPX:
inc_op = 1'b1;
INC_ABSX:
begin
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
JMP_IND:
begin
dl_to_pch = 1'b1;
alusum_to_pcl = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
JSR:
begin
load_prg_byte_noinc = 1'b1;
r_nw_out = 1'b0;
end
LDA_ABSX,
LDA_ABSY:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LDX_ABSY:
begin
load_prg_byte = 1'b1;
ldx_op = 1'b1;
end
LDY_ABSX:
begin
load_prg_byte = 1'b1;
ldy_op = 1'b1;
end
LSR_ABS,
LSR_ZPX:
lsr_mem_op = 1'b1;
ORA_ABS,
ORA_ZPX:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
ROL_ABS,
ROL_ZPX:
rol_mem_op = 1'b1;
ROR_ABS,
ROR_ZPX:
ror_mem_op = 1'b1;
RTI:
begin
aluinc_to_abl = 1'b1;
dl_to_s = 1'b1;
end
RTS:
begin
dl_to_pch = 1'b1;
s_to_pcl = 1'b1;
aluinc_to_s = 1'b1;
end
SAX_INDX:
begin
ac_to_dor = 1'b1;
x_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STA_INDX:
begin
ac_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STA_INDY:
begin
ac_to_dor = 1'b1;
aluinc_to_abh = q_acr;
end
endcase
end
else if (q_t == T5)
begin
case (q_ir)
ADC_ABSX, SBC_ABSX,
ADC_ABSY, SBC_ABSY:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
ADC_INDX, AND_INDX, EOR_INDX, ORA_INDX,
ADC_INDY, AND_INDY, EOR_INDY, ORA_INDY:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
AND_ABSX,
AND_ABSY:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ABS, DEC_ABS, INC_ABS, LSR_ABS, ROL_ABS, ROR_ABS,
ASL_ZPX, DEC_ZPX, INC_ZPX, LSR_ZPX, ROL_ZPX, ROR_ZPX,
SAX_INDX, STA_INDX,
STA_INDY:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
ASL_ABSX:
asl_mem_op = 1'b1;
BRK:
begin
ff_to_abh = 1'b1;
dl_to_s = 1'b1;
case (q_irq_sel)
INTERRUPT_RST: fd_to_abl = 1'b1;
INTERRUPT_NMI: fb_to_abl = 1'b1;
INTERRUPT_IRQ, INTERRUPT_BRK: ff_to_abl = 1'b1;
endcase
end
CMP_ABSX,
CMP_ABSY:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
CMP_INDX, SBC_INDX,
CMP_INDY, SBC_INDY:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEC_ABSX:
dec_op = 1'b1;
EOR_ABSX,
EOR_ABSY:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
INC_ABSX:
inc_op = 1'b1;
JSR:
begin
dl_to_pch = 1'b1;
s_to_pcl = 1'b1;
dl_to_abh = 1'b1;
s_to_abl = 1'b1;
alusum_to_s = 1'b1;
end
LDA_INDX,
LDA_INDY:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LSR_ABSX:
lsr_mem_op = 1'b1;
ORA_ABSX,
ORA_ABSY:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
ROL_ABSX:
rol_mem_op = 1'b1;
ROR_ABSX:
ror_mem_op = 1'b1;
RTI:
begin
dl_to_pch = 1'b1;
s_to_pcl = 1'b1;
dl_to_abh = 1'b1;
s_to_abl = 1'b1;
aluinc_to_s = 1'b1;
end
RTS:
load_prg_byte = 1'b1;
endcase
end
else if (q_t == T6)
begin
case (q_ir)
ADC_INDX, SBC_INDX,
ADC_INDY, SBC_INDY:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
AND_INDX,
AND_INDY:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ABSX, DEC_ABSX, INC_ABSX, LSR_ABSX, ROL_ABSX, ROR_ABSX:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
BRK:
begin
dl_to_pch = 1'b1;
s_to_pcl = 1'b1;
dl_to_abh = 1'b1;
s_to_abl = 1'b1;
alusum_to_s = 1'b1;
case (q_irq_sel)
INTERRUPT_RST: clear_rst = 1'b1;
INTERRUPT_NMI: clear_nmi = 1'b1;
endcase
end
CMP_INDX,
CMP_INDY:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
EOR_INDX,
EOR_INDY:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
ORA_INDX,
ORA_INDY:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
endcase
end
end
//
// ALU
//
always @*
begin
acr = 1'b0;
avr = 1'b0;
if (ands)
d_add = q_ai & q_bi;
else if (eors)
d_add = q_ai ^ q_bi;
else if (ors)
d_add = q_ai | q_bi;
else if (sums)
begin
{ acr, d_add } = q_ai + q_bi + addc;
avr = ((q_ai[7] ^ q_bi[7]) ^ d_add[7]) ^ acr;
end
else if (srs)
{ d_add, acr } = { addc, q_bi };
else
d_add = q_add;
end
//
// Random Control Logic
//
assign add_adl = aluinc_to_abl | aluinc_to_bi | alusum_to_abl |
alusum_to_bi | alusum_to_pcl;
assign dl_adl = dl_to_abl;
assign pcl_adl = load_prg_byte | load_prg_byte_noinc |
pcl_to_bi;
assign s_adl = s_to_abl | s_to_bi | s_to_pcl;
assign zero_adl0 = fa_to_abl | fc_to_abl | fe_to_abl;
assign zero_adl1 = fc_to_abl | fd_to_abl;
assign zero_adl2 = fa_to_abl | fb_to_abl;
assign dl_adh = dl_to_abh | dl_to_pch;
assign pch_adh = load_prg_byte | load_prg_byte_noinc;
assign zero_adh0 = zero_to_abh;
assign zero_adh17 = one_to_abh | one_to_ai | zero_to_abh;
assign ac_db = ac_to_bi | ac_to_dor;
assign dl_db = dl_to_ai | dl_to_bi |
dl_to_p | dl_to_s | invdl_to_bi |
lda_op | ldx_op | ldy_op;
assign p_db = p_to_dor;
assign pch_db = pch_to_bi | pch_to_dor;
assign pcl_db = pcl_to_dor;
assign ac_sb = ac_to_ai | tax_op | tay_op;
assign add_sb = adc_op | aluinc_to_abh |
aluinc_to_s | alusum_to_abh | alusum_to_pch |
alusum_to_s | and_op |
asl_acc_op | asl_mem_op | bit_op |
cmp_op | dec_op | dex_op |
dey_op | eor_op | inc_op |
inx_op | iny_op | lsr_acc_op |
lsr_mem_op | ora_op | rol_acc_op |
rol_mem_op | ror_acc_op | ror_mem_op;
assign x_sb = txa_op | txs_op | x_to_ai |
x_to_bi | x_to_dor;
assign y_sb = tya_op | y_to_ai | y_to_bi |
y_to_dor;
assign s_sb = s_to_ai | tsx_op;
assign sb_adh = aluinc_to_abh | alusum_to_abh | alusum_to_pch |
one_to_ai | one_to_i;
assign sb_db = adc_op |
and_op | asl_acc_op |
asl_mem_op | bit_op | cmp_op |
dl_to_s | dec_op | dex_op |
dey_op | dl_to_ai | eor_op |
inc_op | inx_op | iny_op |
lda_op | ldx_op | ldy_op |
lsr_acc_op | lsr_mem_op | one_to_i |
ora_op | rol_acc_op | rol_mem_op |
ror_acc_op | ror_mem_op | tax_op |
tay_op | tsx_op | txa_op |
tya_op | x_to_bi | x_to_dor |
y_to_bi | y_to_dor;
assign adh_abh = aluinc_to_abh | alusum_to_abh | dl_to_abh |
ff_to_abh | load_prg_byte | load_prg_byte_noinc |
one_to_abh | zero_to_abh;
assign adl_abl = aluinc_to_abl | alusum_to_abl | dl_to_abl |
fa_to_abl | fb_to_abl | fc_to_abl |
fd_to_abl | fe_to_abl | ff_to_abl |
load_prg_byte | load_prg_byte_noinc |
s_to_abl;
assign adl_add = aluinc_to_bi | alusum_to_bi | pcl_to_bi |
s_to_bi;
assign db_add = ac_to_bi | dl_to_bi |
neg1_to_bi | pch_to_bi | x_to_bi |
y_to_bi;
assign invdb_add = invdl_to_bi;
assign sb_s = aluinc_to_s | alusum_to_s | dl_to_s |
txs_op;
assign zero_add = zero_to_ai;
assign sb_ac = adc_op | and_op |
asl_acc_op | eor_op |
lda_op | lsr_acc_op | ora_op |
rol_acc_op | ror_acc_op | txa_op |
tya_op;
assign sb_add = ac_to_ai | dl_to_ai | neg1_to_ai |
one_to_ai | s_to_ai | x_to_ai |
y_to_ai;
assign adh_pch = alusum_to_pch | dl_to_pch;
assign adl_pcl = alusum_to_pcl | s_to_pcl;
assign sb_x = dex_op | inx_op | ldx_op |
tax_op | tsx_op;
assign sb_y = dey_op | iny_op | ldy_op |
tay_op;
assign acr_c = adc_op | asl_acc_op | asl_mem_op |
cmp_op | lsr_acc_op | lsr_mem_op |
rol_acc_op | rol_mem_op | ror_acc_op |
ror_mem_op;
assign db0_c = dl_to_p;
assign ir5_c = clc_op | sec_op;
assign db3_d = dl_to_p;
assign ir5_d = cld_op | sed_op;
assign db2_i = dl_to_p | one_to_i;
assign ir5_i = cli_op | sei_op;
assign db7_n = adc_op | and_op |
asl_acc_op | asl_mem_op |
cmp_op | dec_op | dex_op |
dey_op | dl_bits67_to_p | dl_to_p |
eor_op | inc_op | inx_op |
iny_op | lda_op | ldx_op |
ldy_op | lsr_acc_op | lsr_mem_op |
ora_op | rol_acc_op | rol_mem_op |
ror_acc_op | ror_mem_op | tax_op |
tay_op | tsx_op | txa_op |
tya_op;
assign avr_v = adc_op;
assign db6_v = dl_bits67_to_p | dl_to_p;
assign zero_v = clv_op;
assign db1_z = dl_to_p;
assign dbz_z = adc_op | and_op |
asl_acc_op | asl_mem_op |
bit_op | cmp_op | dec_op |
dex_op | dey_op | eor_op |
inc_op | inx_op | iny_op |
lda_op | ldx_op | ldy_op |
lsr_acc_op | lsr_mem_op | ora_op |
rol_acc_op | rol_mem_op | ror_acc_op |
ror_mem_op | tax_op | tay_op |
tsx_op | txa_op | tya_op;
assign ands = and_op | bit_op;
assign eors = eor_op;
assign ors = ora_op;
assign sums = adc_op | aluinc_to_abh | aluinc_to_abl |
aluinc_to_bi | aluinc_to_s |
alusum_to_abh | alusum_to_abl | alusum_to_bi |
alusum_to_pch | alusum_to_pcl | alusum_to_s |
asl_acc_op | asl_mem_op | cmp_op |
dec_op | dex_op | dey_op |
inc_op | inx_op | iny_op |
rol_acc_op | rol_mem_op;
assign srs = lsr_acc_op | lsr_mem_op |
ror_acc_op | ror_mem_op;
assign addc = (adc_op | rol_acc_op | rol_mem_op | ror_acc_op | ror_mem_op) ? q_c :
aluinc_to_abh | aluinc_to_abl | aluinc_to_bi |
aluinc_to_s | cmp_op |
inc_op | inx_op | iny_op;
assign i_pc = (incpc_noload | load_prg_byte) & !force_noinc_pc;
//
// Update internal buses. Use in/out to replicate pass mosfets and avoid using internal
// tristate buffers.
//
assign adh_in[7:1] = (dl_adh) ? q_dl[7:1] :
(pch_adh) ? q_pch[7:1] :
(zero_adh17) ? 7'h00 : 7'h7F;
assign adh_in[0] = (dl_adh) ? q_dl[0] :
(pch_adh) ? q_pch[0] :
(zero_adh0) ? 1'b0 : 1'b1;
assign adl[7:3] = (add_adl) ? q_add[7:3] :
(dl_adl) ? q_dl[7:3] :
(pcl_adl) ? q_pcl[7:3] :
(s_adl) ? q_s[7:3] : 5'h1F;
assign adl[2] = (add_adl) ? q_add[2] :
(dl_adl) ? q_dl[2] :
(pcl_adl) ? q_pcl[2] :
(s_adl) ? q_s[2] :
(zero_adl2) ? 1'b0 : 1'b1;
assign adl[1] = (add_adl) ? q_add[1] :
(dl_adl) ? q_dl[1] :
(pcl_adl) ? q_pcl[1] :
(s_adl) ? q_s[1] :
(zero_adl1) ? 1'b0 : 1'b1;
assign adl[0] = (add_adl) ? q_add[0] :
(dl_adl) ? q_dl[0] :
(pcl_adl) ? q_pcl[0] :
(s_adl) ? q_s[0] :
(zero_adl0) ? 1'b0 : 1'b1;
assign db_in = 8'hFF & ({8{~ac_db}} | q_ac) &
({8{~dl_db}} | q_dl) &
({8{~p_db}} | p) &
({8{~pch_db}} | q_pch) &
({8{~pcl_db}} | q_pcl);
assign sb_in = 8'hFF & ({8{~ac_sb}} | q_ac) &
({8{~add_sb}} | q_add) &
({8{~s_sb}} | q_s) &
({8{~x_sb}} | q_x) &
({8{~y_sb}} | q_y);
assign adh_out = (sb_adh & sb_db) ? (adh_in & sb_in & db_in) :
(sb_adh) ? (adh_in & sb_in) :
(adh_in);
assign db_out = (sb_db & sb_adh) ? (db_in & sb_in & adh_in) :
(sb_db) ? (db_in & sb_in) :
(db_in);
assign sb_out = (sb_adh & sb_db) ? (sb_in & db_in & adh_in) :
(sb_db) ? (sb_in & db_in) :
(sb_adh) ? (sb_in & adh_in) :
(sb_in);
//
// Assign next FF states.
//
assign d_ac = (sb_ac) ? sb_out : q_ac;
assign d_x = (sb_x) ? sb_out : q_x;
assign d_y = (sb_y) ? sb_out : q_y;
assign d_c = (acr_c) ? acr :
(db0_c) ? db_out[0] :
(ir5_c) ? q_ir[5] : q_c;
assign d_d = (db3_d) ? db_out[3] :
(ir5_d) ? q_ir[5] : q_d;
assign d_i = (db2_i) ? db_out[2] :
(ir5_i) ? q_ir[5] : q_i;
assign d_n = (db7_n) ? db_out[7] : q_n;
assign d_v = (avr_v) ? avr :
(db6_v) ? db_out[6] :
(zero_v) ? 1'b0 : q_v;
assign d_z = (db1_z) ? db_out[1] :
(dbz_z) ? ~|db_out : q_z;
assign d_abh = (adh_abh) ? adh_out : q_abh;
assign d_abl = (adl_abl) ? adl : q_abl;
assign d_ai = (sb_add) ? sb_out :
(zero_add) ? 8'h0 : q_ai;
assign d_bi = (adl_add) ? adl :
(db_add) ? db_out :
(invdb_add) ? ~db_out : q_bi;
assign d_dl = (r_nw_out) ? d_in : q_dl;
assign d_dor = db_out;
assign d_pd = (r_nw_out) ? d_in : q_pd;
assign d_s = (sb_s) ? sb_out : q_s;
assign d_pchs = (adh_pch) ? adh_out : q_pch;
assign d_pcls = (adl_pcl) ? adl : q_pcl;
assign { d_pch, d_pcl } = (i_pc) ? { q_pchs, q_pcls } + 16'h0001 : { q_pchs, q_pcls };
// Combine full processor status register.
assign p = { q_n, q_v, 1'b1, (q_irq_sel == INTERRUPT_BRK), q_d, q_i, q_z, q_c };
//
// Assign output signals.
//
assign d_out = q_dor;
assign a_out = { q_abh, q_abl };
always @*
begin
case (dbgreg_sel_in)
`REGSEL_AC: dbgreg_out = q_ac;
`REGSEL_X: dbgreg_out = q_x;
`REGSEL_Y: dbgreg_out = q_y;
`REGSEL_P: dbgreg_out = p;
`REGSEL_PCH: dbgreg_out = q_pch;
`REGSEL_PCL: dbgreg_out = q_pcl;
`REGSEL_S: dbgreg_out = q_s;
default: dbgreg_out = 8'hxx;
endcase
end
endmodule |
module sky130_fd_sc_hs__a311oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
// Local signals
wire B1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule |
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hvl__nor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule |
module iobdg_int_mondo_addr_dec (/*AUTOARG*/
// Outputs
creg_mdata0_dec, creg_mdata1_dec, creg_mbusy_dec, mondo_data_addr,
addr_invld,
// Inputs
addr_in, thr_id_in
);
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
input [`IOB_ADDR_WIDTH-1:0] addr_in;
input [`IOB_CPUTHR_INDEX-1:0] thr_id_in;
output creg_mdata0_dec;
output creg_mdata1_dec;
output creg_mbusy_dec;
output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr;
output addr_invld;
wire creg_mdata0_alias_dec;
wire creg_mdata1_alias_dec;
wire creg_mbusy_alias_dec;
wire creg_mdata0_proper_dec;
wire creg_mdata1_proper_dec;
wire creg_mbusy_proper_dec;
wire use_thr_addr;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
// Assertion: Decode signals should be mutually exclusive.
/*****************************************************************
* Decode for Mondo Data0, Mondo Data1, Mondo Busy access
* Assumption: addr_in is within the IOB_INT_CSR range
*****************************************************************/
// Decode alias address (what software normally uses)
assign creg_mdata0_alias_dec =
(addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0]
== `IOB_CREG_MDATA0_ALIAS);
assign creg_mdata1_alias_dec =
(addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0]
== `IOB_CREG_MDATA1_ALIAS);
assign creg_mbusy_alias_dec =
(addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0]
== `IOB_CREG_MBUSY_ALIAS);
// Decode proper address (what the TAP has to use)
assign creg_mdata0_proper_dec =
((addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0] & `IOB_THR_ADDR_MASK)
== `IOB_CREG_MDATA0);
assign creg_mdata1_proper_dec =
((addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0] & `IOB_THR_ADDR_MASK)
== `IOB_CREG_MDATA1);
assign creg_mbusy_proper_dec =
((addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0] & `IOB_THR_ADDR_MASK)
== `IOB_CREG_MBUSY);
// Combine proper and alias decode results
assign creg_mdata0_dec = creg_mdata0_proper_dec | creg_mdata0_alias_dec;
assign creg_mdata1_dec = creg_mdata1_proper_dec | creg_mdata1_alias_dec;
assign creg_mbusy_dec = creg_mbusy_proper_dec | creg_mbusy_alias_dec;
assign use_thr_addr = creg_mdata0_alias_dec |
creg_mdata1_alias_dec |
creg_mbusy_alias_dec;
// Use thread ID as index into array if request comes from software
// Use the address directly if request comes from TAP
assign mondo_data_addr = use_thr_addr ? thr_id_in :
addr_in[`IOB_MONDO_DATA_INDEX-1+3:3];
/*****************************************************************
* Assert address invalid if no register address match
*****************************************************************/
assign addr_invld = ~creg_mdata0_dec &
~creg_mdata1_dec &
~creg_mbusy_dec;
endmodule |
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_ps2, input_i2c, input_switches, input_eth_rx, input_buttons, input_timer_stb, input_rs232_rx_stb, input_ps2_stb, input_i2c_stb, input_switches_stb, input_eth_rx_stb, input_buttons_stb, input_timer_ack, input_rs232_rx_ack, input_ps2_ack, input_i2c_ack, input_switches_ack, input_eth_rx_ack, input_buttons_ack, output_seven_segment_annode, output_eth_tx, output_rs232_tx, output_leds, output_audio, output_led_g, output_seven_segment_cathode, output_led_b, output_i2c, output_vga, output_led_r, output_seven_segment_annode_stb, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_audio_stb, output_led_g_stb, output_seven_segment_cathode_stb, output_led_b_stb, output_i2c_stb, output_vga_stb, output_led_r_stb, output_seven_segment_annode_ack, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack, output_audio_ack, output_led_g_ack, output_seven_segment_cathode_ack, output_led_b_ack, output_i2c_ack, output_vga_ack, output_led_r_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
input [31:0] input_i2c;
input input_i2c_stb;
output input_i2c_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
output [31:0] output_seven_segment_annode;
output output_seven_segment_annode_stb;
input output_seven_segment_annode_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_audio;
output output_audio_stb;
input output_audio_ack;
output [31:0] output_led_g;
output output_led_g_stb;
input output_led_g_ack;
output [31:0] output_seven_segment_cathode;
output output_seven_segment_cathode_stb;
input output_seven_segment_cathode_ack;
output [31:0] output_led_b;
output output_led_b_stb;
input output_led_b_ack;
output [31:0] output_i2c;
output output_i2c_stb;
input output_i2c_ack;
output [31:0] output_vga;
output output_vga_stb;
input output_vga_ack;
output [31:0] output_led_r;
output output_led_r_stb;
input output_led_r_ack;
wire exception_139931276207744;
wire exception_139931276329976;
wire exception_139931273691576;
wire exception_139931279256392;
wire exception_139931273476792;
wire exception_139931279285064;
wire exception_139931284115112;
wire exception_139931283339240;
wire exception_139931274721040;
wire exception_139931279910528;
wire exception_139931279158952;
wire exception_139931276720176;
wire exception_139931279933952;
wire exception_139931278247408;
wire exception_139931279929216;
wire exception_139931284950696;
wire exception_139931275440568;
main_0 main_0_139931276207744(
.clk(clk),
.rst(rst),
.exception(exception_139931276207744),
.output_rs232_out(output_rs232_tx),
.output_rs232_out_stb(output_rs232_tx_stb),
.output_rs232_out_ack(output_rs232_tx_ack),
.output_vga_out(output_vga),
.output_vga_out_stb(output_vga_stb),
.output_vga_out_ack(output_vga_ack));
main_1 main_1_139931276329976(
.clk(clk),
.rst(rst),
.exception(exception_139931276329976),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_139931273691576(
.clk(clk),
.rst(rst),
.exception(exception_139931273691576),
.input_in(input_rs232_rx),
.input_in_stb(input_rs232_rx_stb),
.input_in_ack(input_rs232_rx_ack));
main_3 main_3_139931279256392(
.clk(clk),
.rst(rst),
.exception(exception_139931279256392),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_4 main_4_139931273476792(
.clk(clk),
.rst(rst),
.exception(exception_139931273476792),
.input_in(input_i2c),
.input_in_stb(input_i2c_stb),
.input_in_ack(input_i2c_ack));
main_5 main_5_139931279285064(
.clk(clk),
.rst(rst),
.exception(exception_139931279285064),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_6 main_6_139931284115112(
.clk(clk),
.rst(rst),
.exception(exception_139931284115112),
.input_in(input_eth_rx),
.input_in_stb(input_eth_rx_stb),
.input_in_ack(input_eth_rx_ack));
main_7 main_7_139931283339240(
.clk(clk),
.rst(rst),
.exception(exception_139931283339240),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_8 main_8_139931274721040(
.clk(clk),
.rst(rst),
.exception(exception_139931274721040),
.output_out(output_seven_segment_annode),
.output_out_stb(output_seven_segment_annode_stb),
.output_out_ack(output_seven_segment_annode_ack));
main_9 main_9_139931279910528(
.clk(clk),
.rst(rst),
.exception(exception_139931279910528),
.output_out(output_eth_tx),
.output_out_stb(output_eth_tx_stb),
.output_out_ack(output_eth_tx_ack));
main_10 main_10_139931279158952(
.clk(clk),
.rst(rst),
.exception(exception_139931279158952),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
main_11 main_11_139931276720176(
.clk(clk),
.rst(rst),
.exception(exception_139931276720176),
.output_out(output_audio),
.output_out_stb(output_audio_stb),
.output_out_ack(output_audio_ack));
main_12 main_12_139931279933952(
.clk(clk),
.rst(rst),
.exception(exception_139931279933952),
.output_out(output_led_g),
.output_out_stb(output_led_g_stb),
.output_out_ack(output_led_g_ack));
main_13 main_13_139931278247408(
.clk(clk),
.rst(rst),
.exception(exception_139931278247408),
.output_out(output_seven_segment_cathode),
.output_out_stb(output_seven_segment_cathode_stb),
.output_out_ack(output_seven_segment_cathode_ack));
main_14 main_14_139931279929216(
.clk(clk),
.rst(rst),
.exception(exception_139931279929216),
.output_out(output_led_b),
.output_out_stb(output_led_b_stb),
.output_out_ack(output_led_b_ack));
main_15 main_15_139931284950696(
.clk(clk),
.rst(rst),
.exception(exception_139931284950696),
.output_out(output_i2c),
.output_out_stb(output_i2c_stb),
.output_out_ack(output_i2c_ack));
main_16 main_16_139931275440568(
.clk(clk),
.rst(rst),
.exception(exception_139931275440568),
.output_out(output_led_r),
.output_out_stb(output_led_r_stb),
.output_out_ack(output_led_r_ack));
assign exception = exception_139931276207744 || exception_139931276329976 || exception_139931273691576 || exception_139931279256392 || exception_139931273476792 || exception_139931279285064 || exception_139931284115112 || exception_139931283339240 || exception_139931274721040 || exception_139931279910528 || exception_139931279158952 || exception_139931276720176 || exception_139931279933952 || exception_139931278247408 || exception_139931279929216 || exception_139931284950696 || exception_139931275440568;
endmodule |
module cmd_seq_core #(
parameter ABUSWIDTH = 16,
parameter OUTPUTS = 1, // from (0 : 8]
parameter CMD_MEM_SIZE = 2048 // max. 8192-1 bytes
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
input wire BUS_RD,
input wire BUS_WR,
output reg [7:0] BUS_DATA_OUT,
output wire [OUTPUTS-1:0] CMD_CLK_OUT,
input wire CMD_CLK_IN,
input wire CMD_EXT_START_FLAG,
output wire CMD_EXT_START_ENABLE,
output wire [OUTPUTS-1:0] CMD_DATA,
output reg CMD_READY,
output reg CMD_START_FLAG
);
localparam VERSION = 1;
generate
if (OUTPUTS > 8) begin
illegal_outputs_parameter non_existing_module();
end
endgenerate
generate
if (CMD_MEM_SIZE > 8191) begin
illegal_outputs_parameter non_existing_module();
end
endgenerate
// IEEE Std 1800-2009
// generate
// if (CONDITION > MAX_ALLOWED) begin
// $error("%m ** Illegal Condition ** CONDITION(%d) > MAX_ALLOWED(%d)", CONDITION, MAX_ALLOWED);
// end
// endgenerate
`include "../includes/log2func.v"
localparam CMD_ADDR_SIZE = `CLOG2(CMD_MEM_SIZE);
wire SOFT_RST; //0
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
// reset sync
// when write to addr = 0 then reset
reg RST_FF, RST_FF2, BUS_RST_FF, BUS_RST_FF2;
always @(posedge BUS_CLK) begin
RST_FF <= SOFT_RST;
RST_FF2 <= RST_FF;
BUS_RST_FF <= BUS_RST;
BUS_RST_FF2 <= BUS_RST_FF;
end
wire SOFT_RST_FLAG;
assign SOFT_RST_FLAG = ~RST_FF2 & RST_FF;
wire BUS_RST_FLAG;
assign BUS_RST_FLAG = BUS_RST_FF2 & ~BUS_RST_FF; // trailing edge
wire RST;
assign RST = BUS_RST_FLAG | SOFT_RST_FLAG;
wire RST_CMD_CLK;
flag_domain_crossing cmd_rst_flag_domain_crossing (
.CLK_A(BUS_CLK),
.CLK_B(CMD_CLK_IN),
.FLAG_IN_CLK_A(RST),
.FLAG_OUT_CLK_B(RST_CMD_CLK)
);
wire CONF_START; // 1
assign CONF_START = (BUS_ADD==1 && BUS_WR);
wire CONF_START_FLAG_SYNC;
flag_domain_crossing conf_start_flag_domain_crossing (
.CLK_A(BUS_CLK),
.CLK_B(CMD_CLK_IN),
.FLAG_IN_CLK_A(CONF_START),
.FLAG_OUT_CLK_B(CONF_START_FLAG_SYNC)
);
reg [0:0] CONF_READY; // 1
wire CONF_EN_EXT_START, CONF_DIS_CLOCK_GATE, CONF_DIS_CMD_PULSE; // 2
wire [1:0] CONF_OUTPUT_MODE; // 2 Mode == 0: posedge, 1: negedge, 2: Manchester Code according to IEEE 802.3, 3: Manchester Code according to G.E. Thomas aka Biphase-L or Manchester-II
wire [15:0] CONF_CMD_SIZE; // 3 - 4
wire [31:0] CONF_REPEAT_COUNT; // 5 - 8
wire [15:0] CONF_START_REPEAT; // 9 - 10
wire [15:0] CONF_STOP_REPEAT; // 11 - 12
wire [7:0] CONF_OUTPUT_ENABLE; //13
// ATTENTION:
// -(CONF_CMD_SIZE - CONF_START_REPEAT - CONF_STOP_REPEAT) must be greater than or equal to 2
// - CONF_START_REPEAT must be greater than or equal to 2
// - CONF_STOP_REPEAT must be greater than or equal to 2
reg [7:0] status_regs [13:0];
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0;
status_regs[1] <= 0;
status_regs[2] <= 8'b0000_0000;
status_regs[3] <= 0;
status_regs[4] <= 0;
status_regs[5] <= 8'd1; // CONF_REPEAT_COUNT, repeat once by default
status_regs[6] <= 0;
status_regs[7] <= 0;
status_regs[8] <= 0;
status_regs[9] <= 0; // CONF_START_REPEAT
status_regs[10] <= 0;
status_regs[11] <= 0;// CONF_STOP_REPEAT
status_regs[12] <= 0;
status_regs[13] <= 8'hff; //OUTPUT_EN
end
else if(BUS_WR && BUS_ADD < 14)
status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN;
end
assign CONF_CMD_SIZE = {status_regs[4], status_regs[3]};
assign CONF_REPEAT_COUNT = {status_regs[8], status_regs[7], status_regs[6], status_regs[5]};
assign CONF_START_REPEAT = {status_regs[10], status_regs[9]};
assign CONF_STOP_REPEAT = {status_regs[12], status_regs[11]};
assign CONF_OUTPUT_ENABLE = status_regs[13];
assign CONF_DIS_CMD_PULSE = status_regs[2][4];
assign CONF_DIS_CLOCK_GATE = status_regs[2][3];
assign CONF_OUTPUT_MODE = status_regs[2][2:1];
assign CONF_EN_EXT_START = status_regs[2][0];
three_stage_synchronizer conf_en_ext_start_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_EN_EXT_START),
.OUT(CMD_EXT_START_ENABLE)
);
wire [15:0] CONF_CMD_SIZE_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(16)
) cmd_size_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_CMD_SIZE),
.OUT(CONF_CMD_SIZE_CMD_CLK)
);
wire [31:0] CONF_REPEAT_COUNT_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(32)
) repeat_cnt_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_REPEAT_COUNT),
.OUT(CONF_REPEAT_COUNT_CMD_CLK)
);
wire [15:0] CONF_START_REPEAT_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(16)
) start_repeat_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_START_REPEAT),
.OUT(CONF_START_REPEAT_CMD_CLK)
);
wire [15:0] CONF_STOP_REPEAT_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(16)
) stop_repeat_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_STOP_REPEAT),
.OUT(CONF_STOP_REPEAT_CMD_CLK)
);
wire [OUTPUTS-1:0] CONF_OUTPUT_ENABLE_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(OUTPUTS)
) conf_output_enable_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_OUTPUT_ENABLE[OUTPUTS-1:0]),
.OUT(CONF_OUTPUT_ENABLE_CMD_CLK)
);
wire CONF_DIS_CMD_PULSE_CMD_CLK;
three_stage_synchronizer conf_dis_cmd_pulse_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_DIS_CMD_PULSE),
.OUT(CONF_DIS_CMD_PULSE_CMD_CLK)
);
wire CONF_DIS_CLOCK_GATE_CMD_CLK;
three_stage_synchronizer conf_dis_clock_gate_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_DIS_CLOCK_GATE),
.OUT(CONF_DIS_CLOCK_GATE_CMD_CLK)
);
wire [1:0] CONF_OUTPUT_MODE_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(2)
) conf_output_mode_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_OUTPUT_MODE),
.OUT(CONF_OUTPUT_MODE_CMD_CLK)
);
wire [7:0] CMD_MEM_DATA;
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= {7'b0, CONF_READY};
else if(BUS_ADD < 14)
BUS_DATA_OUT <= status_regs[BUS_ADD[3:0]];
else if(BUS_ADD < 16)
BUS_DATA_OUT <= 8'b0;
else if(BUS_ADD < (16 + CMD_MEM_SIZE))
BUS_DATA_OUT <= CMD_MEM_DATA;
end
end
// (* RAM_STYLE="{BLOCK}" *)
reg [7:0] cmd_mem [0:CMD_MEM_SIZE-1];
always @(posedge BUS_CLK) begin
if (BUS_WR && BUS_ADD >= 16 && BUS_ADD < (16 + CMD_MEM_SIZE))
cmd_mem[BUS_ADD - 16] <= BUS_DATA_IN;
end
reg [CMD_ADDR_SIZE-1:0] CMD_MEM_ADD;
assign CMD_MEM_DATA = cmd_mem[BUS_RD && BUS_ADD >= 16 && BUS_ADD < (16 + CMD_MEM_SIZE) ? (BUS_ADD - 16) : CMD_MEM_ADD];
wire EXT_START_FLAG;
assign EXT_START_FLAG = (CMD_EXT_START_FLAG & CMD_EXT_START_ENABLE);
wire send_cmd;
assign send_cmd = CONF_START_FLAG_SYNC | EXT_START_FLAG;
localparam WAIT = 0, SEND = 1;
reg [15:0] cnt;
reg [31:0] repeat_cnt;
reg state, next_state;
always @(posedge CMD_CLK_IN)
if (RST_CMD_CLK)
state <= WAIT;
else
state <= next_state;
// reg END_SEQ_REP_NEXT, END_SEQ_REP;
// always @(*) begin
// if((repeat_cnt < CONF_REPEAT_COUNT_CMD_CLK || CONF_REPEAT_COUNT_CMD_CLK == 0) && cnt == CONF_CMD_SIZE_CMD_CLK - 1 - CONF_STOP_REPEAT_CMD_CLK && !END_SEQ_REP)
// END_SEQ_REP_NEXT = 1;
// else
// END_SEQ_REP_NEXT = 0;
// end
// always @(posedge CMD_CLK_IN)
// END_SEQ_REP <= END_SEQ_REP_NEXT;
reg START_STOP_REPEAT_OK;
always @(posedge CMD_CLK_IN)
if ((CONF_START_REPEAT_CMD_CLK + CONF_STOP_REPEAT_CMD_CLK) > CONF_CMD_SIZE_CMD_CLK)
START_STOP_REPEAT_OK <= 1'b0;
else
START_STOP_REPEAT_OK <= 1'b1;
reg [31:0] SET_REPEAT_COUNT;
always @(posedge CMD_CLK_IN)
if (CONF_START_REPEAT_CMD_CLK + CONF_STOP_REPEAT_CMD_CLK == CONF_CMD_SIZE_CMD_CLK)
SET_REPEAT_COUNT <= 1;
else
SET_REPEAT_COUNT <= CONF_REPEAT_COUNT_CMD_CLK;
always @(*) begin
case (state)
WAIT:
if (send_cmd && CONF_CMD_SIZE_CMD_CLK != 0 && START_STOP_REPEAT_OK)
next_state = SEND;
else
next_state = WAIT;
SEND:
if (cnt >= CONF_CMD_SIZE_CMD_CLK && repeat_cnt >= SET_REPEAT_COUNT && SET_REPEAT_COUNT != 0)
next_state = WAIT;
else
next_state = SEND;
default:
next_state = WAIT;
endcase
end
always @(posedge CMD_CLK_IN) begin
if (RST_CMD_CLK) begin
cnt <= 0;
end else begin
if (next_state == WAIT) begin
cnt <= 0; // TODO: adding start value here
end else begin
if ((repeat_cnt < SET_REPEAT_COUNT || SET_REPEAT_COUNT == 0) && (cnt == CONF_CMD_SIZE_CMD_CLK - CONF_STOP_REPEAT_CMD_CLK - 1)) begin
cnt <= CONF_START_REPEAT_CMD_CLK;
end else begin
cnt <= cnt + 1;
end
end
end
end
always @(posedge CMD_CLK_IN) begin
if (RST_CMD_CLK)
repeat_cnt <= 1;
else
if (next_state == WAIT)
repeat_cnt <= 1;
else if ((next_state == SEND) && (cnt == CONF_CMD_SIZE_CMD_CLK - CONF_STOP_REPEAT_CMD_CLK - 1))
repeat_cnt <= repeat_cnt + 1;
end
// always @(posedge CMD_CLK_IN) begin
// if (RST_CMD_CLK) begin
// CMD_MEM_ADD <= 0;
// end else begin
// CMD_MEM_ADD <= cnt / 8;
// end
// end
// reg cmd_data_ser;
// always @(posedge CMD_CLK_IN) begin
// if (state == WAIT)
// cmd_data_ser <= 1'b0;
// else
// cmd_data_ser <= CMD_MEM_DATA[7 - ((cnt_buf) % 8)];
// end
always @(posedge CMD_CLK_IN) begin
if (RST_CMD_CLK) begin
CMD_MEM_ADD <= 0;
end else begin
if (cnt == CONF_CMD_SIZE_CMD_CLK - CONF_STOP_REPEAT_CMD_CLK - 1 && repeat_cnt < SET_REPEAT_COUNT && SET_REPEAT_COUNT != 0) begin
CMD_MEM_ADD <= CONF_START_REPEAT_CMD_CLK / 8;
end else begin
// if ()
CMD_MEM_ADD <= (cnt + 1) / 8;
end
end
end
reg [7:0] CMD_MEM_DATA_BUF;
always @(posedge CMD_CLK_IN) begin
CMD_MEM_DATA_BUF <= CMD_MEM_DATA;
end
reg [15:0] cnt_buf;
always @(posedge CMD_CLK_IN) begin
cnt_buf <= cnt;
end
reg cmd_data_ser;
always @(posedge CMD_CLK_IN) begin
if (state == WAIT)
cmd_data_ser <= 1'b0;
else
cmd_data_ser <= CMD_MEM_DATA_BUF[7 - ((cnt_buf) % 8)];
end
reg [OUTPUTS-1:0] cmd_data_neg;
reg [OUTPUTS-1:0] cmd_data_pos;
always @(negedge CMD_CLK_IN)
cmd_data_neg <= {OUTPUTS{cmd_data_ser}} & CONF_OUTPUT_ENABLE_CMD_CLK;
always @(posedge CMD_CLK_IN)
cmd_data_pos <= {OUTPUTS{cmd_data_ser}} & CONF_OUTPUT_ENABLE_CMD_CLK;
genvar k;
generate
for (k = 0; k < OUTPUTS; k = k + 1) begin: gen
ODDR MANCHESTER_CODE_INST (
.Q(CMD_DATA[k]),
.C(CMD_CLK_IN),
.CE(1'b1),
.D1((CONF_OUTPUT_MODE_CMD_CLK == 2'b00) ? cmd_data_pos[k] : ((CONF_OUTPUT_MODE_CMD_CLK == 2'b01) ? cmd_data_neg[k] : ((CONF_OUTPUT_MODE_CMD_CLK == 2'b10) ? ~cmd_data_pos[k] : cmd_data_pos[k]))),
.D2((CONF_OUTPUT_MODE_CMD_CLK == 2'b00) ? cmd_data_pos[k] : ((CONF_OUTPUT_MODE_CMD_CLK == 2'b01) ? cmd_data_neg[k] : ((CONF_OUTPUT_MODE_CMD_CLK == 2'b10) ? cmd_data_pos[k] : ~cmd_data_pos[k]))),
.R(1'b0),
.S(1'b0)
);
ODDR CMD_CLK_FORWARDING_INST (
.Q(CMD_CLK_OUT[k]),
.C(CMD_CLK_IN),
.CE(1'b1),
.D1(1'b1),
.D2(1'b0),
.R(CONF_DIS_CLOCK_GATE_CMD_CLK),
.S(1'b0)
);
end
endgenerate
// ready signal
always @(posedge CMD_CLK_IN)
CMD_READY <= ~next_state;
// command start flag
reg CMD_START_SIGNAL;
always @(posedge CMD_CLK_IN)
if (state == SEND && cnt_buf == CONF_START_REPEAT_CMD_CLK && CONF_DIS_CMD_PULSE_CMD_CLK == 1'b0)
CMD_START_SIGNAL <= 1'b1;
else
CMD_START_SIGNAL <= 1'b0;
reg CMD_START_SIGNAL_FF, CMD_START_SIGNAL_FF2;
always @(posedge CMD_CLK_IN) begin
CMD_START_SIGNAL_FF <= CMD_START_SIGNAL;
CMD_START_SIGNAL_FF2 <= CMD_START_SIGNAL_FF;
end
always @(posedge CMD_CLK_IN)
if (CONF_OUTPUT_MODE_CMD_CLK == 2'b00)
CMD_START_FLAG <= ~CMD_START_SIGNAL_FF2 & CMD_START_SIGNAL_FF; // delay by 1, 180 degree phase shifted data in output mode 0
else
CMD_START_FLAG <= ~CMD_START_SIGNAL_FF & CMD_START_SIGNAL;
// command start flag
reg CMD_BUSY_FLAG;
always @(posedge CMD_CLK_IN)
if (state != next_state && next_state == SEND)
CMD_BUSY_FLAG <= 1'b1;
else
CMD_BUSY_FLAG <= 1'b0;
// ready flag
reg CMD_READY_FLAG;
always @(posedge CMD_CLK_IN)
if (state != next_state && next_state == WAIT)
CMD_READY_FLAG <= 1'b1;
else
CMD_READY_FLAG <= 1'b0;
wire CMD_BUSY_FLAG_BUS_CLK;
flag_domain_crossing cmd_busy_flag_domain_crossing (
.CLK_A(CMD_CLK_IN),
.CLK_B(BUS_CLK),
.FLAG_IN_CLK_A(CMD_BUSY_FLAG),
.FLAG_OUT_CLK_B(CMD_BUSY_FLAG_BUS_CLK)
);
wire CMD_READY_FLAG_BUS_CLK;
flag_domain_crossing cmd_ready_flag_domain_crossing (
.CLK_A(CMD_CLK_IN),
.CLK_B(BUS_CLK),
.FLAG_IN_CLK_A(CMD_READY_FLAG),
.FLAG_OUT_CLK_B(CMD_READY_FLAG_BUS_CLK)
);
always @(posedge BUS_CLK)
if(RST)
CONF_READY <= 1;
else
if(CMD_BUSY_FLAG_BUS_CLK || CONF_START)
CONF_READY <= 0;
else if(CMD_READY_FLAG_BUS_CLK)
CONF_READY <= 1;
endmodule |
module RAM40x7bits(Address, Din, Clock, Reset, WriteEnabled, Dout);
input [5:0] Address;
input [6:0] Din;
input Reset;
input Clock, WriteEnabled;
output [6:0] Dout;
reg [6:0] Data [39:0];
always@(posedge Clock or posedge Reset)
if (Reset == 1) begin // This spells out
Data[0] <= "E"; // ECE333 Fall 2015 Digital Systems
Data[1] <= "C";
Data[2] <= "E";
Data[3] <= "3";
Data[4] <= "3";
Data[5] <= "3";
Data[6] <= " ";
Data[7] <= "F";
Data[8] <= "a";
Data[9] <= "l";
Data[10] <= "l";
Data[11] <= " ";
Data[12] <= "2";
Data[13] <= "0";
Data[14] <= "1";
Data[15] <= "5";
Data[16] <= " ";
Data[17] <= "D";
Data[18] <= "i";
Data[19] <= "g";
Data[20] <= "i";
Data[21] <= "t";
Data[22] <= "a";
Data[23] <= "l";
Data[24] <= " ";
Data[25] <= "S";
Data[26] <= "y";
Data[27] <= "s";
Data[28] <= "t";
Data[29] <= "e";
Data[30] <= "m";
Data[31] <= "s";
Data[32] <= "\n";
Data[33] <= "\r";
end
else if (WriteEnabled == 1) Data[Address] <= Din;
assign Dout = Data[Address];
endmodule |
module receives an IP frame with header fields in parallel and payload on
an AXI stream interface, decodes and strips the UDP header fields, then
produces the header fields in parallel along with the UDP payload in a
separate AXI stream.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_READ_PAYLOAD = 3'd2,
STATE_READ_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_ip_hdr;
reg store_udp_source_port_0;
reg store_udp_source_port_1;
reg store_udp_dest_port_0;
reg store_udp_dest_port_1;
reg store_udp_length_0;
reg store_udp_length_1;
reg store_udp_checksum_0;
reg store_udp_checksum_1;
reg store_last_word;
reg [2:0] hdr_ptr_reg = 3'd0, hdr_ptr_next;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg [7:0] last_word_data_reg = 8'd0;
reg m_udp_hdr_valid_reg = 1'b0, m_udp_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [3:0] m_ip_version_reg = 4'd0;
reg [3:0] m_ip_ihl_reg = 4'd0;
reg [5:0] m_ip_dscp_reg = 6'd0;
reg [1:0] m_ip_ecn_reg = 2'd0;
reg [15:0] m_ip_length_reg = 16'd0;
reg [15:0] m_ip_identification_reg = 16'd0;
reg [2:0] m_ip_flags_reg = 3'd0;
reg [12:0] m_ip_fragment_offset_reg = 13'd0;
reg [7:0] m_ip_ttl_reg = 8'd0;
reg [7:0] m_ip_protocol_reg = 8'd0;
reg [15:0] m_ip_header_checksum_reg = 16'd0;
reg [31:0] m_ip_source_ip_reg = 32'd0;
reg [31:0] m_ip_dest_ip_reg = 32'd0;
reg [15:0] m_udp_source_port_reg = 16'd0;
reg [15:0] m_udp_dest_port_reg = 16'd0;
reg [15:0] m_udp_length_reg = 16'd0;
reg [15:0] m_udp_checksum_reg = 16'd0;
reg s_ip_hdr_ready_reg = 1'b0, s_ip_hdr_ready_next;
reg s_ip_payload_axis_tready_reg = 1'b0, s_ip_payload_axis_tready_next;
reg busy_reg = 1'b0;
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
// internal datapath
reg [7:0] m_udp_payload_axis_tdata_int;
reg m_udp_payload_axis_tvalid_int;
reg m_udp_payload_axis_tready_int_reg = 1'b0;
reg m_udp_payload_axis_tlast_int;
reg m_udp_payload_axis_tuser_int;
wire m_udp_payload_axis_tready_int_early;
assign s_ip_hdr_ready = s_ip_hdr_ready_reg;
assign s_ip_payload_axis_tready = s_ip_payload_axis_tready_reg;
assign m_udp_hdr_valid = m_udp_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign m_udp_source_port = m_udp_source_port_reg;
assign m_udp_dest_port = m_udp_dest_port_reg;
assign m_udp_length = m_udp_length_reg;
assign m_udp_checksum = m_udp_checksum_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
always @* begin
state_next = STATE_IDLE;
s_ip_hdr_ready_next = 1'b0;
s_ip_payload_axis_tready_next = 1'b0;
store_ip_hdr = 1'b0;
store_udp_source_port_0 = 1'b0;
store_udp_source_port_1 = 1'b0;
store_udp_dest_port_0 = 1'b0;
store_udp_dest_port_1 = 1'b0;
store_udp_length_0 = 1'b0;
store_udp_length_1 = 1'b0;
store_udp_checksum_0 = 1'b0;
store_udp_checksum_1 = 1'b0;
store_last_word = 1'b0;
hdr_ptr_next = hdr_ptr_reg;
word_count_next = word_count_reg;
m_udp_hdr_valid_next = m_udp_hdr_valid_reg && !m_udp_hdr_ready;
error_header_early_termination_next = 1'b0;
error_payload_early_termination_next = 1'b0;
m_udp_payload_axis_tdata_int = 8'd0;
m_udp_payload_axis_tvalid_int = 1'b0;
m_udp_payload_axis_tlast_int = 1'b0;
m_udp_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for header
hdr_ptr_next = 3'd0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
if (s_ip_hdr_ready && s_ip_hdr_valid) begin
s_ip_hdr_ready_next = 1'b0;
s_ip_payload_axis_tready_next = 1'b1;
store_ip_hdr = 1'b1;
state_next = STATE_READ_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_HEADER: begin
// read header state
s_ip_payload_axis_tready_next = 1'b1;
word_count_next = m_udp_length_reg - 16'd8;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
// word transfer in - store it
hdr_ptr_next = hdr_ptr_reg + 3'd1;
state_next = STATE_READ_HEADER;
case (hdr_ptr_reg)
3'h0: store_udp_source_port_1 = 1'b1;
3'h1: store_udp_source_port_0 = 1'b1;
3'h2: store_udp_dest_port_1 = 1'b1;
3'h3: store_udp_dest_port_0 = 1'b1;
3'h4: store_udp_length_1 = 1'b1;
3'h5: store_udp_length_0 = 1'b1;
3'h6: store_udp_checksum_1 = 1'b1;
3'h7: begin
store_udp_checksum_0 = 1'b1;
m_udp_hdr_valid_next = 1'b1;
s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early;
state_next = STATE_READ_PAYLOAD;
end
endcase
if (s_ip_payload_axis_tlast) begin
error_header_early_termination_next = 1'b1;
m_udp_hdr_valid_next = 1'b0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_READ_PAYLOAD: begin
// read payload
s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early;
m_udp_payload_axis_tdata_int = s_ip_payload_axis_tdata;
m_udp_payload_axis_tvalid_int = s_ip_payload_axis_tvalid;
m_udp_payload_axis_tlast_int = s_ip_payload_axis_tlast;
m_udp_payload_axis_tuser_int = s_ip_payload_axis_tuser;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 16'd1;
if (s_ip_payload_axis_tlast) begin
if (word_count_reg != 16'd1) begin
// end of frame, but length does not match
m_udp_payload_axis_tuser_int = 1'b1;
error_payload_early_termination_next = 1'b1;
end
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
if (word_count_reg == 16'd1) begin
store_last_word = 1'b1;
m_udp_payload_axis_tvalid_int = 1'b0;
state_next = STATE_READ_PAYLOAD_LAST;
end else begin
state_next = STATE_READ_PAYLOAD;
end
end
end else begin
state_next = STATE_READ_PAYLOAD;
end
end
STATE_READ_PAYLOAD_LAST: begin
// read and discard until end of frame
s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early;
m_udp_payload_axis_tdata_int = last_word_data_reg;
m_udp_payload_axis_tvalid_int = s_ip_payload_axis_tvalid && s_ip_payload_axis_tlast;
m_udp_payload_axis_tlast_int = s_ip_payload_axis_tlast;
m_udp_payload_axis_tuser_int = s_ip_payload_axis_tuser;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
s_ip_payload_axis_tready_next = 1'b1;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_ip_hdr_ready_reg <= 1'b0;
s_ip_payload_axis_tready_reg <= 1'b0;
m_udp_hdr_valid_reg <= 1'b0;
busy_reg <= 1'b0;
error_header_early_termination_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
s_ip_payload_axis_tready_reg <= s_ip_payload_axis_tready_next;
m_udp_hdr_valid_reg <= m_udp_hdr_valid_next;
error_header_early_termination_reg <= error_header_early_termination_next;
error_payload_early_termination_reg <= error_payload_early_termination_next;
busy_reg <= state_next != STATE_IDLE;
end
hdr_ptr_reg <= hdr_ptr_next;
word_count_reg <= word_count_next;
// datapath
if (store_ip_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
m_ip_version_reg <= s_ip_version;
m_ip_ihl_reg <= s_ip_ihl;
m_ip_dscp_reg <= s_ip_dscp;
m_ip_ecn_reg <= s_ip_ecn;
m_ip_length_reg <= s_ip_length;
m_ip_identification_reg <= s_ip_identification;
m_ip_flags_reg <= s_ip_flags;
m_ip_fragment_offset_reg <= s_ip_fragment_offset;
m_ip_ttl_reg <= s_ip_ttl;
m_ip_protocol_reg <= s_ip_protocol;
m_ip_header_checksum_reg <= s_ip_header_checksum;
m_ip_source_ip_reg <= s_ip_source_ip;
m_ip_dest_ip_reg <= s_ip_dest_ip;
end
if (store_last_word) begin
last_word_data_reg <= m_udp_payload_axis_tdata_int;
end
if (store_udp_source_port_0) m_udp_source_port_reg[ 7: 0] <= s_ip_payload_axis_tdata;
if (store_udp_source_port_1) m_udp_source_port_reg[15: 8] <= s_ip_payload_axis_tdata;
if (store_udp_dest_port_0) m_udp_dest_port_reg[ 7: 0] <= s_ip_payload_axis_tdata;
if (store_udp_dest_port_1) m_udp_dest_port_reg[15: 8] <= s_ip_payload_axis_tdata;
if (store_udp_length_0) m_udp_length_reg[ 7: 0] <= s_ip_payload_axis_tdata;
if (store_udp_length_1) m_udp_length_reg[15: 8] <= s_ip_payload_axis_tdata;
if (store_udp_checksum_0) m_udp_checksum_reg[ 7: 0] <= s_ip_payload_axis_tdata;
if (store_udp_checksum_1) m_udp_checksum_reg[15: 8] <= s_ip_payload_axis_tdata;
end
// output datapath logic
reg [7:0] m_udp_payload_axis_tdata_reg = 8'd0;
reg m_udp_payload_axis_tvalid_reg = 1'b0, m_udp_payload_axis_tvalid_next;
reg m_udp_payload_axis_tlast_reg = 1'b0;
reg m_udp_payload_axis_tuser_reg = 1'b0;
reg [7:0] temp_m_udp_payload_axis_tdata_reg = 8'd0;
reg temp_m_udp_payload_axis_tvalid_reg = 1'b0, temp_m_udp_payload_axis_tvalid_next;
reg temp_m_udp_payload_axis_tlast_reg = 1'b0;
reg temp_m_udp_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_udp_payload_int_to_output;
reg store_udp_payload_int_to_temp;
reg store_udp_payload_axis_temp_to_output;
assign m_udp_payload_axis_tdata = m_udp_payload_axis_tdata_reg;
assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
assign m_udp_payload_axis_tuser = m_udp_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
store_udp_payload_int_to_output = 1'b0;
store_udp_payload_int_to_temp = 1'b0;
store_udp_payload_axis_temp_to_output = 1'b0;
if (m_udp_payload_axis_tready_int_reg) begin
// input is ready
if (m_udp_payload_axis_tready || !m_udp_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_udp_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_udp_payload_int_to_temp = 1'b1;
end
end else if (m_udp_payload_axis_tready) begin
// input is not ready, but output is ready
m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = 1'b0;
store_udp_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_udp_payload_axis_tvalid_reg <= 1'b0;
m_udp_payload_axis_tready_int_reg <= 1'b0;
temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
end
// datapath
if (store_udp_payload_int_to_output) begin
m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end else if (store_udp_payload_axis_temp_to_output) begin
m_udp_payload_axis_tdata_reg <= temp_m_udp_payload_axis_tdata_reg;
m_udp_payload_axis_tlast_reg <= temp_m_udp_payload_axis_tlast_reg;
m_udp_payload_axis_tuser_reg <= temp_m_udp_payload_axis_tuser_reg;
end
if (store_udp_payload_int_to_temp) begin
temp_m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
temp_m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
temp_m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end
end
endmodule |
module to get menu pixels?
update_VGA_RGB(sw);
end
end
// Take in 8 bit color and set VGA colors accordingly
task update_VGA_RGB;
input [7:0] color;
begin
vgaRed = color[7:5];
vgaGreen = color[4:2];
vgaBlue = color[1:0];
end
endtask
/******************************/
/*******Cursor Control*********/
/******************************/
reg [31:0] counter_cursor = 0;
reg clk_cursor = 0; // Ticks at 30 Hz
always @(posedge clk)
begin
counter_cursor <= (counter_cursor == 1666666) ? 0 : counter_cursor + 1;
if (counter_cursor == 0)
clk_cursor <= ~clk_cursor;
end
always @(posedge clk_cursor)
begin
if (joystick_x < 150 && cursorX < drawAreaWidth - 2) cursorX <= cursorX + 2;
else if (joystick_x < 400 && cursorX < drawAreaWidth - 1) cursorX <= cursorX + 1;
if (joystick_x > 850 && cursorX > 2) cursorX <= cursorX - 2;
else if (joystick_x > 600 && cursorX > 1) cursorX <= cursorX - 1;
if (joystick_y < 150 && cursorY > 2) cursorY <= cursorY - 2;
else if (joystick_y < 400 && cursorY > 1) cursorY <= cursorY - 1;
if (joystick_y > 850 && cursorY < drawAreaHeight - 2) cursorY <= cursorY + 2;
else if (joystick_y > 600 && cursorY < drawAreaHeight - 1) cursorY <= cursorY + 1;
end
/******************************/
/********Tool Control**********/
/******************************/
reg [5:0] current_tool = 2;
reg [5:0] old_tool = 0; // Used to go back to current_tool after resetting screen
wire [5:0] TOOL_NONE = 0;
wire [5:0] TOOL_RESET = 1;
wire [5:0] TOOL_PENCIL = 2;
wire [5:0] TOOL_ERASER = 3;
wire [5:0] TOOL_STAMP = 4;
reg is_resetting = 0;
reg is_tool_on = 0;
reg [31:0] reset_counter = 0;
reg [31:0] pencil_size = 4;
reg [31:0] pencil_x = 0;
reg [31:0] pencil_y = 0;
reg [31:0] stamp_size = 30;
reg [31:0] stamp_x = 0;
reg [31:0] stamp_y = 0;
reg [31:0] current_stamp = 4;
reg [31:0] counter_debounce = 0;
wire clk_debounce;
assign clk_debounce = counter_debounce == 166666;
always @(posedge clk)
begin
counter_debounce <= counter_debounce == 166666 ? 0 : counter_debounce + 1;
end
reg btnRdb = 0;
reg btnLdb = 0;
reg btnUdb = 0;
reg btnDdb = 0;
always @(posedge clk_debounce)
begin
btnRdb <= btnR;
btnLdb <= btnL;
btnUdb <= btnU;
btnDdb <= btnD;
end
wire comboLR = btnRdb || btnLdb;
always @(posedge comboLR)
begin
if (btnRdb)
begin
if (current_tool == TOOL_STAMP)
begin
current_stamp <= current_stamp == 6 ? 0 :current_stamp + 1;
end
else
begin
case (pencil_size)
2: pencil_size <= 4;
4: pencil_size <= 6;
endcase
end
end
if (btnLdb)
begin
if (current_tool == TOOL_STAMP)
begin
current_stamp <= current_stamp == 0 ? 6 :current_stamp - 1;
end
else
begin
case (pencil_size)
4: pencil_size <= 2;
6: pencil_size <= 4;
endcase
end
end
end
wire comboUD = btnUdb || btnDdb;
always @(posedge comboUD)
begin
if (btnUdb)
begin
if (current_tool == TOOL_PENCIL) current_tool <= TOOL_STAMP;
if (current_tool == TOOL_ERASER) current_tool <= TOOL_PENCIL;
if (current_tool == TOOL_STAMP) current_tool <= TOOL_ERASER;
end
if (btnDdb)
begin
if (current_tool == TOOL_PENCIL) current_tool <= TOOL_ERASER;
if (current_tool == TOOL_ERASER) current_tool <= TOOL_STAMP;
if (current_tool == TOOL_STAMP) current_tool <= TOOL_PENCIL;
end
end
always @(posedge clk)
begin
// Set current tool
if (btnS && current_tool != TOOL_RESET)
begin
is_resetting <= 1;
reset_counter <= 0;
end
else if (joystick_btn_left)
is_tool_on <= 1;
if (is_resetting)
begin
if (reset_counter == drawAreaWidth * drawAreaHeight)
begin
is_resetting <= 0;
wea <= 0;
end
else
begin
wea <= 1;
dina <= COLOR_WHITE;
pmin_addr <= reset_counter;
reset_counter <= reset_counter + 1;
end
end
if (is_tool_on && current_tool == TOOL_PENCIL)
begin
if (pencil_y == pencil_size)
begin
is_tool_on <= 0;
wea <= 0;
pencil_x <= 0;
pencil_y <= 0;
end
else
begin
wea <= 1;
dina <= sw;
pmin_addr <= (cursorX + pencil_x - pencil_size / 2) + (cursorY + pencil_y - pencil_size / 2) * drawAreaWidth;
if (pencil_x == pencil_size - 1)
begin
pencil_x <= 0;
pencil_y <= pencil_y + 1;
end
else
pencil_x <= pencil_x + 1;
end
end
if (is_tool_on && current_tool == TOOL_ERASER)
begin
if (pencil_y == pencil_size)
begin
is_tool_on <= 0;
wea <= 0;
pencil_x <= 0;
pencil_y <= 0;
end
else
begin
wea <= 1;
dina <= COLOR_WHITE;
pmin_addr <= (cursorX + pencil_x - pencil_size / 2) + (cursorY + pencil_y - pencil_size / 2) * drawAreaWidth;
if (pencil_x == pencil_size - 1)
begin
pencil_x <= 0;
pencil_y <= pencil_y + 1;
end
else
pencil_x <= pencil_x + 1;
end
end
if (is_tool_on && current_tool == TOOL_STAMP)
begin
if (stamp_y == stamp_size)
begin
is_tool_on <= 0;
wea <= 0;
stamp_x <= 0;
stamp_y <= 0;
stamp_draw_addr <= 0;
end
else
begin
stamp_draw_addr <= (stamp_x + (stamp_y * stamp_size));
wea <= stamp_draw_pixel != 8'b00000011;
dina <= stamp_draw_pixel;
pmin_addr <= (cursorX + stamp_x - stamp_size / 2) + (cursorY + stamp_y - stamp_size / 2) * drawAreaWidth;
if (stamp_x == stamp_size)
begin
stamp_x <= 0;
stamp_y <= stamp_y + 1;
end
else
stamp_x <= stamp_x + 1;
end
end
end
/******************************/
/*********Pixel Map ***********/
/******************************/
reg [15:0] pmop_addr;
wire [7:0] pmop_pixel;
reg wea;
reg [15 : 0] pmin_addr;
reg [7 : 0] dina;
pixel_map pixel_map(
.clka(clk), // input clka
.wea(wea), // input [0 : 0] wea
.addra(pmin_addr), // input [15 : 0] addra
.dina(dina), // input [7 : 0] dina
.clkb(clk), // input clkb
.addrb(pmop_addr), // input [15 : 0] addrb
.doutb(pmop_pixel) // output [7 : 0] doutb
);
reg [9:0] stamp_draw_addr = 0;
wire [7:0] stamp_draw_pixel;
reg [9:0] stamp_menu_addr = 0;
wire [7:0] stamp_menu_pixel;
assign stamp_draw_pixel =
current_stamp == 0 ? stamp_draw_pixel_0 :
current_stamp == 1 ? stamp_draw_pixel_1 :
current_stamp == 2 ? stamp_draw_pixel_2 :
current_stamp == 3 ? stamp_draw_pixel_3 :
current_stamp == 4 ? stamp_draw_pixel_4 :
current_stamp == 5 ? stamp_draw_pixel_5 : stamp_draw_pixel_6;
assign stamp_menu_pixel =
current_stamp == 0 ? stamp_menu_pixel_0 :
current_stamp == 1 ? stamp_menu_pixel_1 :
current_stamp == 2 ? stamp_menu_pixel_2 :
current_stamp == 3 ? stamp_menu_pixel_3 :
current_stamp == 4 ? stamp_menu_pixel_4 :
current_stamp == 5 ? stamp_menu_pixel_5 : stamp_menu_pixel_6;
wire [7:0] stamp_draw_pixel_0;
wire [7:0] stamp_menu_pixel_0;
stamp_matt stamp0 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_0), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_0) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_1;
wire [7:0] stamp_menu_pixel_1;
stamp_penguin stamp1 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_1), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_1) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_2;
wire [7:0] stamp_menu_pixel_2;
stamp_jellyfish stamp2 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_2), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_2) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_3;
wire [7:0] stamp_menu_pixel_3;
stamp_cat stamp3 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_3), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_3) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_4;
wire [7:0] stamp_menu_pixel_4;
stamp_taco stamp4 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_4), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_4) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_5;
wire [7:0] stamp_menu_pixel_5;
stamp_mushroom stamp5 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_5), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_5) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_6;
wire [7:0] stamp_menu_pixel_6;
stamp_heart stamp6 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_6), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_6) // output [7 : 0] doutb
);
/******************************/
/*********Joystick ***********/
/******************************/
wire SS; // Active low
wire MOSI; // Data transfer from master to slave
wire SCLK; // Serial clock that controls communication
assign MOSI = 0;
// Data read from PmodJSTK
wire [39:0] jstkData;
wire [9 : 0] joystick_y = {jstkData[9:8], jstkData[23:16]};
wire [9 : 0] joystick_x = {jstkData[25:24], jstkData[39:32]};
wire joystick_btn_right = jstkData[1];
wire joystick_btn_left = jstkData[2];
joy joy(
.CLK(clk),
.sndRec(clk_cursor),
.MISO(MISO),
.SS(SS),
.SCLK(SCLK),
.DOUT(jstkData)
);
endmodule |
module probador(
output reg SD_CLK,
output reg RESET_L,
output reg strobe_IN_DATA_Phy,
output reg ack_IN_DATA_Phy,
output reg [15:0] timeout_Reg_DATA_Phy,
output reg [3:0] blocks_DATA_Phy,
output reg writeRead_DATA_Phy,
output reg multiple_DATA_Phy,
output reg idle_in_DATA_Phy,
output reg transmission_complete_PS_Phy,
output reg reception_complete_SP_Phy,
output reg [31:0] data_read_SP_Phy,
output reg [31:0] dataFromFIFO_FIFO_Phy
);
// Generar CLK
always
begin
#10 SD_CLK= ! SD_CLK;
end
//Generar pruebas
initial begin
//dumps
$dumpfile("PhysicalTest.vcd");
$dumpvars(0,testbench);
// Initialize Inputs
SD_CLK = 0;
writeRead_DATA_Phy = 1;
strobe_IN_DATA_Phy = 1;
ack_IN_DATA_Phy = 0;
timeout_Reg_DATA_Phy = 16'd100;
blocks_DATA_Phy = 4'b1111;
multiple_DATA_Phy = 0;
idle_in_DATA_Phy = 0;
transmission_complete_PS_Phy = 0;
reception_complete_SP_Phy = 0;
data_read_SP_Phy = 32'hCAFECAFE;
dataFromFIFO_FIFO_Phy = 32'hCAFECAFE;
//pulso de RESET_L
#50
RESET_L = 1;
#10
RESET_L = 0;
#30
RESET_L = 1;
//Aqui ya pasa a IDLE
$display("Aqui ya pasa a IDLE");
//pasamos a fifo read
//pasamos al estado LOAD write
$display("Aqui ya pasa a load write, luego a send y wait response");
#100
reception_complete_SP_Phy = 1;
#30
ack_IN_DATA_Phy = 1;
$display("manda el ack y devuelta a IDLE");
#200
$display("-----FIN------");
$finish(2);
end
endmodule |
module design_1_wrapper
(AXI_En,
En,
FrameSize,
M_AXIS_tdata,
M_AXIS_tlast,
M_AXIS_tready,
M_AXIS_tstrb,
M_AXIS_tvalid,
S_AXIS_tdata,
S_AXIS_tlast,
S_AXIS_tready,
S_AXIS_tstrb,
S_AXIS_tvalid,
m_axis_aclk,
m_axis_aresetn);
input AXI_En;
input En;
input [7:0]FrameSize;
output [31:0]M_AXIS_tdata;
output M_AXIS_tlast;
input M_AXIS_tready;
output [3:0]M_AXIS_tstrb;
output M_AXIS_tvalid;
input [31:0]S_AXIS_tdata;
input S_AXIS_tlast;
output S_AXIS_tready;
input [3:0]S_AXIS_tstrb;
input S_AXIS_tvalid;
input m_axis_aclk;
input m_axis_aresetn;
wire AXI_En;
wire En;
wire [7:0]FrameSize;
wire [31:0]M_AXIS_tdata;
wire M_AXIS_tlast;
wire M_AXIS_tready;
wire [3:0]M_AXIS_tstrb;
wire M_AXIS_tvalid;
wire [31:0]S_AXIS_tdata;
wire S_AXIS_tlast;
wire S_AXIS_tready;
wire [3:0]S_AXIS_tstrb;
wire S_AXIS_tvalid;
wire m_axis_aclk;
wire m_axis_aresetn;
design_1 design_1_i
(.AXI_En(AXI_En),
.En(En),
.FrameSize(FrameSize),
.M_AXIS_tdata(M_AXIS_tdata),
.M_AXIS_tlast(M_AXIS_tlast),
.M_AXIS_tready(M_AXIS_tready),
.M_AXIS_tstrb(M_AXIS_tstrb),
.M_AXIS_tvalid(M_AXIS_tvalid),
.S_AXIS_tdata(S_AXIS_tdata),
.S_AXIS_tlast(S_AXIS_tlast),
.S_AXIS_tready(S_AXIS_tready),
.S_AXIS_tstrb(S_AXIS_tstrb),
.S_AXIS_tvalid(S_AXIS_tvalid),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn));
endmodule |
module sky130_fd_sc_ms__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module hrfp_normalize
#(parameter PIPELINESTAGES=5)
(input wire clk,
input wire [`MSBBIT:0] result_4,
input wire [30:0] mantissa_4,
input wire [7:0] zeroesmask_4,
output reg [30:0] mantissa_5,
output reg [`MSBBIT:0] result_5);
(* KEEP = "SOFT" *) reg [7:0] zeroes;
(* KEEP = "SOFT" *) reg [2:0] expdiff;
(* KEEP = "SOFT" *) reg [1:0] expdiff_mux0;
(* KEEP = "SOFT" *) reg [1:0] expdiff_mux1;
reg expdiff_carryin;
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp0 = (mantissa_4[30:25] == 6'b011111);
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp1 = (mantissa_4[24:19] == 6'b111111);
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp2 = (mantissa_4[18:13] == 6'b111111);
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp3 = (mantissa_4[12:7] == 6'b111111);
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp4 = (mantissa_4[6:1] == 6'b111111);
wire rounding_will_overflow_tmp5 = (mantissa_4[0] == 1'b1);
(* KEEP = "SOFT" *) wire rounding_will_overflow = rounding_will_overflow_tmp0 &&
rounding_will_overflow_tmp1 &&
rounding_will_overflow_tmp2 &&
rounding_will_overflow_tmp3 &&
rounding_will_overflow_tmp4 &&
rounding_will_overflow_tmp5;
wire overflow_bit = mantissa_4[30];
initial begin
$display("ERROR ERROR ERROR: This file is deprecated and only kept for historical reasons.");
$stop;
end
/*
rounding_will_overflow = 0;
if(mantissa_4[30:5] == 26'h1ffffff) begin
rounding_will_overflow = 1;
end
*/
// (* KEEP = "SOFT" *) reg iszero;
(* KEEP = "SOFT" *) wire iszero = (mantissa_4 == 0);
always @* begin
zeroes[0] = ~|mantissa_4[1:0] && zeroesmask_4[0];
zeroes[1] = ~|mantissa_4[5:2] && zeroesmask_4[1];
zeroes[2] = ~|mantissa_4[9:6] && zeroesmask_4[2];
zeroes[3] = ~|mantissa_4[13:10] && zeroesmask_4[3];
zeroes[4] = ~|mantissa_4[17:14] && zeroesmask_4[4];
zeroes[5] = ~|mantissa_4[21:18] && zeroesmask_4[5];
zeroes[6] = ~|mantissa_4[25:22] && zeroesmask_4[6];
zeroes[7] = ~|mantissa_4[29:26] && zeroesmask_4[7]; // 8 LUTs (confirmed!)
// iszero = 0;
expdiff = 0;
// if(zeroes == 8'b11111111) begin
// iszero = 1;
// end
casez(zeroes)
8'b1111111?: expdiff = 3'b111; // No need to check for 8'b11111111 since iszero is one in that case!
8'b1111110?: expdiff = 3'b110;
8'b111110??: expdiff = 3'b101;
8'b11110???: expdiff = 3'b100;
8'b1110????: expdiff = 3'b011;
8'b110?????: expdiff = 3'b010;
8'b10??????: expdiff = 3'b001;
8'b0???????: expdiff = 3'b000;
endcase // casez (zeroes) // 4 LUTs (?)
casez({overflow_bit,zeroes[3:0]})
5'b1????: expdiff_mux1 = 3;
5'b0111?: expdiff_mux1 = 3;
5'b0110?: expdiff_mux1 = 2;
5'b010??: expdiff_mux1 = 1;
5'b00???: expdiff_mux1 = 0;
endcase // casez (zeroes) // 4 LUTs (?)
casez(zeroes[7:4])
4'b111?: expdiff_mux0 = 3;
4'b110?: expdiff_mux0 = 2;
4'b10??: expdiff_mux0 = 1;
4'b0???: expdiff_mux0 = 0;
endcase // casez (zeroes) // 4 LUTs (?)
expdiff_carryin = overflow_bit;
// if(mantissa_4[30] ) begin
// expdiff = 0; // In this case, expdiff will be ignored.
// end
// In the code below, 30:5 is used to check for rounded
// overflow. expdiff_carryin will be of course be set in this
// case as well. (Both because mantissa_4[30] is set
// (c.f. above) and because the following condition is true.
if(mantissa_4[29:5] == 25'h1ffffff) begin
// expdiff = 0; // Expdiff value doesn't matter in this case!
expdiff_carryin = 1;
end
end // always @ *
(* KEEP = "SOFT" *) reg [30:0] mantissa_mux_0,mantissa_mux_1;
wire [30:0] mantissa_shifted;
wire [30:0] overflow_mantissa = {3'b000, mantissa_4[30:5], |mantissa_4[4:0]};
wire [30:0] overflow_or_normal_mantissa = overflow_bit ? overflow_mantissa : {mantissa_4[1:0], 28'b0};
always @* begin
case(expdiff_mux1[1:0])
3: mantissa_mux_1 = overflow_mantissa; // Corresponds to expdiff = 7
2: mantissa_mux_1 = {mantissa_4[5:0], 24'b0}; // Corresponds to expdiff = 6
1: mantissa_mux_1 = {mantissa_4[9:0], 20'b0}; // Corresponds to expdiff = 5
0: mantissa_mux_1 = {mantissa_4[13:0], 16'b0}; // Corresponds to expdiff = 4
endcase // case (expdiff[1:0])
case(expdiff_mux0[1:0])
3: mantissa_mux_0 = {mantissa_4[17:0], 12'b0}; // Corresponds to expdiff = 3
2: mantissa_mux_0 = {mantissa_4[21:0], 8'b0}; // Corresponds to expdiff = 2
1: mantissa_mux_0 = {mantissa_4[25:0], 4'b0}; // Corresponds to expdiff = 1
0: mantissa_mux_0 = {mantissa_4[29:0]}; // Corresponds to expdiff = 0
endcase // casez (expdiff[1:0])
end // always @ *
/*
// FIXME - very wasteful since this mux is only needed in a few
// cases due to the large number of zeroes in the expression above.
generate
genvar i;
for(i=0; i <= 30; i = i + 1) begin : f7mux
MUXF7 f7(.I0(mantissa_mux_0[i]),
.I1(mantissa_mux_1[i]),
.S(expdiff[2]),
.O(mantissa_shifted[i]));
end
endgenerate
*/
assign mantissa_shifted = (expdiff[2] || overflow_bit) ? mantissa_mux_1 : mantissa_mux_0;
wire [`EXPONENTBITS:0] expdiff_tmp = expdiff_carryin ? 8'b11111111 : expdiff;
always @(posedge clk) begin
result_5 <= result_4;
// $display("Zeroes is %x", zeroes);
// Note: the case where zeroes == 8'b11111111 is handled implicitly since
// the mantissa is all zero in this case. (That is, mantissa_5 will be set to 0,
// regardless of the setting of expdiff!)
// casez (expdiff)
// 7: mantissa_5 <= {mantissa_4[1:0], 28'b0};
// 6: mantissa_5 <= {mantissa_4[5:0], 24'b0};
// 5: mantissa_5 <= {mantissa_4[9:0], 20'b0};
// 4: mantissa_5 <= {mantissa_4[13:0], 16'b0};
// 3: mantissa_5 <= {mantissa_4[17:0], 12'b0};
// 2: mantissa_5 <= {mantissa_4[21:0], 8'b0};
// 1: mantissa_5 <= {mantissa_4[25:0], 4'b0};
// 0: mantissa_5 <= {mantissa_4[29:0]};
// endcase // casez (zeroes)
mantissa_5 <= mantissa_shifted;
// 4-1 mux: 1 LUT
// 8-1 mux: 2 LUT
// 31 bit 8-1 mux: 62 LUTs (less due to use of reset input!)
// This is the same as the statement above but tweaked so that we hopefully get only one adder.
result_5`EXPONENT <= result_4`EXPONENT - expdiff_tmp;
// if(iszero) result_5`EXPSPEC <= 0;
// if(overflow_bit) begin
// result_5`EXPONENT <= result_4`EXPONENT + 1; // This might also overflow but is also handled below during overflow check.
// mantissa_5 <= {3'b000, mantissa_4[30:5], |mantissa_4[4:0] }; // Oops, a 9-1 mux!
// end
// Detect if rounding operation will overflow!
// Note: Since this is an odd number there is no need to check/generate sticky bit (e.g. |mantissa_4[4:0]
if(rounding_will_overflow) begin
mantissa_5 <= {4'b0001, 26'h0}; // Reset/Set input could be used for this...
// result_5`EXPONENT <= result_4`EXPONENT + 1; // Might overflow but this is handled below during the overflow check where the INF bit will be set.
end
// OVERFLOW!
if(result_4`EXPONENT == 63+8'b01000000) begin
// A thorough testing is needed to determine if this works correctly or not.
if(mantissa_4[29] && !result_4`SPECIAL) begin
result_5`IS_INF_OR_NAN <= 1;
result_5`HRFP_IS_NAN <= 0;
end
end
end // always @ (posedge clk)
endmodule |
module psdos (
input Rx,
input CLKOUT,
output reg Rx_error,
output [7:0] DATA,
output reg DONE
);
reg [8:0] regis;
reg [7:0] regis0;
reg [3:0] i;
reg [3:0] j;
reg [1:0] k;
reg init;
reg DoIt;
//reg NoDoIt;
//reg MakeIt=(DoIt && ~NoDoIt);
initial
begin
i=0;
j=0;
init=0;
regis=0;
regis0=0;
Rx_error=0;
DONE=0;
k=0;
DoIt=1;
//NoDoIt=0;
end
always@(posedge CLKOUT)
begin
if(!Rx&&!i)
begin
init<=1;
DONE=0;
Rx_error=0;
end
// lectura //
// lectura //
// lectura //
if(init)
begin
regis[i]=Rx;
i<=i+1;
if(regis[i]&&(i<8))
begin
j=j+1;
end
end
//=======
if(DoIt)
begin
k<=k+1;
end
//=======
// finalizar //
// finalizar //
// finalizar //
if(i==9)
begin
if(((j%2)&&(regis[8]))||(!(j%2)&&(!regis[8])))
begin
Rx_error=0;
regis0={regis[7:0]};
DONE=1;
end
else
begin
Rx_error=1;
regis0=0;
DONE=0;
end
j=0;
i<=0;
init=0;
end
end
assign DATA=regis0;
endmodule |
module sky130_fd_sc_hdll__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule |
module sky130_fd_sc_hdll__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule |
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.EXPORT_JTAG (0),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // input, width = 1, clock.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // output, width = 8, src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // output, width = 1, .valid
.sink_data (p2b_out_bytes_stream_data), // input, width = 8, sink.data
.sink_valid (p2b_out_bytes_stream_valid), // input, width = 1, .valid
.sink_ready (p2b_out_bytes_stream_ready), // output, width = 1, .ready
.resetrequest (master_reset_reset), // output, width = 1, resetrequest.reset
.source_ready (1'b1), // (terminated),
.mgmt_valid (), // (terminated),
.mgmt_channel (), // (terminated),
.mgmt_data (), // (terminated),
.jtag_tck (1'b0), // (terminated),
.jtag_tms (1'b0), // (terminated),
.jtag_tdi (1'b0), // (terminated),
.jtag_tdo (), // (terminated),
.jtag_ena (1'b0), // (terminated),
.jtag_usr1 (1'b0), // (terminated),
.jtag_clr (1'b0), // (terminated),
.jtag_clrn (1'b0), // (terminated),
.jtag_state_tlr (1'b0), // (terminated),
.jtag_state_rti (1'b0), // (terminated),
.jtag_state_sdrs (1'b0), // (terminated),
.jtag_state_cdr (1'b0), // (terminated),
.jtag_state_sdr (1'b0), // (terminated),
.jtag_state_e1dr (1'b0), // (terminated),
.jtag_state_pdr (1'b0), // (terminated),
.jtag_state_e2dr (1'b0), // (terminated),
.jtag_state_udr (1'b0), // (terminated),
.jtag_state_sirs (1'b0), // (terminated),
.jtag_state_cir (1'b0), // (terminated),
.jtag_state_sir (1'b0), // (terminated),
.jtag_state_e1ir (1'b0), // (terminated),
.jtag_state_pir (1'b0), // (terminated),
.jtag_state_e2ir (1'b0), // (terminated),
.jtag_state_uir (1'b0), // (terminated),
.jtag_ir_in (3'b000), // (terminated),
.jtag_irq (), // (terminated),
.jtag_ir_out () // (terminated),
);
ghrd_10as066n2_fpga_m_timing_adapter_171_xf5weri timing_adt (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // input, width = 8, in.data
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // input, width = 1, .valid
.out_data (timing_adt_out_data), // output, width = 8, out.data
.out_valid (timing_adt_out_valid), // output, width = 1, .valid
.out_ready (timing_adt_out_ready) // input, width = 1, .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // input, width = 1, clk.clk
.reset (rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset
.in_data (timing_adt_out_data), // input, width = 8, in.data
.in_valid (timing_adt_out_valid), // input, width = 1, .valid
.in_ready (timing_adt_out_ready), // output, width = 1, .ready
.out_data (fifo_out_data), // output, width = 8, out.data
.out_valid (fifo_out_valid), // output, width = 1, .valid
.out_ready (fifo_out_ready), // input, width = 1, .ready
.csr_address (2'b00), // (terminated),
.csr_read (1'b0), // (terminated),
.csr_write (1'b0), // (terminated),
.csr_readdata (), // (terminated),
.csr_writedata (32'b00000000000000000000000000000000), // (terminated),
.almost_full_data (), // (terminated),
.almost_empty_data (), // (terminated),
.in_startofpacket (1'b0), // (terminated),
.in_endofpacket (1'b0), // (terminated),
.out_startofpacket (), // (terminated),
.out_endofpacket (), // (terminated),
.in_empty (1'b0), // (terminated),
.out_empty (), // (terminated),
.in_error (1'b0), // (terminated),
.out_error (), // (terminated),
.in_channel (1'b0), // (terminated),
.out_channel () // (terminated),
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // output, width = 8, out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // input, width = 1, .ready
.out_valid (b2p_out_packets_stream_valid), // output, width = 1, .valid
.out_data (b2p_out_packets_stream_data), // output, width = 8, .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // output, width = 1, .endofpacket
.in_ready (fifo_out_ready), // output, width = 1, in_bytes_stream.ready
.in_valid (fifo_out_valid), // input, width = 1, .valid
.in_data (fifo_out_data) // input, width = 8, .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // output, width = 1, in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // input, width = 1, .valid
.in_data (p2b_adapter_out_data), // input, width = 8, .data
.in_channel (p2b_adapter_out_channel), // input, width = 8, .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // input, width = 1, .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // input, width = 1, out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // output, width = 1, .valid
.out_data (p2b_out_bytes_stream_data) // output, width = 8, .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // input, width = 1, out_stream.ready
.out_valid (transacto_out_stream_valid), // output, width = 1, .valid
.out_data (transacto_out_stream_data), // output, width = 8, .data
.out_startofpacket (transacto_out_stream_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // output, width = 1, .endofpacket
.in_ready (b2p_adapter_out_ready), // output, width = 1, in_stream.ready
.in_valid (b2p_adapter_out_valid), // input, width = 1, .valid
.in_data (b2p_adapter_out_data), // input, width = 8, .data
.in_startofpacket (b2p_adapter_out_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // input, width = 1, .endofpacket
.address (master_address), // output, width = 32, avalon_master.address
.readdata (master_readdata), // input, width = 32, .readdata
.read (master_read), // output, width = 1, .read
.write (master_write), // output, width = 1, .write
.writedata (master_writedata), // output, width = 32, .writedata
.waitrequest (master_waitrequest), // input, width = 1, .waitrequest
.readdatavalid (master_readdatavalid), // input, width = 1, .readdatavalid
.byteenable (master_byteenable) // output, width = 4, .byteenable
);
ghrd_10as066n2_fpga_m_channel_adapter_171_2swajja b2p_adapter (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
.in_data (b2p_out_packets_stream_data), // input, width = 8, in.data
.in_valid (b2p_out_packets_stream_valid), // input, width = 1, .valid
.in_ready (b2p_out_packets_stream_ready), // output, width = 1, .ready
.in_startofpacket (b2p_out_packets_stream_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // input, width = 1, .endofpacket
.in_channel (b2p_out_packets_stream_channel), // input, width = 8, .channel
.out_data (b2p_adapter_out_data), // output, width = 8, out.data
.out_valid (b2p_adapter_out_valid), // output, width = 1, .valid
.out_ready (b2p_adapter_out_ready), // input, width = 1, .ready
.out_startofpacket (b2p_adapter_out_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // output, width = 1, .endofpacket
);
ghrd_10as066n2_fpga_m_channel_adapter_171_vh2yu6y p2b_adapter (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
.in_data (transacto_out_stream_data), // input, width = 8, in.data
.in_valid (transacto_out_stream_valid), // input, width = 1, .valid
.in_ready (transacto_out_stream_ready), // output, width = 1, .ready
.in_startofpacket (transacto_out_stream_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // input, width = 1, .endofpacket
.out_data (p2b_adapter_out_data), // output, width = 8, out.data
.out_valid (p2b_adapter_out_valid), // output, width = 1, .valid
.out_ready (p2b_adapter_out_ready), // input, width = 1, .ready
.out_startofpacket (p2b_adapter_out_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // output, width = 1, .endofpacket
.out_channel (p2b_adapter_out_channel) // output, width = 8, .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // input, width = 1, reset_in0.reset
.clk (clk_clk), // input, width = 1, clk.clk
.reset_out (rst_controller_reset_out_reset), // output, width = 1, reset_out.reset
.reset_req (), // (terminated),
.reset_req_in0 (1'b0), // (terminated),
.reset_in1 (1'b0), // (terminated),
.reset_req_in1 (1'b0), // (terminated),
.reset_in2 (1'b0), // (terminated),
.reset_req_in2 (1'b0), // (terminated),
.reset_in3 (1'b0), // (terminated),
.reset_req_in3 (1'b0), // (terminated),
.reset_in4 (1'b0), // (terminated),
.reset_req_in4 (1'b0), // (terminated),
.reset_in5 (1'b0), // (terminated),
.reset_req_in5 (1'b0), // (terminated),
.reset_in6 (1'b0), // (terminated),
.reset_req_in6 (1'b0), // (terminated),
.reset_in7 (1'b0), // (terminated),
.reset_req_in7 (1'b0), // (terminated),
.reset_in8 (1'b0), // (terminated),
.reset_req_in8 (1'b0), // (terminated),
.reset_in9 (1'b0), // (terminated),
.reset_req_in9 (1'b0), // (terminated),
.reset_in10 (1'b0), // (terminated),
.reset_req_in10 (1'b0), // (terminated),
.reset_in11 (1'b0), // (terminated),
.reset_req_in11 (1'b0), // (terminated),
.reset_in12 (1'b0), // (terminated),
.reset_req_in12 (1'b0), // (terminated),
.reset_in13 (1'b0), // (terminated),
.reset_req_in13 (1'b0), // (terminated),
.reset_in14 (1'b0), // (terminated),
.reset_req_in14 (1'b0), // (terminated),
.reset_in15 (1'b0), // (terminated),
.reset_req_in15 (1'b0) // (terminated),
);
endmodule |
module vga_bw
(
CLOCK_PIXEL,
RESET,
PIXEL,
PIXEL_H,
PIXEL_V,
VGA_RED,
VGA_GREEN,
VGA_BLUE,
VGA_HS,
VGA_VS
);
input CLOCK_PIXEL;
input RESET;
input PIXEL; // black (0) or white (1)
output [10:0] PIXEL_H;
output [10:0] PIXEL_V;
output VGA_RED;
output VGA_GREEN;
output VGA_BLUE;
output VGA_HS;
output VGA_VS;
/* Internal registers for horizontal signal timing */
reg [10:0] hor_reg; // to count up to 975
reg [10:0] hor_pixel; // the next pixel
reg hor_sync;
wire hor_max = (hor_reg == 975); // to tell when a line is full
/* Internal registers for vertical signal timing */
reg [9:0] ver_reg; // to count up to 527
reg [10:0] ver_pixel; // the next pixel
reg ver_sync;
reg red, green, blue;
wire ver_max = (ver_reg == 527); // to tell when a line is full
// visible pixel counter
//reg [15:0] visible_pixel;
/* Running through line */
always @ (posedge CLOCK_PIXEL or posedge RESET) begin
if (RESET) begin
hor_reg <= 0;
ver_reg <= 0;
end
else if (hor_max) begin
hor_reg <= 0;
/* Running through frame */
if (ver_max) begin
ver_reg <= 0;
end else begin
ver_reg <= ver_reg + 1;
end
end else begin
hor_reg <= hor_reg + 1;
end
end
always @ (posedge CLOCK_PIXEL or posedge RESET) begin
if (RESET) begin
hor_sync <= 0;
ver_sync <= 0;
red <= 0;
green <= 0;
blue <= 0;
hor_pixel <= 0;
ver_pixel <= 0;
end
else begin
/* Generating the horizontal sync signal */
if (hor_reg == 840) begin // video (800) + front porch (40)
hor_sync <= 1; // turn on horizontal sync pulse
end else if (hor_reg == 928) begin // video (800) + front porch (40) + Sync Pulse (88)
hor_sync <= 0; // turn off horizontal sync pulse
end
/* Generating the vertical sync signal */
if (ver_reg == 493) begin // LINES: video (480) + front porch (13)
ver_sync <= 1; // turn on vertical sync pulse
end else if (ver_reg == 496) begin // LINES: video (480) + front porch (13) + Sync Pulse (3)
ver_sync <= 0; // turn off vertical sync pulse
end
// black during the porches
if (ver_reg > 480 || hor_reg > 800) begin
red <= 0;
green <= 0;
blue <= 0;
if (ver_reg > 480) begin
ver_pixel <= 0;
end
if (hor_reg > 800) begin
hor_pixel <= 0;
end
end
else begin
hor_pixel <= hor_reg;
ver_pixel <= ver_reg;
// Draw the pixel.
if (PIXEL) begin
// white
red <= 1;
green <= 1;
blue <= 1;
end
else begin
// black
red <= 0;
green <= 0;
blue <= 0;
end
end
end
end
// Send the sync signals to the output.
assign VGA_HS = hor_sync;
assign VGA_VS = ver_sync;
assign VGA_RED = red;
assign VGA_GREEN = green;
assign VGA_BLUE = blue;
assign PIXEL_H = hor_pixel;
assign PIXEL_V = ver_pixel;
endmodule |
module HallwayRight(clk_vga, CurrentX, CurrentY, mapData, wall);
input clk_vga;
input [9:0]CurrentX;
input [8:0]CurrentY;
input [7:0]wall;
output [7:0]mapData;
reg [7:0]mColor;
always @(posedge clk_vga) begin
//Top walls
if((CurrentY < 40) && ~(CurrentX < 0)) begin
mColor[7:0] <= wall;
end
//Right side wall
else if(~(CurrentX < 600)) begin
mColor[7:0] <= wall;
end
//Bottom wall
else if((~(CurrentY < 440) && (CurrentX < 260)) || (~(CurrentY < 440) && ~(CurrentX < 380))) begin
mColor[7:0] <= wall;
//floor area - grey
end else
mColor[7:0] <= 8'b10110110;
end
assign mapData = mColor;
endmodule |
module OUTPUT_CTL(
clk,
reset,
in_egress_pkt_wr,
in_egress_pkt,
in_egress_pkt_valid_wr,
in_egress_pkt_valid,
out_egress_pkt_almostfull,
out_slot0_pkt,
out_slot0_pkt_wr,
out_slot0_pkt_valid,
out_slot0_pkt_valid_wr,
in_slot0_pkt_almostfull,
out_slot1_pkt,
out_slot1_pkt_wr,
out_slot1_pkt_valid,
out_slot1_pkt_valid_wr,
in_slot1_pkt_almostfull,
output_receive_pkt_add,
output_discard_error_pkt_add,
output_send_slot0_pkt_add,
output_send_slot1_pkt_add
);
input clk;
input reset;
input in_egress_pkt_wr;
input [133:0] in_egress_pkt;
input in_egress_pkt_valid_wr;
input in_egress_pkt_valid;
output wire out_egress_pkt_almostfull;
output reg [133:0] out_slot0_pkt;
output reg out_slot0_pkt_wr;
output reg out_slot0_pkt_valid;
output reg out_slot0_pkt_valid_wr;
input in_slot0_pkt_almostfull;
output reg [133:0] out_slot1_pkt;
output reg out_slot1_pkt_wr;
output reg out_slot1_pkt_valid;
output reg out_slot1_pkt_valid_wr;
input in_slot1_pkt_almostfull;
output reg output_receive_pkt_add;
output reg output_discard_error_pkt_add;
output reg output_send_slot0_pkt_add;
output reg output_send_slot1_pkt_add;
reg [2:0] xaui_channel;
reg [2:0] current_state;//transmit processed pkt to 4 paths by the outport in the metadata of pkt
parameter idle_s = 3'b000,
discard_s = 3'b001,
transmit_s = 3'b010,
wait_s = 3'b011,
pkt_cut_s = 3'b100;
always@(posedge clk or negedge reset)
if(!reset)
begin
out_slot0_pkt_wr <= 1'b0;
out_slot0_pkt <= 134'b0;
out_slot0_pkt_valid_wr <= 1'b0;
out_slot0_pkt_valid <= 1'b0;
out_slot1_pkt_wr <= 1'b0;
out_slot1_pkt <= 134'b0;
out_slot1_pkt_valid_wr <= 1'b0;
out_slot1_pkt_valid <= 1'b0;
in_egress_pkt_valid_rd <= 1'b0;
in_egress_pkt_rd <= 1'b0;
xaui_channel <= 3'b0;//slot ID
output_receive_pkt_add <= 1'b0;
output_discard_error_pkt_add <= 1'b0;
output_send_slot0_pkt_add <= 1'b0;
output_send_slot1_pkt_add <= 1'b0;
current_state <= idle_s;
end
else
begin
case(current_state)
idle_s:begin//judge and poll pkt from pcietx and iace fifo,and reverse order metadata
out_slot0_pkt_wr <= 1'b0;
out_slot0_pkt <= 134'b0;
out_slot0_pkt_valid_wr <= 1'b0;
out_slot0_pkt_valid <= 1'b0;
out_slot1_pkt_wr <= 1'b0;
out_slot1_pkt <= 134'b0;
out_slot1_pkt_valid_wr <= 1'b0;
out_slot1_pkt_valid <= 1'b0;
output_discard_error_pkt_add <= 1'b0;
output_send_slot0_pkt_add <= 1'b0;
output_send_slot1_pkt_add <= 1'b0;
if(in_egress_pkt_valid_empty == 1'b0) begin//judge and poll pkt from pcietx and iace fifo
if(in_egress_pkt_valid_q == 1'b1) begin
if(in_egress_pkt_q[110] == 1'b0) begin//SLOTid
if(in_slot0_pkt_almostfull == 1'b1) begin
current_state <= idle_s;
end
else begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
xaui_channel <= in_egress_pkt_q[112:110];//slot ID
output_receive_pkt_add <= 1'b1;
current_state <= transmit_s;
end
end
else begin
if(in_slot1_pkt_almostfull == 1'b1) begin
current_state <= idle_s;
end
else begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
xaui_channel <= in_egress_pkt_q[112:110];
output_receive_pkt_add <= 1'b1;
current_state <= transmit_s;
end
end
end
else begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
current_state <= discard_s;
end
end
else
current_state <= idle_s;
end
discard_s:begin//discard the error pkt from pcietx
in_egress_pkt_valid_rd <= 1'b0;
if(in_egress_pkt_q[133:132]==2'b10)
begin
output_discard_error_pkt_add <= 1'b1;
in_egress_pkt_rd <= 1'b0;
current_state <= idle_s;
end
else
begin
current_state<= discard_s;
end
end
transmit_s:begin//transmit pkt body from pcietx
output_receive_pkt_add <= 1'b0;
in_egress_pkt_valid_rd <= 1'b0;
case(xaui_channel[2:0])//slot
3'b000:begin
out_slot0_pkt_wr <=1'b1;
out_slot0_pkt <= in_egress_pkt_q;
if(in_egress_pkt_q[133:132]==2'b10)//pkt tail
begin
in_egress_pkt_rd <= 1'b0;
out_slot0_pkt_valid_wr <= 1'b1;
output_send_slot0_pkt_add <= 1'b1;
out_slot0_pkt_valid <= 1'b1;
current_state<= idle_s;
end
else//pkt head and pkt middle
begin
in_egress_pkt_rd <= 1'b1;
current_state<= transmit_s;
end
end
3'b001:begin
out_slot1_pkt_wr <=1'b1;
out_slot1_pkt <=in_egress_pkt_q;
if(in_egress_pkt_q[133:132]==2'b10)//pkt tail
begin
in_egress_pkt_rd <= 1'b0;
out_slot1_pkt_valid_wr <= 1'b1;
output_send_slot1_pkt_add <= 1'b1;
out_slot1_pkt_valid <= 1'b1;
current_state <= idle_s;
end
else//pkt head and pkt middle
begin
in_egress_pkt_rd <=1'b1;
current_state<= transmit_s;
end
end
endcase
end
endcase
end
wire [7:0] in_egress_pkt_usedw;
assign out_egress_pkt_almostfull = in_egress_pkt_usedw[7];
reg in_egress_pkt_rd;
wire [133:0] in_egress_pkt_q;
fifo_256_134 egress_pkt(
.aclr(!reset),
.clock(clk),
.data(in_egress_pkt),
.rdreq(in_egress_pkt_rd),
.wrreq(in_egress_pkt_wr),
.q(in_egress_pkt_q),
.usedw(in_egress_pkt_usedw)
);
reg in_egress_pkt_valid_rd;
wire in_egress_pkt_valid_empty;
wire in_egress_pkt_valid_q;
fifo_64_1 egress_pkt_valid(
.aclr(!reset),
.clock(clk),
.data(in_egress_pkt_valid),
.rdreq(in_egress_pkt_valid_rd),
.wrreq(in_egress_pkt_valid_wr),
.empty(in_egress_pkt_valid_empty),
.q(in_egress_pkt_valid_q)
);
endmodule |
module sky130_fd_sc_hdll__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Name Output
pullup pullup0 (HI );
pulldown pulldown0 (LO );
endmodule |
module Dc2Tile(
/* verilator lint_off UNUSED */
clock, reset,
regInAddr, regInData,
regOutData, regOutOK,
regInOE, regInWR,
regInOp,
memInData, memOutData, memAddr,
memOE, memWR, memOK,
mmioInData, mmioOutData, mmioAddr,
mmioOE, mmioWR, mmioOK
);
input clock; //clock
input reset; //reset
input[63:0] regInAddr; //input PC address
input[127:0] regInData; //input data (store)
input regInOE; //Load
input regInWR; //Store
input[4:0] regInOp; //Operation Size/Type
output[127:0] regOutData; //output data (load)
output[1:0] regOutOK; //set if operation suceeds
input[127:0] memInData; //memory PC data
output[127:0] memOutData; //memory PC data
output[31:0] memAddr; //memory PC address
output memOE; //memory PC output-enable
output memWR; //memory PC output-enable
input[1:0] memOK; //memory PC OK
reg[127:0] tMemOutData; //memory PC data
reg[31:0] tMemAddr; //memory PC address
reg tMemOE; //memory PC output-enable
reg tMemWR; //memory PC output-enable
assign memOutData = tMemOutData;
assign memAddr = tMemAddr;
assign memOE = tMemOE;
assign memWR = tMemWR;
input[31:0] mmioInData; //mmio data in
output[31:0] mmioOutData; //mmio data out
output[31:0] mmioAddr; //mmio address
output mmioOE; //mmio read
output mmioWR; //mmio write
input[1:0] mmioOK; //mmio OK
reg[31:0] tMmioOutData; //mmio data out
reg[31:0] tMmioAddr; //mmio address
reg tMmioOE; //mmio read
reg tMmioWR; //mmio write
assign mmioOutData = tMmioOutData;
assign mmioAddr = tMmioAddr;
assign mmioOE = tMmioOE;
assign mmioWR = tMmioWR;
// (* ram_style="block" *) reg[127:0] memTile[2047:0]; //memory
(* ram_style="block" *) reg[31:0] memTileA[0:2047]; //memory
(* ram_style="block" *) reg[31:0] memTileB[0:2047]; //memory
(* ram_style="block" *) reg[31:0] memTileC[0:2047]; //memory
(* ram_style="block" *) reg[31:0] memTileD[0:2047]; //memory
(* ram_style="block" *) reg[127:0] romTile[255:0]; //ROM
// reg[127:0] tRomTile;
reg[127:0] tRamTile;
reg[10:0] tAccTileIx;
reg[127:0] tMemTile;
reg[127:0] tOutData;
reg[127:0] tNextTile;
reg[10:0] tRegTileIx;
reg[10:0] tNextTileIx;
reg tNextTileSt;
reg[1:0] tRegOutOK;
wire addrIsRam;
assign addrIsRam =
(regInAddr[28:0] >= 29'h0C00_0000) &&
(regInAddr[28:0] <= 29'h1E00_0000) ;
wire addrIsRom;
assign addrIsRom =
(regInAddr[28:0] <= 29'h0010_0000) ;
assign regOutData = tOutData;
assign regOutOK = tRegOutOK;
initial begin
$readmemh("bootrom.txt", romTile);
end
always @*
begin
tMemTile = 0;
tOutData = 0;
tNextTile = 0;
tRegTileIx = regInAddr[14:4];
tNextTileIx = tRegTileIx;
tNextTileSt = 0;
tRegOutOK = 0;
tMemOutData = 0; //memory PC data
tMemAddr = 0; //memory PC address
tMemOE = 0; //memory PC output-enable
tMemWR = 0; //memory PC output-enable
tMmioOutData = 0; //mmio data out
tMmioAddr = 0; //mmio address
tMmioOE = 0; //mmio read
tMmioWR = 0; //mmio write
if(regInOE || regInWR)
begin
$display("DcTile2 %X %d %d", regInAddr, addrIsRom, addrIsRam);
if(addrIsRom)
begin
tMemTile = romTile[tRegTileIx[7:0]];
// tMemTile = tRomTile;
tNextTile = tMemTile;
tRegOutOK = 1;
// tRegOutOK = (tAccTileIx == tRegTileIx) ?
// UMEM_OK_OK : UMEM_OK_HOLD;
$display("Rom: %X", tMemTile);
case(regInOp[1:0])
2'b00:
tOutData=tMemTile;
2'b01:
tOutData=tMemTile;
2'b10: case(regInAddr[3:2])
2'b00: tOutData={96'h0, tMemTile[ 31: 0]};
2'b01: tOutData={96'h0, tMemTile[ 63:32]};
2'b10: tOutData={96'h0, tMemTile[ 95:64]};
2'b11: tOutData={96'h0, tMemTile[127:96]};
endcase
2'b11: begin
if(regInAddr[3])
tOutData={64'h0, tMemTile[127:64]};
else
tOutData={64'h0, tMemTile[ 63: 0]};
end
endcase
$display("Rom: Out=%X", tOutData);
end
else
if(addrIsRam)
begin
// tMemTile = memTile[tRegTileIx];
// tMemTile[ 31: 0] = memTileA[tRegTileIx];
// tMemTile[ 63:32] = memTileB[tRegTileIx];
// tMemTile[ 95:64] = memTileC[tRegTileIx];
// tMemTile[127:96] = memTileD[tRegTileIx];
tMemTile = tRamTile;
tNextTile = tMemTile;
// tRegOutOK = 1;
tRegOutOK = (tAccTileIx == tRegTileIx) ?
UMEM_OK_OK : UMEM_OK_HOLD;
case(regInOp[1:0])
2'b00:
tOutData=tMemTile;
2'b01:
tOutData=tMemTile;
2'b10: case(regInAddr[3:2])
2'b00: tOutData={96'h0, tMemTile[ 31: 0]};
2'b01: tOutData={96'h0, tMemTile[ 63:32]};
2'b10: tOutData={96'h0, tMemTile[ 95:64]};
2'b11: tOutData={96'h0, tMemTile[127:96]};
endcase
2'b11: begin
if(regInAddr[3])
tOutData={64'h0, tMemTile[127:64]};
else
tOutData={64'h0, tMemTile[ 63: 0]};
end
endcase
if(regInWR)
begin
tNextTileIx = tRegTileIx;
tNextTileSt = 1;
case(regInOp[1:0])
2'b00:
tNextTile=regInData;
2'b01:
tNextTile=regInData;
2'b10: case(regInAddr[3:2])
2'b00: tNextTile[ 31: 0] = regInData[31:0];
2'b01: tNextTile[ 63:32] = regInData[31:0];
2'b10: tNextTile[ 95:64] = regInData[31:0];
2'b11: tNextTile[127:96] = regInData[31:0];
endcase
2'b11: begin
if(regInAddr[3])
tNextTile[127:64] = regInData[63:0];
else
tNextTile[ 63: 0] = regInData[63:0];
end
endcase
end
end
else
begin
tMmioOutData = regInData[31:0];
tMmioAddr = regInAddr[31:0];
tMmioOE = regInOE;
tMmioWR = regInWR;
tRegOutOK = mmioOK;
tOutData = { 96'h0, mmioInData[31:0] };
end
end
end
always @ (posedge clock)
begin
// tRomTile <= romTile[tRegTileIx[7:0]];
// tRamTile <= memTile[tRegTileIx];
tRamTile[ 31: 0] <= memTileA[tRegTileIx];
tRamTile[ 63:32] <= memTileB[tRegTileIx];
tRamTile[ 95:64] <= memTileC[tRegTileIx];
tRamTile[127:96] <= memTileD[tRegTileIx];
tAccTileIx <= tRegTileIx;
if(tNextTileSt)
begin
// memTile[tNextTileIx] <= tNextTile;
memTileA[tNextTileIx] <= tNextTile[ 31: 0];
memTileB[tNextTileIx] <= tNextTile[ 63:32];
memTileC[tNextTileIx] <= tNextTile[ 95:64];
memTileD[tNextTileIx] <= tNextTile[127:96];
end
end
endmodule |
module: based around a Dual port distributed ram
// data is written in and the read only starts once the da/sa have been
// stored. Can cope with a gap of one cycle between packets.
address_swap address_swap (
.axi_tclk (axi_tclk),
.axi_tresetn (axi_tresetn),
.enable_address_swap (enable_address_swap),
.rx_axis_fifo_tdata (rx_axis_tdata_int),
.rx_axis_fifo_tvalid (rx_axis_tvalid_int),
.rx_axis_fifo_tlast (rx_axis_tlast_int),
.rx_axis_fifo_tready (rx_axis_tready_int),
.tx_axis_fifo_tdata (tx_axis_as_tdata),
.tx_axis_fifo_tvalid (tx_axis_as_tvalid),
.tx_axis_fifo_tlast (tx_axis_as_tlast),
.tx_axis_fifo_tready (tx_axis_as_tready)
);
endmodule |
module sky130_fd_sc_ms__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule |
module PushButton_Debouncer#(parameter COUNTER_WIDTH = 16) (
input wire clk,
input wire PB, // "PB" is the glitchy, asynchronous to clk, active low push-button signal
// from which we make three outputs, all synchronous to the clock
output reg PB_state, // 1 as long as the push-button is active (down)
output wire PB_down, // 1 for one clock cycle when the push-button goes down (i.e. just pushed)
output wire PB_up // 1 for one clock cycle when the push-button goes up (i.e. just released)
);
// First use two flip-flops to synchronize the PB signal the "clk" clock domain
reg PB_sync_0; always @(posedge clk) PB_sync_0 <= PB; // invert PB to make PB_sync_0 active high
reg PB_sync_1; always @(posedge clk) PB_sync_1 <= PB_sync_0;
// Next declare a 16-bits counter
reg [COUNTER_WIDTH-1:0] PB_cnt;
// When the push-button is pushed or released, we increment the counter
// The counter has to be maxed out before we decide that the push-button state has changed
wire PB_idle = (PB_state==PB_sync_1);
wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's
always @(posedge clk)
if(PB_idle)
PB_cnt <= 0; // nothing's going on
else
begin
PB_cnt <= PB_cnt + 16'd1; // something's going on, increment the counter
if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed!
end
assign PB_down = ~PB_idle & PB_cnt_max & ~PB_state;
assign PB_up = ~PB_idle & PB_cnt_max & PB_state;
endmodule |
module sky130_fd_sc_hd__sedfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{control|Control Signals}}
input DE ,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module mem_16nm_ram4x73
(
input wire clk,
input wire ram_wr_en,
input wire [1:0] ram_wr_addr,
input wire [72:0] ram_wr_data,
input wire ram_rd_en,
input wire [1:0] ram_rd_addr,
output wire [72:0] ram_rd_data,
input wire bist_clk,
input wire bist_en,
input wire [1:0] bist_addr,
input wire [72:0] bist_wr_data,
output wire [72:0] bist_rd_data
);
// The memory declaration
reg [72:0] memory [3:0];
reg [72:0] ram_rd_data_i;
always @ (posedge clk) begin
if( ram_wr_en ) begin
memory[ram_wr_addr] <= #0 ram_wr_data;
end
if( ram_rd_en ) begin
ram_rd_data_i <= #0 memory[ram_rd_addr];
end
end
always @ (posedge clk) begin
ram_rd_data <= #0 ram_rd_data_i;
end
// Bist fake logic
always @ (posedge bist_clk ) begin
bist_rd_data <= #0 bist_wr_data;
end
endmodule |
module LUTROM(
clka,
addra,
douta
);
input clka;
input [12 : 0] addra;
output [17 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("virtex5"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("LUTROM.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8192),
.C_READ_DEPTH_B(8192),
.C_READ_WIDTH_A(18),
.C_READ_WIDTH_B(18),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(8192),
.C_WRITE_DEPTH_B(8192),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(18),
.C_WRITE_WIDTH_B(18),
.C_XDEVICEFAMILY("virtex5")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule |
module crc16
(
output reg crc16_check_pass_reg,
output [15:0]crc_16,
input clk_crc16,
input rst_crc16,
input data,
input reply_data,
input sync,
input package_complete,
input en_crc16_for_rpy
);
wire d_in;
reg crc16_check_pass;
reg [15:0]reg_crc;
assign d_in = en_crc16_for_rpy? reply_data : data;
assign crc_16 = ~reg_crc;
always@(*) begin
if(reg_crc == 16'h1d0f) crc16_check_pass = 1'b1;
else crc16_check_pass = 1'b0;
end
always@(posedge clk_crc16 or negedge rst_crc16) begin
if(~rst_crc16) crc16_check_pass_reg <= 1'b0;
else if(package_complete) crc16_check_pass_reg <= crc16_check_pass;
end
always@(posedge clk_crc16 or negedge rst_crc16) begin
if(~rst_crc16) reg_crc <= 16'hffff;
else if(sync | en_crc16_for_rpy) begin
reg_crc[15] <= reg_crc[14];
reg_crc[14] <= reg_crc[13];
reg_crc[13] <= reg_crc[12];
reg_crc[12] <= reg_crc[11] ^ (d_in ^ reg_crc[15]);
reg_crc[11] <= reg_crc[10];
reg_crc[10] <= reg_crc[9];
reg_crc[9] <= reg_crc[8];
reg_crc[8] <= reg_crc[7];
reg_crc[7] <= reg_crc[6];
reg_crc[6] <= reg_crc[5];
reg_crc[5] <= reg_crc[4] ^ (d_in ^ reg_crc[15]);
reg_crc[4] <= reg_crc[3];
reg_crc[3] <= reg_crc[2];
reg_crc[2] <= reg_crc[1];
reg_crc[1] <= reg_crc[0];
reg_crc[0] <= d_in ^ reg_crc[15];
end
end
endmodule |
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__buf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module ptp_tag_insert #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = DATA_WIDTH/8,
parameter TAG_WIDTH = 16,
parameter TAG_OFFSET = 1,
parameter USER_WIDTH = TAG_WIDTH+TAG_OFFSET
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Tag input
*/
input wire [TAG_WIDTH-1:0] s_axis_tag,
input wire s_axis_tag_valid,
output wire s_axis_tag_ready
);
reg [TAG_WIDTH-1:0] tag_reg = {TAG_WIDTH{1'b0}};
reg tag_valid_reg = 1'b0;
reg [USER_WIDTH-1:0] user;
assign s_axis_tready = m_axis_tready && tag_valid_reg;
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep;
assign m_axis_tvalid = s_axis_tvalid && tag_valid_reg;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tuser = user;
assign s_axis_tag_ready = !tag_valid_reg;
always @* begin
user = s_axis_tuser;
user[TAG_OFFSET +: TAG_WIDTH] = tag_reg;
end
always @(posedge clk) begin
if (tag_valid_reg) begin
if (s_axis_tvalid && s_axis_tready && s_axis_tlast) begin
tag_valid_reg <= 1'b0;
end
end else begin
tag_reg <= s_axis_tag;
tag_valid_reg <= s_axis_tag_valid;
end
if (rst) begin
tag_valid_reg <= 1'b0;
end
end
endmodule |
module WcaInterruptIF
(
input wire clock, //High speed logic clock
input wire reset, //Reset functions
input wire [7:0] evtsig, //Up to eight events supported.
output wire cpu_interrupt, // signals the CPU an interrupt occurred.
input wire [11:0] rbusCtrl, // Address and control lines { addr[7:0], readStrobe, writeStrobe, cpuclk }
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter CTRL_ADDR=0; //Interrupt register control address.
//****************************************************
//* Event control
//****************************************************
// MASK WRITE REGISTER( WriteByteRegister)
// Write to this register to set the Event mask. Register is also used to
// clear an event by writing a 0 and 1 to the respective event bit.
//
// bit# | Description
//-------|----------------------------------------------------------
// 0 Enable / Disable Event #0
// 1 Enable / Disable Event #1
// 2 Enable / Disable Event #2
// 3 Enable / Disable Event #3
// 4 Enable / Disable Event #4
// 5 Enable / Disable Event #5
// 6 Enable / Disable Event #6
// 7 Enable / Disable Event #7
//
// STATUS READ REGISTER( ReadByteRegister)
// Read this register to get the Event status.
// bit# | Description
//-------|----------------------------------------------------------
// 0 Event #0 Triggered
// 1 Event #1 Triggered
// 2 Event #2 Triggered
// 3 Event #3 Triggered
// 4 Event #4 Triggered
// 5 Event #5 Triggered
// 6 Event #6 Triggered
// 7 Event #7 Triggered
wire [7:0] evtMask;
wire [7:0] evtStatus;
wire [7:0] evtUpdate;
wire evt;
//Combine all signals into general event indicator.
assign evt = (evtsig[7] & evtMask[7]) | (evtsig[6] & evtMask[6])
| (evtsig[5] & evtMask[5]) | (evtsig[4] & evtMask[4])
| (evtsig[3] & evtMask[3]) | (evtsig[2] & evtMask[2])
| (evtsig[1] & evtMask[1]) | (evtsig[0] & evtMask[0]) ;
//Get the current interrupt state.
assign cpu_interrupt = evtStatus[7] | evtStatus[6]
| evtStatus[5] | evtStatus[4]
| evtStatus[3] | evtStatus[2]
| evtStatus[1] | evtStatus[0];
//Calculate the latest event state update.
assign evtUpdate = (evtStatus | evtsig) & evtMask;
//Get Event Enable Mask.
WcaWriteByteReg #(CTRL_ADDR ) wstatreg
(.reset(reset), .out( evtMask), .rbusCtrl(rbusCtrl), .rbusData(rbusData) );
//Latch current event state into the read status register.
//Override standard disable write on read function to allow
//interrupts to happen while register is being processed.
WcaReadByteReg #(CTRL_ADDR, 1'b1) rstatreg
( .reset(reset), .clock(clock), .enableIn(1'b1), .in(evtUpdate),
.Q( evtStatus), .rbusCtrl(rbusCtrl), .rbusData(rbusData) );
endmodule |
module top (
input wire USER_RESET,
input wire USER_CLOCK,
input wire ETH_COL,
input wire ETH_CRS,
output wire ETH_MDC,
inout wire ETH_MDIO,
output wire ETH_RESET_n,
input wire ETH_RX_CLK,
input wire [3:0] ETH_RX_D,
input wire ETH_RX_DV,
input wire ETH_RX_ER,
input wire ETH_TX_CLK,
output wire [3:0] ETH_TX_D,
output wire ETH_TX_EN,
output wire [3:0] GPIO_LED,
input wire [3:0] GPIO_DIP,
inout wire SDA, SCL,
output wire CMD_CLK, CMD_DATA,
input wire [3:0] DOBOUT
);
wire CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKFBIN, LOCKED;
wire RST, BUS_CLK, BUS_RST, SPI_CLK;
PLL_BASE #(
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(16), // Multiply value for all CLKOUT clock outputs (1-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of the clock feedback output (0.0-360.0).
.CLKIN_PERIOD(25.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30
// MHz).
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
.CLKOUT0_DIVIDE(1), //640 - 320MHz
.CLKOUT1_DIVIDE(32), //25
.CLKOUT2_DIVIDE(64), //10HHz
.CLKOUT3_DIVIDE(16), //40MHz
.CLKOUT4_DIVIDE(4), // 160Mhz
.CLKOUT5_DIVIDE(40), //16Mhz
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT5_PHASE: Output phase relationship for CLKOUT# clock output (-360.0-360.0).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLK_FEEDBACK("CLKFBOUT"), // Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0")
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "EXTERNAL"
.DIVCLK_DIVIDE(1), // Division value for all output clocks (1-52)
.REF_JITTER(0.1), // Reference Clock Jitter in UI (0.000-0.999).
.RESET_ON_LOSS_OF_LOCK("FALSE") // Must be set to FALSE
)
PLL_BASE_inst (
.CLKFBOUT(CLKFBOUT), // 1-bit output: PLL_BASE feedback output
// CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
.CLKOUT0(CLKOUT0),
.CLKOUT1(CLKOUT1),
.CLKOUT2(CLKOUT2),
.CLKOUT3(CLKOUT3),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.LOCKED(LOCKED), // 1-bit output: PLL_BASE lock status output
.CLKFBIN(CLKFBIN), // 1-bit input: Feedback clock input
.CLKIN(USER_CLOCK), // 1-bit input: Clock input
.RST(USER_RESET) // 1-bit input: Reset input
);
wire RX_CLK, TX_CLK;
assign RST = USER_RESET | !LOCKED;
assign CLKFBIN = CLKFBOUT; //BUFG BUFG_FB ( .O(CLKFBIN), .I(CLKFBOUT) );
BUFG BUFG_BUS ( .O(BUS_CLK), .I(CLKOUT3) );
BUFG BUFG_ETH_RX_CLK ( .O(RX_CLK), .I(ETH_RX_CLK) );
//BUFG BUFG_SPI( .O(SPI_CLK), .I(CLKOUT2) );
BUFG BUFG_ETH_TX_CLK ( .O(TX_CLK), .I(ETH_TX_CLK) );
wire RX_320_CLK, RX_160_CLK, RX_16_CLK;
//BUFG BUFG_RX_320 ( .O(RX_320_CLK), .I(CLKOUT0) );
//assign RX_320_CLK = CLKOUT0;
BUFG BUFG_RX_160 ( .O(RX_160_CLK), .I(CLKOUT4) );
BUFG BUFG_RX_16 ( .O(RX_16_CLK), .I(CLKOUT5) );
//wire CLKOUT0_BUF;
//BUFG BUFG_RX_320 ( .O(CLKOUT0_BUF), .I(CLKOUT0) );
wire CLK40;
assign CLK40 = BUS_CLK;
wire IOCLK, DIVCLK, DIVCLK_BUF, RX_320_IOCE;
/*
BUFIO2 #(
.DIVIDE(4), // DIVCLK divider (1,3-8)
.DIVIDE_BYPASS("TRUE"), // Bypass the divider circuitry (TRUE/FALSE)
.I_INVERT("FALSE"), // Invert clock (TRUE/FALSE)
.USE_DOUBLER("FALSE") // Use doubler circuitry (TRUE/FALSE)
)
BUFIO2_inst (
.DIVCLK(DIVCLK_BUF), // 1-bit output: Divided clock output
.IOCLK(RX_320_CLK), // 1-bit output: I/O output clock
.SERDESSTROBE(RX_320_IOCE), // 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
.I(CLKOUT3_BUF) // 1-bit input: Clock input (connect to IBUFG)
);
BUFG BUFG_DIV ( .O(RX_160_CLK), .I(DIVCLK_BUF) );
*/
BUFPLL #(
.DIVIDE(4), // DIVCLK divider (1-8)
.ENABLE_SYNC("TRUE") // Enable synchrnonization between PLL and GCLK (TRUE/FALSE)
)
BUFPLL_inst (
.IOCLK(RX_320_CLK), // 1-bit output: Output I/O clock
.LOCK(), // 1-bit output: Synchronized LOCK output
.SERDESSTROBE(RX_320_IOCE), // 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
.GCLK(RX_160_CLK), // 1-bit input: BUFG clock input
.LOCKED(LOCKED), // 1-bit input: LOCKED input from PLL
.PLLIN(CLKOUT0) // 1-bit input: Clock input from PLL
);
wire EEPROM_CS, EEPROM_SK, EEPROM_DI;
wire TCP_CLOSE_REQ;
wire RBCP_ACT, RBCP_WE, RBCP_RE;
wire [7:0] RBCP_WD, RBCP_RD;
wire [31:0] RBCP_ADDR;
wire TCP_RX_WR;
wire [7:0] TCP_RX_DATA;
wire [15:0] TCP_RX_WC;
wire RBCP_ACK;
wire TCP_TX_FULL;
wire TCP_TX_WR;
wire [7:0] TCP_TX_DATA;
wire mdio_gem_i;
wire mdio_gem_o;
wire mdio_gem_t;
wire [3:0] ETH_TX_D_NO;
WRAP_SiTCP_GMII_XC6S_16K #(.TIM_PERIOD(50))sitcp(
.CLK(BUS_CLK), // in : System Clock >129MHz
.RST(RST), // in : System reset
// Configuration parameters
.FORCE_DEFAULTn(1'b0), // in : Load default parameters
.EXT_IP_ADDR(32'hc0a80a11), // in : IP address[31:0] //192.168.10.11
.EXT_TCP_PORT(16'd24), // in : TCP port #[15:0]
.EXT_RBCP_PORT(16'd4660), // in : RBCP port #[15:0]
.PHY_ADDR(5'd30), // in : PHY-device MIF address[4:0]
// EEPROM
.EEPROM_CS(), // out : Chip select
.EEPROM_SK(), // out : Serial data clock
.EEPROM_DI(), // out : Serial write data
.EEPROM_DO(1'b0), // in : Serial read data
// user data, intialial values are stored in the EEPROM, 0xFFFF_FC3C-3F
.USR_REG_X3C(), // out : Stored at 0xFFFF_FF3C
.USR_REG_X3D(), // out : Stored at 0xFFFF_FF3D
.USR_REG_X3E(), // out : Stored at 0xFFFF_FF3E
.USR_REG_X3F(), // out : Stored at 0xFFFF_FF3F
// MII interface
.GMII_RSTn(ETH_RESET_n), // out : PHY reset
.GMII_1000M(1'b0), // in : GMII mode (0:MII, 1:GMII)
// TX
.GMII_TX_CLK(TX_CLK), // in : Tx clock
.GMII_TX_EN(ETH_TX_EN), // out : Tx enable
.GMII_TXD({ETH_TX_D_NO,ETH_TX_D}), // out : Tx data[7:0]
.GMII_TX_ER(), // out : TX error
// RX
.GMII_RX_CLK(RX_CLK), // in : Rx clock
.GMII_RX_DV(ETH_RX_DV), // in : Rx data valid
.GMII_RXD({4'b0, ETH_RX_D}), // in : Rx data[7:0]
.GMII_RX_ER(ETH_RX_ER), // in : Rx error
.GMII_CRS(ETH_CRS), // in : Carrier sense
.GMII_COL(ETH_COL), // in : Collision detected
// Management IF
.GMII_MDC(ETH_MDC), // out : Clock for MDIO
.GMII_MDIO_IN(mdio_gem_i), // in : Data
.GMII_MDIO_OUT(mdio_gem_o), // out : Data
.GMII_MDIO_OE(mdio_gem_t), // out : MDIO output enable
// User I/F
.SiTCP_RST(BUS_RST), // out : Reset for SiTCP and related circuits
// TCP connection control
.TCP_OPEN_REQ(1'b0), // in : Reserved input, shoud be 0
.TCP_OPEN_ACK(), // out : Acknowledge for open (=Socket busy)
.TCP_ERROR(), // out : TCP error, its active period is equal to MSL
.TCP_CLOSE_REQ(TCP_CLOSE_REQ), // out : Connection close request
.TCP_CLOSE_ACK(TCP_CLOSE_REQ), // in : Acknowledge for closing
// FIFO I/F
.TCP_RX_WC(TCP_RX_WC), // in : Rx FIFO write count[15:0] (Unused bits should be set 1)
.TCP_RX_WR(TCP_RX_WR), // out : Write enable
.TCP_RX_DATA(TCP_RX_DATA), // out : Write data[7:0]
.TCP_TX_FULL(TCP_TX_FULL), // out : Almost full flag
.TCP_TX_WR(TCP_TX_WR), // in : Write enable
.TCP_TX_DATA(TCP_TX_DATA), // in : Write data[7:0]
// RBCP
.RBCP_ACT(RBCP_ACT), // out : RBCP active
.RBCP_ADDR(RBCP_ADDR), // out : Address[31:0]
.RBCP_WD(RBCP_WD), // out : Data[7:0]
.RBCP_WE(RBCP_WE), // out : Write enable
.RBCP_RE(RBCP_RE), // out : Read enable
.RBCP_ACK(RBCP_ACK), // in : Access acknowledge
.RBCP_RD(RBCP_RD) // in : Read data[7:0]
);
IOBUF i_iobuf_mdio(
.O(mdio_gem_i),
.IO(ETH_MDIO),
.I(mdio_gem_o),
.T(mdio_gem_t)
);
wire BUS_WR, BUS_RD;
wire [31:0] BUS_ADD;
wire [7:0] BUS_DATA;
wire INVALID;
tcp_to_bus itcp_to_bus(
.BUS_RST(BUS_RST),
.BUS_CLK(BUS_CLK),
.TCP_RX_WC(TCP_RX_WC),
.TCP_RX_WR(TCP_RX_WR),
.TCP_RX_DATA(TCP_RX_DATA),
.RBCP_ACT(RBCP_ACT),
.RBCP_ADDR(RBCP_ADDR),
.RBCP_WD(RBCP_WD),
.RBCP_WE(RBCP_WE),
.RBCP_RE(RBCP_RE),
.RBCP_ACK(RBCP_ACK),
.RBCP_RD(RBCP_RD),
.BUS_WR(BUS_WR),
.BUS_RD(BUS_RD),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.INVALID(INVALID)
);
//MODULE ADDRESSES
localparam CMD_BASEADDR = 32'h0000;
localparam CMD_HIGHADDR = 32'h8000-1;
localparam RX4_BASEADDR = 32'h8300;
localparam RX4_HIGHADDR = 32'h8400-1;
localparam RX3_BASEADDR = 32'h8400;
localparam RX3_HIGHADDR = 32'h8500-1;
localparam RX2_BASEADDR = 32'h8500;
localparam RX2_HIGHADDR = 32'h8600-1;
localparam RX1_BASEADDR = 32'h8600;
localparam RX1_HIGHADDR = 32'h8700-1;
localparam GPIO_BASEADDR = 32'h8700;
localparam GPIO_HIGHADDR = 32'h8800-1;
localparam I2C_BASEADDR = 32'h8800;
localparam I2C_HIGHADDR = 32'h8900-1;
// MODULES //
cmd_seq #(
.BASEADDR(CMD_BASEADDR),
.HIGHADDR(CMD_HIGHADDR),
.ABUSWIDTH(32)
) icmd (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CMD_CLK_OUT(CMD_CLK),
.CMD_CLK_IN(CLK40),
.CMD_EXT_START_FLAG(1'b0),
.CMD_EXT_START_ENABLE(),
.CMD_DATA(CMD_DATA),
.CMD_READY(),
.CMD_START_FLAG()
);
wire [3:0] RX_READY, RX_8B10B_DECODER_ERR, RX_FIFO_OVERFLOW_ERR, RX_FIFO_FULL;
wire [3:0] FE_FIFO_READ;
wire [3:0] FE_FIFO_EMPTY;
wire [31:0] FE_FIFO_DATA [3:0];
genvar i;
generate
for (i = 0; i < 1; i = i + 1) begin: rx_gen
fei4_rx #(
.BASEADDR(RX1_BASEADDR-16'h0100*i),
.HIGHADDR(RX1_HIGHADDR-16'h0100*i),
.DSIZE(10),
.DATA_IDENTIFIER(i+1),
.ABUSWIDTH(32)
) i_fei4_rx (
.RX_CLK(RX_160_CLK),
.RX_CLK2X(RX_320_CLK),
.RX_CLK2X_IOCE(RX_320_IOCE),
.DATA_CLK(RX_16_CLK),
.RX_DATA(DOBOUT[i]),
.RX_READY(RX_READY[i]),
.RX_8B10B_DECODER_ERR(RX_8B10B_DECODER_ERR[i]),
.RX_FIFO_OVERFLOW_ERR(RX_FIFO_OVERFLOW_ERR[i]),
.FIFO_CLK(1'b0),
.FIFO_READ(FE_FIFO_READ[i]),
.FIFO_EMPTY(FE_FIFO_EMPTY[i]),
.FIFO_DATA(FE_FIFO_DATA[i]),
.RX_FIFO_FULL(RX_FIFO_FULL[i]),
.RX_ENABLED(),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR)
);
end
endgenerate
/*
gpio
#(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(32),
.IO_WIDTH(8),
.IO_DIRECTION(8'h0f)
) i_gpio
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO({GPIO_DIP, GPIO_LED})
);
*/
wire I2C_CLK, I2C_CLK_PRE;
clock_divider #( .DIVISOR(4000) ) i2c_clkdev ( .CLK(BUS_CLK), .RESET(BUS_RST), .CE(), .CLOCK(I2C_CLK_PRE) );
BUFG BUFG_I2C ( .O(I2C_CLK), .I(I2C_CLK_PRE) );
i2c
#(
.BASEADDR(I2C_BASEADDR),
.HIGHADDR(I2C_HIGHADDR),
.ABUSWIDTH(32),
.MEM_BYTES(8)
) i_i2c
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.I2C_CLK(I2C_CLK),
.I2C_SDA(SDA),
.I2C_SCL(SCL)
);
//assign FE_FIFO_EMPTY[0] = 1;
//assign FE_FIFO_EMPTY[1] = 1;
//assign FE_FIFO_EMPTY[2] = 1;
//assign FE_FIFO_EMPTY[3] = 1;
wire ARB_READY_OUT, ARB_WRITE_OUT;
wire [31:0] ARB_DATA_OUT;
wire [3:0] READ_GRANT;
/*
rrp_arbiter #(
.WIDTH(4)
) i_rrp_arbiter (
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE_REQ({~FE_FIFO_EMPTY}),
.HOLD_REQ({4'b0}),
.DATA_IN({FE_FIFO_DATA[3],FE_FIFO_DATA[2],FE_FIFO_DATA[1], FE_FIFO_DATA[0]}),
.READ_GRANT(READ_GRANT),
.READY_OUT(ARB_READY_OUT),
.WRITE_OUT(ARB_WRITE_OUT),
.DATA_OUT(ARB_DATA_OUT)
);
assign FE_FIFO_READ = READ_GRANT[3:0];
*/
assign ARB_DATA_OUT = FE_FIFO_DATA[0];
assign FE_FIFO_READ[0] = ARB_READY_OUT;
assign ARB_WRITE_OUT = ~FE_FIFO_EMPTY[0];
wire FIFO_EMPTY, FIFO_FULL;
fifo_32_to_8 #(.DEPTH(1*256)) i_data_fifo (
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE(ARB_WRITE_OUT),
.READ(TCP_TX_WR),
.DATA_IN(ARB_DATA_OUT),
.FULL(FIFO_FULL),
.EMPTY(FIFO_EMPTY),
.DATA_OUT(TCP_TX_DATA)
);
assign ARB_READY_OUT = !FIFO_FULL;
assign TCP_TX_WR = !TCP_TX_FULL && !FIFO_EMPTY;
assign GPIO_LED = RX_READY;
endmodule |
module state_machine_counter #(
parameter INTR_TYPE = 1'b1
)(
clk,
reset_n,
pulse_irq_counter_stop,
global_enable_reg,
counter_start,
counter_stop,
enable,
c_idle,
level_reset,
data_store
);
input wire clk;
input wire reset_n;
input wire pulse_irq_counter_stop;
input wire global_enable_reg;
input wire counter_start;
input wire counter_stop;
output reg enable;
output reg level_reset;
output reg data_store;
output reg c_idle;
reg [1:0] state ;
reg [1:0] next_state ;
localparam IDLE =2'b00;
localparam START =2'b01;
localparam STOP =2'b10;
localparam STORE =2'b11;
//State machine Sequential logic
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n) state <= IDLE;
else state<= next_state;
end
//State Machine Transitional conditions
always @(state or counter_start or counter_stop or pulse_irq_counter_stop or global_enable_reg)
begin
case (state)
IDLE: if (counter_start==1'b0 || global_enable_reg == 1'b0 || pulse_irq_counter_stop==1'b1) begin
next_state = IDLE; // active low reset signal
end else begin
next_state = START;
end
START: if (global_enable_reg == 1'b0) begin
next_state = IDLE;
end
else if ((INTR_TYPE == 0 & counter_stop==1'b1) |(INTR_TYPE == 1 & pulse_irq_counter_stop==1'b1))
begin
next_state = STOP;
end
else
begin
next_state = START;
end
STOP: begin
next_state = STORE;
end
STORE: begin
next_state = IDLE;
end
default:next_state = IDLE;
endcase
end
//combo logic function to control counter
always @ (state) begin
case (state)
IDLE: begin
enable = 1'b0;
level_reset = 1'b0;
data_store = 1'b0;
c_idle = 1'b1;
end
START: begin
enable = 1'b1;
level_reset = 1'b1;
data_store = 1'b0;
c_idle = 1'b0;
end
STOP: begin
enable = 1'b0;
level_reset = 1'b1;
data_store = 1'b0;
c_idle = 1'b0;
end
STORE: begin
enable = 1'b0;
level_reset = 1'b1;
data_store = 1'b1;
c_idle = 1'b0;
end
endcase
end
endmodule |
module sky130_fd_sc_hdll__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule |
module SystemClockUnit
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (20),
.CLKFX_MULTIPLY (13),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule |
module nco_d (
clk, sine
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [15 : 0] sine;
// synthesis translate_off
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
wire sig00000071;
wire sig00000072;
wire sig00000073;
wire sig00000074;
wire sig00000075;
wire sig00000076;
wire sig00000077;
wire sig00000078;
wire sig00000079;
wire sig0000007a;
wire sig0000007b;
wire sig0000007c;
wire sig0000007d;
wire sig0000007e;
wire sig0000007f;
wire sig00000080;
wire sig00000081;
wire sig00000082;
wire sig00000083;
wire sig00000084;
wire sig00000085;
wire sig00000086;
wire sig00000087;
wire sig00000088;
wire sig00000089;
wire sig0000008a;
wire sig0000008b;
wire sig0000008c;
wire sig0000008d;
wire sig0000008e;
wire sig0000008f;
wire sig00000090;
wire sig00000091;
wire sig00000092;
wire sig00000093;
wire sig00000094;
wire sig00000095;
wire sig00000096;
wire sig00000097;
wire sig00000098;
wire sig00000099;
wire sig0000009a;
wire sig0000009b;
wire sig0000009c;
wire sig0000009d;
wire sig0000009e;
wire sig0000009f;
wire sig000000a0;
wire sig000000a1;
wire sig000000a2;
wire sig000000a3;
wire sig000000a4;
wire sig000000a5;
wire sig000000a6;
wire sig000000a7;
wire sig000000a8;
wire sig000000a9;
wire sig000000aa;
wire sig000000ab;
wire sig000000ac;
wire sig000000ad;
wire sig000000ae;
wire sig000000af;
wire sig000000b0;
wire sig000000b1;
wire sig000000b2;
wire sig000000b3;
wire sig000000b4;
wire sig000000b5;
wire sig000000b6;
wire sig000000b7;
wire sig000000b8;
wire sig000000b9;
wire sig000000ba;
wire sig000000bb;
wire sig000000bc;
wire sig000000bd;
wire sig000000be;
wire sig000000bf;
wire sig000000c0;
wire sig000000c1;
wire sig000000c2;
wire sig000000c3;
wire sig000000c4;
wire sig000000c5;
wire sig000000c6;
wire sig000000c7;
wire sig000000c8;
wire sig000000c9;
wire sig000000ca;
wire sig000000cb;
wire sig000000cc;
wire sig000000cd;
wire sig000000ce;
wire sig000000cf;
wire sig000000d0;
wire sig000000d1;
wire sig000000d2;
wire sig000000d3;
wire sig000000d4;
wire sig000000d5;
wire sig000000d6;
wire sig000000d7;
wire sig000000d8;
wire sig000000d9;
wire sig000000da;
wire sig000000db;
wire sig000000dc;
wire sig000000dd;
wire sig000000de;
wire sig000000df;
wire sig000000e0;
wire sig000000e1;
wire sig000000e2;
wire sig000000e3;
wire sig000000e4;
wire sig000000e5;
wire sig000000e6;
wire sig000000e7;
wire sig000000e8;
wire sig000000e9;
wire sig000000ea;
wire sig000000eb;
wire sig000000ec;
wire sig000000ed;
wire sig000000ee;
wire sig000000ef;
wire sig000000f0;
wire sig000000f1;
wire sig000000f2;
wire sig000000f3;
wire sig000000f4;
wire sig000000f5;
wire sig000000f6;
wire sig000000f7;
wire sig000000f8;
wire sig000000f9;
wire sig000000fa;
wire sig000000fb;
wire sig000000fc;
wire sig000000fd;
wire sig000000fe;
wire sig000000ff;
wire sig00000100;
wire sig00000101;
wire sig00000102;
wire sig00000103;
wire sig00000104;
wire sig00000105;
wire sig00000106;
wire sig00000107;
wire sig00000108;
wire sig00000109;
wire sig0000010a;
wire sig0000010b;
wire sig0000010c;
wire sig0000010d;
wire sig0000010e;
wire sig0000010f;
wire sig00000110;
wire sig00000111;
wire sig00000112;
wire sig00000113;
wire sig00000114;
wire sig00000115;
wire sig00000116;
wire sig00000117;
wire sig00000118;
wire sig00000119;
wire sig0000011a;
wire sig0000011b;
wire sig0000011c;
wire sig0000011d;
wire sig0000011e;
wire sig0000011f;
wire sig00000120;
wire sig00000121;
wire sig00000122;
wire sig00000123;
wire sig00000124;
wire sig00000125;
wire sig00000126;
wire sig00000127;
wire sig00000128;
wire sig00000129;
wire sig0000012a;
wire sig0000012b;
wire sig0000012c;
wire sig0000012d;
wire sig0000012e;
wire sig0000012f;
wire sig00000130;
wire sig00000131;
wire sig00000132;
wire sig00000133;
wire sig00000134;
wire sig00000135;
wire sig00000136;
wire sig00000137;
wire sig00000138;
wire sig00000139;
wire sig0000013a;
wire sig0000013b;
wire sig0000013c;
wire sig0000013d;
wire sig0000013e;
wire sig0000013f;
wire sig00000140;
wire sig00000141;
wire sig00000142;
wire sig00000143;
wire sig00000144;
wire sig00000145;
wire sig00000146;
wire sig00000147;
wire sig00000148;
wire \blk00000025/sig00000198 ;
wire \blk00000025/sig00000197 ;
wire \blk00000025/sig00000196 ;
wire \blk00000025/sig00000195 ;
wire \blk00000025/sig00000194 ;
wire \blk00000025/sig00000193 ;
wire \blk00000025/sig00000192 ;
wire \blk00000025/sig00000191 ;
wire \blk00000025/sig00000190 ;
wire \blk00000025/sig0000018f ;
wire \blk00000025/sig0000018e ;
wire \blk00000025/sig0000018d ;
wire \blk00000025/sig0000018c ;
wire \blk00000025/sig0000018b ;
wire \blk00000025/sig0000018a ;
wire \blk00000025/sig00000189 ;
wire \blk00000025/sig00000188 ;
wire \blk00000025/sig00000187 ;
wire \blk00000025/sig00000186 ;
wire \blk00000025/sig00000185 ;
wire \blk00000025/sig00000184 ;
wire \blk00000025/sig00000183 ;
wire \blk00000025/sig00000182 ;
wire \blk00000025/sig00000181 ;
wire \blk00000025/sig00000180 ;
wire \blk00000025/sig0000017f ;
wire \blk00000025/sig0000017e ;
wire \blk00000025/sig0000017d ;
wire \blk00000025/sig0000017c ;
wire \blk00000025/sig0000017b ;
wire \blk00000025/sig0000017a ;
wire \blk00000056/sig000001e9 ;
wire \blk00000056/sig000001e8 ;
wire \blk00000056/sig000001e7 ;
wire \blk00000056/sig000001e6 ;
wire \blk00000056/sig000001e5 ;
wire \blk00000056/sig000001e4 ;
wire \blk00000056/sig000001e3 ;
wire \blk00000056/sig000001e2 ;
wire \blk00000056/sig000001e1 ;
wire \blk00000056/sig000001e0 ;
wire \blk00000056/sig000001df ;
wire \blk00000056/sig000001de ;
wire \blk00000056/sig000001dd ;
wire \blk00000056/sig000001dc ;
wire \blk00000056/sig000001db ;
wire \blk00000056/sig000001da ;
wire \blk00000056/sig000001d9 ;
wire \blk00000056/sig000001d8 ;
wire \blk00000056/sig000001d7 ;
wire \blk00000056/sig000001d6 ;
wire \blk00000056/sig000001d5 ;
wire \blk00000056/sig000001d4 ;
wire \blk00000056/sig000001d3 ;
wire \blk00000056/sig000001d2 ;
wire \blk00000056/sig000001d1 ;
wire \blk00000056/sig000001d0 ;
wire \blk00000056/sig000001cf ;
wire \blk00000056/sig000001ce ;
wire \blk00000056/sig000001cd ;
wire \blk00000056/sig000001cc ;
wire \blk00000056/sig000001cb ;
wire \blk00000087/sig000001ff ;
wire \blk00000087/sig000001fe ;
wire \blk00000087/sig000001fd ;
wire \blk00000087/sig000001fc ;
wire \blk00000087/sig000001fb ;
wire \blk00000087/sig000001fa ;
wire \blk00000087/sig000001f9 ;
wire \blk00000087/sig000001f8 ;
wire \blk00000087/sig000001f7 ;
wire \blk00000087/sig000001f6 ;
wire \blk00000087/sig000001f2 ;
wire \blk00000087/sig000001f1 ;
wire \blk00000087/sig000001f0 ;
wire \blk00000087/sig000001ef ;
wire \blk00000087/sig000001ee ;
wire \blk00000087/sig000001ed ;
wire \blk00000087/sig000001ec ;
wire \NLW_blk0000014d_DIPA<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPA<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPA<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPA<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<4>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<4>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<4>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<4>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<4>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<4>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<4>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<3>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<4>_UNCONNECTED ;
wire NLW_blk00000151_Q15_UNCONNECTED;
wire NLW_blk00000153_Q15_UNCONNECTED;
wire NLW_blk00000155_Q15_UNCONNECTED;
wire NLW_blk00000157_Q15_UNCONNECTED;
wire NLW_blk00000159_Q15_UNCONNECTED;
wire NLW_blk0000015b_Q15_UNCONNECTED;
wire NLW_blk0000015d_Q15_UNCONNECTED;
wire NLW_blk0000015f_Q15_UNCONNECTED;
wire NLW_blk00000161_Q15_UNCONNECTED;
wire NLW_blk00000163_Q15_UNCONNECTED;
wire NLW_blk00000165_Q15_UNCONNECTED;
wire NLW_blk00000167_Q15_UNCONNECTED;
wire NLW_blk00000169_Q15_UNCONNECTED;
wire NLW_blk0000016b_Q15_UNCONNECTED;
wire NLW_blk0000016d_Q15_UNCONNECTED;
wire NLW_blk0000016f_Q15_UNCONNECTED;
wire NLW_blk00000171_Q15_UNCONNECTED;
wire NLW_blk00000173_Q15_UNCONNECTED;
wire NLW_blk00000175_Q15_UNCONNECTED;
wire NLW_blk00000177_Q15_UNCONNECTED;
wire NLW_blk00000179_Q15_UNCONNECTED;
wire NLW_blk0000017b_Q15_UNCONNECTED;
wire NLW_blk0000017d_Q15_UNCONNECTED;
wire NLW_blk0000017f_Q15_UNCONNECTED;
wire NLW_blk00000181_Q15_UNCONNECTED;
wire NLW_blk00000183_Q15_UNCONNECTED;
wire NLW_blk00000185_Q15_UNCONNECTED;
wire NLW_blk00000187_Q15_UNCONNECTED;
wire NLW_blk00000189_Q15_UNCONNECTED;
wire NLW_blk0000018b_Q15_UNCONNECTED;
wire NLW_blk0000018d_Q15_UNCONNECTED;
wire NLW_blk0000018f_Q15_UNCONNECTED;
wire [7 : 0] \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q ;
wire [7 : 0] \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q ;
assign
sine[15] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [7],
sine[14] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [6],
sine[13] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [5],
sine[12] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [4],
sine[11] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [3],
sine[10] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [2],
sine[9] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [1],
sine[8] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [0],
sine[7] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [7],
sine[6] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [6],
sine[5] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [5],
sine[4] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [4],
sine[3] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [3],
sine[2] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [2],
sine[1] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [1],
sine[0] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [0];
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig00000002)
);
FD #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.D(sig00000003),
.Q(sig00000046)
);
FD #(
.INIT ( 1'b0 ))
blk00000004 (
.C(clk),
.D(sig00000004),
.Q(sig00000045)
);
FD #(
.INIT ( 1'b0 ))
blk00000005 (
.C(clk),
.D(sig00000005),
.Q(sig00000044)
);
FD #(
.INIT ( 1'b0 ))
blk00000006 (
.C(clk),
.D(sig00000006),
.Q(sig00000043)
);
FD #(
.INIT ( 1'b0 ))
blk00000007 (
.C(clk),
.D(sig00000007),
.Q(sig00000042)
);
FD #(
.INIT ( 1'b0 ))
blk00000008 (
.C(clk),
.D(sig00000008),
.Q(sig00000041)
);
FD #(
.INIT ( 1'b0 ))
blk00000009 (
.C(clk),
.D(sig00000009),
.Q(sig00000040)
);
FD #(
.INIT ( 1'b0 ))
blk0000000a (
.C(clk),
.D(sig0000000a),
.Q(sig0000003f)
);
FD #(
.INIT ( 1'b0 ))
blk0000000b (
.C(clk),
.D(sig0000000b),
.Q(sig0000003e)
);
FD #(
.INIT ( 1'b0 ))
blk0000000c (
.C(clk),
.D(sig0000000c),
.Q(sig0000003d)
);
FD #(
.INIT ( 1'b0 ))
blk0000000d (
.C(clk),
.D(sig0000000d),
.Q(sig0000003c)
);
FD #(
.INIT ( 1'b0 ))
blk0000000e (
.C(clk),
.D(sig0000000e),
.Q(sig0000003b)
);
FD #(
.INIT ( 1'b0 ))
blk0000000f (
.C(clk),
.D(sig0000000f),
.Q(sig0000003a)
);
FD #(
.INIT ( 1'b0 ))
blk00000010 (
.C(clk),
.D(sig00000010),
.Q(sig00000039)
);
FD #(
.INIT ( 1'b0 ))
blk00000011 (
.C(clk),
.D(sig00000011),
.Q(sig00000038)
);
FD #(
.INIT ( 1'b0 ))
blk00000012 (
.C(clk),
.D(sig00000012),
.Q(sig00000037)
);
FD #(
.INIT ( 1'b0 ))
blk00000013 (
.C(clk),
.D(sig00000013),
.Q(sig00000036)
);
FD #(
.INIT ( 1'b0 ))
blk00000014 (
.C(clk),
.D(sig00000024),
.Q(sig00000049)
);
FD #(
.INIT ( 1'b0 ))
blk00000015 (
.C(clk),
.D(sig00000023),
.Q(sig00000032)
);
FD #(
.INIT ( 1'b0 ))
blk00000016 (
.C(clk),
.D(sig00000022),
.Q(sig00000031)
);
FD #(
.INIT ( 1'b0 ))
blk00000017 (
.C(clk),
.D(sig00000021),
.Q(sig00000030)
);
FD #(
.INIT ( 1'b0 ))
blk00000018 (
.C(clk),
.D(sig00000020),
.Q(sig0000002f)
);
FD #(
.INIT ( 1'b0 ))
blk00000019 (
.C(clk),
.D(sig0000001f),
.Q(sig0000002e)
);
FD #(
.INIT ( 1'b0 ))
blk0000001a (
.C(clk),
.D(sig0000001e),
.Q(sig0000002d)
);
FD #(
.INIT ( 1'b0 ))
blk0000001b (
.C(clk),
.D(sig0000001d),
.Q(sig0000002c)
);
FD #(
.INIT ( 1'b0 ))
blk0000001c (
.C(clk),
.D(sig0000001c),
.Q(sig0000002b)
);
FD #(
.INIT ( 1'b0 ))
blk0000001d (
.C(clk),
.D(sig0000001b),
.Q(sig0000002a)
);
FD #(
.INIT ( 1'b0 ))
blk0000001e (
.C(clk),
.D(sig0000001a),
.Q(sig00000029)
);
FD #(
.INIT ( 1'b0 ))
blk0000001f (
.C(clk),
.D(sig00000019),
.Q(sig00000028)
);
FD #(
.INIT ( 1'b0 ))
blk00000020 (
.C(clk),
.D(sig00000018),
.Q(sig00000027)
);
FD #(
.INIT ( 1'b0 ))
blk00000021 (
.C(clk),
.D(sig00000017),
.Q(sig00000026)
);
FD #(
.INIT ( 1'b0 ))
blk00000022 (
.C(clk),
.D(sig00000016),
.Q(sig00000025)
);
FD #(
.INIT ( 1'b0 ))
blk00000023 (
.C(clk),
.D(sig00000015),
.Q(sig00000048)
);
FD #(
.INIT ( 1'b0 ))
blk00000024 (
.C(clk),
.D(sig00000014),
.Q(sig00000047)
);
XORCY blk0000009c (
.CI(sig0000005d),
.LI(sig0000007d),
.O(sig00000075)
);
MUXCY blk0000009d (
.CI(sig0000005d),
.DI(sig00000002),
.S(sig0000007d),
.O(sig0000005c)
);
XORCY blk0000009e (
.CI(sig0000005e),
.LI(sig0000007c),
.O(sig00000074)
);
MUXCY blk0000009f (
.CI(sig0000005e),
.DI(sig00000002),
.S(sig0000007c),
.O(sig0000005d)
);
XORCY blk000000a0 (
.CI(sig0000005f),
.LI(sig0000007b),
.O(sig00000073)
);
MUXCY blk000000a1 (
.CI(sig0000005f),
.DI(sig00000002),
.S(sig0000007b),
.O(sig0000005e)
);
XORCY blk000000a2 (
.CI(sig00000060),
.LI(sig0000007a),
.O(sig00000072)
);
MUXCY blk000000a3 (
.CI(sig00000060),
.DI(sig00000002),
.S(sig0000007a),
.O(sig0000005f)
);
XORCY blk000000a4 (
.CI(sig00000061),
.LI(sig00000079),
.O(sig00000071)
);
MUXCY blk000000a5 (
.CI(sig00000061),
.DI(sig00000002),
.S(sig00000079),
.O(sig00000060)
);
XORCY blk000000a6 (
.CI(sig00000062),
.LI(sig00000078),
.O(sig00000070)
);
MUXCY blk000000a7 (
.CI(sig00000062),
.DI(sig00000002),
.S(sig00000078),
.O(sig00000061)
);
XORCY blk000000a8 (
.CI(sig00000063),
.LI(sig00000077),
.O(sig0000006f)
);
MUXCY blk000000a9 (
.CI(sig00000063),
.DI(sig00000002),
.S(sig00000077),
.O(sig00000062)
);
XORCY blk000000aa (
.CI(sig00000064),
.LI(sig00000076),
.O(sig0000006e)
);
MUXCY blk000000ab (
.CI(sig00000064),
.DI(sig00000002),
.S(sig00000076),
.O(sig00000063)
);
MUXCY blk000000ac (
.CI(sig00000002),
.DI(sig00000001),
.S(sig00000065),
.O(sig00000064)
);
XORCY blk000000ad (
.CI(sig00000067),
.LI(sig00000094),
.O(sig0000008d)
);
MUXCY blk000000ae (
.CI(sig00000067),
.DI(sig00000002),
.S(sig00000094),
.O(sig00000066)
);
XORCY blk000000af (
.CI(sig00000068),
.LI(sig00000093),
.O(sig0000008c)
);
MUXCY blk000000b0 (
.CI(sig00000068),
.DI(sig00000002),
.S(sig00000093),
.O(sig00000067)
);
XORCY blk000000b1 (
.CI(sig00000069),
.LI(sig00000092),
.O(sig0000008b)
);
MUXCY blk000000b2 (
.CI(sig00000069),
.DI(sig00000002),
.S(sig00000092),
.O(sig00000068)
);
XORCY blk000000b3 (
.CI(sig0000006a),
.LI(sig00000091),
.O(sig0000008a)
);
MUXCY blk000000b4 (
.CI(sig0000006a),
.DI(sig00000002),
.S(sig00000091),
.O(sig00000069)
);
XORCY blk000000b5 (
.CI(sig0000006b),
.LI(sig00000090),
.O(sig00000089)
);
MUXCY blk000000b6 (
.CI(sig0000006b),
.DI(sig00000002),
.S(sig00000090),
.O(sig0000006a)
);
XORCY blk000000b7 (
.CI(sig0000006c),
.LI(sig0000008f),
.O(sig00000088)
);
MUXCY blk000000b8 (
.CI(sig0000006c),
.DI(sig00000002),
.S(sig0000008f),
.O(sig0000006b)
);
XORCY blk000000b9 (
.CI(sig0000006d),
.LI(sig0000008e),
.O(sig00000087)
);
MUXCY blk000000ba (
.CI(sig0000006d),
.DI(sig00000002),
.S(sig0000008e),
.O(sig0000006c)
);
XORCY blk000000bb (
.CI(sig00000002),
.LI(sig00000127),
.O(sig00000086)
);
MUXCY blk000000bc (
.CI(sig00000002),
.DI(sig0000009c),
.S(sig00000127),
.O(sig0000006d)
);
FD #(
.INIT ( 1'b0 ))
blk000000bd (
.C(clk),
.D(sig000000b6),
.Q(sig000000c2)
);
FD #(
.INIT ( 1'b0 ))
blk000000be (
.C(clk),
.D(sig000000b5),
.Q(sig000000c1)
);
FD #(
.INIT ( 1'b0 ))
blk000000bf (
.C(clk),
.D(sig000000b4),
.Q(sig000000c0)
);
FD #(
.INIT ( 1'b0 ))
blk000000c0 (
.C(clk),
.D(sig000000b3),
.Q(sig000000bf)
);
FD #(
.INIT ( 1'b0 ))
blk000000c1 (
.C(clk),
.D(sig000000b2),
.Q(sig000000be)
);
FD #(
.INIT ( 1'b0 ))
blk000000c2 (
.C(clk),
.D(sig000000b1),
.Q(sig000000bd)
);
FD #(
.INIT ( 1'b0 ))
blk000000c3 (
.C(clk),
.D(sig000000b0),
.Q(sig000000bc)
);
FD #(
.INIT ( 1'b0 ))
blk000000c4 (
.C(clk),
.D(sig000000af),
.Q(sig000000bb)
);
FD #(
.INIT ( 1'b0 ))
blk000000c5 (
.C(clk),
.D(sig000000ae),
.Q(sig000000ba)
);
FD #(
.INIT ( 1'b0 ))
blk000000c6 (
.C(clk),
.D(sig000000ad),
.Q(sig000000b9)
);
FD #(
.INIT ( 1'b0 ))
blk000000c7 (
.C(clk),
.D(sig000000ac),
.Q(sig000000b8)
);
FD #(
.INIT ( 1'b0 ))
blk000000c8 (
.C(clk),
.D(sig000000ab),
.Q(sig000000b7)
);
FD #(
.INIT ( 1'b0 ))
blk000000c9 (
.C(clk),
.D(sig00000124),
.Q(sig0000009c)
);
FD #(
.INIT ( 1'b0 ))
blk000000ca (
.C(clk),
.D(sig00000032),
.Q(sig00000126)
);
FD #(
.INIT ( 1'b0 ))
blk000000cb (
.C(clk),
.D(sig00000031),
.Q(sig00000125)
);
FD #(
.INIT ( 1'b0 ))
blk000000cc (
.C(clk),
.D(sig000000f8),
.Q(sig000000e8)
);
FD #(
.INIT ( 1'b0 ))
blk000000cd (
.C(clk),
.D(sig000000f7),
.Q(sig000000e7)
);
FD #(
.INIT ( 1'b0 ))
blk000000ce (
.C(clk),
.D(sig000000f6),
.Q(sig000000e6)
);
FD #(
.INIT ( 1'b0 ))
blk000000cf (
.C(clk),
.D(sig000000f5),
.Q(sig000000e5)
);
FD #(
.INIT ( 1'b0 ))
blk000000d0 (
.C(clk),
.D(sig000000f4),
.Q(sig000000e4)
);
FD #(
.INIT ( 1'b0 ))
blk000000d1 (
.C(clk),
.D(sig000000f3),
.Q(sig000000e3)
);
FD #(
.INIT ( 1'b0 ))
blk000000d2 (
.C(clk),
.D(sig000000f2),
.Q(sig000000e2)
);
FD #(
.INIT ( 1'b0 ))
blk000000d3 (
.C(clk),
.D(sig000000f1),
.Q(sig000000e1)
);
FD #(
.INIT ( 1'b0 ))
blk000000d4 (
.C(clk),
.D(sig000000a3),
.Q(sig000000f0)
);
FD #(
.INIT ( 1'b0 ))
blk000000d5 (
.C(clk),
.D(sig000000a2),
.Q(sig000000ef)
);
FD #(
.INIT ( 1'b0 ))
blk000000d6 (
.C(clk),
.D(sig000000a1),
.Q(sig000000ee)
);
FD #(
.INIT ( 1'b0 ))
blk000000d7 (
.C(clk),
.D(sig000000a0),
.Q(sig000000ed)
);
FD #(
.INIT ( 1'b0 ))
blk000000d8 (
.C(clk),
.D(sig0000009f),
.Q(sig000000ec)
);
FD #(
.INIT ( 1'b0 ))
blk000000d9 (
.C(clk),
.D(sig0000009e),
.Q(sig000000eb)
);
FD #(
.INIT ( 1'b0 ))
blk000000da (
.C(clk),
.D(sig0000009d),
.Q(sig000000ea)
);
FD #(
.INIT ( 1'b0 ))
blk000000db (
.C(clk),
.D(sig00000053),
.Q(sig000000e9)
);
FD #(
.INIT ( 1'b0 ))
blk000000dc (
.C(clk),
.D(sig00000102),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [7])
);
FD #(
.INIT ( 1'b0 ))
blk000000dd (
.C(clk),
.D(sig00000101),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [6])
);
FD #(
.INIT ( 1'b0 ))
blk000000de (
.C(clk),
.D(sig00000100),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [5])
);
FD #(
.INIT ( 1'b0 ))
blk000000df (
.C(clk),
.D(sig000000ff),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [4])
);
FD #(
.INIT ( 1'b0 ))
blk000000e0 (
.C(clk),
.D(sig000000fe),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [3])
);
FD #(
.INIT ( 1'b0 ))
blk000000e1 (
.C(clk),
.D(sig000000fd),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [2])
);
FD #(
.INIT ( 1'b0 ))
blk000000e2 (
.C(clk),
.D(sig000000fc),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [1])
);
FD #(
.INIT ( 1'b0 ))
blk000000e3 (
.C(clk),
.D(sig000000fb),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [0])
);
FD #(
.INIT ( 1'b0 ))
blk000000e4 (
.C(clk),
.D(sig000000aa),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [7])
);
FD #(
.INIT ( 1'b0 ))
blk000000e5 (
.C(clk),
.D(sig000000a9),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [6])
);
FD #(
.INIT ( 1'b0 ))
blk000000e6 (
.C(clk),
.D(sig000000a8),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [5])
);
FD #(
.INIT ( 1'b0 ))
blk000000e7 (
.C(clk),
.D(sig000000a7),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [4])
);
FD #(
.INIT ( 1'b0 ))
blk000000e8 (
.C(clk),
.D(sig000000a6),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [3])
);
FD #(
.INIT ( 1'b0 ))
blk000000e9 (
.C(clk),
.D(sig000000a5),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [2])
);
FD #(
.INIT ( 1'b0 ))
blk000000ea (
.C(clk),
.D(sig000000a4),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [1])
);
FD #(
.INIT ( 1'b0 ))
blk000000eb (
.C(clk),
.D(sig0000005b),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [0])
);
FD #(
.INIT ( 1'b0 ))
blk000000ec (
.C(clk),
.D(sig00000085),
.Q(sig0000004c)
);
FD #(
.INIT ( 1'b0 ))
blk000000ed (
.C(clk),
.D(sig00000084),
.Q(sig0000004d)
);
FD #(
.INIT ( 1'b0 ))
blk000000ee (
.C(clk),
.D(sig00000083),
.Q(sig0000004e)
);
FD #(
.INIT ( 1'b0 ))
blk000000ef (
.C(clk),
.D(sig00000082),
.Q(sig0000004f)
);
FD #(
.INIT ( 1'b0 ))
blk000000f0 (
.C(clk),
.D(sig00000081),
.Q(sig00000050)
);
FD #(
.INIT ( 1'b0 ))
blk000000f1 (
.C(clk),
.D(sig00000080),
.Q(sig00000051)
);
FD #(
.INIT ( 1'b0 ))
blk000000f2 (
.C(clk),
.D(sig0000007f),
.Q(sig00000052)
);
FD #(
.INIT ( 1'b0 ))
blk000000f3 (
.C(clk),
.D(sig0000007e),
.Q(sig000000fa)
);
FD #(
.INIT ( 1'b0 ))
blk000000f4 (
.C(clk),
.D(sig0000009c),
.Q(sig00000054)
);
FD #(
.INIT ( 1'b0 ))
blk000000f5 (
.C(clk),
.D(sig0000009b),
.Q(sig00000055)
);
FD #(
.INIT ( 1'b0 ))
blk000000f6 (
.C(clk),
.D(sig0000009a),
.Q(sig00000056)
);
FD #(
.INIT ( 1'b0 ))
blk000000f7 (
.C(clk),
.D(sig00000099),
.Q(sig00000057)
);
FD #(
.INIT ( 1'b0 ))
blk000000f8 (
.C(clk),
.D(sig00000098),
.Q(sig00000058)
);
FD #(
.INIT ( 1'b0 ))
blk000000f9 (
.C(clk),
.D(sig00000097),
.Q(sig00000059)
);
FD #(
.INIT ( 1'b0 ))
blk000000fa (
.C(clk),
.D(sig00000096),
.Q(sig0000005a)
);
FD #(
.INIT ( 1'b0 ))
blk000000fb (
.C(clk),
.D(sig00000095),
.Q(sig00000104)
);
FD #(
.INIT ( 1'b0 ))
blk000000fc (
.C(clk),
.D(sig0000005c),
.Q(sig000000f9)
);
FD #(
.INIT ( 1'b0 ))
blk000000fd (
.C(clk),
.D(sig00000075),
.Q(sig000000f8)
);
FD #(
.INIT ( 1'b0 ))
blk000000fe (
.C(clk),
.D(sig00000074),
.Q(sig000000f7)
);
FD #(
.INIT ( 1'b0 ))
blk000000ff (
.C(clk),
.D(sig00000073),
.Q(sig000000f6)
);
FD #(
.INIT ( 1'b0 ))
blk00000100 (
.C(clk),
.D(sig00000072),
.Q(sig000000f5)
);
FD #(
.INIT ( 1'b0 ))
blk00000101 (
.C(clk),
.D(sig00000071),
.Q(sig000000f4)
);
FD #(
.INIT ( 1'b0 ))
blk00000102 (
.C(clk),
.D(sig00000070),
.Q(sig000000f3)
);
FD #(
.INIT ( 1'b0 ))
blk00000103 (
.C(clk),
.D(sig0000006f),
.Q(sig000000f2)
);
FD #(
.INIT ( 1'b0 ))
blk00000104 (
.C(clk),
.D(sig0000006e),
.Q(sig000000f1)
);
FD #(
.INIT ( 1'b0 ))
blk00000105 (
.C(clk),
.D(sig00000066),
.Q(sig00000103)
);
FD #(
.INIT ( 1'b0 ))
blk00000106 (
.C(clk),
.D(sig0000008d),
.Q(sig00000102)
);
FD #(
.INIT ( 1'b0 ))
blk00000107 (
.C(clk),
.D(sig0000008c),
.Q(sig00000101)
);
FD #(
.INIT ( 1'b0 ))
blk00000108 (
.C(clk),
.D(sig0000008b),
.Q(sig00000100)
);
FD #(
.INIT ( 1'b0 ))
blk00000109 (
.C(clk),
.D(sig0000008a),
.Q(sig000000ff)
);
FD #(
.INIT ( 1'b0 ))
blk0000010a (
.C(clk),
.D(sig00000089),
.Q(sig000000fe)
);
FD #(
.INIT ( 1'b0 ))
blk0000010b (
.C(clk),
.D(sig00000088),
.Q(sig000000fd)
);
FD #(
.INIT ( 1'b0 ))
blk0000010c (
.C(clk),
.D(sig00000087),
.Q(sig000000fc)
);
FD #(
.INIT ( 1'b0 ))
blk0000010d (
.C(clk),
.D(sig00000086),
.Q(sig000000fb)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000010e (
.I0(sig00000056),
.I1(sig0000004a),
.O(sig000000a8)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000010f (
.I0(sig0000004e),
.I1(sig0000004b),
.O(sig000000a1)
);
LUT3 #(
.INIT ( 8'hA6 ))
blk00000110 (
.I0(sig00000055),
.I1(sig00000056),
.I2(sig0000004a),
.O(sig000000a9)
);
LUT3 #(
.INIT ( 8'hA6 ))
blk00000111 (
.I0(sig0000004d),
.I1(sig0000004e),
.I2(sig0000004b),
.O(sig000000a2)
);
LUT4 #(
.INIT ( 16'hAA6A ))
blk00000112 (
.I0(sig00000054),
.I1(sig00000055),
.I2(sig00000056),
.I3(sig0000004a),
.O(sig000000aa)
);
LUT4 #(
.INIT ( 16'hAA6A ))
blk00000113 (
.I0(sig0000004c),
.I1(sig0000004d),
.I2(sig0000004e),
.I3(sig0000004b),
.O(sig000000a3)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000114 (
.I0(sig00000115),
.I1(sig00000128),
.O(sig0000008e)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000115 (
.I0(sig00000116),
.I1(sig00000128),
.O(sig0000008f)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000116 (
.I0(sig00000117),
.I1(sig00000128),
.O(sig00000090)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000117 (
.I0(sig00000118),
.I1(sig00000128),
.O(sig00000091)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000118 (
.I0(sig00000119),
.I1(sig00000128),
.O(sig00000092)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000119 (
.I0(sig0000011a),
.I1(sig0000009c),
.O(sig00000093)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011a (
.I0(sig0000011b),
.I1(sig0000009c),
.O(sig00000094)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011b (
.I0(sig0000011c),
.I1(sig0000009c),
.O(sig00000095)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011c (
.I0(sig0000011d),
.I1(sig0000009c),
.O(sig00000096)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011d (
.I0(sig0000011e),
.I1(sig0000009c),
.O(sig00000097)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011e (
.I0(sig0000011f),
.I1(sig0000009c),
.O(sig00000098)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011f (
.I0(sig00000120),
.I1(sig0000009c),
.O(sig00000099)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000120 (
.I0(sig00000121),
.I1(sig0000009c),
.O(sig0000009a)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000121 (
.I0(sig00000122),
.I1(sig0000009c),
.O(sig0000009b)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000122 (
.I0(sig00000025),
.I1(sig00000031),
.O(sig000000ab)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000123 (
.I0(sig0000002f),
.I1(sig00000031),
.O(sig000000b5)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000124 (
.I0(sig00000030),
.I1(sig00000031),
.O(sig000000b6)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000125 (
.I0(sig00000026),
.I1(sig00000031),
.O(sig000000ac)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000126 (
.I0(sig00000027),
.I1(sig00000031),
.O(sig000000ad)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000127 (
.I0(sig00000028),
.I1(sig00000031),
.O(sig000000ae)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000128 (
.I0(sig00000029),
.I1(sig00000031),
.O(sig000000af)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000129 (
.I0(sig0000002a),
.I1(sig00000031),
.O(sig000000b0)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012a (
.I0(sig0000002b),
.I1(sig00000031),
.O(sig000000b1)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012b (
.I0(sig0000002c),
.I1(sig00000031),
.O(sig000000b2)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012c (
.I0(sig0000002d),
.I1(sig00000031),
.O(sig000000b3)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012d (
.I0(sig0000002e),
.I1(sig00000031),
.O(sig000000b4)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012e (
.I0(sig00000123),
.I1(sig0000009c),
.O(sig00000085)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012f (
.I0(sig000000fa),
.I1(sig000000f9),
.O(sig00000053)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000130 (
.I0(sig00000104),
.I1(sig00000103),
.O(sig0000005b)
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
blk00000131 (
.I0(sig00000057),
.I1(sig00000058),
.I2(sig00000059),
.I3(sig0000005a),
.I4(sig00000103),
.I5(sig00000104),
.O(sig0000004a)
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
blk00000132 (
.I0(sig0000004f),
.I1(sig00000050),
.I2(sig00000051),
.I3(sig00000052),
.I4(sig000000f9),
.I5(sig000000fa),
.O(sig0000004b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000133 (
.I0(sig00000128),
.I1(sig00000123),
.O(sig00000065)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000134 (
.I0(sig00000105),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000076)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000135 (
.I0(sig00000106),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000077)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000136 (
.I0(sig00000107),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000078)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000137 (
.I0(sig00000108),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000079)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000138 (
.I0(sig00000109),
.I1(sig00000128),
.I2(sig00000123),
.O(sig0000007a)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000139 (
.I0(sig0000010a),
.I1(sig00000128),
.I2(sig00000123),
.O(sig0000007b)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000013a (
.I0(sig0000010b),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007c)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000013b (
.I0(sig0000010c),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007d)
);
LUT5 #(
.INIT ( 32'h6AAAAAAA ))
blk0000013c (
.I0(sig00000058),
.I1(sig00000104),
.I2(sig00000103),
.I3(sig0000005a),
.I4(sig00000059),
.O(sig000000a6)
);
LUT6 #(
.INIT ( 64'h6AAAAAAAAAAAAAAA ))
blk0000013d (
.I0(sig00000057),
.I1(sig00000104),
.I2(sig00000103),
.I3(sig0000005a),
.I4(sig00000059),
.I5(sig00000058),
.O(sig000000a7)
);
LUT4 #(
.INIT ( 16'h6AAA ))
blk0000013e (
.I0(sig00000059),
.I1(sig00000104),
.I2(sig00000103),
.I3(sig0000005a),
.O(sig000000a5)
);
LUT5 #(
.INIT ( 32'h6AAAAAAA ))
blk0000013f (
.I0(sig00000050),
.I1(sig000000fa),
.I2(sig000000f9),
.I3(sig00000052),
.I4(sig00000051),
.O(sig0000009f)
);
LUT6 #(
.INIT ( 64'h6AAAAAAAAAAAAAAA ))
blk00000140 (
.I0(sig0000004f),
.I1(sig000000fa),
.I2(sig000000f9),
.I3(sig00000052),
.I4(sig00000051),
.I5(sig00000050),
.O(sig000000a0)
);
LUT4 #(
.INIT ( 16'h6AAA ))
blk00000141 (
.I0(sig00000051),
.I1(sig000000fa),
.I2(sig000000f9),
.I3(sig00000052),
.O(sig0000009e)
);
LUT3 #(
.INIT ( 8'h6A ))
blk00000142 (
.I0(sig00000052),
.I1(sig000000fa),
.I2(sig000000f9),
.O(sig0000009d)
);
LUT3 #(
.INIT ( 8'h6A ))
blk00000143 (
.I0(sig0000005a),
.I1(sig00000104),
.I2(sig00000103),
.O(sig000000a4)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000144 (
.I0(sig0000010d),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007e)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000145 (
.I0(sig0000010e),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007f)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000146 (
.I0(sig0000010f),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000080)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000147 (
.I0(sig00000110),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000081)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000148 (
.I0(sig00000111),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000082)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000149 (
.I0(sig00000112),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000083)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000014a (
.I0(sig00000113),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000084)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000014b (
.I0(sig00000114),
.O(sig00000127)
);
FD #(
.INIT ( 1'b0 ))
blk0000014c (
.C(clk),
.D(sig00000124),
.Q(sig00000128)
);
RAMB16BWER #(
.INIT_00 ( 256'h3332222222222222222222211111111111111111111100000000000000000000 ),
.INIT_01 ( 256'h6666665555555555555555555544444444444444444444433333333333333333 ),
.INIT_02 ( 256'h9999999998888888888888888888877777777777777777777666666666666666 ),
.INIT_03 ( 256'hCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAA999999999999 ),
.INIT_04 ( 256'hFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDCCCCCCCCC ),
.INIT_05 ( 256'h222222222222222211111111111111111111100000000000000000000FFFFFFF ),
.INIT_06 ( 256'h5555555555555555554444444444444444444443333333333333333333332222 ),
.INIT_07 ( 256'h8888888888888888888877777777777777777777766666666666666666666655 ),
.INIT_08 ( 256'hCBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAA999999999999999999998 ),
.INIT_09 ( 256'hFFEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCC ),
.INIT_0A ( 256'h222111111111111111111111000000000000000000000FFFFFFFFFFFFFFFFFFF ),
.INIT_0B ( 256'h5554444444444444444444444333333333333333333333222222222222222222 ),
.INIT_0C ( 256'h8887777777777777777777777666666666666666666666555555555555555555 ),
.INIT_0D ( 256'hBBBAAAAAAAAAAAAAAAAAAAAA9999999999999999999999888888888888888888 ),
.INIT_0E ( 256'hEDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBB ),
.INIT_0F ( 256'h0000000000000000000000FFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEE ),
.INIT_10 ( 256'h3333333333333333333222222222222222222222221111111111111111111111 ),
.INIT_11 ( 256'h6666666666666666555555555555555555555554444444444444444444444333 ),
.INIT_12 ( 256'h9999999999998888888888888888888888877777777777777777777777666666 ),
.INIT_13 ( 256'hCCCCCCCCBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAAAA9999999999 ),
.INIT_14 ( 256'hFFEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCC ),
.INIT_15 ( 256'h1111111111111111111000000000000000000000000FFFFFFFFFFFFFFFFFFFFF ),
.INIT_16 ( 256'h4444444444433333333333333333333333322222222222222222222222211111 ),
.INIT_17 ( 256'h7776666666666666666666666665555555555555555555555554444444444444 ),
.INIT_18 ( 256'h9999999999999999988888888888888888888888887777777777777777777777 ),
.INIT_19 ( 256'hCCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAAAAAAA9999999 ),
.INIT_1A ( 256'hEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCC ),
.INIT_1B ( 256'h1111100000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEE ),
.INIT_1C ( 256'h3333333333333333222222222222222222222222222111111111111111111111 ),
.INIT_1D ( 256'h5555555555555555555555555544444444444444444444444444433333333333 ),
.INIT_1E ( 256'h8888888777777777777777777777777777766666666666666666666666666665 ),
.INIT_1F ( 256'hAAAAAAAAAAAAAAA9999999999999999999999999999888888888888888888888 ),
.INIT_20 ( 256'hCCCCCCCCCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAA ),
.INIT_21 ( 256'hEEEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCC ),
.INIT_22 ( 256'h0000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEEEEE ),
.INIT_23 ( 256'h2222222222222222222222222222221111111111111111111111111111111000 ),
.INIT_24 ( 256'h4444444444444444444444444444443333333333333333333333333333333322 ),
.INIT_25 ( 256'h6666666666666666666666666665555555555555555555555555555555555444 ),
.INIT_26 ( 256'h8888888888888888888888877777777777777777777777777777777776666666 ),
.INIT_27 ( 256'hAAAAAAAAAAAAAAA9999999999999999999999999999999999998888888888888 ),
.INIT_28 ( 256'hCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAA ),
.INIT_29 ( 256'hDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC ),
.INIT_2A ( 256'hFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDD ),
.INIT_2B ( 256'h00000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2C ( 256'h2222222222222221111111111111111111111111111111111111111111100000 ),
.INIT_2D ( 256'h3333333333333333333333333333333332222222222222222222222222222222 ),
.INIT_2E ( 256'h5444444444444444444444444444444444444444444444444433333333333333 ),
.INIT_2F ( 256'h6666666666666555555555555555555555555555555555555555555555555555 ),
.INIT_30 ( 256'h7777777777777777777777766666666666666666666666666666666666666666 ),
.INIT_31 ( 256'h8888888888888888888888888888887777777777777777777777777777777777 ),
.INIT_32 ( 256'h9999999999999999999999999999999999888888888888888888888888888888 ),
.INIT_33 ( 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9999999999999999999999999999999 ),
.INIT_34 ( 256'hBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ),
.INIT_35 ( 256'hCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB ),
.INIT_36 ( 256'hCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC ),
.INIT_37 ( 256'hDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCC ),
.INIT_38 ( 256'hEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD ),
.INIT_39 ( 256'hEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE ),
.INIT_3A ( 256'hFFFFFEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE ),
.INIT_3B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk0000014d (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk0000014d_DIPA<3>_UNCONNECTED , \NLW_blk0000014d_DIPA<2>_UNCONNECTED , \NLW_blk0000014d_DIPA<1>_UNCONNECTED ,
\NLW_blk0000014d_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk0000014d_DOA<31>_UNCONNECTED , \NLW_blk0000014d_DOA<30>_UNCONNECTED , \NLW_blk0000014d_DOA<29>_UNCONNECTED ,
\NLW_blk0000014d_DOA<28>_UNCONNECTED , \NLW_blk0000014d_DOA<27>_UNCONNECTED , \NLW_blk0000014d_DOA<26>_UNCONNECTED ,
\NLW_blk0000014d_DOA<25>_UNCONNECTED , \NLW_blk0000014d_DOA<24>_UNCONNECTED , \NLW_blk0000014d_DOA<23>_UNCONNECTED ,
\NLW_blk0000014d_DOA<22>_UNCONNECTED , \NLW_blk0000014d_DOA<21>_UNCONNECTED , \NLW_blk0000014d_DOA<20>_UNCONNECTED ,
\NLW_blk0000014d_DOA<19>_UNCONNECTED , \NLW_blk0000014d_DOA<18>_UNCONNECTED , \NLW_blk0000014d_DOA<17>_UNCONNECTED ,
\NLW_blk0000014d_DOA<16>_UNCONNECTED , \NLW_blk0000014d_DOA<15>_UNCONNECTED , \NLW_blk0000014d_DOA<14>_UNCONNECTED ,
\NLW_blk0000014d_DOA<13>_UNCONNECTED , \NLW_blk0000014d_DOA<12>_UNCONNECTED , \NLW_blk0000014d_DOA<11>_UNCONNECTED ,
\NLW_blk0000014d_DOA<10>_UNCONNECTED , \NLW_blk0000014d_DOA<9>_UNCONNECTED , \NLW_blk0000014d_DOA<8>_UNCONNECTED ,
\NLW_blk0000014d_DOA<7>_UNCONNECTED , \NLW_blk0000014d_DOA<6>_UNCONNECTED , \NLW_blk0000014d_DOA<5>_UNCONNECTED , \NLW_blk0000014d_DOA<4>_UNCONNECTED
, sig000000dd, sig000000dc, sig000000db, sig000000da}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk0000014d_ADDRA<1>_UNCONNECTED , \NLW_blk0000014d_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk0000014d_ADDRB<1>_UNCONNECTED , \NLW_blk0000014d_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk0000014d_DIB<31>_UNCONNECTED , \NLW_blk0000014d_DIB<30>_UNCONNECTED , \NLW_blk0000014d_DIB<29>_UNCONNECTED ,
\NLW_blk0000014d_DIB<28>_UNCONNECTED , \NLW_blk0000014d_DIB<27>_UNCONNECTED , \NLW_blk0000014d_DIB<26>_UNCONNECTED ,
\NLW_blk0000014d_DIB<25>_UNCONNECTED , \NLW_blk0000014d_DIB<24>_UNCONNECTED , \NLW_blk0000014d_DIB<23>_UNCONNECTED ,
\NLW_blk0000014d_DIB<22>_UNCONNECTED , \NLW_blk0000014d_DIB<21>_UNCONNECTED , \NLW_blk0000014d_DIB<20>_UNCONNECTED ,
\NLW_blk0000014d_DIB<19>_UNCONNECTED , \NLW_blk0000014d_DIB<18>_UNCONNECTED , \NLW_blk0000014d_DIB<17>_UNCONNECTED ,
\NLW_blk0000014d_DIB<16>_UNCONNECTED , \NLW_blk0000014d_DIB<15>_UNCONNECTED , \NLW_blk0000014d_DIB<14>_UNCONNECTED ,
\NLW_blk0000014d_DIB<13>_UNCONNECTED , \NLW_blk0000014d_DIB<12>_UNCONNECTED , \NLW_blk0000014d_DIB<11>_UNCONNECTED ,
\NLW_blk0000014d_DIB<10>_UNCONNECTED , \NLW_blk0000014d_DIB<9>_UNCONNECTED , \NLW_blk0000014d_DIB<8>_UNCONNECTED ,
\NLW_blk0000014d_DIB<7>_UNCONNECTED , \NLW_blk0000014d_DIB<6>_UNCONNECTED , \NLW_blk0000014d_DIB<5>_UNCONNECTED , \NLW_blk0000014d_DIB<4>_UNCONNECTED
, \NLW_blk0000014d_DIB<3>_UNCONNECTED , \NLW_blk0000014d_DIB<2>_UNCONNECTED , \NLW_blk0000014d_DIB<1>_UNCONNECTED ,
\NLW_blk0000014d_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk0000014d_DOPA<3>_UNCONNECTED , \NLW_blk0000014d_DOPA<2>_UNCONNECTED , \NLW_blk0000014d_DOPA<1>_UNCONNECTED ,
\NLW_blk0000014d_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk0000014d_DIPB<3>_UNCONNECTED , \NLW_blk0000014d_DIPB<2>_UNCONNECTED , \NLW_blk0000014d_DIPB<1>_UNCONNECTED ,
\NLW_blk0000014d_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk0000014d_DOPB<3>_UNCONNECTED , \NLW_blk0000014d_DOPB<2>_UNCONNECTED , \NLW_blk0000014d_DOPB<1>_UNCONNECTED ,
\NLW_blk0000014d_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk0000014d_DOB<31>_UNCONNECTED , \NLW_blk0000014d_DOB<30>_UNCONNECTED , \NLW_blk0000014d_DOB<29>_UNCONNECTED ,
\NLW_blk0000014d_DOB<28>_UNCONNECTED , \NLW_blk0000014d_DOB<27>_UNCONNECTED , \NLW_blk0000014d_DOB<26>_UNCONNECTED ,
\NLW_blk0000014d_DOB<25>_UNCONNECTED , \NLW_blk0000014d_DOB<24>_UNCONNECTED , \NLW_blk0000014d_DOB<23>_UNCONNECTED ,
\NLW_blk0000014d_DOB<22>_UNCONNECTED , \NLW_blk0000014d_DOB<21>_UNCONNECTED , \NLW_blk0000014d_DOB<20>_UNCONNECTED ,
\NLW_blk0000014d_DOB<19>_UNCONNECTED , \NLW_blk0000014d_DOB<18>_UNCONNECTED , \NLW_blk0000014d_DOB<17>_UNCONNECTED ,
\NLW_blk0000014d_DOB<16>_UNCONNECTED , \NLW_blk0000014d_DOB<15>_UNCONNECTED , \NLW_blk0000014d_DOB<14>_UNCONNECTED ,
\NLW_blk0000014d_DOB<13>_UNCONNECTED , \NLW_blk0000014d_DOB<12>_UNCONNECTED , \NLW_blk0000014d_DOB<11>_UNCONNECTED ,
\NLW_blk0000014d_DOB<10>_UNCONNECTED , \NLW_blk0000014d_DOB<9>_UNCONNECTED , \NLW_blk0000014d_DOB<8>_UNCONNECTED ,
\NLW_blk0000014d_DOB<7>_UNCONNECTED , \NLW_blk0000014d_DOB<6>_UNCONNECTED , \NLW_blk0000014d_DOB<5>_UNCONNECTED , \NLW_blk0000014d_DOB<4>_UNCONNECTED
, sig000000ce, sig000000cd, sig000000cc, sig000000cb}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk0000014d_DIA<31>_UNCONNECTED , \NLW_blk0000014d_DIA<30>_UNCONNECTED , \NLW_blk0000014d_DIA<29>_UNCONNECTED ,
\NLW_blk0000014d_DIA<28>_UNCONNECTED , \NLW_blk0000014d_DIA<27>_UNCONNECTED , \NLW_blk0000014d_DIA<26>_UNCONNECTED ,
\NLW_blk0000014d_DIA<25>_UNCONNECTED , \NLW_blk0000014d_DIA<24>_UNCONNECTED , \NLW_blk0000014d_DIA<23>_UNCONNECTED ,
\NLW_blk0000014d_DIA<22>_UNCONNECTED , \NLW_blk0000014d_DIA<21>_UNCONNECTED , \NLW_blk0000014d_DIA<20>_UNCONNECTED ,
\NLW_blk0000014d_DIA<19>_UNCONNECTED , \NLW_blk0000014d_DIA<18>_UNCONNECTED , \NLW_blk0000014d_DIA<17>_UNCONNECTED ,
\NLW_blk0000014d_DIA<16>_UNCONNECTED , \NLW_blk0000014d_DIA<15>_UNCONNECTED , \NLW_blk0000014d_DIA<14>_UNCONNECTED ,
\NLW_blk0000014d_DIA<13>_UNCONNECTED , \NLW_blk0000014d_DIA<12>_UNCONNECTED , \NLW_blk0000014d_DIA<11>_UNCONNECTED ,
\NLW_blk0000014d_DIA<10>_UNCONNECTED , \NLW_blk0000014d_DIA<9>_UNCONNECTED , \NLW_blk0000014d_DIA<8>_UNCONNECTED ,
\NLW_blk0000014d_DIA<7>_UNCONNECTED , \NLW_blk0000014d_DIA<6>_UNCONNECTED , \NLW_blk0000014d_DIA<5>_UNCONNECTED , \NLW_blk0000014d_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
RAMB16BWER #(
.INIT_00 ( 256'h110FEDDCBAA987665432210FFEDCBBA9877654432100FEDCCBA9987655432110 ),
.INIT_01 ( 256'h432100FEDDCBA9987665432210FEEDCBBA9877654332100FEDCCBA9887655432 ),
.INIT_02 ( 256'h654332100FEDCCBA9887655432110FEEDCBAA987665433210FFEDCBBA9887654 ),
.INIT_03 ( 256'h87665432210FEEDCBBA9877654432100FEDCCBA9987655432210FEEDCBAA9877 ),
.INIT_04 ( 256'hA9877654432100FEDDCBA9987665432210FFEDCBBA9877654432100FEDDCBA99 ),
.INIT_05 ( 256'hCBA9987655432210FEEDCBBA9877654432100FEDDCBA9987665432210FEEDCBB ),
.INIT_06 ( 256'hDCCBA9987665432210FFEDCBBA9887654432110FEDDCBAA9877654332100FEDC ),
.INIT_07 ( 256'hFEDCCBA9987655432210FEEDCBBA9887654432110FEDDCBAA9877654332100FE ),
.INIT_08 ( 256'h0FEEDCBAA9877654432110FEDDCBAA9877654332100FEDDCBA9987665433210F ),
.INIT_09 ( 256'h10FEEDCBBA9887655432110FEEDCBBA9887655432110FEEDCBBA987765443211 ),
.INIT_0A ( 256'h110FEEDCBBA9887654432110FEEDCBBA9887655432110FEEDCBBA98876554322 ),
.INIT_0B ( 256'h210FFEDCCBA99876654332100FEDDCBAA9877654332100FEDDCBAA9877654432 ),
.INIT_0C ( 256'h210FFEDCCBA99876654332100FEDDCBAA9877654432110FEEDCBBA9887655432 ),
.INIT_0D ( 256'h100FEDDCBAA9877654432210FFEDCCBA99876654332100FEDDCBAA9887655432 ),
.INIT_0E ( 256'h0FFEDDCBAA9877654432210FFEDCCBA99876654432110FEEDCBBA98876654332 ),
.INIT_0F ( 256'hFEDDCBBA98876554332100FEDDCBAA98876554322100FEDDCBAA988765543221 ),
.INIT_10 ( 256'hDCCBA99877654432210FFEDDCBAA98776554322100FEDDCBAA98876554322100 ),
.INIT_11 ( 256'hBA99876654432210FFEDDCBAA98876554332100FEEDCBBA99876654432110FEE ),
.INIT_12 ( 256'h877654432210FFEDDCBBA98876654432110FFEDCCBAA98876554332100FEEDCB ),
.INIT_13 ( 256'h54322100FEEDCCBA998776554322100FEEDCCBA998776554322100FEEDCBBA99 ),
.INIT_14 ( 256'h10FFEDCCBAA98876654432210FFEDDCBBA998776544322100FEEDCBBA9987765 ),
.INIT_15 ( 256'hCBBA998776554332110FFEDCCBAA988766544322100FEEDCBBA9987765543321 ),
.INIT_16 ( 256'h76554332110FFEEDCCBAA98876654332110FFEDDCBBA998776554332110FFEDD ),
.INIT_17 ( 256'h100FEEDCCBAA988766554332110FFEDDCBBA998776554332110FFEDDCBBA9987 ),
.INIT_18 ( 256'hAA988776554332110FFEEDCCBAA988766544332110FFEDDCBBA9987766544322 ),
.INIT_19 ( 256'h332110FFEDDCCBAA988766554332110FFEEDCCBAA9887765543321100FEEDCCB ),
.INIT_1A ( 256'hBBA9987766544322110FFEDDCCBAA9887765543322100FEEDDCBBA9988766544 ),
.INIT_1B ( 256'h22110FFEEDCCBAA9987766544332110FFEEDCCBBA9987766544332110FFEEDCC ),
.INIT_1C ( 256'h9887665543322110FFEEDCCBBA99887665543322100FEEDDCBBAA98877655443 ),
.INIT_1D ( 256'hFEDDCCBAA99887665543322100FFEEDCCBBA99887665544322110FFEEDCCBBA9 ),
.INIT_1E ( 256'h3322100FFEEDCCBBAA98877665443322100FFEEDCCBBAA98877655443321100F ),
.INIT_1F ( 256'h776655433221100FEEDDCCBAA998877655443321100FFEEDCCBBAA9887766544 ),
.INIT_20 ( 256'hAA9988776654433221100FEEDDCCBBAA988776655433221100FFEDDCCBBAA988 ),
.INIT_21 ( 256'hDCCBBA9988776655443322100FFEEDDCCBBAA988776655443321100FFEEDDCCB ),
.INIT_22 ( 256'hEDDCCBBAA9988776655443322110FFEEDDCCBBAA9988776655433221100FFEED ),
.INIT_23 ( 256'hEEDDCCBBAA99887766554433221100FFEEDDCCBBAA9988776655443322110FFE ),
.INIT_24 ( 256'hEDDCCBBAA998877665544433221100FFEEDDCCBBAA99887766554433221100FF ),
.INIT_25 ( 256'hCCBBAA998877766554433221100FFEEEDDCCBBAA998877665544433221100FFE ),
.INIT_26 ( 256'hA9988776665544332211100FFEEDDCCBBBAA998877665554433221100FFFEEDD ),
.INIT_27 ( 256'h665544333221100FFFEEDDCCCBBAA9988877665544433221100FFFEEDDCCBBBA ),
.INIT_28 ( 256'h11100FFFEEDDCCCBBAA999887766655443332211000FFEEDDDCCBBAAA9988776 ),
.INIT_29 ( 256'hCBBBAA9998877766555443322211000FFEEEDDCCBBBAA9998877766554443322 ),
.INIT_2A ( 256'h554443322211100FFFEEDDDCCBBBAA9998877766555443332211100FFFEEDDDC ),
.INIT_2B ( 256'hDDDCCCBBAAA999887776665544433322111000FFEEEDDCCCBBBAA99988777666 ),
.INIT_2C ( 256'h544433222111000FFFEEDDDCCCBBBAA9998887776655544433322111000FFFEE ),
.INIT_2D ( 256'hBAAA99988877766655544433222111000FFFEEEDDDCCCBBBAA99988877766655 ),
.INIT_2E ( 256'h0FFFEEEDDDCCCBBBAAA9998888777666555444333222111000FFFEEEDDDCCCBB ),
.INIT_2F ( 256'h3332222111000FFFFEEEDDDCCCBBBBAAA9998887776666555444333222111100 ),
.INIT_30 ( 256'h66555544433332221111000FFFFEEEDDDDCCCBBBBAAA99988887776665555444 ),
.INIT_31 ( 256'h877776665555444433322221111000FFFFEEEEDDDCCCCBBBBAAA999988877776 ),
.INIT_32 ( 256'h8877776666555544443333222211110000FFFFEEEEDDDDCCCCBBBAAAA9999888 ),
.INIT_33 ( 256'h777666665555444433332222211110000FFFFEEEEEDDDDCCCCBBBBAAAA999988 ),
.INIT_34 ( 256'h555444443333322222111100000FFFFEEEEEDDDDDCCCCBBBBBAAAA9999888887 ),
.INIT_35 ( 256'h2221111100000FFFFFEEEEEDDDDDCCCCCBBBBBAAAAA999998888877777666665 ),
.INIT_36 ( 256'hEDDDDDDCCCCCBBBBBBAAAAAA9999988888877777666666555554444433333322 ),
.INIT_37 ( 256'h88887777776666665555555444444333333222222111111000000FFFFFFEEEEE ),
.INIT_38 ( 256'h1111110000000FFFFFFFEEEEEEEDDDDDDDCCCCCCCBBBBBBBAAAAAA9999999888 ),
.INIT_39 ( 256'h9999998888888887777777766666666555555554444444433333333222222211 ),
.INIT_3A ( 256'h00000FFFFFFFFFFEEEEEEEEEEDDDDDDDDDDCCCCCCCCCBBBBBBBBBAAAAAAAAA99 ),
.INIT_3B ( 256'h6555555555555444444444444333333333333222222222221111111111100000 ),
.INIT_3C ( 256'hAAAAAA9999999999999999888888888888888777777777777776666666666666 ),
.INIT_3D ( 256'hDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAA ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDD ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk0000014e (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk0000014e_DIPA<3>_UNCONNECTED , \NLW_blk0000014e_DIPA<2>_UNCONNECTED , \NLW_blk0000014e_DIPA<1>_UNCONNECTED ,
\NLW_blk0000014e_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk0000014e_DOA<31>_UNCONNECTED , \NLW_blk0000014e_DOA<30>_UNCONNECTED , \NLW_blk0000014e_DOA<29>_UNCONNECTED ,
\NLW_blk0000014e_DOA<28>_UNCONNECTED , \NLW_blk0000014e_DOA<27>_UNCONNECTED , \NLW_blk0000014e_DOA<26>_UNCONNECTED ,
\NLW_blk0000014e_DOA<25>_UNCONNECTED , \NLW_blk0000014e_DOA<24>_UNCONNECTED , \NLW_blk0000014e_DOA<23>_UNCONNECTED ,
\NLW_blk0000014e_DOA<22>_UNCONNECTED , \NLW_blk0000014e_DOA<21>_UNCONNECTED , \NLW_blk0000014e_DOA<20>_UNCONNECTED ,
\NLW_blk0000014e_DOA<19>_UNCONNECTED , \NLW_blk0000014e_DOA<18>_UNCONNECTED , \NLW_blk0000014e_DOA<17>_UNCONNECTED ,
\NLW_blk0000014e_DOA<16>_UNCONNECTED , \NLW_blk0000014e_DOA<15>_UNCONNECTED , \NLW_blk0000014e_DOA<14>_UNCONNECTED ,
\NLW_blk0000014e_DOA<13>_UNCONNECTED , \NLW_blk0000014e_DOA<12>_UNCONNECTED , \NLW_blk0000014e_DOA<11>_UNCONNECTED ,
\NLW_blk0000014e_DOA<10>_UNCONNECTED , \NLW_blk0000014e_DOA<9>_UNCONNECTED , \NLW_blk0000014e_DOA<8>_UNCONNECTED ,
\NLW_blk0000014e_DOA<7>_UNCONNECTED , \NLW_blk0000014e_DOA<6>_UNCONNECTED , \NLW_blk0000014e_DOA<5>_UNCONNECTED , \NLW_blk0000014e_DOA<4>_UNCONNECTED
, sig000000d9, sig000000d8, sig000000d7, sig000000d6}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk0000014e_ADDRA<1>_UNCONNECTED , \NLW_blk0000014e_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk0000014e_ADDRB<1>_UNCONNECTED , \NLW_blk0000014e_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk0000014e_DIB<31>_UNCONNECTED , \NLW_blk0000014e_DIB<30>_UNCONNECTED , \NLW_blk0000014e_DIB<29>_UNCONNECTED ,
\NLW_blk0000014e_DIB<28>_UNCONNECTED , \NLW_blk0000014e_DIB<27>_UNCONNECTED , \NLW_blk0000014e_DIB<26>_UNCONNECTED ,
\NLW_blk0000014e_DIB<25>_UNCONNECTED , \NLW_blk0000014e_DIB<24>_UNCONNECTED , \NLW_blk0000014e_DIB<23>_UNCONNECTED ,
\NLW_blk0000014e_DIB<22>_UNCONNECTED , \NLW_blk0000014e_DIB<21>_UNCONNECTED , \NLW_blk0000014e_DIB<20>_UNCONNECTED ,
\NLW_blk0000014e_DIB<19>_UNCONNECTED , \NLW_blk0000014e_DIB<18>_UNCONNECTED , \NLW_blk0000014e_DIB<17>_UNCONNECTED ,
\NLW_blk0000014e_DIB<16>_UNCONNECTED , \NLW_blk0000014e_DIB<15>_UNCONNECTED , \NLW_blk0000014e_DIB<14>_UNCONNECTED ,
\NLW_blk0000014e_DIB<13>_UNCONNECTED , \NLW_blk0000014e_DIB<12>_UNCONNECTED , \NLW_blk0000014e_DIB<11>_UNCONNECTED ,
\NLW_blk0000014e_DIB<10>_UNCONNECTED , \NLW_blk0000014e_DIB<9>_UNCONNECTED , \NLW_blk0000014e_DIB<8>_UNCONNECTED ,
\NLW_blk0000014e_DIB<7>_UNCONNECTED , \NLW_blk0000014e_DIB<6>_UNCONNECTED , \NLW_blk0000014e_DIB<5>_UNCONNECTED , \NLW_blk0000014e_DIB<4>_UNCONNECTED
, \NLW_blk0000014e_DIB<3>_UNCONNECTED , \NLW_blk0000014e_DIB<2>_UNCONNECTED , \NLW_blk0000014e_DIB<1>_UNCONNECTED ,
\NLW_blk0000014e_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk0000014e_DOPA<3>_UNCONNECTED , \NLW_blk0000014e_DOPA<2>_UNCONNECTED , \NLW_blk0000014e_DOPA<1>_UNCONNECTED ,
\NLW_blk0000014e_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk0000014e_DIPB<3>_UNCONNECTED , \NLW_blk0000014e_DIPB<2>_UNCONNECTED , \NLW_blk0000014e_DIPB<1>_UNCONNECTED ,
\NLW_blk0000014e_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk0000014e_DOPB<3>_UNCONNECTED , \NLW_blk0000014e_DOPB<2>_UNCONNECTED , \NLW_blk0000014e_DOPB<1>_UNCONNECTED ,
\NLW_blk0000014e_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk0000014e_DOB<31>_UNCONNECTED , \NLW_blk0000014e_DOB<30>_UNCONNECTED , \NLW_blk0000014e_DOB<29>_UNCONNECTED ,
\NLW_blk0000014e_DOB<28>_UNCONNECTED , \NLW_blk0000014e_DOB<27>_UNCONNECTED , \NLW_blk0000014e_DOB<26>_UNCONNECTED ,
\NLW_blk0000014e_DOB<25>_UNCONNECTED , \NLW_blk0000014e_DOB<24>_UNCONNECTED , \NLW_blk0000014e_DOB<23>_UNCONNECTED ,
\NLW_blk0000014e_DOB<22>_UNCONNECTED , \NLW_blk0000014e_DOB<21>_UNCONNECTED , \NLW_blk0000014e_DOB<20>_UNCONNECTED ,
\NLW_blk0000014e_DOB<19>_UNCONNECTED , \NLW_blk0000014e_DOB<18>_UNCONNECTED , \NLW_blk0000014e_DOB<17>_UNCONNECTED ,
\NLW_blk0000014e_DOB<16>_UNCONNECTED , \NLW_blk0000014e_DOB<15>_UNCONNECTED , \NLW_blk0000014e_DOB<14>_UNCONNECTED ,
\NLW_blk0000014e_DOB<13>_UNCONNECTED , \NLW_blk0000014e_DOB<12>_UNCONNECTED , \NLW_blk0000014e_DOB<11>_UNCONNECTED ,
\NLW_blk0000014e_DOB<10>_UNCONNECTED , \NLW_blk0000014e_DOB<9>_UNCONNECTED , \NLW_blk0000014e_DOB<8>_UNCONNECTED ,
\NLW_blk0000014e_DOB<7>_UNCONNECTED , \NLW_blk0000014e_DOB<6>_UNCONNECTED , \NLW_blk0000014e_DOB<5>_UNCONNECTED , \NLW_blk0000014e_DOB<4>_UNCONNECTED
, sig000000ca, sig000000c9, sig000000c8, sig000000c7}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk0000014e_DIA<31>_UNCONNECTED , \NLW_blk0000014e_DIA<30>_UNCONNECTED , \NLW_blk0000014e_DIA<29>_UNCONNECTED ,
\NLW_blk0000014e_DIA<28>_UNCONNECTED , \NLW_blk0000014e_DIA<27>_UNCONNECTED , \NLW_blk0000014e_DIA<26>_UNCONNECTED ,
\NLW_blk0000014e_DIA<25>_UNCONNECTED , \NLW_blk0000014e_DIA<24>_UNCONNECTED , \NLW_blk0000014e_DIA<23>_UNCONNECTED ,
\NLW_blk0000014e_DIA<22>_UNCONNECTED , \NLW_blk0000014e_DIA<21>_UNCONNECTED , \NLW_blk0000014e_DIA<20>_UNCONNECTED ,
\NLW_blk0000014e_DIA<19>_UNCONNECTED , \NLW_blk0000014e_DIA<18>_UNCONNECTED , \NLW_blk0000014e_DIA<17>_UNCONNECTED ,
\NLW_blk0000014e_DIA<16>_UNCONNECTED , \NLW_blk0000014e_DIA<15>_UNCONNECTED , \NLW_blk0000014e_DIA<14>_UNCONNECTED ,
\NLW_blk0000014e_DIA<13>_UNCONNECTED , \NLW_blk0000014e_DIA<12>_UNCONNECTED , \NLW_blk0000014e_DIA<11>_UNCONNECTED ,
\NLW_blk0000014e_DIA<10>_UNCONNECTED , \NLW_blk0000014e_DIA<9>_UNCONNECTED , \NLW_blk0000014e_DIA<8>_UNCONNECTED ,
\NLW_blk0000014e_DIA<7>_UNCONNECTED , \NLW_blk0000014e_DIA<6>_UNCONNECTED , \NLW_blk0000014e_DIA<5>_UNCONNECTED , \NLW_blk0000014e_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
RAMB16BWER #(
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h1111111111111111111111111111111111111111111111111111111110000000 ),
.INIT_06 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_07 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_08 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_09 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_0A ( 256'h2222222222222222222222222222222222222222222221111111111111111111 ),
.INIT_0B ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0C ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0D ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0E ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0F ( 256'h3333333333333333333333222222222222222222222222222222222222222222 ),
.INIT_10 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_11 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_12 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_13 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_14 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_15 ( 256'h4444444444444444444444444444444444444444444333333333333333333333 ),
.INIT_16 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_17 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_18 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_19 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_1A ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_1B ( 256'h5555555555555555555555555555555444444444444444444444444444444444 ),
.INIT_1C ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_1D ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_1E ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_1F ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_20 ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_21 ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_22 ( 256'h6666666666666666666666666666555555555555555555555555555555555555 ),
.INIT_23 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_24 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_25 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_26 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_27 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_28 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_29 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_2A ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_2B ( 256'h7777777777777777777777777777777777777766666666666666666666666666 ),
.INIT_2C ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_2D ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_2E ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_2F ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_30 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_31 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_32 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_33 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_34 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_35 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_36 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_37 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_38 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_39 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3A ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3B ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3C ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3D ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3E ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3F ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_A ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_B ( 36'h000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk0000014f (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk0000014f_DIPA<3>_UNCONNECTED , \NLW_blk0000014f_DIPA<2>_UNCONNECTED , \NLW_blk0000014f_DIPA<1>_UNCONNECTED ,
\NLW_blk0000014f_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk0000014f_DOA<31>_UNCONNECTED , \NLW_blk0000014f_DOA<30>_UNCONNECTED , \NLW_blk0000014f_DOA<29>_UNCONNECTED ,
\NLW_blk0000014f_DOA<28>_UNCONNECTED , \NLW_blk0000014f_DOA<27>_UNCONNECTED , \NLW_blk0000014f_DOA<26>_UNCONNECTED ,
\NLW_blk0000014f_DOA<25>_UNCONNECTED , \NLW_blk0000014f_DOA<24>_UNCONNECTED , \NLW_blk0000014f_DOA<23>_UNCONNECTED ,
\NLW_blk0000014f_DOA<22>_UNCONNECTED , \NLW_blk0000014f_DOA<21>_UNCONNECTED , \NLW_blk0000014f_DOA<20>_UNCONNECTED ,
\NLW_blk0000014f_DOA<19>_UNCONNECTED , \NLW_blk0000014f_DOA<18>_UNCONNECTED , \NLW_blk0000014f_DOA<17>_UNCONNECTED ,
\NLW_blk0000014f_DOA<16>_UNCONNECTED , \NLW_blk0000014f_DOA<15>_UNCONNECTED , \NLW_blk0000014f_DOA<14>_UNCONNECTED ,
\NLW_blk0000014f_DOA<13>_UNCONNECTED , \NLW_blk0000014f_DOA<12>_UNCONNECTED , \NLW_blk0000014f_DOA<11>_UNCONNECTED ,
\NLW_blk0000014f_DOA<10>_UNCONNECTED , \NLW_blk0000014f_DOA<9>_UNCONNECTED , \NLW_blk0000014f_DOA<8>_UNCONNECTED ,
\NLW_blk0000014f_DOA<7>_UNCONNECTED , \NLW_blk0000014f_DOA<6>_UNCONNECTED , \NLW_blk0000014f_DOA<5>_UNCONNECTED , \NLW_blk0000014f_DOA<4>_UNCONNECTED
, \NLW_blk0000014f_DOA<3>_UNCONNECTED , sig000000e0, sig000000df, sig000000de}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk0000014f_ADDRA<1>_UNCONNECTED , \NLW_blk0000014f_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk0000014f_ADDRB<1>_UNCONNECTED , \NLW_blk0000014f_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk0000014f_DIB<31>_UNCONNECTED , \NLW_blk0000014f_DIB<30>_UNCONNECTED , \NLW_blk0000014f_DIB<29>_UNCONNECTED ,
\NLW_blk0000014f_DIB<28>_UNCONNECTED , \NLW_blk0000014f_DIB<27>_UNCONNECTED , \NLW_blk0000014f_DIB<26>_UNCONNECTED ,
\NLW_blk0000014f_DIB<25>_UNCONNECTED , \NLW_blk0000014f_DIB<24>_UNCONNECTED , \NLW_blk0000014f_DIB<23>_UNCONNECTED ,
\NLW_blk0000014f_DIB<22>_UNCONNECTED , \NLW_blk0000014f_DIB<21>_UNCONNECTED , \NLW_blk0000014f_DIB<20>_UNCONNECTED ,
\NLW_blk0000014f_DIB<19>_UNCONNECTED , \NLW_blk0000014f_DIB<18>_UNCONNECTED , \NLW_blk0000014f_DIB<17>_UNCONNECTED ,
\NLW_blk0000014f_DIB<16>_UNCONNECTED , \NLW_blk0000014f_DIB<15>_UNCONNECTED , \NLW_blk0000014f_DIB<14>_UNCONNECTED ,
\NLW_blk0000014f_DIB<13>_UNCONNECTED , \NLW_blk0000014f_DIB<12>_UNCONNECTED , \NLW_blk0000014f_DIB<11>_UNCONNECTED ,
\NLW_blk0000014f_DIB<10>_UNCONNECTED , \NLW_blk0000014f_DIB<9>_UNCONNECTED , \NLW_blk0000014f_DIB<8>_UNCONNECTED ,
\NLW_blk0000014f_DIB<7>_UNCONNECTED , \NLW_blk0000014f_DIB<6>_UNCONNECTED , \NLW_blk0000014f_DIB<5>_UNCONNECTED , \NLW_blk0000014f_DIB<4>_UNCONNECTED
, \NLW_blk0000014f_DIB<3>_UNCONNECTED , \NLW_blk0000014f_DIB<2>_UNCONNECTED , \NLW_blk0000014f_DIB<1>_UNCONNECTED ,
\NLW_blk0000014f_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk0000014f_DOPA<3>_UNCONNECTED , \NLW_blk0000014f_DOPA<2>_UNCONNECTED , \NLW_blk0000014f_DOPA<1>_UNCONNECTED ,
\NLW_blk0000014f_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk0000014f_DIPB<3>_UNCONNECTED , \NLW_blk0000014f_DIPB<2>_UNCONNECTED , \NLW_blk0000014f_DIPB<1>_UNCONNECTED ,
\NLW_blk0000014f_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk0000014f_DOPB<3>_UNCONNECTED , \NLW_blk0000014f_DOPB<2>_UNCONNECTED , \NLW_blk0000014f_DOPB<1>_UNCONNECTED ,
\NLW_blk0000014f_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk0000014f_DOB<31>_UNCONNECTED , \NLW_blk0000014f_DOB<30>_UNCONNECTED , \NLW_blk0000014f_DOB<29>_UNCONNECTED ,
\NLW_blk0000014f_DOB<28>_UNCONNECTED , \NLW_blk0000014f_DOB<27>_UNCONNECTED , \NLW_blk0000014f_DOB<26>_UNCONNECTED ,
\NLW_blk0000014f_DOB<25>_UNCONNECTED , \NLW_blk0000014f_DOB<24>_UNCONNECTED , \NLW_blk0000014f_DOB<23>_UNCONNECTED ,
\NLW_blk0000014f_DOB<22>_UNCONNECTED , \NLW_blk0000014f_DOB<21>_UNCONNECTED , \NLW_blk0000014f_DOB<20>_UNCONNECTED ,
\NLW_blk0000014f_DOB<19>_UNCONNECTED , \NLW_blk0000014f_DOB<18>_UNCONNECTED , \NLW_blk0000014f_DOB<17>_UNCONNECTED ,
\NLW_blk0000014f_DOB<16>_UNCONNECTED , \NLW_blk0000014f_DOB<15>_UNCONNECTED , \NLW_blk0000014f_DOB<14>_UNCONNECTED ,
\NLW_blk0000014f_DOB<13>_UNCONNECTED , \NLW_blk0000014f_DOB<12>_UNCONNECTED , \NLW_blk0000014f_DOB<11>_UNCONNECTED ,
\NLW_blk0000014f_DOB<10>_UNCONNECTED , \NLW_blk0000014f_DOB<9>_UNCONNECTED , \NLW_blk0000014f_DOB<8>_UNCONNECTED ,
\NLW_blk0000014f_DOB<7>_UNCONNECTED , \NLW_blk0000014f_DOB<6>_UNCONNECTED , \NLW_blk0000014f_DOB<5>_UNCONNECTED , \NLW_blk0000014f_DOB<4>_UNCONNECTED
, \NLW_blk0000014f_DOB<3>_UNCONNECTED , sig000000d1, sig000000d0, sig000000cf}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk0000014f_DIA<31>_UNCONNECTED , \NLW_blk0000014f_DIA<30>_UNCONNECTED , \NLW_blk0000014f_DIA<29>_UNCONNECTED ,
\NLW_blk0000014f_DIA<28>_UNCONNECTED , \NLW_blk0000014f_DIA<27>_UNCONNECTED , \NLW_blk0000014f_DIA<26>_UNCONNECTED ,
\NLW_blk0000014f_DIA<25>_UNCONNECTED , \NLW_blk0000014f_DIA<24>_UNCONNECTED , \NLW_blk0000014f_DIA<23>_UNCONNECTED ,
\NLW_blk0000014f_DIA<22>_UNCONNECTED , \NLW_blk0000014f_DIA<21>_UNCONNECTED , \NLW_blk0000014f_DIA<20>_UNCONNECTED ,
\NLW_blk0000014f_DIA<19>_UNCONNECTED , \NLW_blk0000014f_DIA<18>_UNCONNECTED , \NLW_blk0000014f_DIA<17>_UNCONNECTED ,
\NLW_blk0000014f_DIA<16>_UNCONNECTED , \NLW_blk0000014f_DIA<15>_UNCONNECTED , \NLW_blk0000014f_DIA<14>_UNCONNECTED ,
\NLW_blk0000014f_DIA<13>_UNCONNECTED , \NLW_blk0000014f_DIA<12>_UNCONNECTED , \NLW_blk0000014f_DIA<11>_UNCONNECTED ,
\NLW_blk0000014f_DIA<10>_UNCONNECTED , \NLW_blk0000014f_DIA<9>_UNCONNECTED , \NLW_blk0000014f_DIA<8>_UNCONNECTED ,
\NLW_blk0000014f_DIA<7>_UNCONNECTED , \NLW_blk0000014f_DIA<6>_UNCONNECTED , \NLW_blk0000014f_DIA<5>_UNCONNECTED , \NLW_blk0000014f_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
RAMB16BWER #(
.INIT_00 ( 256'hE158CF269D047BE158CF369D047BE258CF36AD047BE258CF36AD147BE259CF36 ),
.INIT_01 ( 256'h158CF36AD147BE259C036AD148BF259C037AE148BF269C037AE158BF269D047A ),
.INIT_02 ( 256'h48BF259C037AE158CF369D047BE259C036AD148BF269C037AE158CF269D047BE ),
.INIT_03 ( 256'h59C037AE158CF36AD148BF269D047BE158CF36AD148BF269D047BE158CF36AD1 ),
.INIT_04 ( 256'h58CF36AD148BF26AD148BF269D047BE259C037AE158CF36AD148BF269D047BE2 ),
.INIT_05 ( 256'h259C037BE259C037BE259C037BE259C037BE259C037AE259C037AE158CF37AE1 ),
.INIT_06 ( 256'hCF36AE158C037BE259D047BF269D148BF36AD148CF36AE158C037AE159C037AE ),
.INIT_07 ( 256'h26AD158C037BE269D148BF36AE159C047BF26AD148CF37AE259C047BF269D148 ),
.INIT_08 ( 256'h59C048BF37AE259D148C037BE26AD158C037BF26AD158C047BF26AD158C037BE ),
.INIT_09 ( 256'h37BF36AE269D159C048CF37BF26AE159D148C037BF26AE159D048CF37BE26AD1 ),
.INIT_0A ( 256'hD159D048C048C037BF37BE26AE269D159D148C048BF37BF26AE269D159D048C0 ),
.INIT_0B ( 256'h159D159D159D159D159D159D048C048C048C048BF37BF37BF36AE26AE26AD159 ),
.INIT_0C ( 256'h048C049D159D159D159D159D159D159E26AE26AE26AE26AE26AE26AE26AE26AD ),
.INIT_0D ( 256'h9D159D26AE26BF37BF38C048C049D159D15AE26AE26AE37BF37BF37B048C048C ),
.INIT_0E ( 256'hAF37C048D159E26AF37B048C159D16AE27BF37C048D159D26AE26BF37B048C04 ),
.INIT_0F ( 256'h5AE27B048D15AE27B048D15AE27BF48C159E26BF38C059D26AE37B048C159E26 ),
.INIT_10 ( 256'h8D16AF38C15AE37C059E27B049D16AF38C15AE27B049D16AF38C059E26BF48C1 ),
.INIT_11 ( 256'h48D26BF49D27B049E27B059E27C059E27C059E27C059E27B059E27B049D26BF4 ),
.INIT_12 ( 256'h6B059E38C16BF49E27C15AF48D26B059E37C16AF48D26B049E27C05AE38C16AF ),
.INIT_13 ( 256'h05AF49E38C16B05AF48D27C16AF49E38C16B059E38D26B05AE38D26B05AE38D2 ),
.INIT_14 ( 256'h16B05AF49E38D28D27C16B05AF49E38D27C16B05AF48D27C16B05AF49E38D16B ),
.INIT_15 ( 256'h8D27D27C17C16B16B05A05AF49F49E38E38D27C17C16B05AF5AF49E38D27D27C ),
.INIT_16 ( 256'h4AF5AF5AF5AF5A05A05A05A05A05AF5AF5AF5AF4AF4AF49F49E49E39E38E38D2 ),
.INIT_17 ( 256'h7C27D28D38E39F4AF5A05B06B16B16C17C27D28D28D38E39E39E49E49F49F4AF ),
.INIT_18 ( 256'hE49F5A06C17D28E39F4A05B16C27D38E49F4A05B16C17D28D39E49F5A05B06B1 ),
.INIT_19 ( 256'hA05B17D39F5A06C28E39F5B17C28E4AF5B17C28E49F5B16C28D39F4A06B17D28 ),
.INIT_1A ( 256'hA06C28E4A07D39F5B17D39F5B17D39F5B17D39F5B17D39F5B17D38E4A06C28E4 ),
.INIT_1B ( 256'hE4A17D3A06C39F5C28E5B17D4A06C39F5B28E4A07D39F5C28E4A07D39F5B17E4 ),
.INIT_1C ( 256'h5C29F5C29F6C3906C3906D3906D3906D3906C3906C39F6C29F5C28F5B28E5B17 ),
.INIT_1D ( 256'h06D4A18E5C2906D4A18E5B29F6C3A07D4B18E5B29F6C3906D3A17E4B18E5B28F ),
.INIT_1E ( 256'hD4B28F6D4B29F6D4B29F6D4B28F6D4A18F6C3A17E5C2907D4B28F6D3A17E5C29 ),
.INIT_1F ( 256'hD4B2907E5C4B2907E5C3A18F6D4B2907E6D3A18F6D4B2907E5C3A18F6D3A18F6 ),
.INIT_20 ( 256'hE6D4C3A2908F6D5C3B2908F6D5C3A2907E6D4B3A18F6E5C3A2907E5C4B2907E6 ),
.INIT_21 ( 256'h291808F7E6D5C4B3A291807F6E5D4C3A291807E6D5C4B2A1907F6D5C4B2A1807 ),
.INIT_22 ( 256'h7E6E6E5D5D4C4C3B3B2A29191808F7F6E6D5D4C4B3B2A291808F7E6E5D4C4B3A ),
.INIT_23 ( 256'hC4D5D5D5D5D5D5C4C4C4C4C4C4C4C4C4B3B3B3B3B2A2A2A29191919080807F7F ),
.INIT_24 ( 256'h3B4C4C5D5D6E6E6F7F7F808081919192A2A2A2B3B3B3B3B3C4C4C4C4C4C4C4C4 ),
.INIT_25 ( 256'hA3B4C5D6E7F808192A3B4C5D5E6F7F809192A2B3C4C5D5E6E7F70809191A2A3B ),
.INIT_26 ( 256'h1A3C4D6F7092A3C4D6E7091A3B4D5E6F8092A3C4D5E7F8091A3B4C5D6E708192 ),
.INIT_27 ( 256'h81A3C5E7092B4D6F81A3C5E7092A3C5E7092A3C5E7081A3C5D6F81A2B4D6E709 ),
.INIT_28 ( 256'hF82B4D7092C5E71A3C5F81A3D6F81A4D6F81A4D6F81A3C5F81A3C5E7092B4D6F ),
.INIT_29 ( 256'h5F82B5E81B4E71A4D70A3C6F92C5F81B4E70A3D6F92B5E71A4D6092B5E71A3D6 ),
.INIT_2A ( 256'hA4E81B5F82C6093D70A4D71B4E81B5E82B5F82C5F92C6F92C6F92C6F92C5F82C ),
.INIT_2B ( 256'hE82C60A4F93D71B5F93D71B5F93D60A4E82C60A4E81B5F93D71A4E82C5F93D70 ),
.INIT_2C ( 256'h1B50A4F93E82C71B60A4F93D82C61B5FA4E82D71B5FA4E82C61B5F93D72C60A4 ),
.INIT_2D ( 256'h1C71C61C61B61B60B50B50A5FA4F94E93E83D82D71C61B60A5FA4E93E82D71C6 ),
.INIT_2E ( 256'h0B61C72D82D83E94E94FA4FA50B50B60B61B61C61C71C71C72C72C72C72C72C7 ),
.INIT_2F ( 256'hD94FA50C72D83FA50B61C73E94FA50B61C72D83E94FA50B61C72D83E94FA50B6 ),
.INIT_30 ( 256'h84FB62D84FB62D84FB61D84FA61C83EA50C72E940B61D83FA50C72D94FA51C72 ),
.INIT_31 ( 256'h1C840B73EA62D950C84FB72EA51D84FB72E951C83FB62D940C73EA51C83FA61D ),
.INIT_32 ( 256'h62EA62FB73FB73FB73FB62EA62EA62EA62E951D951D840C840B73FB62EA61D95 ),
.INIT_33 ( 256'h962EB730C851D962EB73FC840D951DA62EB73FB740C840D951D951DA62EA62EA ),
.INIT_34 ( 256'h963FC952EB841DA730C952FB841DA63FC851EA730C851EA730C851EA63FB841D ),
.INIT_35 ( 256'h730DA741EB852EB852FC852FC952FC962FC952FC952FC852EB851EB741DA730D ),
.INIT_36 ( 256'h0EB8530DA752FC9741EB8630DA741FC9630DA741FC9630DA741EB852FC9630DA ),
.INIT_37 ( 256'h7520DB8631EC9742FDA8530DB8631EB9641EC9741FC9741FC9741FC9641EB963 ),
.INIT_38 ( 256'hB86420EB97530ECA8531FCA8631FCA8631FCA8531ECA7530EB9742FDB8631FCA ),
.INIT_39 ( 256'hA97531FDCA86420ECA86531FDB97531FDB97531FDB97530ECA86420EC97531FD ),
.INIT_3A ( 256'h75421FDCA976421FECA975420FDBA865310ECB975420EDB976420EDB975420EC ),
.INIT_3B ( 256'h0EDCB98764320FEDBA9765321FEDBA8764310FDCA9865320FDCA9764310EDBA8 ),
.INIT_3C ( 256'h543210FEDCBA9876543210FEDCBA987654210FEDCBA87654320FEDCB98765321 ),
.INIT_3D ( 256'h66544322100FEEDCCBAA9877655432110FEEDCBAA987655432100FEDCBA98876 ),
.INIT_3E ( 256'h44333222111000FFEEEDDCCCBBAA998887766554433221100FEEDDCCBAA99877 ),
.INIT_3F ( 256'hEEEEEEEEEEEEEEDDDDDDDDDDDCCCCCCCBBBBBBAAAAA999998888777766655554 ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk00000150 (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk00000150_DIPA<3>_UNCONNECTED , \NLW_blk00000150_DIPA<2>_UNCONNECTED , \NLW_blk00000150_DIPA<1>_UNCONNECTED ,
\NLW_blk00000150_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk00000150_DOA<31>_UNCONNECTED , \NLW_blk00000150_DOA<30>_UNCONNECTED , \NLW_blk00000150_DOA<29>_UNCONNECTED ,
\NLW_blk00000150_DOA<28>_UNCONNECTED , \NLW_blk00000150_DOA<27>_UNCONNECTED , \NLW_blk00000150_DOA<26>_UNCONNECTED ,
\NLW_blk00000150_DOA<25>_UNCONNECTED , \NLW_blk00000150_DOA<24>_UNCONNECTED , \NLW_blk00000150_DOA<23>_UNCONNECTED ,
\NLW_blk00000150_DOA<22>_UNCONNECTED , \NLW_blk00000150_DOA<21>_UNCONNECTED , \NLW_blk00000150_DOA<20>_UNCONNECTED ,
\NLW_blk00000150_DOA<19>_UNCONNECTED , \NLW_blk00000150_DOA<18>_UNCONNECTED , \NLW_blk00000150_DOA<17>_UNCONNECTED ,
\NLW_blk00000150_DOA<16>_UNCONNECTED , \NLW_blk00000150_DOA<15>_UNCONNECTED , \NLW_blk00000150_DOA<14>_UNCONNECTED ,
\NLW_blk00000150_DOA<13>_UNCONNECTED , \NLW_blk00000150_DOA<12>_UNCONNECTED , \NLW_blk00000150_DOA<11>_UNCONNECTED ,
\NLW_blk00000150_DOA<10>_UNCONNECTED , \NLW_blk00000150_DOA<9>_UNCONNECTED , \NLW_blk00000150_DOA<8>_UNCONNECTED ,
\NLW_blk00000150_DOA<7>_UNCONNECTED , \NLW_blk00000150_DOA<6>_UNCONNECTED , \NLW_blk00000150_DOA<5>_UNCONNECTED , \NLW_blk00000150_DOA<4>_UNCONNECTED
, sig000000d5, sig000000d4, sig000000d3, sig000000d2}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk00000150_ADDRA<1>_UNCONNECTED , \NLW_blk00000150_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk00000150_ADDRB<1>_UNCONNECTED , \NLW_blk00000150_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk00000150_DIB<31>_UNCONNECTED , \NLW_blk00000150_DIB<30>_UNCONNECTED , \NLW_blk00000150_DIB<29>_UNCONNECTED ,
\NLW_blk00000150_DIB<28>_UNCONNECTED , \NLW_blk00000150_DIB<27>_UNCONNECTED , \NLW_blk00000150_DIB<26>_UNCONNECTED ,
\NLW_blk00000150_DIB<25>_UNCONNECTED , \NLW_blk00000150_DIB<24>_UNCONNECTED , \NLW_blk00000150_DIB<23>_UNCONNECTED ,
\NLW_blk00000150_DIB<22>_UNCONNECTED , \NLW_blk00000150_DIB<21>_UNCONNECTED , \NLW_blk00000150_DIB<20>_UNCONNECTED ,
\NLW_blk00000150_DIB<19>_UNCONNECTED , \NLW_blk00000150_DIB<18>_UNCONNECTED , \NLW_blk00000150_DIB<17>_UNCONNECTED ,
\NLW_blk00000150_DIB<16>_UNCONNECTED , \NLW_blk00000150_DIB<15>_UNCONNECTED , \NLW_blk00000150_DIB<14>_UNCONNECTED ,
\NLW_blk00000150_DIB<13>_UNCONNECTED , \NLW_blk00000150_DIB<12>_UNCONNECTED , \NLW_blk00000150_DIB<11>_UNCONNECTED ,
\NLW_blk00000150_DIB<10>_UNCONNECTED , \NLW_blk00000150_DIB<9>_UNCONNECTED , \NLW_blk00000150_DIB<8>_UNCONNECTED ,
\NLW_blk00000150_DIB<7>_UNCONNECTED , \NLW_blk00000150_DIB<6>_UNCONNECTED , \NLW_blk00000150_DIB<5>_UNCONNECTED , \NLW_blk00000150_DIB<4>_UNCONNECTED
, \NLW_blk00000150_DIB<3>_UNCONNECTED , \NLW_blk00000150_DIB<2>_UNCONNECTED , \NLW_blk00000150_DIB<1>_UNCONNECTED ,
\NLW_blk00000150_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk00000150_DOPA<3>_UNCONNECTED , \NLW_blk00000150_DOPA<2>_UNCONNECTED , \NLW_blk00000150_DOPA<1>_UNCONNECTED ,
\NLW_blk00000150_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000150_DIPB<3>_UNCONNECTED , \NLW_blk00000150_DIPB<2>_UNCONNECTED , \NLW_blk00000150_DIPB<1>_UNCONNECTED ,
\NLW_blk00000150_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000150_DOPB<3>_UNCONNECTED , \NLW_blk00000150_DOPB<2>_UNCONNECTED , \NLW_blk00000150_DOPB<1>_UNCONNECTED ,
\NLW_blk00000150_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000150_DOB<31>_UNCONNECTED , \NLW_blk00000150_DOB<30>_UNCONNECTED , \NLW_blk00000150_DOB<29>_UNCONNECTED ,
\NLW_blk00000150_DOB<28>_UNCONNECTED , \NLW_blk00000150_DOB<27>_UNCONNECTED , \NLW_blk00000150_DOB<26>_UNCONNECTED ,
\NLW_blk00000150_DOB<25>_UNCONNECTED , \NLW_blk00000150_DOB<24>_UNCONNECTED , \NLW_blk00000150_DOB<23>_UNCONNECTED ,
\NLW_blk00000150_DOB<22>_UNCONNECTED , \NLW_blk00000150_DOB<21>_UNCONNECTED , \NLW_blk00000150_DOB<20>_UNCONNECTED ,
\NLW_blk00000150_DOB<19>_UNCONNECTED , \NLW_blk00000150_DOB<18>_UNCONNECTED , \NLW_blk00000150_DOB<17>_UNCONNECTED ,
\NLW_blk00000150_DOB<16>_UNCONNECTED , \NLW_blk00000150_DOB<15>_UNCONNECTED , \NLW_blk00000150_DOB<14>_UNCONNECTED ,
\NLW_blk00000150_DOB<13>_UNCONNECTED , \NLW_blk00000150_DOB<12>_UNCONNECTED , \NLW_blk00000150_DOB<11>_UNCONNECTED ,
\NLW_blk00000150_DOB<10>_UNCONNECTED , \NLW_blk00000150_DOB<9>_UNCONNECTED , \NLW_blk00000150_DOB<8>_UNCONNECTED ,
\NLW_blk00000150_DOB<7>_UNCONNECTED , \NLW_blk00000150_DOB<6>_UNCONNECTED , \NLW_blk00000150_DOB<5>_UNCONNECTED , \NLW_blk00000150_DOB<4>_UNCONNECTED
, sig000000c6, sig000000c5, sig000000c4, sig000000c3}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk00000150_DIA<31>_UNCONNECTED , \NLW_blk00000150_DIA<30>_UNCONNECTED , \NLW_blk00000150_DIA<29>_UNCONNECTED ,
\NLW_blk00000150_DIA<28>_UNCONNECTED , \NLW_blk00000150_DIA<27>_UNCONNECTED , \NLW_blk00000150_DIA<26>_UNCONNECTED ,
\NLW_blk00000150_DIA<25>_UNCONNECTED , \NLW_blk00000150_DIA<24>_UNCONNECTED , \NLW_blk00000150_DIA<23>_UNCONNECTED ,
\NLW_blk00000150_DIA<22>_UNCONNECTED , \NLW_blk00000150_DIA<21>_UNCONNECTED , \NLW_blk00000150_DIA<20>_UNCONNECTED ,
\NLW_blk00000150_DIA<19>_UNCONNECTED , \NLW_blk00000150_DIA<18>_UNCONNECTED , \NLW_blk00000150_DIA<17>_UNCONNECTED ,
\NLW_blk00000150_DIA<16>_UNCONNECTED , \NLW_blk00000150_DIA<15>_UNCONNECTED , \NLW_blk00000150_DIA<14>_UNCONNECTED ,
\NLW_blk00000150_DIA<13>_UNCONNECTED , \NLW_blk00000150_DIA<12>_UNCONNECTED , \NLW_blk00000150_DIA<11>_UNCONNECTED ,
\NLW_blk00000150_DIA<10>_UNCONNECTED , \NLW_blk00000150_DIA<9>_UNCONNECTED , \NLW_blk00000150_DIA<8>_UNCONNECTED ,
\NLW_blk00000150_DIA<7>_UNCONNECTED , \NLW_blk00000150_DIA<6>_UNCONNECTED , \NLW_blk00000150_DIA<5>_UNCONNECTED , \NLW_blk00000150_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000151 (
.A0(sig00000001),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig00000125),
.Q(sig00000129),
.Q15(NLW_blk00000151_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000152 (
.C(clk),
.CE(sig00000001),
.D(sig00000129),
.Q(sig00000123)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000153 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig00000126),
.Q(sig0000012a),
.Q15(NLW_blk00000153_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000154 (
.C(clk),
.CE(sig00000001),
.D(sig0000012a),
.Q(sig00000124)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000155 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d1),
.Q(sig0000012b),
.Q15(NLW_blk00000155_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000156 (
.C(clk),
.CE(sig00000001),
.D(sig0000012b),
.Q(sig00000113)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000157 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d0),
.Q(sig0000012c),
.Q15(NLW_blk00000157_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000158 (
.C(clk),
.CE(sig00000001),
.D(sig0000012c),
.Q(sig00000112)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000159 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cf),
.Q(sig0000012d),
.Q15(NLW_blk00000159_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015a (
.C(clk),
.CE(sig00000001),
.D(sig0000012d),
.Q(sig00000111)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000015b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000ce),
.Q(sig0000012e),
.Q15(NLW_blk0000015b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015c (
.C(clk),
.CE(sig00000001),
.D(sig0000012e),
.Q(sig00000110)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000015d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cd),
.Q(sig0000012f),
.Q15(NLW_blk0000015d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015e (
.C(clk),
.CE(sig00000001),
.D(sig0000012f),
.Q(sig0000010f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000015f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cc),
.Q(sig00000130),
.Q15(NLW_blk0000015f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000160 (
.C(clk),
.CE(sig00000001),
.D(sig00000130),
.Q(sig0000010e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000161 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cb),
.Q(sig00000131),
.Q15(NLW_blk00000161_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000162 (
.C(clk),
.CE(sig00000001),
.D(sig00000131),
.Q(sig0000010d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000163 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000ca),
.Q(sig00000132),
.Q15(NLW_blk00000163_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000164 (
.C(clk),
.CE(sig00000001),
.D(sig00000132),
.Q(sig0000010c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000165 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c9),
.Q(sig00000133),
.Q15(NLW_blk00000165_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000166 (
.C(clk),
.CE(sig00000001),
.D(sig00000133),
.Q(sig0000010b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000167 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c8),
.Q(sig00000134),
.Q15(NLW_blk00000167_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000168 (
.C(clk),
.CE(sig00000001),
.D(sig00000134),
.Q(sig0000010a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000169 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c7),
.Q(sig00000135),
.Q15(NLW_blk00000169_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016a (
.C(clk),
.CE(sig00000001),
.D(sig00000135),
.Q(sig00000109)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000016b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c6),
.Q(sig00000136),
.Q15(NLW_blk0000016b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016c (
.C(clk),
.CE(sig00000001),
.D(sig00000136),
.Q(sig00000108)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000016d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c5),
.Q(sig00000137),
.Q15(NLW_blk0000016d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016e (
.C(clk),
.CE(sig00000001),
.D(sig00000137),
.Q(sig00000107)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000016f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c4),
.Q(sig00000138),
.Q15(NLW_blk0000016f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000170 (
.C(clk),
.CE(sig00000001),
.D(sig00000138),
.Q(sig00000106)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000171 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c3),
.Q(sig00000139),
.Q15(NLW_blk00000171_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000172 (
.C(clk),
.CE(sig00000001),
.D(sig00000139),
.Q(sig00000105)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000173 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000e0),
.Q(sig0000013a),
.Q15(NLW_blk00000173_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000174 (
.C(clk),
.CE(sig00000001),
.D(sig0000013a),
.Q(sig00000122)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000175 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000df),
.Q(sig0000013b),
.Q15(NLW_blk00000175_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000176 (
.C(clk),
.CE(sig00000001),
.D(sig0000013b),
.Q(sig00000121)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000177 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000de),
.Q(sig0000013c),
.Q15(NLW_blk00000177_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000178 (
.C(clk),
.CE(sig00000001),
.D(sig0000013c),
.Q(sig00000120)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000179 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000dd),
.Q(sig0000013d),
.Q15(NLW_blk00000179_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017a (
.C(clk),
.CE(sig00000001),
.D(sig0000013d),
.Q(sig0000011f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000017b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000dc),
.Q(sig0000013e),
.Q15(NLW_blk0000017b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017c (
.C(clk),
.CE(sig00000001),
.D(sig0000013e),
.Q(sig0000011e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000017d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000db),
.Q(sig0000013f),
.Q15(NLW_blk0000017d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017e (
.C(clk),
.CE(sig00000001),
.D(sig0000013f),
.Q(sig0000011d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000017f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000da),
.Q(sig00000140),
.Q15(NLW_blk0000017f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000180 (
.C(clk),
.CE(sig00000001),
.D(sig00000140),
.Q(sig0000011c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000181 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d9),
.Q(sig00000141),
.Q15(NLW_blk00000181_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000182 (
.C(clk),
.CE(sig00000001),
.D(sig00000141),
.Q(sig0000011b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000183 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d8),
.Q(sig00000142),
.Q15(NLW_blk00000183_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000184 (
.C(clk),
.CE(sig00000001),
.D(sig00000142),
.Q(sig0000011a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000185 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d7),
.Q(sig00000143),
.Q15(NLW_blk00000185_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000186 (
.C(clk),
.CE(sig00000001),
.D(sig00000143),
.Q(sig00000119)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000187 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d6),
.Q(sig00000144),
.Q15(NLW_blk00000187_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000188 (
.C(clk),
.CE(sig00000001),
.D(sig00000144),
.Q(sig00000118)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000189 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d5),
.Q(sig00000145),
.Q15(NLW_blk00000189_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018a (
.C(clk),
.CE(sig00000001),
.D(sig00000145),
.Q(sig00000117)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000018b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d4),
.Q(sig00000146),
.Q15(NLW_blk0000018b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018c (
.C(clk),
.CE(sig00000001),
.D(sig00000146),
.Q(sig00000116)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000018d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d3),
.Q(sig00000147),
.Q15(NLW_blk0000018d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018e (
.C(clk),
.CE(sig00000001),
.D(sig00000147),
.Q(sig00000115)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000018f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d2),
.Q(sig00000148),
.Q15(NLW_blk0000018f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000190 (
.C(clk),
.CE(sig00000001),
.D(sig00000148),
.Q(sig00000114)
);
XORCY \blk00000025/blk00000055 (
.CI(\blk00000025/sig00000197 ),
.LI(\blk00000025/sig00000198 ),
.O(sig00000004)
);
MUXCY \blk00000025/blk00000054 (
.CI(\blk00000025/sig00000197 ),
.DI(sig00000045),
.S(\blk00000025/sig00000198 ),
.O(sig00000003)
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000053 (
.I0(sig00000045),
.I1(sig00000002),
.O(\blk00000025/sig00000198 )
);
XORCY \blk00000025/blk00000052 (
.CI(\blk00000025/sig00000195 ),
.LI(\blk00000025/sig00000196 ),
.O(sig00000005)
);
MUXCY \blk00000025/blk00000051 (
.CI(\blk00000025/sig00000195 ),
.DI(sig00000044),
.S(\blk00000025/sig00000196 ),
.O(\blk00000025/sig00000197 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000050 (
.I0(sig00000044),
.I1(sig00000002),
.O(\blk00000025/sig00000196 )
);
XORCY \blk00000025/blk0000004f (
.CI(\blk00000025/sig00000193 ),
.LI(\blk00000025/sig00000194 ),
.O(sig00000006)
);
MUXCY \blk00000025/blk0000004e (
.CI(\blk00000025/sig00000193 ),
.DI(sig00000043),
.S(\blk00000025/sig00000194 ),
.O(\blk00000025/sig00000195 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000004d (
.I0(sig00000043),
.I1(sig00000002),
.O(\blk00000025/sig00000194 )
);
XORCY \blk00000025/blk0000004c (
.CI(\blk00000025/sig00000191 ),
.LI(\blk00000025/sig00000192 ),
.O(sig00000007)
);
MUXCY \blk00000025/blk0000004b (
.CI(\blk00000025/sig00000191 ),
.DI(sig00000042),
.S(\blk00000025/sig00000192 ),
.O(\blk00000025/sig00000193 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000004a (
.I0(sig00000042),
.I1(sig00000002),
.O(\blk00000025/sig00000192 )
);
XORCY \blk00000025/blk00000049 (
.CI(\blk00000025/sig0000018f ),
.LI(\blk00000025/sig00000190 ),
.O(sig00000008)
);
MUXCY \blk00000025/blk00000048 (
.CI(\blk00000025/sig0000018f ),
.DI(sig00000041),
.S(\blk00000025/sig00000190 ),
.O(\blk00000025/sig00000191 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000047 (
.I0(sig00000041),
.I1(sig00000002),
.O(\blk00000025/sig00000190 )
);
XORCY \blk00000025/blk00000046 (
.CI(\blk00000025/sig0000018d ),
.LI(\blk00000025/sig0000018e ),
.O(sig00000009)
);
MUXCY \blk00000025/blk00000045 (
.CI(\blk00000025/sig0000018d ),
.DI(sig00000040),
.S(\blk00000025/sig0000018e ),
.O(\blk00000025/sig0000018f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000044 (
.I0(sig00000040),
.I1(sig00000002),
.O(\blk00000025/sig0000018e )
);
XORCY \blk00000025/blk00000043 (
.CI(\blk00000025/sig0000018b ),
.LI(\blk00000025/sig0000018c ),
.O(sig0000000a)
);
MUXCY \blk00000025/blk00000042 (
.CI(\blk00000025/sig0000018b ),
.DI(sig0000003f),
.S(\blk00000025/sig0000018c ),
.O(\blk00000025/sig0000018d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000041 (
.I0(sig0000003f),
.I1(sig00000002),
.O(\blk00000025/sig0000018c )
);
XORCY \blk00000025/blk00000040 (
.CI(\blk00000025/sig00000189 ),
.LI(\blk00000025/sig0000018a ),
.O(sig0000000b)
);
MUXCY \blk00000025/blk0000003f (
.CI(\blk00000025/sig00000189 ),
.DI(sig0000003e),
.S(\blk00000025/sig0000018a ),
.O(\blk00000025/sig0000018b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000003e (
.I0(sig0000003e),
.I1(sig00000001),
.O(\blk00000025/sig0000018a )
);
XORCY \blk00000025/blk0000003d (
.CI(\blk00000025/sig00000187 ),
.LI(\blk00000025/sig00000188 ),
.O(sig0000000c)
);
MUXCY \blk00000025/blk0000003c (
.CI(\blk00000025/sig00000187 ),
.DI(sig0000003d),
.S(\blk00000025/sig00000188 ),
.O(\blk00000025/sig00000189 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000003b (
.I0(sig0000003d),
.I1(sig00000001),
.O(\blk00000025/sig00000188 )
);
XORCY \blk00000025/blk0000003a (
.CI(\blk00000025/sig00000185 ),
.LI(\blk00000025/sig00000186 ),
.O(sig0000000d)
);
MUXCY \blk00000025/blk00000039 (
.CI(\blk00000025/sig00000185 ),
.DI(sig0000003c),
.S(\blk00000025/sig00000186 ),
.O(\blk00000025/sig00000187 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000038 (
.I0(sig0000003c),
.I1(sig00000002),
.O(\blk00000025/sig00000186 )
);
XORCY \blk00000025/blk00000037 (
.CI(\blk00000025/sig00000183 ),
.LI(\blk00000025/sig00000184 ),
.O(sig0000000e)
);
MUXCY \blk00000025/blk00000036 (
.CI(\blk00000025/sig00000183 ),
.DI(sig0000003b),
.S(\blk00000025/sig00000184 ),
.O(\blk00000025/sig00000185 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000035 (
.I0(sig0000003b),
.I1(sig00000002),
.O(\blk00000025/sig00000184 )
);
XORCY \blk00000025/blk00000034 (
.CI(\blk00000025/sig00000181 ),
.LI(\blk00000025/sig00000182 ),
.O(sig0000000f)
);
MUXCY \blk00000025/blk00000033 (
.CI(\blk00000025/sig00000181 ),
.DI(sig0000003a),
.S(\blk00000025/sig00000182 ),
.O(\blk00000025/sig00000183 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000032 (
.I0(sig00000002),
.I1(sig0000003a),
.O(\blk00000025/sig00000182 )
);
XORCY \blk00000025/blk00000031 (
.CI(\blk00000025/sig0000017f ),
.LI(\blk00000025/sig00000180 ),
.O(sig00000010)
);
MUXCY \blk00000025/blk00000030 (
.CI(\blk00000025/sig0000017f ),
.DI(sig00000039),
.S(\blk00000025/sig00000180 ),
.O(\blk00000025/sig00000181 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000002f (
.I0(sig00000001),
.I1(sig00000039),
.O(\blk00000025/sig00000180 )
);
XORCY \blk00000025/blk0000002e (
.CI(\blk00000025/sig0000017d ),
.LI(\blk00000025/sig0000017e ),
.O(sig00000011)
);
MUXCY \blk00000025/blk0000002d (
.CI(\blk00000025/sig0000017d ),
.DI(sig00000038),
.S(\blk00000025/sig0000017e ),
.O(\blk00000025/sig0000017f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000002c (
.I0(sig00000002),
.I1(sig00000038),
.O(\blk00000025/sig0000017e )
);
XORCY \blk00000025/blk0000002b (
.CI(\blk00000025/sig0000017b ),
.LI(\blk00000025/sig0000017c ),
.O(sig00000012)
);
MUXCY \blk00000025/blk0000002a (
.CI(\blk00000025/sig0000017b ),
.DI(sig00000037),
.S(\blk00000025/sig0000017c ),
.O(\blk00000025/sig0000017d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000029 (
.I0(sig00000001),
.I1(sig00000037),
.O(\blk00000025/sig0000017c )
);
XORCY \blk00000025/blk00000028 (
.CI(sig00000002),
.LI(\blk00000025/sig0000017a ),
.O(sig00000013)
);
MUXCY \blk00000025/blk00000027 (
.CI(sig00000002),
.DI(sig00000036),
.S(\blk00000025/sig0000017a ),
.O(\blk00000025/sig0000017b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000026 (
.I0(sig00000002),
.I1(sig00000036),
.O(\blk00000025/sig0000017a )
);
XORCY \blk00000056/blk00000086 (
.CI(\blk00000056/sig000001e8 ),
.LI(\blk00000056/sig000001e9 ),
.O(sig00000023)
);
MUXCY \blk00000056/blk00000085 (
.CI(\blk00000056/sig000001e8 ),
.DI(sig00000045),
.S(\blk00000056/sig000001e9 ),
.O(sig00000024)
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000084 (
.I0(sig00000045),
.I1(sig00000035),
.O(\blk00000056/sig000001e9 )
);
XORCY \blk00000056/blk00000083 (
.CI(\blk00000056/sig000001e6 ),
.LI(\blk00000056/sig000001e7 ),
.O(sig00000022)
);
MUXCY \blk00000056/blk00000082 (
.CI(\blk00000056/sig000001e6 ),
.DI(sig00000044),
.S(\blk00000056/sig000001e7 ),
.O(\blk00000056/sig000001e8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000081 (
.I0(sig00000044),
.I1(sig00000035),
.O(\blk00000056/sig000001e7 )
);
XORCY \blk00000056/blk00000080 (
.CI(\blk00000056/sig000001e4 ),
.LI(\blk00000056/sig000001e5 ),
.O(sig00000021)
);
MUXCY \blk00000056/blk0000007f (
.CI(\blk00000056/sig000001e4 ),
.DI(sig00000043),
.S(\blk00000056/sig000001e5 ),
.O(\blk00000056/sig000001e6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000007e (
.I0(sig00000043),
.I1(sig00000035),
.O(\blk00000056/sig000001e5 )
);
XORCY \blk00000056/blk0000007d (
.CI(\blk00000056/sig000001e2 ),
.LI(\blk00000056/sig000001e3 ),
.O(sig00000020)
);
MUXCY \blk00000056/blk0000007c (
.CI(\blk00000056/sig000001e2 ),
.DI(sig00000042),
.S(\blk00000056/sig000001e3 ),
.O(\blk00000056/sig000001e4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000007b (
.I0(sig00000042),
.I1(sig00000035),
.O(\blk00000056/sig000001e3 )
);
XORCY \blk00000056/blk0000007a (
.CI(\blk00000056/sig000001e0 ),
.LI(\blk00000056/sig000001e1 ),
.O(sig0000001f)
);
MUXCY \blk00000056/blk00000079 (
.CI(\blk00000056/sig000001e0 ),
.DI(sig00000041),
.S(\blk00000056/sig000001e1 ),
.O(\blk00000056/sig000001e2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000078 (
.I0(sig00000041),
.I1(sig00000035),
.O(\blk00000056/sig000001e1 )
);
XORCY \blk00000056/blk00000077 (
.CI(\blk00000056/sig000001de ),
.LI(\blk00000056/sig000001df ),
.O(sig0000001e)
);
MUXCY \blk00000056/blk00000076 (
.CI(\blk00000056/sig000001de ),
.DI(sig00000040),
.S(\blk00000056/sig000001df ),
.O(\blk00000056/sig000001e0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000075 (
.I0(sig00000040),
.I1(sig00000035),
.O(\blk00000056/sig000001df )
);
XORCY \blk00000056/blk00000074 (
.CI(\blk00000056/sig000001dc ),
.LI(\blk00000056/sig000001dd ),
.O(sig0000001d)
);
MUXCY \blk00000056/blk00000073 (
.CI(\blk00000056/sig000001dc ),
.DI(sig0000003f),
.S(\blk00000056/sig000001dd ),
.O(\blk00000056/sig000001de )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000072 (
.I0(sig0000003f),
.I1(sig00000035),
.O(\blk00000056/sig000001dd )
);
XORCY \blk00000056/blk00000071 (
.CI(\blk00000056/sig000001da ),
.LI(\blk00000056/sig000001db ),
.O(sig0000001c)
);
MUXCY \blk00000056/blk00000070 (
.CI(\blk00000056/sig000001da ),
.DI(sig0000003e),
.S(\blk00000056/sig000001db ),
.O(\blk00000056/sig000001dc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000006f (
.I0(sig0000003e),
.I1(sig00000035),
.O(\blk00000056/sig000001db )
);
XORCY \blk00000056/blk0000006e (
.CI(\blk00000056/sig000001d8 ),
.LI(\blk00000056/sig000001d9 ),
.O(sig0000001b)
);
MUXCY \blk00000056/blk0000006d (
.CI(\blk00000056/sig000001d8 ),
.DI(sig0000003d),
.S(\blk00000056/sig000001d9 ),
.O(\blk00000056/sig000001da )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000006c (
.I0(sig0000003d),
.I1(sig00000035),
.O(\blk00000056/sig000001d9 )
);
XORCY \blk00000056/blk0000006b (
.CI(\blk00000056/sig000001d6 ),
.LI(\blk00000056/sig000001d7 ),
.O(sig0000001a)
);
MUXCY \blk00000056/blk0000006a (
.CI(\blk00000056/sig000001d6 ),
.DI(sig0000003c),
.S(\blk00000056/sig000001d7 ),
.O(\blk00000056/sig000001d8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000069 (
.I0(sig0000003c),
.I1(sig00000035),
.O(\blk00000056/sig000001d7 )
);
XORCY \blk00000056/blk00000068 (
.CI(\blk00000056/sig000001d4 ),
.LI(\blk00000056/sig000001d5 ),
.O(sig00000019)
);
MUXCY \blk00000056/blk00000067 (
.CI(\blk00000056/sig000001d4 ),
.DI(sig0000003b),
.S(\blk00000056/sig000001d5 ),
.O(\blk00000056/sig000001d6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000066 (
.I0(sig0000003b),
.I1(sig00000035),
.O(\blk00000056/sig000001d5 )
);
XORCY \blk00000056/blk00000065 (
.CI(\blk00000056/sig000001d2 ),
.LI(\blk00000056/sig000001d3 ),
.O(sig00000018)
);
MUXCY \blk00000056/blk00000064 (
.CI(\blk00000056/sig000001d2 ),
.DI(sig0000003a),
.S(\blk00000056/sig000001d3 ),
.O(\blk00000056/sig000001d4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000063 (
.I0(sig0000003a),
.I1(sig00000035),
.O(\blk00000056/sig000001d3 )
);
XORCY \blk00000056/blk00000062 (
.CI(\blk00000056/sig000001d0 ),
.LI(\blk00000056/sig000001d1 ),
.O(sig00000017)
);
MUXCY \blk00000056/blk00000061 (
.CI(\blk00000056/sig000001d0 ),
.DI(sig00000039),
.S(\blk00000056/sig000001d1 ),
.O(\blk00000056/sig000001d2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000060 (
.I0(sig00000039),
.I1(sig00000035),
.O(\blk00000056/sig000001d1 )
);
XORCY \blk00000056/blk0000005f (
.CI(\blk00000056/sig000001ce ),
.LI(\blk00000056/sig000001cf ),
.O(sig00000016)
);
MUXCY \blk00000056/blk0000005e (
.CI(\blk00000056/sig000001ce ),
.DI(sig00000038),
.S(\blk00000056/sig000001cf ),
.O(\blk00000056/sig000001d0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000005d (
.I0(sig00000038),
.I1(sig00000035),
.O(\blk00000056/sig000001cf )
);
XORCY \blk00000056/blk0000005c (
.CI(\blk00000056/sig000001cc ),
.LI(\blk00000056/sig000001cd ),
.O(sig00000015)
);
MUXCY \blk00000056/blk0000005b (
.CI(\blk00000056/sig000001cc ),
.DI(sig00000037),
.S(\blk00000056/sig000001cd ),
.O(\blk00000056/sig000001ce )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000005a (
.I0(sig00000037),
.I1(sig00000034),
.O(\blk00000056/sig000001cd )
);
XORCY \blk00000056/blk00000059 (
.CI(sig00000002),
.LI(\blk00000056/sig000001cb ),
.O(sig00000014)
);
MUXCY \blk00000056/blk00000058 (
.CI(sig00000002),
.DI(sig00000036),
.S(\blk00000056/sig000001cb ),
.O(\blk00000056/sig000001cc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000057 (
.I0(sig00000036),
.I1(sig00000033),
.O(\blk00000056/sig000001cb )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk0000009b (
.I0(\blk00000087/sig000001f1 ),
.I1(\blk00000087/sig000001f0 ),
.O(\blk00000087/sig000001ff )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000087/blk0000009a (
.I0(sig00000033),
.I1(\blk00000087/sig000001f1 ),
.I2(\blk00000087/sig000001f0 ),
.O(\blk00000087/sig000001f8 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000099 (
.I0(\blk00000087/sig000001ef ),
.I1(\blk00000087/sig000001ee ),
.O(\blk00000087/sig000001fe )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000087/blk00000098 (
.I0(sig00000034),
.I1(\blk00000087/sig000001ef ),
.I2(\blk00000087/sig000001ee ),
.O(\blk00000087/sig000001f7 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000097 (
.I0(\blk00000087/sig000001ec ),
.I1(\blk00000087/sig000001ed ),
.O(\blk00000087/sig000001fd )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000087/blk00000096 (
.I0(sig00000035),
.I1(\blk00000087/sig000001ec ),
.I2(\blk00000087/sig000001ed ),
.O(\blk00000087/sig000001f6 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000095 (
.I0(sig00000033),
.I1(\blk00000087/sig000001f2 ),
.O(\blk00000087/sig000001fc )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000094 (
.I0(sig00000035),
.I1(\blk00000087/sig000001ef ),
.O(\blk00000087/sig000001fa )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000093 (
.I0(\blk00000087/sig000001f2 ),
.I1(\blk00000087/sig000001ed ),
.O(\blk00000087/sig000001f9 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000092 (
.I0(sig00000034),
.I1(\blk00000087/sig000001f1 ),
.O(\blk00000087/sig000001fb )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000091 (
.C(clk),
.D(\blk00000087/sig000001fd ),
.Q(\blk00000087/sig000001ec )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000090 (
.C(clk),
.D(\blk00000087/sig000001fe ),
.Q(\blk00000087/sig000001ee )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008f (
.C(clk),
.D(\blk00000087/sig000001ff ),
.Q(\blk00000087/sig000001f0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008e (
.C(clk),
.D(\blk00000087/sig000001f9 ),
.Q(\blk00000087/sig000001ed )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008d (
.C(clk),
.D(\blk00000087/sig000001fa ),
.Q(\blk00000087/sig000001ef )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008c (
.C(clk),
.D(\blk00000087/sig000001fb ),
.Q(\blk00000087/sig000001f1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008b (
.C(clk),
.D(\blk00000087/sig000001fc ),
.Q(\blk00000087/sig000001f2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008a (
.C(clk),
.D(\blk00000087/sig000001f6 ),
.Q(sig00000035)
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000089 (
.C(clk),
.D(\blk00000087/sig000001f7 ),
.Q(sig00000034)
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000088 (
.C(clk),
.D(\blk00000087/sig000001f8 ),
.Q(sig00000033)
);
// synthesis translate_on
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module sky130_fd_sc_hd__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module ip_design_nco_0_0(s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_AWVALID, s_axi_AXILiteS_AWREADY, s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB, s_axi_AXILiteS_WVALID, s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_BRESP, s_axi_AXILiteS_BVALID, s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_ARADDR, s_axi_AXILiteS_ARVALID, s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_RDATA, s_axi_AXILiteS_RRESP, s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY, ap_clk, ap_rst_n)
/* synthesis syn_black_box black_box_pad_pin="s_axi_AXILiteS_AWADDR[5:0],s_axi_AXILiteS_AWVALID,s_axi_AXILiteS_AWREADY,s_axi_AXILiteS_WDATA[31:0],s_axi_AXILiteS_WSTRB[3:0],s_axi_AXILiteS_WVALID,s_axi_AXILiteS_WREADY,s_axi_AXILiteS_BRESP[1:0],s_axi_AXILiteS_BVALID,s_axi_AXILiteS_BREADY,s_axi_AXILiteS_ARADDR[5:0],s_axi_AXILiteS_ARVALID,s_axi_AXILiteS_ARREADY,s_axi_AXILiteS_RDATA[31:0],s_axi_AXILiteS_RRESP[1:0],s_axi_AXILiteS_RVALID,s_axi_AXILiteS_RREADY,ap_clk,ap_rst_n" */;
input [5:0]s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [31:0]s_axi_AXILiteS_WDATA;
input [3:0]s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
output [1:0]s_axi_AXILiteS_BRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
input [5:0]s_axi_AXILiteS_ARADDR;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
output [31:0]s_axi_AXILiteS_RDATA;
output [1:0]s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
input ap_clk;
input ap_rst_n;
endmodule |
module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clock = 0;
#5 clock = 1;
// Period = 10 clock cycles
end
// ============================================================
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clock)
begin
if(rset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=rr;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 2nd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c<=0;
r_e1<=0;
r_b1<=0;
end
else
begin
rr_c<=r_c;
r_e1<=r_e;
r_b1<=r_b;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 3rd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c1<=0;
r_cx1<=0;
r_b2<=0;
end
else
begin
rr_c1<=rr_c;
r_cx1<=r_cx;
r_b2<=r_b1;
end
end
// ------------------------------------------------------------
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
error_level=8'd5;
rset=1;
// @t=20,
#20
rset=0;
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/// $readmemb("testfile.bit",rf);
/**
* IMPORTANT NOTE:
* Start to process inputs from the input file after
* 30 clock cycles
*/
for(count=0;count<size_of_input;count=count+1)
begin
#10
$display("Next");
e=$random;
rr=r[count];
if(rr_c != r_cx)
begin
$display($time,"rr_c NOT EQUAL to r_cx");
end
if(count==150)
begin
rset=1;
end
else if(count==151)
begin
rset=0;
end
end
// Problem with d and error_level
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule |
module outputs)
wire reg_we; // From uart_ of QMFIR_uart_if.v
wire [13:0] uart_addr; // From uart_ of QMFIR_uart_if.v
wire [31:0] uart_dout; // From uart_ of QMFIR_uart_if.v
wire uart_mem_re; // From uart_ of QMFIR_uart_if.v
wire uart_mem_we; // From uart_ of QMFIR_uart_if.v
// End of automatics
wire [23:0] uart_mem_i;
reg [23:0] uart_reg_i; //combinatory
//iReg
wire [15:0] ESCR;
wire [15:0] WPTR;
wire [15:0] ICNT;
wire [15:0] FREQ;
wire [15:0] OCNT;
wire [15:0] FCNT;
wire [31:0] firin;
//bram out
wire [15:0] MEMDATR1;
wire [15:0] MEMDATI1;
wire [15:0] MEMDATR2;
wire [15:0] MEMDATI2;
wire [15:0] MEMDATR3;
wire [15:0] MEMDATI3;
wire [15:0] RealOut1;
wire [15:0] RealOut2;
wire [15:0] RealOut3;
wire [15:0] ImagOut1;
wire [15:0] ImagOut2;
wire [15:0] ImagOut3;
//bram in
wire [9:0] mem_addr1;
wire [9:0] mem_addr2;
wire [9:0] mem_addr3;
wire [11:0] bramin_addr;
// qmfir
reg START;
wire DataValid;
// CORE
assign arst = ~arst_n;
assign arst1 = ESCR[0];
assign uart_rst_n = arst_n & init_rst_n;
QMFIR_uart_if uart_(/*AUTOINST*/
// Outputs
.uart_dout (uart_dout[31:0]),
.uart_addr (uart_addr[13:0]),
.uart_mem_we (uart_mem_we),
.uart_mem_re (uart_mem_re),
.reg_we (reg_we),
.uart_tx (uart_tx),
// Inputs
.uart_mem_i (uart_mem_i[23:0]),
.uart_reg_i (uart_reg_i[23:0]),
.clk (core_clk),
.arst_n (uart_rst_n),
.uart_rx (uart_rx));
iReg ireg_ (//outputs
.ESCR(ESCR),
.WPTR(WPTR),
.ICNT(ICNT),
.FREQ(FREQ),
.OCNT(OCNT),
.FCNT(FCNT),
//inputs
.clk(core_clk),
.arst(arst),
.idata(uart_dout[15:0]),
.iaddr(uart_addr),
.iwe(reg_we),
.FIR_WE(DataValid),
.WFIFO_WE(uart_mem_we)
);
BRAM_larg bramin_(//outputs
.doutb(firin), //32 bit
//inputs
.clka(core_clk),
.clkb(core_clk),
.addra(bramin_addr[11:0]), //12 bit
.addrb(FCNT[11:0]), //12 bit
.dina(uart_dout), //32 bit
.wea(uart_mem_we));
QM_FIR QM_FIR(//outputs
.RealOut1 (RealOut1),
.RealOut2 (RealOut2),
.RealOut3 (RealOut3),
.ImagOut1 (ImagOut1),
.ImagOut2 (ImagOut2),
.ImagOut3 (ImagOut3),
.DataValid (DataValid),
//inputs
.CLK (core_clk),
.ARST (arst1),
.InputValid (START),
.dsp_in0 (firin[31:24]),
.dsp_in1 (firin[23:16]),
.dsp_in2 (firin[15:8]),
.dsp_in3 (firin[7:0]),
.newFreq (FREQ[14]),
.freq (FREQ[6:0]));
BRAM BRAM1_ (//outputs
.doutb({MEMDATI1[15:0],MEMDATR1[15:0]}),
//inputs
.clka(core_clk),
.clkb(core_clk),
.addra(WPTR[6:0]),
.addrb(mem_addr1[6:0]),
.dina({ImagOut1[15:0],RealOut1[15:0]}),
.wea(DataValid));
BRAM BRAM2_ (//outputs
.doutb({MEMDATI2[15:0],MEMDATR2[15:0]}),
//inputs
.clka(core_clk),
.clkb(core_clk),
.addra(WPTR[6:0]),
.addrb(mem_addr2[6:0]),
.dina({ImagOut2[15:0],RealOut2[15:0]}),
.wea(DataValid));
BRAM BRAM3_ (//outputs
.doutb({MEMDATI3[15:0],MEMDATR3[15:0]}),
//inputs
.clka(core_clk),
.clkb(core_clk),
.addra(WPTR[6:0]),
.addrb(mem_addr3[6:0]),
.dina({ImagOut3[15:0],RealOut3[15:0]}),
.wea(DataValid));
always @ (posedge core_clk or posedge arst)
if (arst != 1'b0)
START = 1'b0;
else begin
if (ESCR[3]) begin
init_rst_n <= 0; //assert initial UART reset
START = ESCR[3]; //start the filter
end
else begin
init_rst_n <= 1;
START = 1'b0;
end
end
// BRAMin interface
assign bramin_addr[11:0] = {(12){uart_mem_we}} & uart_addr[11:0];
//iReg interface
always @ (/*AS*/ESCR or FCNT or FREQ or ICNT or OCNT or WPTR or uart_addr)
case (uart_addr[2:0])
3'h1: uart_reg_i = {uart_addr[7:0], ESCR[15:0]};
3'h2: uart_reg_i = {uart_addr[7:0], WPTR[15:0]};
3'h3: uart_reg_i = {uart_addr[7:0], ICNT[15:0]};
3'h4: uart_reg_i = {uart_addr[7:0], FREQ[15:0]};
3'h5: uart_reg_i = {uart_addr[7:0], OCNT[15:0]};
3'h6: uart_reg_i = {uart_addr[7:0], FCNT[15:0]};
//default: uart_reg_i = {uart_addr[7:0],16'hDEAD};
endcase // case (uart_addr[2:0])
// BRAM out interface
//read address
assign mem_addr1[6:0] = ((uart_addr[13:11] == 3'h1) | (uart_addr[13:11] == 3'h2)) ? uart_addr[6:0] : 7'b111_1111;
assign mem_addr2[6:0] = ((uart_addr[13:11] == 3'h3) | (uart_addr[13:11] == 3'h4)) ? uart_addr[6:0] : 7'b111_1111;
assign mem_addr3[6:0] = ((uart_addr[13:11] == 3'h5) | (uart_addr[13:11] == 3'h6)) ? uart_addr[6:0] : 7'b111_1111;
//read data
assign MEMDAT[15:0] = (MEMDATR1[15:0] & {16{uart_addr[13:11] == 3'h1}}) |
(MEMDATI1[15:0] & {16{uart_addr[13:11] == 3'h2}}) |
(MEMDATR2[15:0] & {16{uart_addr[13:11] == 3'h3}}) |
(MEMDATI2[15:0] & {16{uart_addr[13:11] == 3'h4}}) |
(MEMDATR3[15:0] & {16{uart_addr[13:11] == 3'h5}}) |
(MEMDATI3[15:0] & {16{uart_addr[13:11] == 3'h6}});
assign uart_mem_i[23:0] = {1'b0,uart_addr[13:11],uart_addr[3:0], MEMDAT[15:0]};
// DCM_BASE: Base Digital Clock Manager Circuit, Virtex-5
//this DCM is used to divide the clock from 100MHz to 62.5MHz (for UART)
DCM_BASE #(
.CLKFX_DIVIDE(8), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(5), // Can be any integer from 2 to 32
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
.CLK_FEEDBACK("NONE") // Specify clock feedback of NONE or 1X
) DCM_BASE_inst (
.CLKFX(core_clk), // DCM CLK synthesis out (M/D)
.CLKIN(clk), // Clock input (from IBUFG, BUFG or DCM)
.RST(arst) // DCM asynchronous reset input
);
// End of DCM_BASE_inst instantiation
endmodule |
module sky130_fd_sc_ls__sdfbbn_2 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__sdfbbn_2 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule |
module sky130_fd_sc_ms__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module eth_mac_1g_fifo #
(
parameter AXIS_DATA_WIDTH = 8,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
input wire logic_clk,
input wire logic_rst,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* GMII interface
*/
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* Control
*/
input wire rx_clk_enable,
input wire tx_clk_enable,
input wire rx_mii_select,
input wire tx_mii_select,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire [7:0] tx_fifo_axis_tdata;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire tx_fifo_axis_tuser;
wire [7:0] rx_fifo_axis_tdata;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire rx_fifo_axis_tuser;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
eth_mac_1g #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.rx_clk_enable(rx_clk_enable),
.tx_clk_enable(tx_clk_enable),
.rx_mii_select(rx_mii_select),
.tx_mii_select(tx_mii_select),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.ifg_delay(ifg_delay)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(8),
.M_KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(8),
.S_KEEP_ENABLE(0),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule |
module sky130_fd_sc_lp__clkinv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__clkinv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A)
);
endmodule |
module eth_phy_10g_rx_frame_sync #
(
parameter HDR_WIDTH = 2,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8
)
(
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire rx_block_lock
);
parameter BITSLIP_MAX_CYCLES = BITSLIP_HIGH_CYCLES > BITSLIP_LOW_CYCLES ? BITSLIP_HIGH_CYCLES : BITSLIP_LOW_CYCLES;
parameter BITSLIP_COUNT_WIDTH = $clog2(BITSLIP_MAX_CYCLES);
// bus width assertions
initial begin
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
reg [5:0] sh_count_reg = 6'd0, sh_count_next;
reg [3:0] sh_invalid_count_reg = 4'd0, sh_invalid_count_next;
reg [BITSLIP_COUNT_WIDTH-1:0] bitslip_count_reg = 0, bitslip_count_next;
reg serdes_rx_bitslip_reg = 1'b0, serdes_rx_bitslip_next;
reg rx_block_lock_reg = 1'b0, rx_block_lock_next;
assign serdes_rx_bitslip = serdes_rx_bitslip_reg;
assign rx_block_lock = rx_block_lock_reg;
always @* begin
sh_count_next = sh_count_reg;
sh_invalid_count_next = sh_invalid_count_reg;
bitslip_count_next = bitslip_count_reg;
serdes_rx_bitslip_next = serdes_rx_bitslip_reg;
rx_block_lock_next = rx_block_lock_reg;
if (bitslip_count_reg) begin
bitslip_count_next = bitslip_count_reg-1;
end else if (serdes_rx_bitslip_reg) begin
serdes_rx_bitslip_next = 1'b0;
bitslip_count_next = BITSLIP_LOW_CYCLES > 0 ? BITSLIP_LOW_CYCLES-1 : 0;
end else if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
sh_count_next = sh_count_reg + 1;
if (&sh_count_reg) begin
// valid count overflow, reset
sh_count_next = 0;
sh_invalid_count_next = 0;
if (!sh_invalid_count_reg) begin
rx_block_lock_next = 1'b1;
end
end
end else begin
// invalid header
sh_count_next = sh_count_reg + 1;
sh_invalid_count_next = sh_invalid_count_reg + 1;
if (!rx_block_lock_reg || &sh_invalid_count_reg) begin
// invalid count overflow, lost block lock
sh_count_next = 0;
sh_invalid_count_next = 0;
rx_block_lock_next = 1'b0;
// slip one bit
serdes_rx_bitslip_next = 1'b1;
bitslip_count_next = BITSLIP_HIGH_CYCLES > 0 ? BITSLIP_HIGH_CYCLES-1 : 0;
end else if (&sh_count_reg) begin
// valid count overflow, reset
sh_count_next = 0;
sh_invalid_count_next = 0;
end
end
end
always @(posedge clk) begin
sh_count_reg <= sh_count_next;
sh_invalid_count_reg <= sh_invalid_count_next;
bitslip_count_reg <= bitslip_count_next;
serdes_rx_bitslip_reg <= serdes_rx_bitslip_next;
rx_block_lock_reg <= rx_block_lock_next;
if (rst) begin
sh_count_reg <= 6'd0;
sh_invalid_count_reg <= 4'd0;
bitslip_count_reg <= 0;
serdes_rx_bitslip_reg <= 1'b0;
rx_block_lock_reg <= 1'b0;
end
end
endmodule |
module sky130_fd_sc_hd__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule |
module sky130_fd_sc_hs__dfxbp (
VPWR,
VGND,
Q ,
Q_N ,
CLK ,
D
);
// Module ports
input VPWR;
input VGND;
output Q ;
output Q_N ;
input CLK ;
input D ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hs__u_df_p_no_pg u_df_p_no_pg0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule |
module or1200_ctrl(
// Clock and reset
clk, rst,
// Internal i/f
id_freeze, ex_freeze, wb_freeze, flushpipe, if_insn, ex_insn, branch_op, branch_taken,
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op,
wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
cust5_op, cust5_limm,
multicycle, spr_addrimm, wbforw_valid, du_hwbkpt, sig_syscall, sig_trap,
force_dslot_fetch, no_more_dslot, ex_void, id_macrc_op, ex_macrc_op, rfe, except_illegal
);
//
// I/O
//
input clk;
input rst;
input id_freeze;
input ex_freeze;
input wb_freeze;
input flushpipe;
input [31:0] if_insn;
output [31:0] ex_insn;
output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
input branch_taken;
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
output rf_rda;
output rf_rdb;
output [`OR1200_ALUOP_WIDTH-1:0] alu_op;
output [`OR1200_MACOP_WIDTH-1:0] mac_op;
output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
output [31:0] wb_insn;
output [31:0] simm;
output [31:2] branch_addrofs;
output [31:0] lsu_addrofs;
output [`OR1200_SEL_WIDTH-1:0] sel_a;
output [`OR1200_SEL_WIDTH-1:0] sel_b;
output [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
output [`OR1200_COMPOP_WIDTH-1:0] comp_op;
output [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
output [4:0] cust5_op;
output [5:0] cust5_limm;
output [15:0] spr_addrimm;
input wbforw_valid;
input du_hwbkpt;
output sig_syscall;
output sig_trap;
output force_dslot_fetch;
output no_more_dslot;
output ex_void;
output id_macrc_op;
output ex_macrc_op;
output rfe;
output except_illegal;
//
// Internal wires and regs
//
reg [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;
reg [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
reg [`OR1200_ALUOP_WIDTH-1:0] alu_op;
`ifdef OR1200_MAC_IMPLEMENTED
reg [`OR1200_MACOP_WIDTH-1:0] mac_op;
reg ex_macrc_op;
`else
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
wire ex_macrc_op;
`endif
reg [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
reg [31:0] id_insn;
reg [31:0] ex_insn;
reg [31:0] wb_insn;
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
reg [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
reg [31:0] lsu_addrofs;
reg [`OR1200_SEL_WIDTH-1:0] sel_a;
reg [`OR1200_SEL_WIDTH-1:0] sel_b;
reg sel_imm;
reg [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
reg [`OR1200_COMPOP_WIDTH-1:0] comp_op;
reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
reg imm_signextend;
reg [15:0] spr_addrimm;
reg sig_syscall;
reg sig_trap;
reg except_illegal;
wire id_void;
//
// Register file read addresses
//
assign rf_addra = if_insn[20:16];
assign rf_addrb = if_insn[15:11];
assign rf_rda = if_insn[31];
assign rf_rdb = if_insn[30];
//
// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
// instructions
//
// SIMON
// assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op));
assign force_dslot_fetch = 1'b0;
assign no_more_dslot = |branch_op & !id_void & branch_taken | (branch_op == `OR1200_BRANCHOP_RFE);
assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
//
// Sign/Zero extension of immediates
//
assign simm = (imm_signextend == 1'b1) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
//
// Sign extension of branch offset
//
assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};
//
// l.macrc in ID stage
//
`ifdef OR1200_MAC_IMPLEMENTED
assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16];
`else
assign id_macrc_op = 1'b0;
`endif
//
// cust5_op, cust5_limm (L immediate)
//
assign cust5_op = ex_insn[4:0];
assign cust5_limm = ex_insn[10:5];
//
//
//
assign rfe = (pre_branch_op == `OR1200_BRANCHOP_RFE) | (branch_op == `OR1200_BRANCHOP_RFE);
//
// Generation of sel_a
//
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
sel_a = `OR1200_SEL_EX_FORW;
else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
sel_a = `OR1200_SEL_WB_FORW;
else
sel_a = `OR1200_SEL_RF;
//
// Generation of sel_b
//
always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
if (sel_imm)
sel_b = `OR1200_SEL_IMM;
else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
sel_b = `OR1200_SEL_EX_FORW;
else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
sel_b = `OR1200_SEL_WB_FORW;
else
sel_b = `OR1200_SEL_RF;
//
// l.macrc in EX stage
//
`ifdef OR1200_MAC_IMPLEMENTED
always @(posedge clk or posedge rst) begin
if (rst)
ex_macrc_op <= #1 1'b0;
else if (!ex_freeze & id_freeze | flushpipe)
ex_macrc_op <= #1 1'b0;
else if (!ex_freeze)
ex_macrc_op <= #1 id_macrc_op;
end
`else
assign ex_macrc_op = 1'b0;
`endif
//
// Decode of spr_addrimm
//
always @(posedge clk or posedge rst) begin
if (rst)
spr_addrimm <= #1 16'h0000;
else if (!ex_freeze & id_freeze | flushpipe)
spr_addrimm <= #1 16'h0000;
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.mfspr
`OR1200_OR32_MFSPR:
spr_addrimm <= #1 id_insn[15:0];
// l.mtspr
default:
spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};
endcase
end
end
//
// Decode of multicycle
//
always @(id_insn) begin
case (id_insn[31:26]) // synopsys parallel_case
`ifdef UNUSED
// l.lwz
`OR1200_OR32_LWZ:
multicycle = `OR1200_TWO_CYCLES;
// l.lbz
`OR1200_OR32_LBZ:
multicycle = `OR1200_TWO_CYCLES;
// l.lbs
`OR1200_OR32_LBS:
multicycle = `OR1200_TWO_CYCLES;
// l.lhz
`OR1200_OR32_LHZ:
multicycle = `OR1200_TWO_CYCLES;
// l.lhs
`OR1200_OR32_LHS:
multicycle = `OR1200_TWO_CYCLES;
// l.sw
`OR1200_OR32_SW:
multicycle = `OR1200_TWO_CYCLES;
// l.sb
`OR1200_OR32_SB:
multicycle = `OR1200_TWO_CYCLES;
// l.sh
`OR1200_OR32_SH:
multicycle = `OR1200_TWO_CYCLES;
`endif
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
multicycle = id_insn[`OR1200_ALUMCYC_POS];
// Single cycle instructions
default: begin
multicycle = `OR1200_ONE_CYCLE;
end
endcase
end
//
// Decode of imm_signextend
//
always @(id_insn) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.addi
`OR1200_OR32_ADDI:
imm_signextend = 1'b1;
// l.addic
`OR1200_OR32_ADDIC:
imm_signextend = 1'b1;
// l.xori
`OR1200_OR32_XORI:
imm_signextend = 1'b1;
// l.muli
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_OR32_MULI:
imm_signextend = 1'b1;
`endif
// l.maci
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACI:
imm_signextend = 1'b1;
`endif
// SFXX insns with immediate
`OR1200_OR32_SFXXI:
imm_signextend = 1'b1;
// Instructions with no or zero extended immediate
default: begin
imm_signextend = 1'b0;
end
endcase
end
//
// LSU addr offset
//
always @(lsu_op or ex_insn) begin
lsu_addrofs[10:0] = ex_insn[10:0];
case(lsu_op) // synopsys parallel_case
`OR1200_LSUOP_SW, `OR1200_LSUOP_SH, `OR1200_LSUOP_SB :
lsu_addrofs[31:11] = {{16{ex_insn[25]}}, ex_insn[25:21]};
default :
lsu_addrofs[31:11] = {{16{ex_insn[15]}}, ex_insn[15:11]};
endcase
end
//
// Register file write address
//
always @(posedge clk or posedge rst) begin
if (rst)
rf_addrw <= #1 5'd0;
else if (!ex_freeze & id_freeze)
rf_addrw <= #1 5'd00;
else if (!ex_freeze)
case (pre_branch_op) // synopsys parallel_case
`OR1200_BRANCHOP_JR, `OR1200_BRANCHOP_BAL:
rf_addrw <= #1 5'd09; // link register r9
default:
rf_addrw <= #1 id_insn[25:21];
endcase
end
//
// rf_addrw in wb stage (used in forwarding logic)
//
always @(posedge clk or posedge rst) begin
if (rst)
wb_rfaddrw <= #1 5'd0;
else if (!wb_freeze)
wb_rfaddrw <= #1 rf_addrw;
end
//
// Instruction latch in id_insn
//
always @(posedge clk or posedge rst) begin
if (rst)
id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (flushpipe)
id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // id_insn[16] must be 1
else if (!id_freeze) begin
id_insn <= #1 if_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: id_insn <= %h", $time, if_insn);
// synopsys translate_on
`endif
end
end
//
// Instruction latch in ex_insn
//
always @(posedge clk or posedge rst) begin
if (rst)
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (!ex_freeze & id_freeze | flushpipe)
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // ex_insn[16] must be 1
else if (!ex_freeze) begin
ex_insn <= #1 id_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: ex_insn <= %h", $time, id_insn);
// synopsys translate_on
`endif
end
end
//
// Instruction latch in wb_insn
//
always @(posedge clk or posedge rst) begin
if (rst)
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (flushpipe)
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // wb_insn[16] must be 1
else if (!wb_freeze) begin
wb_insn <= #1 ex_insn;
end
end
//
// Decode of sel_imm
//
always @(posedge clk or posedge rst) begin
if (rst)
sel_imm <= #1 1'b0;
else if (!id_freeze) begin
case (if_insn[31:26]) // synopsys parallel_case
// j.jalr
`OR1200_OR32_JALR:
sel_imm <= #1 1'b0;
// l.jr
`OR1200_OR32_JR:
sel_imm <= #1 1'b0;
// l.rfe
`OR1200_OR32_RFE:
sel_imm <= #1 1'b0;
// l.mfspr
`OR1200_OR32_MFSPR:
sel_imm <= #1 1'b0;
// l.mtspr
`OR1200_OR32_MTSPR:
sel_imm <= #1 1'b0;
// l.sys, l.brk and all three sync insns
`OR1200_OR32_XSYNC:
sel_imm <= #1 1'b0;
// l.mac/l.msb
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACMSB:
sel_imm <= #1 1'b0;
`endif
// l.sw
`OR1200_OR32_SW:
sel_imm <= #1 1'b0;
// l.sb
`OR1200_OR32_SB:
sel_imm <= #1 1'b0;
// l.sh
`OR1200_OR32_SH:
sel_imm <= #1 1'b0;
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
sel_imm <= #1 1'b0;
// SFXX instructions
`OR1200_OR32_SFXX:
sel_imm <= #1 1'b0;
`ifdef OR1200_OR32_CUST5
// l.cust5 instructions
`OR1200_OR32_CUST5:
sel_imm <= #1 1'b0;
`endif
// l.nop
`OR1200_OR32_NOP:
sel_imm <= #1 1'b0;
// All instructions with immediates
default: begin
sel_imm <= #1 1'b1;
end
endcase
end
end
//
// Decode of except_illegal
//
always @(posedge clk or posedge rst) begin
if (rst)
except_illegal <= #1 1'b0;
else if (!ex_freeze & id_freeze | flushpipe)
except_illegal <= #1 1'b0;
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
`OR1200_OR32_J,
`OR1200_OR32_JAL,
`OR1200_OR32_JALR,
`OR1200_OR32_JR,
`OR1200_OR32_BNF,
`OR1200_OR32_BF,
`OR1200_OR32_RFE,
`OR1200_OR32_MOVHI,
`OR1200_OR32_MFSPR,
`OR1200_OR32_XSYNC,
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACI,
`endif
`OR1200_OR32_LWZ,
`OR1200_OR32_LBZ,
`OR1200_OR32_LBS,
`OR1200_OR32_LHZ,
`OR1200_OR32_LHS,
`OR1200_OR32_ADDI,
`OR1200_OR32_ADDIC,
`OR1200_OR32_ANDI,
`OR1200_OR32_ORI,
`OR1200_OR32_XORI,
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_OR32_MULI,
`endif
`OR1200_OR32_SH_ROTI,
`OR1200_OR32_SFXXI,
`OR1200_OR32_MTSPR,
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACMSB,
`endif
`OR1200_OR32_SW,
`OR1200_OR32_SB,
`OR1200_OR32_SH,
`OR1200_OR32_ALU,
`OR1200_OR32_SFXX,
`ifdef OR1200_OR32_CUST5
`OR1200_OR32_CUST5,
`endif
`OR1200_OR32_NOP:
except_illegal <= #1 1'b0;
// Illegal and OR1200 unsupported instructions
default:
except_illegal <= #1 1'b1;
endcase
end
end
//
// Decode of alu_op
//
always @(posedge clk or posedge rst) begin
if (rst)
alu_op <= #1 `OR1200_ALUOP_NOP;
else if (!ex_freeze & id_freeze | flushpipe)
alu_op <= #1 `OR1200_ALUOP_NOP;
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.j
`OR1200_OR32_J:
alu_op <= #1 `OR1200_ALUOP_IMM;
// j.jal
`OR1200_OR32_JAL:
alu_op <= #1 `OR1200_ALUOP_IMM;
// l.bnf
`OR1200_OR32_BNF:
alu_op <= #1 `OR1200_ALUOP_NOP;
// l.bf
`OR1200_OR32_BF:
alu_op <= #1 `OR1200_ALUOP_NOP;
// l.movhi
`OR1200_OR32_MOVHI:
alu_op <= #1 `OR1200_ALUOP_MOVHI;
// l.mfspr
`OR1200_OR32_MFSPR:
alu_op <= #1 `OR1200_ALUOP_MFSR;
// l.mtspr
`OR1200_OR32_MTSPR:
alu_op <= #1 `OR1200_ALUOP_MTSR;
// l.addi
`OR1200_OR32_ADDI:
alu_op <= #1 `OR1200_ALUOP_ADD;
// l.addic
`OR1200_OR32_ADDIC:
alu_op <= #1 `OR1200_ALUOP_ADDC;
// l.andi
`OR1200_OR32_ANDI:
alu_op <= #1 `OR1200_ALUOP_AND;
// l.ori
`OR1200_OR32_ORI:
alu_op <= #1 `OR1200_ALUOP_OR;
// l.xori
`OR1200_OR32_XORI:
alu_op <= #1 `OR1200_ALUOP_XOR;
// l.muli
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_OR32_MULI:
alu_op <= #1 `OR1200_ALUOP_MUL;
`endif
// Shift and rotate insns with immediate
`OR1200_OR32_SH_ROTI:
alu_op <= #1 `OR1200_ALUOP_SHROT;
// SFXX insns with immediate
`OR1200_OR32_SFXXI:
alu_op <= #1 `OR1200_ALUOP_COMP;
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
alu_op <= #1 id_insn[3:0];
// SFXX instructions
`OR1200_OR32_SFXX:
alu_op <= #1 `OR1200_ALUOP_COMP;
`ifdef OR1200_OR32_CUST5
// l.cust5 instructions
`OR1200_OR32_CUST5:
alu_op <= #1 `OR1200_ALUOP_CUST5;
`endif
// Default
default: begin
alu_op <= #1 `OR1200_ALUOP_NOP;
end
endcase
end
end
//
// Decode of mac_op
//
`ifdef OR1200_MAC_IMPLEMENTED
always @(posedge clk or posedge rst) begin
if (rst)
mac_op <= #1 `OR1200_MACOP_NOP;
else if (!ex_freeze & id_freeze | flushpipe)
mac_op <= #1 `OR1200_MACOP_NOP;
else if (!ex_freeze)
case (id_insn[31:26]) // synopsys parallel_case
// l.maci
`OR1200_OR32_MACI:
mac_op <= #1 `OR1200_MACOP_MAC;
// l.nop
`OR1200_OR32_MACMSB:
mac_op <= #1 id_insn[1:0];
// Illegal and OR1200 unsupported instructions
default: begin
mac_op <= #1 `OR1200_MACOP_NOP;
end
endcase
else
mac_op <= #1 `OR1200_MACOP_NOP;
end
`else
assign mac_op = `OR1200_MACOP_NOP;
`endif
//
// Decode of shrot_op
//
always @(posedge clk or posedge rst) begin
if (rst)
shrot_op <= #1 `OR1200_SHROTOP_NOP;
else if (!ex_freeze & id_freeze | flushpipe)
shrot_op <= #1 `OR1200_SHROTOP_NOP;
else if (!ex_freeze) begin
shrot_op <= #1 id_insn[`OR1200_SHROTOP_POS];
end
end
//
// Decode of rfwb_op
//
always @(posedge clk or posedge rst) begin
if (rst)
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
else if (!ex_freeze & id_freeze | flushpipe)
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
// j.jal
`OR1200_OR32_JAL:
rfwb_op <= #1 `OR1200_RFWBOP_LR;
// j.jalr
`OR1200_OR32_JALR:
rfwb_op <= #1 `OR1200_RFWBOP_LR;
// l.movhi
`OR1200_OR32_MOVHI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// l.mfspr
`OR1200_OR32_MFSPR:
rfwb_op <= #1 `OR1200_RFWBOP_SPRS;
// l.lwz
`OR1200_OR32_LWZ:
rfwb_op <= #1 `OR1200_RFWBOP_LSU;
// l.lbz
`OR1200_OR32_LBZ:
rfwb_op <= #1 `OR1200_RFWBOP_LSU;
// l.lbs
`OR1200_OR32_LBS:
rfwb_op <= #1 `OR1200_RFWBOP_LSU;
// l.lhz
`OR1200_OR32_LHZ:
rfwb_op <= #1 `OR1200_RFWBOP_LSU;
// l.lhs
`OR1200_OR32_LHS:
rfwb_op <= #1 `OR1200_RFWBOP_LSU;
// l.addi
`OR1200_OR32_ADDI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// l.addic
`OR1200_OR32_ADDIC:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// l.andi
`OR1200_OR32_ANDI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// l.ori
`OR1200_OR32_ORI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// l.xori
`OR1200_OR32_XORI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// l.muli
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_OR32_MULI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
`endif
// Shift and rotate insns with immediate
`OR1200_OR32_SH_ROTI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
`ifdef OR1200_OR32_CUST5
// l.cust5 instructions
`OR1200_OR32_CUST5:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
`endif
// Instructions w/o register-file write-back
default: begin
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
end
endcase
end
end
//
// Decode of pre_branch_op
//
always @(posedge clk or posedge rst) begin
if (rst)
pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
else if (flushpipe)
pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
else if (!id_freeze) begin
case (if_insn[31:26]) // synopsys parallel_case
// l.j
`OR1200_OR32_J:
pre_branch_op <= #1 `OR1200_BRANCHOP_BAL;
// j.jal
`OR1200_OR32_JAL:
pre_branch_op <= #1 `OR1200_BRANCHOP_BAL;
// j.jalr
`OR1200_OR32_JALR:
pre_branch_op <= #1 `OR1200_BRANCHOP_JR;
// l.jr
`OR1200_OR32_JR:
pre_branch_op <= #1 `OR1200_BRANCHOP_JR;
// l.bnf
`OR1200_OR32_BNF:
pre_branch_op <= #1 `OR1200_BRANCHOP_BNF;
// l.bf
`OR1200_OR32_BF:
pre_branch_op <= #1 `OR1200_BRANCHOP_BF;
// l.rfe
`OR1200_OR32_RFE:
pre_branch_op <= #1 `OR1200_BRANCHOP_RFE;
// Non branch instructions
default: begin
pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
end
endcase
end
end
//
// Generation of branch_op
//
always @(posedge clk or posedge rst)
if (rst)
branch_op <= #1 `OR1200_BRANCHOP_NOP;
else if (!ex_freeze & id_freeze | flushpipe)
branch_op <= #1 `OR1200_BRANCHOP_NOP;
else if (!ex_freeze)
branch_op <= #1 pre_branch_op;
//
// Decode of lsu_op
//
always @(posedge clk or posedge rst) begin
if (rst)
lsu_op <= #1 `OR1200_LSUOP_NOP;
else if (!ex_freeze & id_freeze | flushpipe)
lsu_op <= #1 `OR1200_LSUOP_NOP;
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.lwz
`OR1200_OR32_LWZ:
lsu_op <= #1 `OR1200_LSUOP_LWZ;
// l.lbz
`OR1200_OR32_LBZ:
lsu_op <= #1 `OR1200_LSUOP_LBZ;
// l.lbs
`OR1200_OR32_LBS:
lsu_op <= #1 `OR1200_LSUOP_LBS;
// l.lhz
`OR1200_OR32_LHZ:
lsu_op <= #1 `OR1200_LSUOP_LHZ;
// l.lhs
`OR1200_OR32_LHS:
lsu_op <= #1 `OR1200_LSUOP_LHS;
// l.sw
`OR1200_OR32_SW:
lsu_op <= #1 `OR1200_LSUOP_SW;
// l.sb
`OR1200_OR32_SB:
lsu_op <= #1 `OR1200_LSUOP_SB;
// l.sh
`OR1200_OR32_SH:
lsu_op <= #1 `OR1200_LSUOP_SH;
// Non load/store instructions
default: begin
lsu_op <= #1 `OR1200_LSUOP_NOP;
end
endcase
end
end
//
// Decode of comp_op
//
always @(posedge clk or posedge rst) begin
if (rst) begin
comp_op <= #1 4'd0;
end else if (!ex_freeze & id_freeze | flushpipe)
comp_op <= #1 4'd0;
else if (!ex_freeze)
comp_op <= #1 id_insn[24:21];
end
//
// Decode of l.sys
//
always @(posedge clk or posedge rst) begin
if (rst)
sig_syscall <= #1 1'b0;
else if (!ex_freeze & id_freeze | flushpipe)
sig_syscall <= #1 1'b0;
else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000})
$display("Generating sig_syscall");
// synopsys translate_on
`endif
sig_syscall <= #1 (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000});
end
end
//
// Decode of l.trap
//
always @(posedge clk or posedge rst) begin
if (rst)
sig_trap <= #1 1'b0;
else if (!ex_freeze & id_freeze | flushpipe)
sig_trap <= #1 1'b0;
else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
$display("Generating sig_trap");
// synopsys translate_on
`endif
sig_trap <= #1 (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
| du_hwbkpt;
end
end
endmodule |
module pcie3_7x_0_qpll_reset #
(
//---------- Global ------------------------------------
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter BYPASS_COARSE_OVRD = 1 // Bypass coarse frequency override
)
(
//---------- Input -------------------------------------
input QRST_CLK,
input QRST_RST_N,
input QRST_MMCM_LOCK,
input [PCIE_LANE-1:0] QRST_CPLLLOCK,
input [(PCIE_LANE-1)>>2:0]QRST_DRP_DONE,
input [(PCIE_LANE-1)>>2:0]QRST_QPLLLOCK,
input [ 1:0] QRST_RATE,
input [PCIE_LANE-1:0] QRST_QPLLRESET_IN,
input [PCIE_LANE-1:0] QRST_QPLLPD_IN,
//---------- Output ------------------------------------
output QRST_OVRD,
output QRST_DRP_START,
output QRST_QPLLRESET_OUT,
output QRST_QPLLPD_OUT,
output QRST_IDLE,
output [11:0] QRST_FSM
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg2;
//---------- Output Register --------------------------
reg ovrd = 1'd0;
reg qpllreset = 1'd1;
reg qpllpd = 1'd0;
reg [11:0] fsm = 12'd2;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 12'b000000000001;
localparam FSM_WAIT_LOCK = 12'b000000000010;
localparam FSM_MMCM_LOCK = 12'b000000000100;
localparam FSM_DRP_START_NOM = 12'b000000001000;
localparam FSM_DRP_DONE_NOM = 12'b000000010000;
localparam FSM_QPLLLOCK = 12'b000000100000;
localparam FSM_DRP_START_OPT = 12'b000001000000;
localparam FSM_DRP_DONE_OPT = 12'b000010000000;
localparam FSM_QPLL_RESET = 12'b000100000000;
localparam FSM_QPLLLOCK2 = 12'b001000000000;
localparam FSM_QPLL_PDRESET = 12'b010000000000;
localparam FSM_QPLL_PD = 12'b100000000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge QRST_CLK)
begin
if (!QRST_RST_N)
begin
//---------- 1st Stage FF --------------------------
mmcm_lock_reg1 <= 1'd0;
cplllock_reg1 <= {PCIE_LANE{1'd1}};
drp_done_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
qplllock_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
rate_reg1 <= 2'd0;
qpllreset_in_reg1 <= {PCIE_LANE{1'd1}};
qpllpd_in_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
mmcm_lock_reg2 <= 1'd0;
cplllock_reg2 <= {PCIE_LANE{1'd1}};
drp_done_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
qplllock_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
rate_reg2 <= 2'd0;
qpllreset_in_reg2 <= {PCIE_LANE{1'd1}};
qpllpd_in_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
mmcm_lock_reg1 <= QRST_MMCM_LOCK;
cplllock_reg1 <= QRST_CPLLLOCK;
drp_done_reg1 <= QRST_DRP_DONE;
qplllock_reg1 <= QRST_QPLLLOCK;
rate_reg1 <= QRST_RATE;
qpllreset_in_reg1 <= QRST_QPLLRESET_IN;
qpllpd_in_reg1 <= QRST_QPLLPD_IN;
//---------- 2nd Stage FF --------------------------
mmcm_lock_reg2 <= mmcm_lock_reg1;
cplllock_reg2 <= cplllock_reg1;
drp_done_reg2 <= drp_done_reg1;
qplllock_reg2 <= qplllock_reg1;
rate_reg2 <= rate_reg1;
qpllreset_in_reg2 <= qpllreset_in_reg1;
qpllpd_in_reg2 <= qpllpd_in_reg1;
end
end
//---------- QPLL Reset FSM ----------------------------------------------------
always @ (posedge QRST_CLK)
begin
if (!QRST_RST_N)
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!QRST_RST_N)
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
ovrd <= ovrd;
qpllreset <= &qpllreset_in_reg2;
qpllpd <= &qpllpd_in_reg2;
end
end
//---------- Wait for CPLL and QPLL to Lose Lock ---
FSM_WAIT_LOCK :
begin
fsm <= ((&(~cplllock_reg2)) && (&(~qplllock_reg2)) ? FSM_MMCM_LOCK : FSM_WAIT_LOCK);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for MMCM and CPLL Lock -----------
FSM_MMCM_LOCK :
begin
fsm <= ((mmcm_lock_reg2 && (&cplllock_reg2)) ? FSM_DRP_START_NOM : FSM_MMCM_LOCK);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Start QPLL DRP for Normal QPLL Lock Mode
FSM_DRP_START_NOM:
begin
fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_NOM : FSM_DRP_START_NOM);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL DRP Done ----------------
FSM_DRP_DONE_NOM :
begin
fsm <= (&drp_done_reg2 ? FSM_QPLLLOCK : FSM_DRP_DONE_NOM);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL Lock --------------------
FSM_QPLLLOCK :
begin
fsm <= (&qplllock_reg2 ? ((BYPASS_COARSE_OVRD == 1) ? FSM_QPLL_PDRESET : FSM_DRP_START_OPT) : FSM_QPLLLOCK);
ovrd <= ovrd;
qpllreset <= 1'd0;
qpllpd <= qpllpd;
end
//---------- Start QPLL DRP for Optimized QPLL Lock Mode
FSM_DRP_START_OPT:
begin
fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_OPT : FSM_DRP_START_OPT);
ovrd <= 1'd1;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL DRP Done ----------------
FSM_DRP_DONE_OPT :
begin
if (&drp_done_reg2)
begin
fsm <= ((PCIE_PLL_SEL == "QPLL") ? FSM_QPLL_RESET : FSM_QPLL_PDRESET);
ovrd <= ovrd;
qpllreset <= (PCIE_PLL_SEL == "QPLL");
qpllpd <= qpllpd;
end
else
begin
fsm <= FSM_DRP_DONE_OPT;
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
end
//---------- Reset QPLL ----------------------------
FSM_QPLL_RESET :
begin
fsm <= (&(~qplllock_reg2) ? FSM_QPLLLOCK2 : FSM_QPLL_RESET);
ovrd <= ovrd;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
//---------- Wait for QPLL Lock --------------------
FSM_QPLLLOCK2 :
begin
fsm <= (&qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK2);
ovrd <= ovrd;
qpllreset <= 1'd0;
qpllpd <= 1'd0;
end
//---------- Hold QPLL in Reset --------------------
FSM_QPLL_PDRESET :
begin
fsm <= FSM_QPLL_PD;
ovrd <= ovrd;
qpllreset <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0;
qpllpd <= qpllpd;
end
//---------- Power-down QPLL -----------------------
FSM_QPLL_PD :
begin
fsm <= FSM_IDLE;
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd0;
qpllpd <= 1'd0;
end
endcase
end
end
//---------- QPLL Lock Output --------------------------------------------------
assign QRST_OVRD = ovrd;
assign QRST_DRP_START = (fsm == FSM_DRP_START_NOM) || (fsm == FSM_DRP_START_OPT);
assign QRST_QPLLRESET_OUT = qpllreset;
assign QRST_QPLLPD_OUT = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
assign QRST_IDLE = (fsm == FSM_IDLE);
assign QRST_FSM = fsm;
endmodule |
module data_loader #(
parameter DRAM_BASE_ADDR=31'h40000000,
parameter ADDRESS_WIDTH=31,
parameter DATA_WIDTH=32,
parameter BLOCK_SIZE=64
) (
clk,
reset,
//Accumulator port for external writes
accumulate_fifo_read_slave_readdata,
accumulate_fifo_read_slave_waitrequest,
accumulate_fifo_read_slave_read,
//Accumulator for internal writes
accumulator_local_readdata,
accumulator_local_read,
accumulator_local_waitrequest,
//Write interface to write into DDR memory
control_fixed_location,
control_write_base,
control_write_length,
control_go,
control_done,
//user logic
user_write_buffer,
user_buffer_input_data,
user_buffer_full
);
localparam NUM_STATES=6;
localparam STATE_IDLE=0;
localparam STATE_WAIT_READ=1;
localparam STATE_READ_KEY_VAL=2;
localparam STATE_COMPUTE_ADDRESS=3;
localparam STATE_WRITE_DRAM=4;
localparam STATE_WAIT_DONE=5;
////////////Ports///////////////////
input clk;
input reset;
//Read interface to read from accumulator FIFO
input [63: 0] accumulate_fifo_read_slave_readdata;
input accumulate_fifo_read_slave_waitrequest;
output reg accumulate_fifo_read_slave_read;
//Accumulator for local writes
//Signals for local accumulation
input [63:0] accumulator_local_readdata;
input accumulator_local_waitrequest;
output reg accumulator_local_read;
// control inputs and outputs
output wire control_fixed_location;
output reg [ADDRESS_WIDTH-1:0] control_write_base;
output reg [ADDRESS_WIDTH-1:0] control_write_length;
output reg control_go;
input wire control_done;
// user logic inputs and outputs
output reg user_write_buffer;
output reg [DATA_WIDTH-1:0] user_buffer_input_data;
input wire user_buffer_full;
///////////Registers/////////////////////
reg avalonmm_read_slave_read_next;
reg [ADDRESS_WIDTH-1:0] control_write_base_next;
reg [ADDRESS_WIDTH-1:0] control_write_length_next;
reg control_go_next;
reg user_write_buffer_next;
reg [DATA_WIDTH-1:0] user_buffer_input_data_next;
reg [NUM_STATES-1:0] state, state_next;
reg [DATA_WIDTH-1:0] key, val, key_next, val_next;
reg accumulate_fifo_read_slave_read_next;
reg accum_type, accum_type_next;
reg accumulator_local_read_next;
localparam LOCAL=0; //local update
localparam EXT=1; //external update
assign control_fixed_location=1'b0;
always@(*)
begin
accumulate_fifo_read_slave_read_next = 1'b0;
key_next = key;
val_next = val;
control_write_length_next = control_write_length;
control_write_base_next = control_write_base;
control_go_next = 1'b0;
user_buffer_input_data_next = user_buffer_input_data;
user_write_buffer_next = 1'b0;
state_next = state;
accum_type_next = accum_type;
accumulator_local_read_next = 1'b0;
case(state)
STATE_IDLE: begin
if(!accumulate_fifo_read_slave_waitrequest) begin //if fifo is not empty, start reading first key
state_next = STATE_WAIT_READ;
accumulate_fifo_read_slave_read_next = 1'b1;
accum_type_next = EXT;
end
else if(!accumulator_local_waitrequest) begin
state_next = STATE_WAIT_READ;
accumulator_local_read_next = 1'b1;
accum_type_next = LOCAL;
end
else begin
state_next = STATE_IDLE;
end
end
STATE_WAIT_READ: begin
//Issue a sucessive read to get value (The FIFO must have (key,value) pairs
accumulate_fifo_read_slave_read_next = 1'b0;
accumulator_local_read_next = 1'b0;
state_next = STATE_READ_KEY_VAL;
end
STATE_READ_KEY_VAL: begin
if(accum_type==EXT) begin
key_next = accumulate_fifo_read_slave_readdata[63:32];
val_next = accumulate_fifo_read_slave_readdata[31:0];
end
else begin
key_next = accumulator_local_readdata[63:32];
val_next = accumulator_local_readdata[31:0];
end
state_next = STATE_COMPUTE_ADDRESS;
end
STATE_COMPUTE_ADDRESS: begin
control_write_base_next = (DRAM_BASE_ADDR+(key<<BLOCK_SIZE)); //convert key to an addressable location in DDDR2 DRAM [loc=key*64]
control_write_length_next = 4; //write a 32 bit key
control_go_next = 1'b1;
state_next = STATE_WRITE_DRAM;
end
STATE_WRITE_DRAM: begin
if(!user_buffer_full) begin
user_buffer_input_data_next = val;
user_write_buffer_next = 1'b1;
state_next = STATE_WAIT_DONE;
end
end
STATE_WAIT_DONE: begin
if(control_done)
state_next = STATE_IDLE;
end
endcase
end
always@(posedge clk)
begin
if(reset) begin
state <= STATE_IDLE;
accumulate_fifo_read_slave_read <= 1'b0;
key <= 0;
val <= 0;
control_write_length <= 0;
control_write_base <= 0;
control_go <= 0;
user_buffer_input_data <= 0;
user_write_buffer <= 1'b0;
accum_type <= 0;
accumulator_local_read <= 0;
end
else begin
state <= state_next;
accumulate_fifo_read_slave_read <= accumulate_fifo_read_slave_read_next;
key <= key_next;
val <= val_next;
control_write_length <= control_write_length_next;
control_write_base <= control_write_base_next;
control_go <= control_go_next;
user_buffer_input_data <= user_buffer_input_data_next;
user_write_buffer <= user_write_buffer_next;
accum_type <= accum_type_next;
accumulator_local_read <= accumulator_local_read_next;
end
end
endmodule |
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hd__nand4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule |
module sky130_fd_sc_lp__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module system (
input wire clk_50_clk, // clk_50.clk
input wire reset_50_reset_n, // reset_50.reset_n
output wire kernel_clk_clk, // kernel_clk.clk
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
output wire peripheral_hps_io_emac1_inst_TX_CLK, // peripheral.hps_io_emac1_inst_TX_CLK
output wire peripheral_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire peripheral_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire peripheral_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire peripheral_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire peripheral_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire peripheral_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire peripheral_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire peripheral_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire peripheral_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire peripheral_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire peripheral_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire peripheral_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire peripheral_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire peripheral_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire peripheral_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire peripheral_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire peripheral_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire peripheral_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire peripheral_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
input wire peripheral_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire peripheral_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire peripheral_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire peripheral_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire peripheral_hps_io_gpio_inst_GPIO53 // .hps_io_gpio_inst_GPIO53
);
wire acl_iface_kernel_clk_clk; // acl_iface:kernel_clk_clk -> [Sobel_system:clock, avs_sobel_cra_cra_ring:clk, cra_root:clk, irq_mapper:clk, mm_interconnect_0:acl_iface_kernel_clk_clk, mm_interconnect_1:acl_iface_kernel_clk_clk]
wire acl_iface_kernel_clk2x_clk; // acl_iface:kernel_clk2x_clk -> Sobel_system:clock2x
wire acl_iface_kernel_reset_reset; // acl_iface:kernel_reset_reset_n -> [Sobel_system:resetn, avs_sobel_cra_cra_ring:rst_n, cra_root:rst_n, irq_mapper:reset, mm_interconnect_0:Sobel_system_clock_reset_reset_reset_bridge_in_reset_reset, mm_interconnect_1:cra_root_reset_reset_bridge_in_reset_reset]
wire avs_sobel_cra_cra_ring_ring_in_waitrequest; // avs_sobel_cra_cra_ring:ri_waitrequest -> cra_root:ro_waitrequest
wire [7:0] cra_root_ring_out_byteena; // cra_root:ro_byteena -> avs_sobel_cra_cra_ring:ri_byteena
wire [63:0] cra_root_ring_out_data; // cra_root:ro_data -> avs_sobel_cra_cra_ring:ri_data
wire cra_root_ring_out_write; // cra_root:ro_write -> avs_sobel_cra_cra_ring:ri_write
wire cra_root_ring_out_read; // cra_root:ro_read -> avs_sobel_cra_cra_ring:ri_read
wire [3:0] cra_root_ring_out_addr; // cra_root:ro_addr -> avs_sobel_cra_cra_ring:ri_addr
wire cra_root_ring_out_datavalid; // cra_root:ro_datavalid -> avs_sobel_cra_cra_ring:ri_datavalid
wire avs_sobel_cra_cra_ring_cra_master_waitrequest; // Sobel_system:avs_sobel_cra_waitrequest -> avs_sobel_cra_cra_ring:avm_waitrequest
wire [63:0] avs_sobel_cra_cra_ring_cra_master_writedata; // avs_sobel_cra_cra_ring:avm_writedata -> Sobel_system:avs_sobel_cra_writedata
wire [3:0] avs_sobel_cra_cra_ring_cra_master_address; // avs_sobel_cra_cra_ring:avm_addr -> Sobel_system:avs_sobel_cra_address
wire avs_sobel_cra_cra_ring_cra_master_write; // avs_sobel_cra_cra_ring:avm_write -> Sobel_system:avs_sobel_cra_write
wire avs_sobel_cra_cra_ring_cra_master_read; // avs_sobel_cra_cra_ring:avm_read -> Sobel_system:avs_sobel_cra_read
wire [63:0] avs_sobel_cra_cra_ring_cra_master_readdata; // Sobel_system:avs_sobel_cra_readdata -> avs_sobel_cra_cra_ring:avm_readdata
wire avs_sobel_cra_cra_ring_cra_master_readdatavalid; // Sobel_system:avs_sobel_cra_readdatavalid -> avs_sobel_cra_cra_ring:avm_readdatavalid
wire [7:0] avs_sobel_cra_cra_ring_cra_master_byteenable; // avs_sobel_cra_cra_ring:avm_byteena -> Sobel_system:avs_sobel_cra_byteenable
wire cra_root_ring_in_waitrequest; // cra_root:ri_waitrequest -> avs_sobel_cra_cra_ring:ro_waitrequest
wire [7:0] avs_sobel_cra_cra_ring_ring_out_byteena; // avs_sobel_cra_cra_ring:ro_byteena -> cra_root:ri_byteena
wire [63:0] avs_sobel_cra_cra_ring_ring_out_data; // avs_sobel_cra_cra_ring:ro_data -> cra_root:ri_data
wire avs_sobel_cra_cra_ring_ring_out_write; // avs_sobel_cra_cra_ring:ro_write -> cra_root:ri_write
wire avs_sobel_cra_cra_ring_ring_out_read; // avs_sobel_cra_cra_ring:ro_read -> cra_root:ri_read
wire [3:0] avs_sobel_cra_cra_ring_ring_out_addr; // avs_sobel_cra_cra_ring:ro_addr -> cra_root:ri_addr
wire avs_sobel_cra_cra_ring_ring_out_datavalid; // avs_sobel_cra_cra_ring:ro_datavalid -> cra_root:ri_datavalid
wire sobel_system_avm_memgmem0_port_0_0_rw_waitrequest; // mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_waitrequest -> Sobel_system:avm_memgmem0_port_0_0_rw_waitrequest
wire [4:0] sobel_system_avm_memgmem0_port_0_0_rw_burstcount; // Sobel_system:avm_memgmem0_port_0_0_rw_burstcount -> mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_burstcount
wire [255:0] sobel_system_avm_memgmem0_port_0_0_rw_writedata; // Sobel_system:avm_memgmem0_port_0_0_rw_writedata -> mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_writedata
wire [29:0] sobel_system_avm_memgmem0_port_0_0_rw_address; // Sobel_system:avm_memgmem0_port_0_0_rw_address -> mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_address
wire sobel_system_avm_memgmem0_port_0_0_rw_write; // Sobel_system:avm_memgmem0_port_0_0_rw_write -> mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_write
wire sobel_system_avm_memgmem0_port_0_0_rw_read; // Sobel_system:avm_memgmem0_port_0_0_rw_read -> mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_read
wire [255:0] sobel_system_avm_memgmem0_port_0_0_rw_readdata; // mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_readdata -> Sobel_system:avm_memgmem0_port_0_0_rw_readdata
wire sobel_system_avm_memgmem0_port_0_0_rw_readdatavalid; // mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_readdatavalid -> Sobel_system:avm_memgmem0_port_0_0_rw_readdatavalid
wire [31:0] sobel_system_avm_memgmem0_port_0_0_rw_byteenable; // Sobel_system:avm_memgmem0_port_0_0_rw_byteenable -> mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_byteenable
wire mm_interconnect_0_acl_iface_kernel_mem0_waitrequest; // acl_iface:kernel_mem0_waitrequest -> mm_interconnect_0:acl_iface_kernel_mem0_waitrequest
wire [4:0] mm_interconnect_0_acl_iface_kernel_mem0_burstcount; // mm_interconnect_0:acl_iface_kernel_mem0_burstcount -> acl_iface:kernel_mem0_burstcount
wire [255:0] mm_interconnect_0_acl_iface_kernel_mem0_writedata; // mm_interconnect_0:acl_iface_kernel_mem0_writedata -> acl_iface:kernel_mem0_writedata
wire [29:0] mm_interconnect_0_acl_iface_kernel_mem0_address; // mm_interconnect_0:acl_iface_kernel_mem0_address -> acl_iface:kernel_mem0_address
wire mm_interconnect_0_acl_iface_kernel_mem0_write; // mm_interconnect_0:acl_iface_kernel_mem0_write -> acl_iface:kernel_mem0_write
wire mm_interconnect_0_acl_iface_kernel_mem0_read; // mm_interconnect_0:acl_iface_kernel_mem0_read -> acl_iface:kernel_mem0_read
wire [255:0] mm_interconnect_0_acl_iface_kernel_mem0_readdata; // acl_iface:kernel_mem0_readdata -> mm_interconnect_0:acl_iface_kernel_mem0_readdata
wire mm_interconnect_0_acl_iface_kernel_mem0_debugaccess; // mm_interconnect_0:acl_iface_kernel_mem0_debugaccess -> acl_iface:kernel_mem0_debugaccess
wire mm_interconnect_0_acl_iface_kernel_mem0_readdatavalid; // acl_iface:kernel_mem0_readdatavalid -> mm_interconnect_0:acl_iface_kernel_mem0_readdatavalid
wire [31:0] mm_interconnect_0_acl_iface_kernel_mem0_byteenable; // mm_interconnect_0:acl_iface_kernel_mem0_byteenable -> acl_iface:kernel_mem0_byteenable
wire [0:0] acl_iface_kernel_cra_burstcount; // acl_iface:kernel_cra_burstcount -> mm_interconnect_1:acl_iface_kernel_cra_burstcount
wire acl_iface_kernel_cra_waitrequest; // mm_interconnect_1:acl_iface_kernel_cra_waitrequest -> acl_iface:kernel_cra_waitrequest
wire [29:0] acl_iface_kernel_cra_address; // acl_iface:kernel_cra_address -> mm_interconnect_1:acl_iface_kernel_cra_address
wire [63:0] acl_iface_kernel_cra_writedata; // acl_iface:kernel_cra_writedata -> mm_interconnect_1:acl_iface_kernel_cra_writedata
wire acl_iface_kernel_cra_write; // acl_iface:kernel_cra_write -> mm_interconnect_1:acl_iface_kernel_cra_write
wire acl_iface_kernel_cra_read; // acl_iface:kernel_cra_read -> mm_interconnect_1:acl_iface_kernel_cra_read
wire [63:0] acl_iface_kernel_cra_readdata; // mm_interconnect_1:acl_iface_kernel_cra_readdata -> acl_iface:kernel_cra_readdata
wire acl_iface_kernel_cra_debugaccess; // acl_iface:kernel_cra_debugaccess -> mm_interconnect_1:acl_iface_kernel_cra_debugaccess
wire [7:0] acl_iface_kernel_cra_byteenable; // acl_iface:kernel_cra_byteenable -> mm_interconnect_1:acl_iface_kernel_cra_byteenable
wire acl_iface_kernel_cra_readdatavalid; // mm_interconnect_1:acl_iface_kernel_cra_readdatavalid -> acl_iface:kernel_cra_readdatavalid
wire mm_interconnect_1_cra_root_cra_slave_waitrequest; // cra_root:avs_waitrequest -> mm_interconnect_1:cra_root_cra_slave_waitrequest
wire [63:0] mm_interconnect_1_cra_root_cra_slave_writedata; // mm_interconnect_1:cra_root_cra_slave_writedata -> cra_root:avs_writedata
wire [3:0] mm_interconnect_1_cra_root_cra_slave_address; // mm_interconnect_1:cra_root_cra_slave_address -> cra_root:avs_addr
wire mm_interconnect_1_cra_root_cra_slave_write; // mm_interconnect_1:cra_root_cra_slave_write -> cra_root:avs_write
wire mm_interconnect_1_cra_root_cra_slave_read; // mm_interconnect_1:cra_root_cra_slave_read -> cra_root:avs_read
wire [63:0] mm_interconnect_1_cra_root_cra_slave_readdata; // cra_root:avs_readdata -> mm_interconnect_1:cra_root_cra_slave_readdata
wire mm_interconnect_1_cra_root_cra_slave_readdatavalid; // cra_root:avs_readdatavalid -> mm_interconnect_1:cra_root_cra_slave_readdatavalid
wire [7:0] mm_interconnect_1_cra_root_cra_slave_byteenable; // mm_interconnect_1:cra_root_cra_slave_byteenable -> cra_root:avs_byteena
wire irq_mapper_receiver0_irq; // Sobel_system:kernel_irq -> irq_mapper:receiver0_irq
wire [0:0] acl_iface_kernel_irq_irq; // irq_mapper:sender_irq -> acl_iface:kernel_irq_irq
system_acl_iface acl_iface (
.config_clk_clk (clk_50_clk), // config_clk.clk
.reset_n (reset_50_reset_n), // global_reset.reset_n
.kernel_pll_refclk_clk (clk_50_clk), // kernel_pll_refclk.clk
.kernel_clk_clk (acl_iface_kernel_clk_clk), // kernel_clk.clk
.kernel_reset_reset_n (acl_iface_kernel_reset_reset), // kernel_reset.reset_n
.kernel_clk2x_clk (acl_iface_kernel_clk2x_clk), // kernel_clk2x.clk
.kernel_mem0_waitrequest (mm_interconnect_0_acl_iface_kernel_mem0_waitrequest), // kernel_mem0.waitrequest
.kernel_mem0_readdata (mm_interconnect_0_acl_iface_kernel_mem0_readdata), // .readdata
.kernel_mem0_readdatavalid (mm_interconnect_0_acl_iface_kernel_mem0_readdatavalid), // .readdatavalid
.kernel_mem0_burstcount (mm_interconnect_0_acl_iface_kernel_mem0_burstcount), // .burstcount
.kernel_mem0_writedata (mm_interconnect_0_acl_iface_kernel_mem0_writedata), // .writedata
.kernel_mem0_address (mm_interconnect_0_acl_iface_kernel_mem0_address), // .address
.kernel_mem0_write (mm_interconnect_0_acl_iface_kernel_mem0_write), // .write
.kernel_mem0_read (mm_interconnect_0_acl_iface_kernel_mem0_read), // .read
.kernel_mem0_byteenable (mm_interconnect_0_acl_iface_kernel_mem0_byteenable), // .byteenable
.kernel_mem0_debugaccess (mm_interconnect_0_acl_iface_kernel_mem0_debugaccess), // .debugaccess
.acl_kernel_clk_kernel_pll_locked_export (), // acl_kernel_clk_kernel_pll_locked.export
.kernel_clk_snoop_clk (kernel_clk_clk), // kernel_clk_snoop.clk
.memory_mem_a (memory_mem_a), // memory.mem_a
.memory_mem_ba (memory_mem_ba), // .mem_ba
.memory_mem_ck (memory_mem_ck), // .mem_ck
.memory_mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.memory_mem_cke (memory_mem_cke), // .mem_cke
.memory_mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.memory_mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.memory_mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.memory_mem_we_n (memory_mem_we_n), // .mem_we_n
.memory_mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.memory_mem_dq (memory_mem_dq), // .mem_dq
.memory_mem_dqs (memory_mem_dqs), // .mem_dqs
.memory_mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.memory_mem_odt (memory_mem_odt), // .mem_odt
.memory_mem_dm (memory_mem_dm), // .mem_dm
.memory_oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.peripheral_hps_io_emac1_inst_TX_CLK (peripheral_hps_io_emac1_inst_TX_CLK), // peripheral.hps_io_emac1_inst_TX_CLK
.peripheral_hps_io_emac1_inst_TXD0 (peripheral_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.peripheral_hps_io_emac1_inst_TXD1 (peripheral_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.peripheral_hps_io_emac1_inst_TXD2 (peripheral_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.peripheral_hps_io_emac1_inst_TXD3 (peripheral_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.peripheral_hps_io_emac1_inst_RXD0 (peripheral_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.peripheral_hps_io_emac1_inst_MDIO (peripheral_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.peripheral_hps_io_emac1_inst_MDC (peripheral_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.peripheral_hps_io_emac1_inst_RX_CTL (peripheral_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.peripheral_hps_io_emac1_inst_TX_CTL (peripheral_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.peripheral_hps_io_emac1_inst_RX_CLK (peripheral_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.peripheral_hps_io_emac1_inst_RXD1 (peripheral_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.peripheral_hps_io_emac1_inst_RXD2 (peripheral_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.peripheral_hps_io_emac1_inst_RXD3 (peripheral_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.peripheral_hps_io_sdio_inst_CMD (peripheral_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.peripheral_hps_io_sdio_inst_D0 (peripheral_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.peripheral_hps_io_sdio_inst_D1 (peripheral_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.peripheral_hps_io_sdio_inst_CLK (peripheral_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.peripheral_hps_io_sdio_inst_D2 (peripheral_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.peripheral_hps_io_sdio_inst_D3 (peripheral_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.peripheral_hps_io_uart0_inst_RX (peripheral_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.peripheral_hps_io_uart0_inst_TX (peripheral_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.peripheral_hps_io_i2c1_inst_SDA (peripheral_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.peripheral_hps_io_i2c1_inst_SCL (peripheral_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.peripheral_hps_io_gpio_inst_GPIO53 (peripheral_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.acl_internal_memorg_kernel_mode (), // acl_internal_memorg_kernel.mode
.kernel_irq_irq (acl_iface_kernel_irq_irq), // kernel_irq.irq
.kernel_cra_waitrequest (acl_iface_kernel_cra_waitrequest), // kernel_cra.waitrequest
.kernel_cra_readdata (acl_iface_kernel_cra_readdata), // .readdata
.kernel_cra_readdatavalid (acl_iface_kernel_cra_readdatavalid), // .readdatavalid
.kernel_cra_burstcount (acl_iface_kernel_cra_burstcount), // .burstcount
.kernel_cra_writedata (acl_iface_kernel_cra_writedata), // .writedata
.kernel_cra_address (acl_iface_kernel_cra_address), // .address
.kernel_cra_write (acl_iface_kernel_cra_write), // .write
.kernel_cra_read (acl_iface_kernel_cra_read), // .read
.kernel_cra_byteenable (acl_iface_kernel_cra_byteenable), // .byteenable
.kernel_cra_debugaccess (acl_iface_kernel_cra_debugaccess), // .debugaccess
.kernel_interface_acl_bsp_memorg_host_mode () // kernel_interface_acl_bsp_memorg_host.mode
);
Sobel_system sobel_system (
.clock (acl_iface_kernel_clk_clk), // clock_reset.clk
.resetn (acl_iface_kernel_reset_reset), // clock_reset_reset.reset_n
.clock2x (acl_iface_kernel_clk2x_clk), // clock_reset2x.clk
.avs_sobel_cra_read (avs_sobel_cra_cra_ring_cra_master_read), // avs_sobel_cra.read
.avs_sobel_cra_write (avs_sobel_cra_cra_ring_cra_master_write), // .write
.avs_sobel_cra_address (avs_sobel_cra_cra_ring_cra_master_address), // .address
.avs_sobel_cra_writedata (avs_sobel_cra_cra_ring_cra_master_writedata), // .writedata
.avs_sobel_cra_byteenable (avs_sobel_cra_cra_ring_cra_master_byteenable), // .byteenable
.avs_sobel_cra_waitrequest (avs_sobel_cra_cra_ring_cra_master_waitrequest), // .waitrequest
.avs_sobel_cra_readdata (avs_sobel_cra_cra_ring_cra_master_readdata), // .readdata
.avs_sobel_cra_readdatavalid (avs_sobel_cra_cra_ring_cra_master_readdatavalid), // .readdatavalid
.kernel_irq (irq_mapper_receiver0_irq), // kernel_irq.irq
.avm_memgmem0_port_0_0_rw_address (sobel_system_avm_memgmem0_port_0_0_rw_address), // avm_memgmem0_port_0_0_rw.address
.avm_memgmem0_port_0_0_rw_read (sobel_system_avm_memgmem0_port_0_0_rw_read), // .read
.avm_memgmem0_port_0_0_rw_write (sobel_system_avm_memgmem0_port_0_0_rw_write), // .write
.avm_memgmem0_port_0_0_rw_burstcount (sobel_system_avm_memgmem0_port_0_0_rw_burstcount), // .burstcount
.avm_memgmem0_port_0_0_rw_writedata (sobel_system_avm_memgmem0_port_0_0_rw_writedata), // .writedata
.avm_memgmem0_port_0_0_rw_byteenable (sobel_system_avm_memgmem0_port_0_0_rw_byteenable), // .byteenable
.avm_memgmem0_port_0_0_rw_readdata (sobel_system_avm_memgmem0_port_0_0_rw_readdata), // .readdata
.avm_memgmem0_port_0_0_rw_waitrequest (sobel_system_avm_memgmem0_port_0_0_rw_waitrequest), // .waitrequest
.avm_memgmem0_port_0_0_rw_readdatavalid (sobel_system_avm_memgmem0_port_0_0_rw_readdatavalid) // .readdatavalid
);
cra_ring_root #(
.ADDR_W (4),
.DATA_W (64),
.ID_W (0)
) cra_root (
.clk (acl_iface_kernel_clk_clk), // clock.clk
.rst_n (acl_iface_kernel_reset_reset), // reset.reset_n
.avs_write (mm_interconnect_1_cra_root_cra_slave_write), // cra_slave.write
.avs_addr (mm_interconnect_1_cra_root_cra_slave_address), // .address
.avs_byteena (mm_interconnect_1_cra_root_cra_slave_byteenable), // .byteenable
.avs_writedata (mm_interconnect_1_cra_root_cra_slave_writedata), // .writedata
.avs_readdata (mm_interconnect_1_cra_root_cra_slave_readdata), // .readdata
.avs_readdatavalid (mm_interconnect_1_cra_root_cra_slave_readdatavalid), // .readdatavalid
.avs_waitrequest (mm_interconnect_1_cra_root_cra_slave_waitrequest), // .waitrequest
.avs_read (mm_interconnect_1_cra_root_cra_slave_read), // .read
.ri_write (avs_sobel_cra_cra_ring_ring_out_write), // ring_in.write
.ri_addr (avs_sobel_cra_cra_ring_ring_out_addr), // .addr
.ri_byteena (avs_sobel_cra_cra_ring_ring_out_byteena), // .byteena
.ri_data (avs_sobel_cra_cra_ring_ring_out_data), // .data
.ri_read (avs_sobel_cra_cra_ring_ring_out_read), // .read
.ri_datavalid (avs_sobel_cra_cra_ring_ring_out_datavalid), // .datavalid
.ri_waitrequest (cra_root_ring_in_waitrequest), // .waitrequest
.ro_read (cra_root_ring_out_read), // ring_out.read
.ro_write (cra_root_ring_out_write), // .write
.ro_addr (cra_root_ring_out_addr), // .addr
.ro_data (cra_root_ring_out_data), // .data
.ro_byteena (cra_root_ring_out_byteena), // .byteena
.ro_datavalid (cra_root_ring_out_datavalid), // .datavalid
.ro_waitrequest (avs_sobel_cra_cra_ring_ring_in_waitrequest) // .waitrequest
);
cra_ring_node #(
.RING_ADDR_W (4),
.CRA_ADDR_W (4),
.DATA_W (64),
.ID_W (0),
.ID (32'b00000000000000000000000000000000)
) avs_sobel_cra_cra_ring (
.clk (acl_iface_kernel_clk_clk), // clock.clk
.rst_n (acl_iface_kernel_reset_reset), // reset.reset_n
.avm_read (avs_sobel_cra_cra_ring_cra_master_read), // cra_master.read
.avm_write (avs_sobel_cra_cra_ring_cra_master_write), // .write
.avm_addr (avs_sobel_cra_cra_ring_cra_master_address), // .address
.avm_byteena (avs_sobel_cra_cra_ring_cra_master_byteenable), // .byteenable
.avm_writedata (avs_sobel_cra_cra_ring_cra_master_writedata), // .writedata
.avm_readdata (avs_sobel_cra_cra_ring_cra_master_readdata), // .readdata
.avm_readdatavalid (avs_sobel_cra_cra_ring_cra_master_readdatavalid), // .readdatavalid
.avm_waitrequest (avs_sobel_cra_cra_ring_cra_master_waitrequest), // .waitrequest
.ri_read (cra_root_ring_out_read), // ring_in.read
.ri_write (cra_root_ring_out_write), // .write
.ri_addr (cra_root_ring_out_addr), // .addr
.ri_data (cra_root_ring_out_data), // .data
.ri_byteena (cra_root_ring_out_byteena), // .byteena
.ri_datavalid (cra_root_ring_out_datavalid), // .datavalid
.ri_waitrequest (avs_sobel_cra_cra_ring_ring_in_waitrequest), // .waitrequest
.ro_read (avs_sobel_cra_cra_ring_ring_out_read), // ring_out.read
.ro_write (avs_sobel_cra_cra_ring_ring_out_write), // .write
.ro_addr (avs_sobel_cra_cra_ring_ring_out_addr), // .addr
.ro_data (avs_sobel_cra_cra_ring_ring_out_data), // .data
.ro_byteena (avs_sobel_cra_cra_ring_ring_out_byteena), // .byteena
.ro_datavalid (avs_sobel_cra_cra_ring_ring_out_datavalid), // .datavalid
.ro_waitrequest (cra_root_ring_in_waitrequest) // .waitrequest
);
system_mm_interconnect_0 mm_interconnect_0 (
.acl_iface_kernel_clk_clk (acl_iface_kernel_clk_clk), // acl_iface_kernel_clk.clk
.Sobel_system_clock_reset_reset_reset_bridge_in_reset_reset (~acl_iface_kernel_reset_reset), // Sobel_system_clock_reset_reset_reset_bridge_in_reset.reset
.Sobel_system_avm_memgmem0_port_0_0_rw_address (sobel_system_avm_memgmem0_port_0_0_rw_address), // Sobel_system_avm_memgmem0_port_0_0_rw.address
.Sobel_system_avm_memgmem0_port_0_0_rw_waitrequest (sobel_system_avm_memgmem0_port_0_0_rw_waitrequest), // .waitrequest
.Sobel_system_avm_memgmem0_port_0_0_rw_burstcount (sobel_system_avm_memgmem0_port_0_0_rw_burstcount), // .burstcount
.Sobel_system_avm_memgmem0_port_0_0_rw_byteenable (sobel_system_avm_memgmem0_port_0_0_rw_byteenable), // .byteenable
.Sobel_system_avm_memgmem0_port_0_0_rw_read (sobel_system_avm_memgmem0_port_0_0_rw_read), // .read
.Sobel_system_avm_memgmem0_port_0_0_rw_readdata (sobel_system_avm_memgmem0_port_0_0_rw_readdata), // .readdata
.Sobel_system_avm_memgmem0_port_0_0_rw_readdatavalid (sobel_system_avm_memgmem0_port_0_0_rw_readdatavalid), // .readdatavalid
.Sobel_system_avm_memgmem0_port_0_0_rw_write (sobel_system_avm_memgmem0_port_0_0_rw_write), // .write
.Sobel_system_avm_memgmem0_port_0_0_rw_writedata (sobel_system_avm_memgmem0_port_0_0_rw_writedata), // .writedata
.acl_iface_kernel_mem0_address (mm_interconnect_0_acl_iface_kernel_mem0_address), // acl_iface_kernel_mem0.address
.acl_iface_kernel_mem0_write (mm_interconnect_0_acl_iface_kernel_mem0_write), // .write
.acl_iface_kernel_mem0_read (mm_interconnect_0_acl_iface_kernel_mem0_read), // .read
.acl_iface_kernel_mem0_readdata (mm_interconnect_0_acl_iface_kernel_mem0_readdata), // .readdata
.acl_iface_kernel_mem0_writedata (mm_interconnect_0_acl_iface_kernel_mem0_writedata), // .writedata
.acl_iface_kernel_mem0_burstcount (mm_interconnect_0_acl_iface_kernel_mem0_burstcount), // .burstcount
.acl_iface_kernel_mem0_byteenable (mm_interconnect_0_acl_iface_kernel_mem0_byteenable), // .byteenable
.acl_iface_kernel_mem0_readdatavalid (mm_interconnect_0_acl_iface_kernel_mem0_readdatavalid), // .readdatavalid
.acl_iface_kernel_mem0_waitrequest (mm_interconnect_0_acl_iface_kernel_mem0_waitrequest), // .waitrequest
.acl_iface_kernel_mem0_debugaccess (mm_interconnect_0_acl_iface_kernel_mem0_debugaccess) // .debugaccess
);
system_mm_interconnect_1 mm_interconnect_1 (
.acl_iface_kernel_clk_clk (acl_iface_kernel_clk_clk), // acl_iface_kernel_clk.clk
.cra_root_reset_reset_bridge_in_reset_reset (~acl_iface_kernel_reset_reset), // cra_root_reset_reset_bridge_in_reset.reset
.acl_iface_kernel_cra_address (acl_iface_kernel_cra_address), // acl_iface_kernel_cra.address
.acl_iface_kernel_cra_waitrequest (acl_iface_kernel_cra_waitrequest), // .waitrequest
.acl_iface_kernel_cra_burstcount (acl_iface_kernel_cra_burstcount), // .burstcount
.acl_iface_kernel_cra_byteenable (acl_iface_kernel_cra_byteenable), // .byteenable
.acl_iface_kernel_cra_read (acl_iface_kernel_cra_read), // .read
.acl_iface_kernel_cra_readdata (acl_iface_kernel_cra_readdata), // .readdata
.acl_iface_kernel_cra_readdatavalid (acl_iface_kernel_cra_readdatavalid), // .readdatavalid
.acl_iface_kernel_cra_write (acl_iface_kernel_cra_write), // .write
.acl_iface_kernel_cra_writedata (acl_iface_kernel_cra_writedata), // .writedata
.acl_iface_kernel_cra_debugaccess (acl_iface_kernel_cra_debugaccess), // .debugaccess
.cra_root_cra_slave_address (mm_interconnect_1_cra_root_cra_slave_address), // cra_root_cra_slave.address
.cra_root_cra_slave_write (mm_interconnect_1_cra_root_cra_slave_write), // .write
.cra_root_cra_slave_read (mm_interconnect_1_cra_root_cra_slave_read), // .read
.cra_root_cra_slave_readdata (mm_interconnect_1_cra_root_cra_slave_readdata), // .readdata
.cra_root_cra_slave_writedata (mm_interconnect_1_cra_root_cra_slave_writedata), // .writedata
.cra_root_cra_slave_byteenable (mm_interconnect_1_cra_root_cra_slave_byteenable), // .byteenable
.cra_root_cra_slave_readdatavalid (mm_interconnect_1_cra_root_cra_slave_readdatavalid), // .readdatavalid
.cra_root_cra_slave_waitrequest (mm_interconnect_1_cra_root_cra_slave_waitrequest) // .waitrequest
);
system_irq_mapper irq_mapper (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (~acl_iface_kernel_reset_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (acl_iface_kernel_irq_irq) // sender.irq
);
endmodule |
module sky130_fd_sc_lp__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
// Delay Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (m0 , GATE, clkn, , VPWR, VGND);
and and0 (GCLK , m0, CLK );
endmodule |
module ip_design_lms_pcore_0_0
(IPCORE_CLK,
IPCORE_RESETN,
AXI4_Lite_ACLK,
AXI4_Lite_ARESETN,
AXI4_Lite_AWADDR,
AXI4_Lite_AWVALID,
AXI4_Lite_WDATA,
AXI4_Lite_WSTRB,
AXI4_Lite_WVALID,
AXI4_Lite_BREADY,
AXI4_Lite_ARADDR,
AXI4_Lite_ARVALID,
AXI4_Lite_RREADY,
AXI4_Lite_AWREADY,
AXI4_Lite_WREADY,
AXI4_Lite_BRESP,
AXI4_Lite_BVALID,
AXI4_Lite_ARREADY,
AXI4_Lite_RDATA,
AXI4_Lite_RRESP,
AXI4_Lite_RVALID);
(* x_interface_info = "xilinx.com:signal:clock:1.0 IPCORE_CLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME IPCORE_CLK, ASSOCIATED_RESET IPCORE_RESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input IPCORE_CLK;
(* x_interface_info = "xilinx.com:signal:reset:1.0 IPCORE_RESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME IPCORE_RESETN, POLARITY ACTIVE_LOW" *) input IPCORE_RESETN;
(* x_interface_info = "xilinx.com:signal:clock:1.0 AXI4_Lite_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME AXI4_Lite_ACLK, ASSOCIATED_RESET AXI4_Lite_ARESETN, ASSOCIATED_BUSIF AXI4_Lite, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input AXI4_Lite_ACLK;
(* x_interface_info = "xilinx.com:signal:reset:1.0 AXI4_Lite_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME AXI4_Lite_ARESETN, POLARITY ACTIVE_LOW" *) input AXI4_Lite_ARESETN;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME AXI4_Lite, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [15:0]AXI4_Lite_AWADDR;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite AWVALID" *) input AXI4_Lite_AWVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite WDATA" *) input [31:0]AXI4_Lite_WDATA;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite WSTRB" *) input [3:0]AXI4_Lite_WSTRB;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite WVALID" *) input AXI4_Lite_WVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite BREADY" *) input AXI4_Lite_BREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite ARADDR" *) input [15:0]AXI4_Lite_ARADDR;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite ARVALID" *) input AXI4_Lite_ARVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite RREADY" *) input AXI4_Lite_RREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite AWREADY" *) output AXI4_Lite_AWREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite WREADY" *) output AXI4_Lite_WREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite BRESP" *) output [1:0]AXI4_Lite_BRESP;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite BVALID" *) output AXI4_Lite_BVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite ARREADY" *) output AXI4_Lite_ARREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite RDATA" *) output [31:0]AXI4_Lite_RDATA;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite RRESP" *) output [1:0]AXI4_Lite_RRESP;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite RVALID" *) output AXI4_Lite_RVALID;
wire \<const0> ;
wire AXI4_Lite_ACLK;
wire [15:0]AXI4_Lite_ARADDR;
wire AXI4_Lite_ARESETN;
wire AXI4_Lite_ARREADY;
wire AXI4_Lite_ARVALID;
wire [15:0]AXI4_Lite_AWADDR;
wire AXI4_Lite_AWREADY;
wire AXI4_Lite_AWVALID;
wire AXI4_Lite_BREADY;
wire AXI4_Lite_BVALID;
wire [30:0]\^AXI4_Lite_RDATA ;
wire AXI4_Lite_RREADY;
wire AXI4_Lite_RVALID;
wire [31:0]AXI4_Lite_WDATA;
wire AXI4_Lite_WREADY;
wire AXI4_Lite_WVALID;
wire IPCORE_CLK;
wire IPCORE_RESETN;
assign AXI4_Lite_BRESP[1] = \<const0> ;
assign AXI4_Lite_BRESP[0] = \<const0> ;
assign AXI4_Lite_RDATA[31] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[30] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[29] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[28] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[27] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[26] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[25] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[24] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[23] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[22] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[21] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[20] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[19] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[18] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[17] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[16] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[15] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[14:0] = \^AXI4_Lite_RDATA [14:0];
assign AXI4_Lite_RRESP[1] = \<const0> ;
assign AXI4_Lite_RRESP[0] = \<const0> ;
GND GND
(.G(\<const0> ));
ip_design_lms_pcore_0_0_lms_pcore U0
(.AXI4_Lite_ACLK(AXI4_Lite_ACLK),
.AXI4_Lite_ARADDR(AXI4_Lite_ARADDR[15:2]),
.AXI4_Lite_ARESETN(AXI4_Lite_ARESETN),
.AXI4_Lite_ARREADY(AXI4_Lite_ARREADY),
.AXI4_Lite_ARVALID(AXI4_Lite_ARVALID),
.AXI4_Lite_AWADDR(AXI4_Lite_AWADDR[15:2]),
.AXI4_Lite_AWREADY(AXI4_Lite_AWREADY),
.AXI4_Lite_AWVALID(AXI4_Lite_AWVALID),
.AXI4_Lite_BREADY(AXI4_Lite_BREADY),
.AXI4_Lite_BVALID(AXI4_Lite_BVALID),
.AXI4_Lite_RDATA({\^AXI4_Lite_RDATA [30],\^AXI4_Lite_RDATA [14:0]}),
.AXI4_Lite_RREADY(AXI4_Lite_RREADY),
.AXI4_Lite_RVALID(AXI4_Lite_RVALID),
.AXI4_Lite_WDATA(AXI4_Lite_WDATA[15:0]),
.AXI4_Lite_WREADY(AXI4_Lite_WREADY),
.AXI4_Lite_WVALID(AXI4_Lite_WVALID),
.IPCORE_CLK(IPCORE_CLK),
.IPCORE_RESETN(IPCORE_RESETN));
endmodule |
module ip_design_lms_pcore_0_0_LMS
(mul_temp_16,
filter_sum,
\write_reg_x_k_reg[15] ,
cop_dut_enable,
IPCORE_CLK,
AR,
\write_reg_d_k_reg[3] ,
DI,
Q,
\write_reg_d_k_reg[3]_0 ,
\write_reg_d_k_reg[7] ,
\write_reg_d_k_reg[11] ,
S);
output [15:0]mul_temp_16;
output [15:0]filter_sum;
input [15:0]\write_reg_x_k_reg[15] ;
input cop_dut_enable;
input IPCORE_CLK;
input [0:0]AR;
input [2:0]\write_reg_d_k_reg[3] ;
input [0:0]DI;
input [14:0]Q;
input [3:0]\write_reg_d_k_reg[3]_0 ;
input [3:0]\write_reg_d_k_reg[7] ;
input [3:0]\write_reg_d_k_reg[11] ;
input [3:0]S;
wire [0:0]AR;
wire ARG__0_i_1_n_0;
wire ARG__0_n_100;
wire ARG__0_n_101;
wire ARG__0_n_102;
wire ARG__0_n_103;
wire ARG__0_n_104;
wire ARG__0_n_105;
wire ARG__0_n_92;
wire ARG__0_n_93;
wire ARG__0_n_94;
wire ARG__0_n_95;
wire ARG__0_n_96;
wire ARG__0_n_97;
wire ARG__0_n_98;
wire ARG__0_n_99;
wire ARG__10_i_1_n_0;
wire ARG__10_n_100;
wire ARG__10_n_101;
wire ARG__10_n_102;
wire ARG__10_n_103;
wire ARG__10_n_104;
wire ARG__10_n_105;
wire ARG__10_n_92;
wire ARG__10_n_93;
wire ARG__10_n_94;
wire ARG__10_n_95;
wire ARG__10_n_96;
wire ARG__10_n_97;
wire ARG__10_n_98;
wire ARG__10_n_99;
wire ARG__11_i_1_n_0;
wire ARG__11_n_100;
wire ARG__11_n_101;
wire ARG__11_n_102;
wire ARG__11_n_103;
wire ARG__11_n_104;
wire ARG__11_n_105;
wire ARG__11_n_76;
wire ARG__11_n_77;
wire ARG__11_n_78;
wire ARG__11_n_79;
wire ARG__11_n_80;
wire ARG__11_n_81;
wire ARG__11_n_82;
wire ARG__11_n_83;
wire ARG__11_n_84;
wire ARG__11_n_85;
wire ARG__11_n_86;
wire ARG__11_n_87;
wire ARG__11_n_88;
wire ARG__11_n_89;
wire ARG__11_n_90;
wire ARG__11_n_91;
wire ARG__11_n_92;
wire ARG__11_n_93;
wire ARG__11_n_94;
wire ARG__11_n_95;
wire ARG__11_n_96;
wire ARG__11_n_97;
wire ARG__11_n_98;
wire ARG__11_n_99;
wire ARG__12_i_1_n_0;
wire ARG__12_n_100;
wire ARG__12_n_101;
wire ARG__12_n_102;
wire ARG__12_n_103;
wire ARG__12_n_104;
wire ARG__12_n_105;
wire ARG__12_n_92;
wire ARG__12_n_93;
wire ARG__12_n_94;
wire ARG__12_n_95;
wire ARG__12_n_96;
wire ARG__12_n_97;
wire ARG__12_n_98;
wire ARG__12_n_99;
wire ARG__13_i_1_n_0;
wire ARG__13_n_100;
wire ARG__13_n_101;
wire ARG__13_n_102;
wire ARG__13_n_103;
wire ARG__13_n_104;
wire ARG__13_n_105;
wire ARG__13_n_76;
wire ARG__13_n_77;
wire ARG__13_n_78;
wire ARG__13_n_79;
wire ARG__13_n_80;
wire ARG__13_n_81;
wire ARG__13_n_82;
wire ARG__13_n_83;
wire ARG__13_n_84;
wire ARG__13_n_85;
wire ARG__13_n_86;
wire ARG__13_n_87;
wire ARG__13_n_88;
wire ARG__13_n_89;
wire ARG__13_n_90;
wire ARG__13_n_91;
wire ARG__13_n_92;
wire ARG__13_n_93;
wire ARG__13_n_94;
wire ARG__13_n_95;
wire ARG__13_n_96;
wire ARG__13_n_97;
wire ARG__13_n_98;
wire ARG__13_n_99;
wire ARG__14_i_1_n_0;
wire ARG__14_n_100;
wire ARG__14_n_101;
wire ARG__14_n_102;
wire ARG__14_n_103;
wire ARG__14_n_104;
wire ARG__14_n_105;
wire ARG__14_n_92;
wire ARG__14_n_93;
wire ARG__14_n_94;
wire ARG__14_n_95;
wire ARG__14_n_96;
wire ARG__14_n_97;
wire ARG__14_n_98;
wire ARG__14_n_99;
wire ARG__15_i_1_n_0;
wire ARG__15_n_100;
wire ARG__15_n_101;
wire ARG__15_n_102;
wire ARG__15_n_103;
wire ARG__15_n_104;
wire ARG__15_n_105;
wire ARG__15_n_76;
wire ARG__15_n_77;
wire ARG__15_n_78;
wire ARG__15_n_79;
wire ARG__15_n_80;
wire ARG__15_n_81;
wire ARG__15_n_82;
wire ARG__15_n_83;
wire ARG__15_n_84;
wire ARG__15_n_85;
wire ARG__15_n_86;
wire ARG__15_n_87;
wire ARG__15_n_88;
wire ARG__15_n_89;
wire ARG__15_n_90;
wire ARG__15_n_91;
wire ARG__15_n_92;
wire ARG__15_n_93;
wire ARG__15_n_94;
wire ARG__15_n_95;
wire ARG__15_n_96;
wire ARG__15_n_97;
wire ARG__15_n_98;
wire ARG__15_n_99;
wire ARG__16_i_1_n_0;
wire ARG__16_n_100;
wire ARG__16_n_101;
wire ARG__16_n_102;
wire ARG__16_n_103;
wire ARG__16_n_104;
wire ARG__16_n_105;
wire ARG__16_n_92;
wire ARG__16_n_93;
wire ARG__16_n_94;
wire ARG__16_n_95;
wire ARG__16_n_96;
wire ARG__16_n_97;
wire ARG__16_n_98;
wire ARG__16_n_99;
wire ARG__17_i_1_n_0;
wire ARG__17_n_100;
wire ARG__17_n_101;
wire ARG__17_n_102;
wire ARG__17_n_103;
wire ARG__17_n_104;
wire ARG__17_n_105;
wire ARG__17_n_76;
wire ARG__17_n_77;
wire ARG__17_n_78;
wire ARG__17_n_79;
wire ARG__17_n_80;
wire ARG__17_n_81;
wire ARG__17_n_82;
wire ARG__17_n_83;
wire ARG__17_n_84;
wire ARG__17_n_85;
wire ARG__17_n_86;
wire ARG__17_n_87;
wire ARG__17_n_88;
wire ARG__17_n_89;
wire ARG__17_n_90;
wire ARG__17_n_91;
wire ARG__17_n_92;
wire ARG__17_n_93;
wire ARG__17_n_94;
wire ARG__17_n_95;
wire ARG__17_n_96;
wire ARG__17_n_97;
wire ARG__17_n_98;
wire ARG__17_n_99;
wire ARG__18_i_1_n_0;
wire ARG__18_n_100;
wire ARG__18_n_101;
wire ARG__18_n_102;
wire ARG__18_n_103;
wire ARG__18_n_104;
wire ARG__18_n_105;
wire ARG__18_n_92;
wire ARG__18_n_93;
wire ARG__18_n_94;
wire ARG__18_n_95;
wire ARG__18_n_96;
wire ARG__18_n_97;
wire ARG__18_n_98;
wire ARG__18_n_99;
wire ARG__19_i_1_n_0;
wire ARG__19_n_100;
wire ARG__19_n_101;
wire ARG__19_n_102;
wire ARG__19_n_103;
wire ARG__19_n_104;
wire ARG__19_n_105;
wire ARG__19_n_76;
wire ARG__19_n_77;
wire ARG__19_n_78;
wire ARG__19_n_79;
wire ARG__19_n_80;
wire ARG__19_n_81;
wire ARG__19_n_82;
wire ARG__19_n_83;
wire ARG__19_n_84;
wire ARG__19_n_85;
wire ARG__19_n_86;
wire ARG__19_n_87;
wire ARG__19_n_88;
wire ARG__19_n_89;
wire ARG__19_n_90;
wire ARG__19_n_91;
wire ARG__19_n_92;
wire ARG__19_n_93;
wire ARG__19_n_94;
wire ARG__19_n_95;
wire ARG__19_n_96;
wire ARG__19_n_97;
wire ARG__19_n_98;
wire ARG__19_n_99;
wire ARG__1_i_1_n_0;
wire ARG__1_n_100;
wire ARG__1_n_101;
wire ARG__1_n_102;
wire ARG__1_n_103;
wire ARG__1_n_104;
wire ARG__1_n_105;
wire ARG__1_n_76;
wire ARG__1_n_77;
wire ARG__1_n_78;
wire ARG__1_n_79;
wire ARG__1_n_80;
wire ARG__1_n_81;
wire ARG__1_n_82;
wire ARG__1_n_83;
wire ARG__1_n_84;
wire ARG__1_n_85;
wire ARG__1_n_86;
wire ARG__1_n_87;
wire ARG__1_n_88;
wire ARG__1_n_89;
wire ARG__1_n_90;
wire ARG__1_n_91;
wire ARG__1_n_92;
wire ARG__1_n_93;
wire ARG__1_n_94;
wire ARG__1_n_95;
wire ARG__1_n_96;
wire ARG__1_n_97;
wire ARG__1_n_98;
wire ARG__1_n_99;
wire ARG__20_i_1_n_0;
wire ARG__20_n_100;
wire ARG__20_n_101;
wire ARG__20_n_102;
wire ARG__20_n_103;
wire ARG__20_n_104;
wire ARG__20_n_105;
wire ARG__20_n_92;
wire ARG__20_n_93;
wire ARG__20_n_94;
wire ARG__20_n_95;
wire ARG__20_n_96;
wire ARG__20_n_97;
wire ARG__20_n_98;
wire ARG__20_n_99;
wire ARG__21_i_1_n_0;
wire ARG__21_n_100;
wire ARG__21_n_101;
wire ARG__21_n_102;
wire ARG__21_n_103;
wire ARG__21_n_104;
wire ARG__21_n_105;
wire ARG__21_n_76;
wire ARG__21_n_77;
wire ARG__21_n_78;
wire ARG__21_n_79;
wire ARG__21_n_80;
wire ARG__21_n_81;
wire ARG__21_n_82;
wire ARG__21_n_83;
wire ARG__21_n_84;
wire ARG__21_n_85;
wire ARG__21_n_86;
wire ARG__21_n_87;
wire ARG__21_n_88;
wire ARG__21_n_89;
wire ARG__21_n_90;
wire ARG__21_n_91;
wire ARG__21_n_92;
wire ARG__21_n_93;
wire ARG__21_n_94;
wire ARG__21_n_95;
wire ARG__21_n_96;
wire ARG__21_n_97;
wire ARG__21_n_98;
wire ARG__21_n_99;
wire ARG__22_i_1_n_0;
wire ARG__22_n_100;
wire ARG__22_n_101;
wire ARG__22_n_102;
wire ARG__22_n_103;
wire ARG__22_n_104;
wire ARG__22_n_105;
wire ARG__22_n_92;
wire ARG__22_n_93;
wire ARG__22_n_94;
wire ARG__22_n_95;
wire ARG__22_n_96;
wire ARG__22_n_97;
wire ARG__22_n_98;
wire ARG__22_n_99;
wire ARG__23_i_1_n_0;
wire ARG__23_n_100;
wire ARG__23_n_101;
wire ARG__23_n_102;
wire ARG__23_n_103;
wire ARG__23_n_104;
wire ARG__23_n_105;
wire ARG__23_n_76;
wire ARG__23_n_77;
wire ARG__23_n_78;
wire ARG__23_n_79;
wire ARG__23_n_80;
wire ARG__23_n_81;
wire ARG__23_n_82;
wire ARG__23_n_83;
wire ARG__23_n_84;
wire ARG__23_n_85;
wire ARG__23_n_86;
wire ARG__23_n_87;
wire ARG__23_n_88;
wire ARG__23_n_89;
wire ARG__23_n_90;
wire ARG__23_n_91;
wire ARG__23_n_92;
wire ARG__23_n_93;
wire ARG__23_n_94;
wire ARG__23_n_95;
wire ARG__23_n_96;
wire ARG__23_n_97;
wire ARG__23_n_98;
wire ARG__23_n_99;
wire ARG__24_i_1_n_0;
wire ARG__24_n_100;
wire ARG__24_n_101;
wire ARG__24_n_102;
wire ARG__24_n_103;
wire ARG__24_n_104;
wire ARG__24_n_105;
wire ARG__24_n_92;
wire ARG__24_n_93;
wire ARG__24_n_94;
wire ARG__24_n_95;
wire ARG__24_n_96;
wire ARG__24_n_97;
wire ARG__24_n_98;
wire ARG__24_n_99;
wire ARG__25_i_1_n_0;
wire ARG__25_n_100;
wire ARG__25_n_101;
wire ARG__25_n_102;
wire ARG__25_n_103;
wire ARG__25_n_104;
wire ARG__25_n_105;
wire ARG__25_n_76;
wire ARG__25_n_77;
wire ARG__25_n_78;
wire ARG__25_n_79;
wire ARG__25_n_80;
wire ARG__25_n_81;
wire ARG__25_n_82;
wire ARG__25_n_83;
wire ARG__25_n_84;
wire ARG__25_n_85;
wire ARG__25_n_86;
wire ARG__25_n_87;
wire ARG__25_n_88;
wire ARG__25_n_89;
wire ARG__25_n_90;
wire ARG__25_n_91;
wire ARG__25_n_92;
wire ARG__25_n_93;
wire ARG__25_n_94;
wire ARG__25_n_95;
wire ARG__25_n_96;
wire ARG__25_n_97;
wire ARG__25_n_98;
wire ARG__25_n_99;
wire ARG__26_i_1_n_0;
wire ARG__26_n_100;
wire ARG__26_n_101;
wire ARG__26_n_102;
wire ARG__26_n_103;
wire ARG__26_n_104;
wire ARG__26_n_105;
wire ARG__26_n_92;
wire ARG__26_n_93;
wire ARG__26_n_94;
wire ARG__26_n_95;
wire ARG__26_n_96;
wire ARG__26_n_97;
wire ARG__26_n_98;
wire ARG__26_n_99;
wire ARG__27_i_1_n_0;
wire ARG__27_n_100;
wire ARG__27_n_101;
wire ARG__27_n_102;
wire ARG__27_n_103;
wire ARG__27_n_104;
wire ARG__27_n_105;
wire ARG__27_n_76;
wire ARG__27_n_77;
wire ARG__27_n_78;
wire ARG__27_n_79;
wire ARG__27_n_80;
wire ARG__27_n_81;
wire ARG__27_n_82;
wire ARG__27_n_83;
wire ARG__27_n_84;
wire ARG__27_n_85;
wire ARG__27_n_86;
wire ARG__27_n_87;
wire ARG__27_n_88;
wire ARG__27_n_89;
wire ARG__27_n_90;
wire ARG__27_n_91;
wire ARG__27_n_92;
wire ARG__27_n_93;
wire ARG__27_n_94;
wire ARG__27_n_95;
wire ARG__27_n_96;
wire ARG__27_n_97;
wire ARG__27_n_98;
wire ARG__27_n_99;
wire ARG__28_i_1_n_0;
wire ARG__28_n_100;
wire ARG__28_n_101;
wire ARG__28_n_102;
wire ARG__28_n_103;
wire ARG__28_n_104;
wire ARG__28_n_105;
wire ARG__28_n_92;
wire ARG__28_n_93;
wire ARG__28_n_94;
wire ARG__28_n_95;
wire ARG__28_n_96;
wire ARG__28_n_97;
wire ARG__28_n_98;
wire ARG__28_n_99;
wire ARG__29_i_1_n_0;
wire ARG__29_n_100;
wire ARG__29_n_101;
wire ARG__29_n_102;
wire ARG__29_n_103;
wire ARG__29_n_104;
wire ARG__29_n_105;
wire ARG__29_n_76;
wire ARG__29_n_77;
wire ARG__29_n_78;
wire ARG__29_n_79;
wire ARG__29_n_80;
wire ARG__29_n_81;
wire ARG__29_n_82;
wire ARG__29_n_83;
wire ARG__29_n_84;
wire ARG__29_n_85;
wire ARG__29_n_86;
wire ARG__29_n_87;
wire ARG__29_n_88;
wire ARG__29_n_89;
wire ARG__29_n_90;
wire ARG__29_n_91;
wire ARG__29_n_92;
wire ARG__29_n_93;
wire ARG__29_n_94;
wire ARG__29_n_95;
wire ARG__29_n_96;
wire ARG__29_n_97;
wire ARG__29_n_98;
wire ARG__29_n_99;
wire ARG__2_i_1_n_0;
wire ARG__2_n_100;
wire ARG__2_n_101;
wire ARG__2_n_102;
wire ARG__2_n_103;
wire ARG__2_n_104;
wire ARG__2_n_105;
wire ARG__2_n_92;
wire ARG__2_n_93;
wire ARG__2_n_94;
wire ARG__2_n_95;
wire ARG__2_n_96;
wire ARG__2_n_97;
wire ARG__2_n_98;
wire ARG__2_n_99;
wire ARG__30_i_1_n_0;
wire ARG__30_n_100;
wire ARG__30_n_101;
wire ARG__30_n_102;
wire ARG__30_n_103;
wire ARG__30_n_104;
wire ARG__30_n_105;
wire ARG__30_n_92;
wire ARG__30_n_93;
wire ARG__30_n_94;
wire ARG__30_n_95;
wire ARG__30_n_96;
wire ARG__30_n_97;
wire ARG__30_n_98;
wire ARG__30_n_99;
wire [32:17]ARG__31;
wire ARG__3_i_1_n_0;
wire ARG__3_n_100;
wire ARG__3_n_101;
wire ARG__3_n_102;
wire ARG__3_n_103;
wire ARG__3_n_104;
wire ARG__3_n_105;
wire ARG__3_n_76;
wire ARG__3_n_77;
wire ARG__3_n_78;
wire ARG__3_n_79;
wire ARG__3_n_80;
wire ARG__3_n_81;
wire ARG__3_n_82;
wire ARG__3_n_83;
wire ARG__3_n_84;
wire ARG__3_n_85;
wire ARG__3_n_86;
wire ARG__3_n_87;
wire ARG__3_n_88;
wire ARG__3_n_89;
wire ARG__3_n_90;
wire ARG__3_n_91;
wire ARG__3_n_92;
wire ARG__3_n_93;
wire ARG__3_n_94;
wire ARG__3_n_95;
wire ARG__3_n_96;
wire ARG__3_n_97;
wire ARG__3_n_98;
wire ARG__3_n_99;
wire ARG__4_i_1_n_0;
wire ARG__4_n_100;
wire ARG__4_n_101;
wire ARG__4_n_102;
wire ARG__4_n_103;
wire ARG__4_n_104;
wire ARG__4_n_105;
wire ARG__4_n_92;
wire ARG__4_n_93;
wire ARG__4_n_94;
wire ARG__4_n_95;
wire ARG__4_n_96;
wire ARG__4_n_97;
wire ARG__4_n_98;
wire ARG__4_n_99;
wire ARG__5_i_1_n_0;
wire ARG__5_n_100;
wire ARG__5_n_101;
wire ARG__5_n_102;
wire ARG__5_n_103;
wire ARG__5_n_104;
wire ARG__5_n_105;
wire ARG__5_n_76;
wire ARG__5_n_77;
wire ARG__5_n_78;
wire ARG__5_n_79;
wire ARG__5_n_80;
wire ARG__5_n_81;
wire ARG__5_n_82;
wire ARG__5_n_83;
wire ARG__5_n_84;
wire ARG__5_n_85;
wire ARG__5_n_86;
wire ARG__5_n_87;
wire ARG__5_n_88;
wire ARG__5_n_89;
wire ARG__5_n_90;
wire ARG__5_n_91;
wire ARG__5_n_92;
wire ARG__5_n_93;
wire ARG__5_n_94;
wire ARG__5_n_95;
wire ARG__5_n_96;
wire ARG__5_n_97;
wire ARG__5_n_98;
wire ARG__5_n_99;
wire ARG__6_i_1_n_0;
wire ARG__6_n_100;
wire ARG__6_n_101;
wire ARG__6_n_102;
wire ARG__6_n_103;
wire ARG__6_n_104;
wire ARG__6_n_105;
wire ARG__6_n_92;
wire ARG__6_n_93;
wire ARG__6_n_94;
wire ARG__6_n_95;
wire ARG__6_n_96;
wire ARG__6_n_97;
wire ARG__6_n_98;
wire ARG__6_n_99;
wire ARG__7_i_1_n_0;
wire ARG__7_n_100;
wire ARG__7_n_101;
wire ARG__7_n_102;
wire ARG__7_n_103;
wire ARG__7_n_104;
wire ARG__7_n_105;
wire ARG__7_n_76;
wire ARG__7_n_77;
wire ARG__7_n_78;
wire ARG__7_n_79;
wire ARG__7_n_80;
wire ARG__7_n_81;
wire ARG__7_n_82;
wire ARG__7_n_83;
wire ARG__7_n_84;
wire ARG__7_n_85;
wire ARG__7_n_86;
wire ARG__7_n_87;
wire ARG__7_n_88;
wire ARG__7_n_89;
wire ARG__7_n_90;
wire ARG__7_n_91;
wire ARG__7_n_92;
wire ARG__7_n_93;
wire ARG__7_n_94;
wire ARG__7_n_95;
wire ARG__7_n_96;
wire ARG__7_n_97;
wire ARG__7_n_98;
wire ARG__7_n_99;
wire ARG__8_i_1_n_0;
wire ARG__8_n_100;
wire ARG__8_n_101;
wire ARG__8_n_102;
wire ARG__8_n_103;
wire ARG__8_n_104;
wire ARG__8_n_105;
wire ARG__8_n_92;
wire ARG__8_n_93;
wire ARG__8_n_94;
wire ARG__8_n_95;
wire ARG__8_n_96;
wire ARG__8_n_97;
wire ARG__8_n_98;
wire ARG__8_n_99;
wire ARG__9_i_1_n_0;
wire ARG__9_n_100;
wire ARG__9_n_101;
wire ARG__9_n_102;
wire ARG__9_n_103;
wire ARG__9_n_104;
wire ARG__9_n_105;
wire ARG__9_n_76;
wire ARG__9_n_77;
wire ARG__9_n_78;
wire ARG__9_n_79;
wire ARG__9_n_80;
wire ARG__9_n_81;
wire ARG__9_n_82;
wire ARG__9_n_83;
wire ARG__9_n_84;
wire ARG__9_n_85;
wire ARG__9_n_86;
wire ARG__9_n_87;
wire ARG__9_n_88;
wire ARG__9_n_89;
wire ARG__9_n_90;
wire ARG__9_n_91;
wire ARG__9_n_92;
wire ARG__9_n_93;
wire ARG__9_n_94;
wire ARG__9_n_95;
wire ARG__9_n_96;
wire ARG__9_n_97;
wire ARG__9_n_98;
wire ARG__9_n_99;
wire ARG_carry__0_i_2_n_0;
wire ARG_carry__0_i_3_n_0;
wire ARG_carry__0_i_4_n_0;
wire ARG_carry__0_n_0;
wire ARG_carry__0_n_1;
wire ARG_carry__0_n_2;
wire ARG_carry__0_n_3;
wire ARG_carry__1_i_1_n_0;
wire ARG_carry__1_i_2_n_0;
wire ARG_carry__1_i_3_n_0;
wire ARG_carry__1_i_4_n_0;
wire ARG_carry__1_n_0;
wire ARG_carry__1_n_1;
wire ARG_carry__1_n_2;
wire ARG_carry__1_n_3;
wire ARG_carry__2_i_1_n_0;
wire ARG_carry__2_i_2_n_0;
wire ARG_carry__2_i_3_n_0;
wire ARG_carry__2_i_4_n_0;
wire ARG_carry__2_n_0;
wire ARG_carry__2_n_1;
wire ARG_carry__2_n_2;
wire ARG_carry__2_n_3;
wire ARG_carry__3_i_1_n_0;
wire ARG_carry__3_n_3;
wire ARG_carry_n_0;
wire ARG_carry_n_1;
wire ARG_carry_n_2;
wire ARG_carry_n_3;
wire ARG_i_1_n_0;
wire ARG_n_100;
wire ARG_n_101;
wire ARG_n_102;
wire ARG_n_103;
wire ARG_n_104;
wire ARG_n_105;
wire ARG_n_92;
wire ARG_n_93;
wire ARG_n_94;
wire ARG_n_95;
wire ARG_n_96;
wire ARG_n_97;
wire ARG_n_98;
wire ARG_n_99;
wire [0:0]DI;
wire IPCORE_CLK;
wire [14:0]Q;
wire [15:0]RESIZE15;
wire [15:0]RESIZE16;
wire [15:0]RESIZE18;
wire [15:0]RESIZE20;
wire [15:0]RESIZE22;
wire [15:0]RESIZE24;
wire [15:0]RESIZE26;
wire [15:0]RESIZE28;
wire [15:0]RESIZE30;
wire [15:0]RESIZE32;
wire [15:0]RESIZE34;
wire [15:0]RESIZE36;
wire [15:0]RESIZE38;
wire [15:0]RESIZE40;
wire [15:0]RESIZE42;
wire [15:0]RESIZE44;
wire [3:0]S;
wire add_temp_14__0_carry__0_i_1_n_0;
wire add_temp_14__0_carry__0_i_2_n_0;
wire add_temp_14__0_carry__0_i_3_n_0;
wire add_temp_14__0_carry__0_i_4_n_0;
wire add_temp_14__0_carry__0_i_5_n_0;
wire add_temp_14__0_carry__0_i_6_n_0;
wire add_temp_14__0_carry__0_i_7_n_0;
wire add_temp_14__0_carry__0_i_8_n_0;
wire add_temp_14__0_carry__0_n_0;
wire add_temp_14__0_carry__0_n_1;
wire add_temp_14__0_carry__0_n_2;
wire add_temp_14__0_carry__0_n_3;
wire add_temp_14__0_carry__0_n_4;
wire add_temp_14__0_carry__0_n_5;
wire add_temp_14__0_carry__0_n_6;
wire add_temp_14__0_carry__0_n_7;
wire add_temp_14__0_carry__1_i_1_n_0;
wire add_temp_14__0_carry__1_i_2_n_0;
wire add_temp_14__0_carry__1_i_3_n_0;
wire add_temp_14__0_carry__1_i_4_n_0;
wire add_temp_14__0_carry__1_i_5_n_0;
wire add_temp_14__0_carry__1_i_6_n_0;
wire add_temp_14__0_carry__1_i_7_n_0;
wire add_temp_14__0_carry__1_i_8_n_0;
wire add_temp_14__0_carry__1_n_0;
wire add_temp_14__0_carry__1_n_1;
wire add_temp_14__0_carry__1_n_2;
wire add_temp_14__0_carry__1_n_3;
wire add_temp_14__0_carry__1_n_4;
wire add_temp_14__0_carry__1_n_5;
wire add_temp_14__0_carry__1_n_6;
wire add_temp_14__0_carry__1_n_7;
wire add_temp_14__0_carry__2_i_1_n_0;
wire add_temp_14__0_carry__2_i_2_n_0;
wire add_temp_14__0_carry__2_i_3_n_0;
wire add_temp_14__0_carry__2_i_4_n_0;
wire add_temp_14__0_carry__2_i_5_n_0;
wire add_temp_14__0_carry__2_i_6_n_0;
wire add_temp_14__0_carry__2_i_7_n_0;
wire add_temp_14__0_carry__2_n_1;
wire add_temp_14__0_carry__2_n_2;
wire add_temp_14__0_carry__2_n_3;
wire add_temp_14__0_carry__2_n_4;
wire add_temp_14__0_carry__2_n_5;
wire add_temp_14__0_carry__2_n_6;
wire add_temp_14__0_carry__2_n_7;
wire add_temp_14__0_carry_i_1_n_0;
wire add_temp_14__0_carry_i_2_n_0;
wire add_temp_14__0_carry_i_3_n_0;
wire add_temp_14__0_carry_i_4_n_0;
wire add_temp_14__0_carry_i_5_n_0;
wire add_temp_14__0_carry_i_6_n_0;
wire add_temp_14__0_carry_i_7_n_0;
wire add_temp_14__0_carry_n_0;
wire add_temp_14__0_carry_n_1;
wire add_temp_14__0_carry_n_2;
wire add_temp_14__0_carry_n_3;
wire add_temp_14__0_carry_n_4;
wire add_temp_14__0_carry_n_5;
wire add_temp_14__0_carry_n_6;
wire add_temp_14__0_carry_n_7;
wire add_temp_14__138_carry__0_i_1_n_0;
wire add_temp_14__138_carry__0_i_2_n_0;
wire add_temp_14__138_carry__0_i_3_n_0;
wire add_temp_14__138_carry__0_i_4_n_0;
wire add_temp_14__138_carry__0_i_5_n_0;
wire add_temp_14__138_carry__0_i_6_n_0;
wire add_temp_14__138_carry__0_i_7_n_0;
wire add_temp_14__138_carry__0_i_8_n_0;
wire add_temp_14__138_carry__0_n_0;
wire add_temp_14__138_carry__0_n_1;
wire add_temp_14__138_carry__0_n_2;
wire add_temp_14__138_carry__0_n_3;
wire add_temp_14__138_carry__0_n_4;
wire add_temp_14__138_carry__0_n_5;
wire add_temp_14__138_carry__0_n_6;
wire add_temp_14__138_carry__0_n_7;
wire add_temp_14__138_carry__1_i_1_n_0;
wire add_temp_14__138_carry__1_i_2_n_0;
wire add_temp_14__138_carry__1_i_3_n_0;
wire add_temp_14__138_carry__1_i_4_n_0;
wire add_temp_14__138_carry__1_i_5_n_0;
wire add_temp_14__138_carry__1_i_6_n_0;
wire add_temp_14__138_carry__1_i_7_n_0;
wire add_temp_14__138_carry__1_i_8_n_0;
wire add_temp_14__138_carry__1_n_0;
wire add_temp_14__138_carry__1_n_1;
wire add_temp_14__138_carry__1_n_2;
wire add_temp_14__138_carry__1_n_3;
wire add_temp_14__138_carry__1_n_4;
wire add_temp_14__138_carry__1_n_5;
wire add_temp_14__138_carry__1_n_6;
wire add_temp_14__138_carry__1_n_7;
wire add_temp_14__138_carry__2_i_1_n_0;
wire add_temp_14__138_carry__2_i_2_n_0;
wire add_temp_14__138_carry__2_i_3_n_0;
wire add_temp_14__138_carry__2_i_4_n_0;
wire add_temp_14__138_carry__2_i_5_n_0;
wire add_temp_14__138_carry__2_i_6_n_0;
wire add_temp_14__138_carry__2_i_7_n_0;
wire add_temp_14__138_carry__2_n_1;
wire add_temp_14__138_carry__2_n_2;
wire add_temp_14__138_carry__2_n_3;
wire add_temp_14__138_carry__2_n_4;
wire add_temp_14__138_carry__2_n_5;
wire add_temp_14__138_carry__2_n_6;
wire add_temp_14__138_carry__2_n_7;
wire add_temp_14__138_carry_i_1_n_0;
wire add_temp_14__138_carry_i_2_n_0;
wire add_temp_14__138_carry_i_3_n_0;
wire add_temp_14__138_carry_i_4_n_0;
wire add_temp_14__138_carry_i_5_n_0;
wire add_temp_14__138_carry_i_6_n_0;
wire add_temp_14__138_carry_i_7_n_0;
wire add_temp_14__138_carry_n_0;
wire add_temp_14__138_carry_n_1;
wire add_temp_14__138_carry_n_2;
wire add_temp_14__138_carry_n_3;
wire add_temp_14__138_carry_n_4;
wire add_temp_14__138_carry_n_5;
wire add_temp_14__138_carry_n_6;
wire add_temp_14__138_carry_n_7;
wire add_temp_14__184_carry__0_i_1_n_0;
wire add_temp_14__184_carry__0_i_2_n_0;
wire add_temp_14__184_carry__0_i_3_n_0;
wire add_temp_14__184_carry__0_i_4_n_0;
wire add_temp_14__184_carry__0_i_5_n_0;
wire add_temp_14__184_carry__0_i_6_n_0;
wire add_temp_14__184_carry__0_i_7_n_0;
wire add_temp_14__184_carry__0_i_8_n_0;
wire add_temp_14__184_carry__0_n_0;
wire add_temp_14__184_carry__0_n_1;
wire add_temp_14__184_carry__0_n_2;
wire add_temp_14__184_carry__0_n_3;
wire add_temp_14__184_carry__0_n_4;
wire add_temp_14__184_carry__0_n_5;
wire add_temp_14__184_carry__0_n_6;
wire add_temp_14__184_carry__0_n_7;
wire add_temp_14__184_carry__1_i_1_n_0;
wire add_temp_14__184_carry__1_i_2_n_0;
wire add_temp_14__184_carry__1_i_3_n_0;
wire add_temp_14__184_carry__1_i_4_n_0;
wire add_temp_14__184_carry__1_i_5_n_0;
wire add_temp_14__184_carry__1_i_6_n_0;
wire add_temp_14__184_carry__1_i_7_n_0;
wire add_temp_14__184_carry__1_i_8_n_0;
wire add_temp_14__184_carry__1_n_0;
wire add_temp_14__184_carry__1_n_1;
wire add_temp_14__184_carry__1_n_2;
wire add_temp_14__184_carry__1_n_3;
wire add_temp_14__184_carry__1_n_4;
wire add_temp_14__184_carry__1_n_5;
wire add_temp_14__184_carry__1_n_6;
wire add_temp_14__184_carry__1_n_7;
wire add_temp_14__184_carry__2_i_1_n_0;
wire add_temp_14__184_carry__2_i_2_n_0;
wire add_temp_14__184_carry__2_i_3_n_0;
wire add_temp_14__184_carry__2_i_4_n_0;
wire add_temp_14__184_carry__2_i_5_n_0;
wire add_temp_14__184_carry__2_i_6_n_0;
wire add_temp_14__184_carry__2_i_7_n_0;
wire add_temp_14__184_carry__2_n_1;
wire add_temp_14__184_carry__2_n_2;
wire add_temp_14__184_carry__2_n_3;
wire add_temp_14__184_carry__2_n_4;
wire add_temp_14__184_carry__2_n_5;
wire add_temp_14__184_carry__2_n_6;
wire add_temp_14__184_carry__2_n_7;
wire add_temp_14__184_carry_i_1_n_0;
wire add_temp_14__184_carry_i_2_n_0;
wire add_temp_14__184_carry_i_3_n_0;
wire add_temp_14__184_carry_i_4_n_0;
wire add_temp_14__184_carry_i_5_n_0;
wire add_temp_14__184_carry_i_6_n_0;
wire add_temp_14__184_carry_i_7_n_0;
wire add_temp_14__184_carry_n_0;
wire add_temp_14__184_carry_n_1;
wire add_temp_14__184_carry_n_2;
wire add_temp_14__184_carry_n_3;
wire add_temp_14__184_carry_n_4;
wire add_temp_14__184_carry_n_5;
wire add_temp_14__184_carry_n_6;
wire add_temp_14__184_carry_n_7;
wire add_temp_14__230_carry__0_i_1_n_0;
wire add_temp_14__230_carry__0_i_2_n_0;
wire add_temp_14__230_carry__0_i_3_n_0;
wire add_temp_14__230_carry__0_i_4_n_0;
wire add_temp_14__230_carry__0_i_5_n_0;
wire add_temp_14__230_carry__0_i_6_n_0;
wire add_temp_14__230_carry__0_i_7_n_0;
wire add_temp_14__230_carry__0_i_8_n_0;
wire add_temp_14__230_carry__0_n_0;
wire add_temp_14__230_carry__0_n_1;
wire add_temp_14__230_carry__0_n_2;
wire add_temp_14__230_carry__0_n_3;
wire add_temp_14__230_carry__0_n_4;
wire add_temp_14__230_carry__0_n_5;
wire add_temp_14__230_carry__0_n_6;
wire add_temp_14__230_carry__0_n_7;
wire add_temp_14__230_carry__1_i_1_n_0;
wire add_temp_14__230_carry__1_i_2_n_0;
wire add_temp_14__230_carry__1_i_3_n_0;
wire add_temp_14__230_carry__1_i_4_n_0;
wire add_temp_14__230_carry__1_i_5_n_0;
wire add_temp_14__230_carry__1_i_6_n_0;
wire add_temp_14__230_carry__1_i_7_n_0;
wire add_temp_14__230_carry__1_i_8_n_0;
wire add_temp_14__230_carry__1_n_0;
wire add_temp_14__230_carry__1_n_1;
wire add_temp_14__230_carry__1_n_2;
wire add_temp_14__230_carry__1_n_3;
wire add_temp_14__230_carry__1_n_4;
wire add_temp_14__230_carry__1_n_5;
wire add_temp_14__230_carry__1_n_6;
wire add_temp_14__230_carry__1_n_7;
wire add_temp_14__230_carry__2_i_1_n_0;
wire add_temp_14__230_carry__2_i_2_n_0;
wire add_temp_14__230_carry__2_i_3_n_0;
wire add_temp_14__230_carry__2_i_4_n_0;
wire add_temp_14__230_carry__2_i_5_n_0;
wire add_temp_14__230_carry__2_i_6_n_0;
wire add_temp_14__230_carry__2_i_7_n_0;
wire add_temp_14__230_carry__2_n_1;
wire add_temp_14__230_carry__2_n_2;
wire add_temp_14__230_carry__2_n_3;
wire add_temp_14__230_carry__2_n_4;
wire add_temp_14__230_carry__2_n_5;
wire add_temp_14__230_carry__2_n_6;
wire add_temp_14__230_carry__2_n_7;
wire add_temp_14__230_carry_i_1_n_0;
wire add_temp_14__230_carry_i_2_n_0;
wire add_temp_14__230_carry_i_3_n_0;
wire add_temp_14__230_carry_i_4_n_0;
wire add_temp_14__230_carry_i_5_n_0;
wire add_temp_14__230_carry_i_6_n_0;
wire add_temp_14__230_carry_i_7_n_0;
wire add_temp_14__230_carry_n_0;
wire add_temp_14__230_carry_n_1;
wire add_temp_14__230_carry_n_2;
wire add_temp_14__230_carry_n_3;
wire add_temp_14__230_carry_n_4;
wire add_temp_14__230_carry_n_5;
wire add_temp_14__230_carry_n_6;
wire add_temp_14__230_carry_n_7;
wire add_temp_14__278_carry__0_i_10_n_0;
wire add_temp_14__278_carry__0_i_11_n_0;
wire add_temp_14__278_carry__0_i_12_n_0;
wire add_temp_14__278_carry__0_i_1_n_0;
wire add_temp_14__278_carry__0_i_2_n_0;
wire add_temp_14__278_carry__0_i_3_n_0;
wire add_temp_14__278_carry__0_i_4_n_0;
wire add_temp_14__278_carry__0_i_5_n_0;
wire add_temp_14__278_carry__0_i_6_n_0;
wire add_temp_14__278_carry__0_i_7_n_0;
wire add_temp_14__278_carry__0_i_8_n_0;
wire add_temp_14__278_carry__0_i_9_n_0;
wire add_temp_14__278_carry__0_n_0;
wire add_temp_14__278_carry__0_n_1;
wire add_temp_14__278_carry__0_n_2;
wire add_temp_14__278_carry__0_n_3;
wire add_temp_14__278_carry__1_i_10_n_0;
wire add_temp_14__278_carry__1_i_11_n_0;
wire add_temp_14__278_carry__1_i_12_n_0;
wire add_temp_14__278_carry__1_i_1_n_0;
wire add_temp_14__278_carry__1_i_2_n_0;
wire add_temp_14__278_carry__1_i_3_n_0;
wire add_temp_14__278_carry__1_i_4_n_0;
wire add_temp_14__278_carry__1_i_5_n_0;
wire add_temp_14__278_carry__1_i_6_n_0;
wire add_temp_14__278_carry__1_i_7_n_0;
wire add_temp_14__278_carry__1_i_8_n_0;
wire add_temp_14__278_carry__1_i_9_n_0;
wire add_temp_14__278_carry__1_n_0;
wire add_temp_14__278_carry__1_n_1;
wire add_temp_14__278_carry__1_n_2;
wire add_temp_14__278_carry__1_n_3;
wire add_temp_14__278_carry__2_i_10_n_0;
wire add_temp_14__278_carry__2_i_11_n_0;
wire add_temp_14__278_carry__2_i_1_n_0;
wire add_temp_14__278_carry__2_i_2_n_0;
wire add_temp_14__278_carry__2_i_3_n_0;
wire add_temp_14__278_carry__2_i_4_n_0;
wire add_temp_14__278_carry__2_i_5_n_0;
wire add_temp_14__278_carry__2_i_6_n_0;
wire add_temp_14__278_carry__2_i_7_n_0;
wire add_temp_14__278_carry__2_i_8_n_0;
wire add_temp_14__278_carry__2_i_9_n_0;
wire add_temp_14__278_carry__2_n_1;
wire add_temp_14__278_carry__2_n_2;
wire add_temp_14__278_carry__2_n_3;
wire add_temp_14__278_carry_i_10_n_0;
wire add_temp_14__278_carry_i_1_n_0;
wire add_temp_14__278_carry_i_2_n_0;
wire add_temp_14__278_carry_i_3_n_0;
wire add_temp_14__278_carry_i_4_n_0;
wire add_temp_14__278_carry_i_5_n_0;
wire add_temp_14__278_carry_i_6_n_0;
wire add_temp_14__278_carry_i_7_n_0;
wire add_temp_14__278_carry_i_8_n_0;
wire add_temp_14__278_carry_i_9_n_0;
wire add_temp_14__278_carry_n_0;
wire add_temp_14__278_carry_n_1;
wire add_temp_14__278_carry_n_2;
wire add_temp_14__278_carry_n_3;
wire add_temp_14__46_carry__0_i_1_n_0;
wire add_temp_14__46_carry__0_i_2_n_0;
wire add_temp_14__46_carry__0_i_3_n_0;
wire add_temp_14__46_carry__0_i_4_n_0;
wire add_temp_14__46_carry__0_i_5_n_0;
wire add_temp_14__46_carry__0_i_6_n_0;
wire add_temp_14__46_carry__0_i_7_n_0;
wire add_temp_14__46_carry__0_i_8_n_0;
wire add_temp_14__46_carry__0_n_0;
wire add_temp_14__46_carry__0_n_1;
wire add_temp_14__46_carry__0_n_2;
wire add_temp_14__46_carry__0_n_3;
wire add_temp_14__46_carry__0_n_4;
wire add_temp_14__46_carry__0_n_5;
wire add_temp_14__46_carry__0_n_6;
wire add_temp_14__46_carry__0_n_7;
wire add_temp_14__46_carry__1_i_1_n_0;
wire add_temp_14__46_carry__1_i_2_n_0;
wire add_temp_14__46_carry__1_i_3_n_0;
wire add_temp_14__46_carry__1_i_4_n_0;
wire add_temp_14__46_carry__1_i_5_n_0;
wire add_temp_14__46_carry__1_i_6_n_0;
wire add_temp_14__46_carry__1_i_7_n_0;
wire add_temp_14__46_carry__1_i_8_n_0;
wire add_temp_14__46_carry__1_n_0;
wire add_temp_14__46_carry__1_n_1;
wire add_temp_14__46_carry__1_n_2;
wire add_temp_14__46_carry__1_n_3;
wire add_temp_14__46_carry__1_n_4;
wire add_temp_14__46_carry__1_n_5;
wire add_temp_14__46_carry__1_n_6;
wire add_temp_14__46_carry__1_n_7;
wire add_temp_14__46_carry__2_i_1_n_0;
wire add_temp_14__46_carry__2_i_2_n_0;
wire add_temp_14__46_carry__2_i_3_n_0;
wire add_temp_14__46_carry__2_i_4_n_0;
wire add_temp_14__46_carry__2_i_5_n_0;
wire add_temp_14__46_carry__2_i_6_n_0;
wire add_temp_14__46_carry__2_i_7_n_0;
wire add_temp_14__46_carry__2_n_1;
wire add_temp_14__46_carry__2_n_2;
wire add_temp_14__46_carry__2_n_3;
wire add_temp_14__46_carry__2_n_4;
wire add_temp_14__46_carry__2_n_5;
wire add_temp_14__46_carry__2_n_6;
wire add_temp_14__46_carry__2_n_7;
wire add_temp_14__46_carry_i_1_n_0;
wire add_temp_14__46_carry_i_2_n_0;
wire add_temp_14__46_carry_i_3_n_0;
wire add_temp_14__46_carry_i_4_n_0;
wire add_temp_14__46_carry_i_5_n_0;
wire add_temp_14__46_carry_i_6_n_0;
wire add_temp_14__46_carry_i_7_n_0;
wire add_temp_14__46_carry_n_0;
wire add_temp_14__46_carry_n_1;
wire add_temp_14__46_carry_n_2;
wire add_temp_14__46_carry_n_3;
wire add_temp_14__46_carry_n_4;
wire add_temp_14__46_carry_n_5;
wire add_temp_14__46_carry_n_6;
wire add_temp_14__46_carry_n_7;
wire add_temp_14__92_carry__0_i_1_n_0;
wire add_temp_14__92_carry__0_i_2_n_0;
wire add_temp_14__92_carry__0_i_3_n_0;
wire add_temp_14__92_carry__0_i_4_n_0;
wire add_temp_14__92_carry__0_i_5_n_0;
wire add_temp_14__92_carry__0_i_6_n_0;
wire add_temp_14__92_carry__0_i_7_n_0;
wire add_temp_14__92_carry__0_i_8_n_0;
wire add_temp_14__92_carry__0_n_0;
wire add_temp_14__92_carry__0_n_1;
wire add_temp_14__92_carry__0_n_2;
wire add_temp_14__92_carry__0_n_3;
wire add_temp_14__92_carry__0_n_4;
wire add_temp_14__92_carry__0_n_5;
wire add_temp_14__92_carry__0_n_6;
wire add_temp_14__92_carry__0_n_7;
wire add_temp_14__92_carry__1_i_1_n_0;
wire add_temp_14__92_carry__1_i_2_n_0;
wire add_temp_14__92_carry__1_i_3_n_0;
wire add_temp_14__92_carry__1_i_4_n_0;
wire add_temp_14__92_carry__1_i_5_n_0;
wire add_temp_14__92_carry__1_i_6_n_0;
wire add_temp_14__92_carry__1_i_7_n_0;
wire add_temp_14__92_carry__1_i_8_n_0;
wire add_temp_14__92_carry__1_n_0;
wire add_temp_14__92_carry__1_n_1;
wire add_temp_14__92_carry__1_n_2;
wire add_temp_14__92_carry__1_n_3;
wire add_temp_14__92_carry__1_n_4;
wire add_temp_14__92_carry__1_n_5;
wire add_temp_14__92_carry__1_n_6;
wire add_temp_14__92_carry__1_n_7;
wire add_temp_14__92_carry__2_i_1_n_0;
wire add_temp_14__92_carry__2_i_2_n_0;
wire add_temp_14__92_carry__2_i_3_n_0;
wire add_temp_14__92_carry__2_i_4_n_0;
wire add_temp_14__92_carry__2_i_5_n_0;
wire add_temp_14__92_carry__2_i_6_n_0;
wire add_temp_14__92_carry__2_i_7_n_0;
wire add_temp_14__92_carry__2_n_1;
wire add_temp_14__92_carry__2_n_2;
wire add_temp_14__92_carry__2_n_3;
wire add_temp_14__92_carry__2_n_4;
wire add_temp_14__92_carry__2_n_5;
wire add_temp_14__92_carry__2_n_6;
wire add_temp_14__92_carry__2_n_7;
wire add_temp_14__92_carry_i_1_n_0;
wire add_temp_14__92_carry_i_2_n_0;
wire add_temp_14__92_carry_i_3_n_0;
wire add_temp_14__92_carry_i_4_n_0;
wire add_temp_14__92_carry_i_5_n_0;
wire add_temp_14__92_carry_i_6_n_0;
wire add_temp_14__92_carry_i_7_n_0;
wire add_temp_14__92_carry_n_0;
wire add_temp_14__92_carry_n_1;
wire add_temp_14__92_carry_n_2;
wire add_temp_14__92_carry_n_3;
wire add_temp_14__92_carry_n_4;
wire add_temp_14__92_carry_n_5;
wire add_temp_14__92_carry_n_6;
wire add_temp_14__92_carry_n_7;
wire cop_dut_enable;
wire [15:0]\data_pipeline_tmp_reg[0] ;
wire [15:0]\data_pipeline_tmp_reg[10] ;
wire [15:0]\data_pipeline_tmp_reg[11] ;
wire [15:0]\data_pipeline_tmp_reg[12] ;
wire [15:0]\data_pipeline_tmp_reg[13] ;
wire [15:0]\data_pipeline_tmp_reg[14] ;
wire [15:0]\data_pipeline_tmp_reg[1] ;
wire [15:0]\data_pipeline_tmp_reg[2] ;
wire [15:0]\data_pipeline_tmp_reg[3] ;
wire [15:0]\data_pipeline_tmp_reg[4] ;
wire [15:0]\data_pipeline_tmp_reg[5] ;
wire [15:0]\data_pipeline_tmp_reg[6] ;
wire [15:0]\data_pipeline_tmp_reg[7] ;
wire [15:0]\data_pipeline_tmp_reg[8] ;
wire [15:0]\data_pipeline_tmp_reg[9] ;
wire [15:0]filter_sum;
wire [15:0]in;
wire [14:14]\^mul_temp ;
wire [14:14]\^mul_temp_1 ;
wire [14:14]\^mul_temp_10 ;
wire mul_temp_10_n_100;
wire mul_temp_10_n_101;
wire mul_temp_10_n_102;
wire mul_temp_10_n_103;
wire mul_temp_10_n_104;
wire mul_temp_10_n_105;
wire mul_temp_10_n_74;
wire mul_temp_10_n_75;
wire mul_temp_10_n_76;
wire mul_temp_10_n_77;
wire mul_temp_10_n_78;
wire mul_temp_10_n_79;
wire mul_temp_10_n_80;
wire mul_temp_10_n_81;
wire mul_temp_10_n_82;
wire mul_temp_10_n_83;
wire mul_temp_10_n_84;
wire mul_temp_10_n_85;
wire mul_temp_10_n_86;
wire mul_temp_10_n_87;
wire mul_temp_10_n_88;
wire mul_temp_10_n_89;
wire mul_temp_10_n_90;
wire mul_temp_10_n_92;
wire mul_temp_10_n_93;
wire mul_temp_10_n_94;
wire mul_temp_10_n_95;
wire mul_temp_10_n_96;
wire mul_temp_10_n_97;
wire mul_temp_10_n_98;
wire mul_temp_10_n_99;
wire [14:14]\^mul_temp_11 ;
wire mul_temp_11_n_100;
wire mul_temp_11_n_101;
wire mul_temp_11_n_102;
wire mul_temp_11_n_103;
wire mul_temp_11_n_104;
wire mul_temp_11_n_105;
wire mul_temp_11_n_74;
wire mul_temp_11_n_75;
wire mul_temp_11_n_76;
wire mul_temp_11_n_77;
wire mul_temp_11_n_78;
wire mul_temp_11_n_79;
wire mul_temp_11_n_80;
wire mul_temp_11_n_81;
wire mul_temp_11_n_82;
wire mul_temp_11_n_83;
wire mul_temp_11_n_84;
wire mul_temp_11_n_85;
wire mul_temp_11_n_86;
wire mul_temp_11_n_87;
wire mul_temp_11_n_88;
wire mul_temp_11_n_89;
wire mul_temp_11_n_90;
wire mul_temp_11_n_92;
wire mul_temp_11_n_93;
wire mul_temp_11_n_94;
wire mul_temp_11_n_95;
wire mul_temp_11_n_96;
wire mul_temp_11_n_97;
wire mul_temp_11_n_98;
wire mul_temp_11_n_99;
wire [14:14]\^mul_temp_12 ;
wire mul_temp_12_n_100;
wire mul_temp_12_n_101;
wire mul_temp_12_n_102;
wire mul_temp_12_n_103;
wire mul_temp_12_n_104;
wire mul_temp_12_n_105;
wire mul_temp_12_n_74;
wire mul_temp_12_n_75;
wire mul_temp_12_n_76;
wire mul_temp_12_n_77;
wire mul_temp_12_n_78;
wire mul_temp_12_n_79;
wire mul_temp_12_n_80;
wire mul_temp_12_n_81;
wire mul_temp_12_n_82;
wire mul_temp_12_n_83;
wire mul_temp_12_n_84;
wire mul_temp_12_n_85;
wire mul_temp_12_n_86;
wire mul_temp_12_n_87;
wire mul_temp_12_n_88;
wire mul_temp_12_n_89;
wire mul_temp_12_n_90;
wire mul_temp_12_n_92;
wire mul_temp_12_n_93;
wire mul_temp_12_n_94;
wire mul_temp_12_n_95;
wire mul_temp_12_n_96;
wire mul_temp_12_n_97;
wire mul_temp_12_n_98;
wire mul_temp_12_n_99;
wire [14:14]\^mul_temp_13 ;
wire mul_temp_13_n_100;
wire mul_temp_13_n_101;
wire mul_temp_13_n_102;
wire mul_temp_13_n_103;
wire mul_temp_13_n_104;
wire mul_temp_13_n_105;
wire mul_temp_13_n_74;
wire mul_temp_13_n_75;
wire mul_temp_13_n_76;
wire mul_temp_13_n_77;
wire mul_temp_13_n_78;
wire mul_temp_13_n_79;
wire mul_temp_13_n_80;
wire mul_temp_13_n_81;
wire mul_temp_13_n_82;
wire mul_temp_13_n_83;
wire mul_temp_13_n_84;
wire mul_temp_13_n_85;
wire mul_temp_13_n_86;
wire mul_temp_13_n_87;
wire mul_temp_13_n_88;
wire mul_temp_13_n_89;
wire mul_temp_13_n_90;
wire mul_temp_13_n_92;
wire mul_temp_13_n_93;
wire mul_temp_13_n_94;
wire mul_temp_13_n_95;
wire mul_temp_13_n_96;
wire mul_temp_13_n_97;
wire mul_temp_13_n_98;
wire mul_temp_13_n_99;
wire [14:14]\^mul_temp_14 ;
wire mul_temp_14_n_100;
wire mul_temp_14_n_101;
wire mul_temp_14_n_102;
wire mul_temp_14_n_103;
wire mul_temp_14_n_104;
wire mul_temp_14_n_105;
wire mul_temp_14_n_74;
wire mul_temp_14_n_75;
wire mul_temp_14_n_76;
wire mul_temp_14_n_77;
wire mul_temp_14_n_78;
wire mul_temp_14_n_79;
wire mul_temp_14_n_80;
wire mul_temp_14_n_81;
wire mul_temp_14_n_82;
wire mul_temp_14_n_83;
wire mul_temp_14_n_84;
wire mul_temp_14_n_85;
wire mul_temp_14_n_86;
wire mul_temp_14_n_87;
wire mul_temp_14_n_88;
wire mul_temp_14_n_89;
wire mul_temp_14_n_90;
wire mul_temp_14_n_92;
wire mul_temp_14_n_93;
wire mul_temp_14_n_94;
wire mul_temp_14_n_95;
wire mul_temp_14_n_96;
wire mul_temp_14_n_97;
wire mul_temp_14_n_98;
wire mul_temp_14_n_99;
wire [14:14]\^mul_temp_15 ;
wire mul_temp_15_n_100;
wire mul_temp_15_n_101;
wire mul_temp_15_n_102;
wire mul_temp_15_n_103;
wire mul_temp_15_n_104;
wire mul_temp_15_n_105;
wire mul_temp_15_n_74;
wire mul_temp_15_n_75;
wire mul_temp_15_n_76;
wire mul_temp_15_n_77;
wire mul_temp_15_n_78;
wire mul_temp_15_n_79;
wire mul_temp_15_n_80;
wire mul_temp_15_n_81;
wire mul_temp_15_n_82;
wire mul_temp_15_n_83;
wire mul_temp_15_n_84;
wire mul_temp_15_n_85;
wire mul_temp_15_n_86;
wire mul_temp_15_n_87;
wire mul_temp_15_n_88;
wire mul_temp_15_n_89;
wire mul_temp_15_n_90;
wire mul_temp_15_n_92;
wire mul_temp_15_n_93;
wire mul_temp_15_n_94;
wire mul_temp_15_n_95;
wire mul_temp_15_n_96;
wire mul_temp_15_n_97;
wire mul_temp_15_n_98;
wire mul_temp_15_n_99;
wire [15:0]mul_temp_16;
wire [14:14]\^mul_temp_17 ;
wire mul_temp_17_n_100;
wire mul_temp_17_n_101;
wire mul_temp_17_n_102;
wire mul_temp_17_n_103;
wire mul_temp_17_n_104;
wire mul_temp_17_n_105;
wire mul_temp_17_n_74;
wire mul_temp_17_n_75;
wire mul_temp_17_n_76;
wire mul_temp_17_n_77;
wire mul_temp_17_n_78;
wire mul_temp_17_n_79;
wire mul_temp_17_n_80;
wire mul_temp_17_n_81;
wire mul_temp_17_n_82;
wire mul_temp_17_n_83;
wire mul_temp_17_n_84;
wire mul_temp_17_n_85;
wire mul_temp_17_n_86;
wire mul_temp_17_n_87;
wire mul_temp_17_n_88;
wire mul_temp_17_n_89;
wire mul_temp_17_n_90;
wire mul_temp_17_n_92;
wire mul_temp_17_n_93;
wire mul_temp_17_n_94;
wire mul_temp_17_n_95;
wire mul_temp_17_n_96;
wire mul_temp_17_n_97;
wire mul_temp_17_n_98;
wire mul_temp_17_n_99;
wire [14:14]\^mul_temp_18 ;
wire mul_temp_18_n_100;
wire mul_temp_18_n_101;
wire mul_temp_18_n_102;
wire mul_temp_18_n_103;
wire mul_temp_18_n_104;
wire mul_temp_18_n_105;
wire mul_temp_18_n_74;
wire mul_temp_18_n_75;
wire mul_temp_18_n_76;
wire mul_temp_18_n_77;
wire mul_temp_18_n_78;
wire mul_temp_18_n_79;
wire mul_temp_18_n_80;
wire mul_temp_18_n_81;
wire mul_temp_18_n_82;
wire mul_temp_18_n_83;
wire mul_temp_18_n_84;
wire mul_temp_18_n_85;
wire mul_temp_18_n_86;
wire mul_temp_18_n_87;
wire mul_temp_18_n_88;
wire mul_temp_18_n_89;
wire mul_temp_18_n_90;
wire mul_temp_18_n_92;
wire mul_temp_18_n_93;
wire mul_temp_18_n_94;
wire mul_temp_18_n_95;
wire mul_temp_18_n_96;
wire mul_temp_18_n_97;
wire mul_temp_18_n_98;
wire mul_temp_18_n_99;
wire [14:14]\^mul_temp_19 ;
wire mul_temp_19_n_100;
wire mul_temp_19_n_101;
wire mul_temp_19_n_102;
wire mul_temp_19_n_103;
wire mul_temp_19_n_104;
wire mul_temp_19_n_105;
wire mul_temp_19_n_74;
wire mul_temp_19_n_75;
wire mul_temp_19_n_76;
wire mul_temp_19_n_77;
wire mul_temp_19_n_78;
wire mul_temp_19_n_79;
wire mul_temp_19_n_80;
wire mul_temp_19_n_81;
wire mul_temp_19_n_82;
wire mul_temp_19_n_83;
wire mul_temp_19_n_84;
wire mul_temp_19_n_85;
wire mul_temp_19_n_86;
wire mul_temp_19_n_87;
wire mul_temp_19_n_88;
wire mul_temp_19_n_89;
wire mul_temp_19_n_90;
wire mul_temp_19_n_92;
wire mul_temp_19_n_93;
wire mul_temp_19_n_94;
wire mul_temp_19_n_95;
wire mul_temp_19_n_96;
wire mul_temp_19_n_97;
wire mul_temp_19_n_98;
wire mul_temp_19_n_99;
wire mul_temp_1_n_100;
wire mul_temp_1_n_101;
wire mul_temp_1_n_102;
wire mul_temp_1_n_103;
wire mul_temp_1_n_104;
wire mul_temp_1_n_105;
wire mul_temp_1_n_74;
wire mul_temp_1_n_75;
wire mul_temp_1_n_76;
wire mul_temp_1_n_77;
wire mul_temp_1_n_78;
wire mul_temp_1_n_79;
wire mul_temp_1_n_80;
wire mul_temp_1_n_81;
wire mul_temp_1_n_82;
wire mul_temp_1_n_83;
wire mul_temp_1_n_84;
wire mul_temp_1_n_85;
wire mul_temp_1_n_86;
wire mul_temp_1_n_87;
wire mul_temp_1_n_88;
wire mul_temp_1_n_89;
wire mul_temp_1_n_90;
wire mul_temp_1_n_92;
wire mul_temp_1_n_93;
wire mul_temp_1_n_94;
wire mul_temp_1_n_95;
wire mul_temp_1_n_96;
wire mul_temp_1_n_97;
wire mul_temp_1_n_98;
wire mul_temp_1_n_99;
wire [14:14]\^mul_temp_2 ;
wire [14:14]\^mul_temp_20 ;
wire mul_temp_20_n_100;
wire mul_temp_20_n_101;
wire mul_temp_20_n_102;
wire mul_temp_20_n_103;
wire mul_temp_20_n_104;
wire mul_temp_20_n_105;
wire mul_temp_20_n_74;
wire mul_temp_20_n_75;
wire mul_temp_20_n_76;
wire mul_temp_20_n_77;
wire mul_temp_20_n_78;
wire mul_temp_20_n_79;
wire mul_temp_20_n_80;
wire mul_temp_20_n_81;
wire mul_temp_20_n_82;
wire mul_temp_20_n_83;
wire mul_temp_20_n_84;
wire mul_temp_20_n_85;
wire mul_temp_20_n_86;
wire mul_temp_20_n_87;
wire mul_temp_20_n_88;
wire mul_temp_20_n_89;
wire mul_temp_20_n_90;
wire mul_temp_20_n_92;
wire mul_temp_20_n_93;
wire mul_temp_20_n_94;
wire mul_temp_20_n_95;
wire mul_temp_20_n_96;
wire mul_temp_20_n_97;
wire mul_temp_20_n_98;
wire mul_temp_20_n_99;
wire [14:14]\^mul_temp_21 ;
wire mul_temp_21_n_100;
wire mul_temp_21_n_101;
wire mul_temp_21_n_102;
wire mul_temp_21_n_103;
wire mul_temp_21_n_104;
wire mul_temp_21_n_105;
wire mul_temp_21_n_74;
wire mul_temp_21_n_75;
wire mul_temp_21_n_76;
wire mul_temp_21_n_77;
wire mul_temp_21_n_78;
wire mul_temp_21_n_79;
wire mul_temp_21_n_80;
wire mul_temp_21_n_81;
wire mul_temp_21_n_82;
wire mul_temp_21_n_83;
wire mul_temp_21_n_84;
wire mul_temp_21_n_85;
wire mul_temp_21_n_86;
wire mul_temp_21_n_87;
wire mul_temp_21_n_88;
wire mul_temp_21_n_89;
wire mul_temp_21_n_90;
wire mul_temp_21_n_92;
wire mul_temp_21_n_93;
wire mul_temp_21_n_94;
wire mul_temp_21_n_95;
wire mul_temp_21_n_96;
wire mul_temp_21_n_97;
wire mul_temp_21_n_98;
wire mul_temp_21_n_99;
wire [14:14]\^mul_temp_22 ;
wire mul_temp_22_n_100;
wire mul_temp_22_n_101;
wire mul_temp_22_n_102;
wire mul_temp_22_n_103;
wire mul_temp_22_n_104;
wire mul_temp_22_n_105;
wire mul_temp_22_n_74;
wire mul_temp_22_n_75;
wire mul_temp_22_n_76;
wire mul_temp_22_n_77;
wire mul_temp_22_n_78;
wire mul_temp_22_n_79;
wire mul_temp_22_n_80;
wire mul_temp_22_n_81;
wire mul_temp_22_n_82;
wire mul_temp_22_n_83;
wire mul_temp_22_n_84;
wire mul_temp_22_n_85;
wire mul_temp_22_n_86;
wire mul_temp_22_n_87;
wire mul_temp_22_n_88;
wire mul_temp_22_n_89;
wire mul_temp_22_n_90;
wire mul_temp_22_n_92;
wire mul_temp_22_n_93;
wire mul_temp_22_n_94;
wire mul_temp_22_n_95;
wire mul_temp_22_n_96;
wire mul_temp_22_n_97;
wire mul_temp_22_n_98;
wire mul_temp_22_n_99;
wire [14:14]\^mul_temp_23 ;
wire mul_temp_23_n_100;
wire mul_temp_23_n_101;
wire mul_temp_23_n_102;
wire mul_temp_23_n_103;
wire mul_temp_23_n_104;
wire mul_temp_23_n_105;
wire mul_temp_23_n_74;
wire mul_temp_23_n_75;
wire mul_temp_23_n_76;
wire mul_temp_23_n_77;
wire mul_temp_23_n_78;
wire mul_temp_23_n_79;
wire mul_temp_23_n_80;
wire mul_temp_23_n_81;
wire mul_temp_23_n_82;
wire mul_temp_23_n_83;
wire mul_temp_23_n_84;
wire mul_temp_23_n_85;
wire mul_temp_23_n_86;
wire mul_temp_23_n_87;
wire mul_temp_23_n_88;
wire mul_temp_23_n_89;
wire mul_temp_23_n_90;
wire mul_temp_23_n_92;
wire mul_temp_23_n_93;
wire mul_temp_23_n_94;
wire mul_temp_23_n_95;
wire mul_temp_23_n_96;
wire mul_temp_23_n_97;
wire mul_temp_23_n_98;
wire mul_temp_23_n_99;
wire [14:14]\^mul_temp_24 ;
wire mul_temp_24_n_100;
wire mul_temp_24_n_101;
wire mul_temp_24_n_102;
wire mul_temp_24_n_103;
wire mul_temp_24_n_104;
wire mul_temp_24_n_105;
wire mul_temp_24_n_74;
wire mul_temp_24_n_75;
wire mul_temp_24_n_76;
wire mul_temp_24_n_77;
wire mul_temp_24_n_78;
wire mul_temp_24_n_79;
wire mul_temp_24_n_80;
wire mul_temp_24_n_81;
wire mul_temp_24_n_82;
wire mul_temp_24_n_83;
wire mul_temp_24_n_84;
wire mul_temp_24_n_85;
wire mul_temp_24_n_86;
wire mul_temp_24_n_87;
wire mul_temp_24_n_88;
wire mul_temp_24_n_89;
wire mul_temp_24_n_90;
wire mul_temp_24_n_92;
wire mul_temp_24_n_93;
wire mul_temp_24_n_94;
wire mul_temp_24_n_95;
wire mul_temp_24_n_96;
wire mul_temp_24_n_97;
wire mul_temp_24_n_98;
wire mul_temp_24_n_99;
wire [14:14]\^mul_temp_25 ;
wire mul_temp_25_n_100;
wire mul_temp_25_n_101;
wire mul_temp_25_n_102;
wire mul_temp_25_n_103;
wire mul_temp_25_n_104;
wire mul_temp_25_n_105;
wire mul_temp_25_n_74;
wire mul_temp_25_n_75;
wire mul_temp_25_n_76;
wire mul_temp_25_n_77;
wire mul_temp_25_n_78;
wire mul_temp_25_n_79;
wire mul_temp_25_n_80;
wire mul_temp_25_n_81;
wire mul_temp_25_n_82;
wire mul_temp_25_n_83;
wire mul_temp_25_n_84;
wire mul_temp_25_n_85;
wire mul_temp_25_n_86;
wire mul_temp_25_n_87;
wire mul_temp_25_n_88;
wire mul_temp_25_n_89;
wire mul_temp_25_n_90;
wire mul_temp_25_n_92;
wire mul_temp_25_n_93;
wire mul_temp_25_n_94;
wire mul_temp_25_n_95;
wire mul_temp_25_n_96;
wire mul_temp_25_n_97;
wire mul_temp_25_n_98;
wire mul_temp_25_n_99;
wire [14:14]\^mul_temp_26 ;
wire mul_temp_26_n_100;
wire mul_temp_26_n_101;
wire mul_temp_26_n_102;
wire mul_temp_26_n_103;
wire mul_temp_26_n_104;
wire mul_temp_26_n_105;
wire mul_temp_26_n_74;
wire mul_temp_26_n_75;
wire mul_temp_26_n_76;
wire mul_temp_26_n_77;
wire mul_temp_26_n_78;
wire mul_temp_26_n_79;
wire mul_temp_26_n_80;
wire mul_temp_26_n_81;
wire mul_temp_26_n_82;
wire mul_temp_26_n_83;
wire mul_temp_26_n_84;
wire mul_temp_26_n_85;
wire mul_temp_26_n_86;
wire mul_temp_26_n_87;
wire mul_temp_26_n_88;
wire mul_temp_26_n_89;
wire mul_temp_26_n_90;
wire mul_temp_26_n_92;
wire mul_temp_26_n_93;
wire mul_temp_26_n_94;
wire mul_temp_26_n_95;
wire mul_temp_26_n_96;
wire mul_temp_26_n_97;
wire mul_temp_26_n_98;
wire mul_temp_26_n_99;
wire [14:14]\^mul_temp_27 ;
wire mul_temp_27_n_100;
wire mul_temp_27_n_101;
wire mul_temp_27_n_102;
wire mul_temp_27_n_103;
wire mul_temp_27_n_104;
wire mul_temp_27_n_105;
wire mul_temp_27_n_74;
wire mul_temp_27_n_75;
wire mul_temp_27_n_76;
wire mul_temp_27_n_77;
wire mul_temp_27_n_78;
wire mul_temp_27_n_79;
wire mul_temp_27_n_80;
wire mul_temp_27_n_81;
wire mul_temp_27_n_82;
wire mul_temp_27_n_83;
wire mul_temp_27_n_84;
wire mul_temp_27_n_85;
wire mul_temp_27_n_86;
wire mul_temp_27_n_87;
wire mul_temp_27_n_88;
wire mul_temp_27_n_89;
wire mul_temp_27_n_90;
wire mul_temp_27_n_92;
wire mul_temp_27_n_93;
wire mul_temp_27_n_94;
wire mul_temp_27_n_95;
wire mul_temp_27_n_96;
wire mul_temp_27_n_97;
wire mul_temp_27_n_98;
wire mul_temp_27_n_99;
wire [14:14]\^mul_temp_28 ;
wire mul_temp_28_n_100;
wire mul_temp_28_n_101;
wire mul_temp_28_n_102;
wire mul_temp_28_n_103;
wire mul_temp_28_n_104;
wire mul_temp_28_n_105;
wire mul_temp_28_n_74;
wire mul_temp_28_n_75;
wire mul_temp_28_n_76;
wire mul_temp_28_n_77;
wire mul_temp_28_n_78;
wire mul_temp_28_n_79;
wire mul_temp_28_n_80;
wire mul_temp_28_n_81;
wire mul_temp_28_n_82;
wire mul_temp_28_n_83;
wire mul_temp_28_n_84;
wire mul_temp_28_n_85;
wire mul_temp_28_n_86;
wire mul_temp_28_n_87;
wire mul_temp_28_n_88;
wire mul_temp_28_n_89;
wire mul_temp_28_n_90;
wire mul_temp_28_n_92;
wire mul_temp_28_n_93;
wire mul_temp_28_n_94;
wire mul_temp_28_n_95;
wire mul_temp_28_n_96;
wire mul_temp_28_n_97;
wire mul_temp_28_n_98;
wire mul_temp_28_n_99;
wire [14:14]\^mul_temp_29 ;
wire mul_temp_29_n_100;
wire mul_temp_29_n_101;
wire mul_temp_29_n_102;
wire mul_temp_29_n_103;
wire mul_temp_29_n_104;
wire mul_temp_29_n_105;
wire mul_temp_29_n_74;
wire mul_temp_29_n_75;
wire mul_temp_29_n_76;
wire mul_temp_29_n_77;
wire mul_temp_29_n_78;
wire mul_temp_29_n_79;
wire mul_temp_29_n_80;
wire mul_temp_29_n_81;
wire mul_temp_29_n_82;
wire mul_temp_29_n_83;
wire mul_temp_29_n_84;
wire mul_temp_29_n_85;
wire mul_temp_29_n_86;
wire mul_temp_29_n_87;
wire mul_temp_29_n_88;
wire mul_temp_29_n_89;
wire mul_temp_29_n_90;
wire mul_temp_29_n_92;
wire mul_temp_29_n_93;
wire mul_temp_29_n_94;
wire mul_temp_29_n_95;
wire mul_temp_29_n_96;
wire mul_temp_29_n_97;
wire mul_temp_29_n_98;
wire mul_temp_29_n_99;
wire mul_temp_2_n_100;
wire mul_temp_2_n_101;
wire mul_temp_2_n_102;
wire mul_temp_2_n_103;
wire mul_temp_2_n_104;
wire mul_temp_2_n_105;
wire mul_temp_2_n_74;
wire mul_temp_2_n_75;
wire mul_temp_2_n_76;
wire mul_temp_2_n_77;
wire mul_temp_2_n_78;
wire mul_temp_2_n_79;
wire mul_temp_2_n_80;
wire mul_temp_2_n_81;
wire mul_temp_2_n_82;
wire mul_temp_2_n_83;
wire mul_temp_2_n_84;
wire mul_temp_2_n_85;
wire mul_temp_2_n_86;
wire mul_temp_2_n_87;
wire mul_temp_2_n_88;
wire mul_temp_2_n_89;
wire mul_temp_2_n_90;
wire mul_temp_2_n_92;
wire mul_temp_2_n_93;
wire mul_temp_2_n_94;
wire mul_temp_2_n_95;
wire mul_temp_2_n_96;
wire mul_temp_2_n_97;
wire mul_temp_2_n_98;
wire mul_temp_2_n_99;
wire [14:14]\^mul_temp_3 ;
wire [14:14]\^mul_temp_30 ;
wire mul_temp_30_n_100;
wire mul_temp_30_n_101;
wire mul_temp_30_n_102;
wire mul_temp_30_n_103;
wire mul_temp_30_n_104;
wire mul_temp_30_n_105;
wire mul_temp_30_n_74;
wire mul_temp_30_n_75;
wire mul_temp_30_n_76;
wire mul_temp_30_n_77;
wire mul_temp_30_n_78;
wire mul_temp_30_n_79;
wire mul_temp_30_n_80;
wire mul_temp_30_n_81;
wire mul_temp_30_n_82;
wire mul_temp_30_n_83;
wire mul_temp_30_n_84;
wire mul_temp_30_n_85;
wire mul_temp_30_n_86;
wire mul_temp_30_n_87;
wire mul_temp_30_n_88;
wire mul_temp_30_n_89;
wire mul_temp_30_n_90;
wire mul_temp_30_n_92;
wire mul_temp_30_n_93;
wire mul_temp_30_n_94;
wire mul_temp_30_n_95;
wire mul_temp_30_n_96;
wire mul_temp_30_n_97;
wire mul_temp_30_n_98;
wire mul_temp_30_n_99;
wire [14:14]\^mul_temp_31 ;
wire mul_temp_31_n_100;
wire mul_temp_31_n_101;
wire mul_temp_31_n_102;
wire mul_temp_31_n_103;
wire mul_temp_31_n_104;
wire mul_temp_31_n_105;
wire mul_temp_31_n_74;
wire mul_temp_31_n_75;
wire mul_temp_31_n_76;
wire mul_temp_31_n_77;
wire mul_temp_31_n_78;
wire mul_temp_31_n_79;
wire mul_temp_31_n_80;
wire mul_temp_31_n_81;
wire mul_temp_31_n_82;
wire mul_temp_31_n_83;
wire mul_temp_31_n_84;
wire mul_temp_31_n_85;
wire mul_temp_31_n_86;
wire mul_temp_31_n_87;
wire mul_temp_31_n_88;
wire mul_temp_31_n_89;
wire mul_temp_31_n_90;
wire mul_temp_31_n_92;
wire mul_temp_31_n_93;
wire mul_temp_31_n_94;
wire mul_temp_31_n_95;
wire mul_temp_31_n_96;
wire mul_temp_31_n_97;
wire mul_temp_31_n_98;
wire mul_temp_31_n_99;
wire [14:14]\^mul_temp_32 ;
wire mul_temp_32_n_100;
wire mul_temp_32_n_101;
wire mul_temp_32_n_102;
wire mul_temp_32_n_103;
wire mul_temp_32_n_104;
wire mul_temp_32_n_105;
wire mul_temp_32_n_74;
wire mul_temp_32_n_75;
wire mul_temp_32_n_76;
wire mul_temp_32_n_77;
wire mul_temp_32_n_78;
wire mul_temp_32_n_79;
wire mul_temp_32_n_80;
wire mul_temp_32_n_81;
wire mul_temp_32_n_82;
wire mul_temp_32_n_83;
wire mul_temp_32_n_84;
wire mul_temp_32_n_85;
wire mul_temp_32_n_86;
wire mul_temp_32_n_87;
wire mul_temp_32_n_88;
wire mul_temp_32_n_89;
wire mul_temp_32_n_90;
wire mul_temp_32_n_92;
wire mul_temp_32_n_93;
wire mul_temp_32_n_94;
wire mul_temp_32_n_95;
wire mul_temp_32_n_96;
wire mul_temp_32_n_97;
wire mul_temp_32_n_98;
wire mul_temp_32_n_99;
wire mul_temp_3_n_100;
wire mul_temp_3_n_101;
wire mul_temp_3_n_102;
wire mul_temp_3_n_103;
wire mul_temp_3_n_104;
wire mul_temp_3_n_105;
wire mul_temp_3_n_74;
wire mul_temp_3_n_75;
wire mul_temp_3_n_76;
wire mul_temp_3_n_77;
wire mul_temp_3_n_78;
wire mul_temp_3_n_79;
wire mul_temp_3_n_80;
wire mul_temp_3_n_81;
wire mul_temp_3_n_82;
wire mul_temp_3_n_83;
wire mul_temp_3_n_84;
wire mul_temp_3_n_85;
wire mul_temp_3_n_86;
wire mul_temp_3_n_87;
wire mul_temp_3_n_88;
wire mul_temp_3_n_89;
wire mul_temp_3_n_90;
wire mul_temp_3_n_92;
wire mul_temp_3_n_93;
wire mul_temp_3_n_94;
wire mul_temp_3_n_95;
wire mul_temp_3_n_96;
wire mul_temp_3_n_97;
wire mul_temp_3_n_98;
wire mul_temp_3_n_99;
wire [14:14]\^mul_temp_4 ;
wire mul_temp_4_n_100;
wire mul_temp_4_n_101;
wire mul_temp_4_n_102;
wire mul_temp_4_n_103;
wire mul_temp_4_n_104;
wire mul_temp_4_n_105;
wire mul_temp_4_n_74;
wire mul_temp_4_n_75;
wire mul_temp_4_n_76;
wire mul_temp_4_n_77;
wire mul_temp_4_n_78;
wire mul_temp_4_n_79;
wire mul_temp_4_n_80;
wire mul_temp_4_n_81;
wire mul_temp_4_n_82;
wire mul_temp_4_n_83;
wire mul_temp_4_n_84;
wire mul_temp_4_n_85;
wire mul_temp_4_n_86;
wire mul_temp_4_n_87;
wire mul_temp_4_n_88;
wire mul_temp_4_n_89;
wire mul_temp_4_n_90;
wire mul_temp_4_n_92;
wire mul_temp_4_n_93;
wire mul_temp_4_n_94;
wire mul_temp_4_n_95;
wire mul_temp_4_n_96;
wire mul_temp_4_n_97;
wire mul_temp_4_n_98;
wire mul_temp_4_n_99;
wire [14:14]\^mul_temp_5 ;
wire mul_temp_5_n_100;
wire mul_temp_5_n_101;
wire mul_temp_5_n_102;
wire mul_temp_5_n_103;
wire mul_temp_5_n_104;
wire mul_temp_5_n_105;
wire mul_temp_5_n_74;
wire mul_temp_5_n_75;
wire mul_temp_5_n_76;
wire mul_temp_5_n_77;
wire mul_temp_5_n_78;
wire mul_temp_5_n_79;
wire mul_temp_5_n_80;
wire mul_temp_5_n_81;
wire mul_temp_5_n_82;
wire mul_temp_5_n_83;
wire mul_temp_5_n_84;
wire mul_temp_5_n_85;
wire mul_temp_5_n_86;
wire mul_temp_5_n_87;
wire mul_temp_5_n_88;
wire mul_temp_5_n_89;
wire mul_temp_5_n_90;
wire mul_temp_5_n_92;
wire mul_temp_5_n_93;
wire mul_temp_5_n_94;
wire mul_temp_5_n_95;
wire mul_temp_5_n_96;
wire mul_temp_5_n_97;
wire mul_temp_5_n_98;
wire mul_temp_5_n_99;
wire [14:14]\^mul_temp_6 ;
wire mul_temp_6_n_100;
wire mul_temp_6_n_101;
wire mul_temp_6_n_102;
wire mul_temp_6_n_103;
wire mul_temp_6_n_104;
wire mul_temp_6_n_105;
wire mul_temp_6_n_74;
wire mul_temp_6_n_75;
wire mul_temp_6_n_76;
wire mul_temp_6_n_77;
wire mul_temp_6_n_78;
wire mul_temp_6_n_79;
wire mul_temp_6_n_80;
wire mul_temp_6_n_81;
wire mul_temp_6_n_82;
wire mul_temp_6_n_83;
wire mul_temp_6_n_84;
wire mul_temp_6_n_85;
wire mul_temp_6_n_86;
wire mul_temp_6_n_87;
wire mul_temp_6_n_88;
wire mul_temp_6_n_89;
wire mul_temp_6_n_90;
wire mul_temp_6_n_92;
wire mul_temp_6_n_93;
wire mul_temp_6_n_94;
wire mul_temp_6_n_95;
wire mul_temp_6_n_96;
wire mul_temp_6_n_97;
wire mul_temp_6_n_98;
wire mul_temp_6_n_99;
wire [14:14]\^mul_temp_7 ;
wire mul_temp_7_n_100;
wire mul_temp_7_n_101;
wire mul_temp_7_n_102;
wire mul_temp_7_n_103;
wire mul_temp_7_n_104;
wire mul_temp_7_n_105;
wire mul_temp_7_n_74;
wire mul_temp_7_n_75;
wire mul_temp_7_n_76;
wire mul_temp_7_n_77;
wire mul_temp_7_n_78;
wire mul_temp_7_n_79;
wire mul_temp_7_n_80;
wire mul_temp_7_n_81;
wire mul_temp_7_n_82;
wire mul_temp_7_n_83;
wire mul_temp_7_n_84;
wire mul_temp_7_n_85;
wire mul_temp_7_n_86;
wire mul_temp_7_n_87;
wire mul_temp_7_n_88;
wire mul_temp_7_n_89;
wire mul_temp_7_n_90;
wire mul_temp_7_n_92;
wire mul_temp_7_n_93;
wire mul_temp_7_n_94;
wire mul_temp_7_n_95;
wire mul_temp_7_n_96;
wire mul_temp_7_n_97;
wire mul_temp_7_n_98;
wire mul_temp_7_n_99;
wire [14:14]\^mul_temp_8 ;
wire mul_temp_8_n_100;
wire mul_temp_8_n_101;
wire mul_temp_8_n_102;
wire mul_temp_8_n_103;
wire mul_temp_8_n_104;
wire mul_temp_8_n_105;
wire mul_temp_8_n_74;
wire mul_temp_8_n_75;
wire mul_temp_8_n_76;
wire mul_temp_8_n_77;
wire mul_temp_8_n_78;
wire mul_temp_8_n_79;
wire mul_temp_8_n_80;
wire mul_temp_8_n_81;
wire mul_temp_8_n_82;
wire mul_temp_8_n_83;
wire mul_temp_8_n_84;
wire mul_temp_8_n_85;
wire mul_temp_8_n_86;
wire mul_temp_8_n_87;
wire mul_temp_8_n_88;
wire mul_temp_8_n_89;
wire mul_temp_8_n_90;
wire mul_temp_8_n_92;
wire mul_temp_8_n_93;
wire mul_temp_8_n_94;
wire mul_temp_8_n_95;
wire mul_temp_8_n_96;
wire mul_temp_8_n_97;
wire mul_temp_8_n_98;
wire mul_temp_8_n_99;
wire [14:14]\^mul_temp_9 ;
wire mul_temp_9_n_100;
wire mul_temp_9_n_101;
wire mul_temp_9_n_102;
wire mul_temp_9_n_103;
wire mul_temp_9_n_104;
wire mul_temp_9_n_105;
wire mul_temp_9_n_74;
wire mul_temp_9_n_75;
wire mul_temp_9_n_76;
wire mul_temp_9_n_77;
wire mul_temp_9_n_78;
wire mul_temp_9_n_79;
wire mul_temp_9_n_80;
wire mul_temp_9_n_81;
wire mul_temp_9_n_82;
wire mul_temp_9_n_83;
wire mul_temp_9_n_84;
wire mul_temp_9_n_85;
wire mul_temp_9_n_86;
wire mul_temp_9_n_87;
wire mul_temp_9_n_88;
wire mul_temp_9_n_89;
wire mul_temp_9_n_90;
wire mul_temp_9_n_92;
wire mul_temp_9_n_93;
wire mul_temp_9_n_94;
wire mul_temp_9_n_95;
wire mul_temp_9_n_96;
wire mul_temp_9_n_97;
wire mul_temp_9_n_98;
wire mul_temp_9_n_99;
wire mul_temp_n_100;
wire mul_temp_n_101;
wire mul_temp_n_102;
wire mul_temp_n_103;
wire mul_temp_n_104;
wire mul_temp_n_105;
wire mul_temp_n_74;
wire mul_temp_n_75;
wire mul_temp_n_76;
wire mul_temp_n_77;
wire mul_temp_n_78;
wire mul_temp_n_79;
wire mul_temp_n_80;
wire mul_temp_n_81;
wire mul_temp_n_82;
wire mul_temp_n_83;
wire mul_temp_n_84;
wire mul_temp_n_85;
wire mul_temp_n_86;
wire mul_temp_n_87;
wire mul_temp_n_88;
wire mul_temp_n_89;
wire mul_temp_n_90;
wire mul_temp_n_92;
wire mul_temp_n_93;
wire mul_temp_n_94;
wire mul_temp_n_95;
wire mul_temp_n_96;
wire mul_temp_n_97;
wire mul_temp_n_98;
wire mul_temp_n_99;
wire sub_temp_carry__0_n_0;
wire sub_temp_carry__0_n_1;
wire sub_temp_carry__0_n_2;
wire sub_temp_carry__0_n_3;
wire sub_temp_carry__1_n_0;
wire sub_temp_carry__1_n_1;
wire sub_temp_carry__1_n_2;
wire sub_temp_carry__1_n_3;
wire sub_temp_carry__2_n_1;
wire sub_temp_carry__2_n_2;
wire sub_temp_carry__2_n_3;
wire sub_temp_carry_n_0;
wire sub_temp_carry_n_1;
wire sub_temp_carry_n_2;
wire sub_temp_carry_n_3;
wire \weight[0][0]_i_2_n_0 ;
wire \weight[0][0]_i_3_n_0 ;
wire \weight[0][0]_i_4_n_0 ;
wire \weight[0][0]_i_5_n_0 ;
wire \weight[0][12]_i_2_n_0 ;
wire \weight[0][12]_i_3_n_0 ;
wire \weight[0][12]_i_4_n_0 ;
wire \weight[0][12]_i_5_n_0 ;
wire \weight[0][4]_i_2_n_0 ;
wire \weight[0][4]_i_3_n_0 ;
wire \weight[0][4]_i_4_n_0 ;
wire \weight[0][4]_i_5_n_0 ;
wire \weight[0][8]_i_2_n_0 ;
wire \weight[0][8]_i_3_n_0 ;
wire \weight[0][8]_i_4_n_0 ;
wire \weight[0][8]_i_5_n_0 ;
wire \weight[10][0]_i_2_n_0 ;
wire \weight[10][0]_i_3_n_0 ;
wire \weight[10][0]_i_4_n_0 ;
wire \weight[10][0]_i_5_n_0 ;
wire \weight[10][12]_i_2_n_0 ;
wire \weight[10][12]_i_3_n_0 ;
wire \weight[10][12]_i_4_n_0 ;
wire \weight[10][12]_i_5_n_0 ;
wire \weight[10][4]_i_2_n_0 ;
wire \weight[10][4]_i_3_n_0 ;
wire \weight[10][4]_i_4_n_0 ;
wire \weight[10][4]_i_5_n_0 ;
wire \weight[10][8]_i_2_n_0 ;
wire \weight[10][8]_i_3_n_0 ;
wire \weight[10][8]_i_4_n_0 ;
wire \weight[10][8]_i_5_n_0 ;
wire \weight[11][0]_i_2_n_0 ;
wire \weight[11][0]_i_3_n_0 ;
wire \weight[11][0]_i_4_n_0 ;
wire \weight[11][0]_i_5_n_0 ;
wire \weight[11][12]_i_2_n_0 ;
wire \weight[11][12]_i_3_n_0 ;
wire \weight[11][12]_i_4_n_0 ;
wire \weight[11][12]_i_5_n_0 ;
wire \weight[11][4]_i_2_n_0 ;
wire \weight[11][4]_i_3_n_0 ;
wire \weight[11][4]_i_4_n_0 ;
wire \weight[11][4]_i_5_n_0 ;
wire \weight[11][8]_i_2_n_0 ;
wire \weight[11][8]_i_3_n_0 ;
wire \weight[11][8]_i_4_n_0 ;
wire \weight[11][8]_i_5_n_0 ;
wire \weight[12][0]_i_2_n_0 ;
wire \weight[12][0]_i_3_n_0 ;
wire \weight[12][0]_i_4_n_0 ;
wire \weight[12][0]_i_5_n_0 ;
wire \weight[12][12]_i_2_n_0 ;
wire \weight[12][12]_i_3_n_0 ;
wire \weight[12][12]_i_4_n_0 ;
wire \weight[12][12]_i_5_n_0 ;
wire \weight[12][4]_i_2_n_0 ;
wire \weight[12][4]_i_3_n_0 ;
wire \weight[12][4]_i_4_n_0 ;
wire \weight[12][4]_i_5_n_0 ;
wire \weight[12][8]_i_2_n_0 ;
wire \weight[12][8]_i_3_n_0 ;
wire \weight[12][8]_i_4_n_0 ;
wire \weight[12][8]_i_5_n_0 ;
wire \weight[13][0]_i_2_n_0 ;
wire \weight[13][0]_i_3_n_0 ;
wire \weight[13][0]_i_4_n_0 ;
wire \weight[13][0]_i_5_n_0 ;
wire \weight[13][12]_i_2_n_0 ;
wire \weight[13][12]_i_3_n_0 ;
wire \weight[13][12]_i_4_n_0 ;
wire \weight[13][12]_i_5_n_0 ;
wire \weight[13][4]_i_2_n_0 ;
wire \weight[13][4]_i_3_n_0 ;
wire \weight[13][4]_i_4_n_0 ;
wire \weight[13][4]_i_5_n_0 ;
wire \weight[13][8]_i_2_n_0 ;
wire \weight[13][8]_i_3_n_0 ;
wire \weight[13][8]_i_4_n_0 ;
wire \weight[13][8]_i_5_n_0 ;
wire \weight[14][0]_i_2_n_0 ;
wire \weight[14][0]_i_3_n_0 ;
wire \weight[14][0]_i_4_n_0 ;
wire \weight[14][0]_i_5_n_0 ;
wire \weight[14][12]_i_2_n_0 ;
wire \weight[14][12]_i_3_n_0 ;
wire \weight[14][12]_i_4_n_0 ;
wire \weight[14][12]_i_5_n_0 ;
wire \weight[14][4]_i_2_n_0 ;
wire \weight[14][4]_i_3_n_0 ;
wire \weight[14][4]_i_4_n_0 ;
wire \weight[14][4]_i_5_n_0 ;
wire \weight[14][8]_i_2_n_0 ;
wire \weight[14][8]_i_3_n_0 ;
wire \weight[14][8]_i_4_n_0 ;
wire \weight[14][8]_i_5_n_0 ;
wire \weight[15][0]_i_2_n_0 ;
wire \weight[15][0]_i_3_n_0 ;
wire \weight[15][0]_i_4_n_0 ;
wire \weight[15][0]_i_5_n_0 ;
wire \weight[15][12]_i_2_n_0 ;
wire \weight[15][12]_i_3_n_0 ;
wire \weight[15][12]_i_4_n_0 ;
wire \weight[15][12]_i_5_n_0 ;
wire \weight[15][4]_i_2_n_0 ;
wire \weight[15][4]_i_3_n_0 ;
wire \weight[15][4]_i_4_n_0 ;
wire \weight[15][4]_i_5_n_0 ;
wire \weight[15][8]_i_2_n_0 ;
wire \weight[15][8]_i_3_n_0 ;
wire \weight[15][8]_i_4_n_0 ;
wire \weight[15][8]_i_5_n_0 ;
wire \weight[1][0]_i_2_n_0 ;
wire \weight[1][0]_i_3_n_0 ;
wire \weight[1][0]_i_4_n_0 ;
wire \weight[1][0]_i_5_n_0 ;
wire \weight[1][12]_i_2_n_0 ;
wire \weight[1][12]_i_3_n_0 ;
wire \weight[1][12]_i_4_n_0 ;
wire \weight[1][12]_i_5_n_0 ;
wire \weight[1][4]_i_2_n_0 ;
wire \weight[1][4]_i_3_n_0 ;
wire \weight[1][4]_i_4_n_0 ;
wire \weight[1][4]_i_5_n_0 ;
wire \weight[1][8]_i_2_n_0 ;
wire \weight[1][8]_i_3_n_0 ;
wire \weight[1][8]_i_4_n_0 ;
wire \weight[1][8]_i_5_n_0 ;
wire \weight[2][0]_i_2_n_0 ;
wire \weight[2][0]_i_3_n_0 ;
wire \weight[2][0]_i_4_n_0 ;
wire \weight[2][0]_i_5_n_0 ;
wire \weight[2][12]_i_2_n_0 ;
wire \weight[2][12]_i_3_n_0 ;
wire \weight[2][12]_i_4_n_0 ;
wire \weight[2][12]_i_5_n_0 ;
wire \weight[2][4]_i_2_n_0 ;
wire \weight[2][4]_i_3_n_0 ;
wire \weight[2][4]_i_4_n_0 ;
wire \weight[2][4]_i_5_n_0 ;
wire \weight[2][8]_i_2_n_0 ;
wire \weight[2][8]_i_3_n_0 ;
wire \weight[2][8]_i_4_n_0 ;
wire \weight[2][8]_i_5_n_0 ;
wire \weight[3][0]_i_2_n_0 ;
wire \weight[3][0]_i_3_n_0 ;
wire \weight[3][0]_i_4_n_0 ;
wire \weight[3][0]_i_5_n_0 ;
wire \weight[3][12]_i_2_n_0 ;
wire \weight[3][12]_i_3_n_0 ;
wire \weight[3][12]_i_4_n_0 ;
wire \weight[3][12]_i_5_n_0 ;
wire \weight[3][4]_i_2_n_0 ;
wire \weight[3][4]_i_3_n_0 ;
wire \weight[3][4]_i_4_n_0 ;
wire \weight[3][4]_i_5_n_0 ;
wire \weight[3][8]_i_2_n_0 ;
wire \weight[3][8]_i_3_n_0 ;
wire \weight[3][8]_i_4_n_0 ;
wire \weight[3][8]_i_5_n_0 ;
wire \weight[4][0]_i_2_n_0 ;
wire \weight[4][0]_i_3_n_0 ;
wire \weight[4][0]_i_4_n_0 ;
wire \weight[4][0]_i_5_n_0 ;
wire \weight[4][12]_i_2_n_0 ;
wire \weight[4][12]_i_3_n_0 ;
wire \weight[4][12]_i_4_n_0 ;
wire \weight[4][12]_i_5_n_0 ;
wire \weight[4][4]_i_2_n_0 ;
wire \weight[4][4]_i_3_n_0 ;
wire \weight[4][4]_i_4_n_0 ;
wire \weight[4][4]_i_5_n_0 ;
wire \weight[4][8]_i_2_n_0 ;
wire \weight[4][8]_i_3_n_0 ;
wire \weight[4][8]_i_4_n_0 ;
wire \weight[4][8]_i_5_n_0 ;
wire \weight[5][0]_i_2_n_0 ;
wire \weight[5][0]_i_3_n_0 ;
wire \weight[5][0]_i_4_n_0 ;
wire \weight[5][0]_i_5_n_0 ;
wire \weight[5][12]_i_2_n_0 ;
wire \weight[5][12]_i_3_n_0 ;
wire \weight[5][12]_i_4_n_0 ;
wire \weight[5][12]_i_5_n_0 ;
wire \weight[5][4]_i_2_n_0 ;
wire \weight[5][4]_i_3_n_0 ;
wire \weight[5][4]_i_4_n_0 ;
wire \weight[5][4]_i_5_n_0 ;
wire \weight[5][8]_i_2_n_0 ;
wire \weight[5][8]_i_3_n_0 ;
wire \weight[5][8]_i_4_n_0 ;
wire \weight[5][8]_i_5_n_0 ;
wire \weight[6][0]_i_2_n_0 ;
wire \weight[6][0]_i_3_n_0 ;
wire \weight[6][0]_i_4_n_0 ;
wire \weight[6][0]_i_5_n_0 ;
wire \weight[6][12]_i_2_n_0 ;
wire \weight[6][12]_i_3_n_0 ;
wire \weight[6][12]_i_4_n_0 ;
wire \weight[6][12]_i_5_n_0 ;
wire \weight[6][4]_i_2_n_0 ;
wire \weight[6][4]_i_3_n_0 ;
wire \weight[6][4]_i_4_n_0 ;
wire \weight[6][4]_i_5_n_0 ;
wire \weight[6][8]_i_2_n_0 ;
wire \weight[6][8]_i_3_n_0 ;
wire \weight[6][8]_i_4_n_0 ;
wire \weight[6][8]_i_5_n_0 ;
wire \weight[7][0]_i_2_n_0 ;
wire \weight[7][0]_i_3_n_0 ;
wire \weight[7][0]_i_4_n_0 ;
wire \weight[7][0]_i_5_n_0 ;
wire \weight[7][12]_i_2_n_0 ;
wire \weight[7][12]_i_3_n_0 ;
wire \weight[7][12]_i_4_n_0 ;
wire \weight[7][12]_i_5_n_0 ;
wire \weight[7][4]_i_2_n_0 ;
wire \weight[7][4]_i_3_n_0 ;
wire \weight[7][4]_i_4_n_0 ;
wire \weight[7][4]_i_5_n_0 ;
wire \weight[7][8]_i_2_n_0 ;
wire \weight[7][8]_i_3_n_0 ;
wire \weight[7][8]_i_4_n_0 ;
wire \weight[7][8]_i_5_n_0 ;
wire \weight[8][0]_i_2_n_0 ;
wire \weight[8][0]_i_3_n_0 ;
wire \weight[8][0]_i_4_n_0 ;
wire \weight[8][0]_i_5_n_0 ;
wire \weight[8][12]_i_2_n_0 ;
wire \weight[8][12]_i_3_n_0 ;
wire \weight[8][12]_i_4_n_0 ;
wire \weight[8][12]_i_5_n_0 ;
wire \weight[8][4]_i_2_n_0 ;
wire \weight[8][4]_i_3_n_0 ;
wire \weight[8][4]_i_4_n_0 ;
wire \weight[8][4]_i_5_n_0 ;
wire \weight[8][8]_i_2_n_0 ;
wire \weight[8][8]_i_3_n_0 ;
wire \weight[8][8]_i_4_n_0 ;
wire \weight[8][8]_i_5_n_0 ;
wire \weight[9][0]_i_2_n_0 ;
wire \weight[9][0]_i_3_n_0 ;
wire \weight[9][0]_i_4_n_0 ;
wire \weight[9][0]_i_5_n_0 ;
wire \weight[9][12]_i_2_n_0 ;
wire \weight[9][12]_i_3_n_0 ;
wire \weight[9][12]_i_4_n_0 ;
wire \weight[9][12]_i_5_n_0 ;
wire \weight[9][4]_i_2_n_0 ;
wire \weight[9][4]_i_3_n_0 ;
wire \weight[9][4]_i_4_n_0 ;
wire \weight[9][4]_i_5_n_0 ;
wire \weight[9][8]_i_2_n_0 ;
wire \weight[9][8]_i_3_n_0 ;
wire \weight[9][8]_i_4_n_0 ;
wire \weight[9][8]_i_5_n_0 ;
wire \weight_reg[0][0]_i_1_n_0 ;
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wire \weight_reg[0][0]_i_1_n_4 ;
wire \weight_reg[0][0]_i_1_n_5 ;
wire \weight_reg[0][0]_i_1_n_6 ;
wire \weight_reg[0][0]_i_1_n_7 ;
wire \weight_reg[0][12]_i_1_n_1 ;
wire \weight_reg[0][12]_i_1_n_2 ;
wire \weight_reg[0][12]_i_1_n_3 ;
wire \weight_reg[0][12]_i_1_n_4 ;
wire \weight_reg[0][12]_i_1_n_5 ;
wire \weight_reg[0][12]_i_1_n_6 ;
wire \weight_reg[0][12]_i_1_n_7 ;
wire \weight_reg[0][4]_i_1_n_0 ;
wire \weight_reg[0][4]_i_1_n_1 ;
wire \weight_reg[0][4]_i_1_n_2 ;
wire \weight_reg[0][4]_i_1_n_3 ;
wire \weight_reg[0][4]_i_1_n_4 ;
wire \weight_reg[0][4]_i_1_n_5 ;
wire \weight_reg[0][4]_i_1_n_6 ;
wire \weight_reg[0][4]_i_1_n_7 ;
wire \weight_reg[0][8]_i_1_n_0 ;
wire \weight_reg[0][8]_i_1_n_1 ;
wire \weight_reg[0][8]_i_1_n_2 ;
wire \weight_reg[0][8]_i_1_n_3 ;
wire \weight_reg[0][8]_i_1_n_4 ;
wire \weight_reg[0][8]_i_1_n_5 ;
wire \weight_reg[0][8]_i_1_n_6 ;
wire \weight_reg[0][8]_i_1_n_7 ;
wire [15:0]\weight_reg[0]_15 ;
wire \weight_reg[10][0]_i_1_n_0 ;
wire \weight_reg[10][0]_i_1_n_1 ;
wire \weight_reg[10][0]_i_1_n_2 ;
wire \weight_reg[10][0]_i_1_n_3 ;
wire \weight_reg[10][0]_i_1_n_4 ;
wire \weight_reg[10][0]_i_1_n_5 ;
wire \weight_reg[10][0]_i_1_n_6 ;
wire \weight_reg[10][0]_i_1_n_7 ;
wire \weight_reg[10][12]_i_1_n_1 ;
wire \weight_reg[10][12]_i_1_n_2 ;
wire \weight_reg[10][12]_i_1_n_3 ;
wire \weight_reg[10][12]_i_1_n_4 ;
wire \weight_reg[10][12]_i_1_n_5 ;
wire \weight_reg[10][12]_i_1_n_6 ;
wire \weight_reg[10][12]_i_1_n_7 ;
wire \weight_reg[10][4]_i_1_n_0 ;
wire \weight_reg[10][4]_i_1_n_1 ;
wire \weight_reg[10][4]_i_1_n_2 ;
wire \weight_reg[10][4]_i_1_n_3 ;
wire \weight_reg[10][4]_i_1_n_4 ;
wire \weight_reg[10][4]_i_1_n_5 ;
wire \weight_reg[10][4]_i_1_n_6 ;
wire \weight_reg[10][4]_i_1_n_7 ;
wire \weight_reg[10][8]_i_1_n_0 ;
wire \weight_reg[10][8]_i_1_n_1 ;
wire \weight_reg[10][8]_i_1_n_2 ;
wire \weight_reg[10][8]_i_1_n_3 ;
wire \weight_reg[10][8]_i_1_n_4 ;
wire \weight_reg[10][8]_i_1_n_5 ;
wire \weight_reg[10][8]_i_1_n_6 ;
wire \weight_reg[10][8]_i_1_n_7 ;
wire [15:0]\weight_reg[10]_9 ;
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wire \weight_reg[11][0]_i_1_n_2 ;
wire \weight_reg[11][0]_i_1_n_3 ;
wire \weight_reg[11][0]_i_1_n_4 ;
wire \weight_reg[11][0]_i_1_n_5 ;
wire \weight_reg[11][0]_i_1_n_6 ;
wire \weight_reg[11][0]_i_1_n_7 ;
wire \weight_reg[11][12]_i_1_n_1 ;
wire \weight_reg[11][12]_i_1_n_2 ;
wire \weight_reg[11][12]_i_1_n_3 ;
wire \weight_reg[11][12]_i_1_n_4 ;
wire \weight_reg[11][12]_i_1_n_5 ;
wire \weight_reg[11][12]_i_1_n_6 ;
wire \weight_reg[11][12]_i_1_n_7 ;
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wire \weight_reg[11][4]_i_1_n_1 ;
wire \weight_reg[11][4]_i_1_n_2 ;
wire \weight_reg[11][4]_i_1_n_3 ;
wire \weight_reg[11][4]_i_1_n_4 ;
wire \weight_reg[11][4]_i_1_n_5 ;
wire \weight_reg[11][4]_i_1_n_6 ;
wire \weight_reg[11][4]_i_1_n_7 ;
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wire \weight_reg[11][8]_i_1_n_1 ;
wire \weight_reg[11][8]_i_1_n_2 ;
wire \weight_reg[11][8]_i_1_n_3 ;
wire \weight_reg[11][8]_i_1_n_4 ;
wire \weight_reg[11][8]_i_1_n_5 ;
wire \weight_reg[11][8]_i_1_n_6 ;
wire \weight_reg[11][8]_i_1_n_7 ;
wire [15:0]\weight_reg[11]_10 ;
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wire \weight_reg[12][0]_i_1_n_2 ;
wire \weight_reg[12][0]_i_1_n_3 ;
wire \weight_reg[12][0]_i_1_n_4 ;
wire \weight_reg[12][0]_i_1_n_5 ;
wire \weight_reg[12][0]_i_1_n_6 ;
wire \weight_reg[12][0]_i_1_n_7 ;
wire \weight_reg[12][12]_i_1_n_1 ;
wire \weight_reg[12][12]_i_1_n_2 ;
wire \weight_reg[12][12]_i_1_n_3 ;
wire \weight_reg[12][12]_i_1_n_4 ;
wire \weight_reg[12][12]_i_1_n_5 ;
wire \weight_reg[12][12]_i_1_n_6 ;
wire \weight_reg[12][12]_i_1_n_7 ;
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wire \weight_reg[12][4]_i_1_n_1 ;
wire \weight_reg[12][4]_i_1_n_2 ;
wire \weight_reg[12][4]_i_1_n_3 ;
wire \weight_reg[12][4]_i_1_n_4 ;
wire \weight_reg[12][4]_i_1_n_5 ;
wire \weight_reg[12][4]_i_1_n_6 ;
wire \weight_reg[12][4]_i_1_n_7 ;
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wire \weight_reg[12][8]_i_1_n_1 ;
wire \weight_reg[12][8]_i_1_n_2 ;
wire \weight_reg[12][8]_i_1_n_3 ;
wire \weight_reg[12][8]_i_1_n_4 ;
wire \weight_reg[12][8]_i_1_n_5 ;
wire \weight_reg[12][8]_i_1_n_6 ;
wire \weight_reg[12][8]_i_1_n_7 ;
wire [15:0]\weight_reg[12]_11 ;
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wire \weight_reg[13][0]_i_1_n_2 ;
wire \weight_reg[13][0]_i_1_n_3 ;
wire \weight_reg[13][0]_i_1_n_4 ;
wire \weight_reg[13][0]_i_1_n_5 ;
wire \weight_reg[13][0]_i_1_n_6 ;
wire \weight_reg[13][0]_i_1_n_7 ;
wire \weight_reg[13][12]_i_1_n_1 ;
wire \weight_reg[13][12]_i_1_n_2 ;
wire \weight_reg[13][12]_i_1_n_3 ;
wire \weight_reg[13][12]_i_1_n_4 ;
wire \weight_reg[13][12]_i_1_n_5 ;
wire \weight_reg[13][12]_i_1_n_6 ;
wire \weight_reg[13][12]_i_1_n_7 ;
wire \weight_reg[13][4]_i_1_n_0 ;
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wire \weight_reg[13][4]_i_1_n_2 ;
wire \weight_reg[13][4]_i_1_n_3 ;
wire \weight_reg[13][4]_i_1_n_4 ;
wire \weight_reg[13][4]_i_1_n_5 ;
wire \weight_reg[13][4]_i_1_n_6 ;
wire \weight_reg[13][4]_i_1_n_7 ;
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wire \weight_reg[13][8]_i_1_n_1 ;
wire \weight_reg[13][8]_i_1_n_2 ;
wire \weight_reg[13][8]_i_1_n_3 ;
wire \weight_reg[13][8]_i_1_n_4 ;
wire \weight_reg[13][8]_i_1_n_5 ;
wire \weight_reg[13][8]_i_1_n_6 ;
wire \weight_reg[13][8]_i_1_n_7 ;
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wire \weight_reg[14][0]_i_1_n_2 ;
wire \weight_reg[14][0]_i_1_n_3 ;
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wire \weight_reg[14][0]_i_1_n_5 ;
wire \weight_reg[14][0]_i_1_n_6 ;
wire \weight_reg[14][0]_i_1_n_7 ;
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wire \weight_reg[14][12]_i_1_n_2 ;
wire \weight_reg[14][12]_i_1_n_3 ;
wire \weight_reg[14][12]_i_1_n_4 ;
wire \weight_reg[14][12]_i_1_n_5 ;
wire \weight_reg[14][12]_i_1_n_6 ;
wire \weight_reg[14][12]_i_1_n_7 ;
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wire \weight_reg[14][4]_i_1_n_2 ;
wire \weight_reg[14][4]_i_1_n_3 ;
wire \weight_reg[14][4]_i_1_n_4 ;
wire \weight_reg[14][4]_i_1_n_5 ;
wire \weight_reg[14][4]_i_1_n_6 ;
wire \weight_reg[14][4]_i_1_n_7 ;
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wire \weight_reg[14][8]_i_1_n_2 ;
wire \weight_reg[14][8]_i_1_n_3 ;
wire \weight_reg[14][8]_i_1_n_4 ;
wire \weight_reg[14][8]_i_1_n_5 ;
wire \weight_reg[14][8]_i_1_n_6 ;
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wire [15:0]\weight_reg[14]_13 ;
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wire \weight_reg[15][0]_i_1_n_3 ;
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wire \weight_reg[15][0]_i_1_n_5 ;
wire \weight_reg[15][0]_i_1_n_6 ;
wire \weight_reg[15][0]_i_1_n_7 ;
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wire \weight_reg[15][12]_i_1_n_2 ;
wire \weight_reg[15][12]_i_1_n_3 ;
wire \weight_reg[15][12]_i_1_n_4 ;
wire \weight_reg[15][12]_i_1_n_5 ;
wire \weight_reg[15][12]_i_1_n_6 ;
wire \weight_reg[15][12]_i_1_n_7 ;
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wire \weight_reg[15][4]_i_1_n_2 ;
wire \weight_reg[15][4]_i_1_n_3 ;
wire \weight_reg[15][4]_i_1_n_4 ;
wire \weight_reg[15][4]_i_1_n_5 ;
wire \weight_reg[15][4]_i_1_n_6 ;
wire \weight_reg[15][4]_i_1_n_7 ;
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wire \weight_reg[15][8]_i_1_n_2 ;
wire \weight_reg[15][8]_i_1_n_3 ;
wire \weight_reg[15][8]_i_1_n_4 ;
wire \weight_reg[15][8]_i_1_n_5 ;
wire \weight_reg[15][8]_i_1_n_6 ;
wire \weight_reg[15][8]_i_1_n_7 ;
wire [15:0]\weight_reg[15]_14 ;
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wire \weight_reg[1][12]_i_1_n_3 ;
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wire \weight_reg[1][12]_i_1_n_5 ;
wire \weight_reg[1][12]_i_1_n_6 ;
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wire \weight_reg[1][4]_i_1_n_3 ;
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wire \weight_reg[1][8]_i_1_n_2 ;
wire \weight_reg[1][8]_i_1_n_3 ;
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wire \weight_reg[2][12]_i_1_n_5 ;
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wire \weight_reg[2][12]_i_1_n_7 ;
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wire \weight_reg[2][4]_i_1_n_3 ;
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wire \weight_reg[2][8]_i_1_n_3 ;
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wire \weight_reg[2][8]_i_1_n_5 ;
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wire \weight_reg[2][8]_i_1_n_7 ;
wire [15:0]\weight_reg[2]_1 ;
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wire \weight_reg[3][12]_i_1_n_4 ;
wire \weight_reg[3][12]_i_1_n_5 ;
wire \weight_reg[3][12]_i_1_n_6 ;
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wire \weight_reg[3][4]_i_1_n_2 ;
wire \weight_reg[3][4]_i_1_n_3 ;
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wire \weight_reg[3][4]_i_1_n_6 ;
wire \weight_reg[3][4]_i_1_n_7 ;
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wire \weight_reg[3][8]_i_1_n_2 ;
wire \weight_reg[3][8]_i_1_n_3 ;
wire \weight_reg[3][8]_i_1_n_4 ;
wire \weight_reg[3][8]_i_1_n_5 ;
wire \weight_reg[3][8]_i_1_n_6 ;
wire \weight_reg[3][8]_i_1_n_7 ;
wire [15:0]\weight_reg[3]_2 ;
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wire \weight_reg[4][0]_i_1_n_3 ;
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wire \weight_reg[4][0]_i_1_n_5 ;
wire \weight_reg[4][0]_i_1_n_6 ;
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wire \weight_reg[4][12]_i_1_n_3 ;
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wire \weight_reg[4][12]_i_1_n_5 ;
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wire \weight_reg[4][12]_i_1_n_7 ;
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wire \weight_reg[4][4]_i_1_n_2 ;
wire \weight_reg[4][4]_i_1_n_3 ;
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wire \weight_reg[4][4]_i_1_n_5 ;
wire \weight_reg[4][4]_i_1_n_6 ;
wire \weight_reg[4][4]_i_1_n_7 ;
wire \weight_reg[4][8]_i_1_n_0 ;
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wire \weight_reg[4][8]_i_1_n_3 ;
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wire \weight_reg[4][8]_i_1_n_5 ;
wire \weight_reg[4][8]_i_1_n_6 ;
wire \weight_reg[4][8]_i_1_n_7 ;
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wire \weight_reg[5][12]_i_1_n_3 ;
wire \weight_reg[5][12]_i_1_n_4 ;
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wire \weight_reg[5][12]_i_1_n_6 ;
wire \weight_reg[5][12]_i_1_n_7 ;
wire \weight_reg[5][4]_i_1_n_0 ;
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wire \weight_reg[5][4]_i_1_n_2 ;
wire \weight_reg[5][4]_i_1_n_3 ;
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wire \weight_reg[5][4]_i_1_n_6 ;
wire \weight_reg[5][4]_i_1_n_7 ;
wire \weight_reg[5][8]_i_1_n_0 ;
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wire \weight_reg[5][8]_i_1_n_2 ;
wire \weight_reg[5][8]_i_1_n_3 ;
wire \weight_reg[5][8]_i_1_n_4 ;
wire \weight_reg[5][8]_i_1_n_5 ;
wire \weight_reg[5][8]_i_1_n_6 ;
wire \weight_reg[5][8]_i_1_n_7 ;
wire [15:0]\weight_reg[5]_4 ;
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wire \weight_reg[6][0]_i_1_n_3 ;
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wire \weight_reg[6][0]_i_1_n_5 ;
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wire \weight_reg[6][0]_i_1_n_7 ;
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wire \weight_reg[6][12]_i_1_n_2 ;
wire \weight_reg[6][12]_i_1_n_3 ;
wire \weight_reg[6][12]_i_1_n_4 ;
wire \weight_reg[6][12]_i_1_n_5 ;
wire \weight_reg[6][12]_i_1_n_6 ;
wire \weight_reg[6][12]_i_1_n_7 ;
wire \weight_reg[6][4]_i_1_n_0 ;
wire \weight_reg[6][4]_i_1_n_1 ;
wire \weight_reg[6][4]_i_1_n_2 ;
wire \weight_reg[6][4]_i_1_n_3 ;
wire \weight_reg[6][4]_i_1_n_4 ;
wire \weight_reg[6][4]_i_1_n_5 ;
wire \weight_reg[6][4]_i_1_n_6 ;
wire \weight_reg[6][4]_i_1_n_7 ;
wire \weight_reg[6][8]_i_1_n_0 ;
wire \weight_reg[6][8]_i_1_n_1 ;
wire \weight_reg[6][8]_i_1_n_2 ;
wire \weight_reg[6][8]_i_1_n_3 ;
wire \weight_reg[6][8]_i_1_n_4 ;
wire \weight_reg[6][8]_i_1_n_5 ;
wire \weight_reg[6][8]_i_1_n_6 ;
wire \weight_reg[6][8]_i_1_n_7 ;
wire [15:0]\weight_reg[6]_5 ;
wire \weight_reg[7][0]_i_1_n_0 ;
wire \weight_reg[7][0]_i_1_n_1 ;
wire \weight_reg[7][0]_i_1_n_2 ;
wire \weight_reg[7][0]_i_1_n_3 ;
wire \weight_reg[7][0]_i_1_n_4 ;
wire \weight_reg[7][0]_i_1_n_5 ;
wire \weight_reg[7][0]_i_1_n_6 ;
wire \weight_reg[7][0]_i_1_n_7 ;
wire \weight_reg[7][12]_i_1_n_1 ;
wire \weight_reg[7][12]_i_1_n_2 ;
wire \weight_reg[7][12]_i_1_n_3 ;
wire \weight_reg[7][12]_i_1_n_4 ;
wire \weight_reg[7][12]_i_1_n_5 ;
wire \weight_reg[7][12]_i_1_n_6 ;
wire \weight_reg[7][12]_i_1_n_7 ;
wire \weight_reg[7][4]_i_1_n_0 ;
wire \weight_reg[7][4]_i_1_n_1 ;
wire \weight_reg[7][4]_i_1_n_2 ;
wire \weight_reg[7][4]_i_1_n_3 ;
wire \weight_reg[7][4]_i_1_n_4 ;
wire \weight_reg[7][4]_i_1_n_5 ;
wire \weight_reg[7][4]_i_1_n_6 ;
wire \weight_reg[7][4]_i_1_n_7 ;
wire \weight_reg[7][8]_i_1_n_0 ;
wire \weight_reg[7][8]_i_1_n_1 ;
wire \weight_reg[7][8]_i_1_n_2 ;
wire \weight_reg[7][8]_i_1_n_3 ;
wire \weight_reg[7][8]_i_1_n_4 ;
wire \weight_reg[7][8]_i_1_n_5 ;
wire \weight_reg[7][8]_i_1_n_6 ;
wire \weight_reg[7][8]_i_1_n_7 ;
wire [15:0]\weight_reg[7]_6 ;
wire \weight_reg[8][0]_i_1_n_0 ;
wire \weight_reg[8][0]_i_1_n_1 ;
wire \weight_reg[8][0]_i_1_n_2 ;
wire \weight_reg[8][0]_i_1_n_3 ;
wire \weight_reg[8][0]_i_1_n_4 ;
wire \weight_reg[8][0]_i_1_n_5 ;
wire \weight_reg[8][0]_i_1_n_6 ;
wire \weight_reg[8][0]_i_1_n_7 ;
wire \weight_reg[8][12]_i_1_n_1 ;
wire \weight_reg[8][12]_i_1_n_2 ;
wire \weight_reg[8][12]_i_1_n_3 ;
wire \weight_reg[8][12]_i_1_n_4 ;
wire \weight_reg[8][12]_i_1_n_5 ;
wire \weight_reg[8][12]_i_1_n_6 ;
wire \weight_reg[8][12]_i_1_n_7 ;
wire \weight_reg[8][4]_i_1_n_0 ;
wire \weight_reg[8][4]_i_1_n_1 ;
wire \weight_reg[8][4]_i_1_n_2 ;
wire \weight_reg[8][4]_i_1_n_3 ;
wire \weight_reg[8][4]_i_1_n_4 ;
wire \weight_reg[8][4]_i_1_n_5 ;
wire \weight_reg[8][4]_i_1_n_6 ;
wire \weight_reg[8][4]_i_1_n_7 ;
wire \weight_reg[8][8]_i_1_n_0 ;
wire \weight_reg[8][8]_i_1_n_1 ;
wire \weight_reg[8][8]_i_1_n_2 ;
wire \weight_reg[8][8]_i_1_n_3 ;
wire \weight_reg[8][8]_i_1_n_4 ;
wire \weight_reg[8][8]_i_1_n_5 ;
wire \weight_reg[8][8]_i_1_n_6 ;
wire \weight_reg[8][8]_i_1_n_7 ;
wire [15:0]\weight_reg[8]_7 ;
wire \weight_reg[9][0]_i_1_n_0 ;
wire \weight_reg[9][0]_i_1_n_1 ;
wire \weight_reg[9][0]_i_1_n_2 ;
wire \weight_reg[9][0]_i_1_n_3 ;
wire \weight_reg[9][0]_i_1_n_4 ;
wire \weight_reg[9][0]_i_1_n_5 ;
wire \weight_reg[9][0]_i_1_n_6 ;
wire \weight_reg[9][0]_i_1_n_7 ;
wire \weight_reg[9][12]_i_1_n_1 ;
wire \weight_reg[9][12]_i_1_n_2 ;
wire \weight_reg[9][12]_i_1_n_3 ;
wire \weight_reg[9][12]_i_1_n_4 ;
wire \weight_reg[9][12]_i_1_n_5 ;
wire \weight_reg[9][12]_i_1_n_6 ;
wire \weight_reg[9][12]_i_1_n_7 ;
wire \weight_reg[9][4]_i_1_n_0 ;
wire \weight_reg[9][4]_i_1_n_1 ;
wire \weight_reg[9][4]_i_1_n_2 ;
wire \weight_reg[9][4]_i_1_n_3 ;
wire \weight_reg[9][4]_i_1_n_4 ;
wire \weight_reg[9][4]_i_1_n_5 ;
wire \weight_reg[9][4]_i_1_n_6 ;
wire \weight_reg[9][4]_i_1_n_7 ;
wire \weight_reg[9][8]_i_1_n_0 ;
wire \weight_reg[9][8]_i_1_n_1 ;
wire \weight_reg[9][8]_i_1_n_2 ;
wire \weight_reg[9][8]_i_1_n_3 ;
wire \weight_reg[9][8]_i_1_n_4 ;
wire \weight_reg[9][8]_i_1_n_5 ;
wire \weight_reg[9][8]_i_1_n_6 ;
wire \weight_reg[9][8]_i_1_n_7 ;
wire [15:0]\weight_reg[9]_8 ;
wire [3:0]\write_reg_d_k_reg[11] ;
wire [2:0]\write_reg_d_k_reg[3] ;
wire [3:0]\write_reg_d_k_reg[3]_0 ;
wire [3:0]\write_reg_d_k_reg[7] ;
wire [15:0]\write_reg_x_k_reg[15] ;
wire NLW_ARG_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG_OVERFLOW_UNCONNECTED;
wire NLW_ARG_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG_P_UNCONNECTED;
wire [47:0]NLW_ARG_PCOUT_UNCONNECTED;
wire NLW_ARG__0_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__0_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__0_OVERFLOW_UNCONNECTED;
wire NLW_ARG__0_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__0_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__0_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__0_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__0_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__0_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__0_P_UNCONNECTED;
wire [47:0]NLW_ARG__0_PCOUT_UNCONNECTED;
wire NLW_ARG__1_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__1_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__1_OVERFLOW_UNCONNECTED;
wire NLW_ARG__1_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__1_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__1_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__1_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__1_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__1_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__1_P_UNCONNECTED;
wire [47:0]NLW_ARG__1_PCOUT_UNCONNECTED;
wire NLW_ARG__10_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__10_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__10_OVERFLOW_UNCONNECTED;
wire NLW_ARG__10_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__10_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__10_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__10_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__10_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__10_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__10_P_UNCONNECTED;
wire [47:0]NLW_ARG__10_PCOUT_UNCONNECTED;
wire NLW_ARG__11_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__11_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__11_OVERFLOW_UNCONNECTED;
wire NLW_ARG__11_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__11_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__11_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__11_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__11_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__11_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__11_P_UNCONNECTED;
wire [47:0]NLW_ARG__11_PCOUT_UNCONNECTED;
wire NLW_ARG__12_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__12_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__12_OVERFLOW_UNCONNECTED;
wire NLW_ARG__12_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__12_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__12_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__12_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__12_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__12_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__12_P_UNCONNECTED;
wire [47:0]NLW_ARG__12_PCOUT_UNCONNECTED;
wire NLW_ARG__13_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__13_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__13_OVERFLOW_UNCONNECTED;
wire NLW_ARG__13_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__13_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__13_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__13_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__13_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__13_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__13_P_UNCONNECTED;
wire [47:0]NLW_ARG__13_PCOUT_UNCONNECTED;
wire NLW_ARG__14_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__14_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__14_OVERFLOW_UNCONNECTED;
wire NLW_ARG__14_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__14_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__14_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__14_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__14_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__14_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__14_P_UNCONNECTED;
wire [47:0]NLW_ARG__14_PCOUT_UNCONNECTED;
wire NLW_ARG__15_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__15_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__15_OVERFLOW_UNCONNECTED;
wire NLW_ARG__15_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__15_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__15_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__15_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__15_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__15_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__15_P_UNCONNECTED;
wire [47:0]NLW_ARG__15_PCOUT_UNCONNECTED;
wire NLW_ARG__16_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__16_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__16_OVERFLOW_UNCONNECTED;
wire NLW_ARG__16_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__16_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__16_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__16_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__16_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__16_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__16_P_UNCONNECTED;
wire [47:0]NLW_ARG__16_PCOUT_UNCONNECTED;
wire NLW_ARG__17_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__17_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__17_OVERFLOW_UNCONNECTED;
wire NLW_ARG__17_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__17_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__17_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__17_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__17_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__17_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__17_P_UNCONNECTED;
wire [47:0]NLW_ARG__17_PCOUT_UNCONNECTED;
wire NLW_ARG__18_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__18_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__18_OVERFLOW_UNCONNECTED;
wire NLW_ARG__18_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__18_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__18_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__18_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__18_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__18_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__18_P_UNCONNECTED;
wire [47:0]NLW_ARG__18_PCOUT_UNCONNECTED;
wire NLW_ARG__19_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__19_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__19_OVERFLOW_UNCONNECTED;
wire NLW_ARG__19_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__19_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__19_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__19_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__19_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__19_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__19_P_UNCONNECTED;
wire [47:0]NLW_ARG__19_PCOUT_UNCONNECTED;
wire NLW_ARG__2_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__2_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__2_OVERFLOW_UNCONNECTED;
wire NLW_ARG__2_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__2_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__2_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__2_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__2_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__2_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__2_P_UNCONNECTED;
wire [47:0]NLW_ARG__2_PCOUT_UNCONNECTED;
wire NLW_ARG__20_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__20_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__20_OVERFLOW_UNCONNECTED;
wire NLW_ARG__20_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__20_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__20_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__20_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__20_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__20_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__20_P_UNCONNECTED;
wire [47:0]NLW_ARG__20_PCOUT_UNCONNECTED;
wire NLW_ARG__21_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__21_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__21_OVERFLOW_UNCONNECTED;
wire NLW_ARG__21_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__21_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__21_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__21_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__21_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__21_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__21_P_UNCONNECTED;
wire [47:0]NLW_ARG__21_PCOUT_UNCONNECTED;
wire NLW_ARG__22_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__22_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__22_OVERFLOW_UNCONNECTED;
wire NLW_ARG__22_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__22_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__22_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__22_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__22_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__22_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__22_P_UNCONNECTED;
wire [47:0]NLW_ARG__22_PCOUT_UNCONNECTED;
wire NLW_ARG__23_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__23_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__23_OVERFLOW_UNCONNECTED;
wire NLW_ARG__23_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__23_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__23_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__23_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__23_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__23_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__23_P_UNCONNECTED;
wire [47:0]NLW_ARG__23_PCOUT_UNCONNECTED;
wire NLW_ARG__24_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__24_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__24_OVERFLOW_UNCONNECTED;
wire NLW_ARG__24_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__24_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__24_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__24_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__24_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__24_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__24_P_UNCONNECTED;
wire [47:0]NLW_ARG__24_PCOUT_UNCONNECTED;
wire NLW_ARG__25_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__25_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__25_OVERFLOW_UNCONNECTED;
wire NLW_ARG__25_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__25_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__25_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__25_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__25_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__25_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__25_P_UNCONNECTED;
wire [47:0]NLW_ARG__25_PCOUT_UNCONNECTED;
wire NLW_ARG__26_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__26_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__26_OVERFLOW_UNCONNECTED;
wire NLW_ARG__26_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__26_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__26_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__26_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__26_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__26_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__26_P_UNCONNECTED;
wire [47:0]NLW_ARG__26_PCOUT_UNCONNECTED;
wire NLW_ARG__27_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__27_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__27_OVERFLOW_UNCONNECTED;
wire NLW_ARG__27_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__27_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__27_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__27_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__27_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__27_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__27_P_UNCONNECTED;
wire [47:0]NLW_ARG__27_PCOUT_UNCONNECTED;
wire NLW_ARG__28_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__28_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__28_OVERFLOW_UNCONNECTED;
wire NLW_ARG__28_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__28_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__28_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__28_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__28_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__28_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__28_P_UNCONNECTED;
wire [47:0]NLW_ARG__28_PCOUT_UNCONNECTED;
wire NLW_ARG__29_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__29_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__29_OVERFLOW_UNCONNECTED;
wire NLW_ARG__29_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__29_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__29_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__29_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__29_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__29_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__29_P_UNCONNECTED;
wire [47:0]NLW_ARG__29_PCOUT_UNCONNECTED;
wire NLW_ARG__3_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__3_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__3_OVERFLOW_UNCONNECTED;
wire NLW_ARG__3_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__3_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__3_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__3_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__3_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__3_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__3_P_UNCONNECTED;
wire [47:0]NLW_ARG__3_PCOUT_UNCONNECTED;
wire NLW_ARG__30_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__30_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__30_OVERFLOW_UNCONNECTED;
wire NLW_ARG__30_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__30_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__30_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__30_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__30_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__30_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__30_P_UNCONNECTED;
wire [47:0]NLW_ARG__30_PCOUT_UNCONNECTED;
wire NLW_ARG__4_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__4_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__4_OVERFLOW_UNCONNECTED;
wire NLW_ARG__4_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__4_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__4_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__4_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__4_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__4_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__4_P_UNCONNECTED;
wire [47:0]NLW_ARG__4_PCOUT_UNCONNECTED;
wire NLW_ARG__5_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__5_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__5_OVERFLOW_UNCONNECTED;
wire NLW_ARG__5_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__5_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__5_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__5_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__5_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__5_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__5_P_UNCONNECTED;
wire [47:0]NLW_ARG__5_PCOUT_UNCONNECTED;
wire NLW_ARG__6_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__6_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__6_OVERFLOW_UNCONNECTED;
wire NLW_ARG__6_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__6_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__6_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__6_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__6_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__6_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__6_P_UNCONNECTED;
wire [47:0]NLW_ARG__6_PCOUT_UNCONNECTED;
wire NLW_ARG__7_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__7_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__7_OVERFLOW_UNCONNECTED;
wire NLW_ARG__7_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__7_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__7_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__7_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__7_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__7_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__7_P_UNCONNECTED;
wire [47:0]NLW_ARG__7_PCOUT_UNCONNECTED;
wire NLW_ARG__8_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__8_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__8_OVERFLOW_UNCONNECTED;
wire NLW_ARG__8_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__8_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__8_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__8_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__8_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__8_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__8_P_UNCONNECTED;
wire [47:0]NLW_ARG__8_PCOUT_UNCONNECTED;
wire NLW_ARG__9_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__9_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__9_OVERFLOW_UNCONNECTED;
wire NLW_ARG__9_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__9_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__9_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__9_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__9_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__9_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__9_P_UNCONNECTED;
wire [47:0]NLW_ARG__9_PCOUT_UNCONNECTED;
wire [3:0]NLW_ARG_carry_O_UNCONNECTED;
wire [3:1]NLW_ARG_carry__3_CO_UNCONNECTED;
wire [3:2]NLW_ARG_carry__3_O_UNCONNECTED;
wire [3:3]NLW_add_temp_14__0_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_add_temp_14__138_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_add_temp_14__184_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_add_temp_14__230_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_add_temp_14__278_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_add_temp_14__46_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_add_temp_14__92_carry__2_CO_UNCONNECTED;
wire NLW_mul_temp_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_PCOUT_UNCONNECTED;
wire NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_1_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_1_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_1_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_1_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_1_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_1_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_1_PCOUT_UNCONNECTED;
wire NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_10_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_10_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_10_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_10_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_10_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_10_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_10_PCOUT_UNCONNECTED;
wire NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_11_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_11_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_11_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_11_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_11_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_11_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_11_PCOUT_UNCONNECTED;
wire NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_12_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_12_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_12_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_12_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_12_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_12_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_12_PCOUT_UNCONNECTED;
wire NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_13_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_13_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_13_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_13_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_13_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_13_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_13_PCOUT_UNCONNECTED;
wire NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_14_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_14_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_14_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_14_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_14_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_14_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_14_PCOUT_UNCONNECTED;
wire NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_15_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_15_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_15_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_15_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_15_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_15_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_15_PCOUT_UNCONNECTED;
wire NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_17_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_17_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_17_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_17_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_17_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_17_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_17_PCOUT_UNCONNECTED;
wire NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_18_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_18_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_18_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_18_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_18_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_18_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_18_PCOUT_UNCONNECTED;
wire NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_19_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_19_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_19_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_19_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_19_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_19_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_19_PCOUT_UNCONNECTED;
wire NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_2_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_2_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_2_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_2_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_2_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_2_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_2_PCOUT_UNCONNECTED;
wire NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_20_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_20_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_20_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_20_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_20_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_20_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_20_PCOUT_UNCONNECTED;
wire NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_21_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_21_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_21_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_21_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_21_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_21_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_21_PCOUT_UNCONNECTED;
wire NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_22_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_22_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_22_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_22_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_22_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_22_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_22_PCOUT_UNCONNECTED;
wire NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_23_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_23_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_23_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_23_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_23_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_23_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_23_PCOUT_UNCONNECTED;
wire NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_24_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_24_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_24_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_24_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_24_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_24_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_24_PCOUT_UNCONNECTED;
wire NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_25_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_25_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_25_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_25_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_25_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_25_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_25_PCOUT_UNCONNECTED;
wire NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_26_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_26_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_26_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_26_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_26_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_26_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_26_PCOUT_UNCONNECTED;
wire NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_27_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_27_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_27_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_27_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_27_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_27_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_27_PCOUT_UNCONNECTED;
wire NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_28_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_28_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_28_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_28_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_28_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_28_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_28_PCOUT_UNCONNECTED;
wire NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_29_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_29_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_29_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_29_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_29_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_29_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_29_PCOUT_UNCONNECTED;
wire NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_3_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_3_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_3_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_3_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_3_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_3_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_3_PCOUT_UNCONNECTED;
wire NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_30_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_30_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_30_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_30_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_30_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_30_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_30_PCOUT_UNCONNECTED;
wire NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_31_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_31_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_31_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_31_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_31_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_31_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_31_PCOUT_UNCONNECTED;
wire NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_32_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_32_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_32_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_32_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_32_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_32_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_32_PCOUT_UNCONNECTED;
wire NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_4_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_4_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_4_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_4_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_4_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_4_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_4_PCOUT_UNCONNECTED;
wire NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_5_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_5_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_5_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_5_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_5_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_5_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_5_PCOUT_UNCONNECTED;
wire NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_6_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_6_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_6_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_6_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_6_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_6_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_6_PCOUT_UNCONNECTED;
wire NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_7_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_7_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_7_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_7_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_7_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_7_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_7_PCOUT_UNCONNECTED;
wire NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_8_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_8_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_8_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_8_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_8_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_8_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_8_PCOUT_UNCONNECTED;
wire NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_9_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_9_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_9_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_9_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_9_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_9_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_9_PCOUT_UNCONNECTED;
wire [3:3]NLW_sub_temp_carry__2_CO_UNCONNECTED;
wire [3:3]\NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED ;
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG
(.A({\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_18 ,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG_OVERFLOW_UNCONNECTED),
.P({NLW_ARG_P_UNCONNECTED[47:30],in,ARG_n_92,ARG_n_93,ARG_n_94,ARG_n_95,ARG_n_96,ARG_n_97,ARG_n_98,ARG_n_99,ARG_n_100,ARG_n_101,ARG_n_102,ARG_n_103,ARG_n_104,ARG_n_105}),
.PATTERNBDETECT(NLW_ARG_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__0
(.A({\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__0_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[1]_0 [15],\weight_reg[1]_0 [15],\weight_reg[1]_0 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__0_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_1 ,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__0_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__0_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__0_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__0_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__0_P_UNCONNECTED[47:30],RESIZE16,ARG__0_n_92,ARG__0_n_93,ARG__0_n_94,ARG__0_n_95,ARG__0_n_96,ARG__0_n_97,ARG__0_n_98,ARG__0_n_99,ARG__0_n_100,ARG__0_n_101,ARG__0_n_102,ARG__0_n_103,ARG__0_n_104,ARG__0_n_105}),
.PATTERNBDETECT(NLW_ARG__0_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__0_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__0_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__0_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__0_i_1
(.I0(\^mul_temp_1 ),
.O(ARG__0_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__1
(.A({\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__1_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__1_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_19 ,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__1_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__1_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__1_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__1_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__1_P_UNCONNECTED[47:30],ARG__1_n_76,ARG__1_n_77,ARG__1_n_78,ARG__1_n_79,ARG__1_n_80,ARG__1_n_81,ARG__1_n_82,ARG__1_n_83,ARG__1_n_84,ARG__1_n_85,ARG__1_n_86,ARG__1_n_87,ARG__1_n_88,ARG__1_n_89,ARG__1_n_90,ARG__1_n_91,ARG__1_n_92,ARG__1_n_93,ARG__1_n_94,ARG__1_n_95,ARG__1_n_96,ARG__1_n_97,ARG__1_n_98,ARG__1_n_99,ARG__1_n_100,ARG__1_n_101,ARG__1_n_102,ARG__1_n_103,ARG__1_n_104,ARG__1_n_105}),
.PATTERNBDETECT(NLW_ARG__1_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__1_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__1_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__1_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__10
(.A({\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__10_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[6]_5 [15],\weight_reg[6]_5 [15],\weight_reg[6]_5 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__10_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_6 ,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__10_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__10_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__10_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__10_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__10_P_UNCONNECTED[47:30],RESIZE26,ARG__10_n_92,ARG__10_n_93,ARG__10_n_94,ARG__10_n_95,ARG__10_n_96,ARG__10_n_97,ARG__10_n_98,ARG__10_n_99,ARG__10_n_100,ARG__10_n_101,ARG__10_n_102,ARG__10_n_103,ARG__10_n_104,ARG__10_n_105}),
.PATTERNBDETECT(NLW_ARG__10_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__10_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__10_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__10_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__10_i_1
(.I0(\^mul_temp_6 ),
.O(ARG__10_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__11
(.A({\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__11_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__11_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_24 ,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__11_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__11_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__11_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__11_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__11_P_UNCONNECTED[47:30],ARG__11_n_76,ARG__11_n_77,ARG__11_n_78,ARG__11_n_79,ARG__11_n_80,ARG__11_n_81,ARG__11_n_82,ARG__11_n_83,ARG__11_n_84,ARG__11_n_85,ARG__11_n_86,ARG__11_n_87,ARG__11_n_88,ARG__11_n_89,ARG__11_n_90,ARG__11_n_91,ARG__11_n_92,ARG__11_n_93,ARG__11_n_94,ARG__11_n_95,ARG__11_n_96,ARG__11_n_97,ARG__11_n_98,ARG__11_n_99,ARG__11_n_100,ARG__11_n_101,ARG__11_n_102,ARG__11_n_103,ARG__11_n_104,ARG__11_n_105}),
.PATTERNBDETECT(NLW_ARG__11_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__11_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__11_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__11_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__11_i_1
(.I0(\^mul_temp_24 ),
.O(ARG__11_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__12
(.A({\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__12_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[7]_6 [15],\weight_reg[7]_6 [15],\weight_reg[7]_6 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__12_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_7 ,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__12_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__12_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__12_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__12_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__12_P_UNCONNECTED[47:30],RESIZE28,ARG__12_n_92,ARG__12_n_93,ARG__12_n_94,ARG__12_n_95,ARG__12_n_96,ARG__12_n_97,ARG__12_n_98,ARG__12_n_99,ARG__12_n_100,ARG__12_n_101,ARG__12_n_102,ARG__12_n_103,ARG__12_n_104,ARG__12_n_105}),
.PATTERNBDETECT(NLW_ARG__12_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__12_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__12_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__12_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__12_i_1
(.I0(\^mul_temp_7 ),
.O(ARG__12_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__13
(.A({\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__13_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__13_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_25 ,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__13_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__13_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__13_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__13_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__13_P_UNCONNECTED[47:30],ARG__13_n_76,ARG__13_n_77,ARG__13_n_78,ARG__13_n_79,ARG__13_n_80,ARG__13_n_81,ARG__13_n_82,ARG__13_n_83,ARG__13_n_84,ARG__13_n_85,ARG__13_n_86,ARG__13_n_87,ARG__13_n_88,ARG__13_n_89,ARG__13_n_90,ARG__13_n_91,ARG__13_n_92,ARG__13_n_93,ARG__13_n_94,ARG__13_n_95,ARG__13_n_96,ARG__13_n_97,ARG__13_n_98,ARG__13_n_99,ARG__13_n_100,ARG__13_n_101,ARG__13_n_102,ARG__13_n_103,ARG__13_n_104,ARG__13_n_105}),
.PATTERNBDETECT(NLW_ARG__13_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__13_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__13_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__13_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__13_i_1
(.I0(\^mul_temp_25 ),
.O(ARG__13_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__14
(.A({\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__14_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[8]_7 [15],\weight_reg[8]_7 [15],\weight_reg[8]_7 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__14_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_8 ,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__14_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__14_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__14_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__14_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__14_P_UNCONNECTED[47:30],RESIZE30,ARG__14_n_92,ARG__14_n_93,ARG__14_n_94,ARG__14_n_95,ARG__14_n_96,ARG__14_n_97,ARG__14_n_98,ARG__14_n_99,ARG__14_n_100,ARG__14_n_101,ARG__14_n_102,ARG__14_n_103,ARG__14_n_104,ARG__14_n_105}),
.PATTERNBDETECT(NLW_ARG__14_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__14_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__14_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__14_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__14_i_1
(.I0(\^mul_temp_8 ),
.O(ARG__14_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__15
(.A({\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__15_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__15_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_26 ,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__15_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__15_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__15_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__15_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__15_P_UNCONNECTED[47:30],ARG__15_n_76,ARG__15_n_77,ARG__15_n_78,ARG__15_n_79,ARG__15_n_80,ARG__15_n_81,ARG__15_n_82,ARG__15_n_83,ARG__15_n_84,ARG__15_n_85,ARG__15_n_86,ARG__15_n_87,ARG__15_n_88,ARG__15_n_89,ARG__15_n_90,ARG__15_n_91,ARG__15_n_92,ARG__15_n_93,ARG__15_n_94,ARG__15_n_95,ARG__15_n_96,ARG__15_n_97,ARG__15_n_98,ARG__15_n_99,ARG__15_n_100,ARG__15_n_101,ARG__15_n_102,ARG__15_n_103,ARG__15_n_104,ARG__15_n_105}),
.PATTERNBDETECT(NLW_ARG__15_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__15_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__15_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__15_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__15_i_1
(.I0(\^mul_temp_26 ),
.O(ARG__15_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__16
(.A({\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__16_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[9]_8 [15],\weight_reg[9]_8 [15],\weight_reg[9]_8 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__16_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_9 ,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__16_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__16_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__16_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__16_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__16_P_UNCONNECTED[47:30],RESIZE32,ARG__16_n_92,ARG__16_n_93,ARG__16_n_94,ARG__16_n_95,ARG__16_n_96,ARG__16_n_97,ARG__16_n_98,ARG__16_n_99,ARG__16_n_100,ARG__16_n_101,ARG__16_n_102,ARG__16_n_103,ARG__16_n_104,ARG__16_n_105}),
.PATTERNBDETECT(NLW_ARG__16_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__16_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__16_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__16_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__16_i_1
(.I0(\^mul_temp_9 ),
.O(ARG__16_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__17
(.A({\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__17_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__17_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_27 ,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__17_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__17_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__17_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__17_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__17_P_UNCONNECTED[47:30],ARG__17_n_76,ARG__17_n_77,ARG__17_n_78,ARG__17_n_79,ARG__17_n_80,ARG__17_n_81,ARG__17_n_82,ARG__17_n_83,ARG__17_n_84,ARG__17_n_85,ARG__17_n_86,ARG__17_n_87,ARG__17_n_88,ARG__17_n_89,ARG__17_n_90,ARG__17_n_91,ARG__17_n_92,ARG__17_n_93,ARG__17_n_94,ARG__17_n_95,ARG__17_n_96,ARG__17_n_97,ARG__17_n_98,ARG__17_n_99,ARG__17_n_100,ARG__17_n_101,ARG__17_n_102,ARG__17_n_103,ARG__17_n_104,ARG__17_n_105}),
.PATTERNBDETECT(NLW_ARG__17_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__17_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__17_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__17_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__17_i_1
(.I0(\^mul_temp_27 ),
.O(ARG__17_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__18
(.A({\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__18_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[10]_9 [15],\weight_reg[10]_9 [15],\weight_reg[10]_9 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__18_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_10 ,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__18_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__18_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__18_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__18_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__18_P_UNCONNECTED[47:30],RESIZE34,ARG__18_n_92,ARG__18_n_93,ARG__18_n_94,ARG__18_n_95,ARG__18_n_96,ARG__18_n_97,ARG__18_n_98,ARG__18_n_99,ARG__18_n_100,ARG__18_n_101,ARG__18_n_102,ARG__18_n_103,ARG__18_n_104,ARG__18_n_105}),
.PATTERNBDETECT(NLW_ARG__18_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__18_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__18_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__18_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__18_i_1
(.I0(\^mul_temp_10 ),
.O(ARG__18_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__19
(.A({\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__19_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__19_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_28 ,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__19_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__19_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__19_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__19_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__19_P_UNCONNECTED[47:30],ARG__19_n_76,ARG__19_n_77,ARG__19_n_78,ARG__19_n_79,ARG__19_n_80,ARG__19_n_81,ARG__19_n_82,ARG__19_n_83,ARG__19_n_84,ARG__19_n_85,ARG__19_n_86,ARG__19_n_87,ARG__19_n_88,ARG__19_n_89,ARG__19_n_90,ARG__19_n_91,ARG__19_n_92,ARG__19_n_93,ARG__19_n_94,ARG__19_n_95,ARG__19_n_96,ARG__19_n_97,ARG__19_n_98,ARG__19_n_99,ARG__19_n_100,ARG__19_n_101,ARG__19_n_102,ARG__19_n_103,ARG__19_n_104,ARG__19_n_105}),
.PATTERNBDETECT(NLW_ARG__19_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__19_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__19_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__19_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__19_i_1
(.I0(\^mul_temp_28 ),
.O(ARG__19_i_1_n_0));
LUT1 #(
.INIT(2'h1))
ARG__1_i_1
(.I0(\^mul_temp_19 ),
.O(ARG__1_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__2
(.A({\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__2_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[2]_1 [15],\weight_reg[2]_1 [15],\weight_reg[2]_1 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__2_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_2 ,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__2_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__2_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__2_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__2_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__2_P_UNCONNECTED[47:30],RESIZE18,ARG__2_n_92,ARG__2_n_93,ARG__2_n_94,ARG__2_n_95,ARG__2_n_96,ARG__2_n_97,ARG__2_n_98,ARG__2_n_99,ARG__2_n_100,ARG__2_n_101,ARG__2_n_102,ARG__2_n_103,ARG__2_n_104,ARG__2_n_105}),
.PATTERNBDETECT(NLW_ARG__2_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__2_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__2_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__2_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__20
(.A({\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__20_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[11]_10 [15],\weight_reg[11]_10 [15],\weight_reg[11]_10 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__20_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_11 ,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__20_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__20_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__20_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__20_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__20_P_UNCONNECTED[47:30],RESIZE36,ARG__20_n_92,ARG__20_n_93,ARG__20_n_94,ARG__20_n_95,ARG__20_n_96,ARG__20_n_97,ARG__20_n_98,ARG__20_n_99,ARG__20_n_100,ARG__20_n_101,ARG__20_n_102,ARG__20_n_103,ARG__20_n_104,ARG__20_n_105}),
.PATTERNBDETECT(NLW_ARG__20_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__20_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__20_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__20_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__20_i_1
(.I0(\^mul_temp_11 ),
.O(ARG__20_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__21
(.A({\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__21_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__21_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_29 ,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__21_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__21_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__21_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__21_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__21_P_UNCONNECTED[47:30],ARG__21_n_76,ARG__21_n_77,ARG__21_n_78,ARG__21_n_79,ARG__21_n_80,ARG__21_n_81,ARG__21_n_82,ARG__21_n_83,ARG__21_n_84,ARG__21_n_85,ARG__21_n_86,ARG__21_n_87,ARG__21_n_88,ARG__21_n_89,ARG__21_n_90,ARG__21_n_91,ARG__21_n_92,ARG__21_n_93,ARG__21_n_94,ARG__21_n_95,ARG__21_n_96,ARG__21_n_97,ARG__21_n_98,ARG__21_n_99,ARG__21_n_100,ARG__21_n_101,ARG__21_n_102,ARG__21_n_103,ARG__21_n_104,ARG__21_n_105}),
.PATTERNBDETECT(NLW_ARG__21_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__21_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__21_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__21_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__21_i_1
(.I0(\^mul_temp_29 ),
.O(ARG__21_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__22
(.A({\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__22_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[12]_11 [15],\weight_reg[12]_11 [15],\weight_reg[12]_11 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__22_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_12 ,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__22_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__22_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__22_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__22_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__22_P_UNCONNECTED[47:30],RESIZE38,ARG__22_n_92,ARG__22_n_93,ARG__22_n_94,ARG__22_n_95,ARG__22_n_96,ARG__22_n_97,ARG__22_n_98,ARG__22_n_99,ARG__22_n_100,ARG__22_n_101,ARG__22_n_102,ARG__22_n_103,ARG__22_n_104,ARG__22_n_105}),
.PATTERNBDETECT(NLW_ARG__22_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__22_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__22_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__22_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__22_i_1
(.I0(\^mul_temp_12 ),
.O(ARG__22_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__23
(.A({\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__23_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__23_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_30 ,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__23_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__23_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__23_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__23_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__23_P_UNCONNECTED[47:30],ARG__23_n_76,ARG__23_n_77,ARG__23_n_78,ARG__23_n_79,ARG__23_n_80,ARG__23_n_81,ARG__23_n_82,ARG__23_n_83,ARG__23_n_84,ARG__23_n_85,ARG__23_n_86,ARG__23_n_87,ARG__23_n_88,ARG__23_n_89,ARG__23_n_90,ARG__23_n_91,ARG__23_n_92,ARG__23_n_93,ARG__23_n_94,ARG__23_n_95,ARG__23_n_96,ARG__23_n_97,ARG__23_n_98,ARG__23_n_99,ARG__23_n_100,ARG__23_n_101,ARG__23_n_102,ARG__23_n_103,ARG__23_n_104,ARG__23_n_105}),
.PATTERNBDETECT(NLW_ARG__23_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__23_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__23_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__23_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__23_i_1
(.I0(\^mul_temp_30 ),
.O(ARG__23_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__24
(.A({\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__24_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[13]_12 [15],\weight_reg[13]_12 [15],\weight_reg[13]_12 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__24_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_13 ,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__24_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__24_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__24_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__24_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__24_P_UNCONNECTED[47:30],RESIZE40,ARG__24_n_92,ARG__24_n_93,ARG__24_n_94,ARG__24_n_95,ARG__24_n_96,ARG__24_n_97,ARG__24_n_98,ARG__24_n_99,ARG__24_n_100,ARG__24_n_101,ARG__24_n_102,ARG__24_n_103,ARG__24_n_104,ARG__24_n_105}),
.PATTERNBDETECT(NLW_ARG__24_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__24_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__24_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__24_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__24_i_1
(.I0(\^mul_temp_13 ),
.O(ARG__24_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__25
(.A({\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__25_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__25_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_31 ,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__25_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__25_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__25_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__25_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__25_P_UNCONNECTED[47:30],ARG__25_n_76,ARG__25_n_77,ARG__25_n_78,ARG__25_n_79,ARG__25_n_80,ARG__25_n_81,ARG__25_n_82,ARG__25_n_83,ARG__25_n_84,ARG__25_n_85,ARG__25_n_86,ARG__25_n_87,ARG__25_n_88,ARG__25_n_89,ARG__25_n_90,ARG__25_n_91,ARG__25_n_92,ARG__25_n_93,ARG__25_n_94,ARG__25_n_95,ARG__25_n_96,ARG__25_n_97,ARG__25_n_98,ARG__25_n_99,ARG__25_n_100,ARG__25_n_101,ARG__25_n_102,ARG__25_n_103,ARG__25_n_104,ARG__25_n_105}),
.PATTERNBDETECT(NLW_ARG__25_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__25_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__25_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__25_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__25_i_1
(.I0(\^mul_temp_31 ),
.O(ARG__25_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__26
(.A({\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__26_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[14]_13 [15],\weight_reg[14]_13 [15],\weight_reg[14]_13 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__26_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_14 ,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__26_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__26_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__26_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__26_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__26_P_UNCONNECTED[47:30],RESIZE42,ARG__26_n_92,ARG__26_n_93,ARG__26_n_94,ARG__26_n_95,ARG__26_n_96,ARG__26_n_97,ARG__26_n_98,ARG__26_n_99,ARG__26_n_100,ARG__26_n_101,ARG__26_n_102,ARG__26_n_103,ARG__26_n_104,ARG__26_n_105}),
.PATTERNBDETECT(NLW_ARG__26_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__26_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__26_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__26_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__26_i_1
(.I0(\^mul_temp_14 ),
.O(ARG__26_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__27
(.A({\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__27_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__27_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_32 ,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__27_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__27_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__27_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__27_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__27_P_UNCONNECTED[47:30],ARG__27_n_76,ARG__27_n_77,ARG__27_n_78,ARG__27_n_79,ARG__27_n_80,ARG__27_n_81,ARG__27_n_82,ARG__27_n_83,ARG__27_n_84,ARG__27_n_85,ARG__27_n_86,ARG__27_n_87,ARG__27_n_88,ARG__27_n_89,ARG__27_n_90,ARG__27_n_91,ARG__27_n_92,ARG__27_n_93,ARG__27_n_94,ARG__27_n_95,ARG__27_n_96,ARG__27_n_97,ARG__27_n_98,ARG__27_n_99,ARG__27_n_100,ARG__27_n_101,ARG__27_n_102,ARG__27_n_103,ARG__27_n_104,ARG__27_n_105}),
.PATTERNBDETECT(NLW_ARG__27_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__27_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__27_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__27_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__27_i_1
(.I0(\^mul_temp_32 ),
.O(ARG__27_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__28
(.A({\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__28_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[15]_14 [15],\weight_reg[15]_14 [15],\weight_reg[15]_14 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__28_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_15 ,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__28_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__28_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__28_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__28_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__28_P_UNCONNECTED[47:30],RESIZE44,ARG__28_n_92,ARG__28_n_93,ARG__28_n_94,ARG__28_n_95,ARG__28_n_96,ARG__28_n_97,ARG__28_n_98,ARG__28_n_99,ARG__28_n_100,ARG__28_n_101,ARG__28_n_102,ARG__28_n_103,ARG__28_n_104,ARG__28_n_105}),
.PATTERNBDETECT(NLW_ARG__28_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__28_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__28_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__28_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__28_i_1
(.I0(\^mul_temp_15 ),
.O(ARG__28_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__29
(.A({\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__29_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__29_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_17 ,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__29_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__29_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__29_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__29_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__29_P_UNCONNECTED[47:30],ARG__29_n_76,ARG__29_n_77,ARG__29_n_78,ARG__29_n_79,ARG__29_n_80,ARG__29_n_81,ARG__29_n_82,ARG__29_n_83,ARG__29_n_84,ARG__29_n_85,ARG__29_n_86,ARG__29_n_87,ARG__29_n_88,ARG__29_n_89,ARG__29_n_90,ARG__29_n_91,ARG__29_n_92,ARG__29_n_93,ARG__29_n_94,ARG__29_n_95,ARG__29_n_96,ARG__29_n_97,ARG__29_n_98,ARG__29_n_99,ARG__29_n_100,ARG__29_n_101,ARG__29_n_102,ARG__29_n_103,ARG__29_n_104,ARG__29_n_105}),
.PATTERNBDETECT(NLW_ARG__29_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__29_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__29_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__29_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__29_i_1
(.I0(\^mul_temp_17 ),
.O(ARG__29_i_1_n_0));
LUT1 #(
.INIT(2'h1))
ARG__2_i_1
(.I0(\^mul_temp_2 ),
.O(ARG__2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__3
(.A({\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__3_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__3_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_20 ,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__3_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__3_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__3_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__3_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__3_P_UNCONNECTED[47:30],ARG__3_n_76,ARG__3_n_77,ARG__3_n_78,ARG__3_n_79,ARG__3_n_80,ARG__3_n_81,ARG__3_n_82,ARG__3_n_83,ARG__3_n_84,ARG__3_n_85,ARG__3_n_86,ARG__3_n_87,ARG__3_n_88,ARG__3_n_89,ARG__3_n_90,ARG__3_n_91,ARG__3_n_92,ARG__3_n_93,ARG__3_n_94,ARG__3_n_95,ARG__3_n_96,ARG__3_n_97,ARG__3_n_98,ARG__3_n_99,ARG__3_n_100,ARG__3_n_101,ARG__3_n_102,ARG__3_n_103,ARG__3_n_104,ARG__3_n_105}),
.PATTERNBDETECT(NLW_ARG__3_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__3_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__3_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__3_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__30
(.A({\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__30_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[0]_15 [15],\weight_reg[0]_15 [15],\weight_reg[0]_15 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__30_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp ,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__30_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__30_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__30_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__30_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__30_P_UNCONNECTED[47:30],RESIZE15,ARG__30_n_92,ARG__30_n_93,ARG__30_n_94,ARG__30_n_95,ARG__30_n_96,ARG__30_n_97,ARG__30_n_98,ARG__30_n_99,ARG__30_n_100,ARG__30_n_101,ARG__30_n_102,ARG__30_n_103,ARG__30_n_104,ARG__30_n_105}),
.PATTERNBDETECT(NLW_ARG__30_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__30_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__30_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__30_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__30_i_1
(.I0(\^mul_temp ),
.O(ARG__30_i_1_n_0));
LUT1 #(
.INIT(2'h1))
ARG__3_i_1
(.I0(\^mul_temp_20 ),
.O(ARG__3_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__4
(.A({\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__4_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[3]_2 [15],\weight_reg[3]_2 [15],\weight_reg[3]_2 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__4_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_3 ,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__4_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__4_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__4_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__4_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__4_P_UNCONNECTED[47:30],RESIZE20,ARG__4_n_92,ARG__4_n_93,ARG__4_n_94,ARG__4_n_95,ARG__4_n_96,ARG__4_n_97,ARG__4_n_98,ARG__4_n_99,ARG__4_n_100,ARG__4_n_101,ARG__4_n_102,ARG__4_n_103,ARG__4_n_104,ARG__4_n_105}),
.PATTERNBDETECT(NLW_ARG__4_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__4_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__4_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__4_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__4_i_1
(.I0(\^mul_temp_3 ),
.O(ARG__4_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__5
(.A({\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__5_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__5_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_21 ,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__5_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__5_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__5_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__5_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__5_P_UNCONNECTED[47:30],ARG__5_n_76,ARG__5_n_77,ARG__5_n_78,ARG__5_n_79,ARG__5_n_80,ARG__5_n_81,ARG__5_n_82,ARG__5_n_83,ARG__5_n_84,ARG__5_n_85,ARG__5_n_86,ARG__5_n_87,ARG__5_n_88,ARG__5_n_89,ARG__5_n_90,ARG__5_n_91,ARG__5_n_92,ARG__5_n_93,ARG__5_n_94,ARG__5_n_95,ARG__5_n_96,ARG__5_n_97,ARG__5_n_98,ARG__5_n_99,ARG__5_n_100,ARG__5_n_101,ARG__5_n_102,ARG__5_n_103,ARG__5_n_104,ARG__5_n_105}),
.PATTERNBDETECT(NLW_ARG__5_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__5_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__5_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__5_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__5_i_1
(.I0(\^mul_temp_21 ),
.O(ARG__5_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__6
(.A({\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__6_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[4]_3 [15],\weight_reg[4]_3 [15],\weight_reg[4]_3 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__6_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_4 ,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__6_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__6_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__6_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__6_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__6_P_UNCONNECTED[47:30],RESIZE22,ARG__6_n_92,ARG__6_n_93,ARG__6_n_94,ARG__6_n_95,ARG__6_n_96,ARG__6_n_97,ARG__6_n_98,ARG__6_n_99,ARG__6_n_100,ARG__6_n_101,ARG__6_n_102,ARG__6_n_103,ARG__6_n_104,ARG__6_n_105}),
.PATTERNBDETECT(NLW_ARG__6_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__6_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__6_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__6_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__6_i_1
(.I0(\^mul_temp_4 ),
.O(ARG__6_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__7
(.A({\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__7_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__7_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_22 ,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__7_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__7_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__7_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__7_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__7_P_UNCONNECTED[47:30],ARG__7_n_76,ARG__7_n_77,ARG__7_n_78,ARG__7_n_79,ARG__7_n_80,ARG__7_n_81,ARG__7_n_82,ARG__7_n_83,ARG__7_n_84,ARG__7_n_85,ARG__7_n_86,ARG__7_n_87,ARG__7_n_88,ARG__7_n_89,ARG__7_n_90,ARG__7_n_91,ARG__7_n_92,ARG__7_n_93,ARG__7_n_94,ARG__7_n_95,ARG__7_n_96,ARG__7_n_97,ARG__7_n_98,ARG__7_n_99,ARG__7_n_100,ARG__7_n_101,ARG__7_n_102,ARG__7_n_103,ARG__7_n_104,ARG__7_n_105}),
.PATTERNBDETECT(NLW_ARG__7_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__7_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__7_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__7_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__7_i_1
(.I0(\^mul_temp_22 ),
.O(ARG__7_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__8
(.A({\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__8_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[5]_4 [15],\weight_reg[5]_4 [15],\weight_reg[5]_4 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__8_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_5 ,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__8_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__8_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__8_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__8_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__8_P_UNCONNECTED[47:30],RESIZE24,ARG__8_n_92,ARG__8_n_93,ARG__8_n_94,ARG__8_n_95,ARG__8_n_96,ARG__8_n_97,ARG__8_n_98,ARG__8_n_99,ARG__8_n_100,ARG__8_n_101,ARG__8_n_102,ARG__8_n_103,ARG__8_n_104,ARG__8_n_105}),
.PATTERNBDETECT(NLW_ARG__8_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__8_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__8_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__8_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__8_i_1
(.I0(\^mul_temp_5 ),
.O(ARG__8_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__9
(.A({\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__9_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__9_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_23 ,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__9_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__9_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
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LUT1 #(
.INIT(2'h1))
ARG__9_i_1
(.I0(\^mul_temp_23 ),
.O(ARG__9_i_1_n_0));
CARRY4 ARG_carry
(.CI(1'b0),
.CO({ARG_carry_n_0,ARG_carry_n_1,ARG_carry_n_2,ARG_carry_n_3}),
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.DI({1'b0,mul_temp_16[1:0],1'b1}),
.O(NLW_ARG_carry_O_UNCONNECTED[3:0]),
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CARRY4 ARG_carry__0
(.CI(ARG_carry_n_0),
.CO({ARG_carry__0_n_0,ARG_carry__0_n_1,ARG_carry__0_n_2,ARG_carry__0_n_3}),
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.O(ARG__31[20:17]),
.S({ARG_carry__0_i_2_n_0,ARG_carry__0_i_3_n_0,ARG_carry__0_i_4_n_0,mul_temp_16[3]}));
LUT2 #(
.INIT(4'h9))
ARG_carry__0_i_2
(.I0(mul_temp_16[5]),
.I1(mul_temp_16[6]),
.O(ARG_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__0_i_3
(.I0(mul_temp_16[3]),
.I1(mul_temp_16[5]),
.O(ARG_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__0_i_4
(.I0(mul_temp_16[3]),
.I1(mul_temp_16[4]),
.O(ARG_carry__0_i_4_n_0));
CARRY4 ARG_carry__1
(.CI(ARG_carry__0_n_0),
.CO({ARG_carry__1_n_0,ARG_carry__1_n_1,ARG_carry__1_n_2,ARG_carry__1_n_3}),
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.DI(mul_temp_16[9:6]),
.O(ARG__31[24:21]),
.S({ARG_carry__1_i_1_n_0,ARG_carry__1_i_2_n_0,ARG_carry__1_i_3_n_0,ARG_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
ARG_carry__1_i_1
(.I0(mul_temp_16[9]),
.I1(mul_temp_16[10]),
.O(ARG_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__1_i_2
(.I0(mul_temp_16[8]),
.I1(mul_temp_16[9]),
.O(ARG_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__1_i_3
(.I0(mul_temp_16[7]),
.I1(mul_temp_16[8]),
.O(ARG_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__1_i_4
(.I0(mul_temp_16[6]),
.I1(mul_temp_16[7]),
.O(ARG_carry__1_i_4_n_0));
CARRY4 ARG_carry__2
(.CI(ARG_carry__1_n_0),
.CO({ARG_carry__2_n_0,ARG_carry__2_n_1,ARG_carry__2_n_2,ARG_carry__2_n_3}),
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.DI(mul_temp_16[13:10]),
.O(ARG__31[28:25]),
.S({ARG_carry__2_i_1_n_0,ARG_carry__2_i_2_n_0,ARG_carry__2_i_3_n_0,ARG_carry__2_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
ARG_carry__2_i_1
(.I0(mul_temp_16[13]),
.I1(mul_temp_16[14]),
.O(ARG_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__2_i_2
(.I0(mul_temp_16[12]),
.I1(mul_temp_16[13]),
.O(ARG_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__2_i_3
(.I0(mul_temp_16[11]),
.I1(mul_temp_16[12]),
.O(ARG_carry__2_i_3_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__2_i_4
(.I0(mul_temp_16[10]),
.I1(mul_temp_16[11]),
.O(ARG_carry__2_i_4_n_0));
CARRY4 ARG_carry__3
(.CI(ARG_carry__2_n_0),
.CO({NLW_ARG_carry__3_CO_UNCONNECTED[3:1],ARG_carry__3_n_3}),
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.O({NLW_ARG_carry__3_O_UNCONNECTED[3:2],ARG__31[32],ARG__31[29]}),
.S({1'b0,1'b0,1'b1,ARG_carry__3_i_1_n_0}));
LUT2 #(
.INIT(4'h9))
ARG_carry__3_i_1
(.I0(mul_temp_16[14]),
.I1(mul_temp_16[15]),
.O(ARG_carry__3_i_1_n_0));
LUT1 #(
.INIT(2'h1))
ARG_i_1
(.I0(\^mul_temp_18 ),
.O(ARG_i_1_n_0));
CARRY4 add_temp_14__0_carry
(.CI(1'b0),
.CO({add_temp_14__0_carry_n_0,add_temp_14__0_carry_n_1,add_temp_14__0_carry_n_2,add_temp_14__0_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__0_carry_i_1_n_0,add_temp_14__0_carry_i_2_n_0,add_temp_14__0_carry_i_3_n_0,1'b0}),
.O({add_temp_14__0_carry_n_4,add_temp_14__0_carry_n_5,add_temp_14__0_carry_n_6,add_temp_14__0_carry_n_7}),
.S({add_temp_14__0_carry_i_4_n_0,add_temp_14__0_carry_i_5_n_0,add_temp_14__0_carry_i_6_n_0,add_temp_14__0_carry_i_7_n_0}));
CARRY4 add_temp_14__0_carry__0
(.CI(add_temp_14__0_carry_n_0),
.CO({add_temp_14__0_carry__0_n_0,add_temp_14__0_carry__0_n_1,add_temp_14__0_carry__0_n_2,add_temp_14__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__0_carry__0_i_1_n_0,add_temp_14__0_carry__0_i_2_n_0,add_temp_14__0_carry__0_i_3_n_0,add_temp_14__0_carry__0_i_4_n_0}),
.O({add_temp_14__0_carry__0_n_4,add_temp_14__0_carry__0_n_5,add_temp_14__0_carry__0_n_6,add_temp_14__0_carry__0_n_7}),
.S({add_temp_14__0_carry__0_i_5_n_0,add_temp_14__0_carry__0_i_6_n_0,add_temp_14__0_carry__0_i_7_n_0,add_temp_14__0_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair6" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__0_i_1
(.I0(RESIZE44[6]),
.I1(RESIZE15[6]),
.I2(RESIZE42[6]),
.O(add_temp_14__0_carry__0_i_1_n_0));
(* HLUTNM = "lutpair5" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__0_i_2
(.I0(RESIZE44[5]),
.I1(RESIZE15[5]),
.I2(RESIZE42[5]),
.O(add_temp_14__0_carry__0_i_2_n_0));
(* HLUTNM = "lutpair4" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__0_i_3
(.I0(RESIZE44[4]),
.I1(RESIZE15[4]),
.I2(RESIZE42[4]),
.O(add_temp_14__0_carry__0_i_3_n_0));
(* HLUTNM = "lutpair3" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__0_i_4
(.I0(RESIZE44[3]),
.I1(RESIZE15[3]),
.I2(RESIZE42[3]),
.O(add_temp_14__0_carry__0_i_4_n_0));
(* HLUTNM = "lutpair7" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__0_i_5
(.I0(RESIZE44[7]),
.I1(RESIZE15[7]),
.I2(RESIZE42[7]),
.I3(add_temp_14__0_carry__0_i_1_n_0),
.O(add_temp_14__0_carry__0_i_5_n_0));
(* HLUTNM = "lutpair6" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__0_i_6
(.I0(RESIZE44[6]),
.I1(RESIZE15[6]),
.I2(RESIZE42[6]),
.I3(add_temp_14__0_carry__0_i_2_n_0),
.O(add_temp_14__0_carry__0_i_6_n_0));
(* HLUTNM = "lutpair5" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__0_i_7
(.I0(RESIZE44[5]),
.I1(RESIZE15[5]),
.I2(RESIZE42[5]),
.I3(add_temp_14__0_carry__0_i_3_n_0),
.O(add_temp_14__0_carry__0_i_7_n_0));
(* HLUTNM = "lutpair4" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__0_i_8
(.I0(RESIZE44[4]),
.I1(RESIZE15[4]),
.I2(RESIZE42[4]),
.I3(add_temp_14__0_carry__0_i_4_n_0),
.O(add_temp_14__0_carry__0_i_8_n_0));
CARRY4 add_temp_14__0_carry__1
(.CI(add_temp_14__0_carry__0_n_0),
.CO({add_temp_14__0_carry__1_n_0,add_temp_14__0_carry__1_n_1,add_temp_14__0_carry__1_n_2,add_temp_14__0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__0_carry__1_i_1_n_0,add_temp_14__0_carry__1_i_2_n_0,add_temp_14__0_carry__1_i_3_n_0,add_temp_14__0_carry__1_i_4_n_0}),
.O({add_temp_14__0_carry__1_n_4,add_temp_14__0_carry__1_n_5,add_temp_14__0_carry__1_n_6,add_temp_14__0_carry__1_n_7}),
.S({add_temp_14__0_carry__1_i_5_n_0,add_temp_14__0_carry__1_i_6_n_0,add_temp_14__0_carry__1_i_7_n_0,add_temp_14__0_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair10" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__1_i_1
(.I0(RESIZE44[10]),
.I1(RESIZE42[10]),
.I2(RESIZE15[10]),
.O(add_temp_14__0_carry__1_i_1_n_0));
(* HLUTNM = "lutpair9" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__1_i_2
(.I0(RESIZE44[9]),
.I1(RESIZE42[9]),
.I2(RESIZE15[9]),
.O(add_temp_14__0_carry__1_i_2_n_0));
(* HLUTNM = "lutpair8" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__1_i_3
(.I0(RESIZE44[8]),
.I1(RESIZE15[8]),
.I2(RESIZE42[8]),
.O(add_temp_14__0_carry__1_i_3_n_0));
(* HLUTNM = "lutpair7" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__1_i_4
(.I0(RESIZE44[7]),
.I1(RESIZE15[7]),
.I2(RESIZE42[7]),
.O(add_temp_14__0_carry__1_i_4_n_0));
(* HLUTNM = "lutpair11" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__1_i_5
(.I0(RESIZE44[11]),
.I1(RESIZE15[11]),
.I2(RESIZE42[11]),
.I3(add_temp_14__0_carry__1_i_1_n_0),
.O(add_temp_14__0_carry__1_i_5_n_0));
(* HLUTNM = "lutpair10" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__1_i_6
(.I0(RESIZE44[10]),
.I1(RESIZE42[10]),
.I2(RESIZE15[10]),
.I3(add_temp_14__0_carry__1_i_2_n_0),
.O(add_temp_14__0_carry__1_i_6_n_0));
(* HLUTNM = "lutpair9" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__1_i_7
(.I0(RESIZE44[9]),
.I1(RESIZE42[9]),
.I2(RESIZE15[9]),
.I3(add_temp_14__0_carry__1_i_3_n_0),
.O(add_temp_14__0_carry__1_i_7_n_0));
(* HLUTNM = "lutpair8" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__1_i_8
(.I0(RESIZE44[8]),
.I1(RESIZE15[8]),
.I2(RESIZE42[8]),
.I3(add_temp_14__0_carry__1_i_4_n_0),
.O(add_temp_14__0_carry__1_i_8_n_0));
CARRY4 add_temp_14__0_carry__2
(.CI(add_temp_14__0_carry__1_n_0),
.CO({NLW_add_temp_14__0_carry__2_CO_UNCONNECTED[3],add_temp_14__0_carry__2_n_1,add_temp_14__0_carry__2_n_2,add_temp_14__0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,add_temp_14__0_carry__2_i_1_n_0,add_temp_14__0_carry__2_i_2_n_0,add_temp_14__0_carry__2_i_3_n_0}),
.O({add_temp_14__0_carry__2_n_4,add_temp_14__0_carry__2_n_5,add_temp_14__0_carry__2_n_6,add_temp_14__0_carry__2_n_7}),
.S({add_temp_14__0_carry__2_i_4_n_0,add_temp_14__0_carry__2_i_5_n_0,add_temp_14__0_carry__2_i_6_n_0,add_temp_14__0_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair13" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__2_i_1
(.I0(RESIZE15[13]),
.I1(RESIZE42[13]),
.I2(RESIZE44[13]),
.O(add_temp_14__0_carry__2_i_1_n_0));
(* HLUTNM = "lutpair12" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__2_i_2
(.I0(RESIZE44[12]),
.I1(RESIZE15[12]),
.I2(RESIZE42[12]),
.O(add_temp_14__0_carry__2_i_2_n_0));
(* HLUTNM = "lutpair11" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__2_i_3
(.I0(RESIZE44[11]),
.I1(RESIZE15[11]),
.I2(RESIZE42[11]),
.O(add_temp_14__0_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h17E8E817E81717E8))
add_temp_14__0_carry__2_i_4
(.I0(RESIZE15[14]),
.I1(RESIZE44[14]),
.I2(RESIZE42[14]),
.I3(RESIZE44[15]),
.I4(RESIZE42[15]),
.I5(RESIZE15[15]),
.O(add_temp_14__0_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__2_i_5
(.I0(add_temp_14__0_carry__2_i_1_n_0),
.I1(RESIZE44[14]),
.I2(RESIZE42[14]),
.I3(RESIZE15[14]),
.O(add_temp_14__0_carry__2_i_5_n_0));
(* HLUTNM = "lutpair13" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__2_i_6
(.I0(RESIZE15[13]),
.I1(RESIZE42[13]),
.I2(RESIZE44[13]),
.I3(add_temp_14__0_carry__2_i_2_n_0),
.O(add_temp_14__0_carry__2_i_6_n_0));
(* HLUTNM = "lutpair12" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__2_i_7
(.I0(RESIZE44[12]),
.I1(RESIZE15[12]),
.I2(RESIZE42[12]),
.I3(add_temp_14__0_carry__2_i_3_n_0),
.O(add_temp_14__0_carry__2_i_7_n_0));
(* HLUTNM = "lutpair2" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry_i_1
(.I0(RESIZE44[2]),
.I1(RESIZE15[2]),
.I2(RESIZE42[2]),
.O(add_temp_14__0_carry_i_1_n_0));
(* HLUTNM = "lutpair1" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry_i_2
(.I0(RESIZE44[1]),
.I1(RESIZE15[1]),
.I2(RESIZE42[1]),
.O(add_temp_14__0_carry_i_2_n_0));
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LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry_i_3
(.I0(RESIZE44[0]),
.I1(RESIZE15[0]),
.I2(RESIZE42[0]),
.O(add_temp_14__0_carry_i_3_n_0));
(* HLUTNM = "lutpair3" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry_i_4
(.I0(RESIZE44[3]),
.I1(RESIZE15[3]),
.I2(RESIZE42[3]),
.I3(add_temp_14__0_carry_i_1_n_0),
.O(add_temp_14__0_carry_i_4_n_0));
(* HLUTNM = "lutpair2" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry_i_5
(.I0(RESIZE44[2]),
.I1(RESIZE15[2]),
.I2(RESIZE42[2]),
.I3(add_temp_14__0_carry_i_2_n_0),
.O(add_temp_14__0_carry_i_5_n_0));
(* HLUTNM = "lutpair1" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry_i_6
(.I0(RESIZE44[1]),
.I1(RESIZE15[1]),
.I2(RESIZE42[1]),
.I3(add_temp_14__0_carry_i_3_n_0),
.O(add_temp_14__0_carry_i_6_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__0_carry_i_7
(.I0(RESIZE44[0]),
.I1(RESIZE15[0]),
.I2(RESIZE42[0]),
.O(add_temp_14__0_carry_i_7_n_0));
CARRY4 add_temp_14__138_carry
(.CI(1'b0),
.CO({add_temp_14__138_carry_n_0,add_temp_14__138_carry_n_1,add_temp_14__138_carry_n_2,add_temp_14__138_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__138_carry_i_1_n_0,add_temp_14__138_carry_i_2_n_0,add_temp_14__138_carry_i_3_n_0,1'b0}),
.O({add_temp_14__138_carry_n_4,add_temp_14__138_carry_n_5,add_temp_14__138_carry_n_6,add_temp_14__138_carry_n_7}),
.S({add_temp_14__138_carry_i_4_n_0,add_temp_14__138_carry_i_5_n_0,add_temp_14__138_carry_i_6_n_0,add_temp_14__138_carry_i_7_n_0}));
CARRY4 add_temp_14__138_carry__0
(.CI(add_temp_14__138_carry_n_0),
.CO({add_temp_14__138_carry__0_n_0,add_temp_14__138_carry__0_n_1,add_temp_14__138_carry__0_n_2,add_temp_14__138_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__138_carry__0_i_1_n_0,add_temp_14__138_carry__0_i_2_n_0,add_temp_14__138_carry__0_i_3_n_0,add_temp_14__138_carry__0_i_4_n_0}),
.O({add_temp_14__138_carry__0_n_4,add_temp_14__138_carry__0_n_5,add_temp_14__138_carry__0_n_6,add_temp_14__138_carry__0_n_7}),
.S({add_temp_14__138_carry__0_i_5_n_0,add_temp_14__138_carry__0_i_6_n_0,add_temp_14__138_carry__0_i_7_n_0,add_temp_14__138_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair48" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__0_i_1
(.I0(RESIZE24[6]),
.I1(RESIZE26[6]),
.I2(RESIZE28[6]),
.O(add_temp_14__138_carry__0_i_1_n_0));
(* HLUTNM = "lutpair47" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__0_i_2
(.I0(RESIZE28[5]),
.I1(RESIZE24[5]),
.I2(RESIZE26[5]),
.O(add_temp_14__138_carry__0_i_2_n_0));
(* HLUTNM = "lutpair46" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__0_i_3
(.I0(RESIZE26[4]),
.I1(RESIZE24[4]),
.I2(RESIZE28[4]),
.O(add_temp_14__138_carry__0_i_3_n_0));
(* HLUTNM = "lutpair45" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__0_i_4
(.I0(RESIZE26[3]),
.I1(RESIZE28[3]),
.I2(RESIZE24[3]),
.O(add_temp_14__138_carry__0_i_4_n_0));
(* HLUTNM = "lutpair49" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__0_i_5
(.I0(RESIZE24[7]),
.I1(RESIZE26[7]),
.I2(RESIZE28[7]),
.I3(add_temp_14__138_carry__0_i_1_n_0),
.O(add_temp_14__138_carry__0_i_5_n_0));
(* HLUTNM = "lutpair48" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__0_i_6
(.I0(RESIZE24[6]),
.I1(RESIZE26[6]),
.I2(RESIZE28[6]),
.I3(add_temp_14__138_carry__0_i_2_n_0),
.O(add_temp_14__138_carry__0_i_6_n_0));
(* HLUTNM = "lutpair47" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__0_i_7
(.I0(RESIZE28[5]),
.I1(RESIZE24[5]),
.I2(RESIZE26[5]),
.I3(add_temp_14__138_carry__0_i_3_n_0),
.O(add_temp_14__138_carry__0_i_7_n_0));
(* HLUTNM = "lutpair46" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__0_i_8
(.I0(RESIZE26[4]),
.I1(RESIZE24[4]),
.I2(RESIZE28[4]),
.I3(add_temp_14__138_carry__0_i_4_n_0),
.O(add_temp_14__138_carry__0_i_8_n_0));
CARRY4 add_temp_14__138_carry__1
(.CI(add_temp_14__138_carry__0_n_0),
.CO({add_temp_14__138_carry__1_n_0,add_temp_14__138_carry__1_n_1,add_temp_14__138_carry__1_n_2,add_temp_14__138_carry__1_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__138_carry__1_i_1_n_0,add_temp_14__138_carry__1_i_2_n_0,add_temp_14__138_carry__1_i_3_n_0,add_temp_14__138_carry__1_i_4_n_0}),
.O({add_temp_14__138_carry__1_n_4,add_temp_14__138_carry__1_n_5,add_temp_14__138_carry__1_n_6,add_temp_14__138_carry__1_n_7}),
.S({add_temp_14__138_carry__1_i_5_n_0,add_temp_14__138_carry__1_i_6_n_0,add_temp_14__138_carry__1_i_7_n_0,add_temp_14__138_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair52" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__1_i_1
(.I0(RESIZE24[10]),
.I1(RESIZE26[10]),
.I2(RESIZE28[10]),
.O(add_temp_14__138_carry__1_i_1_n_0));
(* HLUTNM = "lutpair51" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__1_i_2
(.I0(RESIZE24[9]),
.I1(RESIZE26[9]),
.I2(RESIZE28[9]),
.O(add_temp_14__138_carry__1_i_2_n_0));
(* HLUTNM = "lutpair50" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__1_i_3
(.I0(RESIZE24[8]),
.I1(RESIZE26[8]),
.I2(RESIZE28[8]),
.O(add_temp_14__138_carry__1_i_3_n_0));
(* HLUTNM = "lutpair49" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__1_i_4
(.I0(RESIZE24[7]),
.I1(RESIZE26[7]),
.I2(RESIZE28[7]),
.O(add_temp_14__138_carry__1_i_4_n_0));
(* HLUTNM = "lutpair53" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__1_i_5
(.I0(RESIZE24[11]),
.I1(RESIZE26[11]),
.I2(RESIZE28[11]),
.I3(add_temp_14__138_carry__1_i_1_n_0),
.O(add_temp_14__138_carry__1_i_5_n_0));
(* HLUTNM = "lutpair52" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__1_i_6
(.I0(RESIZE24[10]),
.I1(RESIZE26[10]),
.I2(RESIZE28[10]),
.I3(add_temp_14__138_carry__1_i_2_n_0),
.O(add_temp_14__138_carry__1_i_6_n_0));
(* HLUTNM = "lutpair51" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__1_i_7
(.I0(RESIZE24[9]),
.I1(RESIZE26[9]),
.I2(RESIZE28[9]),
.I3(add_temp_14__138_carry__1_i_3_n_0),
.O(add_temp_14__138_carry__1_i_7_n_0));
(* HLUTNM = "lutpair50" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__1_i_8
(.I0(RESIZE24[8]),
.I1(RESIZE26[8]),
.I2(RESIZE28[8]),
.I3(add_temp_14__138_carry__1_i_4_n_0),
.O(add_temp_14__138_carry__1_i_8_n_0));
CARRY4 add_temp_14__138_carry__2
(.CI(add_temp_14__138_carry__1_n_0),
.CO({NLW_add_temp_14__138_carry__2_CO_UNCONNECTED[3],add_temp_14__138_carry__2_n_1,add_temp_14__138_carry__2_n_2,add_temp_14__138_carry__2_n_3}),
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.O({add_temp_14__138_carry__2_n_4,add_temp_14__138_carry__2_n_5,add_temp_14__138_carry__2_n_6,add_temp_14__138_carry__2_n_7}),
.S({add_temp_14__138_carry__2_i_4_n_0,add_temp_14__138_carry__2_i_5_n_0,add_temp_14__138_carry__2_i_6_n_0,add_temp_14__138_carry__2_i_7_n_0}));
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LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__2_i_1
(.I0(RESIZE24[13]),
.I1(RESIZE26[13]),
.I2(RESIZE28[13]),
.O(add_temp_14__138_carry__2_i_1_n_0));
(* HLUTNM = "lutpair54" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__2_i_2
(.I0(RESIZE24[12]),
.I1(RESIZE26[12]),
.I2(RESIZE28[12]),
.O(add_temp_14__138_carry__2_i_2_n_0));
(* HLUTNM = "lutpair53" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__2_i_3
(.I0(RESIZE24[11]),
.I1(RESIZE26[11]),
.I2(RESIZE28[11]),
.O(add_temp_14__138_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h17E8E817E81717E8))
add_temp_14__138_carry__2_i_4
(.I0(RESIZE28[14]),
.I1(RESIZE26[14]),
.I2(RESIZE24[14]),
.I3(RESIZE26[15]),
.I4(RESIZE24[15]),
.I5(RESIZE28[15]),
.O(add_temp_14__138_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__2_i_5
(.I0(add_temp_14__138_carry__2_i_1_n_0),
.I1(RESIZE26[14]),
.I2(RESIZE24[14]),
.I3(RESIZE28[14]),
.O(add_temp_14__138_carry__2_i_5_n_0));
(* HLUTNM = "lutpair55" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__2_i_6
(.I0(RESIZE24[13]),
.I1(RESIZE26[13]),
.I2(RESIZE28[13]),
.I3(add_temp_14__138_carry__2_i_2_n_0),
.O(add_temp_14__138_carry__2_i_6_n_0));
(* HLUTNM = "lutpair54" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__2_i_7
(.I0(RESIZE24[12]),
.I1(RESIZE26[12]),
.I2(RESIZE28[12]),
.I3(add_temp_14__138_carry__2_i_3_n_0),
.O(add_temp_14__138_carry__2_i_7_n_0));
(* HLUTNM = "lutpair44" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry_i_1
(.I0(RESIZE26[2]),
.I1(RESIZE28[2]),
.I2(RESIZE24[2]),
.O(add_temp_14__138_carry_i_1_n_0));
(* HLUTNM = "lutpair43" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry_i_2
(.I0(RESIZE26[1]),
.I1(RESIZE28[1]),
.I2(RESIZE24[1]),
.O(add_temp_14__138_carry_i_2_n_0));
(* HLUTNM = "lutpair42" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry_i_3
(.I0(RESIZE26[0]),
.I1(RESIZE28[0]),
.I2(RESIZE24[0]),
.O(add_temp_14__138_carry_i_3_n_0));
(* HLUTNM = "lutpair45" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry_i_4
(.I0(RESIZE26[3]),
.I1(RESIZE28[3]),
.I2(RESIZE24[3]),
.I3(add_temp_14__138_carry_i_1_n_0),
.O(add_temp_14__138_carry_i_4_n_0));
(* HLUTNM = "lutpair44" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry_i_5
(.I0(RESIZE26[2]),
.I1(RESIZE28[2]),
.I2(RESIZE24[2]),
.I3(add_temp_14__138_carry_i_2_n_0),
.O(add_temp_14__138_carry_i_5_n_0));
(* HLUTNM = "lutpair43" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry_i_6
(.I0(RESIZE26[1]),
.I1(RESIZE28[1]),
.I2(RESIZE24[1]),
.I3(add_temp_14__138_carry_i_3_n_0),
.O(add_temp_14__138_carry_i_6_n_0));
(* HLUTNM = "lutpair42" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__138_carry_i_7
(.I0(RESIZE26[0]),
.I1(RESIZE28[0]),
.I2(RESIZE24[0]),
.O(add_temp_14__138_carry_i_7_n_0));
CARRY4 add_temp_14__184_carry
(.CI(1'b0),
.CO({add_temp_14__184_carry_n_0,add_temp_14__184_carry_n_1,add_temp_14__184_carry_n_2,add_temp_14__184_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__184_carry_i_1_n_0,add_temp_14__184_carry_i_2_n_0,add_temp_14__184_carry_i_3_n_0,1'b0}),
.O({add_temp_14__184_carry_n_4,add_temp_14__184_carry_n_5,add_temp_14__184_carry_n_6,add_temp_14__184_carry_n_7}),
.S({add_temp_14__184_carry_i_4_n_0,add_temp_14__184_carry_i_5_n_0,add_temp_14__184_carry_i_6_n_0,add_temp_14__184_carry_i_7_n_0}));
CARRY4 add_temp_14__184_carry__0
(.CI(add_temp_14__184_carry_n_0),
.CO({add_temp_14__184_carry__0_n_0,add_temp_14__184_carry__0_n_1,add_temp_14__184_carry__0_n_2,add_temp_14__184_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__184_carry__0_i_1_n_0,add_temp_14__184_carry__0_i_2_n_0,add_temp_14__184_carry__0_i_3_n_0,add_temp_14__184_carry__0_i_4_n_0}),
.O({add_temp_14__184_carry__0_n_4,add_temp_14__184_carry__0_n_5,add_temp_14__184_carry__0_n_6,add_temp_14__184_carry__0_n_7}),
.S({add_temp_14__184_carry__0_i_5_n_0,add_temp_14__184_carry__0_i_6_n_0,add_temp_14__184_carry__0_i_7_n_0,add_temp_14__184_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair62" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__0_i_1
(.I0(RESIZE20[6]),
.I1(RESIZE18[6]),
.I2(RESIZE22[6]),
.O(add_temp_14__184_carry__0_i_1_n_0));
(* HLUTNM = "lutpair61" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__0_i_2
(.I0(RESIZE20[5]),
.I1(RESIZE18[5]),
.I2(RESIZE22[5]),
.O(add_temp_14__184_carry__0_i_2_n_0));
(* HLUTNM = "lutpair60" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__0_i_3
(.I0(RESIZE20[4]),
.I1(RESIZE18[4]),
.I2(RESIZE22[4]),
.O(add_temp_14__184_carry__0_i_3_n_0));
(* HLUTNM = "lutpair59" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__0_i_4
(.I0(RESIZE18[3]),
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.I2(RESIZE20[3]),
.O(add_temp_14__184_carry__0_i_4_n_0));
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LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__0_i_5
(.I0(RESIZE20[7]),
.I1(RESIZE18[7]),
.I2(RESIZE22[7]),
.I3(add_temp_14__184_carry__0_i_1_n_0),
.O(add_temp_14__184_carry__0_i_5_n_0));
(* HLUTNM = "lutpair62" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__0_i_6
(.I0(RESIZE20[6]),
.I1(RESIZE18[6]),
.I2(RESIZE22[6]),
.I3(add_temp_14__184_carry__0_i_2_n_0),
.O(add_temp_14__184_carry__0_i_6_n_0));
(* HLUTNM = "lutpair61" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__0_i_7
(.I0(RESIZE20[5]),
.I1(RESIZE18[5]),
.I2(RESIZE22[5]),
.I3(add_temp_14__184_carry__0_i_3_n_0),
.O(add_temp_14__184_carry__0_i_7_n_0));
(* HLUTNM = "lutpair60" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__0_i_8
(.I0(RESIZE20[4]),
.I1(RESIZE18[4]),
.I2(RESIZE22[4]),
.I3(add_temp_14__184_carry__0_i_4_n_0),
.O(add_temp_14__184_carry__0_i_8_n_0));
CARRY4 add_temp_14__184_carry__1
(.CI(add_temp_14__184_carry__0_n_0),
.CO({add_temp_14__184_carry__1_n_0,add_temp_14__184_carry__1_n_1,add_temp_14__184_carry__1_n_2,add_temp_14__184_carry__1_n_3}),
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.S({add_temp_14__184_carry__1_i_5_n_0,add_temp_14__184_carry__1_i_6_n_0,add_temp_14__184_carry__1_i_7_n_0,add_temp_14__184_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair66" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__1_i_1
(.I0(RESIZE18[10]),
.I1(RESIZE22[10]),
.I2(RESIZE20[10]),
.O(add_temp_14__184_carry__1_i_1_n_0));
(* HLUTNM = "lutpair65" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__1_i_2
(.I0(RESIZE18[9]),
.I1(RESIZE22[9]),
.I2(RESIZE20[9]),
.O(add_temp_14__184_carry__1_i_2_n_0));
(* HLUTNM = "lutpair64" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__1_i_3
(.I0(RESIZE18[8]),
.I1(RESIZE22[8]),
.I2(RESIZE20[8]),
.O(add_temp_14__184_carry__1_i_3_n_0));
(* HLUTNM = "lutpair63" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__1_i_4
(.I0(RESIZE20[7]),
.I1(RESIZE18[7]),
.I2(RESIZE22[7]),
.O(add_temp_14__184_carry__1_i_4_n_0));
(* HLUTNM = "lutpair67" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__1_i_5
(.I0(RESIZE18[11]),
.I1(RESIZE22[11]),
.I2(RESIZE20[11]),
.I3(add_temp_14__184_carry__1_i_1_n_0),
.O(add_temp_14__184_carry__1_i_5_n_0));
(* HLUTNM = "lutpair66" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__1_i_6
(.I0(RESIZE18[10]),
.I1(RESIZE22[10]),
.I2(RESIZE20[10]),
.I3(add_temp_14__184_carry__1_i_2_n_0),
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(* HLUTNM = "lutpair65" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__1_i_7
(.I0(RESIZE18[9]),
.I1(RESIZE22[9]),
.I2(RESIZE20[9]),
.I3(add_temp_14__184_carry__1_i_3_n_0),
.O(add_temp_14__184_carry__1_i_7_n_0));
(* HLUTNM = "lutpair64" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__1_i_8
(.I0(RESIZE18[8]),
.I1(RESIZE22[8]),
.I2(RESIZE20[8]),
.I3(add_temp_14__184_carry__1_i_4_n_0),
.O(add_temp_14__184_carry__1_i_8_n_0));
CARRY4 add_temp_14__184_carry__2
(.CI(add_temp_14__184_carry__1_n_0),
.CO({NLW_add_temp_14__184_carry__2_CO_UNCONNECTED[3],add_temp_14__184_carry__2_n_1,add_temp_14__184_carry__2_n_2,add_temp_14__184_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,add_temp_14__184_carry__2_i_1_n_0,add_temp_14__184_carry__2_i_2_n_0,add_temp_14__184_carry__2_i_3_n_0}),
.O({add_temp_14__184_carry__2_n_4,add_temp_14__184_carry__2_n_5,add_temp_14__184_carry__2_n_6,add_temp_14__184_carry__2_n_7}),
.S({add_temp_14__184_carry__2_i_4_n_0,add_temp_14__184_carry__2_i_5_n_0,add_temp_14__184_carry__2_i_6_n_0,add_temp_14__184_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair69" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__2_i_1
(.I0(RESIZE18[13]),
.I1(RESIZE22[13]),
.I2(RESIZE20[13]),
.O(add_temp_14__184_carry__2_i_1_n_0));
(* HLUTNM = "lutpair68" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__2_i_2
(.I0(RESIZE18[12]),
.I1(RESIZE22[12]),
.I2(RESIZE20[12]),
.O(add_temp_14__184_carry__2_i_2_n_0));
(* HLUTNM = "lutpair67" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__2_i_3
(.I0(RESIZE18[11]),
.I1(RESIZE22[11]),
.I2(RESIZE20[11]),
.O(add_temp_14__184_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h17E8E817E81717E8))
add_temp_14__184_carry__2_i_4
(.I0(RESIZE20[14]),
.I1(RESIZE22[14]),
.I2(RESIZE18[14]),
.I3(RESIZE20[15]),
.I4(RESIZE18[15]),
.I5(RESIZE22[15]),
.O(add_temp_14__184_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__2_i_5
(.I0(add_temp_14__184_carry__2_i_1_n_0),
.I1(RESIZE20[14]),
.I2(RESIZE18[14]),
.I3(RESIZE22[14]),
.O(add_temp_14__184_carry__2_i_5_n_0));
(* HLUTNM = "lutpair69" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__2_i_6
(.I0(RESIZE18[13]),
.I1(RESIZE22[13]),
.I2(RESIZE20[13]),
.I3(add_temp_14__184_carry__2_i_2_n_0),
.O(add_temp_14__184_carry__2_i_6_n_0));
(* HLUTNM = "lutpair68" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__2_i_7
(.I0(RESIZE18[12]),
.I1(RESIZE22[12]),
.I2(RESIZE20[12]),
.I3(add_temp_14__184_carry__2_i_3_n_0),
.O(add_temp_14__184_carry__2_i_7_n_0));
(* HLUTNM = "lutpair58" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry_i_1
(.I0(RESIZE22[2]),
.I1(RESIZE18[2]),
.I2(RESIZE20[2]),
.O(add_temp_14__184_carry_i_1_n_0));
(* HLUTNM = "lutpair57" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry_i_2
(.I0(RESIZE20[1]),
.I1(RESIZE18[1]),
.I2(RESIZE22[1]),
.O(add_temp_14__184_carry_i_2_n_0));
(* HLUTNM = "lutpair56" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry_i_3
(.I0(RESIZE18[0]),
.I1(RESIZE22[0]),
.I2(RESIZE20[0]),
.O(add_temp_14__184_carry_i_3_n_0));
(* HLUTNM = "lutpair59" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry_i_4
(.I0(RESIZE18[3]),
.I1(RESIZE22[3]),
.I2(RESIZE20[3]),
.I3(add_temp_14__184_carry_i_1_n_0),
.O(add_temp_14__184_carry_i_4_n_0));
(* HLUTNM = "lutpair58" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry_i_5
(.I0(RESIZE22[2]),
.I1(RESIZE18[2]),
.I2(RESIZE20[2]),
.I3(add_temp_14__184_carry_i_2_n_0),
.O(add_temp_14__184_carry_i_5_n_0));
(* HLUTNM = "lutpair57" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry_i_6
(.I0(RESIZE20[1]),
.I1(RESIZE18[1]),
.I2(RESIZE22[1]),
.I3(add_temp_14__184_carry_i_3_n_0),
.O(add_temp_14__184_carry_i_6_n_0));
(* HLUTNM = "lutpair56" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__184_carry_i_7
(.I0(RESIZE18[0]),
.I1(RESIZE22[0]),
.I2(RESIZE20[0]),
.O(add_temp_14__184_carry_i_7_n_0));
CARRY4 add_temp_14__230_carry
(.CI(1'b0),
.CO({add_temp_14__230_carry_n_0,add_temp_14__230_carry_n_1,add_temp_14__230_carry_n_2,add_temp_14__230_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__230_carry_i_1_n_0,add_temp_14__230_carry_i_2_n_0,add_temp_14__230_carry_i_3_n_0,1'b0}),
.O({add_temp_14__230_carry_n_4,add_temp_14__230_carry_n_5,add_temp_14__230_carry_n_6,add_temp_14__230_carry_n_7}),
.S({add_temp_14__230_carry_i_4_n_0,add_temp_14__230_carry_i_5_n_0,add_temp_14__230_carry_i_6_n_0,add_temp_14__230_carry_i_7_n_0}));
CARRY4 add_temp_14__230_carry__0
(.CI(add_temp_14__230_carry_n_0),
.CO({add_temp_14__230_carry__0_n_0,add_temp_14__230_carry__0_n_1,add_temp_14__230_carry__0_n_2,add_temp_14__230_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__230_carry__0_i_1_n_0,add_temp_14__230_carry__0_i_2_n_0,add_temp_14__230_carry__0_i_3_n_0,add_temp_14__230_carry__0_i_4_n_0}),
.O({add_temp_14__230_carry__0_n_4,add_temp_14__230_carry__0_n_5,add_temp_14__230_carry__0_n_6,add_temp_14__230_carry__0_n_7}),
.S({add_temp_14__230_carry__0_i_5_n_0,add_temp_14__230_carry__0_i_6_n_0,add_temp_14__230_carry__0_i_7_n_0,add_temp_14__230_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair76" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__0_i_1
(.I0(RESIZE16[6]),
.I1(add_temp_14__0_carry__0_n_5),
.I2(add_temp_14__46_carry__0_n_5),
.O(add_temp_14__230_carry__0_i_1_n_0));
(* HLUTNM = "lutpair75" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__0_i_2
(.I0(RESIZE16[5]),
.I1(add_temp_14__46_carry__0_n_6),
.I2(add_temp_14__0_carry__0_n_6),
.O(add_temp_14__230_carry__0_i_2_n_0));
(* HLUTNM = "lutpair74" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__0_i_3
(.I0(add_temp_14__0_carry__0_n_7),
.I1(add_temp_14__46_carry__0_n_7),
.I2(RESIZE16[4]),
.O(add_temp_14__230_carry__0_i_3_n_0));
(* HLUTNM = "lutpair73" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__0_i_4
(.I0(add_temp_14__0_carry_n_4),
.I1(add_temp_14__46_carry_n_4),
.I2(RESIZE16[3]),
.O(add_temp_14__230_carry__0_i_4_n_0));
(* HLUTNM = "lutpair77" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__0_i_5
(.I0(add_temp_14__0_carry__0_n_4),
.I1(add_temp_14__46_carry__0_n_4),
.I2(RESIZE16[7]),
.I3(add_temp_14__230_carry__0_i_1_n_0),
.O(add_temp_14__230_carry__0_i_5_n_0));
(* HLUTNM = "lutpair76" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__0_i_6
(.I0(RESIZE16[6]),
.I1(add_temp_14__0_carry__0_n_5),
.I2(add_temp_14__46_carry__0_n_5),
.I3(add_temp_14__230_carry__0_i_2_n_0),
.O(add_temp_14__230_carry__0_i_6_n_0));
(* HLUTNM = "lutpair75" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__0_i_7
(.I0(RESIZE16[5]),
.I1(add_temp_14__46_carry__0_n_6),
.I2(add_temp_14__0_carry__0_n_6),
.I3(add_temp_14__230_carry__0_i_3_n_0),
.O(add_temp_14__230_carry__0_i_7_n_0));
(* HLUTNM = "lutpair74" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__0_i_8
(.I0(add_temp_14__0_carry__0_n_7),
.I1(add_temp_14__46_carry__0_n_7),
.I2(RESIZE16[4]),
.I3(add_temp_14__230_carry__0_i_4_n_0),
.O(add_temp_14__230_carry__0_i_8_n_0));
CARRY4 add_temp_14__230_carry__1
(.CI(add_temp_14__230_carry__0_n_0),
.CO({add_temp_14__230_carry__1_n_0,add_temp_14__230_carry__1_n_1,add_temp_14__230_carry__1_n_2,add_temp_14__230_carry__1_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__230_carry__1_i_1_n_0,add_temp_14__230_carry__1_i_2_n_0,add_temp_14__230_carry__1_i_3_n_0,add_temp_14__230_carry__1_i_4_n_0}),
.O({add_temp_14__230_carry__1_n_4,add_temp_14__230_carry__1_n_5,add_temp_14__230_carry__1_n_6,add_temp_14__230_carry__1_n_7}),
.S({add_temp_14__230_carry__1_i_5_n_0,add_temp_14__230_carry__1_i_6_n_0,add_temp_14__230_carry__1_i_7_n_0,add_temp_14__230_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair80" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__1_i_1
(.I0(RESIZE16[10]),
.I1(add_temp_14__0_carry__1_n_5),
.I2(add_temp_14__46_carry__1_n_5),
.O(add_temp_14__230_carry__1_i_1_n_0));
(* HLUTNM = "lutpair79" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__1_i_2
(.I0(add_temp_14__0_carry__1_n_6),
.I1(add_temp_14__46_carry__1_n_6),
.I2(RESIZE16[9]),
.O(add_temp_14__230_carry__1_i_2_n_0));
(* HLUTNM = "lutpair78" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__1_i_3
(.I0(add_temp_14__0_carry__1_n_7),
.I1(RESIZE16[8]),
.I2(add_temp_14__46_carry__1_n_7),
.O(add_temp_14__230_carry__1_i_3_n_0));
(* HLUTNM = "lutpair77" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__1_i_4
(.I0(add_temp_14__0_carry__0_n_4),
.I1(add_temp_14__46_carry__0_n_4),
.I2(RESIZE16[7]),
.O(add_temp_14__230_carry__1_i_4_n_0));
(* HLUTNM = "lutpair81" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__1_i_5
(.I0(RESIZE16[11]),
.I1(add_temp_14__0_carry__1_n_4),
.I2(add_temp_14__46_carry__1_n_4),
.I3(add_temp_14__230_carry__1_i_1_n_0),
.O(add_temp_14__230_carry__1_i_5_n_0));
(* HLUTNM = "lutpair80" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__1_i_6
(.I0(RESIZE16[10]),
.I1(add_temp_14__0_carry__1_n_5),
.I2(add_temp_14__46_carry__1_n_5),
.I3(add_temp_14__230_carry__1_i_2_n_0),
.O(add_temp_14__230_carry__1_i_6_n_0));
(* HLUTNM = "lutpair79" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__1_i_7
(.I0(add_temp_14__0_carry__1_n_6),
.I1(add_temp_14__46_carry__1_n_6),
.I2(RESIZE16[9]),
.I3(add_temp_14__230_carry__1_i_3_n_0),
.O(add_temp_14__230_carry__1_i_7_n_0));
(* HLUTNM = "lutpair78" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__1_i_8
(.I0(add_temp_14__0_carry__1_n_7),
.I1(RESIZE16[8]),
.I2(add_temp_14__46_carry__1_n_7),
.I3(add_temp_14__230_carry__1_i_4_n_0),
.O(add_temp_14__230_carry__1_i_8_n_0));
CARRY4 add_temp_14__230_carry__2
(.CI(add_temp_14__230_carry__1_n_0),
.CO({NLW_add_temp_14__230_carry__2_CO_UNCONNECTED[3],add_temp_14__230_carry__2_n_1,add_temp_14__230_carry__2_n_2,add_temp_14__230_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,add_temp_14__230_carry__2_i_1_n_0,add_temp_14__230_carry__2_i_2_n_0,add_temp_14__230_carry__2_i_3_n_0}),
.O({add_temp_14__230_carry__2_n_4,add_temp_14__230_carry__2_n_5,add_temp_14__230_carry__2_n_6,add_temp_14__230_carry__2_n_7}),
.S({add_temp_14__230_carry__2_i_4_n_0,add_temp_14__230_carry__2_i_5_n_0,add_temp_14__230_carry__2_i_6_n_0,add_temp_14__230_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair83" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__2_i_1
(.I0(RESIZE16[13]),
.I1(add_temp_14__0_carry__2_n_6),
.I2(add_temp_14__46_carry__2_n_6),
.O(add_temp_14__230_carry__2_i_1_n_0));
(* HLUTNM = "lutpair82" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__2_i_2
(.I0(RESIZE16[12]),
.I1(add_temp_14__0_carry__2_n_7),
.I2(add_temp_14__46_carry__2_n_7),
.O(add_temp_14__230_carry__2_i_2_n_0));
(* HLUTNM = "lutpair81" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__2_i_3
(.I0(RESIZE16[11]),
.I1(add_temp_14__0_carry__1_n_4),
.I2(add_temp_14__46_carry__1_n_4),
.O(add_temp_14__230_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h17E8E817E81717E8))
add_temp_14__230_carry__2_i_4
(.I0(add_temp_14__46_carry__2_n_5),
.I1(add_temp_14__0_carry__2_n_5),
.I2(RESIZE16[14]),
.I3(add_temp_14__0_carry__2_n_4),
.I4(add_temp_14__46_carry__2_n_4),
.I5(RESIZE16[15]),
.O(add_temp_14__230_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__2_i_5
(.I0(add_temp_14__230_carry__2_i_1_n_0),
.I1(add_temp_14__0_carry__2_n_5),
.I2(add_temp_14__46_carry__2_n_5),
.I3(RESIZE16[14]),
.O(add_temp_14__230_carry__2_i_5_n_0));
(* HLUTNM = "lutpair83" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__2_i_6
(.I0(RESIZE16[13]),
.I1(add_temp_14__0_carry__2_n_6),
.I2(add_temp_14__46_carry__2_n_6),
.I3(add_temp_14__230_carry__2_i_2_n_0),
.O(add_temp_14__230_carry__2_i_6_n_0));
(* HLUTNM = "lutpair82" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__2_i_7
(.I0(RESIZE16[12]),
.I1(add_temp_14__0_carry__2_n_7),
.I2(add_temp_14__46_carry__2_n_7),
.I3(add_temp_14__230_carry__2_i_3_n_0),
.O(add_temp_14__230_carry__2_i_7_n_0));
(* HLUTNM = "lutpair72" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry_i_1
(.I0(add_temp_14__46_carry_n_5),
.I1(add_temp_14__0_carry_n_5),
.I2(RESIZE16[2]),
.O(add_temp_14__230_carry_i_1_n_0));
(* HLUTNM = "lutpair71" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry_i_2
(.I0(add_temp_14__0_carry_n_6),
.I1(RESIZE16[1]),
.I2(add_temp_14__46_carry_n_6),
.O(add_temp_14__230_carry_i_2_n_0));
(* HLUTNM = "lutpair70" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry_i_3
(.I0(add_temp_14__46_carry_n_7),
.I1(add_temp_14__0_carry_n_7),
.I2(RESIZE16[0]),
.O(add_temp_14__230_carry_i_3_n_0));
(* HLUTNM = "lutpair73" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry_i_4
(.I0(add_temp_14__0_carry_n_4),
.I1(add_temp_14__46_carry_n_4),
.I2(RESIZE16[3]),
.I3(add_temp_14__230_carry_i_1_n_0),
.O(add_temp_14__230_carry_i_4_n_0));
(* HLUTNM = "lutpair72" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry_i_5
(.I0(add_temp_14__46_carry_n_5),
.I1(add_temp_14__0_carry_n_5),
.I2(RESIZE16[2]),
.I3(add_temp_14__230_carry_i_2_n_0),
.O(add_temp_14__230_carry_i_5_n_0));
(* HLUTNM = "lutpair71" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry_i_6
(.I0(add_temp_14__0_carry_n_6),
.I1(RESIZE16[1]),
.I2(add_temp_14__46_carry_n_6),
.I3(add_temp_14__230_carry_i_3_n_0),
.O(add_temp_14__230_carry_i_6_n_0));
(* HLUTNM = "lutpair70" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__230_carry_i_7
(.I0(add_temp_14__46_carry_n_7),
.I1(add_temp_14__0_carry_n_7),
.I2(RESIZE16[0]),
.O(add_temp_14__230_carry_i_7_n_0));
CARRY4 add_temp_14__278_carry
(.CI(1'b0),
.CO({add_temp_14__278_carry_n_0,add_temp_14__278_carry_n_1,add_temp_14__278_carry_n_2,add_temp_14__278_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__278_carry_i_1_n_0,add_temp_14__278_carry_i_2_n_0,add_temp_14__278_carry_i_3_n_0,add_temp_14__92_carry_n_7}),
.O(filter_sum[3:0]),
.S({add_temp_14__278_carry_i_4_n_0,add_temp_14__278_carry_i_5_n_0,add_temp_14__278_carry_i_6_n_0,add_temp_14__278_carry_i_7_n_0}));
CARRY4 add_temp_14__278_carry__0
(.CI(add_temp_14__278_carry_n_0),
.CO({add_temp_14__278_carry__0_n_0,add_temp_14__278_carry__0_n_1,add_temp_14__278_carry__0_n_2,add_temp_14__278_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__278_carry__0_i_1_n_0,add_temp_14__278_carry__0_i_2_n_0,add_temp_14__278_carry__0_i_3_n_0,add_temp_14__278_carry__0_i_4_n_0}),
.O(filter_sum[7:4]),
.S({add_temp_14__278_carry__0_i_5_n_0,add_temp_14__278_carry__0_i_6_n_0,add_temp_14__278_carry__0_i_7_n_0,add_temp_14__278_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__0_i_1
(.I0(add_temp_14__138_carry__0_n_5),
.I1(add_temp_14__230_carry__0_n_5),
.I2(add_temp_14__184_carry__0_n_5),
.I3(add_temp_14__278_carry__0_i_9_n_0),
.I4(add_temp_14__92_carry__0_n_5),
.O(add_temp_14__278_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__0_i_10
(.I0(add_temp_14__230_carry__0_n_7),
.I1(add_temp_14__184_carry__0_n_7),
.I2(add_temp_14__138_carry__0_n_7),
.O(add_temp_14__278_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__0_i_11
(.I0(add_temp_14__230_carry_n_4),
.I1(add_temp_14__184_carry_n_4),
.I2(add_temp_14__138_carry_n_4),
.O(add_temp_14__278_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
add_temp_14__278_carry__0_i_12
(.I0(add_temp_14__138_carry__0_n_4),
.I1(add_temp_14__230_carry__0_n_4),
.I2(add_temp_14__184_carry__0_n_4),
.O(add_temp_14__278_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__0_i_2
(.I0(add_temp_14__138_carry__0_n_6),
.I1(add_temp_14__230_carry__0_n_6),
.I2(add_temp_14__184_carry__0_n_6),
.I3(add_temp_14__278_carry__0_i_10_n_0),
.I4(add_temp_14__92_carry__0_n_6),
.O(add_temp_14__278_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__0_i_3
(.I0(add_temp_14__138_carry__0_n_7),
.I1(add_temp_14__230_carry__0_n_7),
.I2(add_temp_14__184_carry__0_n_7),
.I3(add_temp_14__278_carry__0_i_11_n_0),
.I4(add_temp_14__92_carry__0_n_7),
.O(add_temp_14__278_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__0_i_4
(.I0(add_temp_14__138_carry_n_4),
.I1(add_temp_14__230_carry_n_4),
.I2(add_temp_14__184_carry_n_4),
.I3(add_temp_14__278_carry_i_9_n_0),
.I4(add_temp_14__92_carry_n_4),
.O(add_temp_14__278_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h6969699669969696))
add_temp_14__278_carry__0_i_5
(.I0(add_temp_14__278_carry__0_i_1_n_0),
.I1(add_temp_14__278_carry__0_i_12_n_0),
.I2(add_temp_14__92_carry__0_n_4),
.I3(add_temp_14__138_carry__0_n_5),
.I4(add_temp_14__184_carry__0_n_5),
.I5(add_temp_14__230_carry__0_n_5),
.O(add_temp_14__278_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__0_i_6
(.I0(add_temp_14__278_carry__0_i_2_n_0),
.I1(add_temp_14__184_carry__0_n_5),
.I2(add_temp_14__230_carry__0_n_5),
.I3(add_temp_14__138_carry__0_n_5),
.I4(add_temp_14__92_carry__0_n_5),
.I5(add_temp_14__278_carry__0_i_9_n_0),
.O(add_temp_14__278_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__0_i_7
(.I0(add_temp_14__278_carry__0_i_3_n_0),
.I1(add_temp_14__184_carry__0_n_6),
.I2(add_temp_14__230_carry__0_n_6),
.I3(add_temp_14__138_carry__0_n_6),
.I4(add_temp_14__92_carry__0_n_6),
.I5(add_temp_14__278_carry__0_i_10_n_0),
.O(add_temp_14__278_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__0_i_8
(.I0(add_temp_14__278_carry__0_i_4_n_0),
.I1(add_temp_14__184_carry__0_n_7),
.I2(add_temp_14__230_carry__0_n_7),
.I3(add_temp_14__138_carry__0_n_7),
.I4(add_temp_14__92_carry__0_n_7),
.I5(add_temp_14__278_carry__0_i_11_n_0),
.O(add_temp_14__278_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__0_i_9
(.I0(add_temp_14__138_carry__0_n_6),
.I1(add_temp_14__184_carry__0_n_6),
.I2(add_temp_14__230_carry__0_n_6),
.O(add_temp_14__278_carry__0_i_9_n_0));
CARRY4 add_temp_14__278_carry__1
(.CI(add_temp_14__278_carry__0_n_0),
.CO({add_temp_14__278_carry__1_n_0,add_temp_14__278_carry__1_n_1,add_temp_14__278_carry__1_n_2,add_temp_14__278_carry__1_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__278_carry__1_i_1_n_0,add_temp_14__278_carry__1_i_2_n_0,add_temp_14__278_carry__1_i_3_n_0,add_temp_14__278_carry__1_i_4_n_0}),
.O(filter_sum[11:8]),
.S({add_temp_14__278_carry__1_i_5_n_0,add_temp_14__278_carry__1_i_6_n_0,add_temp_14__278_carry__1_i_7_n_0,add_temp_14__278_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__1_i_1
(.I0(add_temp_14__138_carry__1_n_5),
.I1(add_temp_14__230_carry__1_n_5),
.I2(add_temp_14__184_carry__1_n_5),
.I3(add_temp_14__278_carry__1_i_9_n_0),
.I4(add_temp_14__92_carry__1_n_5),
.O(add_temp_14__278_carry__1_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__1_i_10
(.I0(add_temp_14__184_carry__1_n_7),
.I1(add_temp_14__138_carry__1_n_7),
.I2(add_temp_14__230_carry__1_n_7),
.O(add_temp_14__278_carry__1_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__278_carry__1_i_11
(.I0(add_temp_14__138_carry__1_n_7),
.I1(add_temp_14__230_carry__1_n_7),
.I2(add_temp_14__184_carry__1_n_7),
.O(add_temp_14__278_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h96))
add_temp_14__278_carry__1_i_12
(.I0(add_temp_14__138_carry__1_n_4),
.I1(add_temp_14__230_carry__1_n_4),
.I2(add_temp_14__184_carry__1_n_4),
.O(add_temp_14__278_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__1_i_2
(.I0(add_temp_14__138_carry__1_n_6),
.I1(add_temp_14__230_carry__1_n_6),
.I2(add_temp_14__184_carry__1_n_6),
.I3(add_temp_14__278_carry__1_i_10_n_0),
.I4(add_temp_14__92_carry__1_n_6),
.O(add_temp_14__278_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'hFEEAA880))
add_temp_14__278_carry__1_i_3
(.I0(add_temp_14__92_carry__1_n_7),
.I1(add_temp_14__138_carry__0_n_4),
.I2(add_temp_14__184_carry__0_n_4),
.I3(add_temp_14__230_carry__0_n_4),
.I4(add_temp_14__278_carry__1_i_11_n_0),
.O(add_temp_14__278_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'hFEEAA880))
add_temp_14__278_carry__1_i_4
(.I0(add_temp_14__92_carry__0_n_4),
.I1(add_temp_14__230_carry__0_n_5),
.I2(add_temp_14__184_carry__0_n_5),
.I3(add_temp_14__138_carry__0_n_5),
.I4(add_temp_14__278_carry__0_i_12_n_0),
.O(add_temp_14__278_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'h6969699669969696))
add_temp_14__278_carry__1_i_5
(.I0(add_temp_14__278_carry__1_i_1_n_0),
.I1(add_temp_14__278_carry__1_i_12_n_0),
.I2(add_temp_14__92_carry__1_n_4),
.I3(add_temp_14__230_carry__1_n_5),
.I4(add_temp_14__184_carry__1_n_5),
.I5(add_temp_14__138_carry__1_n_5),
.O(add_temp_14__278_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__1_i_6
(.I0(add_temp_14__278_carry__1_i_2_n_0),
.I1(add_temp_14__184_carry__1_n_5),
.I2(add_temp_14__230_carry__1_n_5),
.I3(add_temp_14__138_carry__1_n_5),
.I4(add_temp_14__92_carry__1_n_5),
.I5(add_temp_14__278_carry__1_i_9_n_0),
.O(add_temp_14__278_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__1_i_7
(.I0(add_temp_14__278_carry__1_i_3_n_0),
.I1(add_temp_14__184_carry__1_n_6),
.I2(add_temp_14__230_carry__1_n_6),
.I3(add_temp_14__138_carry__1_n_6),
.I4(add_temp_14__92_carry__1_n_6),
.I5(add_temp_14__278_carry__1_i_10_n_0),
.O(add_temp_14__278_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'h6969699669969696))
add_temp_14__278_carry__1_i_8
(.I0(add_temp_14__278_carry__1_i_4_n_0),
.I1(add_temp_14__278_carry__1_i_11_n_0),
.I2(add_temp_14__92_carry__1_n_7),
.I3(add_temp_14__230_carry__0_n_4),
.I4(add_temp_14__184_carry__0_n_4),
.I5(add_temp_14__138_carry__0_n_4),
.O(add_temp_14__278_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__1_i_9
(.I0(add_temp_14__184_carry__1_n_6),
.I1(add_temp_14__230_carry__1_n_6),
.I2(add_temp_14__138_carry__1_n_6),
.O(add_temp_14__278_carry__1_i_9_n_0));
CARRY4 add_temp_14__278_carry__2
(.CI(add_temp_14__278_carry__1_n_0),
.CO({NLW_add_temp_14__278_carry__2_CO_UNCONNECTED[3],add_temp_14__278_carry__2_n_1,add_temp_14__278_carry__2_n_2,add_temp_14__278_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,add_temp_14__278_carry__2_i_1_n_0,add_temp_14__278_carry__2_i_2_n_0,add_temp_14__278_carry__2_i_3_n_0}),
.O(filter_sum[15:12]),
.S({add_temp_14__278_carry__2_i_4_n_0,add_temp_14__278_carry__2_i_5_n_0,add_temp_14__278_carry__2_i_6_n_0,add_temp_14__278_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__2_i_1
(.I0(add_temp_14__138_carry__2_n_6),
.I1(add_temp_14__230_carry__2_n_6),
.I2(add_temp_14__184_carry__2_n_6),
.I3(add_temp_14__278_carry__2_i_8_n_0),
.I4(add_temp_14__92_carry__2_n_6),
.O(add_temp_14__278_carry__2_i_1_n_0));
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__2_i_10
(.I0(add_temp_14__184_carry__2_n_6),
.I1(add_temp_14__230_carry__2_n_6),
.I2(add_temp_14__138_carry__2_n_6),
.O(add_temp_14__278_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__278_carry__2_i_11
(.I0(add_temp_14__184_carry__2_n_4),
.I1(add_temp_14__230_carry__2_n_4),
.I2(add_temp_14__138_carry__2_n_4),
.I3(add_temp_14__92_carry__2_n_4),
.O(add_temp_14__278_carry__2_i_11_n_0));
LUT5 #(
.INIT(32'hFEEAA880))
add_temp_14__278_carry__2_i_2
(.I0(add_temp_14__92_carry__2_n_7),
.I1(add_temp_14__138_carry__1_n_4),
.I2(add_temp_14__184_carry__1_n_4),
.I3(add_temp_14__230_carry__1_n_4),
.I4(add_temp_14__278_carry__2_i_9_n_0),
.O(add_temp_14__278_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'hFEEAA880))
add_temp_14__278_carry__2_i_3
(.I0(add_temp_14__92_carry__1_n_4),
.I1(add_temp_14__138_carry__1_n_5),
.I2(add_temp_14__184_carry__1_n_5),
.I3(add_temp_14__230_carry__1_n_5),
.I4(add_temp_14__278_carry__1_i_12_n_0),
.O(add_temp_14__278_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'hE187871E871E1E78))
add_temp_14__278_carry__2_i_4
(.I0(add_temp_14__92_carry__2_n_5),
.I1(add_temp_14__278_carry__2_i_10_n_0),
.I2(add_temp_14__278_carry__2_i_11_n_0),
.I3(add_temp_14__138_carry__2_n_5),
.I4(add_temp_14__184_carry__2_n_5),
.I5(add_temp_14__230_carry__2_n_5),
.O(add_temp_14__278_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__2_i_5
(.I0(add_temp_14__278_carry__2_i_1_n_0),
.I1(add_temp_14__184_carry__2_n_5),
.I2(add_temp_14__230_carry__2_n_5),
.I3(add_temp_14__138_carry__2_n_5),
.I4(add_temp_14__92_carry__2_n_5),
.I5(add_temp_14__278_carry__2_i_10_n_0),
.O(add_temp_14__278_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__2_i_6
(.I0(add_temp_14__278_carry__2_i_2_n_0),
.I1(add_temp_14__184_carry__2_n_6),
.I2(add_temp_14__230_carry__2_n_6),
.I3(add_temp_14__138_carry__2_n_6),
.I4(add_temp_14__92_carry__2_n_6),
.I5(add_temp_14__278_carry__2_i_8_n_0),
.O(add_temp_14__278_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'h6969699669969696))
add_temp_14__278_carry__2_i_7
(.I0(add_temp_14__278_carry__2_i_3_n_0),
.I1(add_temp_14__278_carry__2_i_9_n_0),
.I2(add_temp_14__92_carry__2_n_7),
.I3(add_temp_14__230_carry__1_n_4),
.I4(add_temp_14__184_carry__1_n_4),
.I5(add_temp_14__138_carry__1_n_4),
.O(add_temp_14__278_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__2_i_8
(.I0(add_temp_14__184_carry__2_n_7),
.I1(add_temp_14__138_carry__2_n_7),
.I2(add_temp_14__230_carry__2_n_7),
.O(add_temp_14__278_carry__2_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__278_carry__2_i_9
(.I0(add_temp_14__138_carry__2_n_7),
.I1(add_temp_14__230_carry__2_n_7),
.I2(add_temp_14__184_carry__2_n_7),
.O(add_temp_14__278_carry__2_i_9_n_0));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry_i_1
(.I0(add_temp_14__138_carry_n_5),
.I1(add_temp_14__230_carry_n_5),
.I2(add_temp_14__184_carry_n_5),
.I3(add_temp_14__278_carry_i_8_n_0),
.I4(add_temp_14__92_carry_n_5),
.O(add_temp_14__278_carry_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__278_carry_i_10
(.I0(add_temp_14__138_carry_n_5),
.I1(add_temp_14__230_carry_n_5),
.I2(add_temp_14__184_carry_n_5),
.O(add_temp_14__278_carry_i_10_n_0));
LUT5 #(
.INIT(32'h96696996))
add_temp_14__278_carry_i_2
(.I0(add_temp_14__278_carry_i_8_n_0),
.I1(add_temp_14__92_carry_n_5),
.I2(add_temp_14__138_carry_n_5),
.I3(add_temp_14__230_carry_n_5),
.I4(add_temp_14__184_carry_n_5),
.O(add_temp_14__278_carry_i_2_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__278_carry_i_3
(.I0(add_temp_14__184_carry_n_6),
.I1(add_temp_14__230_carry_n_6),
.I2(add_temp_14__138_carry_n_6),
.I3(add_temp_14__92_carry_n_6),
.O(add_temp_14__278_carry_i_3_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry_i_4
(.I0(add_temp_14__278_carry_i_1_n_0),
.I1(add_temp_14__184_carry_n_4),
.I2(add_temp_14__230_carry_n_4),
.I3(add_temp_14__138_carry_n_4),
.I4(add_temp_14__92_carry_n_4),
.I5(add_temp_14__278_carry_i_9_n_0),
.O(add_temp_14__278_carry_i_4_n_0));
LUT6 #(
.INIT(64'h6999999699969666))
add_temp_14__278_carry_i_5
(.I0(add_temp_14__278_carry_i_10_n_0),
.I1(add_temp_14__92_carry_n_5),
.I2(add_temp_14__138_carry_n_6),
.I3(add_temp_14__230_carry_n_6),
.I4(add_temp_14__184_carry_n_6),
.I5(add_temp_14__92_carry_n_6),
.O(add_temp_14__278_carry_i_5_n_0));
LUT4 #(
.INIT(16'h566A))
add_temp_14__278_carry_i_6
(.I0(add_temp_14__278_carry_i_3_n_0),
.I1(add_temp_14__230_carry_n_7),
.I2(add_temp_14__184_carry_n_7),
.I3(add_temp_14__138_carry_n_7),
.O(add_temp_14__278_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__278_carry_i_7
(.I0(add_temp_14__184_carry_n_7),
.I1(add_temp_14__230_carry_n_7),
.I2(add_temp_14__138_carry_n_7),
.I3(add_temp_14__92_carry_n_7),
.O(add_temp_14__278_carry_i_7_n_0));
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry_i_8
(.I0(add_temp_14__138_carry_n_6),
.I1(add_temp_14__230_carry_n_6),
.I2(add_temp_14__184_carry_n_6),
.O(add_temp_14__278_carry_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry_i_9
(.I0(add_temp_14__184_carry_n_5),
.I1(add_temp_14__138_carry_n_5),
.I2(add_temp_14__230_carry_n_5),
.O(add_temp_14__278_carry_i_9_n_0));
CARRY4 add_temp_14__46_carry
(.CI(1'b0),
.CO({add_temp_14__46_carry_n_0,add_temp_14__46_carry_n_1,add_temp_14__46_carry_n_2,add_temp_14__46_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__46_carry_i_1_n_0,add_temp_14__46_carry_i_2_n_0,add_temp_14__46_carry_i_3_n_0,1'b0}),
.O({add_temp_14__46_carry_n_4,add_temp_14__46_carry_n_5,add_temp_14__46_carry_n_6,add_temp_14__46_carry_n_7}),
.S({add_temp_14__46_carry_i_4_n_0,add_temp_14__46_carry_i_5_n_0,add_temp_14__46_carry_i_6_n_0,add_temp_14__46_carry_i_7_n_0}));
CARRY4 add_temp_14__46_carry__0
(.CI(add_temp_14__46_carry_n_0),
.CO({add_temp_14__46_carry__0_n_0,add_temp_14__46_carry__0_n_1,add_temp_14__46_carry__0_n_2,add_temp_14__46_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__46_carry__0_i_1_n_0,add_temp_14__46_carry__0_i_2_n_0,add_temp_14__46_carry__0_i_3_n_0,add_temp_14__46_carry__0_i_4_n_0}),
.O({add_temp_14__46_carry__0_n_4,add_temp_14__46_carry__0_n_5,add_temp_14__46_carry__0_n_6,add_temp_14__46_carry__0_n_7}),
.S({add_temp_14__46_carry__0_i_5_n_0,add_temp_14__46_carry__0_i_6_n_0,add_temp_14__46_carry__0_i_7_n_0,add_temp_14__46_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair20" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__0_i_1
(.I0(RESIZE38[6]),
.I1(RESIZE40[6]),
.I2(RESIZE36[6]),
.O(add_temp_14__46_carry__0_i_1_n_0));
(* HLUTNM = "lutpair19" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__0_i_2
(.I0(RESIZE38[5]),
.I1(RESIZE40[5]),
.I2(RESIZE36[5]),
.O(add_temp_14__46_carry__0_i_2_n_0));
(* HLUTNM = "lutpair18" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__0_i_3
(.I0(RESIZE38[4]),
.I1(RESIZE40[4]),
.I2(RESIZE36[4]),
.O(add_temp_14__46_carry__0_i_3_n_0));
(* HLUTNM = "lutpair17" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__0_i_4
(.I0(RESIZE38[3]),
.I1(RESIZE40[3]),
.I2(RESIZE36[3]),
.O(add_temp_14__46_carry__0_i_4_n_0));
(* HLUTNM = "lutpair21" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__0_i_5
(.I0(RESIZE38[7]),
.I1(RESIZE40[7]),
.I2(RESIZE36[7]),
.I3(add_temp_14__46_carry__0_i_1_n_0),
.O(add_temp_14__46_carry__0_i_5_n_0));
(* HLUTNM = "lutpair20" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__0_i_6
(.I0(RESIZE38[6]),
.I1(RESIZE40[6]),
.I2(RESIZE36[6]),
.I3(add_temp_14__46_carry__0_i_2_n_0),
.O(add_temp_14__46_carry__0_i_6_n_0));
(* HLUTNM = "lutpair19" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__0_i_7
(.I0(RESIZE38[5]),
.I1(RESIZE40[5]),
.I2(RESIZE36[5]),
.I3(add_temp_14__46_carry__0_i_3_n_0),
.O(add_temp_14__46_carry__0_i_7_n_0));
(* HLUTNM = "lutpair18" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__0_i_8
(.I0(RESIZE38[4]),
.I1(RESIZE40[4]),
.I2(RESIZE36[4]),
.I3(add_temp_14__46_carry__0_i_4_n_0),
.O(add_temp_14__46_carry__0_i_8_n_0));
CARRY4 add_temp_14__46_carry__1
(.CI(add_temp_14__46_carry__0_n_0),
.CO({add_temp_14__46_carry__1_n_0,add_temp_14__46_carry__1_n_1,add_temp_14__46_carry__1_n_2,add_temp_14__46_carry__1_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__46_carry__1_i_1_n_0,add_temp_14__46_carry__1_i_2_n_0,add_temp_14__46_carry__1_i_3_n_0,add_temp_14__46_carry__1_i_4_n_0}),
.O({add_temp_14__46_carry__1_n_4,add_temp_14__46_carry__1_n_5,add_temp_14__46_carry__1_n_6,add_temp_14__46_carry__1_n_7}),
.S({add_temp_14__46_carry__1_i_5_n_0,add_temp_14__46_carry__1_i_6_n_0,add_temp_14__46_carry__1_i_7_n_0,add_temp_14__46_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair24" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__1_i_1
(.I0(RESIZE40[10]),
.I1(RESIZE36[10]),
.I2(RESIZE38[10]),
.O(add_temp_14__46_carry__1_i_1_n_0));
(* HLUTNM = "lutpair23" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__1_i_2
(.I0(RESIZE38[9]),
.I1(RESIZE40[9]),
.I2(RESIZE36[9]),
.O(add_temp_14__46_carry__1_i_2_n_0));
(* HLUTNM = "lutpair22" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__1_i_3
(.I0(RESIZE38[8]),
.I1(RESIZE40[8]),
.I2(RESIZE36[8]),
.O(add_temp_14__46_carry__1_i_3_n_0));
(* HLUTNM = "lutpair21" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__1_i_4
(.I0(RESIZE38[7]),
.I1(RESIZE40[7]),
.I2(RESIZE36[7]),
.O(add_temp_14__46_carry__1_i_4_n_0));
(* HLUTNM = "lutpair25" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__1_i_5
(.I0(RESIZE36[11]),
.I1(RESIZE38[11]),
.I2(RESIZE40[11]),
.I3(add_temp_14__46_carry__1_i_1_n_0),
.O(add_temp_14__46_carry__1_i_5_n_0));
(* HLUTNM = "lutpair24" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__1_i_6
(.I0(RESIZE40[10]),
.I1(RESIZE36[10]),
.I2(RESIZE38[10]),
.I3(add_temp_14__46_carry__1_i_2_n_0),
.O(add_temp_14__46_carry__1_i_6_n_0));
(* HLUTNM = "lutpair23" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__1_i_7
(.I0(RESIZE38[9]),
.I1(RESIZE40[9]),
.I2(RESIZE36[9]),
.I3(add_temp_14__46_carry__1_i_3_n_0),
.O(add_temp_14__46_carry__1_i_7_n_0));
(* HLUTNM = "lutpair22" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__1_i_8
(.I0(RESIZE38[8]),
.I1(RESIZE40[8]),
.I2(RESIZE36[8]),
.I3(add_temp_14__46_carry__1_i_4_n_0),
.O(add_temp_14__46_carry__1_i_8_n_0));
CARRY4 add_temp_14__46_carry__2
(.CI(add_temp_14__46_carry__1_n_0),
.CO({NLW_add_temp_14__46_carry__2_CO_UNCONNECTED[3],add_temp_14__46_carry__2_n_1,add_temp_14__46_carry__2_n_2,add_temp_14__46_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,add_temp_14__46_carry__2_i_1_n_0,add_temp_14__46_carry__2_i_2_n_0,add_temp_14__46_carry__2_i_3_n_0}),
.O({add_temp_14__46_carry__2_n_4,add_temp_14__46_carry__2_n_5,add_temp_14__46_carry__2_n_6,add_temp_14__46_carry__2_n_7}),
.S({add_temp_14__46_carry__2_i_4_n_0,add_temp_14__46_carry__2_i_5_n_0,add_temp_14__46_carry__2_i_6_n_0,add_temp_14__46_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair27" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__2_i_1
(.I0(RESIZE36[13]),
.I1(RESIZE38[13]),
.I2(RESIZE40[13]),
.O(add_temp_14__46_carry__2_i_1_n_0));
(* HLUTNM = "lutpair26" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__2_i_2
(.I0(RESIZE36[12]),
.I1(RESIZE38[12]),
.I2(RESIZE40[12]),
.O(add_temp_14__46_carry__2_i_2_n_0));
(* HLUTNM = "lutpair25" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__2_i_3
(.I0(RESIZE36[11]),
.I1(RESIZE38[11]),
.I2(RESIZE40[11]),
.O(add_temp_14__46_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h17E8E817E81717E8))
add_temp_14__46_carry__2_i_4
(.I0(RESIZE40[14]),
.I1(RESIZE38[14]),
.I2(RESIZE36[14]),
.I3(RESIZE38[15]),
.I4(RESIZE36[15]),
.I5(RESIZE40[15]),
.O(add_temp_14__46_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__2_i_5
(.I0(add_temp_14__46_carry__2_i_1_n_0),
.I1(RESIZE38[14]),
.I2(RESIZE36[14]),
.I3(RESIZE40[14]),
.O(add_temp_14__46_carry__2_i_5_n_0));
(* HLUTNM = "lutpair27" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__2_i_6
(.I0(RESIZE36[13]),
.I1(RESIZE38[13]),
.I2(RESIZE40[13]),
.I3(add_temp_14__46_carry__2_i_2_n_0),
.O(add_temp_14__46_carry__2_i_6_n_0));
(* HLUTNM = "lutpair26" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__2_i_7
(.I0(RESIZE36[12]),
.I1(RESIZE38[12]),
.I2(RESIZE40[12]),
.I3(add_temp_14__46_carry__2_i_3_n_0),
.O(add_temp_14__46_carry__2_i_7_n_0));
(* HLUTNM = "lutpair16" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry_i_1
(.I0(RESIZE38[2]),
.I1(RESIZE40[2]),
.I2(RESIZE36[2]),
.O(add_temp_14__46_carry_i_1_n_0));
(* HLUTNM = "lutpair15" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry_i_2
(.I0(RESIZE38[1]),
.I1(RESIZE40[1]),
.I2(RESIZE36[1]),
.O(add_temp_14__46_carry_i_2_n_0));
(* HLUTNM = "lutpair14" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry_i_3
(.I0(RESIZE38[0]),
.I1(RESIZE40[0]),
.I2(RESIZE36[0]),
.O(add_temp_14__46_carry_i_3_n_0));
(* HLUTNM = "lutpair17" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry_i_4
(.I0(RESIZE38[3]),
.I1(RESIZE40[3]),
.I2(RESIZE36[3]),
.I3(add_temp_14__46_carry_i_1_n_0),
.O(add_temp_14__46_carry_i_4_n_0));
(* HLUTNM = "lutpair16" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry_i_5
(.I0(RESIZE38[2]),
.I1(RESIZE40[2]),
.I2(RESIZE36[2]),
.I3(add_temp_14__46_carry_i_2_n_0),
.O(add_temp_14__46_carry_i_5_n_0));
(* HLUTNM = "lutpair15" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry_i_6
(.I0(RESIZE38[1]),
.I1(RESIZE40[1]),
.I2(RESIZE36[1]),
.I3(add_temp_14__46_carry_i_3_n_0),
.O(add_temp_14__46_carry_i_6_n_0));
(* HLUTNM = "lutpair14" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__46_carry_i_7
(.I0(RESIZE38[0]),
.I1(RESIZE40[0]),
.I2(RESIZE36[0]),
.O(add_temp_14__46_carry_i_7_n_0));
CARRY4 add_temp_14__92_carry
(.CI(1'b0),
.CO({add_temp_14__92_carry_n_0,add_temp_14__92_carry_n_1,add_temp_14__92_carry_n_2,add_temp_14__92_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__92_carry_i_1_n_0,add_temp_14__92_carry_i_2_n_0,add_temp_14__92_carry_i_3_n_0,1'b0}),
.O({add_temp_14__92_carry_n_4,add_temp_14__92_carry_n_5,add_temp_14__92_carry_n_6,add_temp_14__92_carry_n_7}),
.S({add_temp_14__92_carry_i_4_n_0,add_temp_14__92_carry_i_5_n_0,add_temp_14__92_carry_i_6_n_0,add_temp_14__92_carry_i_7_n_0}));
CARRY4 add_temp_14__92_carry__0
(.CI(add_temp_14__92_carry_n_0),
.CO({add_temp_14__92_carry__0_n_0,add_temp_14__92_carry__0_n_1,add_temp_14__92_carry__0_n_2,add_temp_14__92_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__92_carry__0_i_1_n_0,add_temp_14__92_carry__0_i_2_n_0,add_temp_14__92_carry__0_i_3_n_0,add_temp_14__92_carry__0_i_4_n_0}),
.O({add_temp_14__92_carry__0_n_4,add_temp_14__92_carry__0_n_5,add_temp_14__92_carry__0_n_6,add_temp_14__92_carry__0_n_7}),
.S({add_temp_14__92_carry__0_i_5_n_0,add_temp_14__92_carry__0_i_6_n_0,add_temp_14__92_carry__0_i_7_n_0,add_temp_14__92_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair34" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__0_i_1
(.I0(RESIZE32[6]),
.I1(RESIZE34[6]),
.I2(RESIZE30[6]),
.O(add_temp_14__92_carry__0_i_1_n_0));
(* HLUTNM = "lutpair33" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__0_i_2
(.I0(RESIZE32[5]),
.I1(RESIZE34[5]),
.I2(RESIZE30[5]),
.O(add_temp_14__92_carry__0_i_2_n_0));
(* HLUTNM = "lutpair32" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__0_i_3
(.I0(RESIZE32[4]),
.I1(RESIZE34[4]),
.I2(RESIZE30[4]),
.O(add_temp_14__92_carry__0_i_3_n_0));
(* HLUTNM = "lutpair31" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__0_i_4
(.I0(RESIZE32[3]),
.I1(RESIZE34[3]),
.I2(RESIZE30[3]),
.O(add_temp_14__92_carry__0_i_4_n_0));
(* HLUTNM = "lutpair35" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__0_i_5
(.I0(RESIZE34[7]),
.I1(RESIZE30[7]),
.I2(RESIZE32[7]),
.I3(add_temp_14__92_carry__0_i_1_n_0),
.O(add_temp_14__92_carry__0_i_5_n_0));
(* HLUTNM = "lutpair34" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__0_i_6
(.I0(RESIZE32[6]),
.I1(RESIZE34[6]),
.I2(RESIZE30[6]),
.I3(add_temp_14__92_carry__0_i_2_n_0),
.O(add_temp_14__92_carry__0_i_6_n_0));
(* HLUTNM = "lutpair33" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__0_i_7
(.I0(RESIZE32[5]),
.I1(RESIZE34[5]),
.I2(RESIZE30[5]),
.I3(add_temp_14__92_carry__0_i_3_n_0),
.O(add_temp_14__92_carry__0_i_7_n_0));
(* HLUTNM = "lutpair32" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__0_i_8
(.I0(RESIZE32[4]),
.I1(RESIZE34[4]),
.I2(RESIZE30[4]),
.I3(add_temp_14__92_carry__0_i_4_n_0),
.O(add_temp_14__92_carry__0_i_8_n_0));
CARRY4 add_temp_14__92_carry__1
(.CI(add_temp_14__92_carry__0_n_0),
.CO({add_temp_14__92_carry__1_n_0,add_temp_14__92_carry__1_n_1,add_temp_14__92_carry__1_n_2,add_temp_14__92_carry__1_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__92_carry__1_i_1_n_0,add_temp_14__92_carry__1_i_2_n_0,add_temp_14__92_carry__1_i_3_n_0,add_temp_14__92_carry__1_i_4_n_0}),
.O({add_temp_14__92_carry__1_n_4,add_temp_14__92_carry__1_n_5,add_temp_14__92_carry__1_n_6,add_temp_14__92_carry__1_n_7}),
.S({add_temp_14__92_carry__1_i_5_n_0,add_temp_14__92_carry__1_i_6_n_0,add_temp_14__92_carry__1_i_7_n_0,add_temp_14__92_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair38" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__1_i_1
(.I0(RESIZE30[10]),
.I1(RESIZE32[10]),
.I2(RESIZE34[10]),
.O(add_temp_14__92_carry__1_i_1_n_0));
(* HLUTNM = "lutpair37" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__1_i_2
(.I0(RESIZE30[9]),
.I1(RESIZE32[9]),
.I2(RESIZE34[9]),
.O(add_temp_14__92_carry__1_i_2_n_0));
(* HLUTNM = "lutpair36" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__1_i_3
(.I0(RESIZE30[8]),
.I1(RESIZE32[8]),
.I2(RESIZE34[8]),
.O(add_temp_14__92_carry__1_i_3_n_0));
(* HLUTNM = "lutpair35" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__1_i_4
(.I0(RESIZE34[7]),
.I1(RESIZE30[7]),
.I2(RESIZE32[7]),
.O(add_temp_14__92_carry__1_i_4_n_0));
(* HLUTNM = "lutpair39" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__1_i_5
(.I0(RESIZE30[11]),
.I1(RESIZE32[11]),
.I2(RESIZE34[11]),
.I3(add_temp_14__92_carry__1_i_1_n_0),
.O(add_temp_14__92_carry__1_i_5_n_0));
(* HLUTNM = "lutpair38" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__1_i_6
(.I0(RESIZE30[10]),
.I1(RESIZE32[10]),
.I2(RESIZE34[10]),
.I3(add_temp_14__92_carry__1_i_2_n_0),
.O(add_temp_14__92_carry__1_i_6_n_0));
(* HLUTNM = "lutpair37" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__1_i_7
(.I0(RESIZE30[9]),
.I1(RESIZE32[9]),
.I2(RESIZE34[9]),
.I3(add_temp_14__92_carry__1_i_3_n_0),
.O(add_temp_14__92_carry__1_i_7_n_0));
(* HLUTNM = "lutpair36" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__1_i_8
(.I0(RESIZE30[8]),
.I1(RESIZE32[8]),
.I2(RESIZE34[8]),
.I3(add_temp_14__92_carry__1_i_4_n_0),
.O(add_temp_14__92_carry__1_i_8_n_0));
CARRY4 add_temp_14__92_carry__2
(.CI(add_temp_14__92_carry__1_n_0),
.CO({NLW_add_temp_14__92_carry__2_CO_UNCONNECTED[3],add_temp_14__92_carry__2_n_1,add_temp_14__92_carry__2_n_2,add_temp_14__92_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,add_temp_14__92_carry__2_i_1_n_0,add_temp_14__92_carry__2_i_2_n_0,add_temp_14__92_carry__2_i_3_n_0}),
.O({add_temp_14__92_carry__2_n_4,add_temp_14__92_carry__2_n_5,add_temp_14__92_carry__2_n_6,add_temp_14__92_carry__2_n_7}),
.S({add_temp_14__92_carry__2_i_4_n_0,add_temp_14__92_carry__2_i_5_n_0,add_temp_14__92_carry__2_i_6_n_0,add_temp_14__92_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair41" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__2_i_1
(.I0(RESIZE30[13]),
.I1(RESIZE32[13]),
.I2(RESIZE34[13]),
.O(add_temp_14__92_carry__2_i_1_n_0));
(* HLUTNM = "lutpair40" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__2_i_2
(.I0(RESIZE30[12]),
.I1(RESIZE32[12]),
.I2(RESIZE34[12]),
.O(add_temp_14__92_carry__2_i_2_n_0));
(* HLUTNM = "lutpair39" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__2_i_3
(.I0(RESIZE30[11]),
.I1(RESIZE32[11]),
.I2(RESIZE34[11]),
.O(add_temp_14__92_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h17E8E817E81717E8))
add_temp_14__92_carry__2_i_4
(.I0(RESIZE34[14]),
.I1(RESIZE32[14]),
.I2(RESIZE30[14]),
.I3(RESIZE32[15]),
.I4(RESIZE30[15]),
.I5(RESIZE34[15]),
.O(add_temp_14__92_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__2_i_5
(.I0(add_temp_14__92_carry__2_i_1_n_0),
.I1(RESIZE32[14]),
.I2(RESIZE30[14]),
.I3(RESIZE34[14]),
.O(add_temp_14__92_carry__2_i_5_n_0));
(* HLUTNM = "lutpair41" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__2_i_6
(.I0(RESIZE30[13]),
.I1(RESIZE32[13]),
.I2(RESIZE34[13]),
.I3(add_temp_14__92_carry__2_i_2_n_0),
.O(add_temp_14__92_carry__2_i_6_n_0));
(* HLUTNM = "lutpair40" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__2_i_7
(.I0(RESIZE30[12]),
.I1(RESIZE32[12]),
.I2(RESIZE34[12]),
.I3(add_temp_14__92_carry__2_i_3_n_0),
.O(add_temp_14__92_carry__2_i_7_n_0));
(* HLUTNM = "lutpair30" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry_i_1
(.I0(RESIZE32[2]),
.I1(RESIZE34[2]),
.I2(RESIZE30[2]),
.O(add_temp_14__92_carry_i_1_n_0));
(* HLUTNM = "lutpair29" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry_i_2
(.I0(RESIZE32[1]),
.I1(RESIZE34[1]),
.I2(RESIZE30[1]),
.O(add_temp_14__92_carry_i_2_n_0));
(* HLUTNM = "lutpair28" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry_i_3
(.I0(RESIZE32[0]),
.I1(RESIZE34[0]),
.I2(RESIZE30[0]),
.O(add_temp_14__92_carry_i_3_n_0));
(* HLUTNM = "lutpair31" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry_i_4
(.I0(RESIZE32[3]),
.I1(RESIZE34[3]),
.I2(RESIZE30[3]),
.I3(add_temp_14__92_carry_i_1_n_0),
.O(add_temp_14__92_carry_i_4_n_0));
(* HLUTNM = "lutpair30" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry_i_5
(.I0(RESIZE32[2]),
.I1(RESIZE34[2]),
.I2(RESIZE30[2]),
.I3(add_temp_14__92_carry_i_2_n_0),
.O(add_temp_14__92_carry_i_5_n_0));
(* HLUTNM = "lutpair29" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry_i_6
(.I0(RESIZE32[1]),
.I1(RESIZE34[1]),
.I2(RESIZE30[1]),
.I3(add_temp_14__92_carry_i_3_n_0),
.O(add_temp_14__92_carry_i_6_n_0));
(* HLUTNM = "lutpair28" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__92_carry_i_7
(.I0(RESIZE32[0]),
.I1(RESIZE34[0]),
.I2(RESIZE30[0]),
.O(add_temp_14__92_carry_i_7_n_0));
FDCE \data_pipeline_tmp_reg[0][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [0]),
.Q(\data_pipeline_tmp_reg[0] [0]));
FDCE \data_pipeline_tmp_reg[0][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [10]),
.Q(\data_pipeline_tmp_reg[0] [10]));
FDCE \data_pipeline_tmp_reg[0][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [11]),
.Q(\data_pipeline_tmp_reg[0] [11]));
FDCE \data_pipeline_tmp_reg[0][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [12]),
.Q(\data_pipeline_tmp_reg[0] [12]));
FDCE \data_pipeline_tmp_reg[0][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [13]),
.Q(\data_pipeline_tmp_reg[0] [13]));
FDCE \data_pipeline_tmp_reg[0][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [14]),
.Q(\data_pipeline_tmp_reg[0] [14]));
FDCE \data_pipeline_tmp_reg[0][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [15]),
.Q(\data_pipeline_tmp_reg[0] [15]));
FDCE \data_pipeline_tmp_reg[0][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [1]),
.Q(\data_pipeline_tmp_reg[0] [1]));
FDCE \data_pipeline_tmp_reg[0][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [2]),
.Q(\data_pipeline_tmp_reg[0] [2]));
FDCE \data_pipeline_tmp_reg[0][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [3]),
.Q(\data_pipeline_tmp_reg[0] [3]));
FDCE \data_pipeline_tmp_reg[0][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [4]),
.Q(\data_pipeline_tmp_reg[0] [4]));
FDCE \data_pipeline_tmp_reg[0][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [5]),
.Q(\data_pipeline_tmp_reg[0] [5]));
FDCE \data_pipeline_tmp_reg[0][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [6]),
.Q(\data_pipeline_tmp_reg[0] [6]));
FDCE \data_pipeline_tmp_reg[0][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [7]),
.Q(\data_pipeline_tmp_reg[0] [7]));
FDCE \data_pipeline_tmp_reg[0][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [8]),
.Q(\data_pipeline_tmp_reg[0] [8]));
FDCE \data_pipeline_tmp_reg[0][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [9]),
.Q(\data_pipeline_tmp_reg[0] [9]));
FDCE \data_pipeline_tmp_reg[10][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [0]),
.Q(\data_pipeline_tmp_reg[10] [0]));
FDCE \data_pipeline_tmp_reg[10][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [10]),
.Q(\data_pipeline_tmp_reg[10] [10]));
FDCE \data_pipeline_tmp_reg[10][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [11]),
.Q(\data_pipeline_tmp_reg[10] [11]));
FDCE \data_pipeline_tmp_reg[10][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [12]),
.Q(\data_pipeline_tmp_reg[10] [12]));
FDCE \data_pipeline_tmp_reg[10][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [13]),
.Q(\data_pipeline_tmp_reg[10] [13]));
FDCE \data_pipeline_tmp_reg[10][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [14]),
.Q(\data_pipeline_tmp_reg[10] [14]));
FDCE \data_pipeline_tmp_reg[10][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [15]),
.Q(\data_pipeline_tmp_reg[10] [15]));
FDCE \data_pipeline_tmp_reg[10][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [1]),
.Q(\data_pipeline_tmp_reg[10] [1]));
FDCE \data_pipeline_tmp_reg[10][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [2]),
.Q(\data_pipeline_tmp_reg[10] [2]));
FDCE \data_pipeline_tmp_reg[10][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [3]),
.Q(\data_pipeline_tmp_reg[10] [3]));
FDCE \data_pipeline_tmp_reg[10][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [4]),
.Q(\data_pipeline_tmp_reg[10] [4]));
FDCE \data_pipeline_tmp_reg[10][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [5]),
.Q(\data_pipeline_tmp_reg[10] [5]));
FDCE \data_pipeline_tmp_reg[10][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [6]),
.Q(\data_pipeline_tmp_reg[10] [6]));
FDCE \data_pipeline_tmp_reg[10][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [7]),
.Q(\data_pipeline_tmp_reg[10] [7]));
FDCE \data_pipeline_tmp_reg[10][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [8]),
.Q(\data_pipeline_tmp_reg[10] [8]));
FDCE \data_pipeline_tmp_reg[10][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [9]),
.Q(\data_pipeline_tmp_reg[10] [9]));
FDCE \data_pipeline_tmp_reg[11][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [0]),
.Q(\data_pipeline_tmp_reg[11] [0]));
FDCE \data_pipeline_tmp_reg[11][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [10]),
.Q(\data_pipeline_tmp_reg[11] [10]));
FDCE \data_pipeline_tmp_reg[11][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [11]),
.Q(\data_pipeline_tmp_reg[11] [11]));
FDCE \data_pipeline_tmp_reg[11][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [12]),
.Q(\data_pipeline_tmp_reg[11] [12]));
FDCE \data_pipeline_tmp_reg[11][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [13]),
.Q(\data_pipeline_tmp_reg[11] [13]));
FDCE \data_pipeline_tmp_reg[11][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [14]),
.Q(\data_pipeline_tmp_reg[11] [14]));
FDCE \data_pipeline_tmp_reg[11][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [15]),
.Q(\data_pipeline_tmp_reg[11] [15]));
FDCE \data_pipeline_tmp_reg[11][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [1]),
.Q(\data_pipeline_tmp_reg[11] [1]));
FDCE \data_pipeline_tmp_reg[11][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [2]),
.Q(\data_pipeline_tmp_reg[11] [2]));
FDCE \data_pipeline_tmp_reg[11][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [3]),
.Q(\data_pipeline_tmp_reg[11] [3]));
FDCE \data_pipeline_tmp_reg[11][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [4]),
.Q(\data_pipeline_tmp_reg[11] [4]));
FDCE \data_pipeline_tmp_reg[11][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [5]),
.Q(\data_pipeline_tmp_reg[11] [5]));
FDCE \data_pipeline_tmp_reg[11][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [6]),
.Q(\data_pipeline_tmp_reg[11] [6]));
FDCE \data_pipeline_tmp_reg[11][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [7]),
.Q(\data_pipeline_tmp_reg[11] [7]));
FDCE \data_pipeline_tmp_reg[11][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [8]),
.Q(\data_pipeline_tmp_reg[11] [8]));
FDCE \data_pipeline_tmp_reg[11][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [9]),
.Q(\data_pipeline_tmp_reg[11] [9]));
FDCE \data_pipeline_tmp_reg[12][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [0]),
.Q(\data_pipeline_tmp_reg[12] [0]));
FDCE \data_pipeline_tmp_reg[12][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [10]),
.Q(\data_pipeline_tmp_reg[12] [10]));
FDCE \data_pipeline_tmp_reg[12][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [11]),
.Q(\data_pipeline_tmp_reg[12] [11]));
FDCE \data_pipeline_tmp_reg[12][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [12]),
.Q(\data_pipeline_tmp_reg[12] [12]));
FDCE \data_pipeline_tmp_reg[12][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [13]),
.Q(\data_pipeline_tmp_reg[12] [13]));
FDCE \data_pipeline_tmp_reg[12][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [14]),
.Q(\data_pipeline_tmp_reg[12] [14]));
FDCE \data_pipeline_tmp_reg[12][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [15]),
.Q(\data_pipeline_tmp_reg[12] [15]));
FDCE \data_pipeline_tmp_reg[12][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [1]),
.Q(\data_pipeline_tmp_reg[12] [1]));
FDCE \data_pipeline_tmp_reg[12][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [2]),
.Q(\data_pipeline_tmp_reg[12] [2]));
FDCE \data_pipeline_tmp_reg[12][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [3]),
.Q(\data_pipeline_tmp_reg[12] [3]));
FDCE \data_pipeline_tmp_reg[12][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [4]),
.Q(\data_pipeline_tmp_reg[12] [4]));
FDCE \data_pipeline_tmp_reg[12][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [5]),
.Q(\data_pipeline_tmp_reg[12] [5]));
FDCE \data_pipeline_tmp_reg[12][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [6]),
.Q(\data_pipeline_tmp_reg[12] [6]));
FDCE \data_pipeline_tmp_reg[12][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [7]),
.Q(\data_pipeline_tmp_reg[12] [7]));
FDCE \data_pipeline_tmp_reg[12][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [8]),
.Q(\data_pipeline_tmp_reg[12] [8]));
FDCE \data_pipeline_tmp_reg[12][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [9]),
.Q(\data_pipeline_tmp_reg[12] [9]));
FDCE \data_pipeline_tmp_reg[13][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [0]),
.Q(\data_pipeline_tmp_reg[13] [0]));
FDCE \data_pipeline_tmp_reg[13][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [10]),
.Q(\data_pipeline_tmp_reg[13] [10]));
FDCE \data_pipeline_tmp_reg[13][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [11]),
.Q(\data_pipeline_tmp_reg[13] [11]));
FDCE \data_pipeline_tmp_reg[13][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [12]),
.Q(\data_pipeline_tmp_reg[13] [12]));
FDCE \data_pipeline_tmp_reg[13][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [13]),
.Q(\data_pipeline_tmp_reg[13] [13]));
FDCE \data_pipeline_tmp_reg[13][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [14]),
.Q(\data_pipeline_tmp_reg[13] [14]));
FDCE \data_pipeline_tmp_reg[13][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [15]),
.Q(\data_pipeline_tmp_reg[13] [15]));
FDCE \data_pipeline_tmp_reg[13][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [1]),
.Q(\data_pipeline_tmp_reg[13] [1]));
FDCE \data_pipeline_tmp_reg[13][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [2]),
.Q(\data_pipeline_tmp_reg[13] [2]));
FDCE \data_pipeline_tmp_reg[13][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [3]),
.Q(\data_pipeline_tmp_reg[13] [3]));
FDCE \data_pipeline_tmp_reg[13][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [4]),
.Q(\data_pipeline_tmp_reg[13] [4]));
FDCE \data_pipeline_tmp_reg[13][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [5]),
.Q(\data_pipeline_tmp_reg[13] [5]));
FDCE \data_pipeline_tmp_reg[13][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [6]),
.Q(\data_pipeline_tmp_reg[13] [6]));
FDCE \data_pipeline_tmp_reg[13][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [7]),
.Q(\data_pipeline_tmp_reg[13] [7]));
FDCE \data_pipeline_tmp_reg[13][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [8]),
.Q(\data_pipeline_tmp_reg[13] [8]));
FDCE \data_pipeline_tmp_reg[13][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [9]),
.Q(\data_pipeline_tmp_reg[13] [9]));
FDCE \data_pipeline_tmp_reg[14][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [0]),
.Q(\data_pipeline_tmp_reg[14] [0]));
FDCE \data_pipeline_tmp_reg[14][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [10]),
.Q(\data_pipeline_tmp_reg[14] [10]));
FDCE \data_pipeline_tmp_reg[14][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [11]),
.Q(\data_pipeline_tmp_reg[14] [11]));
FDCE \data_pipeline_tmp_reg[14][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [12]),
.Q(\data_pipeline_tmp_reg[14] [12]));
FDCE \data_pipeline_tmp_reg[14][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [13]),
.Q(\data_pipeline_tmp_reg[14] [13]));
FDCE \data_pipeline_tmp_reg[14][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [14]),
.Q(\data_pipeline_tmp_reg[14] [14]));
FDCE \data_pipeline_tmp_reg[14][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [15]),
.Q(\data_pipeline_tmp_reg[14] [15]));
FDCE \data_pipeline_tmp_reg[14][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [1]),
.Q(\data_pipeline_tmp_reg[14] [1]));
FDCE \data_pipeline_tmp_reg[14][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [2]),
.Q(\data_pipeline_tmp_reg[14] [2]));
FDCE \data_pipeline_tmp_reg[14][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [3]),
.Q(\data_pipeline_tmp_reg[14] [3]));
FDCE \data_pipeline_tmp_reg[14][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [4]),
.Q(\data_pipeline_tmp_reg[14] [4]));
FDCE \data_pipeline_tmp_reg[14][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [5]),
.Q(\data_pipeline_tmp_reg[14] [5]));
FDCE \data_pipeline_tmp_reg[14][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [6]),
.Q(\data_pipeline_tmp_reg[14] [6]));
FDCE \data_pipeline_tmp_reg[14][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [7]),
.Q(\data_pipeline_tmp_reg[14] [7]));
FDCE \data_pipeline_tmp_reg[14][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [8]),
.Q(\data_pipeline_tmp_reg[14] [8]));
FDCE \data_pipeline_tmp_reg[14][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [9]),
.Q(\data_pipeline_tmp_reg[14] [9]));
FDCE \data_pipeline_tmp_reg[1][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [0]),
.Q(\data_pipeline_tmp_reg[1] [0]));
FDCE \data_pipeline_tmp_reg[1][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [10]),
.Q(\data_pipeline_tmp_reg[1] [10]));
FDCE \data_pipeline_tmp_reg[1][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [11]),
.Q(\data_pipeline_tmp_reg[1] [11]));
FDCE \data_pipeline_tmp_reg[1][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [12]),
.Q(\data_pipeline_tmp_reg[1] [12]));
FDCE \data_pipeline_tmp_reg[1][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [13]),
.Q(\data_pipeline_tmp_reg[1] [13]));
FDCE \data_pipeline_tmp_reg[1][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [14]),
.Q(\data_pipeline_tmp_reg[1] [14]));
FDCE \data_pipeline_tmp_reg[1][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [15]),
.Q(\data_pipeline_tmp_reg[1] [15]));
FDCE \data_pipeline_tmp_reg[1][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [1]),
.Q(\data_pipeline_tmp_reg[1] [1]));
FDCE \data_pipeline_tmp_reg[1][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [2]),
.Q(\data_pipeline_tmp_reg[1] [2]));
FDCE \data_pipeline_tmp_reg[1][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [3]),
.Q(\data_pipeline_tmp_reg[1] [3]));
FDCE \data_pipeline_tmp_reg[1][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [4]),
.Q(\data_pipeline_tmp_reg[1] [4]));
FDCE \data_pipeline_tmp_reg[1][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [5]),
.Q(\data_pipeline_tmp_reg[1] [5]));
FDCE \data_pipeline_tmp_reg[1][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [6]),
.Q(\data_pipeline_tmp_reg[1] [6]));
FDCE \data_pipeline_tmp_reg[1][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [7]),
.Q(\data_pipeline_tmp_reg[1] [7]));
FDCE \data_pipeline_tmp_reg[1][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [8]),
.Q(\data_pipeline_tmp_reg[1] [8]));
FDCE \data_pipeline_tmp_reg[1][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [9]),
.Q(\data_pipeline_tmp_reg[1] [9]));
FDCE \data_pipeline_tmp_reg[2][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [0]),
.Q(\data_pipeline_tmp_reg[2] [0]));
FDCE \data_pipeline_tmp_reg[2][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [10]),
.Q(\data_pipeline_tmp_reg[2] [10]));
FDCE \data_pipeline_tmp_reg[2][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [11]),
.Q(\data_pipeline_tmp_reg[2] [11]));
FDCE \data_pipeline_tmp_reg[2][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [12]),
.Q(\data_pipeline_tmp_reg[2] [12]));
FDCE \data_pipeline_tmp_reg[2][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [13]),
.Q(\data_pipeline_tmp_reg[2] [13]));
FDCE \data_pipeline_tmp_reg[2][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [14]),
.Q(\data_pipeline_tmp_reg[2] [14]));
FDCE \data_pipeline_tmp_reg[2][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [15]),
.Q(\data_pipeline_tmp_reg[2] [15]));
FDCE \data_pipeline_tmp_reg[2][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [1]),
.Q(\data_pipeline_tmp_reg[2] [1]));
FDCE \data_pipeline_tmp_reg[2][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [2]),
.Q(\data_pipeline_tmp_reg[2] [2]));
FDCE \data_pipeline_tmp_reg[2][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [3]),
.Q(\data_pipeline_tmp_reg[2] [3]));
FDCE \data_pipeline_tmp_reg[2][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [4]),
.Q(\data_pipeline_tmp_reg[2] [4]));
FDCE \data_pipeline_tmp_reg[2][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [5]),
.Q(\data_pipeline_tmp_reg[2] [5]));
FDCE \data_pipeline_tmp_reg[2][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [6]),
.Q(\data_pipeline_tmp_reg[2] [6]));
FDCE \data_pipeline_tmp_reg[2][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [7]),
.Q(\data_pipeline_tmp_reg[2] [7]));
FDCE \data_pipeline_tmp_reg[2][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [8]),
.Q(\data_pipeline_tmp_reg[2] [8]));
FDCE \data_pipeline_tmp_reg[2][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [9]),
.Q(\data_pipeline_tmp_reg[2] [9]));
FDCE \data_pipeline_tmp_reg[3][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [0]),
.Q(\data_pipeline_tmp_reg[3] [0]));
FDCE \data_pipeline_tmp_reg[3][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [10]),
.Q(\data_pipeline_tmp_reg[3] [10]));
FDCE \data_pipeline_tmp_reg[3][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [11]),
.Q(\data_pipeline_tmp_reg[3] [11]));
FDCE \data_pipeline_tmp_reg[3][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [12]),
.Q(\data_pipeline_tmp_reg[3] [12]));
FDCE \data_pipeline_tmp_reg[3][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [13]),
.Q(\data_pipeline_tmp_reg[3] [13]));
FDCE \data_pipeline_tmp_reg[3][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [14]),
.Q(\data_pipeline_tmp_reg[3] [14]));
FDCE \data_pipeline_tmp_reg[3][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [15]),
.Q(\data_pipeline_tmp_reg[3] [15]));
FDCE \data_pipeline_tmp_reg[3][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [1]),
.Q(\data_pipeline_tmp_reg[3] [1]));
FDCE \data_pipeline_tmp_reg[3][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [2]),
.Q(\data_pipeline_tmp_reg[3] [2]));
FDCE \data_pipeline_tmp_reg[3][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [3]),
.Q(\data_pipeline_tmp_reg[3] [3]));
FDCE \data_pipeline_tmp_reg[3][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [4]),
.Q(\data_pipeline_tmp_reg[3] [4]));
FDCE \data_pipeline_tmp_reg[3][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [5]),
.Q(\data_pipeline_tmp_reg[3] [5]));
FDCE \data_pipeline_tmp_reg[3][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [6]),
.Q(\data_pipeline_tmp_reg[3] [6]));
FDCE \data_pipeline_tmp_reg[3][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [7]),
.Q(\data_pipeline_tmp_reg[3] [7]));
FDCE \data_pipeline_tmp_reg[3][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [8]),
.Q(\data_pipeline_tmp_reg[3] [8]));
FDCE \data_pipeline_tmp_reg[3][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [9]),
.Q(\data_pipeline_tmp_reg[3] [9]));
FDCE \data_pipeline_tmp_reg[4][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [0]),
.Q(\data_pipeline_tmp_reg[4] [0]));
FDCE \data_pipeline_tmp_reg[4][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [10]),
.Q(\data_pipeline_tmp_reg[4] [10]));
FDCE \data_pipeline_tmp_reg[4][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [11]),
.Q(\data_pipeline_tmp_reg[4] [11]));
FDCE \data_pipeline_tmp_reg[4][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [12]),
.Q(\data_pipeline_tmp_reg[4] [12]));
FDCE \data_pipeline_tmp_reg[4][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [13]),
.Q(\data_pipeline_tmp_reg[4] [13]));
FDCE \data_pipeline_tmp_reg[4][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [14]),
.Q(\data_pipeline_tmp_reg[4] [14]));
FDCE \data_pipeline_tmp_reg[4][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [15]),
.Q(\data_pipeline_tmp_reg[4] [15]));
FDCE \data_pipeline_tmp_reg[4][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [1]),
.Q(\data_pipeline_tmp_reg[4] [1]));
FDCE \data_pipeline_tmp_reg[4][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [2]),
.Q(\data_pipeline_tmp_reg[4] [2]));
FDCE \data_pipeline_tmp_reg[4][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [3]),
.Q(\data_pipeline_tmp_reg[4] [3]));
FDCE \data_pipeline_tmp_reg[4][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [4]),
.Q(\data_pipeline_tmp_reg[4] [4]));
FDCE \data_pipeline_tmp_reg[4][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [5]),
.Q(\data_pipeline_tmp_reg[4] [5]));
FDCE \data_pipeline_tmp_reg[4][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [6]),
.Q(\data_pipeline_tmp_reg[4] [6]));
FDCE \data_pipeline_tmp_reg[4][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [7]),
.Q(\data_pipeline_tmp_reg[4] [7]));
FDCE \data_pipeline_tmp_reg[4][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [8]),
.Q(\data_pipeline_tmp_reg[4] [8]));
FDCE \data_pipeline_tmp_reg[4][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [9]),
.Q(\data_pipeline_tmp_reg[4] [9]));
FDCE \data_pipeline_tmp_reg[5][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [0]),
.Q(\data_pipeline_tmp_reg[5] [0]));
FDCE \data_pipeline_tmp_reg[5][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [10]),
.Q(\data_pipeline_tmp_reg[5] [10]));
FDCE \data_pipeline_tmp_reg[5][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [11]),
.Q(\data_pipeline_tmp_reg[5] [11]));
FDCE \data_pipeline_tmp_reg[5][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [12]),
.Q(\data_pipeline_tmp_reg[5] [12]));
FDCE \data_pipeline_tmp_reg[5][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [13]),
.Q(\data_pipeline_tmp_reg[5] [13]));
FDCE \data_pipeline_tmp_reg[5][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [14]),
.Q(\data_pipeline_tmp_reg[5] [14]));
FDCE \data_pipeline_tmp_reg[5][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [15]),
.Q(\data_pipeline_tmp_reg[5] [15]));
FDCE \data_pipeline_tmp_reg[5][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [1]),
.Q(\data_pipeline_tmp_reg[5] [1]));
FDCE \data_pipeline_tmp_reg[5][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [2]),
.Q(\data_pipeline_tmp_reg[5] [2]));
FDCE \data_pipeline_tmp_reg[5][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [3]),
.Q(\data_pipeline_tmp_reg[5] [3]));
FDCE \data_pipeline_tmp_reg[5][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [4]),
.Q(\data_pipeline_tmp_reg[5] [4]));
FDCE \data_pipeline_tmp_reg[5][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [5]),
.Q(\data_pipeline_tmp_reg[5] [5]));
FDCE \data_pipeline_tmp_reg[5][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [6]),
.Q(\data_pipeline_tmp_reg[5] [6]));
FDCE \data_pipeline_tmp_reg[5][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [7]),
.Q(\data_pipeline_tmp_reg[5] [7]));
FDCE \data_pipeline_tmp_reg[5][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [8]),
.Q(\data_pipeline_tmp_reg[5] [8]));
FDCE \data_pipeline_tmp_reg[5][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [9]),
.Q(\data_pipeline_tmp_reg[5] [9]));
FDCE \data_pipeline_tmp_reg[6][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [0]),
.Q(\data_pipeline_tmp_reg[6] [0]));
FDCE \data_pipeline_tmp_reg[6][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [10]),
.Q(\data_pipeline_tmp_reg[6] [10]));
FDCE \data_pipeline_tmp_reg[6][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [11]),
.Q(\data_pipeline_tmp_reg[6] [11]));
FDCE \data_pipeline_tmp_reg[6][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [12]),
.Q(\data_pipeline_tmp_reg[6] [12]));
FDCE \data_pipeline_tmp_reg[6][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [13]),
.Q(\data_pipeline_tmp_reg[6] [13]));
FDCE \data_pipeline_tmp_reg[6][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [14]),
.Q(\data_pipeline_tmp_reg[6] [14]));
FDCE \data_pipeline_tmp_reg[6][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [15]),
.Q(\data_pipeline_tmp_reg[6] [15]));
FDCE \data_pipeline_tmp_reg[6][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [1]),
.Q(\data_pipeline_tmp_reg[6] [1]));
FDCE \data_pipeline_tmp_reg[6][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [2]),
.Q(\data_pipeline_tmp_reg[6] [2]));
FDCE \data_pipeline_tmp_reg[6][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [3]),
.Q(\data_pipeline_tmp_reg[6] [3]));
FDCE \data_pipeline_tmp_reg[6][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [4]),
.Q(\data_pipeline_tmp_reg[6] [4]));
FDCE \data_pipeline_tmp_reg[6][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [5]),
.Q(\data_pipeline_tmp_reg[6] [5]));
FDCE \data_pipeline_tmp_reg[6][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [6]),
.Q(\data_pipeline_tmp_reg[6] [6]));
FDCE \data_pipeline_tmp_reg[6][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [7]),
.Q(\data_pipeline_tmp_reg[6] [7]));
FDCE \data_pipeline_tmp_reg[6][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [8]),
.Q(\data_pipeline_tmp_reg[6] [8]));
FDCE \data_pipeline_tmp_reg[6][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [9]),
.Q(\data_pipeline_tmp_reg[6] [9]));
FDCE \data_pipeline_tmp_reg[7][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [0]),
.Q(\data_pipeline_tmp_reg[7] [0]));
FDCE \data_pipeline_tmp_reg[7][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [10]),
.Q(\data_pipeline_tmp_reg[7] [10]));
FDCE \data_pipeline_tmp_reg[7][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [11]),
.Q(\data_pipeline_tmp_reg[7] [11]));
FDCE \data_pipeline_tmp_reg[7][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [12]),
.Q(\data_pipeline_tmp_reg[7] [12]));
FDCE \data_pipeline_tmp_reg[7][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [13]),
.Q(\data_pipeline_tmp_reg[7] [13]));
FDCE \data_pipeline_tmp_reg[7][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [14]),
.Q(\data_pipeline_tmp_reg[7] [14]));
FDCE \data_pipeline_tmp_reg[7][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [15]),
.Q(\data_pipeline_tmp_reg[7] [15]));
FDCE \data_pipeline_tmp_reg[7][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [1]),
.Q(\data_pipeline_tmp_reg[7] [1]));
FDCE \data_pipeline_tmp_reg[7][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [2]),
.Q(\data_pipeline_tmp_reg[7] [2]));
FDCE \data_pipeline_tmp_reg[7][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [3]),
.Q(\data_pipeline_tmp_reg[7] [3]));
FDCE \data_pipeline_tmp_reg[7][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [4]),
.Q(\data_pipeline_tmp_reg[7] [4]));
FDCE \data_pipeline_tmp_reg[7][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [5]),
.Q(\data_pipeline_tmp_reg[7] [5]));
FDCE \data_pipeline_tmp_reg[7][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [6]),
.Q(\data_pipeline_tmp_reg[7] [6]));
FDCE \data_pipeline_tmp_reg[7][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [7]),
.Q(\data_pipeline_tmp_reg[7] [7]));
FDCE \data_pipeline_tmp_reg[7][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [8]),
.Q(\data_pipeline_tmp_reg[7] [8]));
FDCE \data_pipeline_tmp_reg[7][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [9]),
.Q(\data_pipeline_tmp_reg[7] [9]));
FDCE \data_pipeline_tmp_reg[8][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [0]),
.Q(\data_pipeline_tmp_reg[8] [0]));
FDCE \data_pipeline_tmp_reg[8][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [10]),
.Q(\data_pipeline_tmp_reg[8] [10]));
FDCE \data_pipeline_tmp_reg[8][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [11]),
.Q(\data_pipeline_tmp_reg[8] [11]));
FDCE \data_pipeline_tmp_reg[8][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [12]),
.Q(\data_pipeline_tmp_reg[8] [12]));
FDCE \data_pipeline_tmp_reg[8][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [13]),
.Q(\data_pipeline_tmp_reg[8] [13]));
FDCE \data_pipeline_tmp_reg[8][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [14]),
.Q(\data_pipeline_tmp_reg[8] [14]));
FDCE \data_pipeline_tmp_reg[8][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [15]),
.Q(\data_pipeline_tmp_reg[8] [15]));
FDCE \data_pipeline_tmp_reg[8][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [1]),
.Q(\data_pipeline_tmp_reg[8] [1]));
FDCE \data_pipeline_tmp_reg[8][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [2]),
.Q(\data_pipeline_tmp_reg[8] [2]));
FDCE \data_pipeline_tmp_reg[8][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [3]),
.Q(\data_pipeline_tmp_reg[8] [3]));
FDCE \data_pipeline_tmp_reg[8][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [4]),
.Q(\data_pipeline_tmp_reg[8] [4]));
FDCE \data_pipeline_tmp_reg[8][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [5]),
.Q(\data_pipeline_tmp_reg[8] [5]));
FDCE \data_pipeline_tmp_reg[8][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [6]),
.Q(\data_pipeline_tmp_reg[8] [6]));
FDCE \data_pipeline_tmp_reg[8][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [7]),
.Q(\data_pipeline_tmp_reg[8] [7]));
FDCE \data_pipeline_tmp_reg[8][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [8]),
.Q(\data_pipeline_tmp_reg[8] [8]));
FDCE \data_pipeline_tmp_reg[8][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [9]),
.Q(\data_pipeline_tmp_reg[8] [9]));
FDCE \data_pipeline_tmp_reg[9][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [0]),
.Q(\data_pipeline_tmp_reg[9] [0]));
FDCE \data_pipeline_tmp_reg[9][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [10]),
.Q(\data_pipeline_tmp_reg[9] [10]));
FDCE \data_pipeline_tmp_reg[9][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [11]),
.Q(\data_pipeline_tmp_reg[9] [11]));
FDCE \data_pipeline_tmp_reg[9][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [12]),
.Q(\data_pipeline_tmp_reg[9] [12]));
FDCE \data_pipeline_tmp_reg[9][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [13]),
.Q(\data_pipeline_tmp_reg[9] [13]));
FDCE \data_pipeline_tmp_reg[9][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [14]),
.Q(\data_pipeline_tmp_reg[9] [14]));
FDCE \data_pipeline_tmp_reg[9][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [15]),
.Q(\data_pipeline_tmp_reg[9] [15]));
FDCE \data_pipeline_tmp_reg[9][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [1]),
.Q(\data_pipeline_tmp_reg[9] [1]));
FDCE \data_pipeline_tmp_reg[9][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [2]),
.Q(\data_pipeline_tmp_reg[9] [2]));
FDCE \data_pipeline_tmp_reg[9][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [3]),
.Q(\data_pipeline_tmp_reg[9] [3]));
FDCE \data_pipeline_tmp_reg[9][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [4]),
.Q(\data_pipeline_tmp_reg[9] [4]));
FDCE \data_pipeline_tmp_reg[9][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [5]),
.Q(\data_pipeline_tmp_reg[9] [5]));
FDCE \data_pipeline_tmp_reg[9][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [6]),
.Q(\data_pipeline_tmp_reg[9] [6]));
FDCE \data_pipeline_tmp_reg[9][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [7]),
.Q(\data_pipeline_tmp_reg[9] [7]));
FDCE \data_pipeline_tmp_reg[9][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [8]),
.Q(\data_pipeline_tmp_reg[9] [8]));
FDCE \data_pipeline_tmp_reg[9][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [9]),
.Q(\data_pipeline_tmp_reg[9] [9]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp
(.A({\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[0]_15 [15],\weight_reg[0]_15 [15],\weight_reg[0]_15 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_P_UNCONNECTED[47:32],mul_temp_n_74,mul_temp_n_75,mul_temp_n_76,mul_temp_n_77,mul_temp_n_78,mul_temp_n_79,mul_temp_n_80,mul_temp_n_81,mul_temp_n_82,mul_temp_n_83,mul_temp_n_84,mul_temp_n_85,mul_temp_n_86,mul_temp_n_87,mul_temp_n_88,mul_temp_n_89,mul_temp_n_90,\^mul_temp ,mul_temp_n_92,mul_temp_n_93,mul_temp_n_94,mul_temp_n_95,mul_temp_n_96,mul_temp_n_97,mul_temp_n_98,mul_temp_n_99,mul_temp_n_100,mul_temp_n_101,mul_temp_n_102,mul_temp_n_103,mul_temp_n_104,mul_temp_n_105}),
.PATTERNBDETECT(NLW_mul_temp_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_1
(.A({\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_1_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[1]_0 [15],\weight_reg[1]_0 [15],\weight_reg[1]_0 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_1_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_1_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_1_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_1_P_UNCONNECTED[47:32],mul_temp_1_n_74,mul_temp_1_n_75,mul_temp_1_n_76,mul_temp_1_n_77,mul_temp_1_n_78,mul_temp_1_n_79,mul_temp_1_n_80,mul_temp_1_n_81,mul_temp_1_n_82,mul_temp_1_n_83,mul_temp_1_n_84,mul_temp_1_n_85,mul_temp_1_n_86,mul_temp_1_n_87,mul_temp_1_n_88,mul_temp_1_n_89,mul_temp_1_n_90,\^mul_temp_1 ,mul_temp_1_n_92,mul_temp_1_n_93,mul_temp_1_n_94,mul_temp_1_n_95,mul_temp_1_n_96,mul_temp_1_n_97,mul_temp_1_n_98,mul_temp_1_n_99,mul_temp_1_n_100,mul_temp_1_n_101,mul_temp_1_n_102,mul_temp_1_n_103,mul_temp_1_n_104,mul_temp_1_n_105}),
.PATTERNBDETECT(NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_1_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_1_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_10
(.A({\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_10_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[10]_9 [15],\weight_reg[10]_9 [15],\weight_reg[10]_9 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_10_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_10_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_10_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_10_P_UNCONNECTED[47:32],mul_temp_10_n_74,mul_temp_10_n_75,mul_temp_10_n_76,mul_temp_10_n_77,mul_temp_10_n_78,mul_temp_10_n_79,mul_temp_10_n_80,mul_temp_10_n_81,mul_temp_10_n_82,mul_temp_10_n_83,mul_temp_10_n_84,mul_temp_10_n_85,mul_temp_10_n_86,mul_temp_10_n_87,mul_temp_10_n_88,mul_temp_10_n_89,mul_temp_10_n_90,\^mul_temp_10 ,mul_temp_10_n_92,mul_temp_10_n_93,mul_temp_10_n_94,mul_temp_10_n_95,mul_temp_10_n_96,mul_temp_10_n_97,mul_temp_10_n_98,mul_temp_10_n_99,mul_temp_10_n_100,mul_temp_10_n_101,mul_temp_10_n_102,mul_temp_10_n_103,mul_temp_10_n_104,mul_temp_10_n_105}),
.PATTERNBDETECT(NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_10_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_10_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_11
(.A({\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_11_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[11]_10 [15],\weight_reg[11]_10 [15],\weight_reg[11]_10 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_11_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_11_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_11_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_11_P_UNCONNECTED[47:32],mul_temp_11_n_74,mul_temp_11_n_75,mul_temp_11_n_76,mul_temp_11_n_77,mul_temp_11_n_78,mul_temp_11_n_79,mul_temp_11_n_80,mul_temp_11_n_81,mul_temp_11_n_82,mul_temp_11_n_83,mul_temp_11_n_84,mul_temp_11_n_85,mul_temp_11_n_86,mul_temp_11_n_87,mul_temp_11_n_88,mul_temp_11_n_89,mul_temp_11_n_90,\^mul_temp_11 ,mul_temp_11_n_92,mul_temp_11_n_93,mul_temp_11_n_94,mul_temp_11_n_95,mul_temp_11_n_96,mul_temp_11_n_97,mul_temp_11_n_98,mul_temp_11_n_99,mul_temp_11_n_100,mul_temp_11_n_101,mul_temp_11_n_102,mul_temp_11_n_103,mul_temp_11_n_104,mul_temp_11_n_105}),
.PATTERNBDETECT(NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_11_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_11_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_12
(.A({\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_12_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[12]_11 [15],\weight_reg[12]_11 [15],\weight_reg[12]_11 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_12_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_12_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_12_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_12_P_UNCONNECTED[47:32],mul_temp_12_n_74,mul_temp_12_n_75,mul_temp_12_n_76,mul_temp_12_n_77,mul_temp_12_n_78,mul_temp_12_n_79,mul_temp_12_n_80,mul_temp_12_n_81,mul_temp_12_n_82,mul_temp_12_n_83,mul_temp_12_n_84,mul_temp_12_n_85,mul_temp_12_n_86,mul_temp_12_n_87,mul_temp_12_n_88,mul_temp_12_n_89,mul_temp_12_n_90,\^mul_temp_12 ,mul_temp_12_n_92,mul_temp_12_n_93,mul_temp_12_n_94,mul_temp_12_n_95,mul_temp_12_n_96,mul_temp_12_n_97,mul_temp_12_n_98,mul_temp_12_n_99,mul_temp_12_n_100,mul_temp_12_n_101,mul_temp_12_n_102,mul_temp_12_n_103,mul_temp_12_n_104,mul_temp_12_n_105}),
.PATTERNBDETECT(NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_12_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_12_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_13
(.A({\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_13_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[13]_12 [15],\weight_reg[13]_12 [15],\weight_reg[13]_12 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_13_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_13_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_13_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_13_P_UNCONNECTED[47:32],mul_temp_13_n_74,mul_temp_13_n_75,mul_temp_13_n_76,mul_temp_13_n_77,mul_temp_13_n_78,mul_temp_13_n_79,mul_temp_13_n_80,mul_temp_13_n_81,mul_temp_13_n_82,mul_temp_13_n_83,mul_temp_13_n_84,mul_temp_13_n_85,mul_temp_13_n_86,mul_temp_13_n_87,mul_temp_13_n_88,mul_temp_13_n_89,mul_temp_13_n_90,\^mul_temp_13 ,mul_temp_13_n_92,mul_temp_13_n_93,mul_temp_13_n_94,mul_temp_13_n_95,mul_temp_13_n_96,mul_temp_13_n_97,mul_temp_13_n_98,mul_temp_13_n_99,mul_temp_13_n_100,mul_temp_13_n_101,mul_temp_13_n_102,mul_temp_13_n_103,mul_temp_13_n_104,mul_temp_13_n_105}),
.PATTERNBDETECT(NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_13_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_13_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_14
(.A({\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_14_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[14]_13 [15],\weight_reg[14]_13 [15],\weight_reg[14]_13 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_14_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_14_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_14_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_14_P_UNCONNECTED[47:32],mul_temp_14_n_74,mul_temp_14_n_75,mul_temp_14_n_76,mul_temp_14_n_77,mul_temp_14_n_78,mul_temp_14_n_79,mul_temp_14_n_80,mul_temp_14_n_81,mul_temp_14_n_82,mul_temp_14_n_83,mul_temp_14_n_84,mul_temp_14_n_85,mul_temp_14_n_86,mul_temp_14_n_87,mul_temp_14_n_88,mul_temp_14_n_89,mul_temp_14_n_90,\^mul_temp_14 ,mul_temp_14_n_92,mul_temp_14_n_93,mul_temp_14_n_94,mul_temp_14_n_95,mul_temp_14_n_96,mul_temp_14_n_97,mul_temp_14_n_98,mul_temp_14_n_99,mul_temp_14_n_100,mul_temp_14_n_101,mul_temp_14_n_102,mul_temp_14_n_103,mul_temp_14_n_104,mul_temp_14_n_105}),
.PATTERNBDETECT(NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_14_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_14_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_15
(.A({\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_15_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[15]_14 [15],\weight_reg[15]_14 [15],\weight_reg[15]_14 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_15_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_15_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_15_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_15_P_UNCONNECTED[47:32],mul_temp_15_n_74,mul_temp_15_n_75,mul_temp_15_n_76,mul_temp_15_n_77,mul_temp_15_n_78,mul_temp_15_n_79,mul_temp_15_n_80,mul_temp_15_n_81,mul_temp_15_n_82,mul_temp_15_n_83,mul_temp_15_n_84,mul_temp_15_n_85,mul_temp_15_n_86,mul_temp_15_n_87,mul_temp_15_n_88,mul_temp_15_n_89,mul_temp_15_n_90,\^mul_temp_15 ,mul_temp_15_n_92,mul_temp_15_n_93,mul_temp_15_n_94,mul_temp_15_n_95,mul_temp_15_n_96,mul_temp_15_n_97,mul_temp_15_n_98,mul_temp_15_n_99,mul_temp_15_n_100,mul_temp_15_n_101,mul_temp_15_n_102,mul_temp_15_n_103,mul_temp_15_n_104,mul_temp_15_n_105}),
.PATTERNBDETECT(NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_15_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_15_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_17
(.A({\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_17_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_17_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_17_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_17_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_17_P_UNCONNECTED[47:32],mul_temp_17_n_74,mul_temp_17_n_75,mul_temp_17_n_76,mul_temp_17_n_77,mul_temp_17_n_78,mul_temp_17_n_79,mul_temp_17_n_80,mul_temp_17_n_81,mul_temp_17_n_82,mul_temp_17_n_83,mul_temp_17_n_84,mul_temp_17_n_85,mul_temp_17_n_86,mul_temp_17_n_87,mul_temp_17_n_88,mul_temp_17_n_89,mul_temp_17_n_90,\^mul_temp_17 ,mul_temp_17_n_92,mul_temp_17_n_93,mul_temp_17_n_94,mul_temp_17_n_95,mul_temp_17_n_96,mul_temp_17_n_97,mul_temp_17_n_98,mul_temp_17_n_99,mul_temp_17_n_100,mul_temp_17_n_101,mul_temp_17_n_102,mul_temp_17_n_103,mul_temp_17_n_104,mul_temp_17_n_105}),
.PATTERNBDETECT(NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_17_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_17_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_18
(.A({\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_18_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_18_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_18_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_18_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_18_P_UNCONNECTED[47:32],mul_temp_18_n_74,mul_temp_18_n_75,mul_temp_18_n_76,mul_temp_18_n_77,mul_temp_18_n_78,mul_temp_18_n_79,mul_temp_18_n_80,mul_temp_18_n_81,mul_temp_18_n_82,mul_temp_18_n_83,mul_temp_18_n_84,mul_temp_18_n_85,mul_temp_18_n_86,mul_temp_18_n_87,mul_temp_18_n_88,mul_temp_18_n_89,mul_temp_18_n_90,\^mul_temp_18 ,mul_temp_18_n_92,mul_temp_18_n_93,mul_temp_18_n_94,mul_temp_18_n_95,mul_temp_18_n_96,mul_temp_18_n_97,mul_temp_18_n_98,mul_temp_18_n_99,mul_temp_18_n_100,mul_temp_18_n_101,mul_temp_18_n_102,mul_temp_18_n_103,mul_temp_18_n_104,mul_temp_18_n_105}),
.PATTERNBDETECT(NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_18_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_18_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_19
(.A({\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_19_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_19_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_19_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_19_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_19_P_UNCONNECTED[47:32],mul_temp_19_n_74,mul_temp_19_n_75,mul_temp_19_n_76,mul_temp_19_n_77,mul_temp_19_n_78,mul_temp_19_n_79,mul_temp_19_n_80,mul_temp_19_n_81,mul_temp_19_n_82,mul_temp_19_n_83,mul_temp_19_n_84,mul_temp_19_n_85,mul_temp_19_n_86,mul_temp_19_n_87,mul_temp_19_n_88,mul_temp_19_n_89,mul_temp_19_n_90,\^mul_temp_19 ,mul_temp_19_n_92,mul_temp_19_n_93,mul_temp_19_n_94,mul_temp_19_n_95,mul_temp_19_n_96,mul_temp_19_n_97,mul_temp_19_n_98,mul_temp_19_n_99,mul_temp_19_n_100,mul_temp_19_n_101,mul_temp_19_n_102,mul_temp_19_n_103,mul_temp_19_n_104,mul_temp_19_n_105}),
.PATTERNBDETECT(NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_19_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_19_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_2
(.A({\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_2_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[2]_1 [15],\weight_reg[2]_1 [15],\weight_reg[2]_1 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_2_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_2_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_2_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_2_P_UNCONNECTED[47:32],mul_temp_2_n_74,mul_temp_2_n_75,mul_temp_2_n_76,mul_temp_2_n_77,mul_temp_2_n_78,mul_temp_2_n_79,mul_temp_2_n_80,mul_temp_2_n_81,mul_temp_2_n_82,mul_temp_2_n_83,mul_temp_2_n_84,mul_temp_2_n_85,mul_temp_2_n_86,mul_temp_2_n_87,mul_temp_2_n_88,mul_temp_2_n_89,mul_temp_2_n_90,\^mul_temp_2 ,mul_temp_2_n_92,mul_temp_2_n_93,mul_temp_2_n_94,mul_temp_2_n_95,mul_temp_2_n_96,mul_temp_2_n_97,mul_temp_2_n_98,mul_temp_2_n_99,mul_temp_2_n_100,mul_temp_2_n_101,mul_temp_2_n_102,mul_temp_2_n_103,mul_temp_2_n_104,mul_temp_2_n_105}),
.PATTERNBDETECT(NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_2_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_2_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_20
(.A({\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_20_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_20_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_20_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_20_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_20_P_UNCONNECTED[47:32],mul_temp_20_n_74,mul_temp_20_n_75,mul_temp_20_n_76,mul_temp_20_n_77,mul_temp_20_n_78,mul_temp_20_n_79,mul_temp_20_n_80,mul_temp_20_n_81,mul_temp_20_n_82,mul_temp_20_n_83,mul_temp_20_n_84,mul_temp_20_n_85,mul_temp_20_n_86,mul_temp_20_n_87,mul_temp_20_n_88,mul_temp_20_n_89,mul_temp_20_n_90,\^mul_temp_20 ,mul_temp_20_n_92,mul_temp_20_n_93,mul_temp_20_n_94,mul_temp_20_n_95,mul_temp_20_n_96,mul_temp_20_n_97,mul_temp_20_n_98,mul_temp_20_n_99,mul_temp_20_n_100,mul_temp_20_n_101,mul_temp_20_n_102,mul_temp_20_n_103,mul_temp_20_n_104,mul_temp_20_n_105}),
.PATTERNBDETECT(NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_20_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_20_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_21
(.A({\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_21_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_21_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_21_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_21_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_21_P_UNCONNECTED[47:32],mul_temp_21_n_74,mul_temp_21_n_75,mul_temp_21_n_76,mul_temp_21_n_77,mul_temp_21_n_78,mul_temp_21_n_79,mul_temp_21_n_80,mul_temp_21_n_81,mul_temp_21_n_82,mul_temp_21_n_83,mul_temp_21_n_84,mul_temp_21_n_85,mul_temp_21_n_86,mul_temp_21_n_87,mul_temp_21_n_88,mul_temp_21_n_89,mul_temp_21_n_90,\^mul_temp_21 ,mul_temp_21_n_92,mul_temp_21_n_93,mul_temp_21_n_94,mul_temp_21_n_95,mul_temp_21_n_96,mul_temp_21_n_97,mul_temp_21_n_98,mul_temp_21_n_99,mul_temp_21_n_100,mul_temp_21_n_101,mul_temp_21_n_102,mul_temp_21_n_103,mul_temp_21_n_104,mul_temp_21_n_105}),
.PATTERNBDETECT(NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_21_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_21_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_22
(.A({\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_22_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_22_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_22_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_22_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_22_P_UNCONNECTED[47:32],mul_temp_22_n_74,mul_temp_22_n_75,mul_temp_22_n_76,mul_temp_22_n_77,mul_temp_22_n_78,mul_temp_22_n_79,mul_temp_22_n_80,mul_temp_22_n_81,mul_temp_22_n_82,mul_temp_22_n_83,mul_temp_22_n_84,mul_temp_22_n_85,mul_temp_22_n_86,mul_temp_22_n_87,mul_temp_22_n_88,mul_temp_22_n_89,mul_temp_22_n_90,\^mul_temp_22 ,mul_temp_22_n_92,mul_temp_22_n_93,mul_temp_22_n_94,mul_temp_22_n_95,mul_temp_22_n_96,mul_temp_22_n_97,mul_temp_22_n_98,mul_temp_22_n_99,mul_temp_22_n_100,mul_temp_22_n_101,mul_temp_22_n_102,mul_temp_22_n_103,mul_temp_22_n_104,mul_temp_22_n_105}),
.PATTERNBDETECT(NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_22_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_22_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_23
(.A({\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_23_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_23_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_23_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_23_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_23_P_UNCONNECTED[47:32],mul_temp_23_n_74,mul_temp_23_n_75,mul_temp_23_n_76,mul_temp_23_n_77,mul_temp_23_n_78,mul_temp_23_n_79,mul_temp_23_n_80,mul_temp_23_n_81,mul_temp_23_n_82,mul_temp_23_n_83,mul_temp_23_n_84,mul_temp_23_n_85,mul_temp_23_n_86,mul_temp_23_n_87,mul_temp_23_n_88,mul_temp_23_n_89,mul_temp_23_n_90,\^mul_temp_23 ,mul_temp_23_n_92,mul_temp_23_n_93,mul_temp_23_n_94,mul_temp_23_n_95,mul_temp_23_n_96,mul_temp_23_n_97,mul_temp_23_n_98,mul_temp_23_n_99,mul_temp_23_n_100,mul_temp_23_n_101,mul_temp_23_n_102,mul_temp_23_n_103,mul_temp_23_n_104,mul_temp_23_n_105}),
.PATTERNBDETECT(NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_23_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_23_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_24
(.A({\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_24_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_24_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_24_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_24_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_24_P_UNCONNECTED[47:32],mul_temp_24_n_74,mul_temp_24_n_75,mul_temp_24_n_76,mul_temp_24_n_77,mul_temp_24_n_78,mul_temp_24_n_79,mul_temp_24_n_80,mul_temp_24_n_81,mul_temp_24_n_82,mul_temp_24_n_83,mul_temp_24_n_84,mul_temp_24_n_85,mul_temp_24_n_86,mul_temp_24_n_87,mul_temp_24_n_88,mul_temp_24_n_89,mul_temp_24_n_90,\^mul_temp_24 ,mul_temp_24_n_92,mul_temp_24_n_93,mul_temp_24_n_94,mul_temp_24_n_95,mul_temp_24_n_96,mul_temp_24_n_97,mul_temp_24_n_98,mul_temp_24_n_99,mul_temp_24_n_100,mul_temp_24_n_101,mul_temp_24_n_102,mul_temp_24_n_103,mul_temp_24_n_104,mul_temp_24_n_105}),
.PATTERNBDETECT(NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_24_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_24_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_25
(.A({\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_25_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_25_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_25_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_25_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_25_P_UNCONNECTED[47:32],mul_temp_25_n_74,mul_temp_25_n_75,mul_temp_25_n_76,mul_temp_25_n_77,mul_temp_25_n_78,mul_temp_25_n_79,mul_temp_25_n_80,mul_temp_25_n_81,mul_temp_25_n_82,mul_temp_25_n_83,mul_temp_25_n_84,mul_temp_25_n_85,mul_temp_25_n_86,mul_temp_25_n_87,mul_temp_25_n_88,mul_temp_25_n_89,mul_temp_25_n_90,\^mul_temp_25 ,mul_temp_25_n_92,mul_temp_25_n_93,mul_temp_25_n_94,mul_temp_25_n_95,mul_temp_25_n_96,mul_temp_25_n_97,mul_temp_25_n_98,mul_temp_25_n_99,mul_temp_25_n_100,mul_temp_25_n_101,mul_temp_25_n_102,mul_temp_25_n_103,mul_temp_25_n_104,mul_temp_25_n_105}),
.PATTERNBDETECT(NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_25_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_25_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_26
(.A({\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_26_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_26_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_26_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_26_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_26_P_UNCONNECTED[47:32],mul_temp_26_n_74,mul_temp_26_n_75,mul_temp_26_n_76,mul_temp_26_n_77,mul_temp_26_n_78,mul_temp_26_n_79,mul_temp_26_n_80,mul_temp_26_n_81,mul_temp_26_n_82,mul_temp_26_n_83,mul_temp_26_n_84,mul_temp_26_n_85,mul_temp_26_n_86,mul_temp_26_n_87,mul_temp_26_n_88,mul_temp_26_n_89,mul_temp_26_n_90,\^mul_temp_26 ,mul_temp_26_n_92,mul_temp_26_n_93,mul_temp_26_n_94,mul_temp_26_n_95,mul_temp_26_n_96,mul_temp_26_n_97,mul_temp_26_n_98,mul_temp_26_n_99,mul_temp_26_n_100,mul_temp_26_n_101,mul_temp_26_n_102,mul_temp_26_n_103,mul_temp_26_n_104,mul_temp_26_n_105}),
.PATTERNBDETECT(NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_26_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_26_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_27
(.A({\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_27_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_27_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_27_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_27_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_27_P_UNCONNECTED[47:32],mul_temp_27_n_74,mul_temp_27_n_75,mul_temp_27_n_76,mul_temp_27_n_77,mul_temp_27_n_78,mul_temp_27_n_79,mul_temp_27_n_80,mul_temp_27_n_81,mul_temp_27_n_82,mul_temp_27_n_83,mul_temp_27_n_84,mul_temp_27_n_85,mul_temp_27_n_86,mul_temp_27_n_87,mul_temp_27_n_88,mul_temp_27_n_89,mul_temp_27_n_90,\^mul_temp_27 ,mul_temp_27_n_92,mul_temp_27_n_93,mul_temp_27_n_94,mul_temp_27_n_95,mul_temp_27_n_96,mul_temp_27_n_97,mul_temp_27_n_98,mul_temp_27_n_99,mul_temp_27_n_100,mul_temp_27_n_101,mul_temp_27_n_102,mul_temp_27_n_103,mul_temp_27_n_104,mul_temp_27_n_105}),
.PATTERNBDETECT(NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_27_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_27_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_28
(.A({\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_28_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_28_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_28_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_28_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_28_P_UNCONNECTED[47:32],mul_temp_28_n_74,mul_temp_28_n_75,mul_temp_28_n_76,mul_temp_28_n_77,mul_temp_28_n_78,mul_temp_28_n_79,mul_temp_28_n_80,mul_temp_28_n_81,mul_temp_28_n_82,mul_temp_28_n_83,mul_temp_28_n_84,mul_temp_28_n_85,mul_temp_28_n_86,mul_temp_28_n_87,mul_temp_28_n_88,mul_temp_28_n_89,mul_temp_28_n_90,\^mul_temp_28 ,mul_temp_28_n_92,mul_temp_28_n_93,mul_temp_28_n_94,mul_temp_28_n_95,mul_temp_28_n_96,mul_temp_28_n_97,mul_temp_28_n_98,mul_temp_28_n_99,mul_temp_28_n_100,mul_temp_28_n_101,mul_temp_28_n_102,mul_temp_28_n_103,mul_temp_28_n_104,mul_temp_28_n_105}),
.PATTERNBDETECT(NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_28_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_28_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_29
(.A({\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_29_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_29_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_29_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_29_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_29_P_UNCONNECTED[47:32],mul_temp_29_n_74,mul_temp_29_n_75,mul_temp_29_n_76,mul_temp_29_n_77,mul_temp_29_n_78,mul_temp_29_n_79,mul_temp_29_n_80,mul_temp_29_n_81,mul_temp_29_n_82,mul_temp_29_n_83,mul_temp_29_n_84,mul_temp_29_n_85,mul_temp_29_n_86,mul_temp_29_n_87,mul_temp_29_n_88,mul_temp_29_n_89,mul_temp_29_n_90,\^mul_temp_29 ,mul_temp_29_n_92,mul_temp_29_n_93,mul_temp_29_n_94,mul_temp_29_n_95,mul_temp_29_n_96,mul_temp_29_n_97,mul_temp_29_n_98,mul_temp_29_n_99,mul_temp_29_n_100,mul_temp_29_n_101,mul_temp_29_n_102,mul_temp_29_n_103,mul_temp_29_n_104,mul_temp_29_n_105}),
.PATTERNBDETECT(NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_29_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_29_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_3
(.A({\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_3_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[3]_2 [15],\weight_reg[3]_2 [15],\weight_reg[3]_2 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_3_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_3_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_3_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_3_P_UNCONNECTED[47:32],mul_temp_3_n_74,mul_temp_3_n_75,mul_temp_3_n_76,mul_temp_3_n_77,mul_temp_3_n_78,mul_temp_3_n_79,mul_temp_3_n_80,mul_temp_3_n_81,mul_temp_3_n_82,mul_temp_3_n_83,mul_temp_3_n_84,mul_temp_3_n_85,mul_temp_3_n_86,mul_temp_3_n_87,mul_temp_3_n_88,mul_temp_3_n_89,mul_temp_3_n_90,\^mul_temp_3 ,mul_temp_3_n_92,mul_temp_3_n_93,mul_temp_3_n_94,mul_temp_3_n_95,mul_temp_3_n_96,mul_temp_3_n_97,mul_temp_3_n_98,mul_temp_3_n_99,mul_temp_3_n_100,mul_temp_3_n_101,mul_temp_3_n_102,mul_temp_3_n_103,mul_temp_3_n_104,mul_temp_3_n_105}),
.PATTERNBDETECT(NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_3_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_3_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_30
(.A({\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_30_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_30_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_30_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_30_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_30_P_UNCONNECTED[47:32],mul_temp_30_n_74,mul_temp_30_n_75,mul_temp_30_n_76,mul_temp_30_n_77,mul_temp_30_n_78,mul_temp_30_n_79,mul_temp_30_n_80,mul_temp_30_n_81,mul_temp_30_n_82,mul_temp_30_n_83,mul_temp_30_n_84,mul_temp_30_n_85,mul_temp_30_n_86,mul_temp_30_n_87,mul_temp_30_n_88,mul_temp_30_n_89,mul_temp_30_n_90,\^mul_temp_30 ,mul_temp_30_n_92,mul_temp_30_n_93,mul_temp_30_n_94,mul_temp_30_n_95,mul_temp_30_n_96,mul_temp_30_n_97,mul_temp_30_n_98,mul_temp_30_n_99,mul_temp_30_n_100,mul_temp_30_n_101,mul_temp_30_n_102,mul_temp_30_n_103,mul_temp_30_n_104,mul_temp_30_n_105}),
.PATTERNBDETECT(NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_30_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_30_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_31
(.A({\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_31_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_31_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_31_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_31_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_31_P_UNCONNECTED[47:32],mul_temp_31_n_74,mul_temp_31_n_75,mul_temp_31_n_76,mul_temp_31_n_77,mul_temp_31_n_78,mul_temp_31_n_79,mul_temp_31_n_80,mul_temp_31_n_81,mul_temp_31_n_82,mul_temp_31_n_83,mul_temp_31_n_84,mul_temp_31_n_85,mul_temp_31_n_86,mul_temp_31_n_87,mul_temp_31_n_88,mul_temp_31_n_89,mul_temp_31_n_90,\^mul_temp_31 ,mul_temp_31_n_92,mul_temp_31_n_93,mul_temp_31_n_94,mul_temp_31_n_95,mul_temp_31_n_96,mul_temp_31_n_97,mul_temp_31_n_98,mul_temp_31_n_99,mul_temp_31_n_100,mul_temp_31_n_101,mul_temp_31_n_102,mul_temp_31_n_103,mul_temp_31_n_104,mul_temp_31_n_105}),
.PATTERNBDETECT(NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_31_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_31_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_32
(.A({\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_32_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_32_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_32_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_32_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_32_P_UNCONNECTED[47:32],mul_temp_32_n_74,mul_temp_32_n_75,mul_temp_32_n_76,mul_temp_32_n_77,mul_temp_32_n_78,mul_temp_32_n_79,mul_temp_32_n_80,mul_temp_32_n_81,mul_temp_32_n_82,mul_temp_32_n_83,mul_temp_32_n_84,mul_temp_32_n_85,mul_temp_32_n_86,mul_temp_32_n_87,mul_temp_32_n_88,mul_temp_32_n_89,mul_temp_32_n_90,\^mul_temp_32 ,mul_temp_32_n_92,mul_temp_32_n_93,mul_temp_32_n_94,mul_temp_32_n_95,mul_temp_32_n_96,mul_temp_32_n_97,mul_temp_32_n_98,mul_temp_32_n_99,mul_temp_32_n_100,mul_temp_32_n_101,mul_temp_32_n_102,mul_temp_32_n_103,mul_temp_32_n_104,mul_temp_32_n_105}),
.PATTERNBDETECT(NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_32_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_32_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_4
(.A({\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_4_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[4]_3 [15],\weight_reg[4]_3 [15],\weight_reg[4]_3 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_4_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_4_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_4_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_4_P_UNCONNECTED[47:32],mul_temp_4_n_74,mul_temp_4_n_75,mul_temp_4_n_76,mul_temp_4_n_77,mul_temp_4_n_78,mul_temp_4_n_79,mul_temp_4_n_80,mul_temp_4_n_81,mul_temp_4_n_82,mul_temp_4_n_83,mul_temp_4_n_84,mul_temp_4_n_85,mul_temp_4_n_86,mul_temp_4_n_87,mul_temp_4_n_88,mul_temp_4_n_89,mul_temp_4_n_90,\^mul_temp_4 ,mul_temp_4_n_92,mul_temp_4_n_93,mul_temp_4_n_94,mul_temp_4_n_95,mul_temp_4_n_96,mul_temp_4_n_97,mul_temp_4_n_98,mul_temp_4_n_99,mul_temp_4_n_100,mul_temp_4_n_101,mul_temp_4_n_102,mul_temp_4_n_103,mul_temp_4_n_104,mul_temp_4_n_105}),
.PATTERNBDETECT(NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_4_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_4_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_5
(.A({\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_5_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[5]_4 [15],\weight_reg[5]_4 [15],\weight_reg[5]_4 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_5_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_5_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_5_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_5_P_UNCONNECTED[47:32],mul_temp_5_n_74,mul_temp_5_n_75,mul_temp_5_n_76,mul_temp_5_n_77,mul_temp_5_n_78,mul_temp_5_n_79,mul_temp_5_n_80,mul_temp_5_n_81,mul_temp_5_n_82,mul_temp_5_n_83,mul_temp_5_n_84,mul_temp_5_n_85,mul_temp_5_n_86,mul_temp_5_n_87,mul_temp_5_n_88,mul_temp_5_n_89,mul_temp_5_n_90,\^mul_temp_5 ,mul_temp_5_n_92,mul_temp_5_n_93,mul_temp_5_n_94,mul_temp_5_n_95,mul_temp_5_n_96,mul_temp_5_n_97,mul_temp_5_n_98,mul_temp_5_n_99,mul_temp_5_n_100,mul_temp_5_n_101,mul_temp_5_n_102,mul_temp_5_n_103,mul_temp_5_n_104,mul_temp_5_n_105}),
.PATTERNBDETECT(NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_5_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_5_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_6
(.A({\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_6_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[6]_5 [15],\weight_reg[6]_5 [15],\weight_reg[6]_5 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_6_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_6_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_6_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_6_P_UNCONNECTED[47:32],mul_temp_6_n_74,mul_temp_6_n_75,mul_temp_6_n_76,mul_temp_6_n_77,mul_temp_6_n_78,mul_temp_6_n_79,mul_temp_6_n_80,mul_temp_6_n_81,mul_temp_6_n_82,mul_temp_6_n_83,mul_temp_6_n_84,mul_temp_6_n_85,mul_temp_6_n_86,mul_temp_6_n_87,mul_temp_6_n_88,mul_temp_6_n_89,mul_temp_6_n_90,\^mul_temp_6 ,mul_temp_6_n_92,mul_temp_6_n_93,mul_temp_6_n_94,mul_temp_6_n_95,mul_temp_6_n_96,mul_temp_6_n_97,mul_temp_6_n_98,mul_temp_6_n_99,mul_temp_6_n_100,mul_temp_6_n_101,mul_temp_6_n_102,mul_temp_6_n_103,mul_temp_6_n_104,mul_temp_6_n_105}),
.PATTERNBDETECT(NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_6_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_6_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_7
(.A({\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_7_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[7]_6 [15],\weight_reg[7]_6 [15],\weight_reg[7]_6 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_7_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_7_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_7_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_7_P_UNCONNECTED[47:32],mul_temp_7_n_74,mul_temp_7_n_75,mul_temp_7_n_76,mul_temp_7_n_77,mul_temp_7_n_78,mul_temp_7_n_79,mul_temp_7_n_80,mul_temp_7_n_81,mul_temp_7_n_82,mul_temp_7_n_83,mul_temp_7_n_84,mul_temp_7_n_85,mul_temp_7_n_86,mul_temp_7_n_87,mul_temp_7_n_88,mul_temp_7_n_89,mul_temp_7_n_90,\^mul_temp_7 ,mul_temp_7_n_92,mul_temp_7_n_93,mul_temp_7_n_94,mul_temp_7_n_95,mul_temp_7_n_96,mul_temp_7_n_97,mul_temp_7_n_98,mul_temp_7_n_99,mul_temp_7_n_100,mul_temp_7_n_101,mul_temp_7_n_102,mul_temp_7_n_103,mul_temp_7_n_104,mul_temp_7_n_105}),
.PATTERNBDETECT(NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_7_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_7_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_8
(.A({\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_8_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[8]_7 [15],\weight_reg[8]_7 [15],\weight_reg[8]_7 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_8_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_8_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_8_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_8_P_UNCONNECTED[47:32],mul_temp_8_n_74,mul_temp_8_n_75,mul_temp_8_n_76,mul_temp_8_n_77,mul_temp_8_n_78,mul_temp_8_n_79,mul_temp_8_n_80,mul_temp_8_n_81,mul_temp_8_n_82,mul_temp_8_n_83,mul_temp_8_n_84,mul_temp_8_n_85,mul_temp_8_n_86,mul_temp_8_n_87,mul_temp_8_n_88,mul_temp_8_n_89,mul_temp_8_n_90,\^mul_temp_8 ,mul_temp_8_n_92,mul_temp_8_n_93,mul_temp_8_n_94,mul_temp_8_n_95,mul_temp_8_n_96,mul_temp_8_n_97,mul_temp_8_n_98,mul_temp_8_n_99,mul_temp_8_n_100,mul_temp_8_n_101,mul_temp_8_n_102,mul_temp_8_n_103,mul_temp_8_n_104,mul_temp_8_n_105}),
.PATTERNBDETECT(NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_8_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_8_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_9
(.A({\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_9_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[9]_8 [15],\weight_reg[9]_8 [15],\weight_reg[9]_8 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_9_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_9_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_9_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_9_P_UNCONNECTED[47:32],mul_temp_9_n_74,mul_temp_9_n_75,mul_temp_9_n_76,mul_temp_9_n_77,mul_temp_9_n_78,mul_temp_9_n_79,mul_temp_9_n_80,mul_temp_9_n_81,mul_temp_9_n_82,mul_temp_9_n_83,mul_temp_9_n_84,mul_temp_9_n_85,mul_temp_9_n_86,mul_temp_9_n_87,mul_temp_9_n_88,mul_temp_9_n_89,mul_temp_9_n_90,\^mul_temp_9 ,mul_temp_9_n_92,mul_temp_9_n_93,mul_temp_9_n_94,mul_temp_9_n_95,mul_temp_9_n_96,mul_temp_9_n_97,mul_temp_9_n_98,mul_temp_9_n_99,mul_temp_9_n_100,mul_temp_9_n_101,mul_temp_9_n_102,mul_temp_9_n_103,mul_temp_9_n_104,mul_temp_9_n_105}),
.PATTERNBDETECT(NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_9_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_9_UNDERFLOW_UNCONNECTED));
CARRY4 sub_temp_carry
(.CI(1'b0),
.CO({sub_temp_carry_n_0,sub_temp_carry_n_1,sub_temp_carry_n_2,sub_temp_carry_n_3}),
.CYINIT(1'b1),
.DI(Q[3:0]),
.O(mul_temp_16[3:0]),
.S(\write_reg_d_k_reg[3]_0 ));
CARRY4 sub_temp_carry__0
(.CI(sub_temp_carry_n_0),
.CO({sub_temp_carry__0_n_0,sub_temp_carry__0_n_1,sub_temp_carry__0_n_2,sub_temp_carry__0_n_3}),
.CYINIT(1'b0),
.DI(Q[7:4]),
.O(mul_temp_16[7:4]),
.S(\write_reg_d_k_reg[7] ));
CARRY4 sub_temp_carry__1
(.CI(sub_temp_carry__0_n_0),
.CO({sub_temp_carry__1_n_0,sub_temp_carry__1_n_1,sub_temp_carry__1_n_2,sub_temp_carry__1_n_3}),
.CYINIT(1'b0),
.DI(Q[11:8]),
.O(mul_temp_16[11:8]),
.S(\write_reg_d_k_reg[11] ));
CARRY4 sub_temp_carry__2
(.CI(sub_temp_carry__1_n_0),
.CO({NLW_sub_temp_carry__2_CO_UNCONNECTED[3],sub_temp_carry__2_n_1,sub_temp_carry__2_n_2,sub_temp_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Q[14:12]}),
.O(mul_temp_16[15:12]),
.S(S));
LUT2 #(
.INIT(4'h6))
\weight[0][0]_i_2
(.I0(ARG__29_n_88),
.I1(\weight_reg[0]_15 [3]),
.O(\weight[0][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][0]_i_3
(.I0(ARG__29_n_89),
.I1(\weight_reg[0]_15 [2]),
.O(\weight[0][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][0]_i_4
(.I0(ARG__29_n_90),
.I1(\weight_reg[0]_15 [1]),
.O(\weight[0][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][0]_i_5
(.I0(ARG__29_n_91),
.I1(\weight_reg[0]_15 [0]),
.O(\weight[0][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][12]_i_2
(.I0(ARG__29_n_76),
.I1(\weight_reg[0]_15 [15]),
.O(\weight[0][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][12]_i_3
(.I0(ARG__29_n_77),
.I1(\weight_reg[0]_15 [14]),
.O(\weight[0][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][12]_i_4
(.I0(ARG__29_n_78),
.I1(\weight_reg[0]_15 [13]),
.O(\weight[0][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][12]_i_5
(.I0(ARG__29_n_79),
.I1(\weight_reg[0]_15 [12]),
.O(\weight[0][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][4]_i_2
(.I0(ARG__29_n_84),
.I1(\weight_reg[0]_15 [7]),
.O(\weight[0][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][4]_i_3
(.I0(ARG__29_n_85),
.I1(\weight_reg[0]_15 [6]),
.O(\weight[0][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][4]_i_4
(.I0(ARG__29_n_86),
.I1(\weight_reg[0]_15 [5]),
.O(\weight[0][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][4]_i_5
(.I0(ARG__29_n_87),
.I1(\weight_reg[0]_15 [4]),
.O(\weight[0][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][8]_i_2
(.I0(ARG__29_n_80),
.I1(\weight_reg[0]_15 [11]),
.O(\weight[0][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][8]_i_3
(.I0(ARG__29_n_81),
.I1(\weight_reg[0]_15 [10]),
.O(\weight[0][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][8]_i_4
(.I0(ARG__29_n_82),
.I1(\weight_reg[0]_15 [9]),
.O(\weight[0][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][8]_i_5
(.I0(ARG__29_n_83),
.I1(\weight_reg[0]_15 [8]),
.O(\weight[0][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][0]_i_2
(.I0(ARG__17_n_88),
.I1(\weight_reg[10]_9 [3]),
.O(\weight[10][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][0]_i_3
(.I0(ARG__17_n_89),
.I1(\weight_reg[10]_9 [2]),
.O(\weight[10][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][0]_i_4
(.I0(ARG__17_n_90),
.I1(\weight_reg[10]_9 [1]),
.O(\weight[10][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][0]_i_5
(.I0(ARG__17_n_91),
.I1(\weight_reg[10]_9 [0]),
.O(\weight[10][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][12]_i_2
(.I0(ARG__17_n_76),
.I1(\weight_reg[10]_9 [15]),
.O(\weight[10][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][12]_i_3
(.I0(ARG__17_n_77),
.I1(\weight_reg[10]_9 [14]),
.O(\weight[10][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][12]_i_4
(.I0(ARG__17_n_78),
.I1(\weight_reg[10]_9 [13]),
.O(\weight[10][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][12]_i_5
(.I0(ARG__17_n_79),
.I1(\weight_reg[10]_9 [12]),
.O(\weight[10][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][4]_i_2
(.I0(ARG__17_n_84),
.I1(\weight_reg[10]_9 [7]),
.O(\weight[10][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][4]_i_3
(.I0(ARG__17_n_85),
.I1(\weight_reg[10]_9 [6]),
.O(\weight[10][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][4]_i_4
(.I0(ARG__17_n_86),
.I1(\weight_reg[10]_9 [5]),
.O(\weight[10][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][4]_i_5
(.I0(ARG__17_n_87),
.I1(\weight_reg[10]_9 [4]),
.O(\weight[10][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][8]_i_2
(.I0(ARG__17_n_80),
.I1(\weight_reg[10]_9 [11]),
.O(\weight[10][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][8]_i_3
(.I0(ARG__17_n_81),
.I1(\weight_reg[10]_9 [10]),
.O(\weight[10][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][8]_i_4
(.I0(ARG__17_n_82),
.I1(\weight_reg[10]_9 [9]),
.O(\weight[10][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][8]_i_5
(.I0(ARG__17_n_83),
.I1(\weight_reg[10]_9 [8]),
.O(\weight[10][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][0]_i_2
(.I0(ARG__19_n_88),
.I1(\weight_reg[11]_10 [3]),
.O(\weight[11][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][0]_i_3
(.I0(ARG__19_n_89),
.I1(\weight_reg[11]_10 [2]),
.O(\weight[11][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][0]_i_4
(.I0(ARG__19_n_90),
.I1(\weight_reg[11]_10 [1]),
.O(\weight[11][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][0]_i_5
(.I0(ARG__19_n_91),
.I1(\weight_reg[11]_10 [0]),
.O(\weight[11][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][12]_i_2
(.I0(ARG__19_n_76),
.I1(\weight_reg[11]_10 [15]),
.O(\weight[11][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][12]_i_3
(.I0(ARG__19_n_77),
.I1(\weight_reg[11]_10 [14]),
.O(\weight[11][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][12]_i_4
(.I0(ARG__19_n_78),
.I1(\weight_reg[11]_10 [13]),
.O(\weight[11][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][12]_i_5
(.I0(ARG__19_n_79),
.I1(\weight_reg[11]_10 [12]),
.O(\weight[11][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][4]_i_2
(.I0(ARG__19_n_84),
.I1(\weight_reg[11]_10 [7]),
.O(\weight[11][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][4]_i_3
(.I0(ARG__19_n_85),
.I1(\weight_reg[11]_10 [6]),
.O(\weight[11][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][4]_i_4
(.I0(ARG__19_n_86),
.I1(\weight_reg[11]_10 [5]),
.O(\weight[11][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][4]_i_5
(.I0(ARG__19_n_87),
.I1(\weight_reg[11]_10 [4]),
.O(\weight[11][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][8]_i_2
(.I0(ARG__19_n_80),
.I1(\weight_reg[11]_10 [11]),
.O(\weight[11][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][8]_i_3
(.I0(ARG__19_n_81),
.I1(\weight_reg[11]_10 [10]),
.O(\weight[11][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][8]_i_4
(.I0(ARG__19_n_82),
.I1(\weight_reg[11]_10 [9]),
.O(\weight[11][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][8]_i_5
(.I0(ARG__19_n_83),
.I1(\weight_reg[11]_10 [8]),
.O(\weight[11][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][0]_i_2
(.I0(ARG__21_n_88),
.I1(\weight_reg[12]_11 [3]),
.O(\weight[12][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][0]_i_3
(.I0(ARG__21_n_89),
.I1(\weight_reg[12]_11 [2]),
.O(\weight[12][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][0]_i_4
(.I0(ARG__21_n_90),
.I1(\weight_reg[12]_11 [1]),
.O(\weight[12][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][0]_i_5
(.I0(ARG__21_n_91),
.I1(\weight_reg[12]_11 [0]),
.O(\weight[12][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][12]_i_2
(.I0(ARG__21_n_76),
.I1(\weight_reg[12]_11 [15]),
.O(\weight[12][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][12]_i_3
(.I0(ARG__21_n_77),
.I1(\weight_reg[12]_11 [14]),
.O(\weight[12][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][12]_i_4
(.I0(ARG__21_n_78),
.I1(\weight_reg[12]_11 [13]),
.O(\weight[12][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][12]_i_5
(.I0(ARG__21_n_79),
.I1(\weight_reg[12]_11 [12]),
.O(\weight[12][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][4]_i_2
(.I0(ARG__21_n_84),
.I1(\weight_reg[12]_11 [7]),
.O(\weight[12][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][4]_i_3
(.I0(ARG__21_n_85),
.I1(\weight_reg[12]_11 [6]),
.O(\weight[12][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][4]_i_4
(.I0(ARG__21_n_86),
.I1(\weight_reg[12]_11 [5]),
.O(\weight[12][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][4]_i_5
(.I0(ARG__21_n_87),
.I1(\weight_reg[12]_11 [4]),
.O(\weight[12][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][8]_i_2
(.I0(ARG__21_n_80),
.I1(\weight_reg[12]_11 [11]),
.O(\weight[12][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][8]_i_3
(.I0(ARG__21_n_81),
.I1(\weight_reg[12]_11 [10]),
.O(\weight[12][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][8]_i_4
(.I0(ARG__21_n_82),
.I1(\weight_reg[12]_11 [9]),
.O(\weight[12][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][8]_i_5
(.I0(ARG__21_n_83),
.I1(\weight_reg[12]_11 [8]),
.O(\weight[12][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][0]_i_2
(.I0(ARG__23_n_88),
.I1(\weight_reg[13]_12 [3]),
.O(\weight[13][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][0]_i_3
(.I0(ARG__23_n_89),
.I1(\weight_reg[13]_12 [2]),
.O(\weight[13][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][0]_i_4
(.I0(ARG__23_n_90),
.I1(\weight_reg[13]_12 [1]),
.O(\weight[13][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][0]_i_5
(.I0(ARG__23_n_91),
.I1(\weight_reg[13]_12 [0]),
.O(\weight[13][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][12]_i_2
(.I0(ARG__23_n_76),
.I1(\weight_reg[13]_12 [15]),
.O(\weight[13][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][12]_i_3
(.I0(ARG__23_n_77),
.I1(\weight_reg[13]_12 [14]),
.O(\weight[13][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][12]_i_4
(.I0(ARG__23_n_78),
.I1(\weight_reg[13]_12 [13]),
.O(\weight[13][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][12]_i_5
(.I0(ARG__23_n_79),
.I1(\weight_reg[13]_12 [12]),
.O(\weight[13][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][4]_i_2
(.I0(ARG__23_n_84),
.I1(\weight_reg[13]_12 [7]),
.O(\weight[13][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][4]_i_3
(.I0(ARG__23_n_85),
.I1(\weight_reg[13]_12 [6]),
.O(\weight[13][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][4]_i_4
(.I0(ARG__23_n_86),
.I1(\weight_reg[13]_12 [5]),
.O(\weight[13][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][4]_i_5
(.I0(ARG__23_n_87),
.I1(\weight_reg[13]_12 [4]),
.O(\weight[13][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][8]_i_2
(.I0(ARG__23_n_80),
.I1(\weight_reg[13]_12 [11]),
.O(\weight[13][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][8]_i_3
(.I0(ARG__23_n_81),
.I1(\weight_reg[13]_12 [10]),
.O(\weight[13][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][8]_i_4
(.I0(ARG__23_n_82),
.I1(\weight_reg[13]_12 [9]),
.O(\weight[13][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][8]_i_5
(.I0(ARG__23_n_83),
.I1(\weight_reg[13]_12 [8]),
.O(\weight[13][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][0]_i_2
(.I0(ARG__25_n_88),
.I1(\weight_reg[14]_13 [3]),
.O(\weight[14][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][0]_i_3
(.I0(ARG__25_n_89),
.I1(\weight_reg[14]_13 [2]),
.O(\weight[14][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][0]_i_4
(.I0(ARG__25_n_90),
.I1(\weight_reg[14]_13 [1]),
.O(\weight[14][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][0]_i_5
(.I0(ARG__25_n_91),
.I1(\weight_reg[14]_13 [0]),
.O(\weight[14][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][12]_i_2
(.I0(ARG__25_n_76),
.I1(\weight_reg[14]_13 [15]),
.O(\weight[14][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][12]_i_3
(.I0(ARG__25_n_77),
.I1(\weight_reg[14]_13 [14]),
.O(\weight[14][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][12]_i_4
(.I0(ARG__25_n_78),
.I1(\weight_reg[14]_13 [13]),
.O(\weight[14][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][12]_i_5
(.I0(ARG__25_n_79),
.I1(\weight_reg[14]_13 [12]),
.O(\weight[14][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][4]_i_2
(.I0(ARG__25_n_84),
.I1(\weight_reg[14]_13 [7]),
.O(\weight[14][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][4]_i_3
(.I0(ARG__25_n_85),
.I1(\weight_reg[14]_13 [6]),
.O(\weight[14][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][4]_i_4
(.I0(ARG__25_n_86),
.I1(\weight_reg[14]_13 [5]),
.O(\weight[14][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][4]_i_5
(.I0(ARG__25_n_87),
.I1(\weight_reg[14]_13 [4]),
.O(\weight[14][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][8]_i_2
(.I0(ARG__25_n_80),
.I1(\weight_reg[14]_13 [11]),
.O(\weight[14][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][8]_i_3
(.I0(ARG__25_n_81),
.I1(\weight_reg[14]_13 [10]),
.O(\weight[14][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][8]_i_4
(.I0(ARG__25_n_82),
.I1(\weight_reg[14]_13 [9]),
.O(\weight[14][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][8]_i_5
(.I0(ARG__25_n_83),
.I1(\weight_reg[14]_13 [8]),
.O(\weight[14][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][0]_i_2
(.I0(ARG__27_n_88),
.I1(\weight_reg[15]_14 [3]),
.O(\weight[15][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][0]_i_3
(.I0(ARG__27_n_89),
.I1(\weight_reg[15]_14 [2]),
.O(\weight[15][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][0]_i_4
(.I0(ARG__27_n_90),
.I1(\weight_reg[15]_14 [1]),
.O(\weight[15][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][0]_i_5
(.I0(ARG__27_n_91),
.I1(\weight_reg[15]_14 [0]),
.O(\weight[15][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][12]_i_2
(.I0(ARG__27_n_76),
.I1(\weight_reg[15]_14 [15]),
.O(\weight[15][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][12]_i_3
(.I0(ARG__27_n_77),
.I1(\weight_reg[15]_14 [14]),
.O(\weight[15][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][12]_i_4
(.I0(ARG__27_n_78),
.I1(\weight_reg[15]_14 [13]),
.O(\weight[15][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][12]_i_5
(.I0(ARG__27_n_79),
.I1(\weight_reg[15]_14 [12]),
.O(\weight[15][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][4]_i_2
(.I0(ARG__27_n_84),
.I1(\weight_reg[15]_14 [7]),
.O(\weight[15][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][4]_i_3
(.I0(ARG__27_n_85),
.I1(\weight_reg[15]_14 [6]),
.O(\weight[15][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][4]_i_4
(.I0(ARG__27_n_86),
.I1(\weight_reg[15]_14 [5]),
.O(\weight[15][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][4]_i_5
(.I0(ARG__27_n_87),
.I1(\weight_reg[15]_14 [4]),
.O(\weight[15][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][8]_i_2
(.I0(ARG__27_n_80),
.I1(\weight_reg[15]_14 [11]),
.O(\weight[15][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][8]_i_3
(.I0(ARG__27_n_81),
.I1(\weight_reg[15]_14 [10]),
.O(\weight[15][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][8]_i_4
(.I0(ARG__27_n_82),
.I1(\weight_reg[15]_14 [9]),
.O(\weight[15][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][8]_i_5
(.I0(ARG__27_n_83),
.I1(\weight_reg[15]_14 [8]),
.O(\weight[15][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][0]_i_2
(.I0(in[3]),
.I1(\weight_reg[1]_0 [3]),
.O(\weight[1][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][0]_i_3
(.I0(in[2]),
.I1(\weight_reg[1]_0 [2]),
.O(\weight[1][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][0]_i_4
(.I0(in[1]),
.I1(\weight_reg[1]_0 [1]),
.O(\weight[1][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][0]_i_5
(.I0(in[0]),
.I1(\weight_reg[1]_0 [0]),
.O(\weight[1][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][12]_i_2
(.I0(in[15]),
.I1(\weight_reg[1]_0 [15]),
.O(\weight[1][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][12]_i_3
(.I0(in[14]),
.I1(\weight_reg[1]_0 [14]),
.O(\weight[1][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][12]_i_4
(.I0(in[13]),
.I1(\weight_reg[1]_0 [13]),
.O(\weight[1][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][12]_i_5
(.I0(in[12]),
.I1(\weight_reg[1]_0 [12]),
.O(\weight[1][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][4]_i_2
(.I0(in[7]),
.I1(\weight_reg[1]_0 [7]),
.O(\weight[1][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][4]_i_3
(.I0(in[6]),
.I1(\weight_reg[1]_0 [6]),
.O(\weight[1][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][4]_i_4
(.I0(in[5]),
.I1(\weight_reg[1]_0 [5]),
.O(\weight[1][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][4]_i_5
(.I0(in[4]),
.I1(\weight_reg[1]_0 [4]),
.O(\weight[1][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][8]_i_2
(.I0(in[11]),
.I1(\weight_reg[1]_0 [11]),
.O(\weight[1][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][8]_i_3
(.I0(in[10]),
.I1(\weight_reg[1]_0 [10]),
.O(\weight[1][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][8]_i_4
(.I0(in[9]),
.I1(\weight_reg[1]_0 [9]),
.O(\weight[1][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][8]_i_5
(.I0(in[8]),
.I1(\weight_reg[1]_0 [8]),
.O(\weight[1][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][0]_i_2
(.I0(ARG__1_n_88),
.I1(\weight_reg[2]_1 [3]),
.O(\weight[2][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][0]_i_3
(.I0(ARG__1_n_89),
.I1(\weight_reg[2]_1 [2]),
.O(\weight[2][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][0]_i_4
(.I0(ARG__1_n_90),
.I1(\weight_reg[2]_1 [1]),
.O(\weight[2][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][0]_i_5
(.I0(ARG__1_n_91),
.I1(\weight_reg[2]_1 [0]),
.O(\weight[2][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][12]_i_2
(.I0(ARG__1_n_76),
.I1(\weight_reg[2]_1 [15]),
.O(\weight[2][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][12]_i_3
(.I0(ARG__1_n_77),
.I1(\weight_reg[2]_1 [14]),
.O(\weight[2][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][12]_i_4
(.I0(ARG__1_n_78),
.I1(\weight_reg[2]_1 [13]),
.O(\weight[2][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][12]_i_5
(.I0(ARG__1_n_79),
.I1(\weight_reg[2]_1 [12]),
.O(\weight[2][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][4]_i_2
(.I0(ARG__1_n_84),
.I1(\weight_reg[2]_1 [7]),
.O(\weight[2][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][4]_i_3
(.I0(ARG__1_n_85),
.I1(\weight_reg[2]_1 [6]),
.O(\weight[2][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][4]_i_4
(.I0(ARG__1_n_86),
.I1(\weight_reg[2]_1 [5]),
.O(\weight[2][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][4]_i_5
(.I0(ARG__1_n_87),
.I1(\weight_reg[2]_1 [4]),
.O(\weight[2][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][8]_i_2
(.I0(ARG__1_n_80),
.I1(\weight_reg[2]_1 [11]),
.O(\weight[2][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][8]_i_3
(.I0(ARG__1_n_81),
.I1(\weight_reg[2]_1 [10]),
.O(\weight[2][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][8]_i_4
(.I0(ARG__1_n_82),
.I1(\weight_reg[2]_1 [9]),
.O(\weight[2][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][8]_i_5
(.I0(ARG__1_n_83),
.I1(\weight_reg[2]_1 [8]),
.O(\weight[2][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][0]_i_2
(.I0(ARG__3_n_88),
.I1(\weight_reg[3]_2 [3]),
.O(\weight[3][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][0]_i_3
(.I0(ARG__3_n_89),
.I1(\weight_reg[3]_2 [2]),
.O(\weight[3][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][0]_i_4
(.I0(ARG__3_n_90),
.I1(\weight_reg[3]_2 [1]),
.O(\weight[3][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][0]_i_5
(.I0(ARG__3_n_91),
.I1(\weight_reg[3]_2 [0]),
.O(\weight[3][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][12]_i_2
(.I0(ARG__3_n_76),
.I1(\weight_reg[3]_2 [15]),
.O(\weight[3][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][12]_i_3
(.I0(ARG__3_n_77),
.I1(\weight_reg[3]_2 [14]),
.O(\weight[3][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][12]_i_4
(.I0(ARG__3_n_78),
.I1(\weight_reg[3]_2 [13]),
.O(\weight[3][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][12]_i_5
(.I0(ARG__3_n_79),
.I1(\weight_reg[3]_2 [12]),
.O(\weight[3][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][4]_i_2
(.I0(ARG__3_n_84),
.I1(\weight_reg[3]_2 [7]),
.O(\weight[3][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][4]_i_3
(.I0(ARG__3_n_85),
.I1(\weight_reg[3]_2 [6]),
.O(\weight[3][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][4]_i_4
(.I0(ARG__3_n_86),
.I1(\weight_reg[3]_2 [5]),
.O(\weight[3][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][4]_i_5
(.I0(ARG__3_n_87),
.I1(\weight_reg[3]_2 [4]),
.O(\weight[3][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][8]_i_2
(.I0(ARG__3_n_80),
.I1(\weight_reg[3]_2 [11]),
.O(\weight[3][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][8]_i_3
(.I0(ARG__3_n_81),
.I1(\weight_reg[3]_2 [10]),
.O(\weight[3][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][8]_i_4
(.I0(ARG__3_n_82),
.I1(\weight_reg[3]_2 [9]),
.O(\weight[3][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][8]_i_5
(.I0(ARG__3_n_83),
.I1(\weight_reg[3]_2 [8]),
.O(\weight[3][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][0]_i_2
(.I0(ARG__5_n_88),
.I1(\weight_reg[4]_3 [3]),
.O(\weight[4][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][0]_i_3
(.I0(ARG__5_n_89),
.I1(\weight_reg[4]_3 [2]),
.O(\weight[4][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][0]_i_4
(.I0(ARG__5_n_90),
.I1(\weight_reg[4]_3 [1]),
.O(\weight[4][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][0]_i_5
(.I0(ARG__5_n_91),
.I1(\weight_reg[4]_3 [0]),
.O(\weight[4][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][12]_i_2
(.I0(ARG__5_n_76),
.I1(\weight_reg[4]_3 [15]),
.O(\weight[4][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][12]_i_3
(.I0(ARG__5_n_77),
.I1(\weight_reg[4]_3 [14]),
.O(\weight[4][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][12]_i_4
(.I0(ARG__5_n_78),
.I1(\weight_reg[4]_3 [13]),
.O(\weight[4][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][12]_i_5
(.I0(ARG__5_n_79),
.I1(\weight_reg[4]_3 [12]),
.O(\weight[4][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][4]_i_2
(.I0(ARG__5_n_84),
.I1(\weight_reg[4]_3 [7]),
.O(\weight[4][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][4]_i_3
(.I0(ARG__5_n_85),
.I1(\weight_reg[4]_3 [6]),
.O(\weight[4][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][4]_i_4
(.I0(ARG__5_n_86),
.I1(\weight_reg[4]_3 [5]),
.O(\weight[4][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][4]_i_5
(.I0(ARG__5_n_87),
.I1(\weight_reg[4]_3 [4]),
.O(\weight[4][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][8]_i_2
(.I0(ARG__5_n_80),
.I1(\weight_reg[4]_3 [11]),
.O(\weight[4][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][8]_i_3
(.I0(ARG__5_n_81),
.I1(\weight_reg[4]_3 [10]),
.O(\weight[4][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][8]_i_4
(.I0(ARG__5_n_82),
.I1(\weight_reg[4]_3 [9]),
.O(\weight[4][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][8]_i_5
(.I0(ARG__5_n_83),
.I1(\weight_reg[4]_3 [8]),
.O(\weight[4][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][0]_i_2
(.I0(ARG__7_n_88),
.I1(\weight_reg[5]_4 [3]),
.O(\weight[5][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][0]_i_3
(.I0(ARG__7_n_89),
.I1(\weight_reg[5]_4 [2]),
.O(\weight[5][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][0]_i_4
(.I0(ARG__7_n_90),
.I1(\weight_reg[5]_4 [1]),
.O(\weight[5][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][0]_i_5
(.I0(ARG__7_n_91),
.I1(\weight_reg[5]_4 [0]),
.O(\weight[5][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][12]_i_2
(.I0(ARG__7_n_76),
.I1(\weight_reg[5]_4 [15]),
.O(\weight[5][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][12]_i_3
(.I0(ARG__7_n_77),
.I1(\weight_reg[5]_4 [14]),
.O(\weight[5][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][12]_i_4
(.I0(ARG__7_n_78),
.I1(\weight_reg[5]_4 [13]),
.O(\weight[5][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][12]_i_5
(.I0(ARG__7_n_79),
.I1(\weight_reg[5]_4 [12]),
.O(\weight[5][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][4]_i_2
(.I0(ARG__7_n_84),
.I1(\weight_reg[5]_4 [7]),
.O(\weight[5][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][4]_i_3
(.I0(ARG__7_n_85),
.I1(\weight_reg[5]_4 [6]),
.O(\weight[5][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][4]_i_4
(.I0(ARG__7_n_86),
.I1(\weight_reg[5]_4 [5]),
.O(\weight[5][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][4]_i_5
(.I0(ARG__7_n_87),
.I1(\weight_reg[5]_4 [4]),
.O(\weight[5][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][8]_i_2
(.I0(ARG__7_n_80),
.I1(\weight_reg[5]_4 [11]),
.O(\weight[5][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][8]_i_3
(.I0(ARG__7_n_81),
.I1(\weight_reg[5]_4 [10]),
.O(\weight[5][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][8]_i_4
(.I0(ARG__7_n_82),
.I1(\weight_reg[5]_4 [9]),
.O(\weight[5][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][8]_i_5
(.I0(ARG__7_n_83),
.I1(\weight_reg[5]_4 [8]),
.O(\weight[5][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][0]_i_2
(.I0(ARG__9_n_88),
.I1(\weight_reg[6]_5 [3]),
.O(\weight[6][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][0]_i_3
(.I0(ARG__9_n_89),
.I1(\weight_reg[6]_5 [2]),
.O(\weight[6][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][0]_i_4
(.I0(ARG__9_n_90),
.I1(\weight_reg[6]_5 [1]),
.O(\weight[6][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][0]_i_5
(.I0(ARG__9_n_91),
.I1(\weight_reg[6]_5 [0]),
.O(\weight[6][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][12]_i_2
(.I0(ARG__9_n_76),
.I1(\weight_reg[6]_5 [15]),
.O(\weight[6][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][12]_i_3
(.I0(ARG__9_n_77),
.I1(\weight_reg[6]_5 [14]),
.O(\weight[6][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][12]_i_4
(.I0(ARG__9_n_78),
.I1(\weight_reg[6]_5 [13]),
.O(\weight[6][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][12]_i_5
(.I0(ARG__9_n_79),
.I1(\weight_reg[6]_5 [12]),
.O(\weight[6][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][4]_i_2
(.I0(ARG__9_n_84),
.I1(\weight_reg[6]_5 [7]),
.O(\weight[6][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][4]_i_3
(.I0(ARG__9_n_85),
.I1(\weight_reg[6]_5 [6]),
.O(\weight[6][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][4]_i_4
(.I0(ARG__9_n_86),
.I1(\weight_reg[6]_5 [5]),
.O(\weight[6][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][4]_i_5
(.I0(ARG__9_n_87),
.I1(\weight_reg[6]_5 [4]),
.O(\weight[6][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][8]_i_2
(.I0(ARG__9_n_80),
.I1(\weight_reg[6]_5 [11]),
.O(\weight[6][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][8]_i_3
(.I0(ARG__9_n_81),
.I1(\weight_reg[6]_5 [10]),
.O(\weight[6][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][8]_i_4
(.I0(ARG__9_n_82),
.I1(\weight_reg[6]_5 [9]),
.O(\weight[6][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][8]_i_5
(.I0(ARG__9_n_83),
.I1(\weight_reg[6]_5 [8]),
.O(\weight[6][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][0]_i_2
(.I0(ARG__11_n_88),
.I1(\weight_reg[7]_6 [3]),
.O(\weight[7][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][0]_i_3
(.I0(ARG__11_n_89),
.I1(\weight_reg[7]_6 [2]),
.O(\weight[7][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][0]_i_4
(.I0(ARG__11_n_90),
.I1(\weight_reg[7]_6 [1]),
.O(\weight[7][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][0]_i_5
(.I0(ARG__11_n_91),
.I1(\weight_reg[7]_6 [0]),
.O(\weight[7][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][12]_i_2
(.I0(ARG__11_n_76),
.I1(\weight_reg[7]_6 [15]),
.O(\weight[7][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][12]_i_3
(.I0(ARG__11_n_77),
.I1(\weight_reg[7]_6 [14]),
.O(\weight[7][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][12]_i_4
(.I0(ARG__11_n_78),
.I1(\weight_reg[7]_6 [13]),
.O(\weight[7][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][12]_i_5
(.I0(ARG__11_n_79),
.I1(\weight_reg[7]_6 [12]),
.O(\weight[7][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][4]_i_2
(.I0(ARG__11_n_84),
.I1(\weight_reg[7]_6 [7]),
.O(\weight[7][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][4]_i_3
(.I0(ARG__11_n_85),
.I1(\weight_reg[7]_6 [6]),
.O(\weight[7][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][4]_i_4
(.I0(ARG__11_n_86),
.I1(\weight_reg[7]_6 [5]),
.O(\weight[7][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][4]_i_5
(.I0(ARG__11_n_87),
.I1(\weight_reg[7]_6 [4]),
.O(\weight[7][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][8]_i_2
(.I0(ARG__11_n_80),
.I1(\weight_reg[7]_6 [11]),
.O(\weight[7][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][8]_i_3
(.I0(ARG__11_n_81),
.I1(\weight_reg[7]_6 [10]),
.O(\weight[7][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][8]_i_4
(.I0(ARG__11_n_82),
.I1(\weight_reg[7]_6 [9]),
.O(\weight[7][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][8]_i_5
(.I0(ARG__11_n_83),
.I1(\weight_reg[7]_6 [8]),
.O(\weight[7][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][0]_i_2
(.I0(ARG__13_n_88),
.I1(\weight_reg[8]_7 [3]),
.O(\weight[8][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][0]_i_3
(.I0(ARG__13_n_89),
.I1(\weight_reg[8]_7 [2]),
.O(\weight[8][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][0]_i_4
(.I0(ARG__13_n_90),
.I1(\weight_reg[8]_7 [1]),
.O(\weight[8][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][0]_i_5
(.I0(ARG__13_n_91),
.I1(\weight_reg[8]_7 [0]),
.O(\weight[8][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][12]_i_2
(.I0(ARG__13_n_76),
.I1(\weight_reg[8]_7 [15]),
.O(\weight[8][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][12]_i_3
(.I0(ARG__13_n_77),
.I1(\weight_reg[8]_7 [14]),
.O(\weight[8][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][12]_i_4
(.I0(ARG__13_n_78),
.I1(\weight_reg[8]_7 [13]),
.O(\weight[8][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][12]_i_5
(.I0(ARG__13_n_79),
.I1(\weight_reg[8]_7 [12]),
.O(\weight[8][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][4]_i_2
(.I0(ARG__13_n_84),
.I1(\weight_reg[8]_7 [7]),
.O(\weight[8][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][4]_i_3
(.I0(ARG__13_n_85),
.I1(\weight_reg[8]_7 [6]),
.O(\weight[8][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][4]_i_4
(.I0(ARG__13_n_86),
.I1(\weight_reg[8]_7 [5]),
.O(\weight[8][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][4]_i_5
(.I0(ARG__13_n_87),
.I1(\weight_reg[8]_7 [4]),
.O(\weight[8][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][8]_i_2
(.I0(ARG__13_n_80),
.I1(\weight_reg[8]_7 [11]),
.O(\weight[8][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][8]_i_3
(.I0(ARG__13_n_81),
.I1(\weight_reg[8]_7 [10]),
.O(\weight[8][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][8]_i_4
(.I0(ARG__13_n_82),
.I1(\weight_reg[8]_7 [9]),
.O(\weight[8][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][8]_i_5
(.I0(ARG__13_n_83),
.I1(\weight_reg[8]_7 [8]),
.O(\weight[8][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][0]_i_2
(.I0(ARG__15_n_88),
.I1(\weight_reg[9]_8 [3]),
.O(\weight[9][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][0]_i_3
(.I0(ARG__15_n_89),
.I1(\weight_reg[9]_8 [2]),
.O(\weight[9][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][0]_i_4
(.I0(ARG__15_n_90),
.I1(\weight_reg[9]_8 [1]),
.O(\weight[9][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][0]_i_5
(.I0(ARG__15_n_91),
.I1(\weight_reg[9]_8 [0]),
.O(\weight[9][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][12]_i_2
(.I0(ARG__15_n_76),
.I1(\weight_reg[9]_8 [15]),
.O(\weight[9][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][12]_i_3
(.I0(ARG__15_n_77),
.I1(\weight_reg[9]_8 [14]),
.O(\weight[9][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][12]_i_4
(.I0(ARG__15_n_78),
.I1(\weight_reg[9]_8 [13]),
.O(\weight[9][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][12]_i_5
(.I0(ARG__15_n_79),
.I1(\weight_reg[9]_8 [12]),
.O(\weight[9][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][4]_i_2
(.I0(ARG__15_n_84),
.I1(\weight_reg[9]_8 [7]),
.O(\weight[9][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][4]_i_3
(.I0(ARG__15_n_85),
.I1(\weight_reg[9]_8 [6]),
.O(\weight[9][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][4]_i_4
(.I0(ARG__15_n_86),
.I1(\weight_reg[9]_8 [5]),
.O(\weight[9][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][4]_i_5
(.I0(ARG__15_n_87),
.I1(\weight_reg[9]_8 [4]),
.O(\weight[9][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][8]_i_2
(.I0(ARG__15_n_80),
.I1(\weight_reg[9]_8 [11]),
.O(\weight[9][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][8]_i_3
(.I0(ARG__15_n_81),
.I1(\weight_reg[9]_8 [10]),
.O(\weight[9][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][8]_i_4
(.I0(ARG__15_n_82),
.I1(\weight_reg[9]_8 [9]),
.O(\weight[9][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][8]_i_5
(.I0(ARG__15_n_83),
.I1(\weight_reg[9]_8 [8]),
.O(\weight[9][8]_i_5_n_0 ));
FDCE \weight_reg[0][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][0]_i_1_n_7 ),
.Q(\weight_reg[0]_15 [0]));
CARRY4 \weight_reg[0][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[0][0]_i_1_n_0 ,\weight_reg[0][0]_i_1_n_1 ,\weight_reg[0][0]_i_1_n_2 ,\weight_reg[0][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__29_n_88,ARG__29_n_89,ARG__29_n_90,ARG__29_n_91}),
.O({\weight_reg[0][0]_i_1_n_4 ,\weight_reg[0][0]_i_1_n_5 ,\weight_reg[0][0]_i_1_n_6 ,\weight_reg[0][0]_i_1_n_7 }),
.S({\weight[0][0]_i_2_n_0 ,\weight[0][0]_i_3_n_0 ,\weight[0][0]_i_4_n_0 ,\weight[0][0]_i_5_n_0 }));
FDCE \weight_reg[0][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][8]_i_1_n_5 ),
.Q(\weight_reg[0]_15 [10]));
FDCE \weight_reg[0][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][8]_i_1_n_4 ),
.Q(\weight_reg[0]_15 [11]));
FDCE \weight_reg[0][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][12]_i_1_n_7 ),
.Q(\weight_reg[0]_15 [12]));
CARRY4 \weight_reg[0][12]_i_1
(.CI(\weight_reg[0][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED [3],\weight_reg[0][12]_i_1_n_1 ,\weight_reg[0][12]_i_1_n_2 ,\weight_reg[0][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__29_n_77,ARG__29_n_78,ARG__29_n_79}),
.O({\weight_reg[0][12]_i_1_n_4 ,\weight_reg[0][12]_i_1_n_5 ,\weight_reg[0][12]_i_1_n_6 ,\weight_reg[0][12]_i_1_n_7 }),
.S({\weight[0][12]_i_2_n_0 ,\weight[0][12]_i_3_n_0 ,\weight[0][12]_i_4_n_0 ,\weight[0][12]_i_5_n_0 }));
FDCE \weight_reg[0][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][12]_i_1_n_6 ),
.Q(\weight_reg[0]_15 [13]));
FDCE \weight_reg[0][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][12]_i_1_n_5 ),
.Q(\weight_reg[0]_15 [14]));
FDCE \weight_reg[0][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][12]_i_1_n_4 ),
.Q(\weight_reg[0]_15 [15]));
FDCE \weight_reg[0][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][0]_i_1_n_6 ),
.Q(\weight_reg[0]_15 [1]));
FDCE \weight_reg[0][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][0]_i_1_n_5 ),
.Q(\weight_reg[0]_15 [2]));
FDCE \weight_reg[0][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][0]_i_1_n_4 ),
.Q(\weight_reg[0]_15 [3]));
FDCE \weight_reg[0][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][4]_i_1_n_7 ),
.Q(\weight_reg[0]_15 [4]));
CARRY4 \weight_reg[0][4]_i_1
(.CI(\weight_reg[0][0]_i_1_n_0 ),
.CO({\weight_reg[0][4]_i_1_n_0 ,\weight_reg[0][4]_i_1_n_1 ,\weight_reg[0][4]_i_1_n_2 ,\weight_reg[0][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__29_n_84,ARG__29_n_85,ARG__29_n_86,ARG__29_n_87}),
.O({\weight_reg[0][4]_i_1_n_4 ,\weight_reg[0][4]_i_1_n_5 ,\weight_reg[0][4]_i_1_n_6 ,\weight_reg[0][4]_i_1_n_7 }),
.S({\weight[0][4]_i_2_n_0 ,\weight[0][4]_i_3_n_0 ,\weight[0][4]_i_4_n_0 ,\weight[0][4]_i_5_n_0 }));
FDCE \weight_reg[0][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][4]_i_1_n_6 ),
.Q(\weight_reg[0]_15 [5]));
FDCE \weight_reg[0][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][4]_i_1_n_5 ),
.Q(\weight_reg[0]_15 [6]));
FDCE \weight_reg[0][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][4]_i_1_n_4 ),
.Q(\weight_reg[0]_15 [7]));
FDCE \weight_reg[0][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][8]_i_1_n_7 ),
.Q(\weight_reg[0]_15 [8]));
CARRY4 \weight_reg[0][8]_i_1
(.CI(\weight_reg[0][4]_i_1_n_0 ),
.CO({\weight_reg[0][8]_i_1_n_0 ,\weight_reg[0][8]_i_1_n_1 ,\weight_reg[0][8]_i_1_n_2 ,\weight_reg[0][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__29_n_80,ARG__29_n_81,ARG__29_n_82,ARG__29_n_83}),
.O({\weight_reg[0][8]_i_1_n_4 ,\weight_reg[0][8]_i_1_n_5 ,\weight_reg[0][8]_i_1_n_6 ,\weight_reg[0][8]_i_1_n_7 }),
.S({\weight[0][8]_i_2_n_0 ,\weight[0][8]_i_3_n_0 ,\weight[0][8]_i_4_n_0 ,\weight[0][8]_i_5_n_0 }));
FDCE \weight_reg[0][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][8]_i_1_n_6 ),
.Q(\weight_reg[0]_15 [9]));
FDCE \weight_reg[10][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][0]_i_1_n_7 ),
.Q(\weight_reg[10]_9 [0]));
CARRY4 \weight_reg[10][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[10][0]_i_1_n_0 ,\weight_reg[10][0]_i_1_n_1 ,\weight_reg[10][0]_i_1_n_2 ,\weight_reg[10][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__17_n_88,ARG__17_n_89,ARG__17_n_90,ARG__17_n_91}),
.O({\weight_reg[10][0]_i_1_n_4 ,\weight_reg[10][0]_i_1_n_5 ,\weight_reg[10][0]_i_1_n_6 ,\weight_reg[10][0]_i_1_n_7 }),
.S({\weight[10][0]_i_2_n_0 ,\weight[10][0]_i_3_n_0 ,\weight[10][0]_i_4_n_0 ,\weight[10][0]_i_5_n_0 }));
FDCE \weight_reg[10][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][8]_i_1_n_5 ),
.Q(\weight_reg[10]_9 [10]));
FDCE \weight_reg[10][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][8]_i_1_n_4 ),
.Q(\weight_reg[10]_9 [11]));
FDCE \weight_reg[10][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][12]_i_1_n_7 ),
.Q(\weight_reg[10]_9 [12]));
CARRY4 \weight_reg[10][12]_i_1
(.CI(\weight_reg[10][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED [3],\weight_reg[10][12]_i_1_n_1 ,\weight_reg[10][12]_i_1_n_2 ,\weight_reg[10][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__17_n_77,ARG__17_n_78,ARG__17_n_79}),
.O({\weight_reg[10][12]_i_1_n_4 ,\weight_reg[10][12]_i_1_n_5 ,\weight_reg[10][12]_i_1_n_6 ,\weight_reg[10][12]_i_1_n_7 }),
.S({\weight[10][12]_i_2_n_0 ,\weight[10][12]_i_3_n_0 ,\weight[10][12]_i_4_n_0 ,\weight[10][12]_i_5_n_0 }));
FDCE \weight_reg[10][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][12]_i_1_n_6 ),
.Q(\weight_reg[10]_9 [13]));
FDCE \weight_reg[10][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][12]_i_1_n_5 ),
.Q(\weight_reg[10]_9 [14]));
FDCE \weight_reg[10][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][12]_i_1_n_4 ),
.Q(\weight_reg[10]_9 [15]));
FDCE \weight_reg[10][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][0]_i_1_n_6 ),
.Q(\weight_reg[10]_9 [1]));
FDCE \weight_reg[10][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][0]_i_1_n_5 ),
.Q(\weight_reg[10]_9 [2]));
FDCE \weight_reg[10][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][0]_i_1_n_4 ),
.Q(\weight_reg[10]_9 [3]));
FDCE \weight_reg[10][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][4]_i_1_n_7 ),
.Q(\weight_reg[10]_9 [4]));
CARRY4 \weight_reg[10][4]_i_1
(.CI(\weight_reg[10][0]_i_1_n_0 ),
.CO({\weight_reg[10][4]_i_1_n_0 ,\weight_reg[10][4]_i_1_n_1 ,\weight_reg[10][4]_i_1_n_2 ,\weight_reg[10][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__17_n_84,ARG__17_n_85,ARG__17_n_86,ARG__17_n_87}),
.O({\weight_reg[10][4]_i_1_n_4 ,\weight_reg[10][4]_i_1_n_5 ,\weight_reg[10][4]_i_1_n_6 ,\weight_reg[10][4]_i_1_n_7 }),
.S({\weight[10][4]_i_2_n_0 ,\weight[10][4]_i_3_n_0 ,\weight[10][4]_i_4_n_0 ,\weight[10][4]_i_5_n_0 }));
FDCE \weight_reg[10][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][4]_i_1_n_6 ),
.Q(\weight_reg[10]_9 [5]));
FDCE \weight_reg[10][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][4]_i_1_n_5 ),
.Q(\weight_reg[10]_9 [6]));
FDCE \weight_reg[10][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][4]_i_1_n_4 ),
.Q(\weight_reg[10]_9 [7]));
FDCE \weight_reg[10][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][8]_i_1_n_7 ),
.Q(\weight_reg[10]_9 [8]));
CARRY4 \weight_reg[10][8]_i_1
(.CI(\weight_reg[10][4]_i_1_n_0 ),
.CO({\weight_reg[10][8]_i_1_n_0 ,\weight_reg[10][8]_i_1_n_1 ,\weight_reg[10][8]_i_1_n_2 ,\weight_reg[10][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__17_n_80,ARG__17_n_81,ARG__17_n_82,ARG__17_n_83}),
.O({\weight_reg[10][8]_i_1_n_4 ,\weight_reg[10][8]_i_1_n_5 ,\weight_reg[10][8]_i_1_n_6 ,\weight_reg[10][8]_i_1_n_7 }),
.S({\weight[10][8]_i_2_n_0 ,\weight[10][8]_i_3_n_0 ,\weight[10][8]_i_4_n_0 ,\weight[10][8]_i_5_n_0 }));
FDCE \weight_reg[10][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][8]_i_1_n_6 ),
.Q(\weight_reg[10]_9 [9]));
FDCE \weight_reg[11][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][0]_i_1_n_7 ),
.Q(\weight_reg[11]_10 [0]));
CARRY4 \weight_reg[11][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[11][0]_i_1_n_0 ,\weight_reg[11][0]_i_1_n_1 ,\weight_reg[11][0]_i_1_n_2 ,\weight_reg[11][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__19_n_88,ARG__19_n_89,ARG__19_n_90,ARG__19_n_91}),
.O({\weight_reg[11][0]_i_1_n_4 ,\weight_reg[11][0]_i_1_n_5 ,\weight_reg[11][0]_i_1_n_6 ,\weight_reg[11][0]_i_1_n_7 }),
.S({\weight[11][0]_i_2_n_0 ,\weight[11][0]_i_3_n_0 ,\weight[11][0]_i_4_n_0 ,\weight[11][0]_i_5_n_0 }));
FDCE \weight_reg[11][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][8]_i_1_n_5 ),
.Q(\weight_reg[11]_10 [10]));
FDCE \weight_reg[11][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][8]_i_1_n_4 ),
.Q(\weight_reg[11]_10 [11]));
FDCE \weight_reg[11][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][12]_i_1_n_7 ),
.Q(\weight_reg[11]_10 [12]));
CARRY4 \weight_reg[11][12]_i_1
(.CI(\weight_reg[11][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED [3],\weight_reg[11][12]_i_1_n_1 ,\weight_reg[11][12]_i_1_n_2 ,\weight_reg[11][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__19_n_77,ARG__19_n_78,ARG__19_n_79}),
.O({\weight_reg[11][12]_i_1_n_4 ,\weight_reg[11][12]_i_1_n_5 ,\weight_reg[11][12]_i_1_n_6 ,\weight_reg[11][12]_i_1_n_7 }),
.S({\weight[11][12]_i_2_n_0 ,\weight[11][12]_i_3_n_0 ,\weight[11][12]_i_4_n_0 ,\weight[11][12]_i_5_n_0 }));
FDCE \weight_reg[11][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][12]_i_1_n_6 ),
.Q(\weight_reg[11]_10 [13]));
FDCE \weight_reg[11][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][12]_i_1_n_5 ),
.Q(\weight_reg[11]_10 [14]));
FDCE \weight_reg[11][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][12]_i_1_n_4 ),
.Q(\weight_reg[11]_10 [15]));
FDCE \weight_reg[11][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][0]_i_1_n_6 ),
.Q(\weight_reg[11]_10 [1]));
FDCE \weight_reg[11][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][0]_i_1_n_5 ),
.Q(\weight_reg[11]_10 [2]));
FDCE \weight_reg[11][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][0]_i_1_n_4 ),
.Q(\weight_reg[11]_10 [3]));
FDCE \weight_reg[11][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][4]_i_1_n_7 ),
.Q(\weight_reg[11]_10 [4]));
CARRY4 \weight_reg[11][4]_i_1
(.CI(\weight_reg[11][0]_i_1_n_0 ),
.CO({\weight_reg[11][4]_i_1_n_0 ,\weight_reg[11][4]_i_1_n_1 ,\weight_reg[11][4]_i_1_n_2 ,\weight_reg[11][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__19_n_84,ARG__19_n_85,ARG__19_n_86,ARG__19_n_87}),
.O({\weight_reg[11][4]_i_1_n_4 ,\weight_reg[11][4]_i_1_n_5 ,\weight_reg[11][4]_i_1_n_6 ,\weight_reg[11][4]_i_1_n_7 }),
.S({\weight[11][4]_i_2_n_0 ,\weight[11][4]_i_3_n_0 ,\weight[11][4]_i_4_n_0 ,\weight[11][4]_i_5_n_0 }));
FDCE \weight_reg[11][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][4]_i_1_n_6 ),
.Q(\weight_reg[11]_10 [5]));
FDCE \weight_reg[11][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][4]_i_1_n_5 ),
.Q(\weight_reg[11]_10 [6]));
FDCE \weight_reg[11][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][4]_i_1_n_4 ),
.Q(\weight_reg[11]_10 [7]));
FDCE \weight_reg[11][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][8]_i_1_n_7 ),
.Q(\weight_reg[11]_10 [8]));
CARRY4 \weight_reg[11][8]_i_1
(.CI(\weight_reg[11][4]_i_1_n_0 ),
.CO({\weight_reg[11][8]_i_1_n_0 ,\weight_reg[11][8]_i_1_n_1 ,\weight_reg[11][8]_i_1_n_2 ,\weight_reg[11][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__19_n_80,ARG__19_n_81,ARG__19_n_82,ARG__19_n_83}),
.O({\weight_reg[11][8]_i_1_n_4 ,\weight_reg[11][8]_i_1_n_5 ,\weight_reg[11][8]_i_1_n_6 ,\weight_reg[11][8]_i_1_n_7 }),
.S({\weight[11][8]_i_2_n_0 ,\weight[11][8]_i_3_n_0 ,\weight[11][8]_i_4_n_0 ,\weight[11][8]_i_5_n_0 }));
FDCE \weight_reg[11][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][8]_i_1_n_6 ),
.Q(\weight_reg[11]_10 [9]));
FDCE \weight_reg[12][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][0]_i_1_n_7 ),
.Q(\weight_reg[12]_11 [0]));
CARRY4 \weight_reg[12][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[12][0]_i_1_n_0 ,\weight_reg[12][0]_i_1_n_1 ,\weight_reg[12][0]_i_1_n_2 ,\weight_reg[12][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__21_n_88,ARG__21_n_89,ARG__21_n_90,ARG__21_n_91}),
.O({\weight_reg[12][0]_i_1_n_4 ,\weight_reg[12][0]_i_1_n_5 ,\weight_reg[12][0]_i_1_n_6 ,\weight_reg[12][0]_i_1_n_7 }),
.S({\weight[12][0]_i_2_n_0 ,\weight[12][0]_i_3_n_0 ,\weight[12][0]_i_4_n_0 ,\weight[12][0]_i_5_n_0 }));
FDCE \weight_reg[12][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][8]_i_1_n_5 ),
.Q(\weight_reg[12]_11 [10]));
FDCE \weight_reg[12][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][8]_i_1_n_4 ),
.Q(\weight_reg[12]_11 [11]));
FDCE \weight_reg[12][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][12]_i_1_n_7 ),
.Q(\weight_reg[12]_11 [12]));
CARRY4 \weight_reg[12][12]_i_1
(.CI(\weight_reg[12][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED [3],\weight_reg[12][12]_i_1_n_1 ,\weight_reg[12][12]_i_1_n_2 ,\weight_reg[12][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__21_n_77,ARG__21_n_78,ARG__21_n_79}),
.O({\weight_reg[12][12]_i_1_n_4 ,\weight_reg[12][12]_i_1_n_5 ,\weight_reg[12][12]_i_1_n_6 ,\weight_reg[12][12]_i_1_n_7 }),
.S({\weight[12][12]_i_2_n_0 ,\weight[12][12]_i_3_n_0 ,\weight[12][12]_i_4_n_0 ,\weight[12][12]_i_5_n_0 }));
FDCE \weight_reg[12][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][12]_i_1_n_6 ),
.Q(\weight_reg[12]_11 [13]));
FDCE \weight_reg[12][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][12]_i_1_n_5 ),
.Q(\weight_reg[12]_11 [14]));
FDCE \weight_reg[12][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][12]_i_1_n_4 ),
.Q(\weight_reg[12]_11 [15]));
FDCE \weight_reg[12][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][0]_i_1_n_6 ),
.Q(\weight_reg[12]_11 [1]));
FDCE \weight_reg[12][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][0]_i_1_n_5 ),
.Q(\weight_reg[12]_11 [2]));
FDCE \weight_reg[12][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][0]_i_1_n_4 ),
.Q(\weight_reg[12]_11 [3]));
FDCE \weight_reg[12][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][4]_i_1_n_7 ),
.Q(\weight_reg[12]_11 [4]));
CARRY4 \weight_reg[12][4]_i_1
(.CI(\weight_reg[12][0]_i_1_n_0 ),
.CO({\weight_reg[12][4]_i_1_n_0 ,\weight_reg[12][4]_i_1_n_1 ,\weight_reg[12][4]_i_1_n_2 ,\weight_reg[12][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__21_n_84,ARG__21_n_85,ARG__21_n_86,ARG__21_n_87}),
.O({\weight_reg[12][4]_i_1_n_4 ,\weight_reg[12][4]_i_1_n_5 ,\weight_reg[12][4]_i_1_n_6 ,\weight_reg[12][4]_i_1_n_7 }),
.S({\weight[12][4]_i_2_n_0 ,\weight[12][4]_i_3_n_0 ,\weight[12][4]_i_4_n_0 ,\weight[12][4]_i_5_n_0 }));
FDCE \weight_reg[12][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][4]_i_1_n_6 ),
.Q(\weight_reg[12]_11 [5]));
FDCE \weight_reg[12][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][4]_i_1_n_5 ),
.Q(\weight_reg[12]_11 [6]));
FDCE \weight_reg[12][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][4]_i_1_n_4 ),
.Q(\weight_reg[12]_11 [7]));
FDCE \weight_reg[12][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][8]_i_1_n_7 ),
.Q(\weight_reg[12]_11 [8]));
CARRY4 \weight_reg[12][8]_i_1
(.CI(\weight_reg[12][4]_i_1_n_0 ),
.CO({\weight_reg[12][8]_i_1_n_0 ,\weight_reg[12][8]_i_1_n_1 ,\weight_reg[12][8]_i_1_n_2 ,\weight_reg[12][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__21_n_80,ARG__21_n_81,ARG__21_n_82,ARG__21_n_83}),
.O({\weight_reg[12][8]_i_1_n_4 ,\weight_reg[12][8]_i_1_n_5 ,\weight_reg[12][8]_i_1_n_6 ,\weight_reg[12][8]_i_1_n_7 }),
.S({\weight[12][8]_i_2_n_0 ,\weight[12][8]_i_3_n_0 ,\weight[12][8]_i_4_n_0 ,\weight[12][8]_i_5_n_0 }));
FDCE \weight_reg[12][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][8]_i_1_n_6 ),
.Q(\weight_reg[12]_11 [9]));
FDCE \weight_reg[13][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][0]_i_1_n_7 ),
.Q(\weight_reg[13]_12 [0]));
CARRY4 \weight_reg[13][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[13][0]_i_1_n_0 ,\weight_reg[13][0]_i_1_n_1 ,\weight_reg[13][0]_i_1_n_2 ,\weight_reg[13][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__23_n_88,ARG__23_n_89,ARG__23_n_90,ARG__23_n_91}),
.O({\weight_reg[13][0]_i_1_n_4 ,\weight_reg[13][0]_i_1_n_5 ,\weight_reg[13][0]_i_1_n_6 ,\weight_reg[13][0]_i_1_n_7 }),
.S({\weight[13][0]_i_2_n_0 ,\weight[13][0]_i_3_n_0 ,\weight[13][0]_i_4_n_0 ,\weight[13][0]_i_5_n_0 }));
FDCE \weight_reg[13][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][8]_i_1_n_5 ),
.Q(\weight_reg[13]_12 [10]));
FDCE \weight_reg[13][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][8]_i_1_n_4 ),
.Q(\weight_reg[13]_12 [11]));
FDCE \weight_reg[13][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][12]_i_1_n_7 ),
.Q(\weight_reg[13]_12 [12]));
CARRY4 \weight_reg[13][12]_i_1
(.CI(\weight_reg[13][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED [3],\weight_reg[13][12]_i_1_n_1 ,\weight_reg[13][12]_i_1_n_2 ,\weight_reg[13][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__23_n_77,ARG__23_n_78,ARG__23_n_79}),
.O({\weight_reg[13][12]_i_1_n_4 ,\weight_reg[13][12]_i_1_n_5 ,\weight_reg[13][12]_i_1_n_6 ,\weight_reg[13][12]_i_1_n_7 }),
.S({\weight[13][12]_i_2_n_0 ,\weight[13][12]_i_3_n_0 ,\weight[13][12]_i_4_n_0 ,\weight[13][12]_i_5_n_0 }));
FDCE \weight_reg[13][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][12]_i_1_n_6 ),
.Q(\weight_reg[13]_12 [13]));
FDCE \weight_reg[13][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][12]_i_1_n_5 ),
.Q(\weight_reg[13]_12 [14]));
FDCE \weight_reg[13][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][12]_i_1_n_4 ),
.Q(\weight_reg[13]_12 [15]));
FDCE \weight_reg[13][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][0]_i_1_n_6 ),
.Q(\weight_reg[13]_12 [1]));
FDCE \weight_reg[13][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][0]_i_1_n_5 ),
.Q(\weight_reg[13]_12 [2]));
FDCE \weight_reg[13][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][0]_i_1_n_4 ),
.Q(\weight_reg[13]_12 [3]));
FDCE \weight_reg[13][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][4]_i_1_n_7 ),
.Q(\weight_reg[13]_12 [4]));
CARRY4 \weight_reg[13][4]_i_1
(.CI(\weight_reg[13][0]_i_1_n_0 ),
.CO({\weight_reg[13][4]_i_1_n_0 ,\weight_reg[13][4]_i_1_n_1 ,\weight_reg[13][4]_i_1_n_2 ,\weight_reg[13][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__23_n_84,ARG__23_n_85,ARG__23_n_86,ARG__23_n_87}),
.O({\weight_reg[13][4]_i_1_n_4 ,\weight_reg[13][4]_i_1_n_5 ,\weight_reg[13][4]_i_1_n_6 ,\weight_reg[13][4]_i_1_n_7 }),
.S({\weight[13][4]_i_2_n_0 ,\weight[13][4]_i_3_n_0 ,\weight[13][4]_i_4_n_0 ,\weight[13][4]_i_5_n_0 }));
FDCE \weight_reg[13][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][4]_i_1_n_6 ),
.Q(\weight_reg[13]_12 [5]));
FDCE \weight_reg[13][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][4]_i_1_n_5 ),
.Q(\weight_reg[13]_12 [6]));
FDCE \weight_reg[13][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][4]_i_1_n_4 ),
.Q(\weight_reg[13]_12 [7]));
FDCE \weight_reg[13][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][8]_i_1_n_7 ),
.Q(\weight_reg[13]_12 [8]));
CARRY4 \weight_reg[13][8]_i_1
(.CI(\weight_reg[13][4]_i_1_n_0 ),
.CO({\weight_reg[13][8]_i_1_n_0 ,\weight_reg[13][8]_i_1_n_1 ,\weight_reg[13][8]_i_1_n_2 ,\weight_reg[13][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__23_n_80,ARG__23_n_81,ARG__23_n_82,ARG__23_n_83}),
.O({\weight_reg[13][8]_i_1_n_4 ,\weight_reg[13][8]_i_1_n_5 ,\weight_reg[13][8]_i_1_n_6 ,\weight_reg[13][8]_i_1_n_7 }),
.S({\weight[13][8]_i_2_n_0 ,\weight[13][8]_i_3_n_0 ,\weight[13][8]_i_4_n_0 ,\weight[13][8]_i_5_n_0 }));
FDCE \weight_reg[13][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][8]_i_1_n_6 ),
.Q(\weight_reg[13]_12 [9]));
FDCE \weight_reg[14][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][0]_i_1_n_7 ),
.Q(\weight_reg[14]_13 [0]));
CARRY4 \weight_reg[14][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[14][0]_i_1_n_0 ,\weight_reg[14][0]_i_1_n_1 ,\weight_reg[14][0]_i_1_n_2 ,\weight_reg[14][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__25_n_88,ARG__25_n_89,ARG__25_n_90,ARG__25_n_91}),
.O({\weight_reg[14][0]_i_1_n_4 ,\weight_reg[14][0]_i_1_n_5 ,\weight_reg[14][0]_i_1_n_6 ,\weight_reg[14][0]_i_1_n_7 }),
.S({\weight[14][0]_i_2_n_0 ,\weight[14][0]_i_3_n_0 ,\weight[14][0]_i_4_n_0 ,\weight[14][0]_i_5_n_0 }));
FDCE \weight_reg[14][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][8]_i_1_n_5 ),
.Q(\weight_reg[14]_13 [10]));
FDCE \weight_reg[14][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][8]_i_1_n_4 ),
.Q(\weight_reg[14]_13 [11]));
FDCE \weight_reg[14][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][12]_i_1_n_7 ),
.Q(\weight_reg[14]_13 [12]));
CARRY4 \weight_reg[14][12]_i_1
(.CI(\weight_reg[14][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED [3],\weight_reg[14][12]_i_1_n_1 ,\weight_reg[14][12]_i_1_n_2 ,\weight_reg[14][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__25_n_77,ARG__25_n_78,ARG__25_n_79}),
.O({\weight_reg[14][12]_i_1_n_4 ,\weight_reg[14][12]_i_1_n_5 ,\weight_reg[14][12]_i_1_n_6 ,\weight_reg[14][12]_i_1_n_7 }),
.S({\weight[14][12]_i_2_n_0 ,\weight[14][12]_i_3_n_0 ,\weight[14][12]_i_4_n_0 ,\weight[14][12]_i_5_n_0 }));
FDCE \weight_reg[14][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][12]_i_1_n_6 ),
.Q(\weight_reg[14]_13 [13]));
FDCE \weight_reg[14][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][12]_i_1_n_5 ),
.Q(\weight_reg[14]_13 [14]));
FDCE \weight_reg[14][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][12]_i_1_n_4 ),
.Q(\weight_reg[14]_13 [15]));
FDCE \weight_reg[14][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][0]_i_1_n_6 ),
.Q(\weight_reg[14]_13 [1]));
FDCE \weight_reg[14][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][0]_i_1_n_5 ),
.Q(\weight_reg[14]_13 [2]));
FDCE \weight_reg[14][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][0]_i_1_n_4 ),
.Q(\weight_reg[14]_13 [3]));
FDCE \weight_reg[14][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][4]_i_1_n_7 ),
.Q(\weight_reg[14]_13 [4]));
CARRY4 \weight_reg[14][4]_i_1
(.CI(\weight_reg[14][0]_i_1_n_0 ),
.CO({\weight_reg[14][4]_i_1_n_0 ,\weight_reg[14][4]_i_1_n_1 ,\weight_reg[14][4]_i_1_n_2 ,\weight_reg[14][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__25_n_84,ARG__25_n_85,ARG__25_n_86,ARG__25_n_87}),
.O({\weight_reg[14][4]_i_1_n_4 ,\weight_reg[14][4]_i_1_n_5 ,\weight_reg[14][4]_i_1_n_6 ,\weight_reg[14][4]_i_1_n_7 }),
.S({\weight[14][4]_i_2_n_0 ,\weight[14][4]_i_3_n_0 ,\weight[14][4]_i_4_n_0 ,\weight[14][4]_i_5_n_0 }));
FDCE \weight_reg[14][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][4]_i_1_n_6 ),
.Q(\weight_reg[14]_13 [5]));
FDCE \weight_reg[14][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][4]_i_1_n_5 ),
.Q(\weight_reg[14]_13 [6]));
FDCE \weight_reg[14][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][4]_i_1_n_4 ),
.Q(\weight_reg[14]_13 [7]));
FDCE \weight_reg[14][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][8]_i_1_n_7 ),
.Q(\weight_reg[14]_13 [8]));
CARRY4 \weight_reg[14][8]_i_1
(.CI(\weight_reg[14][4]_i_1_n_0 ),
.CO({\weight_reg[14][8]_i_1_n_0 ,\weight_reg[14][8]_i_1_n_1 ,\weight_reg[14][8]_i_1_n_2 ,\weight_reg[14][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__25_n_80,ARG__25_n_81,ARG__25_n_82,ARG__25_n_83}),
.O({\weight_reg[14][8]_i_1_n_4 ,\weight_reg[14][8]_i_1_n_5 ,\weight_reg[14][8]_i_1_n_6 ,\weight_reg[14][8]_i_1_n_7 }),
.S({\weight[14][8]_i_2_n_0 ,\weight[14][8]_i_3_n_0 ,\weight[14][8]_i_4_n_0 ,\weight[14][8]_i_5_n_0 }));
FDCE \weight_reg[14][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][8]_i_1_n_6 ),
.Q(\weight_reg[14]_13 [9]));
FDCE \weight_reg[15][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][0]_i_1_n_7 ),
.Q(\weight_reg[15]_14 [0]));
CARRY4 \weight_reg[15][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[15][0]_i_1_n_0 ,\weight_reg[15][0]_i_1_n_1 ,\weight_reg[15][0]_i_1_n_2 ,\weight_reg[15][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__27_n_88,ARG__27_n_89,ARG__27_n_90,ARG__27_n_91}),
.O({\weight_reg[15][0]_i_1_n_4 ,\weight_reg[15][0]_i_1_n_5 ,\weight_reg[15][0]_i_1_n_6 ,\weight_reg[15][0]_i_1_n_7 }),
.S({\weight[15][0]_i_2_n_0 ,\weight[15][0]_i_3_n_0 ,\weight[15][0]_i_4_n_0 ,\weight[15][0]_i_5_n_0 }));
FDCE \weight_reg[15][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][8]_i_1_n_5 ),
.Q(\weight_reg[15]_14 [10]));
FDCE \weight_reg[15][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][8]_i_1_n_4 ),
.Q(\weight_reg[15]_14 [11]));
FDCE \weight_reg[15][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][12]_i_1_n_7 ),
.Q(\weight_reg[15]_14 [12]));
CARRY4 \weight_reg[15][12]_i_1
(.CI(\weight_reg[15][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED [3],\weight_reg[15][12]_i_1_n_1 ,\weight_reg[15][12]_i_1_n_2 ,\weight_reg[15][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__27_n_77,ARG__27_n_78,ARG__27_n_79}),
.O({\weight_reg[15][12]_i_1_n_4 ,\weight_reg[15][12]_i_1_n_5 ,\weight_reg[15][12]_i_1_n_6 ,\weight_reg[15][12]_i_1_n_7 }),
.S({\weight[15][12]_i_2_n_0 ,\weight[15][12]_i_3_n_0 ,\weight[15][12]_i_4_n_0 ,\weight[15][12]_i_5_n_0 }));
FDCE \weight_reg[15][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][12]_i_1_n_6 ),
.Q(\weight_reg[15]_14 [13]));
FDCE \weight_reg[15][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][12]_i_1_n_5 ),
.Q(\weight_reg[15]_14 [14]));
FDCE \weight_reg[15][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][12]_i_1_n_4 ),
.Q(\weight_reg[15]_14 [15]));
FDCE \weight_reg[15][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][0]_i_1_n_6 ),
.Q(\weight_reg[15]_14 [1]));
FDCE \weight_reg[15][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][0]_i_1_n_5 ),
.Q(\weight_reg[15]_14 [2]));
FDCE \weight_reg[15][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][0]_i_1_n_4 ),
.Q(\weight_reg[15]_14 [3]));
FDCE \weight_reg[15][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][4]_i_1_n_7 ),
.Q(\weight_reg[15]_14 [4]));
CARRY4 \weight_reg[15][4]_i_1
(.CI(\weight_reg[15][0]_i_1_n_0 ),
.CO({\weight_reg[15][4]_i_1_n_0 ,\weight_reg[15][4]_i_1_n_1 ,\weight_reg[15][4]_i_1_n_2 ,\weight_reg[15][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__27_n_84,ARG__27_n_85,ARG__27_n_86,ARG__27_n_87}),
.O({\weight_reg[15][4]_i_1_n_4 ,\weight_reg[15][4]_i_1_n_5 ,\weight_reg[15][4]_i_1_n_6 ,\weight_reg[15][4]_i_1_n_7 }),
.S({\weight[15][4]_i_2_n_0 ,\weight[15][4]_i_3_n_0 ,\weight[15][4]_i_4_n_0 ,\weight[15][4]_i_5_n_0 }));
FDCE \weight_reg[15][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][4]_i_1_n_6 ),
.Q(\weight_reg[15]_14 [5]));
FDCE \weight_reg[15][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][4]_i_1_n_5 ),
.Q(\weight_reg[15]_14 [6]));
FDCE \weight_reg[15][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][4]_i_1_n_4 ),
.Q(\weight_reg[15]_14 [7]));
FDCE \weight_reg[15][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][8]_i_1_n_7 ),
.Q(\weight_reg[15]_14 [8]));
CARRY4 \weight_reg[15][8]_i_1
(.CI(\weight_reg[15][4]_i_1_n_0 ),
.CO({\weight_reg[15][8]_i_1_n_0 ,\weight_reg[15][8]_i_1_n_1 ,\weight_reg[15][8]_i_1_n_2 ,\weight_reg[15][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__27_n_80,ARG__27_n_81,ARG__27_n_82,ARG__27_n_83}),
.O({\weight_reg[15][8]_i_1_n_4 ,\weight_reg[15][8]_i_1_n_5 ,\weight_reg[15][8]_i_1_n_6 ,\weight_reg[15][8]_i_1_n_7 }),
.S({\weight[15][8]_i_2_n_0 ,\weight[15][8]_i_3_n_0 ,\weight[15][8]_i_4_n_0 ,\weight[15][8]_i_5_n_0 }));
FDCE \weight_reg[15][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][8]_i_1_n_6 ),
.Q(\weight_reg[15]_14 [9]));
FDCE \weight_reg[1][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][0]_i_1_n_7 ),
.Q(\weight_reg[1]_0 [0]));
CARRY4 \weight_reg[1][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[1][0]_i_1_n_0 ,\weight_reg[1][0]_i_1_n_1 ,\weight_reg[1][0]_i_1_n_2 ,\weight_reg[1][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(in[3:0]),
.O({\weight_reg[1][0]_i_1_n_4 ,\weight_reg[1][0]_i_1_n_5 ,\weight_reg[1][0]_i_1_n_6 ,\weight_reg[1][0]_i_1_n_7 }),
.S({\weight[1][0]_i_2_n_0 ,\weight[1][0]_i_3_n_0 ,\weight[1][0]_i_4_n_0 ,\weight[1][0]_i_5_n_0 }));
FDCE \weight_reg[1][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][8]_i_1_n_5 ),
.Q(\weight_reg[1]_0 [10]));
FDCE \weight_reg[1][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][8]_i_1_n_4 ),
.Q(\weight_reg[1]_0 [11]));
FDCE \weight_reg[1][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][12]_i_1_n_7 ),
.Q(\weight_reg[1]_0 [12]));
CARRY4 \weight_reg[1][12]_i_1
(.CI(\weight_reg[1][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED [3],\weight_reg[1][12]_i_1_n_1 ,\weight_reg[1][12]_i_1_n_2 ,\weight_reg[1][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,in[14:12]}),
.O({\weight_reg[1][12]_i_1_n_4 ,\weight_reg[1][12]_i_1_n_5 ,\weight_reg[1][12]_i_1_n_6 ,\weight_reg[1][12]_i_1_n_7 }),
.S({\weight[1][12]_i_2_n_0 ,\weight[1][12]_i_3_n_0 ,\weight[1][12]_i_4_n_0 ,\weight[1][12]_i_5_n_0 }));
FDCE \weight_reg[1][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][12]_i_1_n_6 ),
.Q(\weight_reg[1]_0 [13]));
FDCE \weight_reg[1][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][12]_i_1_n_5 ),
.Q(\weight_reg[1]_0 [14]));
FDCE \weight_reg[1][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][12]_i_1_n_4 ),
.Q(\weight_reg[1]_0 [15]));
FDCE \weight_reg[1][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][0]_i_1_n_6 ),
.Q(\weight_reg[1]_0 [1]));
FDCE \weight_reg[1][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][0]_i_1_n_5 ),
.Q(\weight_reg[1]_0 [2]));
FDCE \weight_reg[1][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][0]_i_1_n_4 ),
.Q(\weight_reg[1]_0 [3]));
FDCE \weight_reg[1][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][4]_i_1_n_7 ),
.Q(\weight_reg[1]_0 [4]));
CARRY4 \weight_reg[1][4]_i_1
(.CI(\weight_reg[1][0]_i_1_n_0 ),
.CO({\weight_reg[1][4]_i_1_n_0 ,\weight_reg[1][4]_i_1_n_1 ,\weight_reg[1][4]_i_1_n_2 ,\weight_reg[1][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(in[7:4]),
.O({\weight_reg[1][4]_i_1_n_4 ,\weight_reg[1][4]_i_1_n_5 ,\weight_reg[1][4]_i_1_n_6 ,\weight_reg[1][4]_i_1_n_7 }),
.S({\weight[1][4]_i_2_n_0 ,\weight[1][4]_i_3_n_0 ,\weight[1][4]_i_4_n_0 ,\weight[1][4]_i_5_n_0 }));
FDCE \weight_reg[1][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][4]_i_1_n_6 ),
.Q(\weight_reg[1]_0 [5]));
FDCE \weight_reg[1][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][4]_i_1_n_5 ),
.Q(\weight_reg[1]_0 [6]));
FDCE \weight_reg[1][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][4]_i_1_n_4 ),
.Q(\weight_reg[1]_0 [7]));
FDCE \weight_reg[1][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][8]_i_1_n_7 ),
.Q(\weight_reg[1]_0 [8]));
CARRY4 \weight_reg[1][8]_i_1
(.CI(\weight_reg[1][4]_i_1_n_0 ),
.CO({\weight_reg[1][8]_i_1_n_0 ,\weight_reg[1][8]_i_1_n_1 ,\weight_reg[1][8]_i_1_n_2 ,\weight_reg[1][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(in[11:8]),
.O({\weight_reg[1][8]_i_1_n_4 ,\weight_reg[1][8]_i_1_n_5 ,\weight_reg[1][8]_i_1_n_6 ,\weight_reg[1][8]_i_1_n_7 }),
.S({\weight[1][8]_i_2_n_0 ,\weight[1][8]_i_3_n_0 ,\weight[1][8]_i_4_n_0 ,\weight[1][8]_i_5_n_0 }));
FDCE \weight_reg[1][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][8]_i_1_n_6 ),
.Q(\weight_reg[1]_0 [9]));
FDCE \weight_reg[2][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][0]_i_1_n_7 ),
.Q(\weight_reg[2]_1 [0]));
CARRY4 \weight_reg[2][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[2][0]_i_1_n_0 ,\weight_reg[2][0]_i_1_n_1 ,\weight_reg[2][0]_i_1_n_2 ,\weight_reg[2][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__1_n_88,ARG__1_n_89,ARG__1_n_90,ARG__1_n_91}),
.O({\weight_reg[2][0]_i_1_n_4 ,\weight_reg[2][0]_i_1_n_5 ,\weight_reg[2][0]_i_1_n_6 ,\weight_reg[2][0]_i_1_n_7 }),
.S({\weight[2][0]_i_2_n_0 ,\weight[2][0]_i_3_n_0 ,\weight[2][0]_i_4_n_0 ,\weight[2][0]_i_5_n_0 }));
FDCE \weight_reg[2][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][8]_i_1_n_5 ),
.Q(\weight_reg[2]_1 [10]));
FDCE \weight_reg[2][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][8]_i_1_n_4 ),
.Q(\weight_reg[2]_1 [11]));
FDCE \weight_reg[2][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][12]_i_1_n_7 ),
.Q(\weight_reg[2]_1 [12]));
CARRY4 \weight_reg[2][12]_i_1
(.CI(\weight_reg[2][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED [3],\weight_reg[2][12]_i_1_n_1 ,\weight_reg[2][12]_i_1_n_2 ,\weight_reg[2][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__1_n_77,ARG__1_n_78,ARG__1_n_79}),
.O({\weight_reg[2][12]_i_1_n_4 ,\weight_reg[2][12]_i_1_n_5 ,\weight_reg[2][12]_i_1_n_6 ,\weight_reg[2][12]_i_1_n_7 }),
.S({\weight[2][12]_i_2_n_0 ,\weight[2][12]_i_3_n_0 ,\weight[2][12]_i_4_n_0 ,\weight[2][12]_i_5_n_0 }));
FDCE \weight_reg[2][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][12]_i_1_n_6 ),
.Q(\weight_reg[2]_1 [13]));
FDCE \weight_reg[2][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][12]_i_1_n_5 ),
.Q(\weight_reg[2]_1 [14]));
FDCE \weight_reg[2][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][12]_i_1_n_4 ),
.Q(\weight_reg[2]_1 [15]));
FDCE \weight_reg[2][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][0]_i_1_n_6 ),
.Q(\weight_reg[2]_1 [1]));
FDCE \weight_reg[2][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][0]_i_1_n_5 ),
.Q(\weight_reg[2]_1 [2]));
FDCE \weight_reg[2][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][0]_i_1_n_4 ),
.Q(\weight_reg[2]_1 [3]));
FDCE \weight_reg[2][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][4]_i_1_n_7 ),
.Q(\weight_reg[2]_1 [4]));
CARRY4 \weight_reg[2][4]_i_1
(.CI(\weight_reg[2][0]_i_1_n_0 ),
.CO({\weight_reg[2][4]_i_1_n_0 ,\weight_reg[2][4]_i_1_n_1 ,\weight_reg[2][4]_i_1_n_2 ,\weight_reg[2][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__1_n_84,ARG__1_n_85,ARG__1_n_86,ARG__1_n_87}),
.O({\weight_reg[2][4]_i_1_n_4 ,\weight_reg[2][4]_i_1_n_5 ,\weight_reg[2][4]_i_1_n_6 ,\weight_reg[2][4]_i_1_n_7 }),
.S({\weight[2][4]_i_2_n_0 ,\weight[2][4]_i_3_n_0 ,\weight[2][4]_i_4_n_0 ,\weight[2][4]_i_5_n_0 }));
FDCE \weight_reg[2][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][4]_i_1_n_6 ),
.Q(\weight_reg[2]_1 [5]));
FDCE \weight_reg[2][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][4]_i_1_n_5 ),
.Q(\weight_reg[2]_1 [6]));
FDCE \weight_reg[2][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][4]_i_1_n_4 ),
.Q(\weight_reg[2]_1 [7]));
FDCE \weight_reg[2][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][8]_i_1_n_7 ),
.Q(\weight_reg[2]_1 [8]));
CARRY4 \weight_reg[2][8]_i_1
(.CI(\weight_reg[2][4]_i_1_n_0 ),
.CO({\weight_reg[2][8]_i_1_n_0 ,\weight_reg[2][8]_i_1_n_1 ,\weight_reg[2][8]_i_1_n_2 ,\weight_reg[2][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__1_n_80,ARG__1_n_81,ARG__1_n_82,ARG__1_n_83}),
.O({\weight_reg[2][8]_i_1_n_4 ,\weight_reg[2][8]_i_1_n_5 ,\weight_reg[2][8]_i_1_n_6 ,\weight_reg[2][8]_i_1_n_7 }),
.S({\weight[2][8]_i_2_n_0 ,\weight[2][8]_i_3_n_0 ,\weight[2][8]_i_4_n_0 ,\weight[2][8]_i_5_n_0 }));
FDCE \weight_reg[2][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][8]_i_1_n_6 ),
.Q(\weight_reg[2]_1 [9]));
FDCE \weight_reg[3][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][0]_i_1_n_7 ),
.Q(\weight_reg[3]_2 [0]));
CARRY4 \weight_reg[3][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[3][0]_i_1_n_0 ,\weight_reg[3][0]_i_1_n_1 ,\weight_reg[3][0]_i_1_n_2 ,\weight_reg[3][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__3_n_88,ARG__3_n_89,ARG__3_n_90,ARG__3_n_91}),
.O({\weight_reg[3][0]_i_1_n_4 ,\weight_reg[3][0]_i_1_n_5 ,\weight_reg[3][0]_i_1_n_6 ,\weight_reg[3][0]_i_1_n_7 }),
.S({\weight[3][0]_i_2_n_0 ,\weight[3][0]_i_3_n_0 ,\weight[3][0]_i_4_n_0 ,\weight[3][0]_i_5_n_0 }));
FDCE \weight_reg[3][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][8]_i_1_n_5 ),
.Q(\weight_reg[3]_2 [10]));
FDCE \weight_reg[3][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][8]_i_1_n_4 ),
.Q(\weight_reg[3]_2 [11]));
FDCE \weight_reg[3][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][12]_i_1_n_7 ),
.Q(\weight_reg[3]_2 [12]));
CARRY4 \weight_reg[3][12]_i_1
(.CI(\weight_reg[3][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED [3],\weight_reg[3][12]_i_1_n_1 ,\weight_reg[3][12]_i_1_n_2 ,\weight_reg[3][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__3_n_77,ARG__3_n_78,ARG__3_n_79}),
.O({\weight_reg[3][12]_i_1_n_4 ,\weight_reg[3][12]_i_1_n_5 ,\weight_reg[3][12]_i_1_n_6 ,\weight_reg[3][12]_i_1_n_7 }),
.S({\weight[3][12]_i_2_n_0 ,\weight[3][12]_i_3_n_0 ,\weight[3][12]_i_4_n_0 ,\weight[3][12]_i_5_n_0 }));
FDCE \weight_reg[3][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][12]_i_1_n_6 ),
.Q(\weight_reg[3]_2 [13]));
FDCE \weight_reg[3][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][12]_i_1_n_5 ),
.Q(\weight_reg[3]_2 [14]));
FDCE \weight_reg[3][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][12]_i_1_n_4 ),
.Q(\weight_reg[3]_2 [15]));
FDCE \weight_reg[3][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][0]_i_1_n_6 ),
.Q(\weight_reg[3]_2 [1]));
FDCE \weight_reg[3][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][0]_i_1_n_5 ),
.Q(\weight_reg[3]_2 [2]));
FDCE \weight_reg[3][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][0]_i_1_n_4 ),
.Q(\weight_reg[3]_2 [3]));
FDCE \weight_reg[3][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][4]_i_1_n_7 ),
.Q(\weight_reg[3]_2 [4]));
CARRY4 \weight_reg[3][4]_i_1
(.CI(\weight_reg[3][0]_i_1_n_0 ),
.CO({\weight_reg[3][4]_i_1_n_0 ,\weight_reg[3][4]_i_1_n_1 ,\weight_reg[3][4]_i_1_n_2 ,\weight_reg[3][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__3_n_84,ARG__3_n_85,ARG__3_n_86,ARG__3_n_87}),
.O({\weight_reg[3][4]_i_1_n_4 ,\weight_reg[3][4]_i_1_n_5 ,\weight_reg[3][4]_i_1_n_6 ,\weight_reg[3][4]_i_1_n_7 }),
.S({\weight[3][4]_i_2_n_0 ,\weight[3][4]_i_3_n_0 ,\weight[3][4]_i_4_n_0 ,\weight[3][4]_i_5_n_0 }));
FDCE \weight_reg[3][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][4]_i_1_n_6 ),
.Q(\weight_reg[3]_2 [5]));
FDCE \weight_reg[3][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][4]_i_1_n_5 ),
.Q(\weight_reg[3]_2 [6]));
FDCE \weight_reg[3][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][4]_i_1_n_4 ),
.Q(\weight_reg[3]_2 [7]));
FDCE \weight_reg[3][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][8]_i_1_n_7 ),
.Q(\weight_reg[3]_2 [8]));
CARRY4 \weight_reg[3][8]_i_1
(.CI(\weight_reg[3][4]_i_1_n_0 ),
.CO({\weight_reg[3][8]_i_1_n_0 ,\weight_reg[3][8]_i_1_n_1 ,\weight_reg[3][8]_i_1_n_2 ,\weight_reg[3][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__3_n_80,ARG__3_n_81,ARG__3_n_82,ARG__3_n_83}),
.O({\weight_reg[3][8]_i_1_n_4 ,\weight_reg[3][8]_i_1_n_5 ,\weight_reg[3][8]_i_1_n_6 ,\weight_reg[3][8]_i_1_n_7 }),
.S({\weight[3][8]_i_2_n_0 ,\weight[3][8]_i_3_n_0 ,\weight[3][8]_i_4_n_0 ,\weight[3][8]_i_5_n_0 }));
FDCE \weight_reg[3][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][8]_i_1_n_6 ),
.Q(\weight_reg[3]_2 [9]));
FDCE \weight_reg[4][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][0]_i_1_n_7 ),
.Q(\weight_reg[4]_3 [0]));
CARRY4 \weight_reg[4][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[4][0]_i_1_n_0 ,\weight_reg[4][0]_i_1_n_1 ,\weight_reg[4][0]_i_1_n_2 ,\weight_reg[4][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__5_n_88,ARG__5_n_89,ARG__5_n_90,ARG__5_n_91}),
.O({\weight_reg[4][0]_i_1_n_4 ,\weight_reg[4][0]_i_1_n_5 ,\weight_reg[4][0]_i_1_n_6 ,\weight_reg[4][0]_i_1_n_7 }),
.S({\weight[4][0]_i_2_n_0 ,\weight[4][0]_i_3_n_0 ,\weight[4][0]_i_4_n_0 ,\weight[4][0]_i_5_n_0 }));
FDCE \weight_reg[4][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][8]_i_1_n_5 ),
.Q(\weight_reg[4]_3 [10]));
FDCE \weight_reg[4][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][8]_i_1_n_4 ),
.Q(\weight_reg[4]_3 [11]));
FDCE \weight_reg[4][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][12]_i_1_n_7 ),
.Q(\weight_reg[4]_3 [12]));
CARRY4 \weight_reg[4][12]_i_1
(.CI(\weight_reg[4][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED [3],\weight_reg[4][12]_i_1_n_1 ,\weight_reg[4][12]_i_1_n_2 ,\weight_reg[4][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__5_n_77,ARG__5_n_78,ARG__5_n_79}),
.O({\weight_reg[4][12]_i_1_n_4 ,\weight_reg[4][12]_i_1_n_5 ,\weight_reg[4][12]_i_1_n_6 ,\weight_reg[4][12]_i_1_n_7 }),
.S({\weight[4][12]_i_2_n_0 ,\weight[4][12]_i_3_n_0 ,\weight[4][12]_i_4_n_0 ,\weight[4][12]_i_5_n_0 }));
FDCE \weight_reg[4][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][12]_i_1_n_6 ),
.Q(\weight_reg[4]_3 [13]));
FDCE \weight_reg[4][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][12]_i_1_n_5 ),
.Q(\weight_reg[4]_3 [14]));
FDCE \weight_reg[4][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][12]_i_1_n_4 ),
.Q(\weight_reg[4]_3 [15]));
FDCE \weight_reg[4][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][0]_i_1_n_6 ),
.Q(\weight_reg[4]_3 [1]));
FDCE \weight_reg[4][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][0]_i_1_n_5 ),
.Q(\weight_reg[4]_3 [2]));
FDCE \weight_reg[4][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][0]_i_1_n_4 ),
.Q(\weight_reg[4]_3 [3]));
FDCE \weight_reg[4][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][4]_i_1_n_7 ),
.Q(\weight_reg[4]_3 [4]));
CARRY4 \weight_reg[4][4]_i_1
(.CI(\weight_reg[4][0]_i_1_n_0 ),
.CO({\weight_reg[4][4]_i_1_n_0 ,\weight_reg[4][4]_i_1_n_1 ,\weight_reg[4][4]_i_1_n_2 ,\weight_reg[4][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__5_n_84,ARG__5_n_85,ARG__5_n_86,ARG__5_n_87}),
.O({\weight_reg[4][4]_i_1_n_4 ,\weight_reg[4][4]_i_1_n_5 ,\weight_reg[4][4]_i_1_n_6 ,\weight_reg[4][4]_i_1_n_7 }),
.S({\weight[4][4]_i_2_n_0 ,\weight[4][4]_i_3_n_0 ,\weight[4][4]_i_4_n_0 ,\weight[4][4]_i_5_n_0 }));
FDCE \weight_reg[4][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][4]_i_1_n_6 ),
.Q(\weight_reg[4]_3 [5]));
FDCE \weight_reg[4][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][4]_i_1_n_5 ),
.Q(\weight_reg[4]_3 [6]));
FDCE \weight_reg[4][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][4]_i_1_n_4 ),
.Q(\weight_reg[4]_3 [7]));
FDCE \weight_reg[4][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][8]_i_1_n_7 ),
.Q(\weight_reg[4]_3 [8]));
CARRY4 \weight_reg[4][8]_i_1
(.CI(\weight_reg[4][4]_i_1_n_0 ),
.CO({\weight_reg[4][8]_i_1_n_0 ,\weight_reg[4][8]_i_1_n_1 ,\weight_reg[4][8]_i_1_n_2 ,\weight_reg[4][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__5_n_80,ARG__5_n_81,ARG__5_n_82,ARG__5_n_83}),
.O({\weight_reg[4][8]_i_1_n_4 ,\weight_reg[4][8]_i_1_n_5 ,\weight_reg[4][8]_i_1_n_6 ,\weight_reg[4][8]_i_1_n_7 }),
.S({\weight[4][8]_i_2_n_0 ,\weight[4][8]_i_3_n_0 ,\weight[4][8]_i_4_n_0 ,\weight[4][8]_i_5_n_0 }));
FDCE \weight_reg[4][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][8]_i_1_n_6 ),
.Q(\weight_reg[4]_3 [9]));
FDCE \weight_reg[5][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][0]_i_1_n_7 ),
.Q(\weight_reg[5]_4 [0]));
CARRY4 \weight_reg[5][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[5][0]_i_1_n_0 ,\weight_reg[5][0]_i_1_n_1 ,\weight_reg[5][0]_i_1_n_2 ,\weight_reg[5][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__7_n_88,ARG__7_n_89,ARG__7_n_90,ARG__7_n_91}),
.O({\weight_reg[5][0]_i_1_n_4 ,\weight_reg[5][0]_i_1_n_5 ,\weight_reg[5][0]_i_1_n_6 ,\weight_reg[5][0]_i_1_n_7 }),
.S({\weight[5][0]_i_2_n_0 ,\weight[5][0]_i_3_n_0 ,\weight[5][0]_i_4_n_0 ,\weight[5][0]_i_5_n_0 }));
FDCE \weight_reg[5][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][8]_i_1_n_5 ),
.Q(\weight_reg[5]_4 [10]));
FDCE \weight_reg[5][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][8]_i_1_n_4 ),
.Q(\weight_reg[5]_4 [11]));
FDCE \weight_reg[5][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][12]_i_1_n_7 ),
.Q(\weight_reg[5]_4 [12]));
CARRY4 \weight_reg[5][12]_i_1
(.CI(\weight_reg[5][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED [3],\weight_reg[5][12]_i_1_n_1 ,\weight_reg[5][12]_i_1_n_2 ,\weight_reg[5][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__7_n_77,ARG__7_n_78,ARG__7_n_79}),
.O({\weight_reg[5][12]_i_1_n_4 ,\weight_reg[5][12]_i_1_n_5 ,\weight_reg[5][12]_i_1_n_6 ,\weight_reg[5][12]_i_1_n_7 }),
.S({\weight[5][12]_i_2_n_0 ,\weight[5][12]_i_3_n_0 ,\weight[5][12]_i_4_n_0 ,\weight[5][12]_i_5_n_0 }));
FDCE \weight_reg[5][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][12]_i_1_n_6 ),
.Q(\weight_reg[5]_4 [13]));
FDCE \weight_reg[5][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][12]_i_1_n_5 ),
.Q(\weight_reg[5]_4 [14]));
FDCE \weight_reg[5][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][12]_i_1_n_4 ),
.Q(\weight_reg[5]_4 [15]));
FDCE \weight_reg[5][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][0]_i_1_n_6 ),
.Q(\weight_reg[5]_4 [1]));
FDCE \weight_reg[5][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][0]_i_1_n_5 ),
.Q(\weight_reg[5]_4 [2]));
FDCE \weight_reg[5][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][0]_i_1_n_4 ),
.Q(\weight_reg[5]_4 [3]));
FDCE \weight_reg[5][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][4]_i_1_n_7 ),
.Q(\weight_reg[5]_4 [4]));
CARRY4 \weight_reg[5][4]_i_1
(.CI(\weight_reg[5][0]_i_1_n_0 ),
.CO({\weight_reg[5][4]_i_1_n_0 ,\weight_reg[5][4]_i_1_n_1 ,\weight_reg[5][4]_i_1_n_2 ,\weight_reg[5][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__7_n_84,ARG__7_n_85,ARG__7_n_86,ARG__7_n_87}),
.O({\weight_reg[5][4]_i_1_n_4 ,\weight_reg[5][4]_i_1_n_5 ,\weight_reg[5][4]_i_1_n_6 ,\weight_reg[5][4]_i_1_n_7 }),
.S({\weight[5][4]_i_2_n_0 ,\weight[5][4]_i_3_n_0 ,\weight[5][4]_i_4_n_0 ,\weight[5][4]_i_5_n_0 }));
FDCE \weight_reg[5][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][4]_i_1_n_6 ),
.Q(\weight_reg[5]_4 [5]));
FDCE \weight_reg[5][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][4]_i_1_n_5 ),
.Q(\weight_reg[5]_4 [6]));
FDCE \weight_reg[5][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][4]_i_1_n_4 ),
.Q(\weight_reg[5]_4 [7]));
FDCE \weight_reg[5][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][8]_i_1_n_7 ),
.Q(\weight_reg[5]_4 [8]));
CARRY4 \weight_reg[5][8]_i_1
(.CI(\weight_reg[5][4]_i_1_n_0 ),
.CO({\weight_reg[5][8]_i_1_n_0 ,\weight_reg[5][8]_i_1_n_1 ,\weight_reg[5][8]_i_1_n_2 ,\weight_reg[5][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__7_n_80,ARG__7_n_81,ARG__7_n_82,ARG__7_n_83}),
.O({\weight_reg[5][8]_i_1_n_4 ,\weight_reg[5][8]_i_1_n_5 ,\weight_reg[5][8]_i_1_n_6 ,\weight_reg[5][8]_i_1_n_7 }),
.S({\weight[5][8]_i_2_n_0 ,\weight[5][8]_i_3_n_0 ,\weight[5][8]_i_4_n_0 ,\weight[5][8]_i_5_n_0 }));
FDCE \weight_reg[5][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][8]_i_1_n_6 ),
.Q(\weight_reg[5]_4 [9]));
FDCE \weight_reg[6][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][0]_i_1_n_7 ),
.Q(\weight_reg[6]_5 [0]));
CARRY4 \weight_reg[6][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[6][0]_i_1_n_0 ,\weight_reg[6][0]_i_1_n_1 ,\weight_reg[6][0]_i_1_n_2 ,\weight_reg[6][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__9_n_88,ARG__9_n_89,ARG__9_n_90,ARG__9_n_91}),
.O({\weight_reg[6][0]_i_1_n_4 ,\weight_reg[6][0]_i_1_n_5 ,\weight_reg[6][0]_i_1_n_6 ,\weight_reg[6][0]_i_1_n_7 }),
.S({\weight[6][0]_i_2_n_0 ,\weight[6][0]_i_3_n_0 ,\weight[6][0]_i_4_n_0 ,\weight[6][0]_i_5_n_0 }));
FDCE \weight_reg[6][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][8]_i_1_n_5 ),
.Q(\weight_reg[6]_5 [10]));
FDCE \weight_reg[6][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][8]_i_1_n_4 ),
.Q(\weight_reg[6]_5 [11]));
FDCE \weight_reg[6][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][12]_i_1_n_7 ),
.Q(\weight_reg[6]_5 [12]));
CARRY4 \weight_reg[6][12]_i_1
(.CI(\weight_reg[6][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED [3],\weight_reg[6][12]_i_1_n_1 ,\weight_reg[6][12]_i_1_n_2 ,\weight_reg[6][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__9_n_77,ARG__9_n_78,ARG__9_n_79}),
.O({\weight_reg[6][12]_i_1_n_4 ,\weight_reg[6][12]_i_1_n_5 ,\weight_reg[6][12]_i_1_n_6 ,\weight_reg[6][12]_i_1_n_7 }),
.S({\weight[6][12]_i_2_n_0 ,\weight[6][12]_i_3_n_0 ,\weight[6][12]_i_4_n_0 ,\weight[6][12]_i_5_n_0 }));
FDCE \weight_reg[6][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][12]_i_1_n_6 ),
.Q(\weight_reg[6]_5 [13]));
FDCE \weight_reg[6][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][12]_i_1_n_5 ),
.Q(\weight_reg[6]_5 [14]));
FDCE \weight_reg[6][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][12]_i_1_n_4 ),
.Q(\weight_reg[6]_5 [15]));
FDCE \weight_reg[6][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][0]_i_1_n_6 ),
.Q(\weight_reg[6]_5 [1]));
FDCE \weight_reg[6][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][0]_i_1_n_5 ),
.Q(\weight_reg[6]_5 [2]));
FDCE \weight_reg[6][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][0]_i_1_n_4 ),
.Q(\weight_reg[6]_5 [3]));
FDCE \weight_reg[6][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][4]_i_1_n_7 ),
.Q(\weight_reg[6]_5 [4]));
CARRY4 \weight_reg[6][4]_i_1
(.CI(\weight_reg[6][0]_i_1_n_0 ),
.CO({\weight_reg[6][4]_i_1_n_0 ,\weight_reg[6][4]_i_1_n_1 ,\weight_reg[6][4]_i_1_n_2 ,\weight_reg[6][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__9_n_84,ARG__9_n_85,ARG__9_n_86,ARG__9_n_87}),
.O({\weight_reg[6][4]_i_1_n_4 ,\weight_reg[6][4]_i_1_n_5 ,\weight_reg[6][4]_i_1_n_6 ,\weight_reg[6][4]_i_1_n_7 }),
.S({\weight[6][4]_i_2_n_0 ,\weight[6][4]_i_3_n_0 ,\weight[6][4]_i_4_n_0 ,\weight[6][4]_i_5_n_0 }));
FDCE \weight_reg[6][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][4]_i_1_n_6 ),
.Q(\weight_reg[6]_5 [5]));
FDCE \weight_reg[6][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][4]_i_1_n_5 ),
.Q(\weight_reg[6]_5 [6]));
FDCE \weight_reg[6][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][4]_i_1_n_4 ),
.Q(\weight_reg[6]_5 [7]));
FDCE \weight_reg[6][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][8]_i_1_n_7 ),
.Q(\weight_reg[6]_5 [8]));
CARRY4 \weight_reg[6][8]_i_1
(.CI(\weight_reg[6][4]_i_1_n_0 ),
.CO({\weight_reg[6][8]_i_1_n_0 ,\weight_reg[6][8]_i_1_n_1 ,\weight_reg[6][8]_i_1_n_2 ,\weight_reg[6][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__9_n_80,ARG__9_n_81,ARG__9_n_82,ARG__9_n_83}),
.O({\weight_reg[6][8]_i_1_n_4 ,\weight_reg[6][8]_i_1_n_5 ,\weight_reg[6][8]_i_1_n_6 ,\weight_reg[6][8]_i_1_n_7 }),
.S({\weight[6][8]_i_2_n_0 ,\weight[6][8]_i_3_n_0 ,\weight[6][8]_i_4_n_0 ,\weight[6][8]_i_5_n_0 }));
FDCE \weight_reg[6][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][8]_i_1_n_6 ),
.Q(\weight_reg[6]_5 [9]));
FDCE \weight_reg[7][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][0]_i_1_n_7 ),
.Q(\weight_reg[7]_6 [0]));
CARRY4 \weight_reg[7][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[7][0]_i_1_n_0 ,\weight_reg[7][0]_i_1_n_1 ,\weight_reg[7][0]_i_1_n_2 ,\weight_reg[7][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__11_n_88,ARG__11_n_89,ARG__11_n_90,ARG__11_n_91}),
.O({\weight_reg[7][0]_i_1_n_4 ,\weight_reg[7][0]_i_1_n_5 ,\weight_reg[7][0]_i_1_n_6 ,\weight_reg[7][0]_i_1_n_7 }),
.S({\weight[7][0]_i_2_n_0 ,\weight[7][0]_i_3_n_0 ,\weight[7][0]_i_4_n_0 ,\weight[7][0]_i_5_n_0 }));
FDCE \weight_reg[7][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][8]_i_1_n_5 ),
.Q(\weight_reg[7]_6 [10]));
FDCE \weight_reg[7][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][8]_i_1_n_4 ),
.Q(\weight_reg[7]_6 [11]));
FDCE \weight_reg[7][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][12]_i_1_n_7 ),
.Q(\weight_reg[7]_6 [12]));
CARRY4 \weight_reg[7][12]_i_1
(.CI(\weight_reg[7][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED [3],\weight_reg[7][12]_i_1_n_1 ,\weight_reg[7][12]_i_1_n_2 ,\weight_reg[7][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__11_n_77,ARG__11_n_78,ARG__11_n_79}),
.O({\weight_reg[7][12]_i_1_n_4 ,\weight_reg[7][12]_i_1_n_5 ,\weight_reg[7][12]_i_1_n_6 ,\weight_reg[7][12]_i_1_n_7 }),
.S({\weight[7][12]_i_2_n_0 ,\weight[7][12]_i_3_n_0 ,\weight[7][12]_i_4_n_0 ,\weight[7][12]_i_5_n_0 }));
FDCE \weight_reg[7][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][12]_i_1_n_6 ),
.Q(\weight_reg[7]_6 [13]));
FDCE \weight_reg[7][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][12]_i_1_n_5 ),
.Q(\weight_reg[7]_6 [14]));
FDCE \weight_reg[7][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][12]_i_1_n_4 ),
.Q(\weight_reg[7]_6 [15]));
FDCE \weight_reg[7][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][0]_i_1_n_6 ),
.Q(\weight_reg[7]_6 [1]));
FDCE \weight_reg[7][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][0]_i_1_n_5 ),
.Q(\weight_reg[7]_6 [2]));
FDCE \weight_reg[7][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][0]_i_1_n_4 ),
.Q(\weight_reg[7]_6 [3]));
FDCE \weight_reg[7][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][4]_i_1_n_7 ),
.Q(\weight_reg[7]_6 [4]));
CARRY4 \weight_reg[7][4]_i_1
(.CI(\weight_reg[7][0]_i_1_n_0 ),
.CO({\weight_reg[7][4]_i_1_n_0 ,\weight_reg[7][4]_i_1_n_1 ,\weight_reg[7][4]_i_1_n_2 ,\weight_reg[7][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__11_n_84,ARG__11_n_85,ARG__11_n_86,ARG__11_n_87}),
.O({\weight_reg[7][4]_i_1_n_4 ,\weight_reg[7][4]_i_1_n_5 ,\weight_reg[7][4]_i_1_n_6 ,\weight_reg[7][4]_i_1_n_7 }),
.S({\weight[7][4]_i_2_n_0 ,\weight[7][4]_i_3_n_0 ,\weight[7][4]_i_4_n_0 ,\weight[7][4]_i_5_n_0 }));
FDCE \weight_reg[7][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][4]_i_1_n_6 ),
.Q(\weight_reg[7]_6 [5]));
FDCE \weight_reg[7][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][4]_i_1_n_5 ),
.Q(\weight_reg[7]_6 [6]));
FDCE \weight_reg[7][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][4]_i_1_n_4 ),
.Q(\weight_reg[7]_6 [7]));
FDCE \weight_reg[7][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][8]_i_1_n_7 ),
.Q(\weight_reg[7]_6 [8]));
CARRY4 \weight_reg[7][8]_i_1
(.CI(\weight_reg[7][4]_i_1_n_0 ),
.CO({\weight_reg[7][8]_i_1_n_0 ,\weight_reg[7][8]_i_1_n_1 ,\weight_reg[7][8]_i_1_n_2 ,\weight_reg[7][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__11_n_80,ARG__11_n_81,ARG__11_n_82,ARG__11_n_83}),
.O({\weight_reg[7][8]_i_1_n_4 ,\weight_reg[7][8]_i_1_n_5 ,\weight_reg[7][8]_i_1_n_6 ,\weight_reg[7][8]_i_1_n_7 }),
.S({\weight[7][8]_i_2_n_0 ,\weight[7][8]_i_3_n_0 ,\weight[7][8]_i_4_n_0 ,\weight[7][8]_i_5_n_0 }));
FDCE \weight_reg[7][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][8]_i_1_n_6 ),
.Q(\weight_reg[7]_6 [9]));
FDCE \weight_reg[8][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][0]_i_1_n_7 ),
.Q(\weight_reg[8]_7 [0]));
CARRY4 \weight_reg[8][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[8][0]_i_1_n_0 ,\weight_reg[8][0]_i_1_n_1 ,\weight_reg[8][0]_i_1_n_2 ,\weight_reg[8][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__13_n_88,ARG__13_n_89,ARG__13_n_90,ARG__13_n_91}),
.O({\weight_reg[8][0]_i_1_n_4 ,\weight_reg[8][0]_i_1_n_5 ,\weight_reg[8][0]_i_1_n_6 ,\weight_reg[8][0]_i_1_n_7 }),
.S({\weight[8][0]_i_2_n_0 ,\weight[8][0]_i_3_n_0 ,\weight[8][0]_i_4_n_0 ,\weight[8][0]_i_5_n_0 }));
FDCE \weight_reg[8][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][8]_i_1_n_5 ),
.Q(\weight_reg[8]_7 [10]));
FDCE \weight_reg[8][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][8]_i_1_n_4 ),
.Q(\weight_reg[8]_7 [11]));
FDCE \weight_reg[8][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][12]_i_1_n_7 ),
.Q(\weight_reg[8]_7 [12]));
CARRY4 \weight_reg[8][12]_i_1
(.CI(\weight_reg[8][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED [3],\weight_reg[8][12]_i_1_n_1 ,\weight_reg[8][12]_i_1_n_2 ,\weight_reg[8][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__13_n_77,ARG__13_n_78,ARG__13_n_79}),
.O({\weight_reg[8][12]_i_1_n_4 ,\weight_reg[8][12]_i_1_n_5 ,\weight_reg[8][12]_i_1_n_6 ,\weight_reg[8][12]_i_1_n_7 }),
.S({\weight[8][12]_i_2_n_0 ,\weight[8][12]_i_3_n_0 ,\weight[8][12]_i_4_n_0 ,\weight[8][12]_i_5_n_0 }));
FDCE \weight_reg[8][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][12]_i_1_n_6 ),
.Q(\weight_reg[8]_7 [13]));
FDCE \weight_reg[8][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][12]_i_1_n_5 ),
.Q(\weight_reg[8]_7 [14]));
FDCE \weight_reg[8][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][12]_i_1_n_4 ),
.Q(\weight_reg[8]_7 [15]));
FDCE \weight_reg[8][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][0]_i_1_n_6 ),
.Q(\weight_reg[8]_7 [1]));
FDCE \weight_reg[8][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][0]_i_1_n_5 ),
.Q(\weight_reg[8]_7 [2]));
FDCE \weight_reg[8][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][0]_i_1_n_4 ),
.Q(\weight_reg[8]_7 [3]));
FDCE \weight_reg[8][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][4]_i_1_n_7 ),
.Q(\weight_reg[8]_7 [4]));
CARRY4 \weight_reg[8][4]_i_1
(.CI(\weight_reg[8][0]_i_1_n_0 ),
.CO({\weight_reg[8][4]_i_1_n_0 ,\weight_reg[8][4]_i_1_n_1 ,\weight_reg[8][4]_i_1_n_2 ,\weight_reg[8][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__13_n_84,ARG__13_n_85,ARG__13_n_86,ARG__13_n_87}),
.O({\weight_reg[8][4]_i_1_n_4 ,\weight_reg[8][4]_i_1_n_5 ,\weight_reg[8][4]_i_1_n_6 ,\weight_reg[8][4]_i_1_n_7 }),
.S({\weight[8][4]_i_2_n_0 ,\weight[8][4]_i_3_n_0 ,\weight[8][4]_i_4_n_0 ,\weight[8][4]_i_5_n_0 }));
FDCE \weight_reg[8][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][4]_i_1_n_6 ),
.Q(\weight_reg[8]_7 [5]));
FDCE \weight_reg[8][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][4]_i_1_n_5 ),
.Q(\weight_reg[8]_7 [6]));
FDCE \weight_reg[8][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][4]_i_1_n_4 ),
.Q(\weight_reg[8]_7 [7]));
FDCE \weight_reg[8][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][8]_i_1_n_7 ),
.Q(\weight_reg[8]_7 [8]));
CARRY4 \weight_reg[8][8]_i_1
(.CI(\weight_reg[8][4]_i_1_n_0 ),
.CO({\weight_reg[8][8]_i_1_n_0 ,\weight_reg[8][8]_i_1_n_1 ,\weight_reg[8][8]_i_1_n_2 ,\weight_reg[8][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__13_n_80,ARG__13_n_81,ARG__13_n_82,ARG__13_n_83}),
.O({\weight_reg[8][8]_i_1_n_4 ,\weight_reg[8][8]_i_1_n_5 ,\weight_reg[8][8]_i_1_n_6 ,\weight_reg[8][8]_i_1_n_7 }),
.S({\weight[8][8]_i_2_n_0 ,\weight[8][8]_i_3_n_0 ,\weight[8][8]_i_4_n_0 ,\weight[8][8]_i_5_n_0 }));
FDCE \weight_reg[8][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][8]_i_1_n_6 ),
.Q(\weight_reg[8]_7 [9]));
FDCE \weight_reg[9][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][0]_i_1_n_7 ),
.Q(\weight_reg[9]_8 [0]));
CARRY4 \weight_reg[9][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[9][0]_i_1_n_0 ,\weight_reg[9][0]_i_1_n_1 ,\weight_reg[9][0]_i_1_n_2 ,\weight_reg[9][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__15_n_88,ARG__15_n_89,ARG__15_n_90,ARG__15_n_91}),
.O({\weight_reg[9][0]_i_1_n_4 ,\weight_reg[9][0]_i_1_n_5 ,\weight_reg[9][0]_i_1_n_6 ,\weight_reg[9][0]_i_1_n_7 }),
.S({\weight[9][0]_i_2_n_0 ,\weight[9][0]_i_3_n_0 ,\weight[9][0]_i_4_n_0 ,\weight[9][0]_i_5_n_0 }));
FDCE \weight_reg[9][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][8]_i_1_n_5 ),
.Q(\weight_reg[9]_8 [10]));
FDCE \weight_reg[9][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][8]_i_1_n_4 ),
.Q(\weight_reg[9]_8 [11]));
FDCE \weight_reg[9][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][12]_i_1_n_7 ),
.Q(\weight_reg[9]_8 [12]));
CARRY4 \weight_reg[9][12]_i_1
(.CI(\weight_reg[9][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED [3],\weight_reg[9][12]_i_1_n_1 ,\weight_reg[9][12]_i_1_n_2 ,\weight_reg[9][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__15_n_77,ARG__15_n_78,ARG__15_n_79}),
.O({\weight_reg[9][12]_i_1_n_4 ,\weight_reg[9][12]_i_1_n_5 ,\weight_reg[9][12]_i_1_n_6 ,\weight_reg[9][12]_i_1_n_7 }),
.S({\weight[9][12]_i_2_n_0 ,\weight[9][12]_i_3_n_0 ,\weight[9][12]_i_4_n_0 ,\weight[9][12]_i_5_n_0 }));
FDCE \weight_reg[9][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][12]_i_1_n_6 ),
.Q(\weight_reg[9]_8 [13]));
FDCE \weight_reg[9][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][12]_i_1_n_5 ),
.Q(\weight_reg[9]_8 [14]));
FDCE \weight_reg[9][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][12]_i_1_n_4 ),
.Q(\weight_reg[9]_8 [15]));
FDCE \weight_reg[9][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][0]_i_1_n_6 ),
.Q(\weight_reg[9]_8 [1]));
FDCE \weight_reg[9][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][0]_i_1_n_5 ),
.Q(\weight_reg[9]_8 [2]));
FDCE \weight_reg[9][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][0]_i_1_n_4 ),
.Q(\weight_reg[9]_8 [3]));
FDCE \weight_reg[9][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][4]_i_1_n_7 ),
.Q(\weight_reg[9]_8 [4]));
CARRY4 \weight_reg[9][4]_i_1
(.CI(\weight_reg[9][0]_i_1_n_0 ),
.CO({\weight_reg[9][4]_i_1_n_0 ,\weight_reg[9][4]_i_1_n_1 ,\weight_reg[9][4]_i_1_n_2 ,\weight_reg[9][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__15_n_84,ARG__15_n_85,ARG__15_n_86,ARG__15_n_87}),
.O({\weight_reg[9][4]_i_1_n_4 ,\weight_reg[9][4]_i_1_n_5 ,\weight_reg[9][4]_i_1_n_6 ,\weight_reg[9][4]_i_1_n_7 }),
.S({\weight[9][4]_i_2_n_0 ,\weight[9][4]_i_3_n_0 ,\weight[9][4]_i_4_n_0 ,\weight[9][4]_i_5_n_0 }));
FDCE \weight_reg[9][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][4]_i_1_n_6 ),
.Q(\weight_reg[9]_8 [5]));
FDCE \weight_reg[9][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][4]_i_1_n_5 ),
.Q(\weight_reg[9]_8 [6]));
FDCE \weight_reg[9][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][4]_i_1_n_4 ),
.Q(\weight_reg[9]_8 [7]));
FDCE \weight_reg[9][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][8]_i_1_n_7 ),
.Q(\weight_reg[9]_8 [8]));
CARRY4 \weight_reg[9][8]_i_1
(.CI(\weight_reg[9][4]_i_1_n_0 ),
.CO({\weight_reg[9][8]_i_1_n_0 ,\weight_reg[9][8]_i_1_n_1 ,\weight_reg[9][8]_i_1_n_2 ,\weight_reg[9][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__15_n_80,ARG__15_n_81,ARG__15_n_82,ARG__15_n_83}),
.O({\weight_reg[9][8]_i_1_n_4 ,\weight_reg[9][8]_i_1_n_5 ,\weight_reg[9][8]_i_1_n_6 ,\weight_reg[9][8]_i_1_n_7 }),
.S({\weight[9][8]_i_2_n_0 ,\weight[9][8]_i_3_n_0 ,\weight[9][8]_i_4_n_0 ,\weight[9][8]_i_5_n_0 }));
FDCE \weight_reg[9][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][8]_i_1_n_6 ),
.Q(\weight_reg[9]_8 [9]));
endmodule |
module ip_design_lms_pcore_0_0_lms_pcore
(AXI4_Lite_WREADY,
AXI4_Lite_BVALID,
AXI4_Lite_RVALID,
AXI4_Lite_RDATA,
AXI4_Lite_ARREADY,
AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID,
AXI4_Lite_WVALID,
AXI4_Lite_ARESETN,
IPCORE_RESETN,
AXI4_Lite_WDATA,
AXI4_Lite_ACLK,
AXI4_Lite_AWADDR,
IPCORE_CLK,
AXI4_Lite_ARVALID,
AXI4_Lite_ARADDR,
AXI4_Lite_RREADY,
AXI4_Lite_BREADY);
output AXI4_Lite_WREADY;
output AXI4_Lite_BVALID;
output AXI4_Lite_RVALID;
output [15:0]AXI4_Lite_RDATA;
output AXI4_Lite_ARREADY;
output AXI4_Lite_AWREADY;
input AXI4_Lite_AWVALID;
input AXI4_Lite_WVALID;
input AXI4_Lite_ARESETN;
input IPCORE_RESETN;
input [15:0]AXI4_Lite_WDATA;
input AXI4_Lite_ACLK;
input [13:0]AXI4_Lite_AWADDR;
input IPCORE_CLK;
input AXI4_Lite_ARVALID;
input [13:0]AXI4_Lite_ARADDR;
input AXI4_Lite_RREADY;
input AXI4_Lite_BREADY;
wire AXI4_Lite_ACLK;
wire [13:0]AXI4_Lite_ARADDR;
wire AXI4_Lite_ARESETN;
wire AXI4_Lite_ARREADY;
wire AXI4_Lite_ARVALID;
wire [13:0]AXI4_Lite_AWADDR;
wire AXI4_Lite_AWREADY;
wire AXI4_Lite_AWVALID;
wire AXI4_Lite_BREADY;
wire AXI4_Lite_BVALID;
wire [15:0]AXI4_Lite_RDATA;
wire AXI4_Lite_RREADY;
wire AXI4_Lite_RVALID;
wire [15:0]AXI4_Lite_WDATA;
wire AXI4_Lite_WREADY;
wire AXI4_Lite_WVALID;
wire IPCORE_CLK;
wire IPCORE_RESETN;
wire cop_dut_enable;
wire cop_out_ready;
wire [1:0]cp_controller_cpstate;
wire [15:0]filter_sum;
wire [15:0]\u_LMS/mul_temp_16 ;
wire u_lms_pcore_axi_lite_inst_n_0;
wire u_lms_pcore_axi_lite_inst_n_24;
wire u_lms_pcore_axi_lite_inst_n_25;
wire u_lms_pcore_axi_lite_inst_n_26;
wire u_lms_pcore_axi_lite_inst_n_27;
wire u_lms_pcore_axi_lite_inst_n_28;
wire u_lms_pcore_axi_lite_inst_n_29;
wire u_lms_pcore_axi_lite_inst_n_30;
wire u_lms_pcore_axi_lite_inst_n_31;
wire u_lms_pcore_axi_lite_inst_n_32;
wire u_lms_pcore_axi_lite_inst_n_33;
wire u_lms_pcore_axi_lite_inst_n_34;
wire u_lms_pcore_axi_lite_inst_n_35;
wire u_lms_pcore_axi_lite_inst_n_36;
wire u_lms_pcore_axi_lite_inst_n_37;
wire u_lms_pcore_axi_lite_inst_n_38;
wire u_lms_pcore_axi_lite_inst_n_39;
wire u_lms_pcore_axi_lite_inst_n_40;
wire u_lms_pcore_axi_lite_inst_n_5;
wire u_lms_pcore_axi_lite_inst_n_6;
wire u_lms_pcore_axi_lite_inst_n_7;
wire u_lms_pcore_axi_lite_inst_n_8;
wire write_reg_axi_enable;
wire [14:0]write_reg_d_k;
wire [15:0]write_reg_x_k;
ip_design_lms_pcore_0_0_lms_pcore_axi_lite u_lms_pcore_axi_lite_inst
(.ARG__28(write_reg_x_k),
.ARG__29({u_lms_pcore_axi_lite_inst_n_37,u_lms_pcore_axi_lite_inst_n_38,u_lms_pcore_axi_lite_inst_n_39}),
.AXI4_Lite_ACLK(AXI4_Lite_ACLK),
.AXI4_Lite_ARADDR(AXI4_Lite_ARADDR),
.AXI4_Lite_ARESETN(AXI4_Lite_ARESETN),
.AXI4_Lite_ARREADY(AXI4_Lite_ARREADY),
.AXI4_Lite_ARVALID(AXI4_Lite_ARVALID),
.AXI4_Lite_AWADDR(AXI4_Lite_AWADDR),
.AXI4_Lite_AWREADY(AXI4_Lite_AWREADY),
.AXI4_Lite_AWVALID(AXI4_Lite_AWVALID),
.AXI4_Lite_BREADY(AXI4_Lite_BREADY),
.AXI4_Lite_BVALID(AXI4_Lite_BVALID),
.AXI4_Lite_RDATA(AXI4_Lite_RDATA),
.AXI4_Lite_RREADY(AXI4_Lite_RREADY),
.AXI4_Lite_RVALID(AXI4_Lite_RVALID),
.AXI4_Lite_WDATA(AXI4_Lite_WDATA),
.AXI4_Lite_WREADY(AXI4_Lite_WREADY),
.AXI4_Lite_WVALID(AXI4_Lite_WVALID),
.DI(u_lms_pcore_axi_lite_inst_n_36),
.IPCORE_RESETN(IPCORE_RESETN),
.Q(write_reg_d_k),
.S({u_lms_pcore_axi_lite_inst_n_5,u_lms_pcore_axi_lite_inst_n_6,u_lms_pcore_axi_lite_inst_n_7,u_lms_pcore_axi_lite_inst_n_8}),
.cop_out_ready(cop_out_ready),
.cp_controller_cpstate(cp_controller_cpstate),
.\cp_controller_cpstate_reg[0] (u_lms_pcore_axi_lite_inst_n_40),
.filter_sum(filter_sum),
.mul_temp_16(\u_LMS/mul_temp_16 ),
.\sync_reg_e_k_reg[11] ({u_lms_pcore_axi_lite_inst_n_24,u_lms_pcore_axi_lite_inst_n_25,u_lms_pcore_axi_lite_inst_n_26,u_lms_pcore_axi_lite_inst_n_27}),
.\sync_reg_e_k_reg[3] ({u_lms_pcore_axi_lite_inst_n_32,u_lms_pcore_axi_lite_inst_n_33,u_lms_pcore_axi_lite_inst_n_34,u_lms_pcore_axi_lite_inst_n_35}),
.\sync_reg_e_k_reg[7] ({u_lms_pcore_axi_lite_inst_n_28,u_lms_pcore_axi_lite_inst_n_29,u_lms_pcore_axi_lite_inst_n_30,u_lms_pcore_axi_lite_inst_n_31}),
.write_reg_axi_enable(write_reg_axi_enable),
.write_reg_axi_enable_reg(u_lms_pcore_axi_lite_inst_n_0));
ip_design_lms_pcore_0_0_lms_pcore_cop u_lms_pcore_cop_inst
(.AR(u_lms_pcore_axi_lite_inst_n_0),
.IPCORE_CLK(IPCORE_CLK),
.cop_dut_enable(cop_dut_enable),
.cop_out_ready(cop_out_ready),
.cp_controller_cpstate(cp_controller_cpstate),
.strobe_reg_cop_in_strobe_reg(u_lms_pcore_axi_lite_inst_n_40),
.write_reg_axi_enable(write_reg_axi_enable));
ip_design_lms_pcore_0_0_lms_pcore_dut u_lms_pcore_dut_inst
(.AR(u_lms_pcore_axi_lite_inst_n_0),
.DI(u_lms_pcore_axi_lite_inst_n_36),
.IPCORE_CLK(IPCORE_CLK),
.Q(write_reg_d_k),
.S({u_lms_pcore_axi_lite_inst_n_5,u_lms_pcore_axi_lite_inst_n_6,u_lms_pcore_axi_lite_inst_n_7,u_lms_pcore_axi_lite_inst_n_8}),
.cop_dut_enable(cop_dut_enable),
.filter_sum(filter_sum),
.mul_temp_16(\u_LMS/mul_temp_16 ),
.\write_reg_d_k_reg[11] ({u_lms_pcore_axi_lite_inst_n_24,u_lms_pcore_axi_lite_inst_n_25,u_lms_pcore_axi_lite_inst_n_26,u_lms_pcore_axi_lite_inst_n_27}),
.\write_reg_d_k_reg[3] ({u_lms_pcore_axi_lite_inst_n_37,u_lms_pcore_axi_lite_inst_n_38,u_lms_pcore_axi_lite_inst_n_39}),
.\write_reg_d_k_reg[3]_0 ({u_lms_pcore_axi_lite_inst_n_32,u_lms_pcore_axi_lite_inst_n_33,u_lms_pcore_axi_lite_inst_n_34,u_lms_pcore_axi_lite_inst_n_35}),
.\write_reg_d_k_reg[7] ({u_lms_pcore_axi_lite_inst_n_28,u_lms_pcore_axi_lite_inst_n_29,u_lms_pcore_axi_lite_inst_n_30,u_lms_pcore_axi_lite_inst_n_31}),
.\write_reg_x_k_reg[15] (write_reg_x_k));
endmodule |
module ip_design_lms_pcore_0_0_lms_pcore_addr_decoder
(read_reg_cop_out_ready,
write_reg_axi_enable,
S,
Q,
\sync_reg_e_k_reg[11]_0 ,
\sync_reg_e_k_reg[7]_0 ,
\sync_reg_e_k_reg[3]_0 ,
DI,
ARG__29,
\cp_controller_cpstate_reg[0] ,
ARG__28,
\AXI4_Lite_RDATA_tmp_reg[31] ,
strobe_sw_cop_in_strobe,
AXI4_Lite_ACLK,
AR,
cop_out_ready,
\wdata_reg[0] ,
filter_sum,
mul_temp_16,
cp_controller_cpstate,
E,
\wdata_reg[15] ,
wr_enb_1_reg);
output read_reg_cop_out_ready;
output write_reg_axi_enable;
output [3:0]S;
output [14:0]Q;
output [3:0]\sync_reg_e_k_reg[11]_0 ;
output [3:0]\sync_reg_e_k_reg[7]_0 ;
output [3:0]\sync_reg_e_k_reg[3]_0 ;
output [0:0]DI;
output [2:0]ARG__29;
output \cp_controller_cpstate_reg[0] ;
output [15:0]ARG__28;
output [15:0]\AXI4_Lite_RDATA_tmp_reg[31] ;
input strobe_sw_cop_in_strobe;
input AXI4_Lite_ACLK;
input [0:0]AR;
input cop_out_ready;
input \wdata_reg[0] ;
input [15:0]filter_sum;
input [15:0]mul_temp_16;
input [1:0]cp_controller_cpstate;
input [0:0]E;
input [15:0]\wdata_reg[15] ;
input [0:0]wr_enb_1_reg;
wire [0:0]AR;
wire [15:0]ARG__28;
wire [2:0]ARG__29;
wire AXI4_Lite_ACLK;
wire [15:0]\AXI4_Lite_RDATA_tmp_reg[31] ;
wire [0:0]DI;
wire [0:0]E;
wire [14:0]Q;
wire [3:0]S;
wire cop_out_ready;
wire [1:0]cp_controller_cpstate;
wire \cp_controller_cpstate_reg[0] ;
wire [15:0]filter_sum;
wire in_strobe;
wire [15:0]mul_temp_16;
wire read_reg_cop_out_ready;
wire strobe_sw_cop_in_strobe;
wire [3:0]\sync_reg_e_k_reg[11]_0 ;
wire [3:0]\sync_reg_e_k_reg[3]_0 ;
wire [3:0]\sync_reg_e_k_reg[7]_0 ;
wire \wdata_reg[0] ;
wire [15:0]\wdata_reg[15] ;
wire [0:0]wr_enb_1_reg;
wire write_reg_axi_enable;
wire [15:15]write_reg_d_k;
LUT1 #(
.INIT(2'h1))
ARG_carry__0_i_1
(.I0(mul_temp_16[3]),
.O(DI));
LUT1 #(
.INIT(2'h1))
ARG_carry_i_1
(.I0(mul_temp_16[1]),
.O(ARG__29[2]));
LUT1 #(
.INIT(2'h1))
ARG_carry_i_2
(.I0(mul_temp_16[0]),
.O(ARG__29[1]));
LUT1 #(
.INIT(2'h1))
ARG_carry_i_3
(.I0(mul_temp_16[3]),
.O(ARG__29[0]));
LUT4 #(
.INIT(16'h0F20))
\cp_controller_cpstate[0]_i_1
(.I0(in_strobe),
.I1(cp_controller_cpstate[1]),
.I2(write_reg_axi_enable),
.I3(cp_controller_cpstate[0]),
.O(\cp_controller_cpstate_reg[0] ));
FDCE read_reg_cop_out_ready_reg
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(AR),
.D(cop_out_ready),
.Q(read_reg_cop_out_ready));
FDCE strobe_reg_cop_in_strobe_reg
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(AR),
.D(strobe_sw_cop_in_strobe),
.Q(in_strobe));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__0_i_1
(.I0(Q[7]),
.I1(filter_sum[7]),
.O(\sync_reg_e_k_reg[7]_0 [3]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__0_i_2
(.I0(Q[6]),
.I1(filter_sum[6]),
.O(\sync_reg_e_k_reg[7]_0 [2]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__0_i_3
(.I0(Q[5]),
.I1(filter_sum[5]),
.O(\sync_reg_e_k_reg[7]_0 [1]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__0_i_4
(.I0(Q[4]),
.I1(filter_sum[4]),
.O(\sync_reg_e_k_reg[7]_0 [0]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__1_i_1
(.I0(Q[11]),
.I1(filter_sum[11]),
.O(\sync_reg_e_k_reg[11]_0 [3]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__1_i_2
(.I0(Q[10]),
.I1(filter_sum[10]),
.O(\sync_reg_e_k_reg[11]_0 [2]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__1_i_3
(.I0(Q[9]),
.I1(filter_sum[9]),
.O(\sync_reg_e_k_reg[11]_0 [1]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__1_i_4
(.I0(Q[8]),
.I1(filter_sum[8]),
.O(\sync_reg_e_k_reg[11]_0 [0]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__2_i_1
(.I0(write_reg_d_k),
.I1(filter_sum[15]),
.O(S[3]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__2_i_2
(.I0(Q[14]),
.I1(filter_sum[14]),
.O(S[2]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__2_i_3
(.I0(Q[13]),
.I1(filter_sum[13]),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__2_i_4
(.I0(Q[12]),
.I1(filter_sum[12]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry_i_1
(.I0(Q[3]),
.I1(filter_sum[3]),
.O(\sync_reg_e_k_reg[3]_0 [3]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry_i_2
(.I0(Q[2]),
.I1(filter_sum[2]),
.O(\sync_reg_e_k_reg[3]_0 [2]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry_i_3
(.I0(Q[1]),
.I1(filter_sum[1]),
.O(\sync_reg_e_k_reg[3]_0 [1]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry_i_4
(.I0(Q[0]),
.I1(filter_sum[0]),
.O(\sync_reg_e_k_reg[3]_0 [0]));
FDCE \sync_reg_e_k_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[0]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [0]));
FDCE \sync_reg_e_k_reg[10]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[10]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [10]));
FDCE \sync_reg_e_k_reg[11]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[11]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [11]));
FDCE \sync_reg_e_k_reg[12]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[12]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [12]));
FDCE \sync_reg_e_k_reg[13]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[13]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [13]));
FDCE \sync_reg_e_k_reg[14]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[14]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [14]));
FDCE \sync_reg_e_k_reg[15]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[15]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [15]));
FDCE \sync_reg_e_k_reg[1]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[1]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [1]));
FDCE \sync_reg_e_k_reg[2]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[2]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [2]));
FDCE \sync_reg_e_k_reg[3]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[3]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [3]));
FDCE \sync_reg_e_k_reg[4]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[4]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [4]));
FDCE \sync_reg_e_k_reg[5]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[5]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [5]));
FDCE \sync_reg_e_k_reg[6]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[6]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [6]));
FDCE \sync_reg_e_k_reg[7]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[7]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [7]));
FDCE \sync_reg_e_k_reg[8]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[8]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [8]));
FDCE \sync_reg_e_k_reg[9]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[9]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [9]));
FDPE write_reg_axi_enable_reg
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.D(\wdata_reg[0] ),
.PRE(AR),
.Q(write_reg_axi_enable));
FDCE \write_reg_d_k_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [0]),
.Q(Q[0]));
FDCE \write_reg_d_k_reg[10]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [10]),
.Q(Q[10]));
FDCE \write_reg_d_k_reg[11]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [11]),
.Q(Q[11]));
FDCE \write_reg_d_k_reg[12]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [12]),
.Q(Q[12]));
FDCE \write_reg_d_k_reg[13]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [13]),
.Q(Q[13]));
FDCE \write_reg_d_k_reg[14]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [14]),
.Q(Q[14]));
FDCE \write_reg_d_k_reg[15]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [15]),
.Q(write_reg_d_k));
FDCE \write_reg_d_k_reg[1]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [1]),
.Q(Q[1]));
FDCE \write_reg_d_k_reg[2]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [2]),
.Q(Q[2]));
FDCE \write_reg_d_k_reg[3]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [3]),
.Q(Q[3]));
FDCE \write_reg_d_k_reg[4]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [4]),
.Q(Q[4]));
FDCE \write_reg_d_k_reg[5]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [5]),
.Q(Q[5]));
FDCE \write_reg_d_k_reg[6]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [6]),
.Q(Q[6]));
FDCE \write_reg_d_k_reg[7]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [7]),
.Q(Q[7]));
FDCE \write_reg_d_k_reg[8]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [8]),
.Q(Q[8]));
FDCE \write_reg_d_k_reg[9]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [9]),
.Q(Q[9]));
FDCE \write_reg_x_k_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [0]),
.Q(ARG__28[0]));
FDCE \write_reg_x_k_reg[10]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [10]),
.Q(ARG__28[10]));
FDCE \write_reg_x_k_reg[11]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [11]),
.Q(ARG__28[11]));
FDCE \write_reg_x_k_reg[12]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [12]),
.Q(ARG__28[12]));
FDCE \write_reg_x_k_reg[13]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [13]),
.Q(ARG__28[13]));
FDCE \write_reg_x_k_reg[14]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [14]),
.Q(ARG__28[14]));
FDCE \write_reg_x_k_reg[15]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [15]),
.Q(ARG__28[15]));
FDCE \write_reg_x_k_reg[1]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [1]),
.Q(ARG__28[1]));
FDCE \write_reg_x_k_reg[2]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [2]),
.Q(ARG__28[2]));
FDCE \write_reg_x_k_reg[3]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [3]),
.Q(ARG__28[3]));
FDCE \write_reg_x_k_reg[4]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [4]),
.Q(ARG__28[4]));
FDCE \write_reg_x_k_reg[5]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [5]),
.Q(ARG__28[5]));
FDCE \write_reg_x_k_reg[6]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [6]),
.Q(ARG__28[6]));
FDCE \write_reg_x_k_reg[7]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [7]),
.Q(ARG__28[7]));
FDCE \write_reg_x_k_reg[8]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [8]),
.Q(ARG__28[8]));
FDCE \write_reg_x_k_reg[9]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [9]),
.Q(ARG__28[9]));
endmodule |
module ip_design_lms_pcore_0_0_lms_pcore_axi_lite
(write_reg_axi_enable_reg,
AXI4_Lite_RVALID,
write_reg_axi_enable,
AXI4_Lite_WREADY,
AXI4_Lite_BVALID,
S,
Q,
\sync_reg_e_k_reg[11] ,
\sync_reg_e_k_reg[7] ,
\sync_reg_e_k_reg[3] ,
DI,
ARG__29,
\cp_controller_cpstate_reg[0] ,
ARG__28,
AXI4_Lite_RDATA,
AXI4_Lite_AWREADY,
AXI4_Lite_ARREADY,
AXI4_Lite_ACLK,
cop_out_ready,
AXI4_Lite_AWVALID,
AXI4_Lite_WVALID,
AXI4_Lite_ARESETN,
IPCORE_RESETN,
filter_sum,
mul_temp_16,
cp_controller_cpstate,
AXI4_Lite_WDATA,
AXI4_Lite_AWADDR,
AXI4_Lite_BREADY,
AXI4_Lite_ARVALID,
AXI4_Lite_ARADDR,
AXI4_Lite_RREADY);
output write_reg_axi_enable_reg;
output AXI4_Lite_RVALID;
output write_reg_axi_enable;
output AXI4_Lite_WREADY;
output AXI4_Lite_BVALID;
output [3:0]S;
output [14:0]Q;
output [3:0]\sync_reg_e_k_reg[11] ;
output [3:0]\sync_reg_e_k_reg[7] ;
output [3:0]\sync_reg_e_k_reg[3] ;
output [0:0]DI;
output [2:0]ARG__29;
output \cp_controller_cpstate_reg[0] ;
output [15:0]ARG__28;
output [15:0]AXI4_Lite_RDATA;
output AXI4_Lite_AWREADY;
output AXI4_Lite_ARREADY;
input AXI4_Lite_ACLK;
input cop_out_ready;
input AXI4_Lite_AWVALID;
input AXI4_Lite_WVALID;
input AXI4_Lite_ARESETN;
input IPCORE_RESETN;
input [15:0]filter_sum;
input [15:0]mul_temp_16;
input [1:0]cp_controller_cpstate;
input [15:0]AXI4_Lite_WDATA;
input [13:0]AXI4_Lite_AWADDR;
input AXI4_Lite_BREADY;
input AXI4_Lite_ARVALID;
input [13:0]AXI4_Lite_ARADDR;
input AXI4_Lite_RREADY;
wire [15:0]ARG__28;
wire [2:0]ARG__29;
wire AXI4_Lite_ACLK;
wire [13:0]AXI4_Lite_ARADDR;
wire AXI4_Lite_ARESETN;
wire AXI4_Lite_ARREADY;
wire AXI4_Lite_ARVALID;
wire [13:0]AXI4_Lite_AWADDR;
wire AXI4_Lite_AWREADY;
wire AXI4_Lite_AWVALID;
wire AXI4_Lite_BREADY;
wire AXI4_Lite_BVALID;
wire [15:0]AXI4_Lite_RDATA;
wire AXI4_Lite_RREADY;
wire AXI4_Lite_RVALID;
wire [15:0]AXI4_Lite_WDATA;
wire AXI4_Lite_WREADY;
wire AXI4_Lite_WVALID;
wire [0:0]DI;
wire IPCORE_RESETN;
wire [14:0]Q;
wire [3:0]S;
wire cop_out_ready;
wire [1:0]cp_controller_cpstate;
wire \cp_controller_cpstate_reg[0] ;
wire [15:0]filter_sum;
wire [15:0]mul_temp_16;
wire read_reg_cop_out_ready;
wire reg_enb_d_k;
wire reg_enb_x_k;
wire strobe_sw_cop_in_strobe;
wire [15:0]sync_reg_e_k;
wire [3:0]\sync_reg_e_k_reg[11] ;
wire [3:0]\sync_reg_e_k_reg[3] ;
wire [3:0]\sync_reg_e_k_reg[7] ;
wire [0:0]top_data_write;
wire u_lms_pcore_axi_lite_module_inst_n_10;
wire u_lms_pcore_axi_lite_module_inst_n_11;
wire u_lms_pcore_axi_lite_module_inst_n_12;
wire u_lms_pcore_axi_lite_module_inst_n_13;
wire u_lms_pcore_axi_lite_module_inst_n_14;
wire u_lms_pcore_axi_lite_module_inst_n_15;
wire u_lms_pcore_axi_lite_module_inst_n_16;
wire u_lms_pcore_axi_lite_module_inst_n_17;
wire u_lms_pcore_axi_lite_module_inst_n_18;
wire u_lms_pcore_axi_lite_module_inst_n_19;
wire u_lms_pcore_axi_lite_module_inst_n_4;
wire u_lms_pcore_axi_lite_module_inst_n_5;
wire u_lms_pcore_axi_lite_module_inst_n_6;
wire u_lms_pcore_axi_lite_module_inst_n_7;
wire u_lms_pcore_axi_lite_module_inst_n_8;
wire u_lms_pcore_axi_lite_module_inst_n_9;
wire write_reg_axi_enable;
wire write_reg_axi_enable_reg;
ip_design_lms_pcore_0_0_lms_pcore_addr_decoder u_lms_pcore_addr_decoder_inst
(.AR(write_reg_axi_enable_reg),
.ARG__28(ARG__28),
.ARG__29(ARG__29),
.AXI4_Lite_ACLK(AXI4_Lite_ACLK),
.\AXI4_Lite_RDATA_tmp_reg[31] (sync_reg_e_k),
.DI(DI),
.E(reg_enb_x_k),
.Q(Q),
.S(S),
.cop_out_ready(cop_out_ready),
.cp_controller_cpstate(cp_controller_cpstate),
.\cp_controller_cpstate_reg[0] (\cp_controller_cpstate_reg[0] ),
.filter_sum(filter_sum),
.mul_temp_16(mul_temp_16),
.read_reg_cop_out_ready(read_reg_cop_out_ready),
.strobe_sw_cop_in_strobe(strobe_sw_cop_in_strobe),
.\sync_reg_e_k_reg[11]_0 (\sync_reg_e_k_reg[11] ),
.\sync_reg_e_k_reg[3]_0 (\sync_reg_e_k_reg[3] ),
.\sync_reg_e_k_reg[7]_0 (\sync_reg_e_k_reg[7] ),
.\wdata_reg[0] (u_lms_pcore_axi_lite_module_inst_n_4),
.\wdata_reg[15] ({u_lms_pcore_axi_lite_module_inst_n_5,u_lms_pcore_axi_lite_module_inst_n_6,u_lms_pcore_axi_lite_module_inst_n_7,u_lms_pcore_axi_lite_module_inst_n_8,u_lms_pcore_axi_lite_module_inst_n_9,u_lms_pcore_axi_lite_module_inst_n_10,u_lms_pcore_axi_lite_module_inst_n_11,u_lms_pcore_axi_lite_module_inst_n_12,u_lms_pcore_axi_lite_module_inst_n_13,u_lms_pcore_axi_lite_module_inst_n_14,u_lms_pcore_axi_lite_module_inst_n_15,u_lms_pcore_axi_lite_module_inst_n_16,u_lms_pcore_axi_lite_module_inst_n_17,u_lms_pcore_axi_lite_module_inst_n_18,u_lms_pcore_axi_lite_module_inst_n_19,top_data_write}),
.wr_enb_1_reg(reg_enb_d_k),
.write_reg_axi_enable(write_reg_axi_enable));
ip_design_lms_pcore_0_0_lms_pcore_axi_lite_module u_lms_pcore_axi_lite_module_inst
(.AXI4_Lite_ACLK(AXI4_Lite_ACLK),
.AXI4_Lite_ARADDR(AXI4_Lite_ARADDR),
.AXI4_Lite_ARESETN(AXI4_Lite_ARESETN),
.AXI4_Lite_ARREADY(AXI4_Lite_ARREADY),
.AXI4_Lite_ARVALID(AXI4_Lite_ARVALID),
.AXI4_Lite_AWADDR(AXI4_Lite_AWADDR),
.AXI4_Lite_AWREADY(AXI4_Lite_AWREADY),
.AXI4_Lite_AWVALID(AXI4_Lite_AWVALID),
.AXI4_Lite_BREADY(AXI4_Lite_BREADY),
.AXI4_Lite_BVALID(AXI4_Lite_BVALID),
.AXI4_Lite_RDATA(AXI4_Lite_RDATA),
.AXI4_Lite_RREADY(AXI4_Lite_RREADY),
.AXI4_Lite_RVALID(AXI4_Lite_RVALID),
.AXI4_Lite_WDATA(AXI4_Lite_WDATA),
.AXI4_Lite_WREADY(AXI4_Lite_WREADY),
.AXI4_Lite_WVALID(AXI4_Lite_WVALID),
.E(reg_enb_x_k),
.IPCORE_RESETN(IPCORE_RESETN),
.Q({u_lms_pcore_axi_lite_module_inst_n_5,u_lms_pcore_axi_lite_module_inst_n_6,u_lms_pcore_axi_lite_module_inst_n_7,u_lms_pcore_axi_lite_module_inst_n_8,u_lms_pcore_axi_lite_module_inst_n_9,u_lms_pcore_axi_lite_module_inst_n_10,u_lms_pcore_axi_lite_module_inst_n_11,u_lms_pcore_axi_lite_module_inst_n_12,u_lms_pcore_axi_lite_module_inst_n_13,u_lms_pcore_axi_lite_module_inst_n_14,u_lms_pcore_axi_lite_module_inst_n_15,u_lms_pcore_axi_lite_module_inst_n_16,u_lms_pcore_axi_lite_module_inst_n_17,u_lms_pcore_axi_lite_module_inst_n_18,u_lms_pcore_axi_lite_module_inst_n_19,top_data_write}),
.read_reg_cop_out_ready(read_reg_cop_out_ready),
.strobe_sw_cop_in_strobe(strobe_sw_cop_in_strobe),
.\sync_reg_e_k_reg[15] (sync_reg_e_k),
.write_reg_axi_enable(write_reg_axi_enable),
.write_reg_axi_enable_reg(write_reg_axi_enable_reg),
.write_reg_axi_enable_reg_0(u_lms_pcore_axi_lite_module_inst_n_4),
.\write_reg_d_k_reg[15] (reg_enb_d_k));
endmodule |
module ip_design_lms_pcore_0_0_lms_pcore_axi_lite_module
(AXI4_Lite_RVALID,
write_reg_axi_enable_reg,
AXI4_Lite_WREADY,
AXI4_Lite_BVALID,
write_reg_axi_enable_reg_0,
Q,
AXI4_Lite_RDATA,
AXI4_Lite_AWREADY,
strobe_sw_cop_in_strobe,
\write_reg_d_k_reg[15] ,
E,
AXI4_Lite_ARREADY,
AXI4_Lite_ACLK,
AXI4_Lite_AWVALID,
AXI4_Lite_WVALID,
AXI4_Lite_ARESETN,
IPCORE_RESETN,
write_reg_axi_enable,
AXI4_Lite_WDATA,
AXI4_Lite_AWADDR,
AXI4_Lite_BREADY,
\sync_reg_e_k_reg[15] ,
AXI4_Lite_ARVALID,
AXI4_Lite_ARADDR,
read_reg_cop_out_ready,
AXI4_Lite_RREADY);
output AXI4_Lite_RVALID;
output write_reg_axi_enable_reg;
output AXI4_Lite_WREADY;
output AXI4_Lite_BVALID;
output write_reg_axi_enable_reg_0;
output [15:0]Q;
output [15:0]AXI4_Lite_RDATA;
output AXI4_Lite_AWREADY;
output strobe_sw_cop_in_strobe;
output [0:0]\write_reg_d_k_reg[15] ;
output [0:0]E;
output AXI4_Lite_ARREADY;
input AXI4_Lite_ACLK;
input AXI4_Lite_AWVALID;
input AXI4_Lite_WVALID;
input AXI4_Lite_ARESETN;
input IPCORE_RESETN;
input write_reg_axi_enable;
input [15:0]AXI4_Lite_WDATA;
input [13:0]AXI4_Lite_AWADDR;
input AXI4_Lite_BREADY;
input [15:0]\sync_reg_e_k_reg[15] ;
input AXI4_Lite_ARVALID;
input [13:0]AXI4_Lite_ARADDR;
input read_reg_cop_out_ready;
input AXI4_Lite_RREADY;
wire AXI4_Lite_ACLK;
wire [13:0]AXI4_Lite_ARADDR;
wire AXI4_Lite_ARESETN;
wire AXI4_Lite_ARREADY;
wire AXI4_Lite_ARVALID;
wire [13:0]AXI4_Lite_AWADDR;
wire AXI4_Lite_AWREADY;
wire AXI4_Lite_AWVALID;
wire AXI4_Lite_BREADY;
wire AXI4_Lite_BVALID;
wire [15:0]AXI4_Lite_RDATA;
wire \AXI4_Lite_RDATA_tmp[0]_i_2_n_0 ;
wire \AXI4_Lite_RDATA_tmp[0]_i_3_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_10_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_11_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_12_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_9_n_0 ;
wire AXI4_Lite_RREADY;
wire AXI4_Lite_RVALID;
wire [15:0]AXI4_Lite_WDATA;
wire AXI4_Lite_WREADY;
wire AXI4_Lite_WVALID;
wire [0:0]E;
wire IPCORE_RESETN;
wire [15:0]Q;
wire aw_transfer;
wire \axi_lite_rstate[0]_i_1_n_0 ;
wire [1:0]axi_lite_wstate;
wire \axi_lite_wstate[0]_i_1_n_0 ;
wire \axi_lite_wstate_next_inferred__1/i__n_0 ;
wire [31:0]data_read;
wire read_reg_cop_out_ready;
wire reset;
wire [13:0]sel0;
wire soft_reset;
wire soft_reset_i_2_n_0;
wire soft_reset_i_3_n_0;
wire soft_reset_i_4_n_0;
wire strobe_reg_cop_in_strobe_i_3_n_0;
wire strobe_sw;
wire strobe_sw_cop_in_strobe;
wire [15:0]\sync_reg_e_k_reg[15] ;
wire top_rd_enb;
wire top_wr_enb;
wire w_transfer;
wire write_reg_axi_enable;
wire write_reg_axi_enable_i_2_n_0;
wire write_reg_axi_enable_reg;
wire write_reg_axi_enable_reg_0;
wire [0:0]\write_reg_d_k_reg[15] ;
LUT1 #(
.INIT(2'h1))
AXI4_Lite_ARREADY_INST_0
(.I0(AXI4_Lite_RVALID),
.O(AXI4_Lite_ARREADY));
LUT2 #(
.INIT(4'h1))
AXI4_Lite_AWREADY_INST_0
(.I0(axi_lite_wstate[0]),
.I1(axi_lite_wstate[1]),
.O(AXI4_Lite_AWREADY));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
AXI4_Lite_BVALID_INST_0
(.I0(axi_lite_wstate[1]),
.I1(axi_lite_wstate[0]),
.O(AXI4_Lite_BVALID));
LUT6 #(
.INIT(64'h00008CCC00008000))
\AXI4_Lite_RDATA_tmp[0]_i_1
(.I0(\sync_reg_e_k_reg[15] [0]),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[0]_i_2_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I5(\AXI4_Lite_RDATA_tmp[0]_i_3_n_0 ),
.O(data_read[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h000ACC0A))
\AXI4_Lite_RDATA_tmp[0]_i_2
(.I0(sel0[6]),
.I1(AXI4_Lite_ARADDR[6]),
.I2(sel0[0]),
.I3(AXI4_Lite_ARVALID),
.I4(AXI4_Lite_ARADDR[0]),
.O(\AXI4_Lite_RDATA_tmp[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000B80000000000))
\AXI4_Lite_RDATA_tmp[0]_i_3
(.I0(AXI4_Lite_ARADDR[0]),
.I1(AXI4_Lite_ARVALID),
.I2(sel0[0]),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I5(read_reg_cop_out_ready),
.O(\AXI4_Lite_RDATA_tmp[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[10]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [10]),
.O(data_read[10]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[11]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [11]),
.O(data_read[11]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[12]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [12]),
.O(data_read[12]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[13]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [13]),
.O(data_read[13]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[14]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [14]),
.O(data_read[14]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[1]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [1]),
.O(data_read[1]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[2]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [2]),
.O(data_read[2]));
LUT2 #(
.INIT(4'h2))
\AXI4_Lite_RDATA_tmp[31]_i_1
(.I0(AXI4_Lite_ARVALID),
.I1(AXI4_Lite_RVALID),
.O(top_rd_enb));
LUT5 #(
.INIT(32'hFFEEF0EE))
\AXI4_Lite_RDATA_tmp[31]_i_10
(.I0(sel0[5]),
.I1(sel0[4]),
.I2(AXI4_Lite_ARADDR[5]),
.I3(AXI4_Lite_ARVALID),
.I4(AXI4_Lite_ARADDR[4]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_10_n_0 ));
LUT5 #(
.INIT(32'hFFEEF0EE))
\AXI4_Lite_RDATA_tmp[31]_i_11
(.I0(sel0[3]),
.I1(sel0[2]),
.I2(AXI4_Lite_ARADDR[3]),
.I3(AXI4_Lite_ARVALID),
.I4(AXI4_Lite_ARADDR[2]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_11_n_0 ));
LUT5 #(
.INIT(32'hFFEEF0EE))
\AXI4_Lite_RDATA_tmp[31]_i_12
(.I0(sel0[9]),
.I1(sel0[8]),
.I2(AXI4_Lite_ARADDR[9]),
.I3(AXI4_Lite_ARVALID),
.I4(AXI4_Lite_ARADDR[8]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_12_n_0 ));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[31]_i_2
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [15]),
.O(data_read[31]));
LUT1 #(
.INIT(2'h1))
\AXI4_Lite_RDATA_tmp[31]_i_3
(.I0(AXI4_Lite_ARESETN),
.O(reset));
LUT6 #(
.INIT(64'hFFFFEFEFFFFAEFEA))
\AXI4_Lite_RDATA_tmp[31]_i_4
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_9_n_0 ),
.I1(AXI4_Lite_ARADDR[10]),
.I2(AXI4_Lite_ARVALID),
.I3(sel0[10]),
.I4(AXI4_Lite_ARADDR[11]),
.I5(sel0[11]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hB8))
\AXI4_Lite_RDATA_tmp[31]_i_5
(.I0(AXI4_Lite_ARADDR[1]),
.I1(AXI4_Lite_ARVALID),
.I2(sel0[1]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\AXI4_Lite_RDATA_tmp[31]_i_6
(.I0(AXI4_Lite_ARADDR[6]),
.I1(AXI4_Lite_ARVALID),
.I2(sel0[6]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\AXI4_Lite_RDATA_tmp[31]_i_7
(.I0(AXI4_Lite_ARADDR[0]),
.I1(AXI4_Lite_ARVALID),
.I2(sel0[0]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ));
LUT5 #(
.INIT(32'h00011101))
\AXI4_Lite_RDATA_tmp[31]_i_8
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_10_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_11_n_0 ),
.I2(sel0[7]),
.I3(AXI4_Lite_ARVALID),
.I4(AXI4_Lite_ARADDR[7]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFBBFCB8))
\AXI4_Lite_RDATA_tmp[31]_i_9
(.I0(AXI4_Lite_ARADDR[13]),
.I1(AXI4_Lite_ARVALID),
.I2(sel0[13]),
.I3(AXI4_Lite_ARADDR[12]),
.I4(sel0[12]),
.I5(\AXI4_Lite_RDATA_tmp[31]_i_12_n_0 ),
.O(\AXI4_Lite_RDATA_tmp[31]_i_9_n_0 ));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[3]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [3]),
.O(data_read[3]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[4]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [4]),
.O(data_read[4]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[5]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [5]),
.O(data_read[5]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[6]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [6]),
.O(data_read[6]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[7]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [7]),
.O(data_read[7]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[8]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [8]),
.O(data_read[8]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[9]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [9]),
.O(data_read[9]));
FDCE \AXI4_Lite_RDATA_tmp_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[0]),
.Q(AXI4_Lite_RDATA[0]));
FDCE \AXI4_Lite_RDATA_tmp_reg[10]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[10]),
.Q(AXI4_Lite_RDATA[10]));
FDCE \AXI4_Lite_RDATA_tmp_reg[11]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[11]),
.Q(AXI4_Lite_RDATA[11]));
FDCE \AXI4_Lite_RDATA_tmp_reg[12]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[12]),
.Q(AXI4_Lite_RDATA[12]));
FDCE \AXI4_Lite_RDATA_tmp_reg[13]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[13]),
.Q(AXI4_Lite_RDATA[13]));
FDCE \AXI4_Lite_RDATA_tmp_reg[14]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[14]),
.Q(AXI4_Lite_RDATA[14]));
FDCE \AXI4_Lite_RDATA_tmp_reg[1]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[1]),
.Q(AXI4_Lite_RDATA[1]));
FDCE \AXI4_Lite_RDATA_tmp_reg[2]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[2]),
.Q(AXI4_Lite_RDATA[2]));
FDCE \AXI4_Lite_RDATA_tmp_reg[31]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[31]),
.Q(AXI4_Lite_RDATA[15]));
FDCE \AXI4_Lite_RDATA_tmp_reg[3]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[3]),
.Q(AXI4_Lite_RDATA[3]));
FDCE \AXI4_Lite_RDATA_tmp_reg[4]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[4]),
.Q(AXI4_Lite_RDATA[4]));
FDCE \AXI4_Lite_RDATA_tmp_reg[5]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[5]),
.Q(AXI4_Lite_RDATA[5]));
FDCE \AXI4_Lite_RDATA_tmp_reg[6]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[6]),
.Q(AXI4_Lite_RDATA[6]));
FDCE \AXI4_Lite_RDATA_tmp_reg[7]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[7]),
.Q(AXI4_Lite_RDATA[7]));
FDCE \AXI4_Lite_RDATA_tmp_reg[8]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[8]),
.Q(AXI4_Lite_RDATA[8]));
FDCE \AXI4_Lite_RDATA_tmp_reg[9]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[9]),
.Q(AXI4_Lite_RDATA[9]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
AXI4_Lite_WREADY_INST_0
(.I0(axi_lite_wstate[0]),
.I1(axi_lite_wstate[1]),
.O(AXI4_Lite_WREADY));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h74))
\axi_lite_rstate[0]_i_1
(.I0(AXI4_Lite_RREADY),
.I1(AXI4_Lite_RVALID),
.I2(AXI4_Lite_ARVALID),
.O(\axi_lite_rstate[0]_i_1_n_0 ));
FDCE \axi_lite_rstate_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(reset),
.D(\axi_lite_rstate[0]_i_1_n_0 ),
.Q(AXI4_Lite_RVALID));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h002E))
\axi_lite_wstate[0]_i_1
(.I0(AXI4_Lite_AWVALID),
.I1(axi_lite_wstate[0]),
.I2(AXI4_Lite_WVALID),
.I3(axi_lite_wstate[1]),
.O(\axi_lite_wstate[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0838))
\axi_lite_wstate_next_inferred__1/i_
(.I0(AXI4_Lite_WVALID),
.I1(axi_lite_wstate[0]),
.I2(axi_lite_wstate[1]),
.I3(AXI4_Lite_BREADY),
.O(\axi_lite_wstate_next_inferred__1/i__n_0 ));
FDCE \axi_lite_wstate_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(reset),
.D(\axi_lite_wstate[0]_i_1_n_0 ),
.Q(axi_lite_wstate[0]));
FDCE \axi_lite_wstate_reg[1]
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(reset),
.D(\axi_lite_wstate_next_inferred__1/i__n_0 ),
.Q(axi_lite_wstate[1]));
LUT6 #(
.INIT(64'h0000000200000000))
soft_reset_i_1
(.I0(soft_reset_i_2_n_0),
.I1(sel0[1]),
.I2(sel0[0]),
.I3(sel0[7]),
.I4(sel0[6]),
.I5(soft_reset_i_3_n_0),
.O(strobe_sw));
LUT4 #(
.INIT(16'h0001))
soft_reset_i_2
(.I0(sel0[13]),
.I1(sel0[12]),
.I2(sel0[11]),
.I3(sel0[10]),
.O(soft_reset_i_2_n_0));
LUT5 #(
.INIT(32'h00010000))
soft_reset_i_3
(.I0(sel0[2]),
.I1(sel0[3]),
.I2(sel0[8]),
.I3(sel0[9]),
.I4(soft_reset_i_4_n_0),
.O(soft_reset_i_3_n_0));
LUT4 #(
.INIT(16'h0008))
soft_reset_i_4
(.I0(top_wr_enb),
.I1(Q[0]),
.I2(sel0[5]),
.I3(sel0[4]),
.O(soft_reset_i_4_n_0));
FDCE soft_reset_reg
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(reset),
.D(strobe_sw),
.Q(soft_reset));
LUT6 #(
.INIT(64'h0000000020000000))
strobe_reg_cop_in_strobe_i_1
(.I0(Q[0]),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I2(strobe_reg_cop_in_strobe_i_3_n_0),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I4(top_wr_enb),
.I5(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.O(strobe_sw_cop_in_strobe));
LUT3 #(
.INIT(8'hDF))
strobe_reg_cop_in_strobe_i_2
(.I0(AXI4_Lite_ARESETN),
.I1(soft_reset),
.I2(IPCORE_RESETN),
.O(write_reg_axi_enable_reg));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h000ACC0A))
strobe_reg_cop_in_strobe_i_3
(.I0(sel0[1]),
.I1(AXI4_Lite_ARADDR[1]),
.I2(sel0[0]),
.I3(AXI4_Lite_ARVALID),
.I4(AXI4_Lite_ARADDR[0]),
.O(strobe_reg_cop_in_strobe_i_3_n_0));
LUT3 #(
.INIT(8'h02))
\waddr[15]_i_1
(.I0(AXI4_Lite_AWVALID),
.I1(axi_lite_wstate[1]),
.I2(axi_lite_wstate[0]),
.O(aw_transfer));
FDCE \waddr_reg[10]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[8]),
.Q(sel0[8]));
FDCE \waddr_reg[11]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[9]),
.Q(sel0[9]));
FDCE \waddr_reg[12]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[10]),
.Q(sel0[10]));
FDCE \waddr_reg[13]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[11]),
.Q(sel0[11]));
FDCE \waddr_reg[14]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[12]),
.Q(sel0[12]));
FDCE \waddr_reg[15]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[13]),
.Q(sel0[13]));
FDCE \waddr_reg[2]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[0]),
.Q(sel0[0]));
FDCE \waddr_reg[3]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[1]),
.Q(sel0[1]));
FDCE \waddr_reg[4]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[2]),
.Q(sel0[2]));
FDCE \waddr_reg[5]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[3]),
.Q(sel0[3]));
FDCE \waddr_reg[6]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[4]),
.Q(sel0[4]));
FDCE \waddr_reg[7]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[5]),
.Q(sel0[5]));
FDCE \waddr_reg[8]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[6]),
.Q(sel0[6]));
FDCE \waddr_reg[9]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[7]),
.Q(sel0[7]));
LUT3 #(
.INIT(8'h20))
\wdata[15]_i_1
(.I0(AXI4_Lite_WVALID),
.I1(axi_lite_wstate[1]),
.I2(axi_lite_wstate[0]),
.O(w_transfer));
FDCE \wdata_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[0]),
.Q(Q[0]));
FDCE \wdata_reg[10]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[10]),
.Q(Q[10]));
FDCE \wdata_reg[11]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[11]),
.Q(Q[11]));
FDCE \wdata_reg[12]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[12]),
.Q(Q[12]));
FDCE \wdata_reg[13]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[13]),
.Q(Q[13]));
FDCE \wdata_reg[14]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[14]),
.Q(Q[14]));
FDCE \wdata_reg[15]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[15]),
.Q(Q[15]));
FDCE \wdata_reg[1]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[1]),
.Q(Q[1]));
FDCE \wdata_reg[2]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[2]),
.Q(Q[2]));
FDCE \wdata_reg[3]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[3]),
.Q(Q[3]));
FDCE \wdata_reg[4]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[4]),
.Q(Q[4]));
FDCE \wdata_reg[5]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[5]),
.Q(Q[5]));
FDCE \wdata_reg[6]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[6]),
.Q(Q[6]));
FDCE \wdata_reg[7]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[7]),
.Q(Q[7]));
FDCE \wdata_reg[8]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[8]),
.Q(Q[8]));
FDCE \wdata_reg[9]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[9]),
.Q(Q[9]));
FDCE wr_enb_1_reg
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(reset),
.D(w_transfer),
.Q(top_wr_enb));
LUT6 #(
.INIT(64'hFFFFBFFF00008000))
write_reg_axi_enable_i_1
(.I0(Q[0]),
.I1(write_reg_axi_enable_i_2_n_0),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I3(top_wr_enb),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I5(write_reg_axi_enable),
.O(write_reg_axi_enable_reg_0));
LUT6 #(
.INIT(64'h0000000047034400))
write_reg_axi_enable_i_2
(.I0(AXI4_Lite_ARADDR[6]),
.I1(AXI4_Lite_ARVALID),
.I2(sel0[6]),
.I3(AXI4_Lite_ARADDR[0]),
.I4(sel0[0]),
.I5(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.O(write_reg_axi_enable_i_2_n_0));
LUT6 #(
.INIT(64'h0000000040000000))
\write_reg_d_k[15]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I4(top_wr_enb),
.I5(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.O(\write_reg_d_k_reg[15] ));
LUT6 #(
.INIT(64'h0000000004000000))
\write_reg_x_k[15]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I4(top_wr_enb),
.I5(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.O(E));
endmodule |
module ip_design_lms_pcore_0_0_lms_pcore_cop
(cp_controller_cpstate,
cop_out_ready,
cop_dut_enable,
strobe_reg_cop_in_strobe_reg,
IPCORE_CLK,
AR,
write_reg_axi_enable);
output [1:0]cp_controller_cpstate;
output cop_out_ready;
output cop_dut_enable;
input strobe_reg_cop_in_strobe_reg;
input IPCORE_CLK;
input [0:0]AR;
input write_reg_axi_enable;
wire [0:0]AR;
wire IPCORE_CLK;
wire cop_dut_enable;
wire cop_out_ready;
wire [1:0]cp_controller_cpstate;
wire \cp_controller_cpstate[1]_i_1_n_0 ;
wire strobe_reg_cop_in_strobe_reg;
wire write_reg_axi_enable;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h38))
\cp_controller_cpstate[1]_i_1
(.I0(cp_controller_cpstate[0]),
.I1(write_reg_axi_enable),
.I2(cp_controller_cpstate[1]),
.O(\cp_controller_cpstate[1]_i_1_n_0 ));
FDCE \cp_controller_cpstate_reg[0]
(.C(IPCORE_CLK),
.CE(1'b1),
.CLR(AR),
.D(strobe_reg_cop_in_strobe_reg),
.Q(cp_controller_cpstate[0]));
FDCE \cp_controller_cpstate_reg[1]
(.C(IPCORE_CLK),
.CE(1'b1),
.CLR(AR),
.D(\cp_controller_cpstate[1]_i_1_n_0 ),
.Q(cp_controller_cpstate[1]));
LUT2 #(
.INIT(4'h2))
\data_pipeline_tmp[14][15]_i_1
(.I0(cp_controller_cpstate[0]),
.I1(cp_controller_cpstate[1]),
.O(cop_dut_enable));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h1))
read_reg_cop_out_ready_i_1
(.I0(cp_controller_cpstate[0]),
.I1(cp_controller_cpstate[1]),
.O(cop_out_ready));
endmodule |
module ip_design_lms_pcore_0_0_lms_pcore_dut
(mul_temp_16,
filter_sum,
\write_reg_x_k_reg[15] ,
cop_dut_enable,
IPCORE_CLK,
AR,
\write_reg_d_k_reg[3] ,
DI,
Q,
\write_reg_d_k_reg[3]_0 ,
\write_reg_d_k_reg[7] ,
\write_reg_d_k_reg[11] ,
S);
output [15:0]mul_temp_16;
output [15:0]filter_sum;
input [15:0]\write_reg_x_k_reg[15] ;
input cop_dut_enable;
input IPCORE_CLK;
input [0:0]AR;
input [2:0]\write_reg_d_k_reg[3] ;
input [0:0]DI;
input [14:0]Q;
input [3:0]\write_reg_d_k_reg[3]_0 ;
input [3:0]\write_reg_d_k_reg[7] ;
input [3:0]\write_reg_d_k_reg[11] ;
input [3:0]S;
wire [0:0]AR;
wire [0:0]DI;
wire IPCORE_CLK;
wire [14:0]Q;
wire [3:0]S;
wire cop_dut_enable;
wire [15:0]filter_sum;
wire [15:0]mul_temp_16;
wire [3:0]\write_reg_d_k_reg[11] ;
wire [2:0]\write_reg_d_k_reg[3] ;
wire [3:0]\write_reg_d_k_reg[3]_0 ;
wire [3:0]\write_reg_d_k_reg[7] ;
wire [15:0]\write_reg_x_k_reg[15] ;
ip_design_lms_pcore_0_0_LMS u_LMS
(.AR(AR),
.DI(DI),
.IPCORE_CLK(IPCORE_CLK),
.Q(Q),
.S(S),
.cop_dut_enable(cop_dut_enable),
.filter_sum(filter_sum),
.mul_temp_16(mul_temp_16),
.\write_reg_d_k_reg[11] (\write_reg_d_k_reg[11] ),
.\write_reg_d_k_reg[3] (\write_reg_d_k_reg[3] ),
.\write_reg_d_k_reg[3]_0 (\write_reg_d_k_reg[3]_0 ),
.\write_reg_d_k_reg[7] (\write_reg_d_k_reg[7] ),
.\write_reg_x_k_reg[15] (\write_reg_x_k_reg[15] ));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module t_mem;
// Inputs
reg [31:0] writedata, aluresultin, pcbranch1;
reg [4:0] writereg1;
reg branch, memwrite, memtoreg1, regwrite1, zerowire, clk;
// Outputs
wire [31:0] readdata, aluresultout, pcbranch2;
wire [4:0] writereg2;
wire regwrite2, memtoreg2, pcsrc;
// Instantiate the Unit Under Test
memoryaccess uut (
.ReadDataM( readdata ), .ALUResultOut( aluresultout ), .PCBranchM2( pcbranch2 ),
.WriteRegM2( writereg2 ),
.RegWriteM2( regwrite2 ), .MemToRegM2( memtoreg2 ), .PCSrcM( pcsrc ),
.WriteDataM( writedata ), .ALUResultIn( aluresultin ), .PCBranchM1( pcbranch1 ),
.WriteRegM1( writereg1 ),
.BranchM( branch ), .MemWriteM( memwrite ), .MemToRegM1( memtoreg1 ),
.RegWriteM1( regwrite1 ),
.ZerowireM( zerowire ), .clk( clk )
);
// Intialise the clock
initial begin
clk = 0;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
// Initialise inputs
writedata = 0; aluresultin = 0; pcbranch1 = 0;
writereg1 = 0;
branch = 0; memwrite = 0; memtoreg1 = 0; regwrite1 = 0; zerowire = 0; clk = 0;
// Wait 100 ns for global resets
#100;
// Test zerowire + branch and PCBranch
#10 zerowire = 0; branch = 0; pcbranch1 = 32'h00000008; //expected output pcsrc = 0; pcbranch2 = 32'h00000008;
#20 zerowire = 0; branch = 1; pcbranch1 = 32'h00000008; //expected output pcsrc = 0; pcbranch2 = 32'h00000008;
#20 zerowire = 1; branch = 0; pcbranch1 = 32'h00000008; //expected output pcsrc = 0; pcbranch2 = 32'h00000008;
#20 zerowire = 1; branch = 1; pcbranch1 = 32'h00000008; //expected output pcsrc = 1; pcbranch2 = 32'h00000008;
// Test ALUResultIn for when MemWrite = 0 and MemWrite = 1;
#20 aluresultin = 32'h00000001; memwrite = 1; writedata = 32'hFFFFFFFF;
// expected output aluresultout = 32'h00000001; dmem stores value FFFFFFFF into address 32'h00000001
#20 aluresultin = 32'h00000001; memwrite = 0; writedata = 32'hAAAAAAAA; // expected output aluresultout = 32'h00000001; readdata = 32'hFFFFFFFF;
// Test read function of dmem
// Test follow-through signals
#20 writereg1 = 5'b01000; memtoreg1 = 1; regwrite1 = 1; // expected output writereg2 = 5'b01000; memtoreg2 = 1; regwrite2 = 1;
#20 writereg1 = 5'b01001; memtoreg1 = 0; regwrite1 = 0; // expected output writereg2 = 5'b01001; memtoreg2 = 0; regwrite2 = 0;
end
endmodule |
module qdiv #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] i_dividend,
input [N-1:0] i_divisor,
input i_start,
input i_clk,
output [N-1:0] o_quotient_out,
output o_complete,
output o_overflow
);
reg [2*N+Q-3:0] reg_working_quotient; // Our working copy of the quotient
reg [N-1:0] reg_quotient; // Final quotient
reg [N-2+Q:0] reg_working_dividend; // Working copy of the dividend
reg [2*N+Q-3:0] reg_working_divisor; // Working copy of the divisor
reg [N-1:0] reg_count; // This is obviously a lot bigger than it needs to be, as we only need
// count to N-1+Q but, computing that number of bits requires a
// logarithm (base 2), and I don't know how to do that in a
// way that will work for everyone
reg reg_done; // Computation completed flag
reg reg_sign; // The quotient's sign bit
reg reg_overflow; // Overflow flag
initial reg_done = 1'b1; // Initial state is to not be doing anything
initial reg_overflow = 1'b0; // And there should be no woverflow present
initial reg_sign = 1'b0; // And the sign should be positive
initial reg_working_quotient = 0;
initial reg_quotient = 0;
initial reg_working_dividend = 0;
initial reg_working_divisor = 0;
initial reg_count = 0;
assign o_quotient_out[N-2:0] = reg_quotient[N-2:0]; // The division results
assign o_quotient_out[N-1] = reg_sign; // The sign of the quotient
assign o_complete = reg_done;
assign o_overflow = reg_overflow;
always @( posedge i_clk ) begin
if( reg_done && i_start ) begin // This is our startup condition
// Need to check for a divide by zero right here, I think....
reg_done <= 1'b0; // We're not done
reg_count <= N+Q-1; // Set the count
reg_working_quotient <= 0; // Clear out the quotient register
reg_working_dividend <= 0; // Clear out the dividend register
reg_working_divisor <= 0; // Clear out the divisor register
reg_overflow <= 1'b0; // Clear the overflow register
reg_working_dividend[N+Q-2:Q] <= i_dividend[N-2:0]; // Left-align the dividend in its working register
reg_working_divisor[2*N+Q-3:N+Q-1] <= i_divisor[N-2:0]; // Left-align the divisor into its working register
reg_sign <= i_dividend[N-1] ^ i_divisor[N-1]; // Set the sign bit
end
else if(!reg_done) begin
reg_working_divisor <= reg_working_divisor >> 1; // Right shift the divisor (that is, divide it by two - aka reduce the divisor)
reg_count <= reg_count - 1; // Decrement the count
// If the dividend is greater than the divisor
if(reg_working_dividend >= reg_working_divisor) begin
reg_working_quotient[reg_count] <= 1'b1; // Set the quotient bit
reg_working_dividend <= reg_working_dividend - reg_working_divisor; // and subtract the divisor from the dividend
end
//stop condition
if(reg_count == 0) begin
reg_done <= 1'b1; // If we're done, it's time to tell the calling process
reg_quotient <= reg_working_quotient; // Move in our working copy to the outside world
if (reg_working_quotient[2*N+Q-3:N]>0)
reg_overflow <= 1'b1;
end
else
reg_count <= reg_count - 1;
end
end
endmodule |
module SimpleRam
#(parameter BUS_WIDTH = 8, parameter SIZE = 512, parameter ADDRESS_WIDTH = 32)
(
input wire clk,
input wire reset,
input wire [ADDRESS_WIDTH-1:0] addrA,
input wire [BUS_WIDTH-1:0] dataIn,
input wire writeEnable,
input wire [ADDRESS_WIDTH-1:0] addrB,
output reg [BUS_WIDTH-1:0] outA,
output reg [BUS_WIDTH-1:0] outB,
output reg busyA,
output reg busyB
);
reg [BUS_WIDTH-1:0] memory[0:SIZE-1];
reg [BUS_WIDTH-1:0] lastAddrA = 0;
reg [BUS_WIDTH-1:0] lastAddrB = 0;
// Counter variable for initialization
integer i;
// For debugging
always @(posedge reset) $writememh("ram.hex", memory);
always @(clk)
begin
if(writeEnable)
begin
outA <= dataIn;
memory[addrA] <= dataIn;
end
if(addrA != lastAddrA)
busyA <= 1;
if(addrB != lastAddrB)
busyA <= 1;
if(~writeEnable)
begin
busyA <= 0;
outA <= memory[addrA];
busyB <= 0;
outB <= memory[addrB];
end
lastAddrA = addrA;
lastAddrB = addrB;
if(reset)
begin
busyA <= 1;
busyB <= 1;
outA <= 0;
outB <= 0;
for(i = 0; i < SIZE; i=i+1)
memory[i] <= 0;
end
end
endmodule |
module DE0_NANO_SOC_Default();
wire [31:0] cpuDataOut;
wire [31:0] cpuDataIn;
wire [31:0] cpuDataInAddr;
wire [31:0] cpuDataOutAddr;
wire cpuWrEn;
wire [31:0] instrBus;
wire [31:0] pcBus;
wire [31:0] CPU_StatusBus;
wire forceRoot;
wire flushing;
wire [31:0] instrCacheAddr;
wire [31:0] instrCacheData;
wire [31:0] dataOutFlowCtrl;
wire [31:0] dataOutUART;
wire [31:0] dataOutDataCache;
wire [31:0] IRQBus;
wire [31:0] uartStatus;
reg clk;
reg rst;
wire TxD;
assign IRQBus = 0;
assign IRQBus[0] = uartStatus[2]; // RX buffer ready
assign IRQBus[1] = uartStatus[1]; // TX complete
wolfcore CPU(
.dataOutput(cpuDataOut),
.dataInput(cpuDataIn),
.dataInAddr(cpuDataInAddr),
.dataOutAddr(cpuDataOutAddr),
.dataWrEn(cpuWrEn),
.instrInput(instrBus),
.pc(pcBus),
.CPU_Status(CPU_StatusBus),
.rst(rst),
.clk(clk),
.forceRoot(forceRoot),
.flushing(flushing)
);
flowController instrCtrl(
.rst(rst),
.clk(clk),
.pc(pcBus),
.CPU_Status(CPU_StatusBus),
.flushing(flushing),
.instrOut(instrBus),
.forceRoot(forceRoot),
.memAddr(instrCacheAddr),
.instrIn(instrCacheData),
.IRQ(IRQBus),
.inputAddr(cpuDataOutAddr),
.outputAddr(cpuDataInAddr),
.inputData(cpuDataOut),
.outputData(dataOutFlowCtrl),
.wrEn(cpuWrEn)
);
progMem instrCache(
.instrOutput(instrCacheData),
.instrAddress(instrCacheAddr),
.clk(clk)
);
dataController dataCache(
.dataIn(cpuDataOut),
.dataInAddr(cpuDataOutAddr),
.dataOut(dataOutDataCache),
.dataOutAddr(cpuDataInAddr),
.wren(cpuWrEn),
.clk(clk)
);
UART testUART(
.clk(clk),
.rst(rst),
.RxD(1'b0),
.TxD(TxD),
.inputData(cpuDataOut),
.inputAddr(cpuDataOutAddr),
.outputData(dataOutUART),
.outputAddr(cpuDataInAddr),
.wren(cpuWrEn),
.uartStatus(uartStatus)
);
outputDataMux dataMux(
.outputAddr(cpuDataInAddr),
.outputDataUART(dataOutUART),
.outputDataFlowCtrl(dataOutFlowCtrl),
.outputDataDataCache(dataOutDataCache),
.outputData(cpuDataIn)
);
initial begin
clk = 1'b0;
forever begin
#1
clk = ~clk;
end
end
initial begin
rst = 1'b1;
#10
rst = 1'b0;
end
endmodule |
module sky130_fd_sc_hd__a21oi (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sp_co_ord_delay (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
phi_0_0_0_V_read,
phi_0_0_1_V_read,
phi_0_1_0_V_read,
phi_0_1_1_V_read,
phi_0_2_0_V_read,
phi_0_2_1_V_read,
phi_0_3_0_V_read,
phi_0_3_1_V_read,
phi_0_4_0_V_read,
phi_0_4_1_V_read,
phi_0_5_0_V_read,
phi_0_5_1_V_read,
phi_0_6_0_V_read,
phi_0_6_1_V_read,
phi_0_7_0_V_read,
phi_0_7_1_V_read,
phi_0_8_0_V_read,
phi_0_8_1_V_read,
phi_1_0_0_V_read,
phi_1_0_1_V_read,
phi_1_1_0_V_read,
phi_1_1_1_V_read,
phi_1_2_0_V_read,
phi_1_2_1_V_read,
phi_1_3_0_V_read,
phi_1_3_1_V_read,
phi_1_4_0_V_read,
phi_1_4_1_V_read,
phi_1_5_0_V_read,
phi_1_5_1_V_read,
phi_1_6_0_V_read,
phi_1_6_1_V_read,
phi_1_7_0_V_read,
phi_1_7_1_V_read,
phi_1_8_0_V_read,
phi_1_8_1_V_read,
phi_2_0_0_V_read,
phi_2_0_1_V_read,
phi_2_1_0_V_read,
phi_2_1_1_V_read,
phi_2_2_0_V_read,
phi_2_2_1_V_read,
phi_2_3_0_V_read,
phi_2_3_1_V_read,
phi_2_4_0_V_read,
phi_2_4_1_V_read,
phi_2_5_0_V_read,
phi_2_5_1_V_read,
phi_2_6_0_V_read,
phi_2_6_1_V_read,
phi_2_7_0_V_read,
phi_2_7_1_V_read,
phi_2_8_0_V_read,
phi_2_8_1_V_read,
phi_3_0_0_V_read,
phi_3_0_1_V_read,
phi_3_1_0_V_read,
phi_3_1_1_V_read,
phi_3_2_0_V_read,
phi_3_2_1_V_read,
phi_3_3_0_V_read,
phi_3_3_1_V_read,
phi_3_4_0_V_read,
phi_3_4_1_V_read,
phi_3_5_0_V_read,
phi_3_5_1_V_read,
phi_3_6_0_V_read,
phi_3_6_1_V_read,
phi_3_7_0_V_read,
phi_3_7_1_V_read,
phi_3_8_0_V_read,
phi_3_8_1_V_read,
phi_4_0_0_V_read,
phi_4_0_1_V_read,
phi_4_1_0_V_read,
phi_4_1_1_V_read,
phi_4_2_0_V_read,
phi_4_2_1_V_read,
phi_4_3_0_V_read,
phi_4_3_1_V_read,
phi_4_4_0_V_read,
phi_4_4_1_V_read,
phi_4_5_0_V_read,
phi_4_5_1_V_read,
phi_4_6_0_V_read,
phi_4_6_1_V_read,
phi_4_7_0_V_read,
phi_4_7_1_V_read,
phi_4_8_0_V_read,
phi_4_8_1_V_read,
cpati_0_0_0_V_read,
cpati_0_0_1_V_read,
cpati_0_1_0_V_read,
cpati_0_1_1_V_read,
cpati_0_2_0_V_read,
cpati_0_2_1_V_read,
cpati_0_3_0_V_read,
cpati_0_3_1_V_read,
cpati_0_4_0_V_read,
cpati_0_4_1_V_read,
cpati_0_5_0_V_read,
cpati_0_5_1_V_read,
cpati_0_6_0_V_read,
cpati_0_6_1_V_read,
cpati_0_7_0_V_read,
cpati_0_7_1_V_read,
cpati_0_8_0_V_read,
cpati_0_8_1_V_read,
cpati_1_0_0_V_read,
cpati_1_0_1_V_read,
cpati_1_1_0_V_read,
cpati_1_1_1_V_read,
cpati_1_2_0_V_read,
cpati_1_2_1_V_read,
cpati_1_3_0_V_read,
cpati_1_3_1_V_read,
cpati_1_4_0_V_read,
cpati_1_4_1_V_read,
cpati_1_5_0_V_read,
cpati_1_5_1_V_read,
cpati_1_6_0_V_read,
cpati_1_6_1_V_read,
cpati_1_7_0_V_read,
cpati_1_7_1_V_read,
cpati_1_8_0_V_read,
cpati_1_8_1_V_read,
cpati_2_0_0_V_read,
cpati_2_0_1_V_read,
cpati_2_1_0_V_read,
cpati_2_1_1_V_read,
cpati_2_2_0_V_read,
cpati_2_2_1_V_read,
cpati_2_3_0_V_read,
cpati_2_3_1_V_read,
cpati_2_4_0_V_read,
cpati_2_4_1_V_read,
cpati_2_5_0_V_read,
cpati_2_5_1_V_read,
cpati_2_6_0_V_read,
cpati_2_6_1_V_read,
cpati_2_7_0_V_read,
cpati_2_7_1_V_read,
cpati_2_8_0_V_read,
cpati_2_8_1_V_read,
cpati_3_0_0_V_read,
cpati_3_0_1_V_read,
cpati_3_1_0_V_read,
cpati_3_1_1_V_read,
cpati_3_2_0_V_read,
cpati_3_2_1_V_read,
cpati_3_3_0_V_read,
cpati_3_3_1_V_read,
cpati_3_4_0_V_read,
cpati_3_4_1_V_read,
cpati_3_5_0_V_read,
cpati_3_5_1_V_read,
cpati_3_6_0_V_read,
cpati_3_6_1_V_read,
cpati_3_7_0_V_read,
cpati_3_7_1_V_read,
cpati_3_8_0_V_read,
cpati_3_8_1_V_read,
cpati_4_0_0_V_read,
cpati_4_0_1_V_read,
cpati_4_1_0_V_read,
cpati_4_1_1_V_read,
cpati_4_2_0_V_read,
cpati_4_2_1_V_read,
cpati_4_3_0_V_read,
cpati_4_3_1_V_read,
cpati_4_4_0_V_read,
cpati_4_4_1_V_read,
cpati_4_5_0_V_read,
cpati_4_5_1_V_read,
cpati_4_6_0_V_read,
cpati_4_6_1_V_read,
cpati_4_7_0_V_read,
cpati_4_7_1_V_read,
cpati_4_8_0_V_read,
cpati_4_8_1_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3,
ap_return_4,
ap_return_5,
ap_return_6,
ap_return_7,
ap_return_8,
ap_return_9,
ap_return_10,
ap_return_11,
ap_return_12,
ap_return_13,
ap_return_14,
ap_return_15,
ap_return_16,
ap_return_17,
ap_return_18,
ap_return_19,
ap_return_20,
ap_return_21,
ap_return_22,
ap_return_23,
ap_return_24,
ap_return_25,
ap_return_26,
ap_return_27,
ap_return_28,
ap_return_29,
ap_return_30,
ap_return_31,
ap_return_32,
ap_return_33,
ap_return_34,
ap_return_35,
ap_return_36,
ap_return_37
);
parameter ap_ST_pp0_stg0_fsm_0 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [11:0] phi_0_0_0_V_read;
input [11:0] phi_0_0_1_V_read;
input [11:0] phi_0_1_0_V_read;
input [11:0] phi_0_1_1_V_read;
input [11:0] phi_0_2_0_V_read;
input [11:0] phi_0_2_1_V_read;
input [11:0] phi_0_3_0_V_read;
input [11:0] phi_0_3_1_V_read;
input [11:0] phi_0_4_0_V_read;
input [11:0] phi_0_4_1_V_read;
input [11:0] phi_0_5_0_V_read;
input [11:0] phi_0_5_1_V_read;
input [11:0] phi_0_6_0_V_read;
input [11:0] phi_0_6_1_V_read;
input [11:0] phi_0_7_0_V_read;
input [11:0] phi_0_7_1_V_read;
input [11:0] phi_0_8_0_V_read;
input [11:0] phi_0_8_1_V_read;
input [11:0] phi_1_0_0_V_read;
input [11:0] phi_1_0_1_V_read;
input [11:0] phi_1_1_0_V_read;
input [11:0] phi_1_1_1_V_read;
input [11:0] phi_1_2_0_V_read;
input [11:0] phi_1_2_1_V_read;
input [11:0] phi_1_3_0_V_read;
input [11:0] phi_1_3_1_V_read;
input [11:0] phi_1_4_0_V_read;
input [11:0] phi_1_4_1_V_read;
input [11:0] phi_1_5_0_V_read;
input [11:0] phi_1_5_1_V_read;
input [11:0] phi_1_6_0_V_read;
input [11:0] phi_1_6_1_V_read;
input [11:0] phi_1_7_0_V_read;
input [11:0] phi_1_7_1_V_read;
input [11:0] phi_1_8_0_V_read;
input [11:0] phi_1_8_1_V_read;
input [11:0] phi_2_0_0_V_read;
input [11:0] phi_2_0_1_V_read;
input [11:0] phi_2_1_0_V_read;
input [11:0] phi_2_1_1_V_read;
input [11:0] phi_2_2_0_V_read;
input [11:0] phi_2_2_1_V_read;
input [11:0] phi_2_3_0_V_read;
input [11:0] phi_2_3_1_V_read;
input [11:0] phi_2_4_0_V_read;
input [11:0] phi_2_4_1_V_read;
input [11:0] phi_2_5_0_V_read;
input [11:0] phi_2_5_1_V_read;
input [11:0] phi_2_6_0_V_read;
input [11:0] phi_2_6_1_V_read;
input [11:0] phi_2_7_0_V_read;
input [11:0] phi_2_7_1_V_read;
input [11:0] phi_2_8_0_V_read;
input [11:0] phi_2_8_1_V_read;
input [11:0] phi_3_0_0_V_read;
input [11:0] phi_3_0_1_V_read;
input [11:0] phi_3_1_0_V_read;
input [11:0] phi_3_1_1_V_read;
input [11:0] phi_3_2_0_V_read;
input [11:0] phi_3_2_1_V_read;
input [11:0] phi_3_3_0_V_read;
input [11:0] phi_3_3_1_V_read;
input [11:0] phi_3_4_0_V_read;
input [11:0] phi_3_4_1_V_read;
input [11:0] phi_3_5_0_V_read;
input [11:0] phi_3_5_1_V_read;
input [11:0] phi_3_6_0_V_read;
input [11:0] phi_3_6_1_V_read;
input [11:0] phi_3_7_0_V_read;
input [11:0] phi_3_7_1_V_read;
input [11:0] phi_3_8_0_V_read;
input [11:0] phi_3_8_1_V_read;
input [11:0] phi_4_0_0_V_read;
input [11:0] phi_4_0_1_V_read;
input [11:0] phi_4_1_0_V_read;
input [11:0] phi_4_1_1_V_read;
input [11:0] phi_4_2_0_V_read;
input [11:0] phi_4_2_1_V_read;
input [11:0] phi_4_3_0_V_read;
input [11:0] phi_4_3_1_V_read;
input [11:0] phi_4_4_0_V_read;
input [11:0] phi_4_4_1_V_read;
input [11:0] phi_4_5_0_V_read;
input [11:0] phi_4_5_1_V_read;
input [11:0] phi_4_6_0_V_read;
input [11:0] phi_4_6_1_V_read;
input [11:0] phi_4_7_0_V_read;
input [11:0] phi_4_7_1_V_read;
input [11:0] phi_4_8_0_V_read;
input [11:0] phi_4_8_1_V_read;
input [3:0] cpati_0_0_0_V_read;
input [3:0] cpati_0_0_1_V_read;
input [3:0] cpati_0_1_0_V_read;
input [3:0] cpati_0_1_1_V_read;
input [3:0] cpati_0_2_0_V_read;
input [3:0] cpati_0_2_1_V_read;
input [3:0] cpati_0_3_0_V_read;
input [3:0] cpati_0_3_1_V_read;
input [3:0] cpati_0_4_0_V_read;
input [3:0] cpati_0_4_1_V_read;
input [3:0] cpati_0_5_0_V_read;
input [3:0] cpati_0_5_1_V_read;
input [3:0] cpati_0_6_0_V_read;
input [3:0] cpati_0_6_1_V_read;
input [3:0] cpati_0_7_0_V_read;
input [3:0] cpati_0_7_1_V_read;
input [3:0] cpati_0_8_0_V_read;
input [3:0] cpati_0_8_1_V_read;
input [3:0] cpati_1_0_0_V_read;
input [3:0] cpati_1_0_1_V_read;
input [3:0] cpati_1_1_0_V_read;
input [3:0] cpati_1_1_1_V_read;
input [3:0] cpati_1_2_0_V_read;
input [3:0] cpati_1_2_1_V_read;
input [3:0] cpati_1_3_0_V_read;
input [3:0] cpati_1_3_1_V_read;
input [3:0] cpati_1_4_0_V_read;
input [3:0] cpati_1_4_1_V_read;
input [3:0] cpati_1_5_0_V_read;
input [3:0] cpati_1_5_1_V_read;
input [3:0] cpati_1_6_0_V_read;
input [3:0] cpati_1_6_1_V_read;
input [3:0] cpati_1_7_0_V_read;
input [3:0] cpati_1_7_1_V_read;
input [3:0] cpati_1_8_0_V_read;
input [3:0] cpati_1_8_1_V_read;
input [3:0] cpati_2_0_0_V_read;
input [3:0] cpati_2_0_1_V_read;
input [3:0] cpati_2_1_0_V_read;
input [3:0] cpati_2_1_1_V_read;
input [3:0] cpati_2_2_0_V_read;
input [3:0] cpati_2_2_1_V_read;
input [3:0] cpati_2_3_0_V_read;
input [3:0] cpati_2_3_1_V_read;
input [3:0] cpati_2_4_0_V_read;
input [3:0] cpati_2_4_1_V_read;
input [3:0] cpati_2_5_0_V_read;
input [3:0] cpati_2_5_1_V_read;
input [3:0] cpati_2_6_0_V_read;
input [3:0] cpati_2_6_1_V_read;
input [3:0] cpati_2_7_0_V_read;
input [3:0] cpati_2_7_1_V_read;
input [3:0] cpati_2_8_0_V_read;
input [3:0] cpati_2_8_1_V_read;
input [3:0] cpati_3_0_0_V_read;
input [3:0] cpati_3_0_1_V_read;
input [3:0] cpati_3_1_0_V_read;
input [3:0] cpati_3_1_1_V_read;
input [3:0] cpati_3_2_0_V_read;
input [3:0] cpati_3_2_1_V_read;
input [3:0] cpati_3_3_0_V_read;
input [3:0] cpati_3_3_1_V_read;
input [3:0] cpati_3_4_0_V_read;
input [3:0] cpati_3_4_1_V_read;
input [3:0] cpati_3_5_0_V_read;
input [3:0] cpati_3_5_1_V_read;
input [3:0] cpati_3_6_0_V_read;
input [3:0] cpati_3_6_1_V_read;
input [3:0] cpati_3_7_0_V_read;
input [3:0] cpati_3_7_1_V_read;
input [3:0] cpati_3_8_0_V_read;
input [3:0] cpati_3_8_1_V_read;
input [3:0] cpati_4_0_0_V_read;
input [3:0] cpati_4_0_1_V_read;
input [3:0] cpati_4_1_0_V_read;
input [3:0] cpati_4_1_1_V_read;
input [3:0] cpati_4_2_0_V_read;
input [3:0] cpati_4_2_1_V_read;
input [3:0] cpati_4_3_0_V_read;
input [3:0] cpati_4_3_1_V_read;
input [3:0] cpati_4_4_0_V_read;
input [3:0] cpati_4_4_1_V_read;
input [3:0] cpati_4_5_0_V_read;
input [3:0] cpati_4_5_1_V_read;
input [3:0] cpati_4_6_0_V_read;
input [3:0] cpati_4_6_1_V_read;
input [3:0] cpati_4_7_0_V_read;
input [3:0] cpati_4_7_1_V_read;
input [3:0] cpati_4_8_0_V_read;
input [3:0] cpati_4_8_1_V_read;
output [11:0] ap_return_0;
output [11:0] ap_return_1;
output [11:0] ap_return_2;
output [11:0] ap_return_3;
output [11:0] ap_return_4;
output [11:0] ap_return_5;
output [11:0] ap_return_6;
output [11:0] ap_return_7;
output [11:0] ap_return_8;
output [6:0] ap_return_9;
output [6:0] ap_return_10;
output [6:0] ap_return_11;
output [6:0] ap_return_12;
output [6:0] ap_return_13;
output [6:0] ap_return_14;
output [6:0] ap_return_15;
output [6:0] ap_return_16;
output [6:0] ap_return_17;
output [6:0] ap_return_18;
output [6:0] ap_return_19;
output [6:0] ap_return_20;
output [6:0] ap_return_21;
output [6:0] ap_return_22;
output [6:0] ap_return_23;
output [6:0] ap_return_24;
output [6:0] ap_return_25;
output [6:0] ap_return_26;
output [6:0] ap_return_27;
output [6:0] ap_return_28;
output [3:0] ap_return_29;
output [3:0] ap_return_30;
output [3:0] ap_return_31;
output [3:0] ap_return_32;
output [3:0] ap_return_33;
output [3:0] ap_return_34;
output [3:0] ap_return_35;
output [3:0] ap_return_36;
output [3:0] ap_return_37;
reg ap_done;
reg ap_idle;
reg ap_ready;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
reg ap_sig_cseq_ST_pp0_stg0_fsm_0;
reg ap_sig_18;
wire ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it3;
reg grp_sp_co_ord_delay_actual_fu_2538_ap_start;
wire grp_sp_co_ord_delay_actual_fu_2538_ap_done;
wire grp_sp_co_ord_delay_actual_fu_2538_ap_idle;
wire grp_sp_co_ord_delay_actual_fu_2538_ap_ready;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_0;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_1;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_2;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_3;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_4;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_5;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_6;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_7;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_8;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_9;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_10;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_11;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_12;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_13;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_14;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_15;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_16;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_17;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_18;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_19;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_20;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_21;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_22;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_23;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_24;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_25;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_26;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_27;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_28;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_29;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_30;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_31;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_32;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_33;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_34;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_35;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_36;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_37;
reg [0:0] ap_NS_fsm;
reg ap_sig_grp_sp_co_ord_delay_actual_fu_2538_ap_start;
reg ap_sig_pprstidle_pp0;
// power-on initialization
initial begin
#0 ap_CS_fsm = 1'b1;
#0 ap_reg_ppiten_pp0_it1 = 1'b0;
#0 ap_reg_ppiten_pp0_it2 = 1'b0;
#0 ap_reg_ppiten_pp0_it3 = 1'b0;
end
sp_co_ord_delay_actual grp_sp_co_ord_delay_actual_fu_2538(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(grp_sp_co_ord_delay_actual_fu_2538_ap_start),
.ap_done(grp_sp_co_ord_delay_actual_fu_2538_ap_done),
.ap_idle(grp_sp_co_ord_delay_actual_fu_2538_ap_idle),
.ap_ready(grp_sp_co_ord_delay_actual_fu_2538_ap_ready),
.phi_0_0_0_V_read(phi_0_0_0_V_read),
.phi_0_0_1_V_read(phi_0_0_1_V_read),
.phi_0_1_0_V_read(phi_0_1_0_V_read),
.phi_0_1_1_V_read(phi_0_1_1_V_read),
.phi_0_2_0_V_read(phi_0_2_0_V_read),
.phi_0_2_1_V_read(phi_0_2_1_V_read),
.phi_0_3_0_V_read(phi_0_3_0_V_read),
.phi_0_3_1_V_read(phi_0_3_1_V_read),
.phi_0_4_0_V_read(phi_0_4_0_V_read),
.phi_0_4_1_V_read(phi_0_4_1_V_read),
.phi_0_5_0_V_read(phi_0_5_0_V_read),
.phi_0_5_1_V_read(phi_0_5_1_V_read),
.phi_0_6_0_V_read(phi_0_6_0_V_read),
.phi_0_6_1_V_read(phi_0_6_1_V_read),
.phi_0_7_0_V_read(phi_0_7_0_V_read),
.phi_0_7_1_V_read(phi_0_7_1_V_read),
.phi_0_8_0_V_read(phi_0_8_0_V_read),
.phi_0_8_1_V_read(phi_0_8_1_V_read),
.phi_1_0_0_V_read(phi_1_0_0_V_read),
.phi_1_0_1_V_read(phi_1_0_1_V_read),
.phi_1_1_0_V_read(phi_1_1_0_V_read),
.phi_1_1_1_V_read(phi_1_1_1_V_read),
.phi_1_2_0_V_read(phi_1_2_0_V_read),
.phi_1_2_1_V_read(phi_1_2_1_V_read),
.phi_1_3_0_V_read(phi_1_3_0_V_read),
.phi_1_3_1_V_read(phi_1_3_1_V_read),
.phi_1_4_0_V_read(phi_1_4_0_V_read),
.phi_1_4_1_V_read(phi_1_4_1_V_read),
.phi_1_5_0_V_read(phi_1_5_0_V_read),
.phi_1_5_1_V_read(phi_1_5_1_V_read),
.phi_1_6_0_V_read(phi_1_6_0_V_read),
.phi_1_6_1_V_read(phi_1_6_1_V_read),
.phi_1_7_0_V_read(phi_1_7_0_V_read),
.phi_1_7_1_V_read(phi_1_7_1_V_read),
.phi_1_8_0_V_read(phi_1_8_0_V_read),
.phi_1_8_1_V_read(phi_1_8_1_V_read),
.phi_2_0_0_V_read(phi_2_0_0_V_read),
.phi_2_0_1_V_read(phi_2_0_1_V_read),
.phi_2_1_0_V_read(phi_2_1_0_V_read),
.phi_2_1_1_V_read(phi_2_1_1_V_read),
.phi_2_2_0_V_read(phi_2_2_0_V_read),
.phi_2_2_1_V_read(phi_2_2_1_V_read),
.phi_2_3_0_V_read(phi_2_3_0_V_read),
.phi_2_3_1_V_read(phi_2_3_1_V_read),
.phi_2_4_0_V_read(phi_2_4_0_V_read),
.phi_2_4_1_V_read(phi_2_4_1_V_read),
.phi_2_5_0_V_read(phi_2_5_0_V_read),
.phi_2_5_1_V_read(phi_2_5_1_V_read),
.phi_2_6_0_V_read(phi_2_6_0_V_read),
.phi_2_6_1_V_read(phi_2_6_1_V_read),
.phi_2_7_0_V_read(phi_2_7_0_V_read),
.phi_2_7_1_V_read(phi_2_7_1_V_read),
.phi_2_8_0_V_read(phi_2_8_0_V_read),
.phi_2_8_1_V_read(phi_2_8_1_V_read),
.phi_3_0_0_V_read(phi_3_0_0_V_read),
.phi_3_0_1_V_read(phi_3_0_1_V_read),
.phi_3_1_0_V_read(phi_3_1_0_V_read),
.phi_3_1_1_V_read(phi_3_1_1_V_read),
.phi_3_2_0_V_read(phi_3_2_0_V_read),
.phi_3_2_1_V_read(phi_3_2_1_V_read),
.phi_3_3_0_V_read(phi_3_3_0_V_read),
.phi_3_3_1_V_read(phi_3_3_1_V_read),
.phi_3_4_0_V_read(phi_3_4_0_V_read),
.phi_3_4_1_V_read(phi_3_4_1_V_read),
.phi_3_5_0_V_read(phi_3_5_0_V_read),
.phi_3_5_1_V_read(phi_3_5_1_V_read),
.phi_3_6_0_V_read(phi_3_6_0_V_read),
.phi_3_6_1_V_read(phi_3_6_1_V_read),
.phi_3_7_0_V_read(phi_3_7_0_V_read),
.phi_3_7_1_V_read(phi_3_7_1_V_read),
.phi_3_8_0_V_read(phi_3_8_0_V_read),
.phi_3_8_1_V_read(phi_3_8_1_V_read),
.phi_4_0_0_V_read(phi_4_0_0_V_read),
.phi_4_0_1_V_read(phi_4_0_1_V_read),
.phi_4_1_0_V_read(phi_4_1_0_V_read),
.phi_4_1_1_V_read(phi_4_1_1_V_read),
.phi_4_2_0_V_read(phi_4_2_0_V_read),
.phi_4_2_1_V_read(phi_4_2_1_V_read),
.phi_4_3_0_V_read(phi_4_3_0_V_read),
.phi_4_3_1_V_read(phi_4_3_1_V_read),
.phi_4_4_0_V_read(phi_4_4_0_V_read),
.phi_4_4_1_V_read(phi_4_4_1_V_read),
.phi_4_5_0_V_read(phi_4_5_0_V_read),
.phi_4_5_1_V_read(phi_4_5_1_V_read),
.phi_4_6_0_V_read(phi_4_6_0_V_read),
.phi_4_6_1_V_read(phi_4_6_1_V_read),
.phi_4_7_0_V_read(phi_4_7_0_V_read),
.phi_4_7_1_V_read(phi_4_7_1_V_read),
.phi_4_8_0_V_read(phi_4_8_0_V_read),
.phi_4_8_1_V_read(phi_4_8_1_V_read),
.cpati_0_0_0_V_read(cpati_0_0_0_V_read),
.cpati_0_0_1_V_read(cpati_0_0_1_V_read),
.cpati_0_1_0_V_read(cpati_0_1_0_V_read),
.cpati_0_1_1_V_read(cpati_0_1_1_V_read),
.cpati_0_2_0_V_read(cpati_0_2_0_V_read),
.cpati_0_2_1_V_read(cpati_0_2_1_V_read),
.cpati_0_3_0_V_read(cpati_0_3_0_V_read),
.cpati_0_3_1_V_read(cpati_0_3_1_V_read),
.cpati_0_4_0_V_read(cpati_0_4_0_V_read),
.cpati_0_4_1_V_read(cpati_0_4_1_V_read),
.cpati_0_5_0_V_read(cpati_0_5_0_V_read),
.cpati_0_5_1_V_read(cpati_0_5_1_V_read),
.cpati_0_6_0_V_read(cpati_0_6_0_V_read),
.cpati_0_6_1_V_read(cpati_0_6_1_V_read),
.cpati_0_7_0_V_read(cpati_0_7_0_V_read),
.cpati_0_7_1_V_read(cpati_0_7_1_V_read),
.cpati_0_8_0_V_read(cpati_0_8_0_V_read),
.cpati_0_8_1_V_read(cpati_0_8_1_V_read),
.cpati_1_0_0_V_read(cpati_1_0_0_V_read),
.cpati_1_0_1_V_read(cpati_1_0_1_V_read),
.cpati_1_1_0_V_read(cpati_1_1_0_V_read),
.cpati_1_1_1_V_read(cpati_1_1_1_V_read),
.cpati_1_2_0_V_read(cpati_1_2_0_V_read),
.cpati_1_2_1_V_read(cpati_1_2_1_V_read),
.cpati_1_3_0_V_read(cpati_1_3_0_V_read),
.cpati_1_3_1_V_read(cpati_1_3_1_V_read),
.cpati_1_4_0_V_read(cpati_1_4_0_V_read),
.cpati_1_4_1_V_read(cpati_1_4_1_V_read),
.cpati_1_5_0_V_read(cpati_1_5_0_V_read),
.cpati_1_5_1_V_read(cpati_1_5_1_V_read),
.cpati_1_6_0_V_read(cpati_1_6_0_V_read),
.cpati_1_6_1_V_read(cpati_1_6_1_V_read),
.cpati_1_7_0_V_read(cpati_1_7_0_V_read),
.cpati_1_7_1_V_read(cpati_1_7_1_V_read),
.cpati_1_8_0_V_read(cpati_1_8_0_V_read),
.cpati_1_8_1_V_read(cpati_1_8_1_V_read),
.cpati_2_0_0_V_read(cpati_2_0_0_V_read),
.cpati_2_0_1_V_read(cpati_2_0_1_V_read),
.cpati_2_1_0_V_read(cpati_2_1_0_V_read),
.cpati_2_1_1_V_read(cpati_2_1_1_V_read),
.cpati_2_2_0_V_read(cpati_2_2_0_V_read),
.cpati_2_2_1_V_read(cpati_2_2_1_V_read),
.cpati_2_3_0_V_read(cpati_2_3_0_V_read),
.cpati_2_3_1_V_read(cpati_2_3_1_V_read),
.cpati_2_4_0_V_read(cpati_2_4_0_V_read),
.cpati_2_4_1_V_read(cpati_2_4_1_V_read),
.cpati_2_5_0_V_read(cpati_2_5_0_V_read),
.cpati_2_5_1_V_read(cpati_2_5_1_V_read),
.cpati_2_6_0_V_read(cpati_2_6_0_V_read),
.cpati_2_6_1_V_read(cpati_2_6_1_V_read),
.cpati_2_7_0_V_read(cpati_2_7_0_V_read),
.cpati_2_7_1_V_read(cpati_2_7_1_V_read),
.cpati_2_8_0_V_read(cpati_2_8_0_V_read),
.cpati_2_8_1_V_read(cpati_2_8_1_V_read),
.cpati_3_0_0_V_read(cpati_3_0_0_V_read),
.cpati_3_0_1_V_read(cpati_3_0_1_V_read),
.cpati_3_1_0_V_read(cpati_3_1_0_V_read),
.cpati_3_1_1_V_read(cpati_3_1_1_V_read),
.cpati_3_2_0_V_read(cpati_3_2_0_V_read),
.cpati_3_2_1_V_read(cpati_3_2_1_V_read),
.cpati_3_3_0_V_read(cpati_3_3_0_V_read),
.cpati_3_3_1_V_read(cpati_3_3_1_V_read),
.cpati_3_4_0_V_read(cpati_3_4_0_V_read),
.cpati_3_4_1_V_read(cpati_3_4_1_V_read),
.cpati_3_5_0_V_read(cpati_3_5_0_V_read),
.cpati_3_5_1_V_read(cpati_3_5_1_V_read),
.cpati_3_6_0_V_read(cpati_3_6_0_V_read),
.cpati_3_6_1_V_read(cpati_3_6_1_V_read),
.cpati_3_7_0_V_read(cpati_3_7_0_V_read),
.cpati_3_7_1_V_read(cpati_3_7_1_V_read),
.cpati_3_8_0_V_read(cpati_3_8_0_V_read),
.cpati_3_8_1_V_read(cpati_3_8_1_V_read),
.cpati_4_0_0_V_read(cpati_4_0_0_V_read),
.cpati_4_0_1_V_read(cpati_4_0_1_V_read),
.cpati_4_1_0_V_read(cpati_4_1_0_V_read),
.cpati_4_1_1_V_read(cpati_4_1_1_V_read),
.cpati_4_2_0_V_read(cpati_4_2_0_V_read),
.cpati_4_2_1_V_read(cpati_4_2_1_V_read),
.cpati_4_3_0_V_read(cpati_4_3_0_V_read),
.cpati_4_3_1_V_read(cpati_4_3_1_V_read),
.cpati_4_4_0_V_read(cpati_4_4_0_V_read),
.cpati_4_4_1_V_read(cpati_4_4_1_V_read),
.cpati_4_5_0_V_read(cpati_4_5_0_V_read),
.cpati_4_5_1_V_read(cpati_4_5_1_V_read),
.cpati_4_6_0_V_read(cpati_4_6_0_V_read),
.cpati_4_6_1_V_read(cpati_4_6_1_V_read),
.cpati_4_7_0_V_read(cpati_4_7_0_V_read),
.cpati_4_7_1_V_read(cpati_4_7_1_V_read),
.cpati_4_8_0_V_read(cpati_4_8_0_V_read),
.cpati_4_8_1_V_read(cpati_4_8_1_V_read),
.ap_return_0(grp_sp_co_ord_delay_actual_fu_2538_ap_return_0),
.ap_return_1(grp_sp_co_ord_delay_actual_fu_2538_ap_return_1),
.ap_return_2(grp_sp_co_ord_delay_actual_fu_2538_ap_return_2),
.ap_return_3(grp_sp_co_ord_delay_actual_fu_2538_ap_return_3),
.ap_return_4(grp_sp_co_ord_delay_actual_fu_2538_ap_return_4),
.ap_return_5(grp_sp_co_ord_delay_actual_fu_2538_ap_return_5),
.ap_return_6(grp_sp_co_ord_delay_actual_fu_2538_ap_return_6),
.ap_return_7(grp_sp_co_ord_delay_actual_fu_2538_ap_return_7),
.ap_return_8(grp_sp_co_ord_delay_actual_fu_2538_ap_return_8),
.ap_return_9(grp_sp_co_ord_delay_actual_fu_2538_ap_return_9),
.ap_return_10(grp_sp_co_ord_delay_actual_fu_2538_ap_return_10),
.ap_return_11(grp_sp_co_ord_delay_actual_fu_2538_ap_return_11),
.ap_return_12(grp_sp_co_ord_delay_actual_fu_2538_ap_return_12),
.ap_return_13(grp_sp_co_ord_delay_actual_fu_2538_ap_return_13),
.ap_return_14(grp_sp_co_ord_delay_actual_fu_2538_ap_return_14),
.ap_return_15(grp_sp_co_ord_delay_actual_fu_2538_ap_return_15),
.ap_return_16(grp_sp_co_ord_delay_actual_fu_2538_ap_return_16),
.ap_return_17(grp_sp_co_ord_delay_actual_fu_2538_ap_return_17),
.ap_return_18(grp_sp_co_ord_delay_actual_fu_2538_ap_return_18),
.ap_return_19(grp_sp_co_ord_delay_actual_fu_2538_ap_return_19),
.ap_return_20(grp_sp_co_ord_delay_actual_fu_2538_ap_return_20),
.ap_return_21(grp_sp_co_ord_delay_actual_fu_2538_ap_return_21),
.ap_return_22(grp_sp_co_ord_delay_actual_fu_2538_ap_return_22),
.ap_return_23(grp_sp_co_ord_delay_actual_fu_2538_ap_return_23),
.ap_return_24(grp_sp_co_ord_delay_actual_fu_2538_ap_return_24),
.ap_return_25(grp_sp_co_ord_delay_actual_fu_2538_ap_return_25),
.ap_return_26(grp_sp_co_ord_delay_actual_fu_2538_ap_return_26),
.ap_return_27(grp_sp_co_ord_delay_actual_fu_2538_ap_return_27),
.ap_return_28(grp_sp_co_ord_delay_actual_fu_2538_ap_return_28),
.ap_return_29(grp_sp_co_ord_delay_actual_fu_2538_ap_return_29),
.ap_return_30(grp_sp_co_ord_delay_actual_fu_2538_ap_return_30),
.ap_return_31(grp_sp_co_ord_delay_actual_fu_2538_ap_return_31),
.ap_return_32(grp_sp_co_ord_delay_actual_fu_2538_ap_return_32),
.ap_return_33(grp_sp_co_ord_delay_actual_fu_2538_ap_return_33),
.ap_return_34(grp_sp_co_ord_delay_actual_fu_2538_ap_return_34),
.ap_return_35(grp_sp_co_ord_delay_actual_fu_2538_ap_return_35),
.ap_return_36(grp_sp_co_ord_delay_actual_fu_2538_ap_return_36),
.ap_return_37(grp_sp_co_ord_delay_actual_fu_2538_ap_return_37)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= 1'b0;
end else begin
if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_start;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= 1'b0;
end else begin
if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= 1'b0;
end else begin
if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
end
always @ (*) begin
if ((((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0)) | ((1'b1 == ap_reg_ppiten_pp0_it3) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b0 == ap_reg_ppiten_pp0_it0) & (1'b0 == ap_reg_ppiten_pp0_it1) & (1'b0 == ap_reg_ppiten_pp0_it2) & (1'b0 == ap_reg_ppiten_pp0_it3))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (ap_sig_18) begin
ap_sig_cseq_ST_pp0_stg0_fsm_0 = 1'b1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~(ap_start == 1'b0))) begin
ap_sig_grp_sp_co_ord_delay_actual_fu_2538_ap_start = 1'b1;
end else begin
ap_sig_grp_sp_co_ord_delay_actual_fu_2538_ap_start = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b0 == ap_reg_ppiten_pp0_it0) & (1'b0 == ap_reg_ppiten_pp0_it1) & (1'b0 == ap_reg_ppiten_pp0_it2))) begin
ap_sig_pprstidle_pp0 = 1'b1;
end else begin
ap_sig_pprstidle_pp0 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_sig_grp_sp_co_ord_delay_actual_fu_2538_ap_start)) begin
grp_sp_co_ord_delay_actual_fu_2538_ap_start = ap_sig_grp_sp_co_ord_delay_actual_fu_2538_ap_start;
end else begin
grp_sp_co_ord_delay_actual_fu_2538_ap_start = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_pp0_stg0_fsm_0 : begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_reg_ppiten_pp0_it0 = ap_start;
assign ap_return_0 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_0;
assign ap_return_1 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_1;
assign ap_return_10 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_10;
assign ap_return_11 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_11;
assign ap_return_12 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_12;
assign ap_return_13 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_13;
assign ap_return_14 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_14;
assign ap_return_15 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_15;
assign ap_return_16 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_16;
assign ap_return_17 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_17;
assign ap_return_18 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_18;
assign ap_return_19 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_19;
assign ap_return_2 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_2;
assign ap_return_20 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_20;
assign ap_return_21 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_21;
assign ap_return_22 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_22;
assign ap_return_23 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_23;
assign ap_return_24 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_24;
assign ap_return_25 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_25;
assign ap_return_26 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_26;
assign ap_return_27 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_27;
assign ap_return_28 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_28;
assign ap_return_29 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_29;
assign ap_return_3 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_3;
assign ap_return_30 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_30;
assign ap_return_31 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_31;
assign ap_return_32 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_32;
assign ap_return_33 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_33;
assign ap_return_34 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_34;
assign ap_return_35 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_35;
assign ap_return_36 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_36;
assign ap_return_37 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_37;
assign ap_return_4 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_4;
assign ap_return_5 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_5;
assign ap_return_6 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_6;
assign ap_return_7 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_7;
assign ap_return_8 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_8;
assign ap_return_9 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_9;
always @ (*) begin
ap_sig_18 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1);
end
endmodule |
module mcdSingleDramPCIe
#(parameter DRAM_WIDTH = 512,
parameter FLASH_WIDTH = 64,
// parameter DRAM_CMD_WIDTH = 24,
parameter DRAM_CMD_WIDTH = 40,
parameter FLASH_CMD_WIDTH = 48)
(
input clk,
input aresetn,
// Memcached Pipeline Input and Output Streams
output AXI_M_Stream_TVALID,
input AXI_M_Stream_TREADY,
output[63:0] AXI_M_Stream_TDATA,
output[7:0] AXI_M_Stream_TKEEP,
output[111:0] AXI_M_Stream_TUSER,
output AXI_M_Stream_TLAST,
input AXI_S_Stream_TVALID,
output AXI_S_Stream_TREADY,
input[63:0] AXI_S_Stream_TDATA,
input[7:0] AXI_S_Stream_TKEEP,
input[111:0] AXI_S_Stream_TUSER,
input AXI_S_Stream_TLAST,
//stats signals
input [31:0] stats0,
input [31:0] stats1,
//pcie interface
input [31: 0] pcie_axi_AWADDR,
input pcie_axi_AWVALID,
output pcie_axi_AWREADY,
//data write
input [31: 0] pcie_axi_WDATA,
input [3: 0] pcie_axi_WSTRB,
input pcie_axi_WVALID,
output pcie_axi_WREADY,
//write response (handhake)
output [1:0] pcie_axi_BRESP,
output pcie_axi_BVALID,
input pcie_axi_BREADY,
//address read
input [31: 0] pcie_axi_ARADDR,
input pcie_axi_ARVALID,
output pcie_axi_ARREADY,
//data read
output [31: 0] pcie_axi_RDATA,
output [1:0] pcie_axi_RRESP,
output pcie_axi_RVALID,
input pcie_axi_RREADY,
input pcieClk,
input pcie_user_lnk_up,
//signals to DRAM memory interface
//ht stream interface signals
output ht_s_axis_read_cmd_tvalid,
input ht_s_axis_read_cmd_tready,
output[71:0] ht_s_axis_read_cmd_tdata,
//read status
input ht_m_axis_read_sts_tvalid,
output ht_m_axis_read_sts_tready,
input[7:0] ht_m_axis_read_sts_tdata,
//read stream
input[511:0] ht_m_axis_read_tdata,
input[63:0] ht_m_axis_read_tkeep,
input ht_m_axis_read_tlast,
input ht_m_axis_read_tvalid,
output ht_m_axis_read_tready,
//write commands
output ht_s_axis_write_cmd_tvalid,
input ht_s_axis_write_cmd_tready,
output[71:0] ht_s_axis_write_cmd_tdata,
//write status
input ht_m_axis_write_sts_tvalid,
output ht_m_axis_write_sts_tready,
input[7:0] ht_m_axis_write_sts_tdata,
//write stream
output[511:0] ht_s_axis_write_tdata,
output[63:0] ht_s_axis_write_tkeep,
output ht_s_axis_write_tlast,
output ht_s_axis_write_tvalid,
input ht_s_axis_write_tready,
//vs stream interface signals
output vs_s_axis_read_cmd_tvalid,
input vs_s_axis_read_cmd_tready,
output[71:0] vs_s_axis_read_cmd_tdata,
//read status
input vs_m_axis_read_sts_tvalid,
output vs_m_axis_read_sts_tready,
input[7:0] vs_m_axis_read_sts_tdata,
//read stream
input[511:0] vs_m_axis_read_tdata,
input[63:0] vs_m_axis_read_tkeep,
input vs_m_axis_read_tlast,
input vs_m_axis_read_tvalid,
output vs_m_axis_read_tready,
//write commands
output vs_s_axis_write_cmd_tvalid,
input vs_s_axis_write_cmd_tready,
output[71:0] vs_s_axis_write_cmd_tdata,
//write status
input vs_m_axis_write_sts_tvalid,
output vs_m_axis_write_sts_tready,
input[7:0] vs_m_axis_write_sts_tdata,
//write stream
output[511:0] vs_s_axis_write_tdata,
output[63:0] vs_s_axis_write_tkeep,
output vs_s_axis_write_tlast,
output vs_s_axis_write_tvalid,
input vs_s_axis_write_tready
);
//DRAM model connections
wire[DRAM_WIDTH-1: 0] ht_dramRdData_data;
wire ht_dramRdData_valid;
wire ht_dramRdData_ready;
// ht_cmd_dramRdData: Push Output, 16b
wire[DRAM_CMD_WIDTH-1:0] ht_cmd_dramRdData_data;
wire ht_cmd_dramRdData_valid;
wire ht_cmd_dramRdData_ready;
// ht_dramWrData: Push Output, 512b
wire[DRAM_WIDTH-1:0] ht_dramWrData_data;
wire ht_dramWrData_valid;
wire ht_dramWrData_ready;
// ht_cmd_dramWrData: Push Output, 16b
wire[DRAM_CMD_WIDTH-1:0] ht_cmd_dramWrData_data;
wire ht_cmd_dramWrData_valid;
wire ht_cmd_dramWrData_ready;
// upd_cmd_dramRdData: Push Output, 16b
wire[DRAM_CMD_WIDTH-1:0] upd_cmd_dramRdData_data;
wire upd_cmd_dramRdData_valid;
wire upd_cmd_dramRdData_ready;
// upd_cmd_dramWrData: Push Output, 16b
wire[DRAM_CMD_WIDTH-1:0] upd_cmd_dramWrData_data;
wire upd_cmd_dramWrData_valid;
wire upd_cmd_dramWrData_ready;
// Update Flash Connection
// upd_flashRdData: Pull Input, 64b
wire[FLASH_WIDTH-1:0] flashValueStoreMemRdData_data;
wire flashValueStoreMemRdData_valid;
wire flashValueStoreMemRdData_ready;
// upd_cmd_flashRdData: Push Output, 48b
wire[FLASH_CMD_WIDTH-1:0] flashValueStoreMemRdCmd_data;
wire flashValueStoreMemRdCmd_valid;
wire flashValueStoreMemRdCmd_ready;
// upd_flashWrData: Push Output, 64b
wire[FLASH_WIDTH-1:0] flashValueStoreMemWrData_data;
wire flashValueStoreMemWrData_valid;
wire flashValueStoreMemWrData_ready;
// upd_cmd_flashWrData: Push Output, 48b
wire[FLASH_CMD_WIDTH-1:0] flashValueStoreMemWrCmd_data;
wire flashValueStoreMemWrCmd_valid;
wire flashValueStoreMemWrCmd_ready;
//dram memory path
wire dramValueStoreMemRdCmd_V_TVALID;
wire [DRAM_CMD_WIDTH-1:0] dramValueStoreMemRdCmd_V_TDATA;
wire dramValueStoreMemRdCmd_V_TREADY;
wire dramValueStoreMemRdData_V_V_TVALID;
wire [511:0] dramValueStoreMemRdData_V_V_TDATA;
wire dramValueStoreMemRdData_V_V_TREADY;
wire dramValueStoreMemWrCmd_V_TVALID;
wire [DRAM_CMD_WIDTH-1:0] dramValueStoreMemWrCmd_V_TDATA;
wire dramValueStoreMemWrCmd_V_TREADY;
wire dramValueStoreMemWrData_V_V_TVALID;
wire [511:0] dramValueStoreMemWrData_V_V_TDATA;
wire dramValueStoreMemWrData_V_V_TREADY;
//////////////////Memory Allocation Signals//////////////////////////////////////////-
wire[31:0] memcached2memAllocation_data; // Address reclamation
wire memcached2memAllocation_valid;
wire memcached2memAllocation_ready;
wire[31:0] memAllocation2memcached_dram_data; // Address assignment for DRAM
wire memAllocation2memcached_dram_valid;
wire memAllocation2memcached_dram_ready;
wire[31:0] memAllocation2memcached_flash_data; // Address assignment for SSD
wire memAllocation2memcached_flash_valid;
wire memAllocation2memcached_flash_ready;
//flush related signals
wire flushReq_V;
wire flushAck_V;
wire flushDone_V;
flashModel flash_vs(
.rdCmdIn_V_TVALID(flashValueStoreMemRdCmd_valid),
.rdCmdIn_V_TREADY(flashValueStoreMemRdCmd_ready),
.rdCmdIn_V_TDATA(flashValueStoreMemRdCmd_data),
.rdDataOut_V_V_TVALID(flashValueStoreMemRdData_valid),
.rdDataOut_V_V_TREADY(flashValueStoreMemRdData_ready),
.rdDataOut_V_V_TDATA(flashValueStoreMemRdData_data),
.wrCmdIn_V_TVALID(flashValueStoreMemWrCmd_valid),
.wrCmdIn_V_TREADY(flashValueStoreMemWrCmd_ready),
.wrCmdIn_V_TDATA(flashValueStoreMemWrCmd_data),
.wrDataIn_V_V_TVALID(flashValueStoreMemWrData_valid),
.wrDataIn_V_V_TREADY(flashValueStoreMemWrData_ready),
.wrDataIn_V_V_TDATA(flashValueStoreMemWrData_data),
.ap_rst_n(aresetn),
.ap_clk(clk)
);
readconverter_top ht_dram_read_converter(
.dmRdCmd_V_TVALID(ht_s_axis_read_cmd_tvalid),
.dmRdCmd_V_TREADY(ht_s_axis_read_cmd_tready),
.dmRdCmd_V_TDATA(ht_s_axis_read_cmd_tdata),
.dmRdData_V_TVALID(ht_m_axis_read_tvalid),
.dmRdData_V_TREADY(ht_m_axis_read_tready),
.dmRdData_V_TDATA(ht_m_axis_read_tdata),
.dmRdData_V_TKEEP(ht_m_axis_read_tkeep),
.dmRdData_V_TLAST(ht_m_axis_read_tlast),
.dmRdStatus_V_V_TVALID(ht_m_axis_read_sts_tvalid),
.dmRdStatus_V_V_TREADY(ht_m_axis_read_sts_tready),
.dmRdStatus_V_V_TDATA(ht_m_axis_read_sts_tdata),
.memRdCmd_V_TVALID(ht_cmd_dramRdData_valid),
.memRdCmd_V_TREADY(ht_cmd_dramRdData_ready),
.memRdCmd_V_TDATA(ht_cmd_dramRdData_data),
.memRdData_V_V_TVALID(ht_dramRdData_valid),
.memRdData_V_V_TREADY(ht_dramRdData_ready),
.memRdData_V_V_TDATA(ht_dramRdData_data),
.aresetn(aresetn),
.aclk(clk)
);
writeconverter_top ht_dram_write_converter(
.dmWrCmd_V_TVALID(ht_s_axis_write_cmd_tvalid),
.dmWrCmd_V_TREADY(ht_s_axis_write_cmd_tready),
.dmWrCmd_V_TDATA(ht_s_axis_write_cmd_tdata),
.dmWrData_V_TVALID(ht_s_axis_write_tvalid),
.dmWrData_V_TREADY(ht_s_axis_write_tready),
.dmWrData_V_TDATA(ht_s_axis_write_tdata),
.dmWrData_V_TKEEP(ht_s_axis_write_tkeep),
.dmWrData_V_TLAST(ht_s_axis_write_tlast),
.dmWrStatus_V_V_TVALID(ht_m_axis_write_sts_tvalid),
.dmWrStatus_V_V_TREADY(ht_m_axis_write_sts_tready),
.dmWrStatus_V_V_TDATA(ht_m_axis_write_sts_tdata),
.memWrCmd_V_TVALID(ht_cmd_dramWrData_valid),
.memWrCmd_V_TREADY(ht_cmd_dramWrData_ready),
.memWrCmd_V_TDATA(ht_cmd_dramWrData_data),
.memWrData_V_V_TVALID(ht_dramWrData_valid),
.memWrData_V_V_TREADY(ht_dramWrData_ready),
.memWrData_V_V_TDATA(ht_dramWrData_data),
.aresetn(aresetn),
.aclk(clk)
);
readconverter_top vs_dram_read_converter(
.dmRdCmd_V_TVALID(vs_s_axis_read_cmd_tvalid),
.dmRdCmd_V_TREADY(vs_s_axis_read_cmd_tready),
.dmRdCmd_V_TDATA(vs_s_axis_read_cmd_tdata),
.dmRdData_V_TVALID(vs_m_axis_read_tvalid),
.dmRdData_V_TREADY(vs_m_axis_read_tready),
.dmRdData_V_TDATA(vs_m_axis_read_tdata),
.dmRdData_V_TKEEP(vs_m_axis_read_tkeep),
.dmRdData_V_TLAST(vs_m_axis_read_tlast),
.dmRdStatus_V_V_TVALID(vs_m_axis_read_sts_tvalid),
.dmRdStatus_V_V_TREADY(vs_m_axis_read_sts_tready),
.dmRdStatus_V_V_TDATA(vs_m_axis_read_sts_tdata),
.memRdCmd_V_TVALID(dramValueStoreMemRdCmd_V_TVALID),
.memRdCmd_V_TREADY(dramValueStoreMemRdCmd_V_TREADY),
.memRdCmd_V_TDATA(dramValueStoreMemRdCmd_V_TDATA),
.memRdData_V_V_TVALID(dramValueStoreMemRdData_V_V_TVALID),
.memRdData_V_V_TREADY(dramValueStoreMemRdData_V_V_TREADY),
.memRdData_V_V_TDATA(dramValueStoreMemRdData_V_V_TDATA),
.aresetn(aresetn),
.aclk(clk)
);
writeconverter_top vs_dram_write_converter(
.dmWrCmd_V_TVALID(vs_s_axis_write_cmd_tvalid),
.dmWrCmd_V_TREADY(vs_s_axis_write_cmd_tready),
.dmWrCmd_V_TDATA(vs_s_axis_write_cmd_tdata),
.dmWrData_V_TVALID(vs_s_axis_write_tvalid),
.dmWrData_V_TREADY(vs_s_axis_write_tready),
.dmWrData_V_TDATA(vs_s_axis_write_tdata),
.dmWrData_V_TKEEP(vs_s_axis_write_tkeep),
.dmWrData_V_TLAST(vs_s_axis_write_tlast),
.dmWrStatus_V_V_TVALID(vs_m_axis_write_sts_tvalid),
.dmWrStatus_V_V_TREADY(vs_m_axis_write_sts_tready),
.dmWrStatus_V_V_TDATA(vs_m_axis_write_sts_tdata),
.memWrCmd_V_TVALID(dramValueStoreMemWrCmd_V_TVALID),
.memWrCmd_V_TREADY(dramValueStoreMemWrCmd_V_TREADY),
.memWrCmd_V_TDATA(dramValueStoreMemWrCmd_V_TDATA),
.memWrData_V_V_TVALID(dramValueStoreMemWrData_V_V_TVALID),
.memWrData_V_V_TREADY(dramValueStoreMemWrData_V_V_TREADY),
.memWrData_V_V_TDATA(dramValueStoreMemWrData_V_V_TDATA),
.aresetn(aresetn),
.aclk(clk)
);
//pciE instantiation
pcie_mem_alloc #(.REVISION(32'h12000006)) pcie_mem_alloc_inst (
.ACLK(clk),
.Axi_resetn(aresetn),
.stats0_data (stats0),
.stats1_data (stats1),
.stats2_data (32'h0),
.stats3_data (32'h0),
.pcie_axi_AWADDR(pcie_axi_AWADDR),
.pcie_axi_AWVALID(pcie_axi_AWVALID),
.pcie_axi_AWREADY(pcie_axi_AWREADY),
.pcie_axi_WDATA(pcie_axi_WDATA),
.pcie_axi_WSTRB(pcie_axi_WSTRB),
.pcie_axi_WVALID(pcie_axi_WVALID),
.pcie_axi_WREADY(pcie_axi_WREADY),
.pcie_axi_BRESP(pcie_axi_BRESP),
.pcie_axi_BVALID(pcie_axi_BVALID),
.pcie_axi_BREADY(pcie_axi_BREADY),
.pcie_axi_ARADDR(pcie_axi_ARADDR),
.pcie_axi_ARVALID(pcie_axi_ARVALID),
.pcie_axi_ARREADY(pcie_axi_ARREADY),
.pcie_axi_RDATA(pcie_axi_RDATA),
.pcie_axi_RRESP(pcie_axi_RRESP),
.pcie_axi_RVALID(pcie_axi_RVALID),
.pcie_axi_RREADY(pcie_axi_RREADY),
.pcieClk(pcieClk),
.pcie_user_lnk_up(pcie_user_lnk_up),
.memcached2memAllocation_data(memcached2memAllocation_data), // Address reclamation axis input 32
.memcached2memAllocation_valid(memcached2memAllocation_valid),
.memcached2memAllocation_ready(memcached2memAllocation_ready),
.memAllocation2memcached_dram_data(memAllocation2memcached_dram_data), // Address assignment for DRAM axis output 32
.memAllocation2memcached_dram_valid(memAllocation2memcached_dram_valid),
.memAllocation2memcached_dram_ready(memAllocation2memcached_dram_ready),
.memAllocation2memcached_flash_data(memAllocation2memcached_flash_data), // Address assignment for SSD axis output 32
.memAllocation2memcached_flash_valid(memAllocation2memcached_flash_valid),
.memAllocation2memcached_flash_ready(memAllocation2memcached_flash_ready),
.flushReq(flushReq_V),
.flushAck(flushAck_V),
.flushDone(flushDone_V)
);
//memcached Pipeline Instantiation
//memcached_bin_flash_ip myMemcachedPipeline (
memcachedPipeline myMemcachedPipeline(//use the one from synplify
.hashTableMemRdCmd_V_TVALID(ht_cmd_dramRdData_valid),
.hashTableMemRdCmd_V_TREADY(ht_cmd_dramRdData_ready),
.hashTableMemRdCmd_V_TDATA(ht_cmd_dramRdData_data),
.hashTableMemRdData_V_V_TVALID(ht_dramRdData_valid),
.hashTableMemRdData_V_V_TREADY(ht_dramRdData_ready),
.hashTableMemRdData_V_V_TDATA(ht_dramRdData_data),
.hashTableMemWrCmd_V_TVALID(ht_cmd_dramWrData_valid),
.hashTableMemWrCmd_V_TREADY(ht_cmd_dramWrData_ready),
.hashTableMemWrCmd_V_TDATA(ht_cmd_dramWrData_data),
.hashTableMemWrData_V_V_TVALID(ht_dramWrData_valid),
.hashTableMemWrData_V_V_TREADY(ht_dramWrData_ready),
.hashTableMemWrData_V_V_TDATA(ht_dramWrData_data),
.inData_TVALID(AXI_S_Stream_TVALID),
.inData_TREADY(AXI_S_Stream_TREADY),
.inData_TDATA(AXI_S_Stream_TDATA),
.inData_TUSER(AXI_S_Stream_TUSER),
.inData_TKEEP(AXI_S_Stream_TKEEP),
.inData_TLAST(AXI_S_Stream_TLAST),
.outData_TVALID(AXI_M_Stream_TVALID),
.outData_TREADY(AXI_M_Stream_TREADY),
.outData_TDATA(AXI_M_Stream_TDATA),
.outData_TUSER(AXI_M_Stream_TUSER),
.outData_TKEEP(AXI_M_Stream_TKEEP),
.outData_TLAST(AXI_M_Stream_TLAST),
.flashValueStoreMemRdCmd_V_TVALID(flashValueStoreMemRdCmd_valid),
.flashValueStoreMemRdCmd_V_TREADY(flashValueStoreMemRdCmd_ready),
.flashValueStoreMemRdCmd_V_TDATA(flashValueStoreMemRdCmd_data),
.flashValueStoreMemRdData_V_V_TVALID(flashValueStoreMemRdData_valid),
.flashValueStoreMemRdData_V_V_TREADY(flashValueStoreMemRdData_ready),
.flashValueStoreMemRdData_V_V_TDATA(flashValueStoreMemRdData_data),
.flashValueStoreMemWrCmd_V_TVALID(flashValueStoreMemWrCmd_valid),
.flashValueStoreMemWrCmd_V_TREADY(flashValueStoreMemWrCmd_ready),
.flashValueStoreMemWrCmd_V_TDATA(flashValueStoreMemWrCmd_data),
.flashValueStoreMemWrData_V_V_TVALID(flashValueStoreMemWrData_valid),
.flashValueStoreMemWrData_V_V_TREADY(flashValueStoreMemWrData_ready),
.flashValueStoreMemWrData_V_V_TDATA (flashValueStoreMemWrData_data),
.addressReturnOut_V_V_TDATA(memcached2memAllocation_data),
.addressReturnOut_V_V_TVALID(memcached2memAllocation_valid),
.addressReturnOut_V_V_TREADY(memcached2memAllocation_ready),
.addressAssignDramIn_V_V_TDATA(memAllocation2memcached_dram_data),
.addressAssignDramIn_V_V_TVALID(memAllocation2memcached_dram_valid),
.addressAssignDramIn_V_V_TREADY(memAllocation2memcached_dram_ready),
.addressAssignFlashIn_V_V_TDATA(memAllocation2memcached_flash_data),
.addressAssignFlashIn_V_V_TVALID(memAllocation2memcached_flash_valid),
.addressAssignFlashIn_V_V_TREADY(memAllocation2memcached_flash_ready),
//.aresetn(aresetn),
//.aclk(clk),
.ap_rst_n(aresetn),
.ap_clk(clk),
.dramValueStoreMemRdCmd_V_TVALID(dramValueStoreMemRdCmd_V_TVALID),
.dramValueStoreMemRdCmd_V_TDATA(dramValueStoreMemRdCmd_V_TDATA),
.dramValueStoreMemRdCmd_V_TREADY(dramValueStoreMemRdCmd_V_TREADY),
.dramValueStoreMemRdData_V_V_TVALID(dramValueStoreMemRdData_V_V_TVALID),
.dramValueStoreMemRdData_V_V_TDATA(dramValueStoreMemRdData_V_V_TDATA),
.dramValueStoreMemRdData_V_V_TREADY(dramValueStoreMemRdData_V_V_TREADY),
.dramValueStoreMemWrCmd_V_TVALID(dramValueStoreMemWrCmd_V_TVALID),
.dramValueStoreMemWrCmd_V_TDATA(dramValueStoreMemWrCmd_V_TDATA),
.dramValueStoreMemWrCmd_V_TREADY(dramValueStoreMemWrCmd_V_TREADY),
.dramValueStoreMemWrData_V_V_TVALID(dramValueStoreMemWrData_V_V_TVALID),
.dramValueStoreMemWrData_V_V_TDATA(dramValueStoreMemWrData_V_V_TDATA),
.dramValueStoreMemWrData_V_V_TREADY(dramValueStoreMemWrData_V_V_TREADY),
.flushReq_V(flushReq_V),
.flushAck_V(flushAck_V),
.flushDone_V(flushDone_V)
);
/* ------------------------------------------------------------ */
/* ChipScope Debugging */
/* ------------------------------------------------------------ */
//chipscope debugging
/*
reg [255:0] data;
reg [31:0] trig0;
wire [35:0] control0, control1;
wire vio_reset; //active high
chipscope_icon icon0
(
.CONTROL0 (control0),
.CONTROL1 (control1)
);
chipscope_ila ila0
(
.CLK (clk),
.CONTROL (control0),
.TRIG0 (trig0),
.DATA (data)
);
chipscope_vio vio0
(
.CONTROL(control1),
.ASYNC_OUT(vio_reset)
);
always @(posedge clk) begin
data[39:0] <= ht_cmd_dramRdData_data;
data[79:40] <= dramValueStoreMemRdCmd_V_TDATA;
data[80] <= ht_cmd_dramRdData_valid;
data[81] <= ht_cmd_dramRdData_ready;
data[82] <= ht_dramRdData_valid;
data[83] <= ht_dramRdData_ready;
data[84] <= ht_s_axis_read_cmd_tvalid;
data[85] <= ht_s_axis_read_cmd_tready;
data[86] <= ht_m_axis_read_tvalid;
data[87] <= ht_m_axis_read_tready;
data[88] <= ht_m_axis_read_tkeep;
data[89] <= ht_m_axis_read_tlast;
data[90] <= ht_m_axis_read_sts_tvalid;
data[91] <= ht_m_axis_read_sts_tready;
data[92] <= dramValueStoreMemRdCmd_V_TVALID;
data[93] <= dramValueStoreMemRdCmd_V_TREADY;
data[94] <= dramValueStoreMemRdData_V_V_TVALID;
data[95] <= dramValueStoreMemRdData_V_V_TREADY;
data[96] <= vs_s_axis_read_cmd_tvalid;
data[97] <= vs_s_axis_read_cmd_tready;
data[98] <= vs_m_axis_read_tvalid;
data[99] <= vs_m_axis_read_tready;
data[100] <= vs_m_axis_read_tkeep;
data[101] <= vs_m_axis_read_tlast;
data[102] <= vs_m_axis_read_sts_tvalid;
data[103] <= vs_m_axis_read_sts_tready;
data[104] <= link_initialized_clk156;
data[105] <= ncq_idle_clk156;
data[106] <= fin_read_sig_clk156;
trig0[0] <= ht_cmd_dramRdData_valid;
trig0[1] <= ht_cmd_dramRdData_ready;
trig0[2] <= ht_dramRdData_valid;
trig0[3] <= ht_dramRdData_ready;
trig0[4] <= ht_s_axis_read_cmd_tvalid;
trig0[5] <= ht_s_axis_read_cmd_tready;
trig0[6] <= ht_m_axis_read_tvalid;
trig0[7] <= ht_m_axis_read_tready;
trig0[8] <= ht_m_axis_read_tkeep;
trig0[9] <= ht_m_axis_read_tlast;
trig0[10] <= ht_m_axis_read_sts_tvalid;
trig0[11] <= ht_m_axis_read_sts_tready;
trig0[12] <= dramValueStoreMemRdCmd_V_TVALID;
trig0[13] <= dramValueStoreMemRdCmd_V_TREADY;
trig0[14] <= dramValueStoreMemRdData_V_V_TVALID;
trig0[15] <= dramValueStoreMemRdData_V_V_TREADY;
trig0[16] <= vs_s_axis_read_cmd_tvalid;
trig0[17] <= vs_s_axis_read_cmd_tready;
trig0[18] <= vs_m_axis_read_tvalid;
trig0[19] <= vs_m_axis_read_tready;
trig0[20] <= vs_m_axis_read_tkeep;
trig0[21] <= vs_m_axis_read_tlast;
trig0[22] <= vs_m_axis_read_sts_tvalid;
trig0[23] <= vs_m_axis_read_sts_tready;
end*/
endmodule |
module csa (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
// Defining integers: integer [name_of_integer] = value;
// Indicates the number of bits that have been shifted
integer sgn;
/**
* Indicates the number of iterations for adding a multiplier
* so that these additions resemble the multiplication/shift
* operation with this currently enumerated bit of the
* multiplicand
*/
integer cnt;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
/**
* Temporary reg(s) to contain the partial products during
* multiplication
*/
reg [0:127] p_pdt;
// Temporary reg variables for WW=8, for 8-bit multiplication
reg [0:15] p_pdt8a;
reg [0:15] p_pdt8a2;
reg [0:7] p_pdt8a3;
reg [0:15] p_pdt8b;
reg [0:15] p_pdt8b2;
reg [0:15] p_pdt8c;
reg [0:15] p_pdt8c2;
reg [0:15] p_pdt8d;
reg [0:15] p_pdt8d2;
reg [0:15] p_pdt8e;
reg [0:15] p_pdt8e2;
reg [0:15] p_pdt8f;
reg [0:15] p_pdt8f2;
reg [0:15] p_pdt8g;
reg [0:15] p_pdt8g2;
reg [0:15] p_pdt8h;
reg [0:15] p_pdt8h2;
// Temporary reg variables for WW=16, for 16-bit multiplication
reg [0:31] p_pdt16a;
reg [0:31] p_pdt16a2;
reg [0:31] p_pdt16a3;
reg [0:31] p_pdt16b;
reg [0:31] p_pdt16b2;
reg [0:31] p_pdt16c;
reg [0:31] p_pdt16c2;
reg [0:31] p_pdt16d;
reg [0:31] p_pdt16d2;
// ===============================================================
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
$display("reg_A",reg_A);
$display("reg_B",reg_B);
p_pdt=128'd0;
p_pdt8a=16'd0;
p_pdt8a2=16'd0;
p_pdt8a3=8'd0;
p_pdt8b=16'd0;
p_pdt8b2=16'd0;
p_pdt8c=16'd0;
p_pdt8c2=16'd0;
p_pdt8d=16'd0;
p_pdt8d2=16'd0;
p_pdt8e=16'd0;
p_pdt8e2=16'd0;
p_pdt8f=16'd0;
p_pdt8f2=16'd0;
p_pdt8g=16'd0;
p_pdt8g2=16'd0;
p_pdt8h=16'd0;
p_pdt8h2=16'd0;
p_pdt16a=32'd0;
p_pdt16a2=32'd0;
p_pdt16a3=32'd0;
p_pdt16b=32'd0;
p_pdt16b2=32'd0;
p_pdt16c=32'd0;
p_pdt16c2=32'd0;
p_pdt16d=32'd0;
p_pdt16d2=32'd0;
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
// ======================================================
// Unsigned Multiplication - odd subfields
`aluwmulou:
begin
case(ctrl_ww)
(`w8+2'd1): // aluwmulou AND `w8
begin
p_pdt8a[8:15]=reg_A[8:15];
p_pdt8a[0:7]=8'd0;
p_pdt8a2[0:15]={{8{1'b0}},reg_B[8:15]};
$display("reg_A[8:15]",reg_A[8:15]);
$display("p_pdt8a2[0:15]",p_pdt8a2[0:15]);
$display("reg_B[8:15]",reg_B[8:15]);
$display("p_pdt8a[0:15]",p_pdt8a[0:15]);
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[0:15]=p_pdt[0:15]+((p_pdt8a[sgn]==1'd1)?(p_pdt8a2<<(8'd15-sgn)):16'b0);
end
result[0:15]=p_pdt[0:15];
p_pdt8b[8:15]=reg_A[24:31];
p_pdt8b[0:7]=8'd0;
p_pdt8b2[0:15]={{8{1'b0}},reg_B[24:31]};
$display("reg_A[24:31]",reg_A[24:31]);
$display("p_pdt8b2[0:15]",p_pdt8b2[0:15]);
$display("reg_B[24:31]",reg_B[24:31]);
$display("p_pdt8b[0:15]",p_pdt8b[0:15]);
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[16:31]=p_pdt[16:31]+((p_pdt8b[sgn]==1'd1)?(p_pdt8b2<<(8'd15-sgn)):16'b0);
end
result[16:31]=p_pdt[16:31];
p_pdt8c[8:15]=reg_A[40:47];
p_pdt8c[0:7]=8'd0;
p_pdt8c2[0:15]={{8{1'b0}},reg_B[40:47]};
$display("reg_A[40:47]",reg_A[40:47]);
$display("p_pdt8c2[0:15]",p_pdt8c2[0:15]);
$display("reg_B[40:47]",reg_B[40:47]);
$display("p_pdt8c[0:15]",p_pdt8c[0:15]);
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[32:47]=p_pdt[32:47]+((p_pdt8c[sgn]==1'd1)?(p_pdt8c2<<(8'd15-sgn)):16'b0);
$display("p_pdt[32:47]",p_pdt[32:47]);
end
result[32:47]=p_pdt[32:47];
p_pdt8d[8:15]=reg_A[56:63];
p_pdt8d[0:7]=8'd0;
p_pdt8d2[0:15]={{8{1'b0}},reg_B[56:63]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[48:63]=p_pdt[48:63]+((p_pdt8d[sgn]==1'd1)?(p_pdt8d2<<(8'd15-sgn)):16'b0);
end
result[48:63]=p_pdt[48:63];
p_pdt8e[8:15]=reg_A[72:79];
p_pdt8e[0:7]=8'd0;
p_pdt8e2[0:15]={{8{1'b0}},reg_B[72:79]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[64:79]=p_pdt[64:79]+((p_pdt8e[sgn]==1'd1)?(p_pdt8e2<<(8'd15-sgn)):16'b0);
end
result[64:79]=p_pdt[64:79];
p_pdt8f[8:15]=reg_A[88:95];
p_pdt8f[0:7]=8'd0;
p_pdt8f2[0:15]={{8{1'b0}},reg_B[88:95]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[80:95]=p_pdt[80:95]+((p_pdt8f[sgn]==1'd1)?(p_pdt8f2<<(8'd15-sgn)):16'b0);
end
result[80:95]=p_pdt[80:95];
p_pdt8g[8:15]=reg_A[104:111];
p_pdt8g[0:7]=8'd0;
p_pdt8g2[0:15]={{8{1'b0}},reg_B[104:111]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[96:111]=p_pdt[96:111]+((p_pdt8g[sgn]==1'd1)?(p_pdt8g2<<(8'd15-sgn)):16'b0);
end
result[96:111]=p_pdt[96:111];
p_pdt8h[8:15]=reg_A[120:127];
p_pdt8h[0:7]=8'd0;
p_pdt8h2[0:15]={{8{1'b0}},reg_B[120:127]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[112:127]=p_pdt[112:127]+((p_pdt8h[sgn]==1'd1)?(p_pdt8h2<<(8'd15-sgn)):16'b0);
end
result[112:127]=p_pdt[112:127];
end
(`w16+2'b01): // aluwmulou AND `w16
begin
p_pdt16a[0:31]={{16{1'b0}},reg_B[16:31]};
p_pdt16a2[0:31]={{16{1'b0}},reg_A[16:31]};
p_pdt16b[0:31]={{16{1'b0}},reg_B[48:63]};
p_pdt16b2[0:31]={{16{1'b0}},reg_A[48:63]};
p_pdt16c[0:31]={{16{1'b0}},reg_B[80:95]};
p_pdt16c2[0:31]={{16{1'b0}},reg_A[80:95]};
p_pdt16d[0:31]={{16{1'b0}},reg_B[112:127]};
p_pdt16d2[0:31]={{16{1'b0}},reg_A[112:127]};
for(sgn=31; sgn>=16; sgn=sgn-1)
begin
p_pdt[0:31]=p_pdt[0:31]+((p_pdt16a[sgn]==1'd1)?(p_pdt16a2<<(16'd31-sgn)):32'd0);
p_pdt[32:63]=p_pdt[32:63]+((p_pdt16b[sgn]==1'd1)?(p_pdt16b2<<(16'd31-sgn)):32'd0);
p_pdt[64:95]=p_pdt[64:95]+((p_pdt16c[sgn]==1'd1)?(p_pdt16c2<<(16'd31-sgn)):32'd0);
p_pdt[96:127]=p_pdt[96:127]+((p_pdt16d[sgn]==1'd1)?(p_pdt16d2<<(16'd31-sgn)):32'd0);
end
result[0:31]=p_pdt[0:31];
result[32:63]=p_pdt[32:63];
result[64:95]=p_pdt[64:95];
result[96:127]=p_pdt[96:127];
end
default: // aluwmulou AND Default
begin
result=128'd0;
end
endcase
end
default:
begin
// Default arithmetic/logic operation
result=128'd0;
end
endcase
end
endmodule |
module ip_lpm
#(parameter DATA_WIDTH = 64,
parameter NUM_QUEUES = 5,
parameter LUT_DEPTH = `ROUTER_OP_LUT_ROUTE_TABLE_DEPTH,
parameter LUT_DEPTH_BITS = log2(LUT_DEPTH)
)
(// --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
// --- Interface to arp_lut
output reg [31:0] next_hop_ip,
output reg [NUM_QUEUES-1:0] lpm_output_port,
output reg lpm_vld,
output reg lpm_hit,
// --- Interface to preprocess block
input word_IP_SRC_DST,
input word_IP_DST_LO,
// --- Interface to registers
// --- Read port
input [LUT_DEPTH_BITS-1:0] lpm_rd_addr, // address in table to read
input lpm_rd_req, // request a read
output [31:0] lpm_rd_ip, // ip to match in the CAM
output [31:0] lpm_rd_mask, // subnet mask
output [NUM_QUEUES-1:0] lpm_rd_oq, // output queue
output [31:0] lpm_rd_next_hop_ip, // ip addr of next hop
output lpm_rd_ack, // pulses high
// --- Write port
input [LUT_DEPTH_BITS-1:0] lpm_wr_addr,
input lpm_wr_req,
input [NUM_QUEUES-1:0] lpm_wr_oq,
input [31:0] lpm_wr_next_hop_ip, // ip addr of next hop
input [31:0] lpm_wr_ip, // data to match in the CAM
input [31:0] lpm_wr_mask,
output lpm_wr_ack,
// --- Misc
output ready_out,
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//---------------------- Wires and regs----------------------------
wire cam_busy;
wire cam_match;
wire [LUT_DEPTH-1:0] cam_match_addr;
wire [31:0] cam_cmp_din, cam_cmp_data_mask;
wire [31:0] cam_din, cam_data_mask;
wire cam_we;
wire [LUT_DEPTH_BITS-1:0] cam_wr_addr;
wire [NUM_QUEUES-1:0] lookup_port_result;
wire [31:0] next_hop_ip_result;
reg dst_ip_vld;
reg [31:0] dst_ip;
wire [31:0] lpm_rd_mask_inverted;
//------------------------- Modules-------------------------------
assign lpm_rd_mask = ~lpm_rd_mask_inverted;
// 1 cycle read latency, 16 cycles write latency
// priority encoded for the smallest address.
/*
srl_cam_unencoded_32x32 lpm_cam
(
// Outputs
.busy (cam_busy),
.match (cam_match),
.match_addr (cam_match_addr),
// Inputs
.clk (clk),
.cmp_din (cam_cmp_din),
.din (cam_din),
.cmp_data_mask (cam_cmp_data_mask),
.data_mask (cam_data_mask),
.we (cam_we),
.wr_addr (cam_wr_addr));
*/
wire ready_reg;
ram_based_cam lpm_cam
(
.clk(clk),
.rst(reset),
.start_write(cam_we),
.waddr(cam_wr_addr),
.wdata(cam_din),
.wcare(cam_data_mask),
.lookup_data(cam_cmp_din),
.match_lines(cam_match_addr),
.ready(ready_reg),
.match_found(cam_match)
);
assign cam_busy = 1'b0;
assign ready_out = ready_reg;
unencoded_cam_lut_sm_lpm
#(.CMP_WIDTH (32), // IPv4 addr width
.DATA_WIDTH (32+NUM_QUEUES), // next hop ip and output queue
.LUT_DEPTH (LUT_DEPTH),
.DEFAULT_DATA (1)
) cam_lut_sm_lpm
(// --- Interface for lookups
.lookup_req (dst_ip_vld),
.lookup_cmp_data (dst_ip),
.lookup_cmp_dmask (32'h0),
.lookup_ack (lpm_vld_result),
.lookup_hit (lpm_hit_result),
.lookup_data ({lookup_port_result, next_hop_ip_result}),
// --- Interface to registers
// --- Read port
.rd_addr (lpm_rd_addr), // address in table to read
.rd_req (lpm_rd_req), // request a read
.rd_data ({lpm_rd_oq, lpm_rd_next_hop_ip}), // data found for the entry
.rd_cmp_data (lpm_rd_ip), // matching data for the entry
.rd_cmp_dmask (lpm_rd_mask_inverted), // don't cares entry
.rd_ack (lpm_rd_ack), // pulses high
// --- Write port
.wr_addr (lpm_wr_addr),
.wr_req (lpm_wr_req),
.wr_data ({lpm_wr_oq, lpm_wr_next_hop_ip}), // data found for the entry
.wr_cmp_data (lpm_wr_ip), // matching data for the entry
.wr_cmp_dmask (~lpm_wr_mask), // don't cares for the entry
.wr_ack (lpm_wr_ack),
// --- CAM interface
.cam_busy (cam_busy),
.cam_match (cam_match),
.cam_match_addr (cam_match_addr),
.cam_cmp_din (cam_cmp_din),
.cam_din (cam_din),
.cam_we (cam_we),
.cam_wr_addr (cam_wr_addr),
.cam_cmp_data_mask (cam_cmp_data_mask),
.cam_data_mask (cam_data_mask),
// --- Misc
.reset (reset),
.clk (clk));
//------------------------- Logic --------------------------------
/*****************************************************************
* find the dst IP address and do the lookup
*****************************************************************/
always @(posedge clk) begin
if(reset) begin
dst_ip <= 0;
dst_ip_vld <= 0;
end
else begin
if(word_IP_SRC_DST) begin
dst_ip[31:16] <= in_data[15:0];
end
if(word_IP_DST_LO) begin
dst_ip[15:0] <= in_data[DATA_WIDTH-1:DATA_WIDTH-16];
dst_ip_vld <= 1;
end
else begin
dst_ip_vld <= 0;
end
end // else: !if(reset)
end // always @ (posedge clk)
/*****************************************************************
* latch the outputs
*****************************************************************/
always @(posedge clk) begin
lpm_output_port <= lookup_port_result;
next_hop_ip <= (next_hop_ip_result == 0) ? dst_ip : next_hop_ip_result;
lpm_hit <= lpm_hit_result;
if(reset) begin
lpm_vld <= 0;
end
else begin
lpm_vld <= lpm_vld_result;
end // else: !if(reset)
end // always @ (posedge clk)
endmodule |
module ovl_time (clock, reset, enable, start_event, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter num_cks = 1;
parameter action_on_new_start = `OVL_ACTION_ON_NEW_START_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event;
input test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_TIME";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if (~((action_on_new_start == `OVL_IGNORE_NEW_START) ||
(action_on_new_start == `OVL_RESET_ON_NEW_START) ||
(action_on_new_start == `OVL_ERROR_ON_NEW_START)))
begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value set for parameter action_on_new_start");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_time_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_time_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_time_psl_logic.v"
`else
`endmodule |
module sky130_fd_sc_ms__dlymetal6s4s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module lo_edge_detect(
input pck0, input pck_divclk,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk,
output ssp_frame, input ssp_dout, output ssp_clk,
input cross_lo,
output dbg,
input lf_field,
input lf_ed_toggle_mode, input [7:0] lf_ed_threshold
);
wire tag_modulation = ssp_dout & !lf_field;
wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
// No logic, straight through.
assign pwr_oe1 = 1'b0; // not used in LF mode
assign pwr_oe3 = 1'b0; // base antenna load = 33 Ohms
// when modulating, add another 33 Ohms and 10k Ohms in parallel:
assign pwr_oe2 = tag_modulation;
assign pwr_oe4 = tag_modulation;
assign ssp_clk = cross_lo;
assign pwr_lo = reader_modulation;
assign pwr_hi = 1'b0;
// filter the ADC values
wire data_rdy;
wire [7:0] adc_filtered;
assign adc_clk = pck0;
lp20khz_1MSa_iir_filter adc_filter(pck0, adc_d, data_rdy, adc_filtered);
// detect edges
wire [7:0] high_threshold, highz_threshold, lowz_threshold, low_threshold;
wire [7:0] max, min;
wire edge_state, edge_toggle;
lf_edge_detect lf_ed(pck0, adc_filtered, lf_ed_threshold,
max, min,
high_threshold, highz_threshold, lowz_threshold, low_threshold,
edge_state, edge_toggle);
assign dbg = lf_ed_toggle_mode ? edge_toggle : edge_state;
assign ssp_frame = lf_ed_toggle_mode ? edge_toggle : edge_state;
endmodule |
module sky130_fd_sc_hd__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_lp__o2111a_m (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__o2111a_m (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule |
module pipe_fw_ctrl(
input wire wr_reg_3_i, wr_reg_4_i,
input wire [`N-1:0] rs1_2_i, rs2_2_i,
input wire [`N-1:0] data_out_3_i,
input wire [`N-1:0] data_4_i,
input wire [4:0] rs1_n_2_i, rs2_n_2_i,
input wire [4:0] reg_wr_n_3_i,
input wire [4:0] reg_wr_n_4_i,
output reg [`N-1:0] rs1_2_o, rs2_2_o
);
//////////////////
// RS 1 forward //
//////////////////
always @(*) begin
if (reg_wr_n_3_i == rs1_n_2_i && wr_reg_3_i == 1'b1)
// Back forward from MEM stage
rs1_2_o = data_out_3_i;
else if (reg_wr_n_4_i == rs1_n_2_i && wr_reg_4_i == 1'b1)
// Back forward from WB stage
rs1_2_o = data_4_i;
else
rs1_2_o = rs1_2_i;
end
//////////////////
// RS 2 forward //
//////////////////
always @(*) begin
if (reg_wr_n_3_i == rs2_n_2_i &&
wr_reg_3_i == 1'b1)
// Back forward from MEM stage
rs2_2_o = data_out_3_i;
else if (reg_wr_n_4_i == rs2_n_2_i &&
wr_reg_4_i == 1'b1)
// Back forward from WB stage
rs2_2_o = data_4_i;
else
rs2_2_o = rs2_2_i;
end
endmodule |
module pipe_stall_ctrl(
input wire [5:0] op_1_i,
input wire alu_rrr_op_1_i,
input wire alu_rri_op_1_i,
input wire load_op_2_i,
input wire [4:0] rd_n_1_i,
input wire [4:0] rs1_n_1_i,
input wire [4:0] rs2_n_1_i,
input wire [4:0] rd_n_2_i,
output reg stall_o);
reg stall_t_1, stall_t_2;
// Type 1 stall management
always @(*) begin
stall_t_1 = 1'b0;
if (load_op_2_i) begin
// Load instruction in EX
if (alu_rrr_op_1_i && // RRR ALU inst
(rd_n_2_i == rs1_n_1_i || rd_n_2_i == rs2_n_1_i))
stall_t_1 = 1'b1; // insert stall
else if (alu_rri_op_1_i && // RRI ALU inst
rd_n_2_i == rs1_n_1_i)
stall_t_1 = 1'b1; // insert stall
end
end
// Type 2 stall management
always @(*) begin
stall_t_2 = 1'h0;
if (load_op_2_i) begin
case (op_1_i)
`LDW_OP, `LDH_OP, `LDHU_OP, `LDB_OP,
`LDBU_OP, `MOV_OP: begin // LD MOV
if (rd_n_2_i == rs1_n_1_i)
stall_t_2 = 1'b1; // stall
end
`STW_OP, `STH_OP, `STHU_OP, `STB_OP,
`STBU_OP: begin // ST
if (rd_n_2_i == rd_n_1_i ||
rd_n_2_i == rs1_n_1_i)
stall_t_2 = 1'b1; // stall
end
`STAW_OP: begin // STAW
if (rd_n_2_i == rd_n_1_i)
stall_t_2 = 1'b1; // stall
end
endcase
end
end
always @(*)
stall_o = stall_t_1 || stall_t_2;
endmodule |
module ctrl(
input wire rst,
input wire[31:0] excepttype_i,
input wire[`RegBus] cp0_epc_i,
input wire stallreq_from_id,
//À´×ÔÖ´Ðн׶εÄÔÝÍ£ÇëÇó
input wire stallreq_from_ex,
input wire branch_from_id,
output reg[`RegBus] new_pc,
output reg flush,
output reg[5:0] stall
);
always @ (*) begin
if(rst == `RstEnable) begin
stall <= 6'b000000;
flush <= 1'b0;
new_pc <= `ZeroWord;
end else if(excepttype_i != `ZeroWord) begin
flush <= 1'b1;
stall <= 6'b000000;
case (excepttype_i)
32'h00000001: begin //interrupt
new_pc <= 32'h4;
end
32'h00000008: begin //syscall
new_pc <= 32'h4;
end
32'h0000000a: begin //inst_invalid
new_pc <= 32'h00000040;
end
32'h0000000d: begin //trap
new_pc <= 32'h4;
end
32'h0000000c: begin //break
new_pc <= 32'h4;
end
32'h0000000e: begin //eret
new_pc <= cp0_epc_i;
end
default : begin
end
endcase
end else if(stallreq_from_ex == `Stop) begin
stall <= 6'b001111;
flush <= 1'b0;
end else if(stallreq_from_id == `Stop) begin
stall <= 6'b000111;
flush <= 1'b0;
end else if(branch_from_id == `Branch) begin
stall <= 6'b000010;
flush <= 1'b0;
end else begin
stall <= 6'b000000;
flush <= 1'b0;
new_pc <= `ZeroWord;
end //if
end //always
endmodule |
module icnbc
#(parameter N = 3,
parameter depth=1024,
parameter width=N, //same as N
parameter addr_sz=$clog2(depth)
)
(input clk,
input rst, //positive reset
input [N-1:0] n,
input [N/2-1:0] min_ld,
input start,
output reg [3:0] codes [N-1:0]
);
localparam [2:0]
IDLE = 0,
CALC_LD = 1,
CLOCK_CALC_LD = 2,
FIND_CODE = 3,
RD_MEM = 4,
OUTPUT_CODES = 5,
CLOCK_OUTPUT_CODES = 6,
DONE = 7;
reg [2:0] state, nxt_state;
reg [3:0] counterl[N-1:0], nxt_counterl[N-1:0], counterh[N-1:0], nxt_counterh[N-1:0];
reg [addr_sz-1:0] codelength, nxt_codelength;
reg [addr_sz-1:0] count, nxt_count;
//sequential block
always @(posedge clk)
if(rst)
begin
state <= #1 IDLE;
counterl <= #1 0;
codelength <= #1 0;
count <= #1 0;
counterh <= #1 0;
end
else
begin
state <= #1 nxt_state;
counterl <= #1 nxt_counterl;
counterh <= #1 nxt_counterh;
codelength <= #1 nxt_codelength;
count <= #1 nxt_count;
end
reg [3:0] summation [N-1:0];
reg [3:0] candidate [N-1:0];
reg wr_en, rd_en;
reg [width-1:0] d_in;
reg [addr_sz-1:0] wr_addr;
reg [width-1:0] d_out;
reg [addr_sz-1:0] rd_addr, r_addr;
reg [width-1:0] code_array[0:depth-1];
//memory
always @(posedge clk)
begin
if (wr_en)
begin
code_array[wr_addr] <= #1 d_in;
end
else if (rd_en)
begin
d_out <= #1 code_array[rd_addr];
end
end // always @ (posedge clk)
//Finite STATE MACHINE
always@*
begin
//defaults
nxt_state = state;
nxt_counterl = counterl;
nxt_counterh = counterh;
nxt_count = count;
nxt_codelength = codelength;
case(state)
IDLE:
begin
if(start)
begin
wr_addr = 0;
wr_en = 1;
d_in = 0;
nxt_codelength = 1;
nxt_state = CALC_LD;
end
end
CALC_LD:
begin
wr_en = 0;
if( (counterh == 1 ) || (codelength == depth -1) )
nxt_state = OUTPUT_CODES;
else
begin
if(counterl == 2**N-1)
nxt_counterh = counterh + 1;
summation = sum(counterl, counterh); //function call
if( summation >= min_ld )
begin
//LD[counterl] = counterl;
candidate = counterl;
nxt_counterl = counterl + 1;
nxt_state = FIND_CODE;
end
else
begin
nxt_counterl = counterl + 1;
nxt_state = CLOCK_CALC_LD;
end
end // else: !if( (counterh == 1 ) || (codelength == depth -1) )
end // case: CALC_LD
CLOCK_CALC_LD:
begin
nxt_state = CALC_LD;
end
FIND_CODE:
begin
if(count < codelength)
begin
rd_en = 1;
rd_addr = count;
nxt_state = RD_MEM;
end
else if(count == codelength)
begin
wr_en = 1;
d_in = candidate;
wr_addr = codelength;
nxt_codelength = codelength + 1;
nxt_count = 0;
nxt_state = CALC_LD;
end
end //FIND_CODE
RD_MEM:
begin
rd_en = 0;
summation = sum(d_out ^ candidate);
if (summation >= min_ld)
begin
nxt_count = count + 1;
nxt_state = FIND_CODE;
end
else
begin
nxt_count = 0;
nxt_state = CALC_LD;
end
end
OUTPUT_CODES:
begin
if( count < codelength)
begin
rd_en = 1;
rd_addr = count;
nxt_count = count + 1;
nxt_state = CLOCK_OUTPUT_CODES;
end
else
nxt_state = DONE;
end // case: OUTPUT_CODE
CLOCK_OUTPUT_CODES:
begin
rd_en = 0;
codes = d_out;
nxt_state = OUTPUT_CODES;
end
DONE:
begin
$display($time,": Done \n");
$finish;
end
endcase // case (state)
end // always@ *
function [N-1:0] sum(
input [3:0] input_vector_a [N-1:0],
input [3:0] input_vector_b [N-1:0]
);
integer k;
reg [N-1:0] temp;
begin
temp = 0;
for(k=0; k < N; k=k+1)
begin
temp = temp + input_vector[k][3:0];
end
sum = temp;
end
endfunction // sum
endmodule |
module user_tx_wr_if #(parameter USER_TAG = `AFU_TAG)
(
input wire clk,
input wire rst_n,
input wire reset_interface,
input wire set_if_pipelined,
output wire user_tx_wr_if_empty,
input wire set_if_mem_pipelined,
input wire [57:0] mem_pipeline_addr,
input wire writes_finished,
//--------------------- User RD Request -----------------------------//
// User Module TX RD
input wire [57:0] um_tx_wr_addr,
input wire [USER_TAG-1:0] um_tx_wr_tag,
input wire [511:0] um_tx_data,
input wire um_tx_wr_valid,
output wire um_tx_wr_ready,
// User Module RX RD
output reg [USER_TAG-1:0] um_rx_wr_tag,
output reg um_rx_wr_valid,
//-------------------- to Fthread Controller ------------------------//
output wire usr_arb_tx_wr_valid,
output wire [57:0] usr_arb_tx_wr_addr,
output wire [`IF_TAG-1:0] usr_arb_tx_wr_tag,
output wire [511:0] usr_arb_tx_data,
input wire usr_arb_tx_wr_ready,
input wire usr_arb_rx_wr_valid,
input wire [`IF_TAG-1:0] usr_arb_rx_wr_tag,
output wire [57:0] wif_tx_rd_addr,
output wire [`IF_TAG-1:0] wif_tx_rd_tag,
output wire wif_tx_rd_valid,
input wire wif_tx_rd_ready,
input wire [`IF_TAG-1:0] wif_rx_rd_tag,
input wire [511:0] wif_rx_data,
input wire wif_rx_rd_valid,
//-------------------- To pipeline reader ---------------------------//
input wire usr_pipe_tx_rd_valid,
input wire [`IF_TAG-1:0] usr_pipe_tx_rd_tag,
output wire usr_pipe_tx_rd_ready,
output reg usr_pipe_rx_rd_valid,
output reg [`IF_TAG-1:0] usr_pipe_rx_rd_tag,
output reg [511:0] usr_pipe_rx_data,
input wire usr_pipe_rx_rd_ready
);
wire [512+57+USER_TAG:0] tx_wr_fifo_dout;
wire tx_wr_fifo_valid;
wire tx_wr_fifo_full;
wire tx_wr_fifo_re;
wire tx_wr_fifo_empty;
wire [`IF_TAG-1:0] pipe_rd_pending_fifo_tag;
wire pipe_rd_pending_fifo_valid;
wire pipe_rd_pending_fifo_full;
wire fifo_tx_wr_valid;
wire [57:0] fifo_tx_wr_addr;
wire [USER_TAG+1:0] fifo_tx_wr_tag;
wire [511:0] fifo_tx_data;
wire fifo_tx_wr_ready;
wire [USER_TAG+1:0] fifo_rx_wr_tag;
wire fifo_rx_wr_valid;
wire usr_tx_wr_ready;
wire [USER_TAG-1:0] usr_rx_wr_tag;
wire usr_rx_wr_valid;
wire fifo_done;
reg wr_if_pipelined = 0;
reg in_memory_pipeline = 0;
reg [57:0] fifo_base_addr;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Pipelining Control Flags ////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (~rst_n | reset_interface) begin
wr_if_pipelined <= 0;
in_memory_pipeline <= 0;
fifo_base_addr <= 0;
end
else begin
if(set_if_pipelined) begin
wr_if_pipelined <= 1'b1;
end
fifo_base_addr <= mem_pipeline_addr;
if(fifo_done) begin
in_memory_pipeline <= 1'b0;
end
else if(set_if_mem_pipelined) begin
in_memory_pipeline <= 1'b1;
end
end
end
assign user_tx_wr_if_empty = (in_memory_pipeline)? fifo_done : tx_wr_fifo_empty & ~fifo_tx_wr_valid;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Writer Requests FIFO /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
quick_fifo #(.FIFO_WIDTH(512 + 58 + USER_TAG),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) tx_wr_fifo(
.clk (clk),
.reset_n (rst_n & ~reset_interface),
.din ({um_tx_wr_tag, um_tx_wr_addr, um_tx_data}),
.we (um_tx_wr_valid),
.re (tx_wr_fifo_re),
.dout (tx_wr_fifo_dout),
.empty (tx_wr_fifo_empty),
.valid (tx_wr_fifo_valid),
.full (tx_wr_fifo_full),
.count (),
.almostfull ()
);
assign um_tx_wr_ready = ~tx_wr_fifo_full;
assign tx_wr_fifo_re = (wr_if_pipelined)? usr_pipe_rx_rd_ready & pipe_rd_pending_fifo_valid : usr_tx_wr_ready;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Accesses To Main Memory /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Pass through in-memory FIFO
sw_fifo_writer #(.USER_TAG(USER_TAG) )
sw_fifo_writer(
.clk (clk),
.rst_n (rst_n & ~reset_interface),
//-------------------------------------------------//
.fifo_base_addr (fifo_base_addr),
.setup_fifo (in_memory_pipeline & ~fifo_done),
.writes_finished (writes_finished & tx_wr_fifo_empty),
.fifo_done (fifo_done),
//--------------------- FIFO to QPI ----------------//
// TX RD
.fifo_tx_rd_addr (wif_tx_rd_addr),
.fifo_tx_rd_tag (wif_tx_rd_tag),
.fifo_tx_rd_valid (wif_tx_rd_valid),
.fifo_tx_rd_ready (wif_tx_rd_ready),
// TX WR
.fifo_tx_wr_addr (fifo_tx_wr_addr),
.fifo_tx_wr_tag (fifo_tx_wr_tag),
.fifo_tx_wr_valid (fifo_tx_wr_valid),
.fifo_tx_data (fifo_tx_data),
.fifo_tx_wr_ready (fifo_tx_wr_ready),
// RX RD
.fifo_rx_rd_tag (wif_rx_rd_tag),
.fifo_rx_data (wif_rx_data),
.fifo_rx_rd_valid (wif_rx_rd_valid),
// RX WR
.fifo_rx_wr_valid (fifo_rx_wr_valid),
.fifo_rx_wr_tag (fifo_rx_wr_tag),
///////////////////////// User Logic Interface ////////////////////
.usr_tx_wr_tag (tx_wr_fifo_dout[512+57+USER_TAG:570]),
.usr_tx_wr_valid (tx_wr_fifo_valid & ~wr_if_pipelined),
.usr_tx_wr_addr (tx_wr_fifo_dout[569:512]),
.usr_tx_data (tx_wr_fifo_dout[511:0]),
.usr_tx_wr_ready (usr_tx_wr_ready),
.usr_rx_wr_tag (usr_rx_wr_tag),
.usr_rx_wr_valid (usr_rx_wr_valid)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Requests Ordering Module ////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
order_module_backpressure_wr #(
.TAG_WIDTH(7),
.OUT_TAG_WIDTH(`IF_TAG),
.USER_TAG_WIDTH(USER_TAG+2))
omodule(
.clk (clk),
.rst_n (rst_n & ~reset_interface),
//-------------------------------------------------//
// input requests
.usr_tx_wr_addr (fifo_tx_wr_addr),
.usr_tx_wr_tag (fifo_tx_wr_tag),
.usr_tx_wr_valid (fifo_tx_wr_valid),
.usr_tx_data (fifo_tx_data),
.usr_tx_wr_ready (fifo_tx_wr_ready),
// TX RD
.ord_tx_wr_addr (usr_arb_tx_wr_addr),
.ord_tx_wr_tag (usr_arb_tx_wr_tag),
.ord_tx_wr_valid (usr_arb_tx_wr_valid),
.ord_tx_data (usr_arb_tx_data),
.ord_tx_wr_ready (usr_arb_tx_wr_ready),
// RX RD
.ord_rx_wr_tag (usr_arb_rx_wr_tag[7:0]),
.ord_rx_wr_valid (usr_arb_rx_wr_valid),
//
.usr_rx_wr_tag (fifo_rx_wr_tag),
.usr_rx_wr_valid (fifo_rx_wr_valid),
.usr_rx_wr_ready (1'b1)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Direct AFU-AFU Pipeline /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//-------------------------------------------//
// Pipe RX RD
// data, tag
always @(posedge clk) begin
if(usr_pipe_rx_rd_ready) begin
usr_pipe_rx_rd_tag <= pipe_rd_pending_fifo_tag;
usr_pipe_rx_data <= tx_wr_fifo_dout[511:0];
end
end
// valid
always @(posedge clk) begin
if (~rst_n) begin
usr_pipe_rx_rd_valid <= 0;
end
else if(usr_pipe_rx_rd_ready) begin
usr_pipe_rx_rd_valid <= pipe_rd_pending_fifo_valid & tx_wr_fifo_valid;
end
end
//--------------------------------------------//
// pipe_rd_pending_fifo
quick_fifo #(.FIFO_WIDTH(`IF_TAG),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) pipe_rd_pending_fifo(
.clk (clk),
.reset_n (rst_n),
.din (usr_pipe_tx_rd_tag),
.we (usr_pipe_tx_rd_valid & wr_if_pipelined),
.re (tx_wr_fifo_valid & usr_pipe_rx_rd_ready),
.dout (pipe_rd_pending_fifo_tag),
.empty (),
.valid (pipe_rd_pending_fifo_valid),
.full (pipe_rd_pending_fifo_full),
.count (),
.almostfull ()
);
assign usr_pipe_tx_rd_ready = ~pipe_rd_pending_fifo_full;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Write Request Responses /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// tag
always @(posedge clk) begin
if (wr_if_pipelined) begin
um_rx_wr_tag <= tx_wr_fifo_dout[512+57+USER_TAG:570];
end
else begin
um_rx_wr_tag <= fifo_rx_wr_tag;//[USER_TAG-1:0];
end
end
// valid
always @(posedge clk) begin
if (~rst_n) begin
// reset
um_rx_wr_valid <= 0;
end
else if (wr_if_pipelined) begin
um_rx_wr_valid <= usr_pipe_rx_rd_ready & pipe_rd_pending_fifo_valid & tx_wr_fifo_valid;
end
else begin
um_rx_wr_valid <= usr_rx_wr_valid;
end
end
endmodule |
module f_permutation(clk, reset, in, in_ready, ack, out, out_ready);
input clk, reset;
input [575:0] in;
input in_ready;
output ack;
output reg [1599:0] out;
output reg out_ready;
reg [10:0] i; /* select round constant */
wire [1599:0] round_in, round_out;
wire [63:0] rc1, rc2;
wire update;
wire accept;
reg calc; /* == 1: calculating rounds */
assign accept = in_ready & (~ calc); // in_ready & (i == 0)
always @ (posedge clk)
if (reset) i <= 0;
else i <= {i[9:0], accept};
always @ (posedge clk)
if (reset) calc <= 0;
else calc <= (calc & (~ i[10])) | accept;
assign update = calc | accept;
assign ack = accept;
always @ (posedge clk)
if (reset)
out_ready <= 0;
else if (accept)
out_ready <= 0;
else if (i[10]) // only change at the last round
out_ready <= 1;
assign round_in = accept ? {in ^ out[1599:1599-575], out[1599-576:0]} : out;
rconst2in1
rconst_ ({i, accept}, rc1, rc2);
round2in1
round_ (round_in, rc1, rc2, round_out);
always @ (posedge clk)
if (reset)
out <= 0;
else if (update)
out <= round_out;
endmodule |
module CFGLUT5 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output CDO,
output O5,
output O6,
input CDI,
input CE,
input CLK,
input I0,
input I1,
input I2,
input I3,
input I4
);
`ifdef XIL_TIMING
wire CDI_dly;
wire CE_dly;
wire CLK_dly;
`endif
reg [31:0] data = INIT;
reg first_time = 1'b1;
initial
begin
assign data = INIT;
first_time <= #100000 1'b0;
`ifdef XIL_TIMING
while ((((CLK_dly !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) ||
((CLK_dly !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) &&
(first_time == 1'b1)) #1000;
`else
while ((((CLK !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) ||
((CLK !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) &&
(first_time == 1'b1)) #1000;
`endif
deassign data;
end
`ifdef XIL_TIMING
generate
if (IS_CLK_INVERTED == 1'b0) begin : generate_block1
always @(posedge CLK_dly) begin
if (CE_dly == 1'b1) begin
data[31:0] <= {data[30:0], CDI_dly};
end
end
end else begin : generate_block1
always @(negedge CLK_dly) begin
if (CE_dly == 1'b1) begin
data[31:0] <= {data[30:0], CDI_dly};
end
end
end
endgenerate
`else
generate
if (IS_CLK_INVERTED == 1'b0) begin : generate_block1
always @(posedge CLK) begin
if (CE == 1'b1) begin
data[31:0] <= {data[30:0], CDI};
end
end
end else begin : generate_block1
always @(negedge CLK) begin
if (CE == 1'b1) begin
data[31:0] <= {data[30:0], CDI};
end
end
end
endgenerate
`endif
assign O6 = data[{I4,I3,I2,I1,I0}];
assign O5 = data[{1'b0,I3,I2,I1,I0}];
assign CDO = data[31];
`ifdef XIL_TIMING
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_ce_clk_en_p;
wire sh_ce_clk_en_n;
always @(notifier)
data[0] = 1'bx;
assign sh_clk_en_p = ~IS_CLK_INVERTED;
assign sh_clk_en_n = IS_CLK_INVERTED;
assign sh_ce_clk_en_p = CE && ~IS_CLK_INVERTED;
assign sh_ce_clk_en_n = CE && IS_CLK_INVERTED;
`endif
specify
(CLK => CDO) = (100:100:100, 100:100:100);
(CLK => O5) = (100:100:100, 100:100:100);
(CLK => O6) = (100:100:100, 100:100:100);
(I0 => CDO) = (0:0:0, 0:0:0);
(I0 => O5) = (0:0:0, 0:0:0);
(I0 => O6) = (0:0:0, 0:0:0);
(I1 => CDO) = (0:0:0, 0:0:0);
(I1 => O5) = (0:0:0, 0:0:0);
(I1 => O6) = (0:0:0, 0:0:0);
(I2 => CDO) = (0:0:0, 0:0:0);
(I2 => O5) = (0:0:0, 0:0:0);
(I2 => O6) = (0:0:0, 0:0:0);
(I3 => CDO) = (0:0:0, 0:0:0);
(I3 => O5) = (0:0:0, 0:0:0);
(I3 => O6) = (0:0:0, 0:0:0);
(I4 => CDO) = (0:0:0, 0:0:0);
(I4 => O5) = (0:0:0, 0:0:0);
(I4 => O6) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, negedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,CDI_dly);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly);
$setuphold (negedge CLK, posedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,CDI_dly);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly);
$setuphold (posedge CLK, negedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,CDI_dly);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly);
$setuphold (posedge CLK, posedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,CDI_dly);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule |
module ao486_rst_controller
(
input wire clk_sys,
input wire rst,
output reg ao486_rst,
input wire [1:0] address,
input wire write,
input wire [31:0] writedata
);
always @(posedge clk_sys) begin
if(rst) begin
ao486_rst <= 1;
end else begin
if(write && writedata[0] == 1'b0 && address == 4'b0000)
ao486_rst <= 0;
else if(write && writedata[0] == 1'b1 && address == 4'b0000)
ao486_rst <= 1;
end
end
endmodule |
module clk_gen (
input wire clk_ref,
input wire reset_sw,
output wire clk,
output wire clk_n,
output wire chip_reset
);
wire locked;
wire dcm_reset;
assign locked = 1'b1;
assign dcm_reset = (reset_sw == `RESET_ENABLE) ? `ENABLE : `DISABLE;
assign chip_reset = ((reset_sw == `RESET_ENABLE) || (locked == `DISABLE)) ?
`RESET_ENABLE : `RESET_DISABLE;
// /********** Xilinx DCM (Digitl Clock Manager) **********/
// x_s3e_dcm x_s3e_dcm (
// .CLKIN_IN (clk_ref),
// .RST_IN (dcm_reset),
// .CLK0_OUT (clk),
// .CLK180_OUT (clk_n),
// .LOCKED_OUT (locked)
//);
assign clk = clk_ref;
assign clk_n = ~clk_ref;
endmodule |
module sky130_fd_sc_hdll__einvp_1 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__einvp_1 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule |
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