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tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc568.vhd | 4 | 2898 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc568.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:33 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:31 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:05 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00568ent IS
END c03s04b01x00p01n01i00568ent;
ARCHITECTURE c03s04b01x00p01n01i00568arch OF c03s04b01x00p01n01i00568ent IS
type positive_vector is array (natural range <>) of positive;
type positive_vector_file is file of positive_vector;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : positive_vector_file open read_mode is "iofile.25";
variable v : positive_vector(0 to 3);
variable len : positive;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= (1,2,3,4)) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00568"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00568 - File reading operation (positive_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00568arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue813/mwe.vhdl | 1 | 102 | entity flip_flop_7474 is
Port ( j: in bit);
begin
assert j'stable (6 ns);
end flip_flop_7474;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd | 4 | 2541 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.words.all;
entity cpu is
port ( address : out uword; data : inout uword; -- . . . );
-- not in book
other_port : in X01Z := 'Z' );
-- end not in book
end entity cpu;
-- not in book
architecture behavioral of cpu is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
use work.words.all;
entity memory is
port ( address : in uword; data : inout uword; -- . . . );
-- not in book
other_port : in X01Z := 'Z' );
-- end not in book
end entity memory;
-- not in book
architecture behavioral of memory is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
-- not in book
use work.words.all;
entity ROM is
port ( a : in uword; d : out ubyte; other_port : in X01Z := 'Z' );
end entity ROM;
architecture behavioral of ROM is
begin
end architecture behavioral;
entity computer_system is
end entity computer_system;
-- end not in book
architecture top_level of computer_system is
use work.words.all;
signal address : uword;
signal data : word;
-- . . .
begin
the_cpu : entity work.cpu(behavioral)
port map ( address, data, -- . . . );
-- not in book
open );
-- end not in book
the_memory : entity work.memory(behavioral)
port map ( address, data, -- . . . );
-- not in book
open );
-- end not in book
-- . . .
-- code from book (in text)
-- boot_rom : entity work.ROM(behavioral)
-- port map ( a => address, d => data(24 to 31), -- . . . ); -- illegal
-- -- not in book
-- other_port => open );
-- -- end not in book
-- end code from book
end architecture top_level;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket73/bug.vhdl | 3 | 306 | entity ent is
end entity;
architecture a of ent is
procedure proc(s : string) is
begin
report integer'image(s'left);
report integer'image(s'right);
report s;
end procedure;
begin
main : process
begin
proc(s(4 to 15) => "Hello world!");
wait;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue107/test1.vhdl | 2 | 550 | library ieee;
use ieee.std_logic_1164.all;
entity ApbMasterBfmE is
generic (
G_ADDR_WIDTH : positive := 8; --* address bus width
G_DATA_WIDTH : positive := 8; --* data bus width
G_SLAVE_COUNT : positive := 1
);
port (
PRreset_n_i : in std_logic;
PClk_i : in std_logic
);
end entity ApbMasterBfmE;
package MyTestPkg is new work.TestPkg generic map (G_TEST => 17);
architecture sim of ApbMasterBfmE is
use work.MyTestPkg.all;
begin
assert false report "done" severity note;
end architecture sim;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2222.vhd | 4 | 1684 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2222.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02222ent IS
END c07s02b06x00p01n01i02222ent;
ARCHITECTURE c07s02b06x00p01n01i02222arch OF c07s02b06x00p01n01i02222ent IS
BEGIN
TESTING: PROCESS
variable BITV : BIT := '0';
variable k : integer;
BEGIN
k := BITV rem '1';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02222 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02222arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1126.vhd | 4 | 2123 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1126.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p04n01i01126ent IS
END c06s05b00x00p04n01i01126ent;
ARCHITECTURE c06s05b00x00p04n01i01126arch OF c06s05b00x00p04n01i01126ent IS
BEGIN
TESTING: PROCESS
type FIVE1 is range 1 to 5;
type FIVE2 is range 1 to 5;
type A3B is array (FIVE1 range <>) of BOOLEAN;
subtype A3 is A3B (FIVE1);
type A4B is array (FIVE2 range <>) of A3;
subtype A4 is A4B (FIVE2);
variable V4: A4 ;
BEGIN
V4(3)(1 to 5) := V4(4)(FIVE1); -- legal assignments.
assert NOT(V4(3)(1 to 5) = (false,false,false,false,false))
report "***PASSED TEST: c06s05b00x00p04n01i01126"
severity NOTE;
assert (V4(3)(1 to 5) = (false,false,false,false,false))
report "***FAILED TEST: c06s05b00x00p04n01i01126 - Bounds of the discrete range must be the type of the index of the array."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p04n01i01126arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/generate_clock.vhd | 4 | 1707 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity generate_clock is
end entity generate_clock;
library ieee; use ieee.std_logic_1164.all;
architecture test of generate_clock is
-- code from book
procedure generate_clock ( signal clk : out std_ulogic;
constant Tperiod, Tpulse, Tphase : in time ) is
begin
wait for Tphase;
loop
clk <= '1', '0' after Tpulse;
wait for Tperiod;
end loop;
end procedure generate_clock;
-- end code from book
-- code from book (in text)
signal phi1, phi2 : std_ulogic := '0';
-- . . .
-- end code from book
begin
-- code from book (in text)
gen_phi1 : generate_clock ( phi1, Tperiod => 50 ns, Tpulse => 20 ns,
Tphase => 0 ns );
gen_phi2 : generate_clock ( phi2, Tperiod => 50 ns, Tpulse => 20 ns,
Tphase => 25 ns );
-- end code from book
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/mul_578.vhd | 2 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_578 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_578;
architecture augh of mul_578 is
signal tmp_res : signed(46 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_06.vhd | 4 | 1417 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture fixed_length_series of cos is
begin
summation : process (theta) is
variable sum, term : real;
begin
sum := 1.0;
term := 1.0;
for n in 1 to 9 loop
term := (-term) * theta**2 / real(((2*n-1) * 2*n));
sum := sum + term;
end loop;
result <= sum;
end process summation;
end architecture fixed_length_series;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug20771/20771.vhd | 3 | 665 | entity Jon is
end Jon;
use std.textio.all;
architecture Taylor of Jon is
begin
process is
variable buf:line;
variable s : string(1 to 1);
variable fstatus : file_open_status;
file readfile : text;
constant temp_string : string := "hello.txt";
begin
file_open(fstatus, readfile, temp_string, read_mode);
report "open " & file_open_status'image(fstatus) severity note;
if fstatus = OPEN_OK then
-- while not endfile(readfile)
loop
readline(readfile, buf);
read(buf, s);
report "s= "& s severity note;
end loop;
end if;
report "done" severity note;
wait;
end process;
end Taylor;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc86.vhd | 4 | 1811 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc86.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x03p05n02i00086ent IS
END c04s03b01x03p05n02i00086ent;
ARCHITECTURE c04s03b01x03p05n02i00086arch OF c04s03b01x03p05n02i00086ent IS
BEGIN
TESTING: PROCESS
type some_type is (Sunday,Monday,Tuesday,Wed,Thur,Fri);
variable X : some_type; -- No_failure_here
-- no default value declared.
BEGIN
assert NOT( X=Sunday )
report "***PASSED TEST: c04s03b01x03p05n02i00086"
severity NOTE;
assert ( X=Sunday )
report "***FAILED TEST: c04s03b01x03p05n02i00086 - Variable default assignment failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x03p05n02i00086arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3167.vhd | 4 | 1901 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3167.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p17n01i03167ent IS
END c14s01b00x00p17n01i03167ent;
ARCHITECTURE c14s01b00x00p17n01i03167arch OF c14s01b00x00p17n01i03167ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'right = 15 and
roufbit'right = 0 )
report "***PASSED TEST: c14s01b00x00p17n01i03167"
severity NOTE;
assert ( fourbit'right = 15 and
roufbit'right = 0 )
report "***FAILED TEST: c14s01b00x00p17n01i03167 - Predefined attribute RIGHT for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p17n01i03167arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1506.vhd | 4 | 1884 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1506.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n04i01506ent IS
END c08s08b00x00p14n04i01506ent;
ARCHITECTURE c08s08b00x00p14n04i01506arch OF c08s08b00x00p14n04i01506ent IS
BEGIN
TESTING: PROCESS
type day is (sun,mon,tue,wed,thu,fri,sat);
type rec_type is
record
element : day;
end record;
variable s_day ; day;
BEGIN
case s_day is
when sun => NULL;
when mon => NULL;
when elements => NULL;
when others => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p14n04i01506 - A simple name is not allowed as an alternative in a CASE statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n04i01506arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1725.vhd | 4 | 1754 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1725.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b01x00p04n01i01725ent IS
END c12s06b01x00p04n01i01725ent;
ARCHITECTURE c12s06b01x00p04n01i01725arch OF c12s06b01x00p04n01i01725ent IS
signal clk : bit;
BEGIN
TESTING: PROCESS
BEGIN
--
-- The signal assignment below tries to make two
-- assignments at the same (current) time.
--
clk <= '0', '1';
assert FALSE
report "***FAILED TEST: c12s06b01x00p04n01i01725 - The signal assignment can not make two assignment at the same (current) time."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b01x00p04n01i01725arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd | 4 | 2336 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.MVL4.all;
entity ROM is
port ( a : in MVL4_ulogic_vector(15 downto 0);
d : inout MVL4_logic_vector(7 downto 0);
rd : in MVL4_ulogic );
end entity ROM;
-- not in book
architecture behavioral of ROM is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
use work.MVL4.all;
entity SIMM is
port ( a : in MVL4_ulogic_vector(9 downto 0);
d : inout MVL4_logic_vector(31 downto 0);
ras, cas, we, cs : in MVL4_ulogic );
end entity SIMM;
-- not in book
architecture behavioral of SIMM is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
-- not in book
use work.MVL4.all;
entity memory_subsystem is
end entity memory_subsystem;
-- end not in book
architecture detailed of memory_subsystem is
signal internal_data : MVL4_logic_vector(31 downto 0);
-- . . .
-- not in book
signal internal_addr : MVL4_ulogic_vector(31 downto 0);
signal main_mem_addr : MVL4_ulogic_vector(9 downto 0);
signal ROM_select : MVL4_ulogic;
-- end not in book
begin
boot_ROM : entity work.ROM(behavioral)
port map ( a => internal_addr(15 downto 0),
d => internal_data(7 downto 0),
rd => ROM_select );
main_mem : entity work.SIMM(behavioral)
port map ( a => main_mem_addr, d => internal_data, -- . . . );
-- not in book
ras => '0', cas => '0', we => '0', cs => '0' );
-- end not in book
-- . . .
end architecture detailed;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1953.vhd | 4 | 1772 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1953.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01953ent IS
END c07s02b01x00p02n02i01953ent;
ARCHITECTURE c07s02b01x00p02n02i01953arch OF c07s02b01x00p02n02i01953ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := TRUE;
variable b : boolean := FALSE;
variable c : boolean;
BEGIN
c := a and b;
assert NOT(c=FALSE)
report "***PASSED TEST: c07s02b01x00p02n02i01953"
severity NOTE;
assert ( c=FALSE )
report "***FAILED TEST: c07s02b01x00p02n02i01953 - Logical operation of 'AND'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01953arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1589.vhd | 4 | 1861 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1589.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01589ent IS
END c08s11b00x00p03n01i01589ent;
ARCHITECTURE c08s11b00x00p03n01i01589arch OF c08s11b00x00p03n01i01589ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
BEGIN
K : for j in 1 to 10 loop
L : for i in 1 to 10 loop
exit K when j = 3;
p := p + 1;
end loop L;
end loop;
assert NOT( p = 20 )
report "***PASSED TEST: c08s11b00x00p03n01i01589"
severity NOTE;
assert ( p = 20 )
report "***FAILED TEST: c08s11b00x00p03n01i01589 - An exit statement with a loop label within a labeled loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01589arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2201.vhd | 4 | 1877 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2201.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02201ent IS
END c07s02b06x00p01n01i02201ent;
ARCHITECTURE c07s02b06x00p01n01i02201arch OF c07s02b06x00p01n01i02201ent IS
BEGIN
TESTING: PROCESS
type array_one is array (1 to 10) of boolean;
type array_two is array (1 to 20) of boolean;
variable x : array_one;
variable y : array_two;
variable z : integer;
BEGIN
z := x * y; -- Failure_here
-- multiplying operator cannot operate on array types.
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02201 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02201arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1853.vhd | 4 | 1751 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1853.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01853ent IS
END c07s01b00x00p08n01i01853ent;
ARCHITECTURE c07s01b00x00p08n01i01853arch OF c07s01b00x00p08n01i01853ent IS
signal sma_int : integer;
BEGIN
b: block ( sma_int = ch0701_p00801_44_arch ) -- body name illegal here
begin
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01853 - Architecture body names are not permitted as primaries in a block guard expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01853arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue1015/std.vhdl | 1 | 20 | package std is end;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1240.vhd | 4 | 1669 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1240.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p03n01i01240ent IS
END c08s02b00x00p03n01i01240ent;
ARCHITECTURE c08s02b00x00p03n01i01240arch OF c08s02b00x00p03n01i01240ent IS
BEGIN
TESTING: PROCESS
type BYTE_T is array (1 to 8) of BIT;
variable k : BYTE_T;
BEGIN
assert k;
assert FALSE
report "***FAILED TEST: c08s02b00x00p03n01i01240 - The condition in the assert statement is not of type boolean"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p03n01i01240arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/vector.d/cmp_200.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_200 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_200;
architecture augh of cmp_200 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_05.vhd | 4 | 1436 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package system_types is
-- code from book
type system_status is (idle, active, overloaded);
-- end code from book
end package system_types;
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
-- code from book
alias status_type is work.system_types.system_status;
-- end code from book
begin
process_2_b : process is
variable status : status_type := idle;
begin
wait for 10 ns;
status := active;
wait for 10 ns;
status := overloaded;
wait;
end process process_2_b;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2425.vhd | 4 | 2022 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2425.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n02i02425ent IS
END c07s03b02x01p01n02i02425ent;
ARCHITECTURE c07s03b02x01p01n02i02425arch OF c07s03b02x01p01n02i02425ent IS
type rec is record
a: integer;
b: integer;
c: integer;
d: integer;
end record;
constant y: rec := (a => 12, others => 10); -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(y.a=12 and y.b=10 and y.c=10 and y.d=10)
report "***PASSED TEST: c07s03b02x01p01n02i02425"
severity NOTE;
assert (y.a=12 and y.b=10 and y.c=10 and y.d=10)
report "***FAILED TEST: c07s03b02x01p01n02i02425 - If the choice others is given as a choice of a record aggregate, it must represent at least one element."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n02i02425arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1293.vhd | 4 | 1697 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1293.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p05n01i01293ent IS
END c08s04b00x00p05n01i01293ent;
ARCHITECTURE c08s04b00x00p05n01i01293arch OF c08s04b00x00p05n01i01293ent IS
signal done : bit;
BEGIN
TESTING: PROCESS
BEGIN
done <= '1' after 10 ns,
'0' after 20 ns
'1' after 35 ns;
wait for 70 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p05n01i01293 - Waveform elements should be separated by commas."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p05n01i01293arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1723.vhd | 4 | 1742 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1723.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b01x00p03n01i01723ent IS
END c12s06b01x00p03n01i01723ent;
ARCHITECTURE c12s06b01x00p03n01i01723arch OF c12s06b01x00p03n01i01723ent IS
signal k : bit;
BEGIN
TESTING: PROCESS
BEGIN
k <= '1';
wait for 1 ns;
assert NOT(k = '1')
report "***PASSED TEST: c12s06b01x00p03n01i01723"
severity NOTE;
assert (k = '1')
report "***FAILED TEST: c12s06b01x00p03n01i01723 - A driver contains at least one transaction. This should be OK."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b01x00p03n01i01723arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc417.vhd | 4 | 3124 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc417.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00417ent IS
END c03s02b01x01p19n01i00417ent;
ARCHITECTURE c03s02b01x01p19n01i00417arch OF c03s02b01x01p19n01i00417ent IS
type real_cons_vector is array (15 downto 0) of real;
constant C1 : real_cons_vector := (others => 3.0);
function complex_scalar(s : real_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return real_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : real_cons_vector;
signal S2 : real_cons_vector;
signal S3 : real_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00417"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00417 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00417arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2712.vhd | 4 | 1912 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2712.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p01n01i02712ent IS
END c13s04b02x00p01n01i02712ent;
ARCHITECTURE c13s04b02x00p01n01i02712arch OF c13s04b02x00p01n01i02712ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( (2#11#=3)
and (7#66#=48)
and (12#BB#=143)
and (16#FF#=255))
report "***PASSED TEST: c13s04b02x00p01n01i02712"
severity NOTE;
assert ( (2#11#=3)
and (7#66#=48)
and (12#BB#=143)
and (16#FF#=255))
report "***FAILED TEST: c13s04b02x00p01n01i02712 - Correct based literal test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p01n01i02712arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1166/tb_ent.vhdl | 1 | 766 | library ieee;
use ieee.std_logic_1164.all;
entity tb_ent is
end;
architecture a of tb_ent is
signal a, enable, d_in, d_out : std_logic;
begin
uut: entity work.ent
port map (
a => a,
enable => enable,
d_in => d_in,
d_out => d_out
);
process
begin
a <= '0';
enable <= '0';
wait for 10 ns;
assert d_out = '0';
a <= '1';
wait for 10 ns;
assert d_out = '1' severity failure;
enable <= '1';
a <= 'Z';
d_in <= '0';
wait for 10 ns;
assert a = '0' severity failure;
d_in <= '1';
wait for 10 ns;
assert a = '1' severity failure;
wait;
end process;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3025.vhd | 4 | 2135 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3025.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c11s04b00x00p07n03i03025pkg_p is
end c11s04b00x00p07n03i03025p;
use work.c11s04b00x00p07n03i03025pkg_p.all;
package c11s04b00x00p07n03i03025pkg_pp is
end c11s04b00x00p07n03i03025pkg_pp;
use work.c11s04b00x00p07n03i03025pkg_pp.all;
package c11s04b00x00p07n03i03025pkg_ppp is
end c11s04b00x00p07n03i03025pkg_ppp;
package c11s04b00x00p07n03i03025pkg_p is
end c11s04b00x00p07n03i03025pkg_p;
use work.c11s04b00x00p07n03i03025pkg_pp.all; -- Failure_here
package c11s04b00x00p07n03i03025pkg_ppp is
end c11s04b00x00p07n03i03025pkg_ppp;
ENTITY c11s04b00x00p07n03i03025ent IS
END c11s04b00x00p07n03i03025ent;
ARCHITECTURE c11s04b00x00p07n03i03025arch OF c11s04b00x00p07n03i03025ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c11s04b00x00p07n03i03025 - Package ch1104_p00703_01_pkg_pp has been changed since last analysis."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s04b00x00p07n03i03025arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2553.vhd | 4 | 1582 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2553.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b06x00p02n01i02553ent IS
END c07s03b06x00p02n01i02553ent;
ARCHITECTURE c07s03b06x00p02n01i02553arch OF c07s03b06x00p02n01i02553ent IS
BEGIN
TESTING: PROCESS
variable b : bit;
BEGIN
b := new bit;
assert FALSE
report "***FAILED TEST: c07s03b06x00p02n01i02553 - Not an access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b06x00p02n01i02553arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug031/ams1.vhdl | 2 | 239 | entity ams1 is
end;
architecture behav of ams1 is
nature electrical is real across real through ground reference;
-- terminal nx : electrical;
-- quantity energy : real;
begin
process
begin
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue960/tb_ent2.vhdl | 1 | 640 | entity tb_ent2 is
end tb_ent2;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent2 is
signal clk : std_logic;
signal dout : std_logic;
begin
dut: entity work.ent2
port map (
o => dout,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
wait for 1 ns;
assert dout = '0' severity failure;
pulse;
assert dout = '1' severity failure;
pulse;
assert dout = '0' severity failure;
pulse;
assert dout = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/dispout01/pkg_rec02.vhdl | 2 | 168 | library ieee;
use ieee.std_logic_1164.all;
package rec02_pkg is
type myrec is record
a : natural range 0 to 5;
b : std_logic;
end record;
end rec02_pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1996.vhd | 4 | 1879 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1996.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n02i01996ent IS
END c07s02b02x00p07n02i01996ent;
ARCHITECTURE c07s02b02x00p07n02i01996arch OF c07s02b02x00p07n02i01996ent IS
BEGIN
TESTING: PROCESS
type ENUM is ( ONE, TWO, THREE, FOUR, FIVE );
variable k : integer := 0;
BEGIN
if (ONE = ONE) then
k := 5;
else
k := 0;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n02i01996"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n02i01996 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n02i01996arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk_wa.vhd | 4 | 2172 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee, ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity bfsk_wa is
generic ( fc : real := 455.0e3; -- mean carrier frequency
delta_f : real := 5.0e3; -- difference between low and high
-- carrier frequency
amp : voltage := 1.0; -- amplitude of modulated signal
offset : voltage := 0.0 ); -- output offset voltage
port ( signal d_in : in std_logic; -- digital input
terminal a_out : electrical ); -- output terminal
end entity bfsk_wa;
----------------------------------------------------------------
architecture behavioral of bfsk_wa is
quantity vout across iout through a_out; -- output branch
quantity phi : real; -- free quantity angle in radians
constant wc : real := math_2_pi * fc; -- convert fc to rad/s
constant delta_w : real := math_2_pi * delta_f; -- convert delta_f to rad/s
begin
if To_X01(d_in) = '0' use
phi'dot == wc; -- set to carrier frequency
elsif To_X01(d_in) = '1' use
phi'dot == wc + delta_w; -- set to carrier frequency + delta
else
phi'dot == 0.0;
end use;
vout == offset + amp * sin(phi); -- create sinusoidal output using phi
end architecture behavioral;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1194.vhd | 4 | 1635 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1194.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p05n01i01194ent IS
END c08s01b00x00p05n01i01194ent;
ARCHITECTURE c08s01b00x00p05n01i01194arch OF c08s01b00x00p05n01i01194ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
k <= 5 after 5 ns;
wait on k untli (k = 5);
assert FALSE
report "***FAILED TEST: c08s01b00x00p05n01i01194 - Reserved word 'until' is misspelled"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p05n01i01194arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc271.vhd | 4 | 1832 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc271.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p06n01i00271ent IS
END c03s01b03x00p06n01i00271ent;
ARCHITECTURE c03s01b03x00p06n01i00271arch OF c03s01b03x00p06n01i00271ent IS
type GLORIA is range 1 to 6
units
PRIM;
SEC1 = 6 PRIM;
SEC2 = 36 SEC1; -- Failure_here
-- ERROR - SEMANTICS ERROR: Position Number of sec2 exceeds
-- range of physical type
end units;
BEGIN
TESTING: PROCESS
variable temp : GLORIA := 10 PRIM;
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p06n01i00271 - Position number exceeds range of physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p06n01i00271arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue328/t6.vhdl | 1 | 211 | entity t6 is
port (s : inout natural := 6);
end;
architecture behav of t6 is
begin
process
begin
s <= s + 1;
wait for 1 ns;
assert s = 7 severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/CPU.vhd | 4 | 1636 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package cell_attributes is
type length is range 0 to integer'high
units nm;
um = 1000 nm;
mm = 1000 um;
mil = 25400 nm;
end units length;
type coordinate is record
x, y : length;
end record coordinate;
attribute cell_position : coordinate;
end package cell_attributes;
entity CPU is
end entity CPU;
-- code from book
architecture cell_based of CPU is
component fpu is
port ( -- . . . );
-- not in book
port_name : bit := '0' );
-- end not in book
end component;
use work.cell_attributes.all;
attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
-- . . .
begin
the_fpu : component fpu
port map ( -- . . . );
-- not in book
port_name => open );
-- end not in book
-- . . .
end architecture cell_based;
-- end code from book
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue875/test.vhdl | 1 | 2722 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use STD.textio.all;
use ieee.std_logic_textio.all;
entity example_file_io_tb is
end example_file_io_tb;
architecture behave of example_file_io_tb is
------------------------------------------------------------------------------
-- Declare the Component under Test
------------------------------------------------------------------------------
component module_ripple_carrier_adder is
generic (
g_WIDTH: natural);
port (
i_add_term1 : in std_logic_vector(g_WIDTH-1 downto 0);
i_add_term2 : in std_logic_vector(g_WIDTH-1 downto 0);
o_result : out std_logic_vector(g_WIDTH downto 0);
);
end component module_ripple_carrier_adder;
------------------------------------------------------------------------------
-- Testbench Internal Signals
------------------------------------------------------------------------------
file file_VECTOR : text;
file file_RESULT: text;
constant c_WIDTH : natural := 4;
signal r_ADD_TERM1 : std_logic_vector(c_WIDTH-1 downto 0) := (others => '0');
signal r_ADD_TERM2 : std_logic_vector(c_WIDTH-1 downto 0) := (others => '0');
signal w_SUM : std_logic_vector(c_WIDTH downto 0);
begin
------------------------------------------------------------------------------
-- Instantiate and Map UUT
------------------------------------------------------------------------------
MODULE_RIPPLE_CARRY_ADDER_INST : module_ripple_carry_adder
generic map (
g_WIDTH => c_WIDTH)
port map (
i_addr_term1 => r_ADD_TERM1,
i_addr_term2 => r_ADD_TERM2,
o_result => w_SUM
);
------------------------------------------------------------------------------
-- This procedure reads the file input_vectors.txt which is located in the
-- simulation project area.
-- It will read the data in and send it to the ripple carry adder component
-- to perform the operations. The result is written to the
-- output_results.txt file, located in the same directory.
------------------------------------------------------------------------------
begin
file_open(file_VECTORS, "input_vectors.txt", read_mode);
file_open(file_RESULTS, "output_results.txt", write_mode);
while not endfile(file_VECTORS) loop
readline(file_VECTORS, v_ILINE);
read(v_ILINE, v_ADD_TERM1);
read(v_ILINE, v_SPACE);
read(v_ILINE, V_ADD_TERM2);
-- Pass the variable to a signal to allow the ripple-carry to use it
r_ADD_TERM1 <= v_ADD_TERM1;
r_ADD_TERM2 <= v_ADD_TERM2;
wait for 60 ns;
write(v_OLINE, w_SUM, right, c_WIDTH);
writeline(file_RESULTS, v_OLINE);
end loop;
file_close(file_VECTORS);
file_close(file_RESULTS);
wait;
end process;
end behave;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1467.vhd | 4 | 1719 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1467.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p02n01i01467ent IS
END c08s08b00x00p02n01i01467ent;
ARCHITECTURE c08s08b00x00p02n01i01467arch OF c08s08b00x00p02n01i01467ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 1;
variable k : integer := 0;
BEGIN
case x is
when 1 => k := 5;
when others => NULL;
end case
assert FALSE
report "***FAILED TEST: c08s08b00x00p02n01i01467 - Missing semicolon after the reserved word 'end case'."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p02n01i01467arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/forgen01/tb_forgen03.vhdl | 1 | 548 | entity tb_forgen03 is
end tb_forgen03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_forgen03 is
signal a : std_logic_vector (7 downto 0);
signal b : std_logic_vector (7 downto 0);
signal o : std_logic_vector (7 downto 0);
begin
dut: entity work.forgen03
port map (a, b, o);
process
begin
a <= x"30";
b <= x"28";
wait for 1 ns;
assert o = x"58" severity failure;
a <= x"11";
b <= x"f7";
wait for 1 ns;
assert o = x"08" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_06.vhd | 4 | 2877 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity data_logger is
end entity data_logger;
-- code from book
architecture high_level of data_logger is
subtype byte is bit_vector(7 downto 0);
type byte_array is array (integer range <>) of byte;
function resolver ( bytes : byte_array ) return byte is
begin
if bytes'length > 0 then
return bytes( bytes'left );
else
return X"00";
end if;
end function resolver;
subtype resolved_byte is resolver byte;
procedure reg ( signal clock, out_enable : in bit;
signal d : in byte;
-- workaround for MTI bugs mt027/mt028
-- signal q : out resolved_byte ) is
signal q : out resolved_byte bus ) is
-- end workaround
variable stored_byte : byte;
begin
loop
if clock = '1' then
stored_byte := d;
end if;
if out_enable = '1' then
q <= stored_byte;
else
q <= null;
end if;
wait on clock, out_enable, d;
end loop;
end procedure reg;
signal data_bus : resolved_byte bus;
-- . . .
-- not in book
signal a_reg_clk, b_reg_clk, a_reg_read, b_reg_read : bit := '0';
signal port_a, port_b : byte := X"00";
-- end not in book
begin
a_reg : reg (a_reg_clk, a_reg_read, port_a, data_bus);
b_reg : reg (b_reg_clk, b_reg_read, port_b, data_bus);
-- . . .
-- not in book
stimulus : process is
begin
port_a <= X"11"; a_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
a_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
port_b <= X"21"; b_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
b_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
a_reg_read <= '1', '0' after 5 ns;
b_reg_read <= '1', '0' after 5 ns;
wait;
end process stimulus;
-- end not in book
end architecture high_level;
-- end code from book
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1426.vhd | 4 | 1978 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1426.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s06b00x00p05n01i01426ent IS
END c08s06b00x00p05n01i01426ent;
ARCHITECTURE c08s06b00x00p05n01i01426arch OF c08s06b00x00p05n01i01426ent IS
procedure copy_int ( variable src, dest : inout integer ) is
--
-- This procedure copies the value of the first argument
-- into the second argument.
--
begin
dest := src;
end copy_int;
BEGIN
TESTING : PROCESS
variable v1,v2 : integer := 0;
BEGIN
--
-- Try calling the procedure with three arguments
--
v1 := 5;
copy_int(v1, v2, 5); -- too many arguments
assert FALSE
report "***FAILED TEST: c08s06b00x00p05n01i01426 - Procedure call without an actual parameter part is permitted."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s06b00x00p05n01i01426arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1165/bug.vhdl | 1 | 1276 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bug is
generic(
ADDR_WIDTH : positive := 32;
BUS_WIDTH : positive := 4;
QUEUE_LENGTH : positive := 32
);
port(
clk : in std_ulogic;
reset_n : in std_ulogic
);
end bug;
architecture behav of bug is
signal write_start_addr : unsigned(ADDR_WIDTH-1 downto 0);
signal num_words : integer range 0 to QUEUE_LENGTH-1;
function non_4k_crossing_length(start_addr : unsigned(ADDR_WIDTH-1 downto 0);
max_length : integer range 0 to QUEUE_LENGTH-1) return integer is
constant words_per_page : integer := 4096/BUS_WIDTH;
constant diff : integer range 0 to words_per_page := (words_per_page-(to_integer(start_addr)/BUS_WIDTH mod words_per_page));
begin
return minimum(diff, max_length);
end function;
begin
process(clk, reset_n)
variable aligned_start_addr : unsigned(ADDR_WIDTH-1 downto 0);
variable write_length : integer range 0 to QUEUE_LENGTH-1;
begin
if reset_n = '0' then
elsif rising_edge(clk) then
aligned_start_addr := resize(write_start_addr/BUS_WIDTH*BUS_WIDTH, ADDR_WIDTH);
write_length := non_4k_crossing_length(aligned_start_addr, num_words);
end if;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug037/arith_addw.vhdl | 2 | 12286 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Entity: arith_addw
--
-- Description:
-- ------------------------------------
-- Implements wide addition providing several options all based
-- on an adaptation of a carry-select approach.
--
-- References:
-- * Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser:
-- FPGA-Specific Arithmetic Optimizations of Short-Latency Adders,
-- FPL 2011.
-- -> ARCH: AAM, CAI, CCA
-- -> SKIPPING: CCC
--
-- * Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol:
-- A Novel Modular Adder for One Thousand Bits and More
-- Using Fast Carry Chains of Modern FPGAs, FPL 2014.
-- -> ARCH: PAI
-- -> SKIPPING: PPN_KS, PPN_BK
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
use PoC.arith.all;
entity arith_addw is
generic (
N : positive; -- Operand Width
K : positive; -- Block Count
ARCH : tArch := AAM; -- Architecture
BLOCKING : tBlocking := DFLT; -- Blocking Scheme
SKIPPING : tSkipping := CCC; -- Carry Skip Scheme
P_INCLUSIVE : boolean := false -- Use Inclusive Propagate, i.e. c^1
);
port (
a, b : in std_logic_vector(N-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(N-1 downto 0);
cout : out std_logic
);
end entity;
use std.textio.all;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of arith_addw is
-- Determine Block Boundaries
type tBlocking_vector is array(tArch) of tBlocking;
constant DEFAULT_BLOCKING : tBlocking_vector := (AAM => ASC, CAI => DESC, PAI => DESC, CCA => DESC);
type integer_vector is array(natural range<>) of integer;
impure function compute_blocks return integer_vector is
variable bs : tBlocking := BLOCKING;
variable res : integer_vector(K-1 downto 0);
variable l : line;
begin
if bs = DFLT then
bs := DEFAULT_BLOCKING(ARCH);
end if;
case bs is
when FIX =>
assert N >= K
report "Cannot have more blocks than input bits."
severity failure;
for i in res'range loop
res(i) := ((i+1)*N+K/2)/K;
end loop;
when ASC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N-K*(K-1)/2)+K/2)/K + (i+1)*i/2;
end loop;
when DESC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N+K*(K-1)/2)+K/2)/K - (i+1)*i/2;
end loop;
when others =>
report "Unknown blocking scheme: "&tBlocking'image(bs) severity failure;
end case;
--synthesis translate_off
write(l, "Implementing "&integer'image(N)&"-bit wide adder: ARCH="&tArch'image(ARCH)&
", BLOCKING="&tBlocking'image(bs)&'[');
for i in K-1 downto 1 loop
write(l, res(i)-res(i-1));
write(l, ',');
end loop;
write(l, res(0));
write(l, "], SKIPPING="&tSkipping'image(SKIPPING));
writeline(output, l);
--synthesis translate_on
return res;
end compute_blocks;
constant BLOCKS : integer_vector(K-1 downto 0) := compute_blocks;
signal g : std_logic_vector(K-1 downto 1); -- Block Generate
signal p : std_logic_vector(K-1 downto 1); -- Block Propagate
signal c : std_logic_vector(K-1 downto 1); -- Block Carry-in
begin
-----------------------------------------------------------------------------
-- Rightmost Block + Carry Computation Core
blkCore: block
constant M : positive := BLOCKS(0); -- Rightmost Block Width
begin
-- Carry Computation with Carry Chain
genCCC: if SKIPPING = CCC generate
signal x, y : unsigned(K+M-2 downto 0);
signal z : unsigned(K+M-1 downto 0);
begin
x <= unsigned(g & a(M-1 downto 0));
genExcl: if not P_INCLUSIVE generate
y <= unsigned((g or p) & b(M-1 downto 0));
-- carry recovery for other blocks
c <= std_logic_vector(z(K+M-2 downto M)) xor p;
end generate genExcl;
genIncl: if P_INCLUSIVE generate
y <= unsigned(p & b(M-1 downto 0));
-- carry recovery for other blocks
c <= std_logic_vector(z(K+M-2 downto M)) xor (p xor g);
end generate genIncl;
z <= ('0' & x) + y + (0 to 0 => cin);
-- output of rightmost block
s(M-1 downto 0) <= std_logic_vector(z(M-1 downto 0));
-- carry output
cout <= z(z'left);
end generate genCCC;
-- LUT-based Carry Computations
genLUT: if SKIPPING /= CCC generate
signal z : unsigned(M downto 0);
begin
-- rightmost block
z <= unsigned('0' & a(M-1 downto 0)) + unsigned(b(M-1 downto 0)) + (0 to 0 => cin);
s(M-1 downto 0) <= std_logic_vector(z(M-1 downto 0));
-- Plain linear LUT-based Carry Forwarding
genPlain: if SKIPPING = PLAIN generate
signal t : std_logic_vector(K downto 1);
begin
-- carry forwarding
t(1) <= z(M);
t(K downto 2) <= g or (p and c);
c <= t(K-1 downto 1);
cout <= t(K);
end generate genPlain;
-- Kogge-Stone Parallel Prefix Network
genPPN_KS: if SKIPPING = PPN_KS generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to LEVELS);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & z(M);
genLevels: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
pp(i) <= (pp(i-1)(K-1 downto D) and pp(i-1)(K-D-1 downto 0)) & pp(i-1)(D-1 downto 0);
gg(i) <= (gg(i-1)(K-1 downto D) or (pp(i-1)(K-1 downto D) and gg(i-1)(K-D-1 downto 0))) & gg(i-1)(D-1 downto 0);
end generate genLevels;
c <= gg(LEVELS)(K-2 downto 0);
cout <= gg(LEVELS)(K-1);
end generate genPPN_KS;
-- Brent-Kung Parallel Prefix Network
genPPN_BK: if SKIPPING = PPN_BK generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to 2*LEVELS-1);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & z(M);
genMerge: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j mod (2*D) = 2*D-1 generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j mod (2*D) /= 2*D-1 generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genMerge;
genSpread: for i in LEVELS+1 to 2*LEVELS-1 generate
constant D : positive := 2**(2*LEVELS-i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j > D and (j+1) mod (2*D) = D generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j <= D or (j+1) mod (2*D) /= D generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genSpread;
c <= gg(gg'high)(K-2 downto 0);
cout <= gg(gg'high)(K-1);
end generate genPPN_BK;
end generate genLUT;
end block blkCore;
-----------------------------------------------------------------------------
-- Implement Carry-Select Variant
--
-- all but rightmost block, implementation architecture selected by ARCH
genBlocks: for i in 1 to K-1 generate
-- Covered Index Range
constant LO : positive := BLOCKS(i-1); -- Low Bit Index
constant HI : positive := BLOCKS(i)-1; -- High Bit Index
-- Internal Block Interface
signal aa : unsigned(HI downto LO);
signal bb : unsigned(HI downto LO);
signal ss : unsigned(HI downto LO);
begin
-- Connect common block interface
aa <= unsigned(a(HI downto LO));
bb <= unsigned(b(HI downto LO));
s(HI downto LO) <= std_logic_vector(ss);
-- ARCH-specific Implementations
--Add-Add-Multiplex
genAAM: if ARCH = AAM generate
signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
signal s1 : unsigned(HI+1 downto LO); -- Block Sum (cin=1)
begin
s0 <= ('0' & aa) + bb;
s1 <= ('0' & aa) + bb + 1;
g(i) <= s0(HI+1);
genExcl: if not P_INCLUSIVE generate
p(i) <= s1(HI+1) xor s0(HI+1);
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= s1(HI+1);
end generate genIncl;
ss <= s0(HI downto LO) when c(i) = '0' else s1(HI downto LO);
end generate genAAM;
-- Compare-Add-Increment
genCAI: if ARCH = CAI generate
signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
begin
s0 <= ('0' & aa) + bb;
g(i) <= s0(HI+1);
genExcl: if not P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when (aa xor bb) = (aa'range => '1') else '0';
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when aa >= not bb else '0';
end generate genIncl;
ss <= s0(HI downto LO) when c(i) = '0' else s0(HI downto LO)+1;
end generate genCAI;
-- Propagate-Add-Increment
genPAI: if ARCH = PAI generate
signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
begin
s0 <= ('0' & aa) + bb;
g(i) <= s0(HI+1);
genExcl: if not P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(s0)) else
'1' when s0(HI downto LO) = (HI downto LO => '1') else '0';
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(s0)) else
'1' when s0(HI downto LO) = (HI downto LO => '1') else g(i);
end generate genIncl;
ss <= s0(HI downto LO) when c(i) = '0' else s0(HI downto LO)+1;
end generate genPAI;
-- Compare-Compare-Add
genCCA: if ARCH = CCA generate
g(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when aa > not bb else '0';
genExcl: if not P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when (aa xor bb) = (aa'range => '1') else '0';
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when aa >= not bb else '0';
end generate genIncl;
ss <= aa + bb + (0 to 0 => c(i));
end generate genCCA;
end generate genBlocks;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue685/tb.vhdl | 1 | 624 | library ieee;
use ieee.std_logic_1164.all;
package wishbone_pkg is
type t_wishbone_master_out is record
dat : std_logic_vector;
-- Works properly when field we is declared before dat
we : std_logic;
end record;
end wishbone_pkg;
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
entity wb_demux_tb is
end entity;
architecture bench of wb_demux_tb is
signal s : t_wishbone_master_out(
dat(1 downto 0)
);
begin
stimulus : process
begin
wait for 1 ns;
s.dat <= "11";
wait for 1 ns;
s.dat <= "00";
wait for 1 ns;
report "pass";
std.env.finish;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/mem02/ram3.vhdl | 1 | 550 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram3 is
port (val : out std_logic_vector (7 downto 0);
waddr : std_logic_vector (2 downto 0);
wdat : std_logic;
clk : std_logic);
end ram3;
architecture behav of ram3 is
signal mem : std_logic_vector(7 downto 0);
begin
process (clk)
variable ra : natural;
variable wa : natural;
begin
if rising_edge (clk) then
ra := to_integer(unsigned (waddr));
mem(ra) <= wdat;
end if;
end process;
val <= mem;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc343.vhd | 4 | 2022 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc343.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p09n03i00343ent IS
END c03s02b01x00p09n03i00343ent;
ARCHITECTURE c03s02b01x00p09n03i00343arch OF c03s02b01x00p09n03i00343ent IS
type M1 is array (1 to 4) of BIT;
signal X1 : M1;
BEGIN
TESTING: PROCESS
BEGIN
X1(1) <= '0' after 10 ns;
X1(2) <= '1' after 20 ns;
X1(3) <= '1' after 30 ns;
X1(4) <= '0' after 40 ns; -- No_failure_here
wait for 50 ns;
assert NOT(X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0')
report "***PASSED TEST: c03s02b01x00p09n03i00343"
severity NOTE;
assert (X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0')
report "***FAILED TEST: c03s02b01x00p09n03i00343 - The values in the given index range are not the values that belong to the corresponding range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p09n03i00343arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_03.vhd | 4 | 3373 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_fg_04_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_04_03 is
end entity fg_04_03;
----------------------------------------------------------------
architecture test of fg_04_03 is
begin
-- code from book:
modem_controller : process is
type symbol is ('a', 't', 'd', 'h', digit, cr, other);
type symbol_string is array (1 to 20) of symbol;
type state is range 0 to 6;
type transition_matrix is array (state, symbol) of state;
constant next_state : transition_matrix :=
( 0 => ('a' => 1, others => 6),
1 => ('t' => 2, others => 6),
2 => ('d' => 3, 'h' => 5, others => 6),
3 => (digit => 4, others => 6),
4 => (digit => 4, cr => 0, others => 6),
5 => (cr => 0, others => 6),
6 => (cr => 0, others => 6) );
variable command : symbol_string;
variable current_state : state := 0;
-- not in book:
type sample_array is array (positive range <>) of symbol_string;
constant sample_command : sample_array :=
( 1 => ( 'a', 't', 'd', digit, digit, cr, others => other ),
2 => ( 'a', 't', 'h', cr, others => other ),
3 => ( 'a', 't', other, other, cr, others => other ) );
-- end not in book
begin
-- . . .
-- not in book:
for command_index in sample_command'range loop
command := sample_command(command_index);
-- end not in book
for index in 1 to 20 loop
current_state := next_state( current_state, command(index) );
case current_state is
-- . . .
-- not in book:
when 0 => exit;
when others => null;
-- end not in book
end case;
end loop;
-- . . .
-- not in book:
end loop;
wait;
-- end not in book
end process modem_controller;
-- end of code from book
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1610.vhd | 4 | 1692 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1610.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p04n01i01610ent IS
END c08s11b00x00p04n01i01610ent;
ARCHITECTURE c08s11b00x00p04n01i01610arch OF c08s11b00x00p04n01i01610ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
exit L when 1;
k := i;
end loop;
assert FALSE
report "***FAILED TEST: c08s11b00x00p04n01i01610 - The condition in an exit statement must be of boolean type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p04n01i01610arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2941.vhd | 4 | 1905 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2941.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n04i02941pkg is
procedure proc1 (x, y : integer);
end c02s02b00x00p07n04i02941pkg;
package body c02s02b00x00p07n04i02941pkg is
procedure proc1 (x : integer; y :integer) is --Failure_here
begin
end proc1;
end c02s02b00x00p07n04i02941pkg;
ENTITY c02s02b00x00p07n04i02941ent IS
END c02s02b00x00p07n04i02941ent;
ARCHITECTURE c02s02b00x00p07n04i02941arch OF c02s02b00x00p07n04i02941ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n04i02941 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n04i02941arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-config-spec.vhdl | 4 | 821 | entity forty_two is
port (
int_out : out integer);
end forty_two;
architecture only of forty_two is
begin -- only
process
begin -- process
int_out <= 42;
wait;
end process;
end only;
entity test_bench is
end test_bench;
architecture only of test_bench is
component forty_two
port (
int_out : out integer);
end component;
for ft0 : forty_two
use entity work.forty_two(only)
port map ( int_out => int_out );
signal int_signal : integer;
begin -- only
ft0 : component forty_two
port map (
int_out => int_signal );
test: process
begin -- process test
wait for 1 ms;
assert int_signal = 42 report "TEST FAILED" severity ERROR;
assert not(int_signal = 42) report "TEST PASSED" severity NOTE;
wait;
end process test;
end only;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1882.vhd | 4 | 1921 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1882.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01882ent IS
END c07s01b00x00p08n01i01882ent;
ARCHITECTURE c07s01b00x00p08n01i01882arch OF c07s01b00x00p08n01i01882ent IS
type small_int is range 0 to 7;
signal s_int : small_int;
signal bool : boolean;
BEGIN
sig : bool <= true;
TESTING : PROCESS
variable tmp : small_int;
BEGIN
case sig is -- signal assignment labels illegal here
when 0 => tmp := 0;
when others => tmp := 1;
end case;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01882 - Signal assignment labels are not permitted as primaries in a case expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01882arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1513.vhd | 4 | 1603 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1513.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p02n01i01513ent IS
END c08s09b00x00p02n01i01513ent;
ARCHITECTURE c08s09b00x00p02n01i01513arch OF c08s09b00x00p02n01i01513ent IS
BEGIN
TESTING: PROCESS
BEGIN
L1 : loop
end L1;
assert FALSE
report "***FAILED TEST: c08s09b00x00p02n01i01513 - Missing reserved word 'end loop' in a loop statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p02n01i01513arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue715/LRAM.vhdl | 1 | 2572 | -------------------------------------------------------------------------------
--
-- walter d. gallegos
-- www.waltergallegos.com
-- Programmable Logic Consulting
--
-- Este archivo y documentacion son propiedad intelectual de Walter D. Gallegos
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL, IEEE.NUMERIC_STD.ALL;
USE STD.TextIO.ALL;
ENTITY LRAM IS
GENERIC ( size : INTEGER := 14; fName : STRING := "IntDemo.mem"; startAdr : INTEGER := 0);
PORT (
CLOCK : IN STD_LOGIC;
WR : IN STD_LOGIC;
BEA : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
DIA : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DOA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADRA : IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
DOB : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADRB : IN STD_LOGIC_VECTOR (size-1 DOWNTO 0)
);
END LRAM;
ARCHITECTURE WDG0 OF LRAM IS
CONSTANT depth : INTEGER := (2**size)-1;
TYPE LocalRAMDesc IS ARRAY (0 TO depth) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
IMPURE FUNCTION Init (fName : STRING) RETURN LocalRAMDesc IS
FILE f : TEXT OPEN READ_MODE IS fName;
VARIABLE l : LINE;
VARIABLE b : STD_LOGIC_VECTOR(31 DOWNTO 0);
VARIABLE m : LocalRAMDesc := (OTHERS => (OTHERS => '0'));
BEGIN
FOR i IN startAdr TO depth LOOP
EXIT WHEN endfile(f);
IF (i = depth) THEN
REPORT "LRAM : Error memory full " SEVERITY FAILURE;
END IF;
readline(f, l); hread(l, b);
m(i) := STD_LOGIC_VECTOR(RESIZE(UNSIGNED(b), 32));
END LOOP;
REPORT ("LRAM : loaded from " & fName & LF) SEVERITY NOTE;
RETURN m;
END FUNCTION;
SIGNAL LocalRAM : LocalRAMDesc := Init(fName);
SIGNAL data, code : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- XILINX ATTRIBUTE
ATTRIBUTE ram_style : STRING;
ATTRIBUTE ram_style OF LocalRAM : SIGNAL IS "block";
-- XILINX END ATTRIBUTE
BEGIN
CodeDataMemory : PROCESS(CLOCK)
BEGIN
IF rising_edge(CLOCK) THEN
FOR i IN DIA'RANGE LOOP
IF (BEA(i/8) AND WR)= '1' THEN
LocalRAM(TO_INTEGER(UNSIGNED(ADRA)))(i) <= DIA(i);
END IF;
END LOOP;
data <= LocalRAM(TO_INTEGER(UNSIGNED(ADRA)));
code <= LocalRAM(TO_INTEGER(UNSIGNED(ADRB)));
END IF;
END PROCESS CodeDataMemory;
DOA <= data;
DOB <= code;
END WDG0;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_25.vhd | 4 | 2618 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_25.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- VHDL-87
entity mux4 is
port ( i0, i1, i2, i3, sel0, sel1 : in bit;
z : out bit );
end mux4;
----------------------------------------------------------------
architecture functional of mux4 is
begin
out_select : process (sel0, sel1, i0, i1, i2, i3)
subtype bits_2 is bit_vector(1 downto 0);
begin
case bits_2'(sel1, sel0) is
when "00" => z <= i0;
when "01" => z <= i1;
when "10" => z <= i2;
when "11" => z <= i3;
end case;
end process out_select;
end functional;
----------------------------------------------------------------
entity ch_05_25 is
end ch_05_25;
----------------------------------------------------------------
architecture test of ch_05_25 is
signal select_line, line0, line1, result_line : bit;
-- code from book:
signal tied_0 : bit := '0';
signal tied_1 : bit := '1';
-- end of code from book
component mux4
port ( i0, i1, i2, i3, sel0, sel1 : in bit;
z : out bit );
end component;
for all : mux4
use entity work.mux4;
begin
a_mux : mux4
-- code from book:
port map ( sel0 => select_line, i0 => line0, i1 => line1,
z => result_line,
sel1 => tied_0, i2 => tied_1, i3 => tied_1 );
-- end of code from book
----------------
stimulus : process
begin
wait for 5 ns;
line0 <= '1'; wait for 5 ns;
line1 <= '1'; wait for 5 ns;
select_line <= '1'; wait for 5 ns;
line1 <= '0'; wait for 5 ns;
line0 <= '0'; wait for 5 ns;
wait;
end process stimulus;
end test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2570.vhd | 4 | 1752 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2570.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s05b00x00p16n02i02570ent IS
END c07s05b00x00p16n02i02570ent;
ARCHITECTURE c07s05b00x00p16n02i02570arch OF c07s05b00x00p16n02i02570ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(2.12E6 = (1.06E3*2.0E3))
report "***PASSED TEST: c07s05b00x00p16n02i02570"
severity NOTE;
assert ( 2.12E6 = (1.06E3*2.0E3) )
report "***FAILED TEST: c07s05b00x00p16n02i02570 - The values of the operands and the result lie within the range of the floating point type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s05b00x00p16n02i02570arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue38/bugreport_aliasprotected.vhdl | 1 | 6351 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
-- Reproducer: Using aliases to protected type methods cause an exception.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
-- Issue 1:
-- When analyzed in VHDL-93 mode an error is reported:
-- .\bugreport_aliasprotected.vhdl:4:26: protected type not allowed in vhdl87/93
-- .\bugreport_aliasprotected.vhdl:9:12: 'protected' is expected instead of 'protected'
-- Line 1 is perfectly clear, but what is the intension of line 2?
-- Is this follow up error necessary or should it have another message text?
--
-- Issue 2:
-- Calling an aliases to a shared variable's method causes an exception in GHDL:
-- ******************** GHDL Bug occurred ****************************
-- Please report this bug on https://github.com/tgingold/ghdl/issues
-- GHDL release: GHDL 0.34dev (commit: 2016-01-27; git branch: paebbels/master'; hash: d424eb8) [Dunoon edition]
-- Compiled with GNAT Version: GPL 2015 (20150428-49)
-- In directory: H:\Austausch\PoC\temp\ghdl\
-- Command line:
-- C:\Tools\GHDL.new\bin\ghdl.exe -r --std=08 test
-- Exception TYPES.INTERNAL_ERROR raised
-- Exception information:
-- Exception name: TYPES.INTERNAL_ERROR
-- Message: trans.adb:487
-- ******************************************************************
-- The alias definition by itself is not causing any errors. In my big example, I
-- could at least use an alias to a procedure without parameters. This short example
-- throws exceptions on all 4 variants (with/without parameter; with/without return value).
--
-- You can comment/uncomment the alias/wrapping function/procedure to cause the error.
--
-- GHDL calls:
-- PS> ghdl.exe -a --std=08 .\bugreport_aliasprotected.vhdl
-- PS> ghdl.exe -r --std=08 test
--
-- Expected output:
-- .\bugreport_aliasprotected.vhdl:163:16:@0ms:(report note): wrapGet: 7 expected: 7
-- .\bugreport_aliasprotected.vhdl:165:16:@0ms:(report note): wrapGet: 5 expected: 5
-- .\bugreport_aliasprotected.vhdl:166:16:@0ms:(report note): wrapExcahnge: 5 expected: 5
-- .\bugreport_aliasprotected.vhdl:167:16:@0ms:(report note): wrapGet: 3 expected: 3
-- .\bugreport_aliasprotected.vhdl:169:16:@0ms:(report note): wrapGet: 0 expected: 0
--
-- =============================================================================
-- Protected type package
-- =============================================================================
package pkg is
type T_INTEGER is protected
procedure Clear;
procedure Set(Value : INTEGER);
impure function Get return INTEGER;
impure function Exchange(Value : INTEGER) return INTEGER;
end protected;
end package;
package body pkg is
type T_INTEGER is protected body
variable LocalVariable : INTEGER := 7;
procedure Clear is
begin
LocalVariable := 0;
end procedure;
procedure Set(Value : INTEGER) is
begin
LocalVariable := Value;
end procedure;
impure function Get return INTEGER is
begin
return LocalVariable;
end function;
impure function Exchange(Value : INTEGER) return INTEGER is
variable Result : INTEGER;
begin
Result := LocalVariable;
LocalVariable := Value;
return Result;
end function;
end protected body;
end package body;
-- =============================================================================
-- Wrapper package
-- =============================================================================
use work.pkg.all;
package wrapper is
shared variable MyBoolean : T_INTEGER;
-- alias wrapClear is MyBoolean.Clear[]; -- if this alias is used, GHDL crashes
alias wrapperClear is MyBoolean.Clear[]; -- unused alias => no crash
procedure wrapClear; -- wrapped by a call chain => no crash
-- alias wrapSet is MyBoolean.Set[INTEGER];
procedure wrapSet(Value : INTEGER);
-- alias wrapGet is MyBoolean.Get[return INTEGER];
impure function wrapGet return INTEGER;
-- alias wrapExchange is MyBoolean.Exchange[INTEGER return INTEGER];
impure function wrapExchange(Value : INTEGER) return INTEGER;
end package;
package body wrapper is
procedure wrapClear is
begin
MyBoolean.Clear;
end procedure;
procedure wrapSet(Value : INTEGER) is
begin
MyBoolean.Set(Value);
end procedure;
impure function wrapGet return INTEGER is
begin
return MyBoolean.Get;
end function;
impure function wrapExchange(Value : INTEGER) return INTEGER is
begin
return MyBoolean.Exchange(Value);
end function;
end package body;
-- =============================================================================
-- Testbench
-- =============================================================================
use work.wrapper.all;
entity test is
end entity;
architecture tb of test is
begin
process
begin
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 7" severity NOTE;
wrapSet(5);
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 5" severity NOTE;
report "wrapExcahnge: " & INTEGER'image(wrapExchange(3)) & " expected: 5" severity NOTE;
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 3" severity NOTE;
wrapperClear;
report "wrapGet: " & INTEGER'image(wrapGet) & " expected: 0" severity NOTE;
wait;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc12.vhd | 4 | 1629 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc12.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p02n01i00012ent IS
END c04s02b00x00p02n01i00012ent;
ARCHITECTURE c04s02b00x00p02n01i00012arch OF c04s02b00x00p02n01i00012ent IS
--reserved word misspelled
subtyp GROUND is BIT range '0' to '0';
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s02b00x00p02n01i00012 - The reserved word is misspelled."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p02n01i00012arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug0114/pkg.vhdl | 1 | 147 | package pkg is
procedure say_hello;
end pkg;
package body pkg is
procedure say_hello is
begin
report "Hello";
end say_hello;
end pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1082/tb_test.vhdl | 1 | 429 | entity tb_test is
end tb_test;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_test is
signal a : std_logic_vector (31 downto 0) := (others => '0');
signal b : std_logic_vector (31 downto 0);
begin
dut: entity work.test
port map (a_in => a, b_out => b);
process
begin
a <= x"0000_0003";
wait for 1 ns;
assert b = x"0000_0007" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc503.vhd | 4 | 2114 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc503.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p03n01i00503ent IS
END c03s02b02x00p03n01i00503ent;
ARCHITECTURE c03s02b02x00p03n01i00503arch OF c03s02b02x00p03n01i00503ent IS
type R2 is record
R11,R12 : INTEGER;
R21,R22,R23 : BOOLEAN;
end record;
BEGIN
TESTING: PROCESS
variable k : R2;
BEGIN
k.R11 := 1;
k.R12 := 2;
k.R21 := true;
k.R22 := false;
k.R23 := true;
wait for 2 ns;
assert NOT(k.R11=1 and k.R12=2 and k.R21=true and k.R22=false and k.R23=true)
report "***PASSED TEST: c03s02b02x00p03n01i00503"
severity NOTE;
assert (k.R11=1 and k.R12=2 and k.R21=true and k.R22=false and k.R23=true)
report "***FAILED TEST: c03s02b02x00p03n01i00503 - A multiple object declaration is equivalent to a sequence of the corresponding number of single object declarations."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p03n01i00503arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_03.vhd | 4 | 1975 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
architecture test of inline_03 is
begin
process_1_c : process is
type mode_type is (immediate, other_mode);
type opcode_type is (load, add, subtract, other_opcode);
variable mode : mode_type;
variable opcode : opcode_type;
constant immed_operand : integer := 1;
constant memory_operand : integer := 2;
constant address_operand : integer := 3;
variable operand : integer;
procedure procedure_1_c is
begin
-- code from book:
if mode = immediate then
operand := immed_operand;
elsif opcode = load or opcode = add or opcode = subtract then
operand := memory_operand;
else
operand := address_operand;
end if;
-- end of code from book
end procedure_1_c;
begin
mode := immediate;
procedure_1_c;
mode := other_mode;
opcode := load;
procedure_1_c;
opcode := add;
procedure_1_c;
opcode := subtract;
procedure_1_c;
opcode := other_opcode;
procedure_1_c;
wait;
end process process_1_c;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2409.vhd | 4 | 1667 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2409.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n05i02409ent IS
END c07s03b02x00p08n05i02409ent;
ARCHITECTURE c07s03b02x00p08n05i02409arch OF c07s03b02x00p08n05i02409ent IS
signal err : bit_vector(0 to 2);
BEGIN
TESTING: PROCESS
BEGIN
err <= (1 => '1', others => '0', others => '1');
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s03b02x00p08n05i02409 - Only one others association is allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n05i02409arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_02.vhd | 4 | 2897 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ap_a_02 is
end entity ap_a_02;
library ieee; use ieee.std_logic_1164.all;
architecture test of ap_a_02 is
-- code from book
-- end code from book
begin
b1 : block is
signal sulv : std_ulogic_vector(7 downto 0);
signal slv : std_logic_vector(7 downto 0);
begin
-- code from book
sulv <= To_stdulogicvector ( slv );
-- end code from book
slv <= "10101010";
end block b1;
b2 : block is
signal sulv : std_ulogic_vector(7 downto 0);
signal slv : std_logic_vector(7 downto 0);
begin
-- code from book
slv <= To_stdlogicvector ( sulv );
-- end code from book
sulv <= "00001111";
end block b2;
b3 : block is
signal a, ena, y : std_logic;
begin
-- code from book
y <= a when ena = '1' else
'Z';
-- end code from book
ena <= '0', '1' after 20 ns, '0' after 40 ns;
a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;
end block b3;
b4 : block is
signal a, ena, y : std_logic;
begin
-- code from book
y <= a when ena = '1' else
'H';
-- end code from book
ena <= '0', '1' after 20 ns, '0' after 40 ns;
a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;
end block b4;
b5 : block is
signal a, b, x, s, y : std_logic;
begin
-- code from book
y <= a when x = '1' else
b when s = '1' else
'-';
-- end code from book
x <= '0', '1' after 20 ns, '0' after 40 ns;
s <= '0', '1' after 60 ns, '0' after 80 ns;
a <= '0', '1' after 10 ns, '0' after 30 ns,
'1' after 50 ns, '0' after 70 ns,
'1' after 90 ns;
b <= '0', '1' after 15 ns, '0' after 35 ns,
'1' after 55 ns, '0' after 75 ns,
'1' after 95 ns;
end block b5;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/record-types/simple-integer-record.vhdl | 4 | 541 | entity test is
end test;
architecture only of test is
begin -- only
p: process
type integerRecord is record
foo : integer;
bar : integer;
end record;
variable myRecord : integerRecord;
begin -- process p
myRecord.foo := 0;
myRecord.bar := 1;
assert myRecord.foo = 0 report "TEST FAILED" severity FAILURE;
assert myRecord.bar = 1 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2328.vhd | 4 | 1680 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2328.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02328ent IS
END c07s02b07x00p02n02i02328ent;
ARCHITECTURE c07s02b07x00p02n02i02328arch OF c07s02b07x00p02n02i02328ent IS
BEGIN
TESTING: PROCESS
constant x : real := 4.5;
constant y : integer := 5;
variable z : integer;
BEGIN
z := y**x; -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02328 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02328arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/case01/case03.vhdl | 1 | 236 | library ieee;
use ieee.std_logic_1164.all;
entity case03 is
port (a : std_logic_vector (4 downto 0);
o : out std_logic);
end case03;
architecture behav of case03 is
begin
with a select o <=
'0' when others;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_21.vhd | 4 | 1991 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_21.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity full_adder is
port ( a, b, c_in : bit; s, c_out : out bit );
end entity full_adder;
architecture truth_table of full_adder is
begin
with bit_vector'(a, b, c_in) select
(c_out, s) <= bit_vector'("00") when "000",
bit_vector'("01") when "001",
bit_vector'("01") when "010",
bit_vector'("10") when "011",
bit_vector'("01") when "100",
bit_vector'("10") when "101",
bit_vector'("10") when "110",
bit_vector'("11") when "111";
end architecture truth_table;
-- not in book
entity fg_05_21 is
end entity fg_05_21;
library stimulus;
use stimulus.stimulus_generators.all;
architecture test of fg_05_21 is
signal a, b, c_in, s, c_out : bit;
signal test_vector : bit_vector(1 to 3);
begin
dut : entity work.full_adder
port map ( a => a, b => b, c_in => c_in, s => s, c_out => c_out );
all_possible_values ( test_vector, 10 ns );
(a, b, c_in) <= test_vector;
end architecture test;
-- end not in book
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3181.vhd | 4 | 1914 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3181.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p85n01i03181ent IS
END c14s01b00x00p85n01i03181ent;
ARCHITECTURE c14s01b00x00p85n01i03181arch OF c14s01b00x00p85n01i03181ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'rightof(0) = 1 and
roufbit'leftof(0) = 1 )
report "***PASSED TEST: c14s01b00x00p85n01i03181"
severity NOTE;
assert ( fourbit'rightof(0) = 1 and
roufbit'leftof(0) = 1 )
report "***FAILED TEST: c14s01b00x00p85n01i03181 - Predefined attribute RIGHTOF for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p85n01i03181arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/vector.d/cmp_176.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_176 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_176;
architecture augh of cmp_176 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue1057/pkg2.vhdl | 1 | 184 | -- Enum literals should be made implicitly visible here
use work.pkg.alias_t;
package pkg2 is
-- Fails with no declaration for "alpha"
constant c : alias_t := alpha;
end package;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1918.vhd | 4 | 1754 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1918.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01918ent IS
END c07s02b01x00p01n01i01918ent;
ARCHITECTURE c07s02b01x00p01n01i01918arch OF c07s02b01x00p01n01i01918ent IS
BEGIN
TESTING: PROCESS
variable b1 : bit := '0';
BEGIN
b1 := b1 xor b1;
assert NOT(b1 = '0')
report "***PASSED TEST: c07s02b01x00p01n01i01918"
severity NOTE;
assert (b1 = '0')
report "***FAILED TEST: c07s02b01x00p01n01i01918 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01918arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1253/repro2.vhdl | 1 | 487 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity repro1 is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end repro1;
architecture archi of repro1 is
signal tmp: signed(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= 1 + tmp;
end if;
end process;
Q <= std_logic_vector(tmp);
end archi;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat-b.vhd | 4 | 31770 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_10_bvat-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use std.textio.all, bv_utilities.bv_arithmetic.all;
architecture bench of bv_test is
begin
process is
variable L : line;
variable byte : bit_vector(0 to 7);
variable word : bit_vector(1 to 32);
variable half_byte : bit_vector(1 to 4);
variable overflow, div_by_zero, result : boolean;
begin
wait for 1 ns;
----------------------------------------------------------------
----------------------------------------------------------------
-- test bit_vector to numeric conversions
----------------------------------------------------------------
----------------------------------------------------------------
write(L, string'("Testing bv_to_natural:"));
writeline(output, L);
write(L, string'(" bv_to_natural(X""02"") = "));
write(L, bv_to_natural(X"02"));
writeline(output, L);
assert bv_to_natural(X"02") = 2;
write(L, string'(" bv_to_natural(X""FE"") = "));
write(L, bv_to_natural(X"FE"));
writeline(output, L);
assert bv_to_natural(X"FE") = 254;
----------------------------------------------------------------
write(L, string'("Testing natural_to_bv:"));
writeline(output, L);
write(L, string'(" natural_to_bv(2) = "));
write(L, natural_to_bv(2, 8));
writeline(output, L);
assert natural_to_bv(2, 8) = X"02";
write(L, string'(" natural_to_bv(254) = "));
write(L, natural_to_bv(254, 8));
writeline(output, L);
assert natural_to_bv(254, 8) = X"FE";
----------------------------------------------------------------
write(L, string'("Testing bv_to_integer:"));
writeline(output, L);
write(L, string'(" bv_to_integer(X""02"") = "));
write(L, bv_to_integer(X"02"));
writeline(output, L);
assert bv_to_integer(X"02") = 2;
write(L, string'(" bv_to_integer(X""FE"") = "));
write(L, bv_to_integer(X"FE"));
writeline(output, L);
assert bv_to_integer(X"FE") = -2;
----------------------------------------------------------------
write(L, string'("Testing integer_to_bv:"));
writeline(output, L);
write(L, string'(" integer_to_bv(2) = "));
write(L, integer_to_bv(2, 8));
writeline(output, L);
assert integer_to_bv(2, 8) = X"02";
write(L, string'(" integer_to_bv(-2) = "));
write(L, integer_to_bv(-2, 8));
writeline(output, L);
assert integer_to_bv(-2, 8) = X"FE";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic operations
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_add: Signed addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_add with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_add(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 2+(-3) = "));
bv_add(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FF" and not overflow;
write(L, string'(" 64+64 = "));
bv_add(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64+(-64) = "));
bv_add(X"C0", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "+": Signed addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""+"" without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
byte := X"02" + X"02";
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 2+(-3) = "));
byte := X"02" + X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"FF";
write(L, string'(" 64+64 = "));
byte := X"40" + X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64+(-64) = "));
byte := X"C0" + X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_sub: Signed subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sub with overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
bv_sub(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 2-(-3) = "));
bv_sub(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"05" and not overflow;
write(L, string'(" 64-(-64) = "));
bv_sub(X"40", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64-64 = "));
bv_sub(X"C0", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "-": Signed subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
byte := X"02" - X"02";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 2-(-3) = "));
byte := X"02" - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"05";
write(L, string'(" 64-(-64) = "));
byte := X"40" - X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64-64 = "));
byte := X"C0" - X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_addu: Unsigned addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_addu(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 64+64 = "));
bv_addu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 128+128 = "));
bv_addu(X"80", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_addu: Unsigned addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
byte := bv_addu(X"02", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 64+64 = "));
byte := bv_addu(X"40", X"40");
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 128+128 = "));
byte := bv_addu(X"80", X"80");
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu with overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
bv_subu(X"03", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"01" and not overflow;
write(L, string'(" 64-64 = "));
bv_subu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 64-128 = "));
bv_subu(X"40", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"C0" and overflow;
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu without overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
byte := bv_subu(X"03", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 64-64 = "));
byte := bv_subu(X"40", X"40");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 64-128 = "));
byte := bv_subu(X"40", X"80");
write(L, byte);
writeline(output, L);
assert byte = X"C0";
----------------------------------------------------------------
-- bv_neg: Signed negation with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_neg with overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
bv_neg(X"03", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not overflow;
write(L, string'(" -(-3) = "));
bv_neg(X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not overflow;
write(L, string'(" -(127) = "));
bv_neg(X"7F", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"81" and not overflow;
write(L, string'(" -(-128) = "));
bv_neg(X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
----------------------------------------------------------------
-- "-": Signed negation without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
byte := - X"03";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -(-3) = "));
byte := - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -(127) = "));
byte := - X"7F";
write(L, byte);
writeline(output, L);
assert byte = X"81";
write(L, string'(" -(-128) = "));
byte := - X"80";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_mult: Signed multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_mult with overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
bv_mult(X"05", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"F1" and not overflow;
write(L, string'(" (-5)*(-3) = "));
bv_mult(X"FB", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"0F" and not overflow;
write(L, string'(" 16*8 = "));
bv_mult(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" 16*16 = "));
bv_mult(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
write(L, string'(" 16*(-8) = "));
bv_mult(X"10", X"F8", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*(-16) = "));
bv_mult(X"10", X"F0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- "*": Signed multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""*"" without overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
byte := X"05" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"F1";
write(L, string'(" (-5)*(-3) = "));
byte := X"FB" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"0F";
write(L, string'(" 16*8 = "));
byte := X"10" * X"08";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
byte := X"10" * X"10";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 16*(-8) = "));
byte := X"10" * X"F8";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*(-16) = "));
byte := X"10" * X"F0";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu with overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
bv_multu(X"05", X"07", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"23" and not overflow;
write(L, string'(" 16*8 = "));
bv_multu(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*16 = "));
bv_multu(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu without overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
byte := bv_multu(X"05", X"07");
write(L, byte);
writeline(output, L);
assert byte = X"23";
write(L, string'(" 16*8 = "));
byte := bv_multu(X"10", X"08");
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
byte := bv_multu(X"10", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_div: Signed division with divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_div with flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_div(X"07", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -7/2 = "));
bv_div(X"F9", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" 7/-2 = "));
bv_div(X"07", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" -7/-2 = "));
bv_div(X"F9", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -128/1 = "));
bv_div(X"80", X"01", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and not overflow;
write(L, string'(" -128/-1 = "));
bv_div(X"80", X"FF", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and overflow;
write(L, string'(" -16/0 = "));
bv_div(X"F0", X"00", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and div_by_zero and not overflow;
----------------------------------------------------------------
-- "/": Signed division without divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""/"" without flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
byte := X"07" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -7/2 = "));
byte := X"F9" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" 7/-2 = "));
byte := X"07" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -7/-2 = "));
byte := X"F9" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -128/1 = "));
byte := X"80" / X"01";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -128/-1 = "));
byte := X"80" / X"FF";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -16/0 = "));
byte := X"F0" / X"00";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_divu: Unsigned division with divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu with flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_divu(X"07", X"02", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"03" and not div_by_zero;
write(L, string'(" 14/7 = "));
bv_divu(X"0E", X"07", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"02" and not div_by_zero;
write(L, string'(" 16/1 = "));
bv_divu(X"10", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and not div_by_zero;
write(L, string'(" 16/0 = "));
bv_divu(X"10", X"00", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and div_by_zero;
write(L, string'(" 16/16 = "));
bv_divu(X"10", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"01" and not div_by_zero;
write(L, string'(" 1/16 = "));
bv_divu(X"01", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"00" and not div_by_zero;
write(L, string'(" 255/1 = "));
bv_divu(X"FF", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"FF" and not div_by_zero;
----------------------------------------------------------------
-- bv_divu: Unsigned division without divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu without flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
byte := bv_divu(X"07", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" 14/7 = "));
byte := bv_divu(X"0E", X"07");
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" 16/1 = "));
byte := bv_divu(X"10", X"01");
write(L, byte);
writeline(output, L);
assert byte = X"10";
write(L, string'(" 16/0 = "));
byte := bv_divu(X"10", X"00");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 16/16 = "));
byte := bv_divu(X"10", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 1/16 = "));
byte := bv_divu(X"01", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 255/1 = "));
byte := bv_divu(X"FF", X"01");
write(L, byte);
writeline(output, L);
assert byte = X"FF";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic comparison operators.
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_lt: Signed less than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_lt:"));
writeline(output, L);
write(L, string'(" 2 < 2 = "));
result := bv_lt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 2 < 3 = "));
result := bv_lt(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 < 2 = "));
result := bv_lt(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 < -3 = "));
result := bv_lt(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_le: Signed less than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_le:"));
writeline(output, L);
write(L, string'(" 2 <= 2 = "));
result := bv_le(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= 3 = "));
result := bv_le(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 <= 2 = "));
result := bv_le(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= -3 = "));
result := bv_le(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_gt: Signed greater than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_gt:"));
writeline(output, L);
write(L, string'(" 2 > 2 = "));
result := bv_gt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 3 > 2 = "));
result := bv_gt(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 > -2 = "));
result := bv_gt(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 > 2 = "));
result := bv_gt(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_ge: Signed greater than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_ge:"));
writeline(output, L);
write(L, string'(" 2 >= 2 = "));
result := bv_ge(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 3 >= 2 = "));
result := bv_ge(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 >= -2 = "));
result := bv_ge(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 >= 2 = "));
result := bv_ge(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
----------------------------------------------------------------
-- Extension operators - convert a bit vector to a longer one
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_sext: Sign extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sext:"));
writeline(output, L);
write(L, string'(" sext(X""02"", 32) = "));
word := bv_sext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" sext(X""FE"", 32) = "));
word := bv_sext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"FFFFFFFE";
write(L, string'(" sext(X""02"", 8) = "));
byte := bv_sext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" sext(X""FE"", 8) = "));
byte := bv_sext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" sext(X""02"", 4) = "));
half_byte := bv_sext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" sext(X""FE"", 4) = "));
half_byte := bv_sext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
----------------------------------------------------------------
-- bv_zext" Zero extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_zext:"));
writeline(output, L);
write(L, string'(" zext(X""02"", 32) = "));
word := bv_zext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" zext(X""FE"", 32) = "));
word := bv_zext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"000000FE";
write(L, string'(" zext(X""02"", 8) = "));
byte := bv_zext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" zext(X""FE"", 8) = "));
byte := bv_zext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" zext(X""02"", 4) = "));
half_byte := bv_zext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" zext(X""FE"", 4) = "));
half_byte := bv_zext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
wait;
end process;
end architecture bench;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug01/repro.vhdl | 3 | 243 | entity repro is
end repro;
architecture behav of repro is
begin -- behav
process
variable v : integer := 523;
variable a : integer := 2;
begin
assert false report integer'image(v)(a);
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/add_420.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_420 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_420;
architecture augh of add_420 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue476/repro/pixel_pkg.vhd | 1 | 916 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pixel_pkg is
generic(
NBITS : natural;
NBR_OF_CHROMA : natural
);
subtype CHROMA is unsigned(NBITS-1 downto 0);
type TYPE_PIXEL is array (NBR_OF_CHROMA-1 downto 0) of CHROMA;
function std_logic_vector_to_pixel
(in_vector : in std_logic_vector(NBR_OF_CHROMA*NBITS-1 downto 0))
return TYPE_PIXEL;
end package pixel_pkg;
package body pixel_pkg is
function std_logic_vector_to_pixel
( in_vector : in std_logic_vector(NBR_OF_CHROMA*NBITS-1 downto 0))
return TYPE_PIXEL is
variable pixel : TYPE_PIXEL;
begin
for chroma in 0 to NBR_OF_CHROMA -1 loop
pixel(chroma) := unsigned(in_vector((chroma+1)*NBITS-1 downto chroma*NBITS));
end loop;
return pixel;
end function std_logic_vector_to_pixel;
end package body pixel_pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1601.vhd | 4 | 2140 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1601.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01601ent IS
END c08s11b00x00p03n01i01601ent;
ARCHITECTURE c08s11b00x00p03n01i01601arch OF c08s11b00x00p03n01i01601ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
variable counter : integer := 0;
BEGIN
L1 :
for i in boolean loop
L2 :
for j in 1 to 3 loop
exit L2 ;
p := 5 ;
end loop L2 ;
counter := counter + 1 ;
end loop L1 ;
assert NOT((p=0)and(counter=(boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1)))
report "***PASSED TEST: c08s11b00x00p03n01i01601"
severity NOTE;
assert ((p=0)and(counter=(boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1)))
report "***FAILED TEST: c08s11b00x00p03n01i01601 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01601arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue1229/tb.vhdl | 1 | 330 | entity tb is
end entity tb;
architecture RTL of tb is
package tbpkg is new work.pkg generic map (N => 3);
begin
process
use tbpkg.all;
variable int : integer := c_int;
begin
report tbpkg.c_int'foreign;
showPackageN;
report "C Int: " & integer'image(int);
wait;
end process;
end architecture RTL;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2365.vhd | 4 | 1765 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2365.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b01x00p01n01i02365ent IS
END c07s03b01x00p01n01i02365ent;
ARCHITECTURE c07s03b01x00p01n01i02365arch OF c07s03b01x00p01n01i02365ent IS
type MVL is ('0','1','X','Z') ;
signal S2 : MVL := '0';
BEGIN
TESTING: PROCESS
BEGIN
S2 <= 'X';
wait for 1 ns;
assert NOT(S2 = 'X')
report "***PASSED TEST: c07s03b01x00p01n01i02365"
severity NOTE;
assert (S2 = 'X')
report "***FAILED TEST: c07s03b01x00p01n01i02365 - A literal is an enumeration literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b01x00p01n01i02365arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1975.vhd | 4 | 3532 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1975.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01975ent IS
constant T:bit := '1';
constant F:bit := '0';
END c07s02b01x00p02n02i01975ent;
ARCHITECTURE c07s02b01x00p02n02i01975arch OF c07s02b01x00p02n02i01975ent IS
BEGIN
TESTING: PROCESS
variable A1 : bit := T;
variable A2 : bit := F;
BEGIN
assert NOT( (A1 and A1) = '1' and
(A1 and A2) = '0' and
(A2 and A1) = '0' and
(A2 and A2) = '0' and
(A1 or A1) = '1' and
(A1 or A2) = '1' and
(A2 or A1) = '1' and
(A2 or A2) = '0' and
(A1 xor A1) = '0' and
(A1 xor A2) = '1' and
(A2 xor A1) = '1' and
(A2 xor A2) = '0' and
(A1 nand A1) = '0' and
(A1 nand A2) = '1' and
(A2 nand A1) = '1' and
(A2 nand A2) = '1' and
(A1 nor A1) = '0' and
(A1 nor A2) = '0' and
(A2 nor A1) = '0' and
(A2 nor A2) = '1' and
(not A1) = '0' and
(not A2) = '1')
report "***PASSED TEST: c07s02b01x00p02n02i01975"
severity NOTE;
assert ( (A1 and A1) = '1' and
(A1 and A2) = '0' and
(A2 and A1) = '0' and
(A2 and A2) = '0' and
(A1 or A1) = '1' and
(A1 or A2) = '1' and
(A2 or A1) = '1' and
(A2 or A2) = '0' and
(A1 xor A1) = '0' and
(A1 xor A2) = '1' and
(A2 xor A1) = '1' and
(A2 xor A2) = '0' and
(A1 nand A1) = '0' and
(A1 nand A2) = '1' and
(A2 nand A1) = '1' and
(A2 nand A2) = '1' and
(A1 nor A1) = '0' and
(A1 nor A2) = '0' and
(A2 nor A1) = '0' and
(A2 nor A2) = '1' and
(not A1) = '0' and
(not A2) = '1')
report "***FAILED TEST: c07s02b01x00p02n02i01975 - BIT type truth table test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01975arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1244/ram_protected_sharedvar.vhd | 1 | 2716 | --
-- Dual-Port Block RAM with Two Write Ports
-- Modelization with a protected shared variable
-- Simulates without warning in VHDL-2002 simulators
--
-- Download: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip
-- File: HDL_Coding_Techniques/rams/ram_protected_sharedvar.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package ram_pkg is
subtype data_type is std_logic_vector(15 downto 0);
type ram_type is protected
procedure write (
addr : std_logic_vector(6 downto 0);
data : data_type);
impure function read (
addr : std_logic_vector(6 downto 0))
return data_type;
end protected ram_type;
end ram_pkg;
package body ram_pkg is
type ram_array is array(0 to 127) of data_type;
type ram_type is protected body
variable ram : ram_array;
procedure write (
addr : std_logic_vector(6 downto 0);
data : data_type) is
begin
ram(conv_integer(addr)) := data;
end procedure write;
impure function read (
addr : std_logic_vector(6 downto 0))
return data_type is
begin
return ram(conv_integer(addr));
end function read;
end protected body ram_type;
end ram_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_pkg.all;
entity ram_protected_sharedvar is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 7
);
port(
clka : in std_logic;
clkb : in std_logic;
ena : in std_logic;
enb : in std_logic;
wea : in std_logic;
web : in std_logic;
addra : in std_logic_vector(ADDR_WIDTH-1 downto 0);
addrb : in std_logic_vector(ADDR_WIDTH-1 downto 0);
dia : in std_logic_vector(DATA_WIDTH-1 downto 0);
dib : in std_logic_vector(DATA_WIDTH-1 downto 0);
doa : out std_logic_vector(DATA_WIDTH-1 downto 0);
dob : out std_logic_vector(DATA_WIDTH-1 downto 0));
end ram_protected_sharedvar;
architecture behavioral of ram_protected_sharedvar is
shared variable RAM : ram_type;
begin
process (CLKA)
begin
if rising_edge(clka) then
if ENA = '1' then
doa <= RAM.read(addra);
if WEA = '1' then
RAM.write(addra, dia);
end if;
end if;
end if;
end process;
process (CLKB)
begin
if rising_edge(clkb) then
if ENB = '1' then
dob <= RAM.read(addrb);
if WEB = '1' then
RAM.write(addrb, dib);
end if;
end if;
end if;
end process;
end behavioral;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd | 4 | 1595 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
architecture functional of S_R_flipflop is
begin
q <= '1' when s = '1' else
'0' when r = '1';
q_n <= '0' when s = '1' else
'1' when r = '1';
end architecture functional;
entity tb_S_R_flipflop is
end entity tb_S_R_flipflop;
architecture test of tb_S_R_flipflop is
signal s, r : bit := '0';
signal q, q_n : bit;
begin
dut : entity work.S_R_flipflop(functional)
port map ( s => s, r => r, q => q, q_n => q_n );
stimulus : process is
begin
wait for 10 ns;
s <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '1'; wait for 10 ns;
r <= '0'; wait for 10 ns;
s <= '1'; wait for 10 ns;
r <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm.vhd | 4 | 1390 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_regm.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.dlx_types.all;
entity reg_multiple_out is
generic ( num_outputs : positive;
Tpd : delay_length );
port ( d : in dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs) );
end entity reg_multiple_out;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_02.vhd | 4 | 1852 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_12_ch_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book
entity reg is
port ( d : in bit_vector; q : out bit_vector; -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end entity reg;
-- end code from book
architecture test of reg is
begin
q <= d;
end architecture test;
entity ch_12_02 is
end entity ch_12_02;
----------------------------------------------------------------
architecture test of ch_12_02 is
-- code from book
signal small_data : bit_vector(0 to 7);
signal large_data : bit_vector(0 to 15);
-- . . .
-- end code from book
begin
-- code from book
problem_reg : entity work.reg
port map ( d => small_data, q => large_data, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- end code from book
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue332/irqc_pif_pkg.vhd | 1 | 4647 | --========================================================================================================================
-- Copyright (c) 2016 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_pif_pkg
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package irqc_pif_pkg is
-- Change this to a generic when generic in packages is allowed (VHDL 2008)
constant C_NUM_SOURCES : integer := 6; -- 1 <= C_NUM_SOURCES <= Data width
-- Notation for regs: (Included in constant name as info to SW)
-- - RW: Readable and writable reg.
-- - RO: Read only reg. (output from IP)
-- - WO: Write only reg. (typically single cycle strobe to IP)
-- Notation for signals (or fields in record) going between PIF and core:
-- Same notations as for register-constants above, but
-- a preceeding 'a' (e.g. awo) means the register is auxiliary to the PIF.
-- This means no flop in the PIF, but in the core. (Or just a dummy-register with no flop)
constant C_ADDR_IRR : integer := 0;
constant C_ADDR_IER : integer := 1;
constant C_ADDR_ITR : integer := 2;
constant C_ADDR_ICR : integer := 3;
constant C_ADDR_IPR : integer := 4;
constant C_ADDR_IRQ2CPU_ENA : integer := 5;
constant C_ADDR_IRQ2CPU_DISABLE : integer := 6;
constant C_ADDR_IRQ2CPU_ALLOWED : integer := 7;
-- Signals from pif to core
type t_p2c is record
rw_ier : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_itr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_icr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_irq2cpu_ena : std_logic;
awt_irq2cpu_disable : std_logic;
end record t_p2c;
-- Signals from core to PIF
type t_c2p is record
aro_irr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_ipr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_irq2cpu_allowed : std_logic;
end record t_c2p;
type t_sbi_if is record
cs : std_logic; -- to dut
addr : unsigned; -- to dut
rd : std_logic; -- to dut
wr : std_logic; -- to dut
wdata : std_logic_vector; -- to dut
ready : std_logic; -- from dut
rdata : std_logic_vector; -- from dut
end record;
------------------------------------------
-- init_sbi_if_signals
------------------------------------------
-- - This function returns an SBI interface with initialized signals.
-- - All SBI input signals are initialized to 0
-- - All SBI output signals are initialized to Z
function init_sbi_if_signals(
addr_width : natural;
data_width : natural
) return t_sbi_if;
end package irqc_pif_pkg;
package body irqc_pif_pkg is
---------------------------------------------------------------------------------
-- initialize sbi to dut signals
---------------------------------------------------------------------------------
function init_sbi_if_signals(
addr_width : natural;
data_width : natural
) return t_sbi_if is
variable result : t_sbi_if( addr(addr_width - 1 downto 0),
wdata(data_width - 1 downto 0),
rdata(data_width - 1 downto 0));
begin
result.cs := '0';
result.rd := '0';
result.wr := '0';
result.addr := (others => '0');
result.wdata := (others => '0');
result.ready := 'Z';
result.rdata := (others => 'Z');
return result;
end function;
end package body irqc_pif_pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/DC_Motor.vhd | 4 | 1669 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed;
use ieee_proposed.mechanical_systems.all;
use ieee_proposed.electrical_systems.all;
entity DC_Motor is
generic ( r_wind : resistance; -- motor winding resistance [ohm]
kt : real; -- torque coefficient [N*m/amp]
l : inductance; -- winding inductance [henrys]
d : real; -- damping coefficient [N*m/(rad/sec)]
j : mmoment_i ); -- moment of inertia [kg*meter**2]
port ( terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
----------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0 * kt * i + d * w + j * w'dot;
v == kt * w + i * r_wind + l * i'dot;
end architecture basic;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/mem2d01/dpram1r.vhdl | 1 | 600 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram1r is
port (raddr : natural range 0 to 3;
rbit : natural range 0 to 7;
rdat : out std_logic;
waddr : natural range 0 to 3;
wdat : std_logic_vector (7 downto 0);
clk : std_logic);
end dpram1r;
architecture behav of dpram1r is
type memtype is array (0 to 3) of std_logic_vector (7 downto 0);
signal mem : memtype;
begin
process (clk)
begin
if rising_edge (clk) then
rdat <= mem (raddr)(rbit);
mem (waddr) <= wdat;
end if;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_15.vhd | 4 | 2213 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_15.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity circuit is
generic ( inpad_delay, outpad_delay : delay_length );
port ( in1, in2, in3 : in bit; out1, out2 : out bit );
end entity circuit;
--------------------------------------------------
architecture with_pad_delays of circuit is
component subcircuit is
port ( a, b : in bit; y1, y2 : out bit );
end component subcircuit;
signal delayed_in1, delayed_in2, delayed_in3 : bit;
signal undelayed_out1, undelayed_out2 : bit;
begin
input_delays : block is
begin
delayed_in1 <= in1 after inpad_delay;
delayed_in2 <= in2 after inpad_delay;
delayed_in3 <= in3 after inpad_delay;
end block input_delays;
functionality : block is
signal intermediate : bit;
begin
cell1 : component subcircuit
port map ( delayed_in1, delayed_in2, undelayed_out1, intermediate );
cell2 : component subcircuit
port map ( intermediate, delayed_in3, undelayed_out2, open );
end block functionality;
output_delays : block is
begin
out1 <= undelayed_out1 after outpad_delay;
out2 <= undelayed_out2 after outpad_delay;
end block output_delays;
end architecture with_pad_delays;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1095/top.vhdl | 1 | 892 | library ieee;
use ieee.std_logic_1164.all;
entity xor_gate is
generic (
INVERT : boolean
);
port (
a : in std_logic;
b : in std_logic;
q : out std_logic
);
end;
architecture a of xor_gate is
begin
gen: if INVERT generate
q <= not (a xor b);
else generate
q <= a xor b;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
x : in std_logic;
y : in std_logic;
o_custom : out std_logic;
o_and : out std_logic
);
end;
architecture a of top is
component comp is
port (
a : in std_logic;
b : in std_logic;
q : out std_logic
);
end component;
begin
comp_inst: comp
port map (
a => x,
b => y,
q => o_custom
);
o_and <= x and y;
end;
configuration conf of top is
for a
for comp_inst : comp
use entity work.xor_gate
generic map (
INVERT => false
);
end for;
end for;
end configuration;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc925.vhd | 4 | 1878 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc925.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p22n01i00925ent IS
END c10s03b00x00p22n01i00925ent;
ARCHITECTURE c10s03b00x00p22n01i00925arch OF c10s03b00x00p22n01i00925ent IS
constant x : integer := 3;
procedure xxx is
constant x : integer := 5;
variable y : bit;
begin
if x > 3 then
y := '1';
else
y := '0';
end if;
assert NOT( y='1' )
report "***PASSED TEST: c10s03b00x00p22n01i00925"
severity NOTE;
assert ( y='1' )
report "***FAILED TEST: c10s03b00x00p22n01i00925 - Within the specification of a subprogram, every declaration with the same designator as the sybprogram is hidden."
severity ERROR;
end xxx;
BEGIN
xxx;
END c10s03b00x00p22n01i00925arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc599.vhd | 4 | 2027 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc599.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00599ent IS
END c03s04b01x00p01n01i00599ent;
ARCHITECTURE c03s04b01x00p01n01i00599arch OF c03s04b01x00p01n01i00599ent IS
type time_vector is array (natural range <>) of time;
type time_vector_file is file of time_vector;
BEGIN
TESTING: PROCESS
file filein : time_vector_file open write_mode is "iofile.27";
BEGIN
for i in 1 to 100 loop
write(filein,(1 ns,2 ns,3 ns,4 ns));
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00599 - The output file will be verified by test s010232.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00599arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2428.vhd | 4 | 1945 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2428.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n03i02428ent IS
END c07s03b02x01p01n03i02428ent;
ARCHITECTURE c07s03b02x01p01n03i02428arch OF c07s03b02x01p01n03i02428ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : real;
ele_2 : real;
end record;
constant p :rec := (ele_1 | ele_2 => 4.5); -- No_failure_here
BEGIN
assert NOT(p.ele_1=4.5 and p.ele_2=4.5)
report "***PASSED TEST: c07s03b02x01p01n03i02428"
severity NOTE;
assert (p.ele_1=4.5 and p.ele_2=4.5)
report "***FAILED TEST: c07s03b02x01p01n03i02428 - Element association with others choice should be used to represent elements of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n03i02428arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/sync_ram.vhd | 4 | 980 | -- Simple generic RAM Model
--
-- +-----------------------------+
-- | Copyright 2008 DOULOS |
-- | designer : JK |
-- +-----------------------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_ram is
port (
clock : in std_logic;
we : in std_logic;
address : in std_logic_vector;
datain : in std_logic_vector;
dataout : out std_logic_vector
);
end entity sync_ram;
architecture rtl of sync_ram is
type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range);
signal ram : ram_type;
signal read_address : std_logic_vector(address'range);
begin
ramproc: process(clock) is
begin
if rising_edge(clock) then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
end if;
read_address <= address;
end if;
end process ramproc;
dataout <= ram(to_integer(unsigned(read_address)));
end architecture rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2661.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2661.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02661ent IS
END c13s03b01x00p02n01i02661ent;
ARCHITECTURE c13s03b01x00p02n01i02661arch OF c13s03b01x00p02n01i02661ent IS
BEGIN
TESTING: PROCESS
variable |k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02661 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02661arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1287.vhd | 4 | 1634 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1287.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01287ent IS
END c08s04b00x00p04n01i01287ent;
ARCHITECTURE c08s04b00x00p04n01i01287arch OF c08s04b00x00p04n01i01287ent IS
signal S1 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
unk <= transport '1' after 10 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01287 - Target of signal assignment statement is not a signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01287arch;
| gpl-2.0 |
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