repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc632.vhd | 4 | 2083 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc632.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:48 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00632ent IS
END c03s04b01x00p01n01i00632ent;
ARCHITECTURE c03s04b01x00p01n01i00632arch OF c03s04b01x00p01n01i00632ent IS
type four_value is ('Z','0','1','X');
subtype binary is four_value range '0' to '1';
type binary_file is file of binary;
constant C38 : binary := '0';
BEGIN
TESTING: PROCESS
file filein : binary_file open write_mode is "iofile.38";
BEGIN
for i in 1 to 100 loop
write(filein, C38);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00632 - The output file will be verified by test s010278.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00632arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2616.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2616.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02616ent IS
END c13s03b01x00p02n01i02616ent;
ARCHITECTURE c13s03b01x00p02n01i02616arch OF c13s03b01x00p02n01i02616ent IS
BEGIN
TESTING: PROCESS
variable k*k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02616 - Identifier can not contain '*'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02616arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2436.vhd | 4 | 2389 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2436.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n02i02436ent IS
END c07s03b02x02p01n02i02436ent;
ARCHITECTURE c07s03b02x02p01n02i02436arch OF c07s03b02x02p01n02i02436ent IS
BEGIN
TESTING: PROCESS
type BIT_VECTOR is array
(natural range <>, positive range <>) of BIT;
variable NUM1 : BIT_VECTOR(0 to 7, 1 to 2) := (
('0', '0'), ('1', '1'),
('0', '1'), ('1', '1'),
('0', '1'), ('0', '1'),
('1', '0'), ('1', '0')
);
-- No_failure_here
BEGIN
assert NOT( NUM1 =(('0', '0'), ('1', '1'),
('0', '1'), ('1', '1'),
('0', '1'), ('0', '1'),
('1', '0'), ('1', '0')))
report "***PASSED TEST: c07s03b02x02p01n02i02436"
severity NOTE;
assert ( NUM1 =(('0', '0'), ('1', '1'),
('0', '1'), ('1', '1'),
('0', '1'), ('0', '1'),
('1', '0'), ('1', '0')))
report "***FAILED TEST: c07s03b02x02p01n02i02436 - Multidimensional aggregates are allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n02i02436arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/PLL.vhd | 4 | 2460 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
library ieee; use ieee.math_real.all;
entity PLL is
generic ( Fp : real := 20.0e3; -- loop filter pole freq [Hz]
Fz : real := 1.0e6; -- loop filter zero freq [Hz]
Kv : real := 100.0e3; -- VCO gain [Hz/V]
Fc : real := 1.0e6 ); -- VCO center freq [Hz]
port ( terminal input, lf_out, vco_out : electrical );
end entity PLL;
----------------------------------------------------------------
architecture behavioral of PLL is
quantity v_in across input to electrical_ref;
quantity v_lf across i_lf through lf_out to electrical_ref;
quantity v_vco across i_vco through vco_out to electrical_ref;
-- internal quantities and constants
-- multiplier
quantity mult : real;
-- loop filter (Lag)
constant wp : real := math_2_pi * fp; -- pole freq in rad/s
constant wz : real := math_2_pi * fz; -- zero freq in rad/s
constant num : real_vector := (1.0, 1.0 / wz); -- numerator array
constant den : real_vector := (1.0, 1.0 / wp); -- denominator array
-- VCO
quantity phi : real; -- used in VCO equation
constant Kv_w : real := math_2_pi * Kv; -- change gain to (rad/s)/V
constant wc : real := math_2_pi * Fc; -- change freq to rad/s
begin
if domain = quiescent_domain use
phi == 0.0; -- initialize phi
else
phi'dot == wc + Kv_w * (v_lf); -- calculate VCO frequency
end use;
mult == v_in * v_vco; -- multiplier output
v_lf == mult'ltf(num, den); -- loop filter output
v_vco == cos(phi); -- VCO output
end architecture behavioral;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug035/arith_prng_tb.vhdl | 2 | 4840 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Pseudo-Random Number Generator (PRNG).
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- Automated testbench for PoC.arith_prng
-- The Pseudo-Random Number Generator is instantiated for 8 bits. The
-- output sequence is compared to 256 pre calculated values.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY PoC;
USE PoC.utils.ALL;
USE PoC.vectors.ALL;
USE PoC.strings.ALL;
USE PoC.simulation.ALL;
ENTITY arith_prng_tb IS
END;
ARCHITECTURE test OF arith_prng_tb IS
CONSTANT CLOCK_PERIOD_100MHZ : TIME := 10 ns;
CONSTANT COMPARE_LIST_8_BITS : T_SLVV_8(0 TO 255) := (
x"12", x"24", x"48", x"90", x"21", x"42", x"85", x"0A", x"14", x"28", x"51", x"A2", x"45", x"8B", x"17", x"2E",
x"5D", x"BB", x"77", x"EF", x"DE", x"BC", x"79", x"F2", x"E4", x"C9", x"93", x"27", x"4E", x"9C", x"38", x"70",
x"E1", x"C3", x"86", x"0C", x"18", x"31", x"63", x"C6", x"8C", x"19", x"33", x"67", x"CE", x"9D", x"3A", x"74",
x"E9", x"D2", x"A5", x"4B", x"96", x"2D", x"5B", x"B7", x"6E", x"DD", x"BA", x"75", x"EB", x"D6", x"AD", x"5A",
x"B5", x"6A", x"D5", x"AB", x"56", x"AC", x"58", x"B1", x"62", x"C4", x"88", x"11", x"22", x"44", x"89", x"13",
x"26", x"4C", x"98", x"30", x"61", x"C2", x"84", x"08", x"10", x"20", x"40", x"81", x"02", x"05", x"0B", x"16",
x"2C", x"59", x"B3", x"66", x"CC", x"99", x"32", x"65", x"CA", x"95", x"2B", x"57", x"AE", x"5C", x"B9", x"73",
x"E7", x"CF", x"9F", x"3E", x"7C", x"F8", x"F1", x"E2", x"C5", x"8A", x"15", x"2A", x"55", x"AA", x"54", x"A8",
x"50", x"A0", x"41", x"83", x"06", x"0D", x"1A", x"35", x"6B", x"D7", x"AF", x"5E", x"BD", x"7B", x"F6", x"EC",
x"D8", x"B0", x"60", x"C0", x"80", x"00", x"01", x"03", x"07", x"0F", x"1E", x"3D", x"7A", x"F4", x"E8", x"D0",
x"A1", x"43", x"87", x"0E", x"1C", x"39", x"72", x"E5", x"CB", x"97", x"2F", x"5F", x"BF", x"7F", x"FE", x"FD",
x"FB", x"F7", x"EE", x"DC", x"B8", x"71", x"E3", x"C7", x"8E", x"1D", x"3B", x"76", x"ED", x"DA", x"B4", x"68",
x"D1", x"A3", x"47", x"8F", x"1F", x"3F", x"7E", x"FC", x"F9", x"F3", x"E6", x"CD", x"9B", x"36", x"6D", x"DB",
x"B6", x"6C", x"D9", x"B2", x"64", x"C8", x"91", x"23", x"46", x"8D", x"1B", x"37", x"6F", x"DF", x"BE", x"7D",
x"FA", x"F5", x"EA", x"D4", x"A9", x"52", x"A4", x"49", x"92", x"25", x"4A", x"94", x"29", x"53", x"A6", x"4D",
x"9A", x"34", x"69", x"D3", x"A7", x"4F", x"9E", x"3C", x"78", x"F0", x"E0", x"C1", x"82", x"04", x"09", x"12"
);
SIGNAL SimStop : std_logic := '0';
SIGNAL Clock : STD_LOGIC := '1';
SIGNAL Reset : STD_LOGIC := '0';
SIGNAL Test_got : STD_LOGIC := '0';
SIGNAL PRNG_Value : T_SLV_8;
BEGIN
Clock <= Clock xnor SimStop after CLOCK_PERIOD_100MHZ / 2.0;
PROCESS
BEGIN
WAIT UNTIL rising_edge(Clock);
Reset <= '1';
WAIT UNTIL rising_edge(Clock);
Reset <= '0';
WAIT UNTIL rising_edge(Clock);
FOR I IN 0 TO 255 LOOP
Test_got <= '1';
WAIT UNTIL rising_edge(Clock);
tbAssert((PRNG_Value = COMPARE_LIST_8_BITS(I)), "I=" & integer'image(I) & " Value=" & raw_format_slv_hex(PRNG_Value) & " Expected=" & raw_format_slv_hex(COMPARE_LIST_8_BITS(I)));
END LOOP;
-- Report overall simulation result
tbPrintResult;
SimStop <= '1';
assert now < 3000 ns severity failure;
WAIT;
END PROCESS;
prng : entity PoC.arith_prng
generic map (
BITS => 8,
SEED => x"12"
)
port map (
clk => Clock,
rst => Reset, -- reset value to initial seed
got => Test_got, -- the current value has been got, and a new value should be calculated
val => PRNG_Value -- the pseudo-random number
);
END;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/case02/case02.vhdl | 1 | 347 | library ieee;
use ieee.std_logic_1164.all;
entity case02 is
port (a : std_logic_vector (1 downto 0);
o : out std_logic);
end case02;
architecture behav of case02 is
begin
process (a)
begin
case a(1 downto 0) is
when "01" =>
o <= '1';
when others =>
o <= '0';
end case;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug15993/testbench.vhdl | 3 | 2500 | -- Test Bench
-- inspired from http://ghdl.free.fr/ghdl/A-full-adder.html#A-full-adder
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
ENTITY add_tb IS
END add_tb;
-------------------------------------------------------------------------------
ARCHITECTURE behave OF add_tb IS
COMPONENT add4
GENERIC ( n : INTEGER := 4 );
PORT ( a, b : IN STD_LOGIC_VECTOR ( n-1 DOWNTO 0 );
cin : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR ( n DOWNTO 0 ) );
END COMPONENT;
FOR ALL: add4 USE ENTITY work.addern;
SIGNAL i0, i1 : STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
SIGNAL s : STD_LOGIC_VECTOR ( 4 DOWNTO 0 );
SIGNAL ci : STD_LOGIC;
BEGIN
adder0: add4
PORT MAP ( a => i0, b => i1, cin => ci, sum => s );
-- This process does the real job.
PROCESS
TYPE pattern_type IS RECORD
-- The inputs of the adder.
i0, i1 : STD_LOGIC_VECTOR( 3 DOWNTO 0 );
ci : STD_LOGIC;
-- The expected outputs of the adder.
s : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
END RECORD;
-- The patterns to apply.
TYPE pattern_array IS ARRAY (natural RANGE <>) OF pattern_type;
CONSTANT patterns : pattern_array :=
(("0000", "0000", '0', "00000"),
("0000", "0001", '0', "00001"),
("0001", "0000", '0', "00001"),
("0001", "0001", '0', "00010"),
("0001", "0001", '1', "00011"),
("0001", "0010", '0', "00011"),
("0001", "0010", '1', "00100"),
("0010", "0010", '0', "00100"));
BEGIN
-- Check each pattern.
FOR i IN patterns'RANGE LOOP
-- Set the inputs.
i0 <= patterns(i).i0;
i1 <= patterns(i).i1;
ci <= patterns(i).ci;
-- Wait for the results.
WAIT FOR 1 ns;
-- Check the outputs.
ASSERT s = patterns(i).s
REPORT "bad sum value" SEVERITY note;
-- assert co = patterns(i).co
-- report "bad carray out value" severity error;
END LOOP;
ASSERT false REPORT "end of test" SEVERITY note;
-- Wait forever; this will finish the simulation.
WAIT;
END PROCESS;
END behave;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2502.vhd | 4 | 2041 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2502.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p02n01i02502ent IS
END c07s03b04x00p02n01i02502ent;
ARCHITECTURE c07s03b04x00p02n01i02502arch OF c07s03b04x00p02n01i02502ent IS
BEGIN
TESTING: PROCESS
type rec_type is
record
x : bit;
y : integer;
z : boolean;
end record;
variable S :rec_type;
BEGIN
S := rec_type'(bit'('0'), 1, true);
assert NOT(S.x='0' and S.y=1 and S.z=true)
report "***PASSED TEST: c07s03b04x00p02n01i02502"
severity NOTE;
assert (S.x='0' and S.y=1 and S.z=true)
report "***FAILED TEST: c07s03b04x00p02n01i02502 - The qualified expression must either consist of a type mark, an apostrophe ('), and an expression enclosed with parentheses or consist of a type mark, an apostrophe ('), and an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p02n01i02502arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2146.vhd | 4 | 2222 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2146.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02146ent IS
END c07s02b04x00p21n01i02146ent;
ARCHITECTURE c07s02b04x00p21n01i02146arch OF c07s02b04x00p21n01i02146ent IS
TYPE time_v is array (integer range <>) of time;
SUBTYPE time_4 is time_v (1 to 4);
SUBTYPE time_5 is time_v (1 to 5);
BEGIN
TESTING: PROCESS
variable result : time_5;
variable l_operand : time_4 := ( 12 ns, 56 ns, 12 ns, 56 ns );
variable r_operand : time := 12 ns;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (12 ns, 56 ns, 12 ns, 56 ns, 12 ns)) and (result(1) = 12 ns))
report "***PASSED TEST: c07s02b04x00p21n01i02146"
severity NOTE;
assert ((result = (12 ns, 56 ns, 12 ns, 56 ns, 12 ns)) and (result(1) = 12 ns))
report "***FAILED TEST: c07s02b04x00p21n01i02146 - Concatenation of element and TIME array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02146arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue72/issue.vhdl | 2 | 591 | library ieee;
use ieee.std_logic_1164.all;
use work.issue_pkg.t_one_two; -- does not work
--use work.issue_pkg.all; -- works
entity issue is
port (
clk : in std_logic;
input : in t_one_two;
output : out std_logic
);
end entity issue;
architecture rtl of issue is
begin -- architecture rtl
process (clk) is
begin -- process
if clk'event and clk = '1' then -- rising clock edge
if input = one then
output <= '1';
else
output <= '0';
end if;
end if;
end process;
end architecture rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2051.vhd | 4 | 1673 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2051.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02051ent IS
END c07s02b04x00p01n01i02051ent;
ARCHITECTURE c07s02b04x00p01n01i02051arch OF c07s02b04x00p01n01i02051ent IS
BEGIN
TESTING: PROCESS
variable BITSTRV : BIT_VECTOR( 0 to 7 );
BEGIN
BITSTRV := BITSTRV + "01010101";
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02051 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02051arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_ml.vhd | 2 | 1405 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_ac_dhuff_tbl_ml is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic;
clk : in std_logic;
ra0_addr : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_ac_dhuff_tbl_ml;
architecture augh of p_jinfo_ac_dhuff_tbl_ml is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue238/rec2.vhdl | 2 | 384 | entity rec2 is
end;
architecture behav of rec2 is
type rec1 is record
a : natural;
end record;
type rec1_arr is array (natural range <>) of rec1;
function resolve (a : rec1_arr) return rec1 is
begin
return (a => 0);
end resolve;
subtype srec1 is resolve rec1;
begin
process
variable a : srec1;
begin
a.a := 5;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/add_210.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_210 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_210;
architecture augh of add_210 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug098/loopy.vhdl | 1 | 755 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity loopy is
end loopy;
architecture foo of loopy is
constant R: integer := 4;
constant L: integer := 16;
constant W: integer := 16;
constant M: integer := 4;
type t_reg_x is array ( 0 to L-1 ) of signed( W-1 downto 0 );
signal reg_x : t_reg_x := ( others => ( others => '0' ) );
type t_mux_in_x is array ( 0 to L - 1 ) of signed( W - 1 downto 0 );
signal mux_in_x: t_mux_in_x := ( others => ( others => '0') );
begin
process (reg_x)
begin
for r in 0 to R-1 loop
for m in 0 to M-1 loop
mux_in_x(r * M + m) <= reg_x(m * R + r);
end loop;
end loop;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2449.vhd | 4 | 1777 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2449.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p02n02i02449ent IS
END c07s03b02x02p02n02i02449ent;
ARCHITECTURE c07s03b02x02p02n02i02449arch OF c07s03b02x02p02n02i02449ent IS
BEGIN
TESTING: PROCESS
type t17 is array (0 to 0) of integer;
variable v17 : t17;
BEGIN
v17 := (1 to 0 | p => 17); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s03b02x02p02n02i02449 - Named association of an array aggregate can have a choice that is a null range only if the single element association has a single choice."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p02n02i02449arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1554.vhd | 4 | 1771 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1554.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p02n01i01554ent IS
END c08s10b00x00p02n01i01554ent;
ARCHITECTURE c08s10b00x00p02n01i01554arch OF c08s10b00x00p02n01i01554ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for i in 1 to 10 loop
next;
k := 5;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s10b00x00p02n01i01554"
severity NOTE;
assert (k=0)
report "***FAILED TEST: c08s10b00x00p02n01i01554 - A next statement is allowed in a loop without a label"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p02n01i01554arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2859.vhd | 4 | 1716 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2859.vhd,v 1.1.1.1 2001-08-22 18:20:50 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
ENTITY c13s10b00x00p04n01i02859ent IS
END c13s10b00x00p04n01i02859ent;
ARCHITECTURE c13s10b00x00p04n01i02859arch OF c13s10b00x00p04n01i02859ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert false
report %This string is illegal because of this character ".%
severity note ;
assert FALSE
report "***FAILED TEST: c13s10b00x00p04n01i02859 - Enclosed sequence of characters contains quotation character."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s10b00x00p04n01i02859arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2184.vhd | 4 | 1915 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2184.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02184ent IS
END c07s02b05x00p01n02i02184ent;
ARCHITECTURE c07s02b05x00p01n02i02184arch OF c07s02b05x00p01n02i02184ent IS
BEGIN
TESTING: PROCESS
type PHYS is range 0 to 1000
units
A;
B = 10 A;
C = 10 B;
D = 10 C;
end units;
variable k : PHYS := 1 A;
variable m : PHYS := 5 B;
BEGIN
k := + m;
assert NOT( k = 5 B )
report "***PASSED TEST: c07s02b05x00p01n02i02184"
severity NOTE;
assert ( k = 5 B )
report "***FAILED TEST: c07s02b05x00p01n02i02184 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02184arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1707.vhd | 4 | 2080 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1707.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p07n01i01707ent IS
END c09s02b00x00p07n01i01707ent;
ARCHITECTURE c09s02b00x00p07n01i01707arch OF c09s02b00x00p07n01i01707ent IS
procedure call_wait (variable dly : in time;
variable bool : out boolean) is
--
-- This procedure simply waits for the time specified in its argument.
--
begin
wait for dly;
bool := false;
end call_wait;
signal trigger : bit;
BEGIN
trigger <= '1' after 5 ns;
TESTING: PROCESS( trigger )
variable delay : time := 2 ns;
variable bool : boolean := true;
BEGIN
call_wait(delay, bool); -- use wait indirectly
assert FALSE
report "***FAILED TEST: c09s02b00x00p07n01i01707 - Procedure with an indirect wait was illegal to be placed in a process with an explicit sensitivity list."
severity ERROR;
END PROCESS TESTING;
END c09s02b00x00p07n01i01707arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue1051/psi_common_math_pkg.vhd | 1 | 5646 | ------------------------------------------------------------------------------
-- Copyright (c) 2018 by Paul Scherrer Institute, Switzerland
-- All rights reserved.
-- Authors: Oliver Bruendler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Libraries
------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_array_pkg.all;
------------------------------------------------------------------------------
-- Package Header
------------------------------------------------------------------------------
package psi_common_math_pkg is
function log2(arg : in natural) return natural;
function log2ceil(arg : in natural) return natural;
function log2ceil(arg : in real) return natural;
function isLog2(arg : in natural) return boolean;
function max( a : in integer;
b : in integer) return integer;
function min( a : in integer;
b : in integer) return integer;
-- choose t if s=true else f
function choose( s : in boolean;
t : in std_logic;
f : in std_logic) return std_logic;
function choose( s : in boolean;
t : in std_logic_vector;
f : in std_logic_vector) return std_logic_vector;
function choose( s : in boolean;
t : in integer;
f : in integer) return integer;
function choose( s : in boolean;
t : in string;
f : in string) return string;
function choose( s : in boolean;
t : in real;
f : in real) return real;
function choose( s : in boolean;
t : in unsigned;
f : in unsigned) return unsigned;
-- count occurence of a value inside an array
function count( a : in t_ainteger;
v : in integer) return integer;
function count( a : in t_abool;
v : in boolean) return integer;
function count( a : in std_logic_vector;
v : in std_logic) return integer;
end psi_common_math_pkg;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body psi_common_math_pkg is
-- *** Log2 integer ***
function log2(arg : in natural) return natural is
variable v : natural := arg;
variable r : natural := 0;
begin
while v > 1 loop
v := v/2;
r := r+1;
end loop;
return r;
end function;
-- *** Log2Ceil integer ***
function log2ceil(arg : in natural) return natural is
begin
if arg = 0 then
return 0;
end if;
return log2(arg*2-1);
end function;
-- *** Log2Ceil real ***
function log2ceil(arg : in real) return natural is
variable v : real := arg;
variable r : natural := 0;
begin
while v > 1.0 loop
v := v/2.0;
r := r+1;
end loop;
return r;
end function;
-- *** isLog2 ***
function isLog2(arg : in natural) return boolean is
begin
if log2(arg) = log2ceil(arg) then
return true;
else
return false;
end if;
end function;
-- *** Max ***
function max( a : in integer;
b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- *** Min ***
function min( a : in integer;
b : in integer) return integer is
begin
if a > b then
return b;
else
return a;
end if;
end function;
-- *** Choose (std_logic) ***
function choose( s : in boolean;
t : in std_logic;
f : in std_logic) return std_logic is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (std_logic_vector) ***
function choose( s : in boolean;
t : in std_logic_vector;
f : in std_logic_vector) return std_logic_vector is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (integer) ***
function choose( s : in boolean;
t : in integer;
f : in integer) return integer is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (string) ***
function choose( s : in boolean;
t : in string;
f : in string) return string is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (real) ***
function choose( s : in boolean;
t : in real;
f : in real) return real is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** Choose (unsigned) ***
function choose( s : in boolean;
t : in unsigned;
f : in unsigned) return unsigned is
begin
if s then
return t;
else
return f;
end if;
end function;
-- *** count (integer) ***
function count( a : in t_ainteger;
v : in integer) return integer is
variable cnt_v : integer := 0;
begin
for idx in a'low to a'high loop
if a(idx) = v then
cnt_v := cnt_v+1;
end if;
end loop;
return cnt_v;
end function;
-- *** count (bool) ***
function count( a : in t_abool;
v : in boolean) return integer is
variable cnt_v : integer := 0;
begin
for idx in a'low to a'high loop
if a(idx) = v then
cnt_v := cnt_v+1;
end if;
end loop;
return cnt_v;
end function;
-- *** count (std_logic) ***
function count( a : in std_logic_vector;
v : in std_logic) return integer is
variable cnt_v : integer := 0;
begin
for idx in a'low to a'high loop
if a(idx) = v then
cnt_v := cnt_v+1;
end if;
end loop;
return cnt_v;
end function;
end psi_common_math_pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1604.vhd | 4 | 1694 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1604.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p04n01i01604ent IS
END c08s11b00x00p04n01i01604ent;
ARCHITECTURE c08s11b00x00p04n01i01604arch OF c08s11b00x00p04n01i01604ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
exit L when 'A';
k := i;
end loop;
assert FALSE
report "***FAILED TEST: c08s11b00x00p04n01i01604 - The condition in an exit statement must be of boolean type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p04n01i01604arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2037.vhd | 4 | 1660 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2037.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02037ent IS
END c07s02b04x00p01n01i02037ent;
ARCHITECTURE c07s02b04x00p01n01i02037arch OF c07s02b04x00p01n01i02037ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
BEGIN
BOOLV := BOOLV + TRUE;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02037 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02037arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/vector.d/cmp_142.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_142 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_142;
architecture augh of cmp_142 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc639.vhd | 4 | 3323 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc639.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:51 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:14 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:28 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00639ent IS
END c03s04b01x00p01n01i00639ent;
ARCHITECTURE c03s04b01x00p01n01i00639arch OF c03s04b01x00p01n01i00639ent IS
type four_value is ('Z','0','1','X');
subtype binary is four_value range '0' to '1';
subtype word is bit_vector(0 to 15);
constant size : integer := 7;
type primary_memory is array(0 to size) of word;
type primary_memory_module is
record
enable : binary;
memory_number : primary_memory;
end record;
type primary_memory_module_file is file of primary_memory_module;
constant C38 : word := (others => '1');
constant C44 : primary_memory := (others => C38);
constant C45 : primary_memory_module := ('1',C44);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : primary_memory_module_file open read_mode is "iofile.43";
variable v : primary_memory_module;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C45) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00639"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00639 - File reading operation (primary_memory_module file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00639arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1238/multiplexers_3.vhdl | 1 | 616 | library ieee;
use ieee.std_logic_1164.all;
entity multiplexers_3 is
port (di : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(7 downto 0);
do : out std_logic);
end multiplexers_3;
architecture archi of multiplexers_3 is
begin
do <= di(0) when sel(0)='0' else 'Z';
do <= di(1) when sel(1)='0' else 'Z';
do <= di(2) when sel(2)='0' else 'Z';
do <= di(3) when sel(3)='0' else 'Z';
do <= di(4) when sel(4)='0' else 'Z';
do <= di(5) when sel(5)='0' else 'Z';
do <= di(6) when sel(6)='0' else 'Z';
do <= di(7) when sel(7)='0' else 'Z';
end archi;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1525.vhd | 4 | 1602 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1525.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p08n01i01525ent IS
END c08s09b00x00p08n01i01525ent;
ARCHITECTURE c08s09b00x00p08n01i01525arch OF c08s09b00x00p08n01i01525ent IS
BEGIN
TESTING: PROCESS
BEGIN
while not '0' loop
end loop;
assert FALSE
report "***FAILED TEST: c08s09b00x00p08n01i01525 - while condition is not boolean expression"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p08n01i01525arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/dff03/tb_dff02.vhdl | 1 | 894 | entity tb_dff02 is
end tb_dff02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff02 is
signal clk : std_logic;
signal en1 : std_logic;
signal en2 : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff02
port map (
q => dout,
d => din,
en1 => en1,
en2 => en2,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en1 <= '1';
en2 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
en1 <= '0';
din <= '0';
pulse;
assert dout = '1' severity failure;
en1 <= '1';
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc695.vhd | 4 | 3133 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc695.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:05 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:39 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:43 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00695ent IS
END c03s04b01x00p23n01i00695ent;
ARCHITECTURE c03s04b01x00p23n01i00695arch OF c03s04b01x00p23n01i00695ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of BOOLEAN;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.10";
-- Declare a variable into which we will read.
constant CON : BOOLEAN := TRUE;
variable VAR : BOOLEAN;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00695"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00695 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00695arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket37/genlogic.vhdl | 3 | 215 | library ieee;
use ieee.std_logic_1164.all;
entity genlogic is
generic (val : std_logic := '0');
end genlogic;
architecture behav of genlogic is
begin
assert val = '1' or val = 'H' severity failure;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2764.vhd | 4 | 1648 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2764.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p06n03i02764ent IS
END c13s07b00x00p06n03i02764ent;
ARCHITECTURE c13s07b00x00p06n03i02764arch OF c13s07b00x00p06n03i02764ent IS
BEGIN
TESTING: PROCESS
constant null_value : bit_vector := X"2AG";
BEGIN
assert FALSE
report "***FAILED TEST: c13s07b00x00p06n03i02764 - For the base specifier `X', the extended digits are restricted to '0' to 'F'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p06n03i02764arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue67/fileerr.vhdl | 2 | 201 | entity fileerr is
end fileerr;
use std.textio.all;
architecture behav of fileerr is
begin
process
file f : text;
begin
file_open (f, "bad-file-name");
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2242.vhd | 4 | 1693 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2242.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02242ent IS
END c07s02b06x00p01n01i02242ent;
ARCHITECTURE c07s02b06x00p01n01i02242arch OF c07s02b06x00p01n01i02242ent IS
BEGIN
TESTING: PROCESS
variable BITSTRV : BIT_VECTOR( 0 to 31 );
variable k : integer;
BEGIN
k := BITSTRV mod X"7777";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02242 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02242arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue290/TbNamesPkg.vhd | 2 | 3119 | --
-- File Increment: TbNamesPkg.vhd
-- Design Unit Increment: TbNamesPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for Increment.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
--
-- Revision History:
-- Date Version Description
-- 05/2015 2015.06 Added input to Get to return when not initialized
--
--
-- Copyright (c) 2010 - 2016 by SynthWorks Design Inc. All rights reserved.
--
package TbNamesPkg is
type IncrementPType is protected
procedure Inc ;
impure function Get return integer ;
end protected IncrementPType ;
procedure PrintNames ;
procedure CallPrintNames ;
end package TbNamesPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TbNamesPkg is
type IncrementPType is protected body
variable IncrementVar : integer := 0 ;
impure function PrintNamesFun(S : string) return integer is
begin
report "IncrementVar'INSTANCE_NAME as a parameter: " & S ;
report "IncrementVar: INSTANCE_NAME " & IncrementVar'INSTANCE_NAME ;
report "IncrementVar: PATH_NAME " & IncrementVar'PATH_NAME ;
report "function PrintNamesFun: INSTANCE_NAME " & PrintNamesFun'INSTANCE_NAME ;
report "function PrintNamesFun: PATH_NAME " & PrintNamesFun'PATH_NAME ;
return 0 ;
end function PrintNamesFun ;
variable Temp : integer := PrintNamesFun(IncrementVar'INSTANCE_NAME) ;
------------------------------------------------------------
procedure Inc is
------------------------------------------------------------
begin
IncrementVar := IncrementVar + 1 ;
end procedure Inc ;
------------------------------------------------------------
impure function Get return integer is
------------------------------------------------------------
begin
report "IncrementVar: INSTANCE_NAME " & IncrementVar'INSTANCE_NAME ;
report "IncrementVar: PATH_NAME " & IncrementVar'PATH_NAME ;
report "Method Get: INSTANCE_NAME " & Get'INSTANCE_NAME ;
report "Method Get: PATH_NAME " & Get'PATH_NAME ;
return IncrementVar ;
end function Get ;
end protected body IncrementPType ;
procedure PrintNames is
begin
report "procedure PrintNames: INSTANCE_NAME " & PrintNames'INSTANCE_NAME ;
report "procedure PrintNames: PATH_NAME " & PrintNames'PATH_NAME ;
end procedure PrintNames ;
procedure CallPrintNames is
begin
PrintNames ;
end procedure CallPrintNames ;
end package body TbNamesPkg ;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_crtl.vhd | 4 | 2719 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_crtl.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.dlx_types.all,
work.alu_types.all,
work.reg_file_types.all;
entity controller is
generic ( Tpd_clk_ctrl, Tpd_clk_const : delay_length;
debug : dlx_debug_control := none );
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
width : out dlx_mem_width;
write_enable : out std_logic;
mem_enable : out std_logic;
ifetch : out std_logic;
ready : in std_logic;
alu_in_latch_en : out std_logic;
alu_function : out alu_func;
alu_zero, alu_negative, alu_overflow : in std_logic;
reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
reg_write : out std_logic;
c_latch_en : out std_logic;
a_latch_en, a_out_en : out std_logic;
b_latch_en, b_out_en : out std_logic;
temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
mem_addr_mux_sel : out std_logic;
mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
mdr_mux_sel : out std_logic;
ir_latch_en : out std_logic;
ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
ir_immed1_en, ir_immed2_en : out std_logic;
current_instruction : in dlx_word;
mem_addr : std_logic_vector(1 downto 0);
const1, const2 : out dlx_word );
end entity controller;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3054.vhd | 4 | 1951 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3054.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s03b00x00p07n03i03054ent IS
END c12s03b00x00p07n03i03054ent;
ARCHITECTURE c12s03b00x00p07n03i03054arch OF c12s03b00x00p07n03i03054ent IS
BEGIN
bl1: block
signal si : integer := 3;
function int (signal sf : in integer) return integer is
constant err:integer := sf;
begin
return err;
end;
begin
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( si = int(si) )
report "***PASSED TEST: c12s03b00x00p07n03i03054"
severity NOTE;
assert ( si = int(si) )
report "***FAILED TEST: c12s03b00x00p07n03i03054 - Name of a signal used in the declarative part of a subprogram test failed."
severity ERROR;
wait;
END PROCESS TESTING;
end block;
END c12s03b00x00p07n03i03054arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue560/reproducer3.vhdl | 1 | 1193 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reproducer_pkg is
-- Functions
function MIN(LEFT, RIGHT: unsigned) return unsigned;
function MIN(LEFT, RIGHT: integer) return integer;
end reproducer_pkg;
package body reproducer_pkg is
function MIN(LEFT, RIGHT: unsigned) return unsigned is
begin
if LEFT < RIGHT then
return LEFT;
else
return RIGHT;
end if;
end;
function MIN(LEFT, RIGHT: integer) return integer is
begin
if LEFT < RIGHT then
return LEFT;
else
return RIGHT;
end if;
end;
end reproducer_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reproducer_pkg.all;
entity reproducer is
port(
inputA : in unsigned(7 downto 0);
inputB : in unsigned(7 downto 0);
inputC : in integer;
inputD : in integer;
OutputA : out unsigned(7 downto 0);
OutputB : out integer
);
end reproducer;
architecture rtl of reproducer is
begin
-- OutputA <= min(inputA, inputB);
OutputB <= min(inputC, inputD);
end rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-fl.vhd | 4 | 8659 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_mem-fl.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all,
std.textio.all;
architecture file_loaded of memory is
begin
mem_behavior : process is
constant high_address : natural := mem_size - 1;
type memory_array is
array (natural range 0 to high_address / 4) of dlx_bv_word;
variable mem : memory_array;
variable byte_address, word_address : natural;
variable write_access : boolean;
procedure load is
file binary_file : text open read_mode is load_file_name;
variable L : line;
variable ch : character;
variable line_number : natural := 0;
variable addr : natural;
variable word : dlx_bv_word;
procedure read_hex_natural ( L : inout line; n : out natural ) is
variable result : natural := 0;
begin
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
result := result*16 + character'pos(ch) - character'pos('0');
elsif 'A' <= ch and ch <= 'F' then
result := result*16 + character'pos(ch) - character'pos('A') + 10;
elsif 'a' <= ch and ch <= 'f' then
result := result*16 + character'pos(ch) - character'pos('a') + 10;
else
report "Format error in file " & load_file_name
& " on line " & integer'image(line_number) severity error;
end if;
end loop;
n := result;
end read_hex_natural;
procedure read_hex_word ( L : inout line; word : out dlx_bv_word ) is
variable digit : natural;
variable r : natural := 0;
begin
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
digit := character'pos(ch) - character'pos('0');
elsif 'A' <= ch and ch <= 'F' then
digit := character'pos(ch) - character'pos('A') + 10;
elsif 'a' <= ch and ch <= 'f' then
digit := character'pos(ch) - character'pos('a') + 10;
else
report "Format error in file " & load_file_name
& " on line " & integer'image(line_number)
severity error;
end if;
word(r to r+3) := natural_to_bv(digit, 4);
r := r + 4;
end loop;
end read_hex_word;
begin
while not endfile(binary_file) loop
readline(binary_file, L);
line_number := line_number + 1;
read_hex_natural(L, addr);
read(L, ch); -- the space between addr and data
read_hex_word(L, word);
mem(addr / 4) := word;
end loop;
end load;
procedure do_write is
subtype ls_2_bits is bit_vector(1 downto 0);
begin
case width is
when dlx_mem_width_word =>
mem(word_address) := to_bitvector(d);
when dlx_mem_width_halfword =>
if To_bit(a(1)) = '0' then -- ms half word
mem(word_address)(0 to 15) := to_bitvector( d(0 to 15) );
else -- ls half word
mem(word_address)(16 to 31) := to_bitvector( d(16 to 31) );
end if;
when dlx_mem_width_byte =>
case ls_2_bits'(To_bitvector(a(1 downto 0))) is
when b"00" =>
mem(word_address)(0 to 7) := to_bitvector( d(0 to 7) );
when b"01" =>
mem(word_address)(8 to 15) := to_bitvector( d(8 to 15) );
when b"10" =>
mem(word_address)(16 to 23) := to_bitvector( d(16 to 23) );
when b"11" =>
mem(word_address)(24 to 31) := to_bitvector( d(24 to 31) );
end case;
when others =>
report "illegal width indicator in write" severity error;
end case;
end do_write;
procedure do_read is
begin
d <= To_X01( mem(word_address) );
end do_read;
begin
load; -- read binary memory image into memory array
-- initialize outputs
d <= disabled_dlx_word;
ready <= '0';
-- process memory cycles
loop
-- wait for a command, valid on leading edge of phi2
wait on phi2 until rising_edge(phi2) and To_bit(mem_enable) = '1';
-- decode address and perform command if selected
byte_address := bv_to_natural(To_bitvector(a));
write_access := To_bit(write_enable) = '1';
if byte_address <= high_address then
word_address := byte_address / 4;
if write_access then -- write cycle
do_write;
wait for Tac_first; -- write access time, 1st cycle
else -- read cycle
wait for Tac_first; -- read access time, 1st cycle
do_read;
end if;
-- ready synchronous with phi2
wait until rising_edge(phi2);
ready <= '1' after Tpd_clk_out;
wait until falling_edge(phi2);
ready <= '0' after Tpd_clk_out;
-- do subsequent cycles in burst
while To_bit(burst) = '1' loop
word_address := (word_address + 1) mod (mem_size / 4);
wait until rising_edge(phi2);
if write_access then -- write cycle
do_write;
wait for Tac_burst; -- write access time, burst cycle
else -- read cycle
wait for Tac_burst; -- read access time, burst cycle
do_read;
end if;
-- ready synchronous with phi2
wait until rising_edge(phi2);
ready <= '1' after Tpd_clk_out;
wait until falling_edge(phi2);
ready <= '0' after Tpd_clk_out;
end loop;
if not write_access then -- was read
d <= disabled_dlx_word after Tpd_clk_out;
end if;
end if;
end loop;
end process mem_behavior;
end architecture file_loaded;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1076/ent.vhdl | 1 | 211 | library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
o : out std_logic
);
end;
architecture a of ent is
begin
gen: if false generate
o <= '1';
else generate
o <= '0';
end generate;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/ret01/ret02.vhdl | 1 | 369 | library ieee;
use ieee.std_logic_1164.all;
entity ret02 is
port (di : std_logic_vector (7 downto 0);
res : out integer);
end ret02;
architecture behav of ret02 is
function sign (v : std_logic_vector (7 downto 0)) return integer is
begin
if v (7) = '1' then
return -1;
end if;
return 1;
end sign;
begin
res <= sign (di);
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue791/test.vhdl | 1 | 244 | entity test is
end test;
architecture behav of test is
procedure proc is
begin
null;
end proc;
package pkg is new work.generic_pkg
generic map (proc);
begin
process
begin
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1236/issue.vhdl | 1 | 156 | library ieee;
use ieee.std_logic_1164.all;
entity issue is
generic (type t_type);
end issue;
architecture beh of issue is
begin
end architecture beh;
| gpl-2.0 |
tgingold/ghdl | testsuite/vpi/vpi002/mydesign.vhdl | 1 | 1307 | library ieee ;
use ieee.std_logic_1164.all;
package mypackage is
type myenum is (ONE, TWO, THREE);
subtype myarray is bit_vector(2 downto 0);
type myarray5 is array(1 downto 0) of bit;
end package;
library ieee ;
use ieee.std_logic_1164.all;
use work.mypackage.all;
entity myentity is
generic (
width: integer := 2;
genenum: myenum := ONE;
genarray1: bit_vector(1 downto 0) := "01";
genarray3: myarray := "010";
genarray5: myarray5 := ('1', '0')
);
port (
portenum: in myenum;
portarray1: in bit_vector(1 downto 0);
portarray2: in bit_vector(width downto 0);
portarray3: in myarray;
portarray5: in myarray5
);
end myentity;
architecture arch of myentity is
subtype myarray4 is bit_vector(width downto 0);
signal sigenum: myenum;
constant constenum: myenum := ONE;
signal sigarray1: bit_vector(1 downto 0);
constant constarray1: bit_vector(1 downto 0) := "10";
signal sigarray2: bit_vector(width downto 0);
constant constarray2: bit_vector(width downto 0) := (others => '1');
signal sigarray3: myarray;
constant constarray3: myarray := "101";
signal sigarray4: myarray4;
constant constarray4: myarray4:= (others => '1');
signal sigarray5: myarray5;
constant constarray5: myarray5:= (others => '1');
begin
end arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/controller.vhd | 4 | 1289 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity controller is
end entity controller;
architecture test of controller is
signal clk : bit;
attribute synthesis_hint : string;
begin
-- code from book
controller : process is
attribute synthesis_hint of control_loop : label is
"implementation:FSM(clk)";
-- . . .
begin
-- . . . -- initialization
control_loop : loop
wait until clk = '1';
-- . . .
end loop;
end process controller;
-- end code fom book
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue72/issue_pkg.vhdl | 2 | 78 | package issue_pkg is
type t_one_two is (one, two);
end package issue_pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_05.vhd | 4 | 941 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
architecture abstract of adder is
begin
add_a_b : process (a, b) is
begin
sum <= a + b;
end process add_a_b;
end architecture abstract;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd | 4 | 1673 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_17 is
end entity inline_17;
----------------------------------------------------------------
architecture test of inline_17 is
signal s, r, q, q_n : bit := '0';
begin
q <= '1' when s = '1' else
'0' when r = '1';
q_n <= '0' when s = '1' else
'1' when r = '1';
-- code from book:
check : process is
begin
assert not (s = '1' and r = '1')
report "Incorrect use of S_R_flip_flop: s and r both '1'";
wait on s, r;
end process check;
-- end of code from book
stimulus : process is
begin
wait for 10 ns;
s <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '1'; wait for 10 ns;
r <= '0'; wait for 10 ns;
s <= '1'; wait for 10 ns;
r <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue301/src/reorder.vhd | 7 | 3970 | --!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Reorder twisted output due to windowing
--! @author Markus Fehrenz
--! @date 2011/05/12
--!
--! @details The windowing output is twisted.
--! The correct order is simply rebuilt by reversing
--! the output of each traceback unit.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
entity reorder is
port(
clk : in std_logic;
rst : in std_logic;
--
-- Traceback unit output, twisted order
--
s_axis_input_tvalid : in std_logic;
s_axis_input_tdata : in std_logic;
s_axis_input_tlast : in std_logic;
s_axis_input_last_tuser : in std_logic;
s_axis_input_tready : out std_logic;
--
-- Viterbi decoder output, original (input) order.
--
m_axis_output_tvalid : out std_logic;
m_axis_output_tdata : out std_logic;
m_axis_output_tlast : out std_logic;
m_axis_output_last_tuser : out std_logic; -- Last bit of one traceback window
m_axis_output_tready : in std_logic
);
end entity reorder;
architecture rtl of reorder is
-- used to store one reversed output of a traceback unit
signal buffer_sreg : unsigned(MAX_WINDOW_LENGTH - 1 downto 0);
signal buffer_cnt : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
signal buffer_end : integer range ENCODER_MEMORY_DEPTH downto 0;
signal send_output, last_window : boolean;
signal s_axis_input_tready_int : std_logic;
begin
s_axis_input_tready <= s_axis_input_tready_int;
s_axis_input_tready_int <= '1' when not(send_output) else
'0';
-- m_axis_output_tvalid <= '1' when send_output and m_axis_output_tready= '1' else
m_axis_output_tvalid <= '1' when send_output else
'0';
m_axis_output_tdata <= buffer_sreg(0);
m_axis_output_tlast <= '1' when buffer_cnt = ENCODER_MEMORY_DEPTH and last_window else
'0';
-- Reorder the global path given from an traceback unit with the help of a shift register.
pr_reorder : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
buffer_sreg <= (others => '0');
buffer_cnt <= (others => '0');
send_output <= false;
last_window <= false;
buffer_end <= 0;
m_axis_output_last_tuser <= '0';
else
-- store output of traceback unit
if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
if s_axis_input_tlast = '1' then
last_window <= true;
buffer_end <= ENCODER_MEMORY_DEPTH;
end if;
if s_axis_input_last_tuser = '1' then
send_output <= true;
buffer_sreg <= buffer_sreg(MAX_WINDOW_LENGTH - 2 downto 0) & s_axis_input_tdata;
else
buffer_sreg <= buffer_sreg(MAX_WINDOW_LENGTH - 2 downto 0) & s_axis_input_tdata;
buffer_cnt <= buffer_cnt + 1;
end if;
end if;
-- send reordered data to the output
if m_axis_output_tready = '1' and send_output then
buffer_sreg <= '0' & buffer_sreg(MAX_WINDOW_LENGTH - 1 downto 1);
-- Next transfer will be the last one of this window.
if buffer_cnt = 1 then
m_axis_output_last_tuser <= '1';
end if;
-- This was the last data transfer. Tailbits are cut off
if buffer_cnt = buffer_end then
send_output <= false;
last_window <= false;
buffer_end <= 0;
buffer_cnt <= (others => '0');
m_axis_output_last_tuser <= '0';
else
buffer_cnt <= buffer_cnt - 1;
end if;
end if;
end if;
end if;
end process pr_reorder;
end architecture rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/anon01/anon02.vhdl | 1 | 563 | entity anon02_sub is
port (i : bit_vector (7 downto 0);
o : out bit_vector (7 downto 0));
end anon02_sub;
architecture behav of anon02_sub is
begin
o <= i xor x"a5";
end behav;
entity anon02 is
port (i : bit_vector (6 downto 0);
o : out bit_vector (6 downto 0));
end anon02;
architecture behav of anon02 is
signal res : bit_vector (7 downto 0);
begin
dut: entity work.anon02_sub
port map (i => '0' & i,
o => res);
o <= res (6 downto 0);
gen: for i in 1 to 2 generate
assert i < 3;
end generate;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_02.vhd | 4 | 2513 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_12_fg_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book
entity D_flipflop is
generic ( Tpd_clk_q, Tsu_d_clk, Th_d_clk : delay_length );
port ( clk, d : in bit; q : out bit );
end entity D_flipflop;
--------------------------------------------------
architecture basic of D_flipflop is
begin
behavior : q <= d after Tpd_clk_q when clk = '1' and clk'event;
check_setup : process is
begin
wait until clk = '1';
assert d'last_event >= Tsu_d_clk
report "setup violation";
end process check_setup;
check_hold : process is
begin
wait until clk'delayed(Th_d_clk) = '1';
assert d'delayed'last_event >= Th_d_clk
report "hold violation";
end process check_hold;
end architecture basic;
-- end code from book
entity fg_12_02 is
end entity fg_12_02;
architecture test of fg_12_02 is
signal system_clock, request, request_pending : bit := '0';
begin
-- code from book (in text)
request_flipflop : entity work.D_flipflop(basic)
generic map ( Tpd_clk_q => 4 ns,
Tsu_d_clk => 3 ns, Th_d_clk => 1 ns )
port map ( clk => system_clock,
d => request, q => request_pending );
-- end code from book
clock_gen : system_clock <= '1' after 10 ns,
'0' after 20 ns when system_clock = '0';
stimulus : request <= '1' after 25 ns, '0' after 35 ns,
'1' after 67 ns, '0' after 71 ns,
'1' after 108 ns, '0' after 110.5 ns;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue816/repro.vhdl | 1 | 797 | library ieee;
context ieee.ieee_std_context;
package integer_vector_ptr_pkg is
subtype index_t is integer range -1 to integer'high;
type integer_vector_ptr_t is record
index : index_t;
end record;
impure function get(ptr : integer_vector_ptr_t; index : integer)
return integer;
end package;
entity tb_test is
generic ( runner_cfg : string );
end entity;
use work.integer_vector_ptr_pkg.all;
architecture tb of tb_test is
constant params: integer_vector_ptr_t := (index => 0);
type time_t is array (natural range 0 to 1) of natural;
procedure get_time(variable t: inout time_t) is begin
t(0) := get(params, 0);
t(1) := get(params, 1);
end;
begin
run: process(all)
variable r: time_t;
begin
get_time(r);
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2694.vhd | 4 | 1741 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2694.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p04n01i02694ent IS
--ERROR: underline cannot be adjacent on the right to 'E' in an integer literal
constant a:integer:=1234E_2; -- failure_here
END c13s04b01x00p04n01i02694ent;
ARCHITECTURE c13s04b01x00p04n01i02694arch OF c13s04b01x00p04n01i02694ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s04b01x00p04n01i02694 - Exponents of decimal literals can have a single plus or minus following the E (optional)."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p04n01i02694arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue613/ent.vhdl | 1 | 197 | entity ent is
end entity;
architecture a of ent is
constant SimulationTime_c : time := 10000 ms;
begin
process begin
report "Hello world" severity note;
wait;
end process;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_04a.vhd | 4 | 1552 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_04a is
end entity inline_04a;
----------------------------------------------------------------
architecture test of inline_04a is
begin
process is
-- code from book:
type stimulus_record is record
stimulus_time : time;
stimulus_value : real_vector(0 to 3);
end record stimulus_record;
type stimulus_ptr is access stimulus_record;
variable bus_stimulus : stimulus_ptr;
-- end of code from book
begin
bus_stimulus := new stimulus_record;
bus_stimulus.all := stimulus_record'(20 ns, real_vector'(0.0, 5.0, 0.0, 42.0) );
report time'image(bus_stimulus.all.stimulus_time);
report time'image(bus_stimulus.stimulus_time);
wait;
end process;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue43/repro2.vhdl | 2 | 478 | entity test_tb is
end entity;
architecture beh of test_tb is
signal rx_data : bit_vector(159 downto 0);
procedure to_t( signal sa : out bit_vector(31 downto 0)) is
begin
sa <= (others => '1');
assert false report "lol";
end procedure;
begin
asd : for i in 0 to 4 generate
begin
process
begin
wait for 10 ns;
to_t(rx_data(32*(i+1)-1 downto 32*i));
wait;
end process;
end generate;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_03.vhd | 4 | 1279 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_ch_21_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity controller is
end entity controller;
-- code from book
architecture instrumented of controller is
shared variable operation_count : natural := 0;
-- . . .
begin
-- . . .
end architecture instrumented;
-- end code from book
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/huff_make_dhuff_tb_ac_huffcode.vhd | 2 | 1519 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huff_make_dhuff_tb_ac_huffcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end huff_make_dhuff_tb_ac_huffcode;
architecture augh of huff_make_dhuff_tb_ac_huffcode is
-- Embedded RAM
type ram_type is array (0 to 256) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 257 else (others => '-');
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1809.vhd | 4 | 1771 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1809.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p07n01i01809ent IS
END c07s01b00x00p07n01i01809ent;
ARCHITECTURE c07s01b00x00p07n01i01809arch OF c07s01b00x00p07n01i01809ent IS
signal POS : boolean;
signal P1 : boolean := false;
BEGIN
TESTING: PROCESS
BEGIN
POS <= not P1 after 20 ns;
wait for 35 ns;
assert NOT(POS = true)
report "***PASSED TEST: c07s01b00x00p07n01i01809"
severity NOTE;
assert (POS = true)
report "***FAILED TEST: c07s01b00x00p07n01i01809 - not Primary test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p07n01i01809arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_10.vhd | 4 | 1833 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity add_1 is
port ( d0, d1, d2, d3 : in bit;
y0, y1, y2, y3 : out bit );
end entity add_1;
architecture boolean_eqn of add_1 is
begin
y0 <= not d0 after 4 ns;
y1 <= (not d1 and d0)
or (d1 and not d0) after 4 ns;
y2 <= (not d2 and d1 and d0)
or (d2 and not (d1 and d0)) after 4 ns;
y3 <= (not d3 and d2 and d1 and d0)
or (d3 and not (d2 and d1 and d0)) after 4 ns;
end architecture boolean_eqn;
entity buf4 is
port ( a0, a1, a2, a3 : in bit;
y0, y1, y2, y3 : out bit );
end entity buf4;
architecture basic of buf4 is
begin
y0 <= a0 after 2 ns;
y1 <= a1 after 2 ns;
y2 <= a2 after 2 ns;
y3 <= a3 after 2 ns;
end architecture basic;
package counter_types is
subtype digit is bit_vector(3 downto 0);
end package counter_types;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2286.vhd | 4 | 2016 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2286.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02286ent IS
END c07s02b06x00p14n01i02286ent;
ARCHITECTURE c07s02b06x00p14n01i02286arch OF c07s02b06x00p14n01i02286ent IS
BEGIN
TESTING: PROCESS
type PHYS is range 1 to 100000
units
A;
B = 100 A;
C = 100 B;
end units;
function F_PHYS ( A : PHYS ) return PHYS is
begin
return A;
end F_PHYS;
variable P : PHYS := 1 B;
variable Z : integer := time'(1 min) / time'(27 sec);
BEGIN
Z := P / F_PHYS(1 A);
assert NOT(Z = 100)
report "***PASSED TEST: c07s02b06x00p14n01i02286"
severity NOTE;
assert (Z = 100)
report "***FAILED TEST: c07s02b06x00p14n01i02286 - Incompatible operands: May not be multiplied or divided."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02286arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue1246/tb.vhdl | 1 | 506 | --------------------------------------
-- use work.pkg_A.all;
--------------------------------------
entity tb is
end tb;
architecture arch of tb is
--------------------------------------
package pkgA is new work.pkg_A
generic map (
A => 0
);
--------------------------------------
begin
process
--------------------------------------
use pkgA.all;
--------------------------------------
begin
showA;
wait;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc662.vhd | 4 | 2348 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc662.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:56 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00662ent IS
END c03s04b01x00p01n01i00662ent;
ARCHITECTURE c03s04b01x00p01n01i00662arch OF c03s04b01x00p01n01i00662ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type positive_vector is array (natural range <>) of positive;
subtype positive_vector_range is positive_vector(hi_to_low_range);
constant C1 : positive_vector_range := (others => 3);
type positive_vector_range_file is file of positive_vector_range;
BEGIN
TESTING: PROCESS
file filein : positive_vector_range_file open write_mode is "iofile.03";
BEGIN
for i in 1 to 100 loop
write(filein,C1);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00662 - The output file will be verified by test s010112.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00662arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1835.vhd | 4 | 1836 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1835.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01835ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of small_int;
END c07s01b00x00p08n01i01835ent;
ARCHITECTURE c07s01b00x00p08n01i01835arch OF c07s01b00x00p08n01i01835ent IS
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_bus <= (0 => c07s01b00x00p08n01i01835ent, others => 0) after 5 ns;--entity name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01835 - Entity name are not permitted as primaries in an element association expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01835arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc870.vhd | 4 | 12340 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc870.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00870pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
subtype dumy is integer range 0 to 3;
signal Sin1 : bit_vector(0 to 5) ;
signal Sin2 : boolean_vector(0 to 5) ;
signal Sin4 : severity_level_vector(0 to 5) ;
signal Sin5 : integer_vector(0 to 5) ;
signal Sin6 : real_vector(0 to 5) ;
signal Sin7 : time_vector(0 to 5) ;
signal Sin8 : natural_vector(0 to 5) ;
signal Sin9 : positive_vector(0 to 5) ;
signal Sin10: array_rec_std(0 to 5) ;
end c01s03b01x00p12n01i00870pkg;
use work.c01s03b01x00p12n01i00870pkg.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00870pkg.all;
entity test1 is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test1 of test1 is
begin
sigout1 <= false;
sigout2 <= '0';
sigout4 <= error;
sigout5 <= 6;
sigout6 <= 6.0;
sigout7 <= 6 ns;
sigout8 <= 6;
sigout9 <= 6;
sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
end;
configuration test1bench of test1 is
for test1
end for;
end;
use work.c01s03b01x00p12n01i00870pkg.all;
ENTITY c01s03b01x00p12n01i00870ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15);
port(
dumy : inout bit_vector(zero to three));
END c01s03b01x00p12n01i00870ent;
ARCHITECTURE c01s03b01x00p12n01i00870arch OF c01s03b01x00p12n01i00870ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test1
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test1
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
variable dumb : bit_vector(zero to three);
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***PASSED TEST: c01s03b01x00p12n01i00870"
severity NOTE;
assert ( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***FAILED TEST: c01s03b01x00p12n01i00870 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00870arch;
configuration c01s03b01x00p12n01i00870cfg of c01s03b01x00p12n01i00870ent is
for c01s03b01x00p12n01i00870arch
for K
for others:test1 use configuration work.test1bench;
end for;
for G(0 to 3)
for all :test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue945/ent.vhdl | 1 | 139 | entity ent is
end ent;
architecture a of ent is
signal test : bit;
alias a1 : bit is test;
alias a2 : bit is a1;
begin
end a;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2675.vhd | 4 | 1802 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2675.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p04n01i02675ent IS
END c13s03b01x00p04n01i02675ent;
ARCHITECTURE c13s03b01x00p04n01i02675arch OF c13s03b01x00p04n01i02675ent IS
constant Qwerty_tyur_RT_456T : Integer := 10 ; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( Qwerty_tyur_RT_456T = 10 )
report "***PASSED TEST: c13s03b01x00p04n01i02675"
severity NOTE;
assert ( Qwerty_tyur_RT_456T = 10 )
report "***FAILED TEST: c13s03b01x00p04n01i02675 - Both upper and lower case letter should be able used in an identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p04n01i02675arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc539.vhd | 4 | 1799 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc539.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b01x00p01n02i00539ent IS
END c03s03b01x00p01n02i00539ent;
ARCHITECTURE c03s03b01x00p01n02i00539arch OF c03s03b01x00p01n02i00539ent IS
BEGIN
TESTING: PROCESS
type a;
type a is access a;
variable k : a;
BEGIN
assert NOT( k=null )
report "***PASSED TEST: c03s03b01x00p01n02i00539"
severity NOTE;
assert ( k=null)
report "***FAILED TEST: c03s03b01x00p01n02i00539 - The type of an element of the designated type can be another access type, or even the same access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b01x00p01n02i00539arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug017/call6b.vhdl | 2 | 374 | entity call6b is
end;
architecture behav of call6b is
type my_rec is record
a, b, c : character;
end record;
procedure check (s : my_rec) is
begin
wait for 1 ns;
assert s.b = 'a';
end;
begin
process
variable c : character := 'a';
begin
check ((a => 'e', b => 'a', c => 'c'));
report "SUCCESS";
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_01.vhd | 4 | 3453 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_01 is
end entity test_bench_03_01;
architecture test_thermostat_example of test_bench_03_01 is
signal desired_temp, actual_temp : integer := 25;
signal heater_on : boolean := false;
begin
dut : entity work.thermostat(example)
port map ( desired_temp => desired_temp, actual_temp => actual_temp,
heater_on => heater_on );
stimulus : process is
begin
wait for 5 sec;
actual_temp <= 24; wait for 5 sec;
actual_temp <= 23; wait for 5 sec;
actual_temp <= 22; wait for 5 sec;
actual_temp <= 21; wait for 5 sec;
actual_temp <= 22; wait for 5 sec;
actual_temp <= 23; wait for 5 sec;
actual_temp <= 24; wait for 5 sec;
actual_temp <= 25; wait for 5 sec;
actual_temp <= 26; wait for 5 sec;
actual_temp <= 27; wait for 5 sec;
actual_temp <= 28; wait for 5 sec;
actual_temp <= 29; wait for 5 sec;
actual_temp <= 28; wait for 5 sec;
actual_temp <= 27; wait for 5 sec;
actual_temp <= 26; wait for 5 sec;
actual_temp <= 25; wait for 5 sec;
actual_temp <= 24; wait for 5 sec;
actual_temp <= 23; wait for 5 sec;
actual_temp <= 22; wait for 5 sec;
actual_temp <= 21; wait for 5 sec;
actual_temp <= 22; wait for 5 sec;
actual_temp <= 23; wait for 5 sec;
actual_temp <= 24; wait for 5 sec;
actual_temp <= 25; wait for 5 sec;
actual_temp <= 26; wait for 5 sec;
actual_temp <= 27; wait for 5 sec;
actual_temp <= 28; wait for 5 sec;
actual_temp <= 29; wait for 5 sec;
actual_temp <= 28; wait for 5 sec;
actual_temp <= 27; wait for 5 sec;
actual_temp <= 26; wait for 5 sec;
desired_temp <= 30; wait for 5 sec;
actual_temp <= 25; wait for 5 sec;
actual_temp <= 26; wait for 5 sec;
actual_temp <= 27; wait for 5 sec;
actual_temp <= 28; wait for 5 sec;
actual_temp <= 29; wait for 5 sec;
actual_temp <= 30; wait for 5 sec;
actual_temp <= 31; wait for 5 sec;
actual_temp <= 32; wait for 5 sec;
actual_temp <= 33; wait for 5 sec;
actual_temp <= 34; wait for 5 sec;
actual_temp <= 35; wait for 5 sec;
actual_temp <= 34; wait for 5 sec;
actual_temp <= 33; wait for 5 sec;
actual_temp <= 32; wait for 5 sec;
actual_temp <= 31; wait for 5 sec;
actual_temp <= 30; wait for 5 sec;
wait;
end process stimulus;
end architecture test_thermostat_example;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug0100/nochoice1.vhdl | 1 | 166 | entity nochoice is
end;
architecture behav of nochoice is
constant n : natural := 5;
begin
process
begin
case n is
end case;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2733.vhd | 4 | 1885 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2733.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s05b00x00p01n01i02733ent IS
END c13s05b00x00p01n01i02733ent;
ARCHITECTURE c13s05b00x00p01n01i02733arch OF c13s05b00x00p01n01i02733ent IS
BEGIN
TESTING: PROCESS
type grph is array (1 to 95) of character;
variable k : grph;
BEGIN
k(1) := 'A';
k(2) := 'B';
assert NOT( k(1) = 'A' and
k(2) = 'B' )
report "***PASSED TEST: c13s05b00x00p01n01i02733"
severity NOTE;
assert ( k(1) = 'A' and
k(2) = 'B' )
report "***FAILED TEST: c13s05b00x00p01n01i02733 - Graphic charcters be used as a character literal test fail."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s05b00x00p01n01i02733arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_06.vhd | 4 | 2295 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_06.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_07_06 is
end entity ch_07_06;
library bv_utilities;
use bv_utilities.bv_arithmetic;
architecture test of ch_07_06 is
begin
process_07_5_b : process is
-- code from book:
function "+" ( left, right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bv_arithmetic."+"(left, right);
-- end not in book
end function "+";
variable addr_reg : bit_vector(31 downto 0);
-- . . .
-- end of code from book
-- code from book:
function "abs" ( right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
if right(right'left) = '0' then
return right;
else
return bv_arithmetic."-"(right);
end if;
-- end not in book
end function "abs";
variable accumulator : bit_vector(31 downto 0);
-- . . .
-- end of code from book
begin
-- code from book:
addr_reg := addr_reg + X"0000_0004";
-- end of code from book
accumulator := X"000000FF";
-- code from book:
accumulator := abs accumulator;
-- end of code from book
accumulator := X"FFFFFFFE";
accumulator := abs accumulator;
wait;
end process process_07_5_b;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc741.vhd | 4 | 2978 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc741.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x01p04n01i00741ent_a is
generic (
constant gc1 : in integer;
constant gc2 : in real;
constant gc3 : in boolean
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n01i00741ent_a;
architecture c01s01b01x01p04n01i00741arch_a of c01s01b01x01p04n01i00741ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1 = 5) AND (gc2 = 0.1234) AND (gc3) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00741"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00741 - Simple generic association in component instantiation failed."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00741arch_a;
ENTITY c01s01b01x01p04n01i00741ent IS
generic ( constant gen_con : integer := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n01i00741ent;
ARCHITECTURE c01s01b01x01p04n01i00741arch OF c01s01b01x01p04n01i00741ent IS
constant c1 : integer := 33;
constant c2 : real := 1.23557;
constant c3 : boolean := FALSE;
signal s1 : integer;
signal s2 : integer;
signal s3 : integer;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : real;
constant dgc3 : boolean
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00741ent_a(c01s01b01x01p04n01i00741arch_a)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
generic map (5, 0.1234, TRUE)
port map (ee1,ee2);
END c01s01b01x01p04n01i00741arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1880.vhd | 4 | 1893 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1880.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01880ent IS
END c07s01b00x00p08n01i01880ent;
ARCHITECTURE c07s01b00x00p08n01i01880arch OF c07s01b00x00p08n01i01880ent IS
type small_int is range 0 to 7;
signal s_int : small_int;
BEGIN
blk : block(s_int = 0)
begin
end block blk;
TESTING : PROCESS
variable tmp : small_int;
BEGIN
case blk is -- block labels illegal here
when 0 => tmp := 0;
when others => tmp := 1;
end case;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01880 - Block labels are not permitted as primaries in a case expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01880arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_07.vhd | 4 | 2188 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_07 is
end entity ch_03_07;
architecture test of ch_03_07 is
begin
process_03_2_b : process is
-- code from book:
subtype index_mode is integer range 0 to 3;
variable instruction_register : integer range 0 to 2**16 - 1;
-- end of code from book
variable index_value : integer;
constant accumulator_A : integer := 1;
constant accumulator_B : integer := 2;
constant index_register : integer := 3;
begin
for i in index_mode loop
instruction_register := i * 2**12;
-- code from book:
case index_mode'((instruction_register / 2**12) rem 2**2) is
when 0 =>
index_value := 0;
when 1 =>
index_value := accumulator_A;
when 2 =>
index_value := accumulator_B;
when 3 =>
index_value := index_register;
end case;
-- end of code from book
end loop;
wait;
end process process_03_2_b;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue283/uut.vhd | 1 | 491 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity foo is
port (
a : std_logic;
b : std_logic_vector(7 downto 0)
);
end entity foo;
architecture RTL of foo is
signal s_test : std_logic_vector(3 downto 0) := "1111";
begin
cmp_bar: entity work.bar
port map(
a => a
);
gen_bars: for i in 0 to 1 generate
cmp_generated_bar: entity work.bar
port map(
a => a
);
end generate gen_bars;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue406/queuet.vhdl | 1 | 402 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library libvhdl;
entity QueueT is
end entity QueueT;
architecture sim of QueueT is
package SlvQueue is new libvhdl.QueueP
generic map (QUEUE_TYPE => std_logic_vector(63 downto 0),
to_string => to_string);
-- shared variable sv_simple_queue : SlvQueue.t_simple_queue;
begin
end architecture sim;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/arr01/arr10.vhdl | 1 | 659 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity arr10 is
port (val : std_logic_vector(3 downto 0);
res : out natural);
end arr10;
architecture behav of arr10 is
function find (s : string; c : character) return natural is
begin
for i in s'range loop
if s (i) = c then
return i;
end if;
end loop;
return 0;
end find;
constant str1 : string := "hello world";
constant pos1 : natural := find (str1, 'w');
alias str2 : string (str1'length downto 1) is str1;
constant pos2 : natural := find (str2, 'w');
begin
assert pos1 = 7;
assert pos2 = 5;
res <= pos1;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/synth45/test2.vhdl | 1 | 631 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
port (val : out std_logic_vector (63 downto 0));
end entity test2;
architecture beh of test2 is
type t_register is array(0 to 7) of std_logic_vector(7 downto 0);
signal s_register : t_register;
begin
-- the problem is the next line
s_register <= (0 => x"f0", 1 => x"e1", 2 => x"d2", 3 => x"c3",
4 => x"b4", 5 => x"a5", 6 => x"96", 7 => x"87");
val <= s_register(7) & s_register(6) & s_register(5) & s_register(4)
& s_register(3) & s_register(2) & s_register(1) & s_register(0);
end architecture beh;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1586.vhd | 4 | 1685 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1586.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p02n01i01586ent IS
END c08s11b00x00p02n01i01586ent;
ARCHITECTURE c08s11b00x00p02n01i01586arch OF c08s11b00x00p02n01i01586ent IS
BEGIN
TESTING: PROCESS
BEGIN
L1: for b in boolean loop
exit when b L1; -- label must precede when clause
end loop L1;
assert FALSE
report "***FAILED TEST: c08s11b00x00p02n01i01586 - Illegal clause ordering in exit statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p02n01i01586arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug019/PoC/tb/common/simulation.v93.vhdl | 6 | 10685 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Simulation constants, functions and utilities.
--
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
package simulation is
-- predefined constants to ease testvector concatenation
constant U8 : T_SLV_8 := (others => 'U');
constant U16 : T_SLV_16 := (others => 'U');
constant U24 : T_SLV_24 := (others => 'U');
constant U32 : T_SLV_32 := (others => 'U');
constant D8 : T_SLV_8 := (others => '-');
constant D16 : T_SLV_16 := (others => '-');
constant D24 : T_SLV_24 := (others => '-');
constant D32 : T_SLV_32 := (others => '-');
-- Testbench Status Management
-- ===========================================================================
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure tbFail(msg : in string := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
-- Prints out the overall testbench result as defined by the automated
-- testbench process. Unless tbFail() or tbAssert() with a false condition
-- have been called before, a successful completion will be reported, a
-- failure otherwise.
procedure tbPrintResult;
-- clock generation
-- ===========================================================================
subtype T_DutyCycle is REAL range 0.0 to 1.0;
procedure simStop;
impure function simIsStopped return BOOLEAN;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5);
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
-- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end;
use std.TextIO.all;
package body simulation is
-- Testbench Status Management
-- ===========================================================================
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
shared variable pass : boolean := true;
shared variable simStopped : BOOLEAN := FALSE;
procedure tbFail(msg : in string := "") is
begin
if (str_length(msg) > 0) then
report str_trim(msg) severity error;
end if;
pass := false;
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
tbFail(msg);
end if;
end;
procedure tbPrintResult is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end procedure;
-- clock generation
procedure simStop is
begin
simStopped := TRUE;
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return simStopped;
end function;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, DutyCycle);
end procedure;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is
constant TIME_HIGH : TIME := Period * DutyCycle;
constant TIME_LOW : TIME := Period - TIME_HIGH;
begin
Clock <= '0';
while (not simStopped) loop
wait for TIME_LOW;
Clock <= '1';
wait for TIME_HIGH;
Clock <= '0';
end loop;
end procedure;
-- waveform generation
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
begin
return (0 => Pause, 1 => ResetPulse);
end function;
-- checksum functions
-- ===========================================================================
-- TODO: move checksum functions here
end package body;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue960/ent.vhdl | 1 | 389 | library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
clk : in std_logic
);
end;
architecture a of ent is
procedure inv(signal s : inout std_logic) is
begin
s <= not s;
end procedure;
signal test : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
inv(test);
end if;
end process;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug18359/testcase.vhdl | 3 | 652 | entity testcase is
end entity testcase;
architecture non_conformity of testcase is
function some_function return integer is
variable my : integer := 0;
begin
my := my + 1;
return my;
end function some_function;
begin
stuff: process
variable last_value : integer;
begin
for i in 1 to 4 loop
report "Count: " & integer'image(some_function)
severity NOTE;
end loop;
last_value := some_function;
assert last_value = 5
report "Counter's last value is " & integer'image(last_value)
& " but expected 5"
severity ERROR;
wait;
end process;
end architecture non_conformity;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/case01/tb_case01.vhdl | 1 | 559 | entity tb_case01 is
end tb_case01;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_case01 is
signal s : std_logic_vector (4 downto 0);
signal o : std_logic;
begin
dut: entity work.case01
port map (s, o);
process
constant ov : std_logic_vector (0 to 31) :=
b"00010011000010001100000000000000";
begin
for i in ov'range loop
s <= std_logic_vector(to_unsigned(i, 5));
wait for 1 ns;
assert o = ov(i) severity failure;
end loop;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1498.vhd | 4 | 1758 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1498.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n01i01498ent IS
END c08s08b00x00p14n01i01498ent;
ARCHITECTURE c08s08b00x00p14n01i01498arch OF c08s08b00x00p14n01i01498ent IS
BEGIN
TESTING: PROCESS
variable k : integer ;
variable p : integer := 5;
variable q : integer ;
BEGIN
case p is
when k => NULL;
when q => NULL;
when others => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p14n01i01498 - Simple expression is not static"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n01i01498arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket18/psl_test_error.vhd | 3 | 1067 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_error is
end entity psl_test_error;
architecture test of psl_test_error is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 100 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING PSL_TEST_ERROR test case";
report "================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
-- -psl statements
-- psl default clock is rising_edge(s_clk);
-- this don't work (error while analyse)
-- psl assert always (s_write -> not(s_read)) report "ERROR: s_write and s_read active @ same time!";
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug097/tb.vhdl | 1 | 320 | entity tb is
end tb;
architecture behav of tb is
function get_rand return integer;
attribute foreign of get_rand: function is "VHPIDIRECT ./getrand.so get_rand";
function get_rand return integer is
begin
assert false severity failure;
end get_rand;
begin
assert get_rand >= 0 severity note;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_07.vhd | 4 | 2491 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_07.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity top is
end entity top;
architecture top_arch of top is
signal top_sig : -- . . .; -- 1
--
bit;
--
begin
stimulus : process
is
variable var : -- . . .; -- 2
--
bit;
--
begin
-- . . .
--
report "--1: " & top'path_name;
report "--1: " & top'instance_name;
report "--1: " & top_sig'path_name;
report "--1: " & top_sig'instance_name;
report "--2: " & stimulus'path_name;
report "--2: " & stimulus'instance_name;
report "--2: " & var'path_name;
report "--2: " & var'instance_name;
wait;
--
end process stimulus;
rep_gen : for index in 0 to 7 generate
begin
end_gen : if index = 7 generate
signal end_sig : -- . . .; -- 3
--
bit;
--
begin
-- . . .
assert false report "--3: " & end_sig'path_name;
assert false report "--3: " & end_sig'instance_name;
--
end generate end_gen;
other_gen : if index /= 7 generate
signal other_sig : -- . . .; -- 4
--
bit;
--
begin
other_comp : entity work.bottom(bottom_arch)
port map ( -- . . . );
--
port_name => open );
assert false report "--4: " & other_sig'path_name;
assert false report "--4: " & other_sig'instance_name;
--
end generate other_gen;
end generate rep_gen;
end architecture top_arch;
| gpl-2.0 |
tgingold/ghdl | libraries/ieee2008/std_logic_1164.vhdl | 2 | 14971 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_1164 package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (PAR 1164),
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1228 $
-- $Date: 2008-04-30 10:04:53 +0930 (Wed, 30 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
package std_logic_1164 is
-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
type STD_ULOGIC is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
-------------------------------------------------------------------
-- unconstrained array of std_ulogic for use with the resolution function
-- and for use in declaring signal arrays of unresolved elements
-------------------------------------------------------------------
type STD_ULOGIC_VECTOR is array (NATURAL range <>) of STD_ULOGIC;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- logic state system (resolved)
-------------------------------------------------------------------
subtype STD_LOGIC is resolved STD_ULOGIC;
-------------------------------------------------------------------
-- unconstrained array of resolved std_ulogic for use in declaring
-- signal arrays of resolved elements
-------------------------------------------------------------------
subtype STD_LOGIC_VECTOR is (resolved) STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- common subtypes
-------------------------------------------------------------------
subtype X01 is resolved STD_ULOGIC range 'X' to '1'; -- ('X','0','1')
subtype X01Z is resolved STD_ULOGIC range 'X' to 'Z'; -- ('X','0','1','Z')
subtype UX01 is resolved STD_ULOGIC range 'U' to '1'; -- ('U','X','0','1')
subtype UX01Z is resolved STD_ULOGIC range 'U' to 'Z'; -- ('U','X','0','1','Z')
-------------------------------------------------------------------
-- overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "not" (l : STD_ULOGIC) return UX01;
-------------------------------------------------------------------
-- vectorized overloaded logical operators
-------------------------------------------------------------------
function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- shift operators
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT;
function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR;
function To_StdULogic (b : BIT) return STD_ULOGIC;
function To_StdLogicVector (b : BIT_VECTOR) return STD_LOGIC_VECTOR;
function To_StdLogicVector (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function To_StdULogicVector (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_StdULogicVector (s : STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
alias To_Bit_Vector is
To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias To_BV is
To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01 (s : STD_ULOGIC) return X01;
function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01 (b : BIT) return X01;
function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01Z (s : STD_ULOGIC) return X01Z;
function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01Z (b : BIT) return X01Z;
function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_UX01 (s : STD_ULOGIC) return UX01;
function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_UX01 (b : BIT) return UX01;
function "??" (l : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN;
function falling_edge (signal s : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN;
function Is_X (s : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- matching relational operators
-------------------------------------------------------------------
-- the following operations are predefined
-- function "?=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- function "?/=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?/=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- function "?<" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?<=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?>" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?>=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-------------------------------------------------------------------
-- string conversion and write operations
-------------------------------------------------------------------
-- the following operations are predefined
-- function TO_STRING (value : STD_ULOGIC) return STRING;
-- function TO_STRING (value : STD_ULOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
end package std_logic_1164;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1428.vhd | 4 | 1705 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1428.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s06b00x00p06n01i01428ent IS
END c08s06b00x00p06n01i01428ent;
ARCHITECTURE c08s06b00x00p06n01i01428arch OF c08s06b00x00p06n01i01428ent IS
procedure check(x : in integer; y : in boolean) is
begin
end;
signal k : real;
signal q : boolean;
BEGIN
TESTING: PROCESS
BEGIN
L1 : check(k,q);
assert FALSE
report "***FAILED TEST: c08s06b00x00p06n01i01428 - Type of argument incompatible with type of parameter"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s06b00x00p06n01i01428arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2028.vhd | 4 | 1767 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2028.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02028ent IS
END c07s02b04x00p01n01i02028ent;
ARCHITECTURE c07s02b04x00p01n01i02028arch OF c07s02b04x00p01n01i02028ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
variable LOGICV : LOGIC_SWITCH := '0';
BEGIN
LOGICV := LOGICV - '0';
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02028 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02028arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2534.vhd | 4 | 1846 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2534.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p13n02i02534ent IS
END c07s03b05x00p13n02i02534ent;
ARCHITECTURE c07s03b05x00p13n02i02534arch OF c07s03b05x00p13n02i02534ent IS
type Memory is array (Integer range <>) of Integer;
subtype T1 is Memory (1 to 6) ;
subtype T2 is Memory (2 to 4) ;
BEGIN
TESTING: PROCESS
variable V1 : T1 ;
variable V2 : T2 := (2,3,6) ;
BEGIN
V1 := Memory (V2) ; -- Failure_here
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p13n02i02534 - Bounds of the result are different from the index subtype of the target."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p13n02i02534arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_05a.vhd | 4 | 1080 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05a is
end entity inline_05a;
architecture test of inline_05a is
-- code from book
type domain_type is (quiescent_domain, time_domain, frequency_domain);
signal domain : domain_type := quiescent_domain;
-- end code from book
begin
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket61/bug.vhdl | 3 | 1165 | entity ent is
end entity;
architecture a of ent is
begin
main : process is
constant c : boolean := false;
variable v : boolean;
type enum is (a, b, short, \Extended\, \Weird\\Name\);
variable e : enum;
begin
report to_string(c); -- Cause TYPES.INTERNAL_ERROR
report to_string(false); -- Cause TYPES.INTERNAL_ERROR
report to_string(integer'(1)); -- Cause TYPES.INTERNAL_ERROR
report to_string(v); -- Works
report to_string(\Extended\);
report to_string(\Weird\\Name\);
assert to_string(CR) = (1 => CR) severity failure;
assert to_string(integer'(1)) = "1" severity failure;
assert to_string(integer'(-12)) = "-12" severity failure;
assert to_string(FaLse) = "false" severity failure;
assert to_string (\Extended\) = "Extended" severity failure;
assert to_string(\Weird\\Name\) = "Weird\Name" severity failure;
assert enum'image(\Weird\\Name\) = "\Weird\\Name\" severity failure;
e := \Weird\\Name\;
assert enum'image(e) = "\Weird\\Name\" severity failure;
report to_string(e);
assert to_string(e) = "Weird\Name" severity failure;
wait;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue45/endpoint_eval.vhdl | 2 | 1184 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
entity psl_endpoint_eval_in_vhdl is
end entity psl_endpoint_eval_in_vhdl;
architecture test of psl_endpoint_eval_in_vhdl is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 100 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING psl_endpoint_eval_in_vhdl test case";
report "==========================================";
s_write <= '0'; -- named assertion should hit
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1';
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait until rising_edge(s_clk);
stop(0);
wait;
end process TestP;
-- psl default clock is rising_edge(s_clk);
-- psl endpoint E_TEST0 is {not(s_write); s_write};
process is
begin
wait until E_TEST0;
report "HIT";
wait;
end process;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2266.vhd | 4 | 3909 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2266.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p11n01i02266ent IS
END c07s02b06x00p11n01i02266ent;
ARCHITECTURE c07s02b06x00p11n01i02266arch OF c07s02b06x00p11n01i02266ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable A, B : INTEGER;
variable OKtest : INTEGER := 0;
BEGIN
-- Test integer division.
-- 1. Both positive.
for A in 0 to 20 loop
for B in 1 to 20 loop
if NOT(((-A)/B) = -(A/B)) then
OKtest := 1;
end if;
assert (((-A)/B) = -(A/B))
report "Integer Division operation has failed for positive integers.";
if NOT((A/(-B)) = -(A/B)) then
OKtest := 1;
end if;
assert ((A/(-B)) = -(A/B))
report "Integer Division operation has failed for positive integers.";
end loop;
end loop;
-- 2. A negative, B positive.
for A in -1 downto -20 loop
for B in 1 to 20 loop
if NOT(((-A)/B) = -(A/B)) then
OKtest := 1;
end if;
assert (((-A)/B) = -(A/B))
report "Integer Division operation has failed for positive integers.";
if NOT((A/(-B)) = -(A/B)) then
OKtest := 1;
end if;
assert ((A/(-B)) = -(A/B))
report "Integer Division operation has failed for positive integers.";
end loop;
end loop;
-- 3. A positive, B negative.
for A in 0 to 20 loop
for B in -1 downto -20 loop
if NOT(((-A)/B) = -(A/B)) then
OKtest := 1;
end if;
assert (((-A)/B) = -(A/B))
report "Integer Division operation has failed for positive integers.";
if NOT((A/(-B)) = -(A/B)) then
OKtest := 1;
end if;
assert ((A/(-B)) = -(A/B))
report "Integer Division operation has failed for positive integers.";
end loop;
end loop;
-- 4. Both negative.
for A in -1 downto -20 loop
for B in -1 downto -20 loop
if NOT(((-A)/B) = -(A/B)) then
OKtest := 1;
end if;
assert (((-A)/B) = -(A/B))
report "Integer Division operation has failed for positive integers.";
if NOT((A/(-B)) = -(A/B)) then
OKtest := 1;
end if;
assert ((A/(-B)) = -(A/B))
report "Integer Division operation has failed for positive integers.";
end loop;
end loop;
wait for 5 ns;
assert NOT(OKtest = 0)
report "***PASSED TEST: c07s02b06x00p11n01i02266"
severity NOTE;
assert (OKtest = 0)
report "***FAILED TEST: c07s02b06x00p11n01i02266 - Integer division should satisfy the following identity: (-A)/B = -(A/B) = A/(-B)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p11n01i02266arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd | 4 | 3435 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity scheduler is
end entity scheduler;
architecture test of scheduler is
constant scheduling_delay : delay_length := 5 ns;
subtype request_type is natural range 0 to 20;
type server_status_type is (ready, busy);
signal first_priority_request,
first_normal_request,
reset_request : request_type := 0;
signal functional_request, equivalent_request : request_type;
signal priority_waiting : boolean := false;
signal server_status : server_status_type := busy;
begin
functional_scheduler : block is
port ( request : out request_type );
port map ( request => functional_request );
begin
-- code from book
scheduler :
request <= first_priority_request after scheduling_delay
when priority_waiting and server_status = ready else
first_normal_request after scheduling_delay
when not priority_waiting and server_status = ready else
unaffected
when server_status = busy else
reset_request after scheduling_delay;
-- end code from book
end block functional_scheduler;
--------------------------------------------------
equivalent_scheduler : block is
port ( request : out request_type );
port map ( request => equivalent_request );
begin
-- code from book
scheduler : process is
begin
if priority_waiting and server_status = ready then
request <= first_priority_request after scheduling_delay;
elsif not priority_waiting and server_status = ready then
request <= first_normal_request after scheduling_delay;
elsif server_status = busy then
null;
else
request <= reset_request after scheduling_delay;
end if;
wait on first_priority_request, priority_waiting, server_status,
first_normal_request, reset_request;
end process scheduler;
-- end code from book
end block equivalent_scheduler;
--------------------------------------------------
stimulus : process is
begin
first_priority_request <= 10; wait for 20 ns;
first_normal_request <= 5; wait for 20 ns;
server_status <= ready; wait for 20 ns;
server_status <= busy; wait for 20 ns;
priority_waiting <= true; wait for 20 ns;
server_status <= ready; wait for 20 ns;
first_normal_request <= 7; wait for 20 ns;
first_priority_request <= 12; wait for 20 ns;
wait;
end process stimulus;
verifier :
assert functional_request = equivalent_request
report "Functional and equivalent models give different results";
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_17.vhd | 4 | 1777 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_17.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package voltage_defs is
type voltage is range -2e9 to +2e9
units
nV;
uV = 1000 nV;
mV = 1000 uV;
V = 1000 mV;
end units voltage;
attribute resolution : real;
attribute resolution of nV : units is 1.0;
attribute resolution of uV : units is 0.01;
attribute resolution of mV : units is 0.01;
attribute resolution of V : units is 0.001;
end package voltage_defs;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd | 4 | 1057 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_02a is
end entity inline_02a;
----------------------------------------------------------------
library wasp_lib;
-- code from book:
use wasp_lib.all;
-- end of code from book
architecture test of inline_02a is
begin
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2471.vhd | 4 | 2058 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2471.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02471ent IS
END c07s03b02x02p03n02i02471ent;
ARCHITECTURE c07s03b02x02p03n02i02471arch OF c07s03b02x02p03n02i02471ent IS
BEGIN
TESTING: PROCESS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 4 );
function F return CONSTRAINED_ARRAY is
begin
return CONSTRAINED_ARRAY'(others => '7');
-- check in function return statement.
end F;
variable k : CONSTRAINED_ARRAY;
BEGIN
k := F;
wait for 5 ns;
assert NOT(k = "7777")
report "***PASSED TEST: c07s03b02x02p03n02i02471"
severity NOTE;
assert (k = "7777")
report "***FAILED TEST: c07s03b02x02p03n02i02471 - Others cannot be used with an unconstrained array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02471arch;
| gpl-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.