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tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-src.vhd | 4 | 1904 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-src.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use std.textio.all;
use qsim.qsim_types.all;
use random.random.all;
architecture source of test_bench is
signal a : arc_type;
signal info_detail : info_detail_type := trace;
begin
source1 : entity qsim.source(behavior)
generic map ( name => "source1",
distribution => fixed, mean_inter_arrival_time => 100 ns,
seed => sample_seeds(0),
time_unit => ns,
info_file_name => "source1.dat" )
port map ( out_arc => a,
info_detail => info_detail );
monitor : process is
variable L : line;
begin
wait on a;
write(L, string'("monitor: at "));
write(L, now, unit => ns);
write(L, string'(" received "));
write(L, a.token, ns);
writeline(output, L);
end process monitor;
end architecture source;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_24.vhd | 4 | 1379 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_24.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ROM is
port ( address : in natural;
data : out bit_vector(0 to 7);
enable : in bit );
begin
trace_reads : process (enable) is
begin
if enable = '1' then
report "ROM read at time " & time'image(now)
& " from address " & natural'image(address);
end if;
end process trace_reads;
end entity ROM;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2612.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2612.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02612ent IS
END c13s03b01x00p02n01i02612ent;
ARCHITECTURE c13s03b01x00p02n01i02612arch OF c13s03b01x00p02n01i02612ent IS
BEGIN
TESTING: PROCESS
variable k#k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02612 - Identifier can not contain '#'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02612arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd | 4 | 1121 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
configuration controller_with_timing of control_section is
for structural
for flag_reg : reg
generic map ( t_setup => 200 ps, t_hold => 150 ps,
t_pd => 150 ps, width => width )
port map ( reset_n => '1' );
end for;
-- . . .
end for;
end configuration controller_with_timing;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/vector.d/cmp_133.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_133 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_133;
architecture augh of cmp_133 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc283.vhd | 4 | 1806 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc283.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p10n01i00283ent IS
END c03s01b03x00p10n01i00283ent;
ARCHITECTURE c03s01b03x00p10n01i00283arch OF c03s01b03x00p10n01i00283ent IS
type J is -- physical type decl
range 0 to 1000
units
A;
B = 10 A;
C = 10.1 B; -- Failure_here
D = 10 C;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p10n01i00283 - Abstract literal portion of a physical literal appearing in a secondary unit declaration must be integer literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p10n01i00283arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1030.vhd | 4 | 2272 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1030.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p02n01i01030ent IS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type A2 is array (THREE, THREE) of BOOLEAN;
type A3 is array (THREE) of A1;
type R1 is record
RE1: A1;
end record;
type R2 is record
RE2: A2;
end record;
type R3 is record
RE3: A3;
end record;
END c06s04b00x00p02n01i01030ent;
ARCHITECTURE c06s04b00x00p02n01i01030arch OF c06s04b00x00p02n01i01030ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
variable V1: R1 ; -- := (RE1=>(others=>TRUE));
variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));
variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
BEGIN
V := V3.RE3(1)(3);
assert NOT( V=false )
report "***PASSED TEST: c06s04b00x00p02n01i01030"
severity NOTE;
assert ( V=false )
report "***FAILED TEST: c06s04b00x00p02n01i01030 - The prefix of an indexed name can be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01030arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue972/test2.vhdl | 1 | 400 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
port(
d_in: in std_ulogic_vector(63 downto 0);
d_out: out std_ulogic_vector(63 downto 0)
);
end entity test2;
architecture behaviour of test2 is
begin
comb : process(all)
begin
d_out <= std_logic_vector(unsigned(d_in) + 4);
end process;
end architecture behaviour;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1876.vhd | 4 | 1830 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1876.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01876ent IS
END c07s01b00x00p08n01i01876ent;
ARCHITECTURE c07s01b00x00p08n01i01876arch OF c07s01b00x00p08n01i01876ent IS
type small_int is range 0 to 7;
signal s_int : small_int;
BEGIN
blk : block (s_int = 0)
begin
end block blk;
TESTING : PROCESS
variable car : small_int;
BEGIN
car := blk; --block labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01876 - Block labels are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01876arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1064/testrec.vhdl | 1 | 472 | library ieee;
use ieee.std_logic_1164.all;
entity testrec is
port (i : std_ulogic;
o : out std_ulogic);
end entity testrec;
architecture behaviour of testrec is
type rec is record
v : std_ulogic;
t : std_ulogic;
end record;
procedure zot(e: inout rec) is
begin
e.v := '0';
end;
begin
execute1_1: process(i)
variable v : rec;
begin
v.v := i;
v.t := i;
zot(v);
o <= v.v;
end process;
end architecture behaviour;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_07.vhd | 4 | 2461 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity fg_16_07 is
end entity fg_16_07;
architecture test of fg_16_07 is
constant reg0 : std_logic_vector(7 downto 0) := "00000000";
constant reg1 : std_logic_vector(7 downto 0) := "11111111";
signal dbus : std_logic_vector(7 downto 0);
signal reg_sel, read, reg_addr : X01 := '0';
begin
-- code from book
reg_read_selector : block (reg_sel = '1' and read = '1') is
begin
dbus <= reg0 when guard and reg_addr = '0' else
reg1 when guard and reg_addr = '1' else
"ZZZZZZZZ";
end block reg_read_selector;
-- end code from book
stimulus : process is
begin
reg_sel <= '1'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
reg_sel <= '0'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
reg_addr <= '1'; wait for 10 ns;
reg_sel <= '1'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/stmt01/forloop2.vhdl | 1 | 581 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity forloop2 is
port (vin: in STD_LOGIC_VECTOR (7 downto 0);
vout: out STD_LOGIC_VECTOR (3 downto 0);
clk: in STD_LOGIC);
end forloop2;
architecture behav of forloop2 is
begin
process (clk, vin)
variable count: unsigned (vout'range);
begin
if rising_edge (clk)
then
count := (others => '0');
for I in vin'range loop
count := count + unsigned'(0 => vin (i));
end loop;
vout <= std_logic_vector (count);
end if;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue613/t1.vhdl | 1 | 110 | entity t1 is
end entity;
architecture a of t1 is
constant SimulationTime_c : time := 0 fs;
begin
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/vector.d/w_split0.vhd | 2 | 1359 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split0 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w_split0;
architecture augh of w_split0 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (
"00000111", "00000111"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc958.vhd | 4 | 2326 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc958.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p02n01i00958ent IS
END c06s03b00x00p02n01i00958ent;
ARCHITECTURE c06s03b00x00p02n01i00958arch OF c06s03b00x00p02n01i00958ent IS
BEGIN
TESTING: PROCESS
type ONE is range 1 to 1;
type R0 is record X: ONE; RE: BOOLEAN; end record;
type R1 is record X: ONE; RE: R0; end record;
type R2 is record X: ONE; RE: R1; end record;
type R3 is record X: ONE; RE: R2; end record;
type R4 is record X: ONE; RE: R3; end record;
type R5 is record X: ONE; RE: R4; end record;
type R6 is record X: ONE; RE: R5; end record;
type R7 is record X: ONE; RE: R6; end record;
type R8 is record X: ONE; RE: R7; end record;
type R9 is record X: ONE; RE: R8; end record;
variable V1: R9;
BEGIN
assert NOT(V1.RE.RE.RE.RE.RE.RE.RE.RE.RE.RE = false)
report "***PASSED TEST: c06s03b00x00p02n01i00958"
severity NOTE;
assert (V1.RE.RE.RE.RE.RE.RE.RE.RE.RE.RE = false)
report "***FAILED TEST: c06s03b00x00p02n01i00958 - The selected name consists of a prefix, a dot (.), and a suffix."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p02n01i00958arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1253.vhd | 4 | 1672 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1253.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n02i01253ent IS
END c08s02b00x00p04n02i01253ent;
ARCHITECTURE c08s02b00x00p04n02i01253arch OF c08s02b00x00p04n02i01253ent IS
BEGIN
TESTING: PROCESS
variable k : real;
BEGIN
assert FALSE
report "Report this Note"
severity k;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n02i01253 - Predefined severity_level type with non-existent value"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n02i01253arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1371.vhd | 4 | 6575 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1371.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01371ent IS
END c08s05b00x00p03n01i01371ent;
ARCHITECTURE c08s05b00x00p03n01i01371arch OF c08s05b00x00p03n01i01371ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_rec3 : st_rec3 :=c_st_rec3_1 ;
--
BEGIN
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01371"
severity NOTE;
assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01371 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01371arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug073/adder_tb.vhdl | 1 | 1855 | -- A testbench has no ports.
entity adder_tb is
end adder_tb;
architecture behav of adder_tb is
-- Declaration of the component that will be instantiated.
component adder
port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
end component;
-- Specifies which entity is bound with the component.
for adder_0: adder use entity work.adder;
signal i0, i1, ci, s, co : bit;
begin
-- Component instantiation.
adder_0: adder port map (i0 => i0, i1 => i1, ci => ci,
s => s, co => co);
-- This process does the real job.
process
type pattern_type is record
-- The inputs of the adder.
i0, i1, ci : bit;
-- The expected outputs of the adder.
s, co : bit;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(('0', '0', '0', '0', '0'),
('0', '0', '1', '1', '0'),
('0', '1', '0', '1', '0'),
('0', '1', '1', '0', '1'),
('1', '0', '0', '1', '0'),
('1', '0', '1', '0', '1'),
('1', '1', '0', '0', '1'),
('1', '1', '1', '1', '1'));
begin
-- Check each pattern.
for i in patterns'range loop
-- Set the inputs.
i0 <= patterns(i).i0;
i1 <= patterns(i).i1;
ci <= patterns(i).ci;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert s = patterns(i).s
report "bad sum value" severity error;
assert co = patterns(i).co
report "bad carry out value" severity error;
end loop;
assert false report "end of test" severity note;
-- Wait forever; this will finish the simulation.
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3003.vhd | 4 | 1767 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3003.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p05n01i03003pkg is
end c02s06b00x00p05n01i03003pkg;
package body c02s06b00x00p05n01i03003 is --Failure here
end c02s06b00x00p05n01i03003;
ENTITY c02s06b00x00p05n01i03003ent IS
END c02s06b00x00p05n01i03003ent;
ARCHITECTURE c02s06b00x00p05n01i03003arch OF c02s06b00x00p05n01i03003ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p05n01i03003 - The simple name at the start of a package body must repeat the package identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p05n01i03003arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_08.vhd | 4 | 1531 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_fg_01_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behav of reg4 is
begin
storage : process is
variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
begin
if en = '1' and clk = '1' then
stored_d0 := d0;
stored_d1 := d1;
stored_d2 := d2;
stored_d3 := d3;
end if;
q0 <= stored_d0 after 5 ns;
q1 <= stored_d1 after 5 ns;
q2 <= stored_d2 after 5 ns;
q3 <= stored_d3 after 5 ns;
wait on d0, d1, d2, d3, en, clk;
end process storage;
end architecture behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_12.vhd | 4 | 1700 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_05_12 is
end entity fg_05_12;
architecture test of fg_05_12 is
signal a, z : bit;
begin
-- code from book
asym_delay : process (a) is
constant Tpd_01 : time := 800 ps;
constant Tpd_10 : time := 500 ps;
begin
if a = '1' then
z <= transport a after Tpd_01;
else -- a = '0'
z <= transport a after Tpd_10;
end if;
end process asym_delay;
-- end code from book
stimulus : process is
begin
a <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc508.vhd | 4 | 1819 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc508.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p06n02i00508ent IS
END c03s02b02x00p06n02i00508ent;
ARCHITECTURE c03s02b02x00p06n02i00508arch OF c03s02b02x00p06n02i00508ent IS
type date is
record
day : integer range 1 to 31;
month : integer range 1 to 12;
-- -- Failure_here: duplicate record field declaration
day : integer range -6000 to 6000;
end record;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b02x00p06n02i00508 -The identifiers of all elements of a record type must be distinct."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p06n02i00508arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue838/top.vhdl | 1 | 3336 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fpga_avalon_top is
port(
-- Zynq Clock/Reset
pl_fclk :in std_logic;
pl_areset_n :in std_logic;
-- AVALON S-Port
s_amm_wait :out std_logic;
s_amm_addr :in std_logic_vector(31 downto 0);
s_amm_byte_en :in std_logic_vector(1 downto 0);
s_amm_rd_en :in std_logic;
s_amm_rd_data :out std_logic_vector(31 downto 0);
s_amm_rd_valid :out std_logic;
s_amm_wr_en :in std_logic;
s_amm_wr_data :in std_logic_vector(31 downto 0);
s_amm_wr_resvld :out std_logic;
s_amm_response :out std_logic_vector(1 downto 0);
-- AVALON M-Port
m_amm_wait :in std_logic;
m_amm_addr :out std_logic_vector(31 downto 0);
m_amm_rd_en :out std_logic;
m_amm_rd_data :in std_logic_vector(31 downto 0);
m_amm_rd_valid :in std_logic;
m_amm_wr_en :out std_logic;
m_amm_wr_data :out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of fpga_avalon_top is
-- UNCOMMENT WHEN ADDING TO VIVADO, COMMENT-OUT WHEN SIMULATING IN GHDL:
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of s_amm_wait :SIGNAL is "xilinx.com:interface:avalon:1.0 s_amm WAITREQUEST";
ATTRIBUTE X_INTERFACE_INFO of s_amm_addr :SIGNAL is "xilinx.com:interface:avalon:1.0 s_amm ADDRESS";
ATTRIBUTE X_INTERFACE_INFO of s_amm_byte_en :SIGNAL is "xilinx.com:interface:avalon:1.0 s_amm BYTEENABLE";
ATTRIBUTE X_INTERFACE_INFO of s_amm_rd_en :SIGNAL is "xilinx.com:interface:avalon:1.0 s_amm READ";
ATTRIBUTE X_INTERFACE_INFO of s_amm_rd_data :SIGNAL is "xilinx.com:interface:avalon:1.0 s_amm READDATA";
ATTRIBUTE X_INTERFACE_INFO of s_amm_rd_valid :SIGNAL is "xilinx.com:interface:avalon:1.0 s_amm READDATAVALID";
ATTRIBUTE X_INTERFACE_INFO of s_amm_wr_en :SIGNAL is "xilinx.com:interface:avalon:1.0 s_amm WRITE";
ATTRIBUTE X_INTERFACE_INFO of s_amm_wr_data :SIGNAL is "xilinx.com:interface:avalon:1.0 s_amm WRITEDATA";
ATTRIBUTE X_INTERFACE_INFO of s_amm_wr_resvld :SIGNAL is "xilinx.com:interface:avalon:1.0 s_amm WRITERESPONSEVALID";
ATTRIBUTE X_INTERFACE_INFO of s_amm_response :SIGNAL is "xilinx.com:interface:avalon:1.0 s_amm RESPONSE";
ATTRIBUTE X_INTERFACE_INFO of m_amm_wait :SIGNAL is "xilinx.com:interface:avalon:1.0 m_amm WAITREQUEST";
ATTRIBUTE X_INTERFACE_INFO of m_amm_addr :SIGNAL is "xilinx.com:interface:avalon:1.0 m_amm ADDRESS";
ATTRIBUTE X_INTERFACE_INFO of m_amm_rd_en :SIGNAL is "xilinx.com:interface:avalon:1.0 m_amm READ";
ATTRIBUTE X_INTERFACE_INFO of m_amm_rd_data :SIGNAL is "xilinx.com:interface:avalon:1.0 m_amm READDATA";
ATTRIBUTE X_INTERFACE_INFO of m_amm_rd_valid :SIGNAL is "xilinx.com:interface:avalon:1.0 m_amm READDATAVALID";
ATTRIBUTE X_INTERFACE_INFO of m_amm_wr_en :SIGNAL is "xilinx.com:interface:avalon:1.0 m_amm WRITE";
ATTRIBUTE X_INTERFACE_INFO of m_amm_wr_data :SIGNAL is "xilinx.com:interface:avalon:1.0 m_amm WRITEDATA";
begin
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1803.vhd | 4 | 1923 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1803.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p05n01i01803ent IS
END c07s01b00x00p05n01i01803ent;
ARCHITECTURE c07s01b00x00p05n01i01803arch OF c07s01b00x00p05n01i01803ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 3;
variable y : integer := 5;
variable z : integer := 9;
BEGIN
if ((-x + z) < (y + x)) then -- NO_Failure_here
-- sign can appear before the first term.
x := y * z;
end if;
assert NOT(x = 45)
report "***PASSED TEST: c07s01b00x00p05n01i01803"
severity NOTE;
assert (x = 45)
report "***FAILED TEST: c07s01b00x00p05n01i01803 - Sign appear before the first term in a simple expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p05n01i01803arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CS3_BuckConverter_average.vhd | 4 | 22544 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : inductor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Electrical Inductor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity inductor is
generic (
ind : inductance; -- Nominal inductance
i_ic : real := real'low); -- Initial current (use IF statement below
-- to activate)
port (
terminal p1, p2 : electrical);
end entity inductor;
-------------------------------------------------------------------------------
-- Ideal Architecture (V = L * di/dt)
-- Includes initial condition
-------------------------------------------------------------------------------
architecture ideal of inductor is
-- Declare Branch Quantities
quantity v across i through p1 to p2;
begin
if domain = quiescent_domain and i_ic /= real'low use
i == i_ic;
else
v == ind * i'dot; -- characteristic equation
end use;
end architecture ideal;
architecture ideal2 of inductor is
-- Declare Branch Quantities
quantity v across i through p1 to p2;
begin
if domain = quiescent_domain and i_ic /= real'low use
i == i_ic;
else
v == ind * i'dot; -- characteristic equation
end use;
end architecture ideal2;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : capacitor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Electrical Capacitor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity capacitor is
generic ( cap : capacitance;
r_esr : resistance := 0.0;
v_ic : voltage := real'low );
port ( terminal p1, p2 : electrical );
end entity capacitor;
architecture esr of capacitor is
quantity v across i through p1 to p2;
quantity vc : voltage; -- Internal voltage across capacitor
begin
if domain = quiescent_domain and v_ic /= real'low use
vc == v_ic;
i == 0.0;
else
vc == v - (i * r_esr);
i == cap * vc'dot;
end use;
end architecture esr;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_constant.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/03
-------------------------------------------------------------------------------
-- Description: Constant Voltage Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_constant is
generic (
level : voltage; -- Constant voltage value [Volts]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_constant;
-------------------------------------------------------------------------------
-- Ideal Architecture (I = constant)
-------------------------------------------------------------------------------
architecture ideal of v_constant is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
if domain = quiescent_domain or domain = time_domain use
v == level;
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity sw_LoopCtrl_wa is
generic (r_open : resistance := 1.0e6;
r_closed : resistance := 1.0e-3;
sw_state : integer := 1);
port (terminal c, p1, p2 : electrical);
end entity sw_LoopCtrl_wa;
architecture ideal of sw_LoopCtrl_wa is
quantity v1 across i1 through c to p1;
quantity v2 across i2 through c to p2;
quantity r1, r2 : resistance;
begin
if (sw_state = 2) use
r1 == r_open;
r2 == r_closed;
else
r1 == r_closed;
r2 == r_open;
end use;
v1 == r1*i1;
v2 == r2*i2;
end architecture ideal;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity pwl_load_wa is
generic (
load_enable: string := "yes";
res_init : resistance;
res1 : resistance;
t1 : time;
res2 : resistance;
t2 : time);
port (terminal p1, p2 : electrical);
end entity pwl_load_wa;
architecture ideal of pwl_load_wa is
quantity v across i through p1 to p2;
signal res_signal : resistance := res_init;
begin
if load_enable = "yes" use
if domain = quiescent_domain or domain = frequency_domain use
v == i*res_init;
else
v == i*res_signal'ramp(1.0e-6, 1.0e-6);
end use;
else
i == 0.0;
end use;
-- purpose: Create Events to change resistance at specified times
-- type : combinational
-- inputs :
-- outputs: res
CreateEvent: process is
begin -- process CreateEvent
wait for t1;
res_signal <= res1;
wait for (t2-t1);
res_signal <= res2;
wait;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_pulse.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/09
-------------------------------------------------------------------------------
-- Description: Voltage Pulse Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
-- time. Uses time2real function.
-- Pulsewidth no longer includes
-- rise and fall times.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_pulse is
generic (
initial : voltage := 0.0; -- initial value [Volts]
pulse : voltage; -- pulsed value [Volts]
ti2p : time := 1ns; -- initial to pulse [Sec]
tp2i : time := 1ns; -- pulse to initial [Sec]
delay : time := 0ms; -- delay time [Sec]
width : time; -- duration of pulse [Sec]
period : time; -- period [Sec]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_pulse;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_pulse is
-- Declare Through and Across Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
-- Signal used in CreateEvent process below
signal pulse_signal : voltage := initial;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
-- Note: these lines gave an error during simulation. Had to use a
-- function call instead.
-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
-- Function to convert numbers of type TIME to type REAL
function time2real(tt : time) return real is
begin
return time'pos(tt) * 1.0e-15;
end time2real;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
constant ri2p : real := time2real(ti2p);
constant rp2i : real := time2real(tp2i);
begin
if domain = quiescent_domain or domain = time_domain use
v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
-- purpose: Create events to define pulse shape
-- type : combinational
-- inputs :
-- outputs: pulse_signal
CreateEvent : process
begin
wait for delay;
loop
pulse_signal <= pulse;
wait for (width + ti2p);
pulse_signal <= initial;
wait for (period - width - ti2p);
end loop;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity buck_sw is
generic (
Vd : voltage := 0.7; -- Diode Voltage
Vramp : voltage := 2.5); -- P-P amplitude of ramp voltage
port (terminal input, output, ref, ctrl: electrical);
end entity buck_sw;
architecture average of buck_sw is
quantity Vout across Iout through output to ref;
quantity Vin across input to ref;
quantity Vctrl across ctrl to ref;
begin
Vout + Vd == Vctrl * Vin / Vramp; -- Averaged equation
end architecture average;
library IEEE;
library IEEE_proposed;
use ieee.math_real.all;
use IEEE_proposed.electrical_systems.all;
entity comp_2p2z is
generic (
gain : real := 100.0; -- High DC gain for good load regulation
fp1 : real := 7.5e3; -- Pole location to achieve crossover frequency
fp2 : real := 531.0e3;-- Pole location to cancel effect of ESR
fz1 : real := 403.0; -- Zero locations to cancel LC filter poles
fz2 : real := 403.0);
port (terminal input, output, ref : electrical);
end entity comp_2p2z;
architecture ltf of comp_2p2z is
quantity vin across input to ref;
quantity vout across iout through output to ref;
constant wp1 : real := math_2_pi*fp1; -- Pole freq (in radians)
constant wp2 : real := math_2_pi*fp2;
constant wz1 : real := math_2_pi*fz1; -- Zero freq (in radians)
constant wz2 : real := math_2_pi*fz2;
constant num : real_vector := (1.0, (wz1+wz2)/(wz1*wz2), 1.0/(wz1*wz2));
constant den : real_vector := (1.0e-9, 1.0, (wp1+wp2)/(wp1*wp2), 1.0/(wp1*wp2));
begin
vout == -1.0*gain*vin'ltf(num, den);
end architecture ltf;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS3_BuckConverter_average is
end TB_CS3_BuckConverter_average;
architecture TB_CS3_BuckConverter_average of TB_CS3_BuckConverter_average is
-- Component declarations
-- Signal declarations
terminal vcomp_out : electrical;
terminal vctrl : electrical;
terminal vctrl_init : electrical;
terminal vin : electrical;
terminal vmid : electrical;
terminal vout : electrical;
terminal vref : electrical;
begin
-- Signal assignments
-- Component instances
L1 : entity work.inductor(ideal)
generic map(
ind => 6.5e-3
)
port map(
p1 => vmid,
p2 => vout
);
C1 : entity work.capacitor(ESR)
generic map(
cap => 6.0e-6,
r_esr => 50.0e-3
)
port map(
p1 => vout,
p2 => ELECTRICAL_REF
);
Vctrl_1 : entity work.v_constant(ideal)
generic map(
level => 0.327
)
port map(
pos => vctrl_init,
neg => ELECTRICAL_REF
);
Vref_1 : entity work.v_constant(ideal)
generic map(
level => 4.8
)
port map(
pos => vref,
neg => ELECTRICAL_REF
);
sw2 : entity work.sw_LoopCtrl_wa(ideal)
generic map(
sw_state => 1
)
port map(
p2 => vctrl_init,
c => vctrl,
p1 => vcomp_out
);
Electrical_Load6 : entity work.pwl_load_wa(ideal)
generic map(
t2 => 30 ms,
res2 => 5.0,
t1 => 5ms,
res1 => 1.0,
res_init => 2.4,
load_enable => "yes"
)
port map(
p1 => vout,
p2 => ELECTRICAL_REF
);
Vin_1 : entity work.v_pulse(ideal)
generic map(
initial => 42.0,
pulse => 42.0,
delay => 10ms,
width => 100ms,
period => 1000ms
)
port map(
pos => vin,
neg => ELECTRICAL_REF
);
buck_sw2 : entity work.buck_sw(average)
port map(
ctrl => vctrl,
input => vin,
ref => ELECTRICAL_REF,
output => vmid
);
comp_2p2z4 : entity work.comp_2p2z(ltf)
generic map(
fz1 => 403.0,
fz2 => 403.0,
gain => 100.0
)
port map(
input => vout,
output => vcomp_out,
ref => vref
);
end TB_CS3_BuckConverter_average;
--
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1466.vhd | 4 | 1638 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1466.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p02n01i01466ent IS
END c08s08b00x00p02n01i01466ent;
ARCHITECTURE c08s08b00x00p02n01i01466arch OF c08s08b00x00p02n01i01466ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 1;
BEGIN
case x is
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p02n01i01466 - missing case statement alternatives in case statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p02n01i01466arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3114.vhd | 4 | 3153 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3114.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b00x00p07n01i03114ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b00x00p07n01i03114ent_a;
ARCHITECTURE c05s02b00x00p07n01i03114arch_a OF c05s02b00x00p07n01i03114ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b00x00p07n01i03114arch_a;
configuration c05s02b00x00p07n01i03114cfg_a of c05s02b00x00p07n01i03114ent_a is
for c05s02b00x00p07n01i03114arch_a
end for;
end c05s02b00x00p07n01i03114cfg_a;
ENTITY c05s02b00x00p07n01i03114ent IS
END c05s02b00x00p07n01i03114ent;
ARCHITECTURE c05s02b00x00p07n01i03114arch OF c05s02b00x00p07n01i03114ent IS
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
for u1 : virtual use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
for others : virtual use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : virtual
generic map ( true )
port map (s1, s2);
u2 : virtual
generic map ( true )
port map (s2, s3);
u3 : virtual
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b00x00p07n01i03114"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b00x00p07n01i03114 - The use of the others clause did not properly configure an instance which has not been previously configured in a configuration specification in an architecture declarative region."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b00x00p07n01i03114arch;
configuration c05s02b00x00p07n01i03114cfg of c05s02b00x00p07n01i03114ent is
for c05s02b00x00p07n01i03114arch
end for;
end c05s02b00x00p07n01i03114cfg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc647.vhd | 4 | 2018 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY c03s04b01x00p01n01i00647ent IS
END c03s04b01x00p01n01i00647ent;
ARCHITECTURE c03s04b01x00p01n01i00647arch OF c03s04b01x00p01n01i00647ent IS
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_file is file of current;
constant C47 : current := 1 A;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : current_file open read_mode is "iofile.62";
variable v : current;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C47) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00647"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00647 - File reading operation (current_file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00647arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/vector.d/cmp_202.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_202 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_202;
architecture augh of cmp_202 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/sub_206.vhd | 2 | 1730 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_206 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_206;
architecture augh of sub_206 is
signal carry_inA : std_logic_vector(42 downto 0);
signal carry_inB : std_logic_vector(42 downto 0);
signal carry_res : std_logic_vector(42 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(41 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(40) & in_b(40) & carry_res(41);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
gt <= not(tmp_le);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1531.vhd | 4 | 2366 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1531.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p09n02i01531ent IS
END c08s09b00x00p09n02i01531ent;
ARCHITECTURE c08s09b00x00p09n02i01531arch OF c08s09b00x00p09n02i01531ent IS
BEGIN
TESTING: PROCESS
-- All different non-numeric type declarations.
-- enumerated types.
type COLORS is (RED, GREEN, BLUE);
type MYFAVS is (RED, YELLOW, GREEN);
-- variable declarations.
variable COLSLOW : COLORS := RED;
variable COLSHIGH : COLORS := GREEN;
variable FAVSLOW : MYFAVS := RED;
variable FAVSHIGH : MYFAVS := GREEN;
variable k : integer := 0;
BEGIN
-- This loop should be fine.
for I in COLSLOW to COLSHIGH loop
if not((I >= COLSLOW) and (I <= COLSHIGH)) then
k := 1;
end if;
end loop;
-- This loop should be fine.
for I in FAVSLOW to FAVSHIGH loop
if not((I >= FAVSLOW) and (I <= FAVSHIGH)) then
k := 1;
end if;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s09b00x00p09n02i01531"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s09b00x00p09n02i01531 - "
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p09n02i01531arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc490.vhd | 4 | 3550 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc490.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p01n01i00490ent IS
END c03s02b02x00p01n01i00490ent;
ARCHITECTURE c03s02b02x00p01n01i00490arch OF c03s02b02x00p01n01i00490ent IS
type T0 is record
el1 : real;
el2 : real;
el3 : real;
el4 : real;
el5 : real;
el6 : real;
el7 : real;
el8 : real;
el9 : real;
el10 : real;
end record;
type T1 is record
el1 : real;
el2 : real;
el3 : real;
el4 : real;
el5 : real;
el6 : real;
end record;
type T2 is record
el5 : real;
el6 : real;
el7 : real;
end record;
function FUNC1(signal recd1: T0) return T1 is
variable recd2:T1;
begin -- procedure FUNC1
recd2.el1 := recd1.el6;
recd2.el2 := recd1.el1;
recd2.el3 := recd1.el3;
recd2.el4 := recd1.el2;
recd2.el5 := recd1.el6;
recd2.el6 := recd1.el10;
return recd2;
end FUNC1;
function FUNC3(signal recd1: T0) return T2 is
variable recd2:T2;
begin -- procedure FUNC3
recd2.el5 := recd1.el5;
recd2.el6 := recd1.el6;
recd2.el7 := recd1.el1;
return recd2;
end FUNC3;
function FUNC4(signal recd1: T2) return T2 is
variable recd2:T2;
begin -- procedure FUNC4
recd2.el5 := recd1.el7;
recd2.el6 := recd1.el5;
recd2.el7 := recd1.el5;
return recd2;
end FUNC4;
signal rec1: T0;
signal s1,v2:T1;
signal s3,s4:T2;
BEGIN
TESTING: PROCESS
BEGIN
rec1 <= (1.1,2.2,3.3,4.4,5.5,6.6,7.7,8.8,9.9,10.01);
wait for 1 ns;
s1 <= FUNC1(rec1);
s3 <= FUNC3(rec1);
wait for 1 ns;
s4 <= FUNC4(s3);
wait for 1 ns;
assert NOT( (s1 = (6.6,1.1,3.3,2.2,6.6,10.01)) AND
(s3 = (5.5,6.6,1.1)) AND
(s4 = (1.1,5.5,5.5)))
report "***PASSED TEST: c03s02b02x00p01n01i00490"
severity NOTE;
assert ( (s1 = (6.6,1.1,3.3,2.2,6.6,10.01)) AND
(s3 = (5.5,6.6,1.1)) AND
(s4 = (1.1,5.5,5.5)))
report "***FAILED TEST: c03s02b02x00p01n01i00490 - Values of a record object consist of the value of its elements."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p01n01i00490arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue309/tb.vhdl | 12226531 | 0 | gpl-2.0 |
|
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-ztex-ufm-115/leon3mp.vhd | 1 | 16905 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
library unisim;
use unisim.vcomponents.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk48 : in std_ulogic;
errorn : out std_logic;
-- DDR SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n: inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
dsuact : out std_ulogic; -- Debug Unit break (connect to button)
-- AHB UART (debug link)
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- SD card
sd_dat : inout std_logic;
sd_cmd : inout std_logic;
sd_sck : inout std_logic;
sd_dat3 : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal clk200 : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal cgo_ddr : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 48000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk48_pad : clkpad generic map (tech => padtech) port map (clk48, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
clkgen_ddr : clkgen
generic map (fabtech, 25, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clk200, open, open, open, open, cgi, cgo_ddr, open, open, open);
ddrc : entity work.ahb2mig_ztex generic map(
hindex => 4, haddr => 16#400#, hmask => CFG_MIG_HMASK,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem => clk200,
test_error => open
);
end generate;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- General purpose timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
-- NOTE:
-- GPIO pads are not instantiated here. If you want to use
-- GPIO then add a top-level port, update the UCF and
-- instantiate pads for the GPIO lines as is done in other
-- template designs.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => CFG_SPICTRL_ODMODE,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_sck, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
nospic: if CFG_SPICTRL_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for ZTEX USB-FPGA Module 1.15",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/gencomp/gencomp.vhd | 1 | 84202 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: gencomp
-- File: gencomp.vhd
-- Author: Jiri Gaisler et al. - Aeroflex Gaisler
-- Description: Declaration of portable memory modules, pads, e.t.c.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config.grlib_config_array;
use grlib.config_types.grlib_techmap_testin_extra;
package gencomp is
---------------------------------------------------------------------------
-- BASIC DECLARATIONS
---------------------------------------------------------------------------
-- technologies and libraries
constant NTECH : integer := 54;
type tech_ability_type is array (0 to NTECH) of integer;
constant inferred : integer := 0;
constant virtex : integer := 1;
constant virtex2 : integer := 2;
constant memvirage : integer := 3;
constant axcel : integer := 4;
constant proasic : integer := 5;
constant atc18s : integer := 6;
constant altera : integer := 7;
constant umc : integer := 8;
constant rhumc : integer := 9;
constant apa3 : integer := 10;
constant spartan3 : integer := 11;
constant ihp25 : integer := 12;
constant rhlib18t : integer := 13;
constant virtex4 : integer := 14;
constant lattice : integer := 15;
constant ut25 : integer := 16;
constant spartan3e : integer := 17;
constant peregrine : integer := 18;
constant memartisan : integer := 19;
constant virtex5 : integer := 20;
constant custom1 : integer := 21;
constant ihp25rh : integer := 22;
constant stratix1 : integer := 23;
constant stratix2 : integer := 24;
constant eclipse : integer := 25;
constant stratix3 : integer := 26;
constant cyclone3 : integer := 27;
constant memvirage90 : integer := 28;
constant tsmc90 : integer := 29;
constant easic90 : integer := 30;
constant atc18rha : integer := 31;
constant smic013 : integer := 32;
constant tm65gplus : integer := 33;
constant axdsp : integer := 34;
constant spartan6 : integer := 35;
constant virtex6 : integer := 36;
constant actfus : integer := 37;
constant stratix4 : integer := 38;
constant st65lp : integer := 39;
constant st65gp : integer := 40;
constant easic45 : integer := 41;
constant cmos9sf : integer := 42;
constant apa3e : integer := 43;
constant apa3l : integer := 44;
constant ut130 : integer := 45;
constant ut90 : integer := 46;
constant gf65 : integer := 47;
constant virtex7 : integer := 48;
constant kintex7 : integer := 49;
constant artix7 : integer := 50;
constant zynq7000 : integer := 51;
constant rhlib13t : integer := 52;
constant saed32 : integer := 53;
constant dare : integer := 54;
constant DEFMEMTECH : integer := inferred;
constant DEFPADTECH : integer := inferred;
constant DEFFABTECH : integer := inferred;
constant is_fpga : tech_ability_type :=
(inferred => 1, virtex => 1, virtex2 => 1, axcel => 1,
proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 1, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 1,
stratix3 => 1, cyclone3 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1,
stratix4 => 1, apa3e => 1, apa3l => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1,
others => 0);
constant infer_mul : tech_ability_type := is_fpga;
constant syncram_2p_write_through : tech_ability_type :=
(rhumc => 1, eclipse => 1, others => 0);
constant regfile_3p_write_through : tech_ability_type :=
(rhumc => 1, ihp25 => 1, ihp25rh => 1, eclipse => 1, others => 0);
constant regfile_3p_infer : tech_ability_type :=
(inferred => 1, rhumc => 1, ihp25 => 1, rhlib18t => 0, ut90 => 1,
peregrine => 1, ihp25rh => 1, umc => 1, custom1 => 0, others => 0);
constant syncram_2p_dest_rw_collision : tech_ability_type :=
(memartisan => 1, smic013 => 1, easic45 => 1, ut130 => 1, others => 0);
constant syncram_dp_dest_rw_collision : tech_ability_type :=
(memartisan => 1, smic013 => 1, easic45 => 1, others => 0);
constant syncram_has_customif : tech_ability_type := (others => 0);
constant syncram_customif_maxwidth: integer := 64; -- Expand as needed
constant has_sram : tech_ability_type :=
(atc18s => 0, others => 1);
constant has_2pram : tech_ability_type :=
( atc18s => 0, umc => 0, rhumc => 0, ihp25 => 0, others => 1);
constant has_dpram : tech_ability_type :=
(virtex => 1, virtex2 => 1, memvirage => 1, axcel => 0,
altera => 1, apa3 => 1, spartan3 => 1, virtex4 => 1,
lattice => 1, spartan3e => 1, memartisan => 1, virtex5 => 1,
custom1 => 1, stratix1 => 1, stratix2 => 1, stratix3 => 1,
cyclone3 => 1, memvirage90 => 1, atc18rha => 1, smic013 => 1,
tm65gplus => 1, axdsp => 0, spartan6 => 1, virtex6 => 1,
actfus => 1, stratix4 => 1, easic45 => 1, apa3e => 1,
apa3l => 1, ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, dare => 1, others => 0);
constant has_sram64 : tech_ability_type :=
(inferred => 0, virtex2 => 1, spartan3 => 1, virtex4 => 1,
spartan3e => 1, memartisan => 1, virtex5 => 1, smic013 => 1,
spartan6 => 1, virtex6 => 1, easic45 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant has_sram128bw : tech_ability_type := (
virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1,
spartan3e => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
altera => 1, cyclone3 => 1, stratix2 => 1, stratix3 => 1, stratix4 => 1,
ut90 => 1, others => 0);
constant has_sram128 : tech_ability_type := (
virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1,
spartan3e => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
tm65gplus => 0, easic45 => 1, others => 0);
constant has_sram156bw : tech_ability_type := (
virtex2 => 0, virtex4 => 0, virtex5 => 0, spartan3 => 0,
spartan3e => 0, spartan6 => 0, virtex6 => 0, virtex7 => 0, kintex7 => 0,
altera => 0, cyclone3 => 0, stratix2 => 0, stratix3 => 0, stratix4 => 0,
tm65gplus => 0, custom1 => 1, ut90 => 1, others => 0);
constant has_sram256bw : tech_ability_type := (
virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1,
spartan3e => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
altera => 1, cyclone3 => 1, stratix2 => 1, stratix3 => 1, stratix4 => 1,
tm65gplus => 0, cmos9sf => 1, others => 0);
constant has_sram_2pbw : tech_ability_type := (
easic45 => 1, others => 0);
constant has_srambw : tech_ability_type := (easic45 => 1, others => 0);
-- ram_raw_latency - describes how many edges on the write-port clock that
-- must pass before data is commited to memory. for example, if the write data
-- is commited to memory on the falling edge after a write cycle, and is
-- available to the read port after a short T_{raw} then ram_raw_latency
-- should be set to 1. If the data is available to the read port immediately
-- after the write-port clock rising edge that latches the write operation then
-- ram_raw_latency(tech) should return 0. If T_{raw} cannot be assumed to be
-- negligible (for instance, it is longer than a clock cycle on the read port)
-- then the ram_raw_latency value should be increased to cover also T_{raw}.
-- this value is important for cores that use DP or 2P memories in CDC.
constant ram_raw_latency : tech_ability_type := (easic45 => 1, others => 0);
constant padoen_polarity : tech_ability_type :=
(axcel => 1, proasic => 1, umc => 1, rhumc => 1, saed32 => 1, dare => 1, apa3 => 1,
ihp25 => 1, ut25 => 1, peregrine => 1, easic90 => 1, axdsp => 1,
actfus => 1, apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
ut90 => 1, others => 0);
constant has_pads : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
axcel => 1, proasic => 1, atc18s => 1, altera => 0,
umc => 1, rhumc => 1, saed32 => 1, dare => 1, apa3 => 1, spartan3 => 1,
ihp25 => 1, rhlib18t => 1, virtex4 => 1, lattice => 0,
ut25 => 1, spartan3e => 1, peregrine => 1, virtex5 => 1, axdsp => 1,
easic90 => 1, atc18rha => 1, spartan6 => 1, virtex6 => 1,
actfus => 1, apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
ut90 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant has_ds_pads : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
axcel => 1, proasic => 0, atc18s => 0, altera => 0,
umc => 0, rhumc => 0, saed32 => 0, dare => 0, apa3 => 1, spartan3 => 1,
ihp25 => 0, rhlib18t => 1, virtex4 => 1, lattice => 0,
ut25 => 1, spartan3e => 1, virtex5 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1,
apa3e => 1, apa3l => 1, ut130 => 0, easic45 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant has_ds_combo : tech_ability_type :=
( rhumc => 1, ut25 => 1, ut130 => 1, others => 0);
constant has_clkand : tech_ability_type :=
( virtex => 1, virtex2 => 1, spartan3 => 1, spartan3e => 1, virtex4 => 1,
virtex5 => 1, ut25 => 1, rhlib18t => 1,
spartan6 => 1, virtex6 => 1, ut130 => 1, easic45 => 1,
ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, saed32 => 1, dare => 1, others => 0);
constant has_clkmux : tech_ability_type :=
( virtex => 1, virtex2 => 1, spartan3 => 1, spartan3e => 1,
virtex4 => 1, virtex5 => 1, rhlib18t => 1,
spartan6 => 1, virtex6 => 1, ut130 => 1, easic45 => 1,
ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, saed32 => 1, dare => 1, rhumc => 1, others => 0);
constant has_clkinv : tech_ability_type :=
( saed32 => 1, dare => 1, others => 0);
constant has_techbuf : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1, axcel => 1, ut25 => 1,
apa3 => 1, easic90 => 1, axdsp => 1, actfus => 1,
apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
ut90 => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant has_tapsel : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1,
spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant tap_tck_gated : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1, spartan3e => 1,
spartan6 => 0, others => 0);
constant need_extra_sync_reset : tech_ability_type :=
(axcel => 1, atc18s => 1, ut25 => 1, rhumc => 1, saed32 => 1, dare => 1, tsmc90 => 1,
rhlib18t => 1, atc18rha => 1, easic90 => 1, tm65gplus => 1,
axdsp => 1, cmos9sf => 1, apa3 => 1, apa3e => 1, apa3l => 1,
ut130 => 1, easic45 => 1, ut90 => 1, others => 0);
constant is_unisim : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1,
spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, others => 0);
constant has_tap : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, axcel => 0,
proasic => 0, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 0, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 0,
stratix3 => 1, cyclone3 => 1, axdsp => 0,
spartan6 => 1, virtex6 => 1, actfus => 1,
stratix4 => 1, easic45 => 0, apa3e => 1, apa3l => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1,
others => 0);
constant has_clkgen : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, axcel => 1,
proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 0, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 0, rhumc => 1, saed32 => 1, dare => 1,
stratix3 => 1, cyclone3 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1, easic90 => 1,
stratix4 => 1, easic45 => 1, apa3e => 1, apa3l => 1,
rhlib18t => 1, ut130 => 1, ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, others => 0);
constant has_ddr2phy: tech_ability_type :=
(inferred => 0, stratix2 => 1, stratix3 => 1, spartan3 => 1,
easic90 => 1, spartan6 => 1, easic45 => 1,
virtex4 => 1, virtex5 => 1, virtex6 => 1, others => 0);
constant ddr2phy_builtin_pads: tech_ability_type := (
-- Wrapped DDR2 IP cores with builtin pads
easic45 => 1,
-- Below techs have builtin pads for legacy reasons, can be converted if needed
easic90 => 1, spartan3 => 1, stratix3 => 1, stratix2 => 1,
others => 0);
constant ddr2phy_has_fbclk: tech_ability_type :=
(inferred => 1, others => 0);
constant ddrphy_has_fbclk: tech_ability_type :=
(others => 0);
constant ddr2phy_has_reg: tech_ability_type :=
(easic45 => 1, others => 0);
constant ddr2phy_has_custom: tech_ability_type :=
(easic45 => 1, others => 0);
constant ddr2phy_refclk_type: tech_ability_type :=
(virtex4 => 1, virtex5 => 1, virtex6 => 1, -- 1: 200 MHz reference
easic45 => 2, -- 2: 270 degree shifted clock
others => 0); -- 0: None
constant ddr2phy_has_datavalid: tech_ability_type :=
(easic45 => 1,
others => 0);
constant ddrphy_has_datavalid: tech_ability_type :=
(ut90 => 1, others => 0);
constant ddrphy_builtin_pads: tech_ability_type := (
inferred => 0,
-- Most techs have builtin pads for legacy reasons, can be converted if needed
others => 1);
constant ddrphy_latency: tech_ability_type := (
-- extra read latency, only used when not datavalid signal is available
inferred => 1,
others => 0
);
-- If the PHY passes through the control signals directly to the pads
-- and therefore needs them to be set asynchronously at reset
constant ddr2phy_ptctrl: tech_ability_type := (
inferred => 1, others => 0
);
constant ddrphy_ptctrl: tech_ability_type := (
inferred => 1, others => 0
);
constant has_syncreg: tech_ability_type := (
inferred => 0, others => 0);
-- pragma translate_off
subtype tech_description is string(1 to 10);
type tech_table_type is array (0 to NTECH) of tech_description;
-------------------------------------------------------------------------------
constant tech_table : tech_table_type := (
inferred => "inferred ", virtex => "virtex ",
virtex2 => "virtex2 ", memvirage => "virage ",
axcel => "axcel ", proasic => "proasic ",
atc18s => "atc18s ", altera => "altera ",
umc => "umc18 ", rhumc => "rhumc ",
apa3 => "proasic3 ", spartan3 => "spartan3 ",
ihp25 => "ihp25 ", rhlib18t => "rhlib18t ",
virtex4 => "virtex4 ", lattice => "lattice ",
ut25 => "ut025crh ", spartan3e => "spartan3e ",
peregrine => "peregrine ", memartisan => "artisan ",
virtex5 => "virtex5 ", custom1 => "custom1 ",
ihp25rh => "ihp25rh ", stratix1 => "stratix ",
stratix2 => "stratixii ", eclipse => "eclipse ",
stratix3 => "stratixiii", cyclone3 => "cycloneiii",
memvirage90 => "virage90 ", tsmc90 => "tsmc90 ",
easic90 => "nextreme ", atc18rha => "atc18rha ",
smic013 => "smic13 ", tm65gplus => "tm65gplus ",
axdsp => "axdsp ", spartan6 => "spartan6 ",
virtex6 => "virtex6 ", actfus => "fusion ",
stratix4 => "stratix4 ", st65lp => "st65lp ",
st65gp => "st65gp ", easic45 => "nextreme2 ",
cmos9sf => "cmos9sf ", apa3e => "proasic3e ",
apa3l => "proasic3l ", ut130 => "ut130hbd ",
ut90 => "ut90nhbd ", gf65 => "gf65g ",
virtex7 => "virtex7 ", kintex7 => "kintex7 ",
artix7 => "artix7 ", zynq7000 => "zynq7000 ",
rhlib13t => "rhlib13t ", saed32 => "saed32 ",
dare => "dare ");
-- pragma translate_on
-- input/output voltage
constant x12v : integer := 12;
constant x15v : integer := 15;
constant x18v : integer := 1;
constant x25v : integer := 2;
constant x33v : integer := 3;
constant x50v : integer := 5;
-- input/output levels
constant ttl : integer := 0;
constant cmos : integer := 1;
constant pci33 : integer := 2;
constant pci66 : integer := 3;
constant lvds : integer := 4;
constant sstl2_i : integer := 5;
constant sstl2_ii : integer := 6;
constant sstl3_i : integer := 7;
constant sstl3_ii : integer := 8;
constant sstl18_i : integer := 9;
constant sstl18_ii: integer := 10;
constant lvpecl : integer := 11;
constant sstl : integer := 12;
-- pad types
constant normal : integer := 0;
constant pullup : integer := 1;
constant pulldown : integer := 2;
constant opendrain: integer := 3;
constant schmitt : integer := 4;
constant dci : integer := 5;
---------------------------------------------------------------------------
-- MEMORY
---------------------------------------------------------------------------
-- testin vector is testen & scanen & (tech-dependent...)
constant TESTIN_WIDTH : integer := 4 + GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra);
constant testin_none : std_logic_vector(TESTIN_WIDTH-1 downto 0) := (others => '0');
-- synchronous single-port ram
component syncram
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(custombits-1 downto 0));
end component;
-- synchronous two-port ram (1 read, 1 write port)
component syncram_2p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(custombits-1 downto 0));
end component;
-- synchronous dual-port ram (2 read/write ports)
component syncram_dp
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits : integer := 1);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(custombits-1 downto 0));
end component;
-- synchronous 3-port regfile (2 read, 1 write port)
component regfile_3p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
wrfst : integer := 0; numregs : integer := 64; testen : integer := 0;
custombits : integer := 1);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(2*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(2*custombits-1 downto 0));
end component;
-- 64-bit synchronous single-port ram with 32-bit write strobe
component syncram64
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0;
paren : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63+8*paren downto 0);
dataout : out std_logic_vector (63+8*paren downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(2*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(2*custombits-1 downto 0));
end component;
-- 128-bit synchronous single-port ram with 32-bit write strobe
component syncram128
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0;
paren : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127+16*paren downto 0);
dataout : out std_logic_vector (127+16*paren downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(4*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(4*custombits-1 downto 0));
end component;
component syncramft
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
ft : integer range 0 to 3 := 0; testen : integer := 0; custombits : integer := 1 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic;
enable : in std_ulogic;
error : out std_logic_vector(((dbits + 7) / 8)-1 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
errinj : in std_logic_vector(((dbits + 7)/8)*2-1 downto 0) := (others => '0');
customclk: in std_ulogic := '0';
customin : in std_logic_vector(3*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(3*custombits-1 downto 0));
end component;
component syncram_2pft
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; ft : integer := 0;
testen : integer := 0; words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
error : out std_logic_vector(((dbits + 7) / 8)-1 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(3*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(3*custombits-1 downto 0));
end component;
component syncram128bw
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(16*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(16*custombits-1 downto 0));
end component;
component syncram156bw
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (155 downto 0);
dataout : out std_logic_vector (155 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(20*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(20*custombits-1 downto 0));
end component;
component syncram256bw is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(32*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(32*custombits-1 downto 0));
end component;
component syncrambw
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits-1 downto 0);
datain : in std_logic_vector (dbits-1 downto 0);
dataout : out std_logic_vector (dbits-1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector (dbits/8-1 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector((dbits/8)*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector((dbits/8)*custombits-1 downto 0));
end component;
component syncram_2pbw
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_logic_vector((dbits/8-1) downto 0);
raddress : in std_logic_vector((abits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
wclk : in std_ulogic;
write : in std_logic_vector((dbits/8-1) downto 0);
waddress : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector((dbits/8)*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector((dbits/8)*custombits-1 downto 0));
end component;
component syncrambwft is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
ft : integer range 0 to 3 := 0; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits-1 downto 0);
datain : in std_logic_vector (dbits-1 downto 0);
dataout : out std_logic_vector (dbits-1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector (dbits/8-1 downto 0);
error : out std_logic_vector (dbits/8-1 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
errinj : in std_logic_vector((dbits/8)*2-1 downto 0) := (others => '0');
customclk : in std_ulogic := '0';
customin : in std_logic_vector(3*(dbits/8)*custombits-1 downto 0) := (others => '0');
customout : out std_logic_vector(3*(dbits/8)*custombits-1 downto 0));
end component;
component from is
generic (
timingcheckson: boolean := True;
instancepath: string := "*";
xon: boolean := False;
msgon: boolean := True;
data_x: integer := 1;
memoryfile: string := "";
progfile: string := "");
port (
clk: in std_ulogic;
addr: in std_logic_vector(6 downto 0);
data: out std_logic_vector(7 downto 0));
end component;
---------------------------------------------------------------------------
-- PADS
---------------------------------------------------------------------------
component inpad
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component inpadv
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; width : integer := 1;
filter : integer := 0; strength : integer := 0);
port (
pad : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component iopadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component iopadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000"
);
end component;
component iodpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end component;
component iodpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component outpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi : in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component outpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component odpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component odpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpad_ds
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component toutpad_dsv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end component;
component toutpad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end component;
component skew_outpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end component;
component clkpad
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; arch : integer := 0;
hf : integer := 0; filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1'; lock : out std_ulogic);
end component;
component inpad_ds
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component clkpad_ds
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component inpad_dsv
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1; term : integer := 0);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad_ds
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component iopad_dsv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad_dsvv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component outpad_ds
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; oepol : integer := 0; slew : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component outpad_dsv
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1; slew : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i, en: in std_logic_vector(width-1 downto 0));
end component;
component lvds_combo is
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
oepol : integer := 0; term : integer := 0);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic := '1'
);
end component;
-------------------------------------------------------------------------------
-- DDR PADS (bundles PAD and DDR register(s))
-------------------------------------------------------------------------------
component inpad_ddr
generic (tech : integer := 0; level : integer := 0; voltage : integer := x33v;
filter : integer := 0; strength : integer := 0 );
port (pad : in std_ulogic; o1, o2 : out std_ulogic; c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component inpad_ddrv
generic (tech : integer := 0; level : integer := 0; voltage : integer := 0;
filter : integer := 0; strength : integer := 0; width : integer := 1);
port (pad : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
ce : in std_ulogic; r: in std_ulogic; s : in std_ulogic);
end component;
component outpad_ddr
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i1, i2 : in std_ulogic; c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component outpad_ddrv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12;
width : integer := 1);
port (pad : out std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic; ce : in std_ulogic;
r : in std_ulogic; s : in std_ulogic);
end component;
component iopad_ddr
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i1, i2 : in std_ulogic; en : in std_ulogic;
o1, o2 : out std_ulogic; c1, c2 : in std_ulogic; ce : in std_ulogic;
r : in std_ulogic; s : in std_ulogic);
end component;
component iopad_ddrv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0); en : in std_ulogic;
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component iopad_ddrvv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
---------------------------------------------------------------------------
-- BUFFERS
---------------------------------------------------------------------------
component techbuf is
generic(
buftype : integer range 0 to 6 := 0;
tech : integer range 0 to NTECH := inferred);
port(
i : in std_ulogic;
o : out std_ulogic
);
end component;
---------------------------------------------------------------------------
-- CLOCK GENERATION
---------------------------------------------------------------------------
type clkgen_in_type is record
pllref : std_logic; -- optional reference for PLL
pllrst : std_logic; -- optional reset for PLL
pllctrl : std_logic_vector(1 downto 0); -- optional control for PLL
clksel : std_logic_vector(1 downto 0); -- optional clock select
end record;
type clkgen_out_type is record
clklock : std_logic;
pcilock : std_logic;
end record;
component clkgen
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 1;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0; -- enable clock select
clk_odiv : integer := 1; -- Proasic3/Fusion output divider clkA
clkb_odiv: integer := 0; -- Proasic3/Fusion output divider clkB
clkc_odiv: integer := 0); -- Proasic3/Fusion output divider clkC
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic; -- unscaled 2X clock
clkb : out std_logic; -- Proasic3/Fusion clkB
clkc : out std_logic; -- Proasic3/Fusion clkC
clk8x : out std_logic); -- 8x clock
end component;
component clkand
generic( tech : integer := 0;
ren : integer range 0 to 1 := 0); -- registered enable
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux
generic( tech : integer := 0;
rsel : integer range 0 to 1 := 0); -- registered sel
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic;
rst : in std_ulogic := '1'
);
end component;
component clkinv
generic( tech : integer := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end component;
component clkrand is
generic( tech : integer := 0);
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
---------------------------------------------------------------------------
-- TAP controller and boundary scan
---------------------------------------------------------------------------
component tap
generic (
tech : integer := 0;
irlen : integer range 2 to 8 := 4;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
trsten : integer range 0 to 1 := 1;
scantest : integer := 0;
oepol : integer := 1;
tcknen : integer := 0);
port (
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic;
tapi_en1 : in std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic;
tapo_tckn : out std_ulogic;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
testoen : in std_ulogic := '0';
tdoen : out std_ulogic;
tckn : in std_ulogic := '0'
);
end component;
component scanregi
generic (
tech : integer := 0;
intesten: integer := 1
);
port (
pad : in std_ulogic;
core : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive data reg to core
bshighz : in std_ulogic
);
end component;
component scanrego
generic (
tech : integer := 0
);
port (
pad : out std_ulogic;
core : in std_ulogic;
samp : in std_ulogic; -- normally same as core unless outpad has feedback
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic -- drive data reg to pad
);
end component;
component scanregto -- 2 scan registers: tdo<---output<--outputen<--tdi
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
samp : in std_ulogic; -- normally same as core unless outpad has feedback
coreo : in std_ulogic;
coreoen : in std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupdo : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive data reg to pad
bshighz : in std_ulogic -- tri-state output
);
end component;
component scanregio -- 3 scan registers: tdo<--input<--output<--outputen<--tdi
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1;
intesten: integer range 0 to 1 := 1
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
padi : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
corei : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive outdata regs to pad,
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
bshighz : in std_ulogic -- tri-state output
);
end component;
---------------------------------------------------------------------------
-- DDR registers and PHY
---------------------------------------------------------------------------
component ddr_ireg is
generic ( tech : integer; arch : integer := 0);
port ( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ddr_oreg is generic (tech : integer; arch : integer := 0);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ddrphy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddrphy_wo_pads
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
rskew : integer := 0; mobile: integer := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (1 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(2 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddr2phy
generic (
tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8 : integer := 0;
ddelayb9 : integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
ctrl2en: integer := 0; resync: integer := 0; custombits: integer := 8; extraio: integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input reference clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
-- Copy of control signals for 2nd DIMM
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddr2phy_wo_pads
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8: integer := 0;
ddelayb9: integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
resync : integer := 0; custombits: integer := 8; scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component lpddr2phy_wo_pads
generic (
tech : integer := virtex5;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- ckkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddr2pads is
generic (tech: integer := virtex5;
dbits: integer := 16;
eightbanks: integer := 0;
dqsse: integer range 0 to 1 := 0;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_odt : in std_logic_vector(ncs-1 downto 0)
);
end component;
component ddrpads is
generic (tech: integer := virtex5;
dbits: integer := 16;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1 downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1 downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0) -- ddr data
);
end component;
component ddrphy_datapath is
generic (
regtech: integer := 0;
dbits: integer;
abits: integer;
bankbits: integer range 2 to 3 := 2;
ncs: integer;
nclk: integer;
resync: integer range 0 to 2 := 0
);
port (
clk0: in std_ulogic;
clk90: in std_ulogic;
clk180: in std_ulogic;
clk270: in std_ulogic;
clkresync: in std_ulogic;
ddr_clk: out std_logic_vector(nclk-1 downto 0);
ddr_clkb: out std_logic_vector(nclk-1 downto 0);
ddr_dq_in: in std_logic_vector(dbits-1 downto 0);
ddr_dq_out: out std_logic_vector(dbits-1 downto 0);
ddr_dq_oen: out std_logic_vector(dbits-1 downto 0);
ddr_dqs_in90: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_in90n: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_out: out std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_oen: out std_logic_vector(dbits/8-1 downto 0);
ddr_cke: out std_logic_vector(ncs-1 downto 0);
ddr_csb: out std_logic_vector(ncs-1 downto 0);
ddr_web: out std_ulogic;
ddr_rasb: out std_ulogic;
ddr_casb: out std_ulogic;
ddr_ad: out std_logic_vector(abits-1 downto 0);
ddr_ba: out std_logic_vector(bankbits-1 downto 0);
ddr_dm: out std_logic_vector(dbits/8-1 downto 0);
ddr_odt: out std_logic_vector(ncs-1 downto 0);
dqin: out std_logic_vector(dbits*2-1 downto 0);
dqout: in std_logic_vector(dbits*2-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (bankbits-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
odt : in std_logic_vector(ncs-1 downto 0);
dqs_en : in std_ulogic;
dqs_oen : in std_ulogic;
ddrclk_en : in std_logic_vector(nclk-1 downto 0)
);
end component;
---------------------------------------------------------------------------
-- 61x61 Multiplier
---------------------------------------------------------------------------
component mul_61x61
generic (multech : integer := 0;
fabtech : integer := 0);
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
---------------------------------------------------------------------------
-- Ring oscillator
---------------------------------------------------------------------------
component ringosc
generic (tech : integer := 0);
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
---------------------------------------------------------------------------
-- System monitor
---------------------------------------------------------------------------
component system_monitor
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
component nandtree
generic(
tech : integer := inferred;
width : integer := 2;
imp : integer := 0 );
port( i : in std_logic_vector(width-1 downto 0);
o : out std_ulogic;
en : in std_ulogic
);
end component;
component grmux2 is generic( tech : integer := inferred; imp : integer := 0);
port( ip0, ip1, sel : in std_logic; op : out std_ulogic); end component;
component grmux2v is generic( tech : integer := inferred; bits : integer := 2; imp : integer := 0);
port( ip0, ip1 : in std_logic_vector(bits-1 downto 0);
sel : in std_logic; op : out std_logic_vector(bits-1 downto 0));
end component;
component grdff is generic( tech : integer := inferred; imp : integer := 0);
port( clk, d : in std_ulogic; q : out std_ulogic); end component;
component gror2 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end component;
component grand12 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end component;
component grnand2 is generic (tech: integer := inferred; imp: integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end component;
component techmult
generic (
tech : integer := 0;
arch : integer := 0;
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end component;
component syncreg
generic (
tech : integer := 0;
stages : integer range 1 to 5 := 2
);
port (
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic
);
end component;
-------------------------------------------------------------------------------
-- SDRAM PHY
-------------------------------------------------------------------------------
component sdram_phy
generic (
tech : integer := spartan3;
oepol : integer := 0;
level : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
aw : integer := 15; -- # address bits
dw : integer := 32; -- # data bits
ncs : integer := 2;
reg : integer := 0); -- 1: include registers on all signals
port (
-- SDRAM interface
addr : out std_logic_vector(aw-1 downto 0);
dq : inout std_logic_vector(dw-1 downto 0);
cke : out std_logic_vector(ncs-1 downto 0);
sn : out std_logic_vector(ncs-1 downto 0);
wen : out std_ulogic;
rasn : out std_ulogic;
casn : out std_ulogic;
dqm : out std_logic_vector(dw/8-1 downto 0);
-- Interface toward memory controller
laddr : in std_logic_vector(aw-1 downto 0);
ldq_din : out std_logic_vector(dw-1 downto 0);
ldq_dout : in std_logic_vector(dw-1 downto 0);
ldq_oen : in std_logic_vector(dw-1 downto 0);
lcke : in std_logic_vector(ncs-1 downto 0);
lsn : in std_logic_vector(ncs-1 downto 0);
lwen : in std_ulogic;
lrasn : in std_ulogic;
lcasn : in std_ulogic;
ldqm : in std_logic_vector(dw/8-1 downto 0);
-- Only used when reg generic is non-zero
rstn : in std_ulogic; -- Registered pads reset
clk : in std_ulogic; -- SDRAM clock for registered pads
-- Optional pad configuration inputs
cfgi_cmd : in std_logic_vector(19 downto 0) := "00000000000000000000"; -- CMD pads
cfgi_dq : in std_logic_vector(19 downto 0) := "00000000000000000000" -- DQ pads
);
end component;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-ztex-ufm-111/config.vhd | 1 | 5589 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (3);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (2);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#FC0#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 1;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep2s60-sdr/config.vhd | 1 | 5586 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-kc705/sgmii_kc705.vhd | 1 | 25153 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sgmii
-- File: sgmii.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: GMII to SGMII interface
------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This is the top level vhdl example design for the
-- Ethernet 1000BASE-X PCS/PMA core.
--
-- This design example instantiates IOB flip-flops
-- and input/output buffers on the GMII.
--
-- A Transmitter Elastic Buffer is instantiated on the Tx
-- GMII path to perform clock compenstation between the
-- core and the external MAC driving the Tx GMII.
--
-- This design example can be synthesised.
--
--
--
-- ----------------------------------------------------------------
-- | Example Design |
-- | |
-- | ---------------------------------------------- |
-- | | Core Block (wrapper) | |
-- | | | |
-- | | -------------- -------------- | |
-- | | | Core | | tranceiver | | |
-- | | | | | | | |
-- | --------- | | | | | | |
-- | | | | | | | | | |
-- | | Tx | | | | | | | |
-- ---->|Elastic|----->| GMII |--------->| TXP |--------->
-- | |Buffer | | | Tx | | TXN | | |
-- | | | | | | | | | |
-- | --------- | | | | | | |
-- | GMII | | | | | | |
-- | IOBs | | | | | | |
-- | | | | | | | |
-- | | | GMII | | RXP | | |
-- <-------------------| Rx |<---------| RXN |<---------
-- | | | | | | | |
-- | | -------------- -------------- | |
-- | | | |
-- | ---------------------------------------------- |
-- | |
-- ----------------------------------------------------------------
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
use gaisler.net.all;
--------------------------------------------------------------------------------
-- The entity declaration for the example design
--------------------------------------------------------------------------------
entity sgmii_kc705 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
autonegotiation : integer := 1
);
port(
-- Tranceiver Interface
sgmiii : in eth_sgmii_in_type;
sgmiio : out eth_sgmii_out_type;
-- GMII Interface (client MAC <=> PCS)
gmiii : out eth_in_type;
gmiio : in eth_out_type;
-- Asynchronous reset for entire core.
reset : in std_logic;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end sgmii_kc705;
architecture top_level of sgmii_kc705 is
------------------------------------------------------------------------------
-- Component Declaration for the Core Block (core wrapper).
------------------------------------------------------------------------------
component sgmii_block
port(
-- Transceiver Interface
------------------------
drpaddr_in : in std_logic_vector(8 downto 0);
drpclk_in : in std_logic;
drpdi_in : in std_logic_vector(15 downto 0);
drpdo_out : out std_logic_vector(15 downto 0);
drpen_in : in std_logic;
drprdy_out : out std_logic;
drpwe_in : in std_logic;
gtrefclk : in std_logic; -- Very high quality 125MHz clock for GT transceiver
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
txoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz)
resetdone : out std_logic; -- The GT transceiver has completed its reset cycle
mmcm_locked : in std_logic; -- Locked signal from MMCM
userclk : in std_logic; -- 62.5MHz clock.
userclk2 : in std_logic; -- 125MHz clock.
independent_clock_bufg : in std_logic;
pma_reset : in std_logic; -- transceiver PMA reset signal
-- GMII Interface
-----------------
sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_en : out std_logic; -- Clock enable for client MAC
gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
gmii_rx_er : out std_logic; -- Received control signal to client MAC.
gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
-- Management: MDIO Interface
-----------------------------
configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV)
an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0
link_timer_value : in std_logic_vector(8 downto 0); -- Programmable Auto-Negotiation Link Timer Control
-- Speed Control
----------------
speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
-- General IO's
---------------
status_vector : out std_logic_vector(15 downto 0); -- Core status.
reset : in std_logic; -- Asynchronous reset for entire core.
signal_detect : in std_logic -- Input from PMD to indicate presence of optical input.
);
end component;
component MMCME2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT_F : real := 5.000;
CLKFBOUT_PHASE : real := 0.000;
CLKFBOUT_USE_FINE_PS : boolean := FALSE;
CLKIN1_PERIOD : real := 0.000;
CLKIN2_PERIOD : real := 0.000;
CLKOUT0_DIVIDE_F : real := 1.000;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
CLKOUT0_USE_FINE_PS : boolean := FALSE;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
CLKOUT1_USE_FINE_PS : boolean := FALSE;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
CLKOUT2_USE_FINE_PS : boolean := FALSE;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
CLKOUT3_USE_FINE_PS : boolean := FALSE;
CLKOUT4_CASCADE : boolean := FALSE;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
CLKOUT4_USE_FINE_PS : boolean := FALSE;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
CLKOUT5_USE_FINE_PS : boolean := FALSE;
CLKOUT6_DIVIDE : integer := 1;
CLKOUT6_DUTY_CYCLE : real := 0.500;
CLKOUT6_PHASE : real := 0.000;
CLKOUT6_USE_FINE_PS : boolean := FALSE;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
SS_EN : string := "FALSE";
SS_MODE : string := "CENTER_HIGH";
SS_MOD_PERIOD : integer := 10000;
STARTUP_WAIT : boolean := FALSE
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKFBOUTB : out std_ulogic := '0';
CLKFBSTOPPED : out std_ulogic := '0';
CLKINSTOPPED : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT0B : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT1B : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT2B : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT3B : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
CLKOUT6 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
----- component IBUFDS_GTE2 -----
component IBUFDS_GTE2
generic (
CLKCM_CFG : boolean := TRUE;
CLKRCV_TRST : boolean := TRUE;
CLKSWING_CFG : bit_vector := "11"
);
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SGMII, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
------------------------------------------------------------------------------
-- internal signals used in this top level example design.
------------------------------------------------------------------------------
-- clock generation signals for tranceiver
signal gtrefclk : std_logic;
signal txoutclk : std_logic;
signal resetdone : std_logic;
signal mmcm_locked : std_logic;
signal mmcm_reset : std_logic;
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal userclk : std_logic;
signal userclk2 : std_logic;
-- PMA reset generation signals for tranceiver
signal pma_reset_pipe : std_logic_vector(3 downto 0);
signal pma_reset : std_logic;
-- clock generation signals for SGMII clock
signal sgmii_clk_r : std_logic;
signal sgmii_clk_f : std_logic;
signal sgmii_clk_en : std_logic;
signal sgmii_clk : std_logic;
signal sgmii_clk_int : std_logic;
-- GMII signals
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
signal gmii_isolate : std_logic;
signal gmii_txd_int : std_logic_vector(7 downto 0);
signal gmii_tx_en_int : std_logic;
signal gmii_tx_er_int : std_logic;
signal gmii_rxd_int : std_logic_vector(7 downto 0);
signal gmii_rx_dv_int : std_logic;
signal gmii_rx_er_int : std_logic;
-- Extra registers to ease IOB placement
signal status_vector_int : std_logic_vector(15 downto 0);
signal status_vector_apb : std_logic_vector(15 downto 0);
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute ASYNC_REG : string;
attribute ASYNC_REG of pma_reset_pipe : signal is "TRUE";
-- Configuration register
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal configuration_vector : std_logic_vector(4 downto 0);
signal an_interrupt : std_logic;
signal an_adv_config_vector : std_logic_vector(15 downto 0);
signal an_restart_config : std_logic;
signal link_timer_value : std_logic_vector(8 downto 0);
signal status_vector : std_logic_vector(15 downto 0);
signal synchronization_done : std_logic;
signal linkup : std_logic;
signal signal_detect : std_logic;
attribute clock_signal : string;
attribute clock_signal of sgmii_clk : signal is "yes";
attribute clock_signal of sgmii_clk_int : signal is "yes";
begin
-----------------------------------------------------------------------------
-- Default for KC705
-----------------------------------------------------------------------------
-- Remove AN during simulation i.e. "00000"
configuration_vector <= "10000" when (autonegotiation = 1) else "00000";
--an_adv_config_vector <= x"4001";
an_adv_config_vector <= "0000000000100001";
an_restart_config <= '0';
link_timer_value <= "000110010";
-- Core Status vector outputs
synchronization_done <= status_vector_int(1);
linkup <= status_vector_int(0);
signal_detect <= '1';
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= status_vector_apb;
gmiii.gtx_clk <= sgmii_clk;
gmiii.tx_clk <= sgmii_clk;
gmiii.rx_clk <= sgmii_clk;
gmii_txd <= gmiio.txd;
gmii_tx_en <= gmiio.tx_en;
gmii_tx_er <= gmiio.tx_er;
gmiii.rxd <= gmii_rxd;
gmiii.rx_dv <= gmii_rx_dv;
gmiii.rx_er <= gmii_rx_er;
gmiii.edclsepahb <= '0';
gmiii.edcldisable <= '0';
gmiii.phyrstaddr <= (others => '0');
gmiii.edcladdr <= (others => '0');
gmiii.rmii_clk <= sgmii_clk;
gmiii.rx_col <= '0';
gmiii.rx_crs <= '0';
sgmiio.mdio_o <= gmiio.mdio_o;
sgmiio.mdio_oe <= gmiio.mdio_oe;
gmiii.mdio_i <= sgmiii.mdio_i;
sgmiio.mdc <= gmiio.mdc;
gmiii.mdint <= sgmiii.mdint;
sgmiio.reset <= apb_rstn;
-----------------------------------------------------------------------------
-- Transceiver Clock Management
-----------------------------------------------------------------------------
-- Clock circuitry for the GT Transceiver uses a differential input clock.
-- gtrefclk is routed to the tranceiver.
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => sgmiii.clkp,
IB => sgmiii.clkn,
CEB => '0',
O => gtrefclk,
ODIV2 => open
);
-- The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is
-- routed to an MMCM module where it is used to create phase and frequency
-- related 62.5MHz and 125MHz clock sources
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
-- STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 16,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 16.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => open,
CLKOUT0 => clkout0,
CLKOUT0B => open,
CLKOUT1 => clkout1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => txoutclk,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => mmcm_reset);
mmcm_reset <= reset or (not resetdone);
-- This 62.5MHz clock is placed onto global clock routing and is then used
-- for tranceiver TXUSRCLK/RXUSRCLK.
bufg_userclk: BUFG
port map (
I => clkout1,
O => userclk
);
-- This 125MHz clock is placed onto global clock routing and is then used
-- to clock all Ethernet core logic.
bufg_userclk2: BUFG
port map (
I => clkout0,
O => userclk2
);
-----------------------------------------------------------------------------
-- Transceiver PMA reset circuitry
-----------------------------------------------------------------------------
-- Create a reset pulse of a decent length
process(reset, apb_clk)
begin
if (reset = '1') then
pma_reset_pipe <= "1111";
elsif apb_clk'event and apb_clk = '1' then
pma_reset_pipe <= pma_reset_pipe(2 downto 0) & reset;
end if;
end process;
pma_reset <= pma_reset_pipe(3);
------------------------------------------------------------------------------
-- Instantiate the Core Block (core wrapper).
------------------------------------------------------------------------------
speed_is_10_100 <= not gmiio.gbit;
speed_is_100 <= gmiio.speed;
core_wrapper : sgmii_block
port map (
drpaddr_in => "000000000",
drpclk_in => '0',
drpdi_in => "0000000000000000",
drpdo_out => OPEN,
drpen_in => '0',
drprdy_out => OPEN,
drpwe_in => '0',
gtrefclk => gtrefclk,
txp => sgmiio.txp,
txn => sgmiio.txn,
rxp => sgmiii.rxp,
rxn => sgmiii.rxn,
txoutclk => txoutclk,
resetdone => resetdone,
mmcm_locked => mmcm_locked,
userclk => userclk,
userclk2 => userclk2,
independent_clock_bufg => apb_clk,
pma_reset => pma_reset,
sgmii_clk_r => sgmii_clk_r,
sgmii_clk_f => sgmii_clk_f,
sgmii_clk_en => sgmii_clk_en,
gmii_txd => gmii_txd_int,
gmii_tx_en => gmii_tx_en_int,
gmii_tx_er => gmii_tx_er_int,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
gmii_isolate => gmii_isolate,
configuration_vector => configuration_vector,
an_interrupt => an_interrupt,
an_adv_config_vector => an_adv_config_vector,
an_restart_config => an_restart_config,
link_timer_value => link_timer_value,
speed_is_10_100 => speed_is_10_100,
speed_is_100 => speed_is_100,
status_vector => status_vector_int,
reset => reset,
signal_detect => signal_detect
);
-----------------------------------------------------------------------------
-- GMII transmitter data logic
-----------------------------------------------------------------------------
-- Drive input GMII signals through IOB input flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_txd_int <= gmii_txd;
gmii_tx_en_int <= gmii_tx_en;
gmii_tx_er_int <= gmii_tx_er;
end if;
end process;
-----------------------------------------------------------------------------
-- SGMII clock logic
-----------------------------------------------------------------------------
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
sgmii_clk_int <= sgmii_clk_r;
end if;
end process;
sgmii_clk <= userclk2 when (gmiio.gbit = '1') else sgmii_clk_int;
-----------------------------------------------------------------------------
-- GMII receiver data logic
-----------------------------------------------------------------------------
-- Drive input GMII signals through IOB output flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_rxd <= gmii_rxd_int;
gmii_rx_dv <= gmii_rx_dv_int;
gmii_rx_er <= gmii_rx_er_int;
end if;
end process;
-----------------------------------------------------------------------------
-- Extra registers to ease IOB placement
-----------------------------------------------------------------------------
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
status_vector <= status_vector_int;
end if;
end process;
-----------------------------------------------------------------------------
-- Extra registers to ease CDC placement
-----------------------------------------------------------------------------
process (apb_clk)
begin
if apb_clk'event and apb_clk = '1' then
status_vector_apb <= status_vector_int;
end if;
end process;
end top_level;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml403/testbench.vhd | 1 | 9339 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal plb_error : std_logic;
signal opb_error : std_logic;
signal flash_a23 : std_ulogic;
signal sram_flash_addr : std_logic_vector(20 downto 0);
signal sram_flash_data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_flash_oe_n : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_ce : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal sram_zz : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (3 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (3 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (31 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(13 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal tft_lcd_clk : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 3);
signal vid_g : std_logic_vector(7 downto 3);
signal vid_b : std_logic_vector(7 downto 3);
signal usb_csn : std_logic;
signal flash_cex : std_logic;
signal iic_scl : std_logic;
signal iic_sda : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxsp : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txdp : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txsp : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal datazz : std_logic_vector(0 to 3);
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
rxd1 <= 'H';
sram_clk_fb <= sram_clk; ddr_clk_fb <= ddr_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl <= 'H'; iic_sda <= 'H';
flash_cex <= not flash_ce;
gpio <= (others => 'L');
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, plb_error, opb_error, sram_flash_addr,
sram_flash_data, sram_cen, sram_bw, sram_flash_oe_n, sram_flash_we_n,
flash_ce, sram_clk, sram_clk_fb, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, ps2_keyb_clk,
ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data, tft_lcd_clk,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b,
usb_csn,
iic_scl, iic_sda
);
datazz <= "HHHH";
u0 : cy7c1354 generic map (fname => sramfile)
port map(
Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data,
Addr => sram_flash_addr(17 downto 0), Mode => sram_mode,
Clk => sram_clk, CEN_n => gnd, AdvLd_n => sram_adv_ld_n,
Bwa_n => sram_bw(3), Bwb_n => sram_bw(2),
Bwc_n => sram_bw(1), Bwd_n => sram_bw(0),
Rw_n => sram_flash_we_n, Oe_n => sram_flash_oe_n,
Ce1_n => sram_cen,
Ce2 => vcc,
Ce3_n => gnd,
Zz => sram_zz);
sram_zz <= '0';
u1 : mt46v16m16
generic map (index => 1, fname => sdramfile, bbits => 32)
PORT MAP(
Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
Dm => ddr_dm(1 downto 0));
u2 : mt46v16m16
generic map (index => 0, fname => sdramfile, bbits => 32)
PORT MAP(
Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
Dm => ddr_dm(3 downto 2));
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(31-i*8 downto 24-i*8),
flash_cex, sram_bw(i), sram_flash_oe_n);
end generate;
phy_mii_data <= 'H';
p0: phy
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv,
phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_gtx_clk);
i0: i2c_slave_model
port map (iic_scl, iic_sda);
plb_error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(plb_error) = '1' then wait on plb_error; end if;
assert (to_x01(plb_error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, plb_error, sram_flash_addr(19 downto 0), sram_flash_data,
iosn, sram_flash_oe_n, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/memctrl/sdctrl.vhd | 1 | 29625 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdctrl
-- File: sdctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 32-bit SDRAM memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity sdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of sdctrl is
constant WPROTEN : boolean := wprot = 1;
constant SDINVCLK : boolean := invclk = 1;
constant BUS64 : boolean := (sdbits = 64);
constant REVISION : integer := 1;
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
constant std_rammask: Std_Logic_Vector(31 downto 20) :=
Conv_Std_Logic_Vector(hmask, 12);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle,
sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
nbdrive : std_ulogic;
burst : std_ulogic;
wprothit : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(sdbits-1 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
address : std_logic_vector(16 downto 2); -- memory address
bsel : std_ulogic;
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
pwron : std_ulogic;
end record;
signal r, ri : reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sdi, rbdrive)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable dout : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable lline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable haddr_tmp : std_logic_vector(31 downto 0);
variable arefresh : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32);
v.hrdata(31 downto 0) := sdi.data(31 downto 0);
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)); v.hwdata := hwdata;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := v.hio;
end if;
v.haddr := ahbsi.haddr;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
-- addr must be masked since address range can be smaller than
-- total banksize. this can result in wrong chip select being
-- asserted
for i in 31 downto 20 loop
haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
end loop;
end if;
if fast = 1 then haddr := r.haddr; end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- main state
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if;
-- main FSM
case r.mstate is
when midle =>
if ((v.hsel and htrans(1) and not v.hio) = '1') then
if (r.sdstate = sidle) and (r.cfg.command = "000")
and (r.cmstate = midle) and (v.hio = '0')
then
if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
v.hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := startsd or r.startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
end if;
if WPROTEN then
v.wprothit := sdi.wprot;
if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if r.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0';
if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
v.hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '1'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (r.htrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
when wr3 =>
if (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when wr5 =>
v.sdstate := sidle; v.idlecnt := (others => '1');
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (ahbsi.htrans = "11") then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if ahbsi.htrans /= "11" then
if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if r.haddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0';
elsif lineburst then
if r.haddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then
if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1' and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1' and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
v.hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" => -- Lodad Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
when "111" => -- Load Ext-Mode Reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (r.cfg.renable = '1' or (pwron /= 0 and r.pwron = '1')) and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if pwron /= 0 then v.pwron := '0'; end if;
if r.cfg.renable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
-- pragma translate_off
if not is_x(r.cfg.refresh) then
-- pragma translate_on
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- AHB register access
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
if r.haddr(3 downto 2) = "00" then
if pageburst = 2 then v.cfg.pageburst := hwdata(17); end if;
v.cfg.command := hwdata(20 downto 18);
v.cfg.csize := hwdata(22 downto 21);
v.cfg.bsize := hwdata(25 downto 23);
v.cfg.casdel := hwdata(26);
v.cfg.trfc := hwdata(29 downto 27);
v.cfg.trp := hwdata(30);
v.cfg.renable := hwdata(31);
v.cfg.refresh := hwdata(14 downto 0);
v.refresh := (others => '0');
elsif r.haddr(3 downto 2) = "01" then
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := hwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
v.cfg.txsr := hwdata(23 downto 20);
v.cfg.pmode := hwdata(18 downto 16);
v.cfg.ds(3 downto 2) := hwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := hwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := hwdata( 2 downto 0);
end if;
end if;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
if r.haddr(3 downto 2) = "00" then
regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
if BUS64 then regsd(15) := '1'; end if;
regsd(14 downto 0) := r.cfg.refresh;
elsif r.haddr(3 downto 2) = "01" then
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
end if;
if (r.hsel and r.hio) = '1' then dout := regsd;
else
if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32);
else dout := r.hrdata(31 downto 0); end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.bsel := '0';
v.startsd := '0';
if pwron /= 0 then v.pwron := '1'; end if;
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
v.hio := '0';
end if;
if pwron = 0 then v.pwron := '0'; end if;
if not WPROTEN then v.wprothit := '0'; end if;
ri <= v;
ribdrive <= vbdrive;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(dout);
end process;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
driveundriven : block
begin
sdo.qdrive <= '0';
sdo.nbdrive <= '0';
sdo.ce <= '0';
sdo.moben <= '0';
sdo.cal_rst <= '0';
sdo.oct <= '0';
sdo.dqs_gate <= '0';
sdo.xsdcsn <= (others => '1');
sdo.data(127 downto sdbits) <= (others => '0');
sdo.cb <= (others => '0');
sdo.ba <= (others => '0');
sdo.sdck <= (others => '0');
sdo.cal_en <= (others => '0');
sdo.cal_inc <= (others => '0');
sdo.cal_pll <= (others => '0');
sdo.odt <= (others => '0');
sdo.conf <= (others => '0');
sdo.vcbdrive <= (others => '0');
sdo.cbdqm <= (others => '0');
sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0');
sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0');
sdo.regwrite <= (others => '0');
end block driveundriven;
regs : process(clk, rst) begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive;
if rst = '0' then r.icnt <= (others => '0'); end if;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
rgen : if not SDINVCLK generate
sdo.address <= r.address;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
drivebus: for i in 0 to sdbits/64 generate
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end generate;
end generate;
ngen : if SDINVCLK generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
sdo.address <= r.address;
if oepol = 1 then sdo.bdrive <= r.nbdrive;
else sdo.bdrive <= r.bdrive; end if;
sdo.vbdrive <= zero32 & rbdrive;
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= "11111111" & r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
for i in 0 to sdbits/64 loop
sdo.data(31+32*i downto 32*i) <= r.hwdata;
end loop;
end if;
if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
end process;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sdctrl" & tost(hindex) &
": PC133 SDRAM controller rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml40x/ahbrom.vhd | 15 | 5978 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 272;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"87444000";
when 16#0002D# => romdata <= X"8730E01C";
when 16#0002E# => romdata <= X"8688E00F";
when 16#0002F# => romdata <= X"12800006";
when 16#00030# => romdata <= X"033FFC00";
when 16#00031# => romdata <= X"82106100";
when 16#00032# => romdata <= X"0539A81B";
when 16#00033# => romdata <= X"8410A260";
when 16#00034# => romdata <= X"C4204000";
when 16#00035# => romdata <= X"3D1003FF";
when 16#00036# => romdata <= X"BC17A3E0";
when 16#00037# => romdata <= X"9C27A060";
when 16#00038# => romdata <= X"03100000";
when 16#00039# => romdata <= X"81C04000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000000";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000000";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-avnet-eval-xc4vlx25/ahbrom.vhd | 28 | 6162 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/grpci2/grpci2.in.vhd | 3 | 1773 | -- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := CFG_GRPCI2_MASTEREN;
constant CFG_GRPCI2_TARGET : integer := CFG_GRPCI2_TARGETEN;
constant CFG_GRPCI2_DMA : integer := CFG_GRPCI2_DMAEN;
constant CFG_GRPCI2_VID : integer := 16#CONFIG_GRPCI2_VENDORID#;
constant CFG_GRPCI2_DID : integer := 16#CONFIG_GRPCI2_DEVICEID#;
constant CFG_GRPCI2_CLASS : integer := 16#CONFIG_GRPCI2_CLASS#;
constant CFG_GRPCI2_RID : integer := 16#CONFIG_GRPCI2_REVID#;
constant CFG_GRPCI2_CAP : integer := 16#CONFIG_GRPCI2_CAPPOINT#;
constant CFG_GRPCI2_NCAP : integer := 16#CONFIG_GRPCI2_NEXTCAPPOINT#;
constant CFG_GRPCI2_BAR0 : integer := CONFIG_GRPCI2_BAR0;
constant CFG_GRPCI2_BAR1 : integer := CONFIG_GRPCI2_BAR1;
constant CFG_GRPCI2_BAR2 : integer := CONFIG_GRPCI2_BAR2;
constant CFG_GRPCI2_BAR3 : integer := CONFIG_GRPCI2_BAR3;
constant CFG_GRPCI2_BAR4 : integer := CONFIG_GRPCI2_BAR4;
constant CFG_GRPCI2_BAR5 : integer := CONFIG_GRPCI2_BAR5;
constant CFG_GRPCI2_FDEPTH : integer := CFG_GRPCI2_FIFO;
constant CFG_GRPCI2_FCOUNT : integer := CFG_GRPCI2_FIFOCNT;
constant CFG_GRPCI2_ENDIAN : integer := CFG_GRPCI2_LENDIAN;
constant CFG_GRPCI2_DEVINT : integer := CFG_GRPCI2_DINT;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#CONFIG_GRPCI2_DINTMASK#;
constant CFG_GRPCI2_HOSTINT : integer := CFG_GRPCI2_HINT;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#CONFIG_GRPCI2_HINTMASK#;
constant CFG_GRPCI2_TRACE : integer := CFG_GRPCI2_TRACEDEPTH;
constant CFG_GRPCI2_TRACEAPB : integer := CONFIG_GRPCI2_TRACEAPB;
constant CFG_GRPCI2_BYPASS : integer := CFG_GRPCI2_INBYPASS;
constant CFG_GRPCI2_EXTCFG : integer := CONFIG_GRPCI2_EXTCFG;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/altera_mf/memory_altera_mf.vhd | 1 | 8340 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_altera_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Altera altsynram
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altsyncram;
-- pragma translate_on
entity altera_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of altera_syncram_dp is
component altsyncram
generic (
width_a : natural;
width_b : natural := 1;
widthad_a : natural;
widthad_b : natural := 1);
port(
address_a : in std_logic_vector(widthad_a-1 downto 0);
address_b : in std_logic_vector(widthad_b-1 downto 0);
clock0 : in std_logic;
clock1 : in std_logic;
data_a : in std_logic_vector(width_a-1 downto 0);
data_b : in std_logic_vector(width_b-1 downto 0);
q_a : out std_logic_vector(width_a-1 downto 0);
q_b : out std_logic_vector(width_b-1 downto 0);
rden_b : in std_logic;
wren_a : in std_logic;
wren_b : in std_logic
);
end component;
begin
u0 : altsyncram
generic map (
WIDTH_A => dbits, WIDTHAD_A => abits,
WIDTH_B => dbits, WIDTHAD_B => abits)
port map (
address_a => address1, address_b => address2, clock0 => clk1,
clock1 => clk2, data_a => datain1, data_b => datain2,
q_a => dataout1, q_b => dataout2, rden_b => enable2,
wren_a => write1, wren_b => write2);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity altera_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of altera_syncram is
component altera_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
signal agnd : std_logic_vector(abits-1 downto 0);
signal dgnd : std_logic_vector(dbits-1 downto 0);
begin
agnd <= (others => '0'); dgnd <= (others => '0');
u0: altera_syncram_dp
generic map (abits, dbits)
port map (
clk1 => clk, address1 => address, datain1 => datain,
dataout1 => dataout, enable1 => enable, write1 => write,
clk2 => clk, address2 => agnd, datain2 => dgnd,
dataout2 => open, enable2 => agnd(0), write2 => agnd(0));
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altsyncram;
-- pragma translate_on
entity altera_syncram128bw is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end;
architecture behav of altera_syncram128bw is
component altsyncram
generic (
width_a : natural;
width_b : natural := 1;
widthad_a : natural;
widthad_b : natural := 1;
byte_size : integer := 0;
width_byteena_a : integer := 1
);
port(
address_a : in std_logic_vector(widthad_a-1 downto 0);
clock0 : in std_logic;
clock1 : in std_logic;
data_a : in std_logic_vector(width_a-1 downto 0);
q_a : out std_logic_vector(width_a-1 downto 0);
wren_a : in std_logic;
byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1')
);
end component;
signal agnd : std_logic_vector(abits-1 downto 0);
signal dgnd : std_logic_vector(127 downto 0);
signal write1 : std_logic;
signal enablex : std_logic_vector (15 downto 0);
begin
agnd <= (others => '0'); dgnd <= (others => '0');
write1 <= orv(write and enable);
enablex <= write when write1 = '1' else enable;
u0 : altsyncram
generic map (
WIDTH_A => 128, WIDTHAD_A => abits,
WIDTH_B => 128, WIDTHAD_B => abits, byte_size => 8,
width_byteena_a => 16 )
port map (
address_a => address, clock0 => clk, clock1 => clk,
data_a => datain, q_a => dataout, wren_a => write1,
byteena_a => enablex );
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altsyncram;
-- pragma translate_on
entity altera_syncram256bw is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0)
);
end;
architecture behav of altera_syncram256bw is
component altsyncram
generic (
width_a : natural;
width_b : natural := 1;
widthad_a : natural;
widthad_b : natural := 1;
byte_size : integer := 0;
width_byteena_a : integer := 1
);
port(
address_a : in std_logic_vector(widthad_a-1 downto 0);
clock0 : in std_logic;
clock1 : in std_logic;
data_a : in std_logic_vector(width_a-1 downto 0);
q_a : out std_logic_vector(width_a-1 downto 0);
wren_a : in std_logic;
byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1')
);
end component;
signal agnd : std_logic_vector(abits-1 downto 0);
signal dgnd : std_logic_vector(255 downto 0);
signal write1 : std_logic;
signal enablex : std_logic_vector (31 downto 0);
begin
agnd <= (others => '0'); dgnd <= (others => '0');
write1 <= orv(write and enable);
enablex <= write when write1 = '1' else enable;
u0 : altsyncram
generic map (
WIDTH_A => 256, WIDTHAD_A => abits,
WIDTH_B => 256, WIDTHAD_B => abits, byte_size => 8,
width_byteena_a => 32 )
port map (
address_a => address, clock0 => clk, clock1 => clk,
data_a => datain, q_a => dataout, wren_a => write1,
byteena_a => enablex );
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-avnet-eval-xc4vlx25/leon3mp.vhd | 1 | 21840 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
);
port (
resetn : in std_ulogic;
resoutn : out std_logic;
clk_100mhz : in std_ulogic;
errorn : out std_ulogic;
-- prom interface
address : out std_logic_vector(21 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
romrstn : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(15 downto 0);
-- pragma translate_on
-- ddr memory
ddr_clk0 : out std_logic;
ddr_clk0b : out std_logic;
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke0 : out std_logic;
ddr_cs0b : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
-- UART for serial DCL/console I/O
serrx : in std_ulogic;
sertx : out std_ulogic;
rtsn : out std_ulogic;
ctsn : in std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- ethernet signals
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
erstn : out std_ulogic;
-- OLED display signals
disp_dcn : out std_ulogic;
disp_csn : out std_ulogic;
disp_rdn : out std_ulogic;
disp_wrn : out std_ulogic;
disp_d : inout std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal lclk : std_ulogic;
signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
signal clkm, rstn, clkml, clk2x : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_ulogic;
-- signal dsubre : std_logic;
signal duart, ldsuen : std_logic;
signal rsertx, rserrx, rdsuen : std_logic;
signal rstraw : std_logic;
signal rstneg : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal lock : std_logic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
romrstn <= rstn;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
rstneg <= not resetn;
rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
clk_pad : clkpad generic map (tech => padtech) port map (clk_100mhz, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0, 1, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0,
paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (width => 22, tech => padtech)
port map (address, memo.address(22 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
end generate;
-- pragma translate_on
bdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- DDR memory controller -------------------------------------------
----------------------------------------------------------------------
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc : ddrspa generic map ( fabtech => virtex4, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => -95
-- pragma translate_off
* 0 -- disable clock skew during simulation
-- pragma translate_on
, clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
port map (
rstneg, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
ddr_ad <= ddr_adl(12 downto 0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => 12 --CFG_GRGPIO_WIDTH
)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
disp_csn_pad : outpad generic map (tech => padtech)
port map (disp_csn, gpioo.dout(8));
disp_dcn_pad : outpad generic map (tech => padtech)
port map (disp_dcn, gpioo.dout(9));
disp_rdn_pad : outpad generic map (tech => padtech)
port map (disp_rdn, gpioo.dout(10));
disp_wrn_pad : outpad generic map (tech => padtech)
port map (disp_wrn, gpioo.dout(11));
disp_d_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (disp_d(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
phyrstadr => 3, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
erstn_pad : outpad generic map (tech => padtech)
port map (erstn, rstn);
end generate;
-----------------------------------------------------------------------
--- AHB DMA ----------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
-- pindex => 12, paddr => 12, dbuf => 32)
-- port map (rstn, clkm, apbi, apbo(12), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
resoutn <= rstn;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design for Avnet Virtex4 Eval board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-- use switch 1 to multiplex DSU UART and UART1
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, ldsuen);
duart <= rdsuen when CFG_AHB_UART /= 0 else '0';
rxd1 <= txd1 when duart = '1' else rserrx;
rsertx <= duo.txd when duart = '1' else txd1;
dui.rxd <= rserrx when duart = '1' else '1';
led_rx <= not rserrx;
p1 : process(clkm)
begin
if rising_edge(clkm) then
sertx <= rsertx; rserrx <= serrx; rdsuen <= ldsuen;
rtsn <= '0';
led_tx <= not rsertx;
end if;
end process;
end rtl;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/gr1553b/gr1553b_stdlogic.vhd | 1 | 6285 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gr1553b_stdlogic
-- File: gr1553b_stdlogic.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Wrapper for GR1553B with std_logic ports
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity gr1553b_stdlogic is
generic (
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer := 0
);
port (
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
-- AHB interface
mi_hgrant : in std_logic; -- bus grant
mi_hready : in std_ulogic; -- transfer done
mi_hresp : in std_logic_vector(1 downto 0); -- response type
mi_hrdata : in std_logic_vector(31 downto 0); -- read data bus
mo_hbusreq : out std_ulogic; -- bus request
mo_htrans : out std_logic_vector(1 downto 0); -- transfer type
mo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte)
mo_hwrite : out std_ulogic; -- read/write
mo_hsize : out std_logic_vector(2 downto 0); -- transfer size
mo_hburst : out std_logic_vector(2 downto 0); -- burst type
mo_hwdata : out std_logic_vector(31 downto 0); -- write data bus
-- APB interface
si_psel : in std_logic; -- slave select
si_penable : in std_ulogic; -- strobe
si_paddr : in std_logic_vector(7 downto 0); -- address bus (byte addr)
si_pwrite : in std_ulogic; -- write
si_pwdata : in std_logic_vector(31 downto 0); -- write data bus
so_prdata : out std_logic_vector(31 downto 0); -- read data bus
so_pirq : out std_logic; -- interrupt bus
-- Aux signals
bcsync : in std_logic;
rtsync : out std_logic;
busreset : out std_logic;
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_logic;
-- 1553 transceiver interface
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaouten : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busbouten : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end;
architecture rtl of gr1553b_stdlogic is
signal gr1553b_txout: gr1553b_txout_type;
signal gr1553b_rxin: gr1553b_rxin_type;
signal mi: ahb_mst_in_type;
signal mo: ahb_mst_out_type;
signal si: apb_slv_in_type;
signal so: apb_slv_out_type;
signal auxin: gr1553b_auxin_type;
signal auxout: gr1553b_auxout_type;
begin
x: gr1553b
generic map (
hindex => 0,
pindex => 0,
paddr => 0,
pmask => 0,
pirq => 0,
bc_enable => bc_enable,
rt_enable => rt_enable,
bm_enable => bm_enable,
bc_timer => bc_timer,
bc_rtbusmask => bc_rtbusmask,
syncrst => syncrst,
extra_regkeys => extra_regkeys,
ahbendian => ahbendian
)
port map (
clk => clk,
rst => rst,
ahbmi => mi,
ahbmo => mo,
apbsi => si,
apbso => so,
codec_clk => codec_clk,
codec_rst => codec_rst,
txout => gr1553b_txout,
txout_fb => gr1553b_txout,
rxin => gr1553b_rxin,
auxin => auxin,
auxout => auxout
);
mi.hgrant(0) <= mi_hgrant;
mi.hgrant(1 to NAHBMST-1) <= (others => '0');
mi.hready <= mi_hready;
mi.hresp <= mi_hresp;
mi.hrdata <= ahbdrivedata(mi_hrdata);
mi.hirq <= (others => '0');
mi.testen <= '0';
mi.testrst <= '0';
mi.scanen <= '0';
mi.testoen <= '0';
mo_hbusreq <= mo.hbusreq;
mo_htrans <= mo.htrans;
mo_haddr <= mo.haddr;
mo_hwrite <= mo.hwrite;
mo_hsize <= mo.hsize;
mo_hburst <= mo.hburst;
mo_hwdata <= ahbreadword(mo.hwdata);
si.psel(0) <= si_psel;
si.psel(1 to NAPBSLV-1) <= (others => '0');
si.penable <= si_penable;
si.paddr <= x"000000" & si_paddr;
si.pwrite <= si_pwrite;
si.pwdata <= si_pwdata;
si.pirq <= (others => '0');
si.testen <= '0';
si.testrst <= '0';
si.scanen <= '0';
si.testoen <= '0';
so_prdata <= so.prdata;
so_pirq <= so.pirq(0);
auxin.extsync <= bcsync;
auxin.rtaddr <= rtaddr;
auxin.rtpar <= rtaddrp;
rtsync <= auxout.rtsync;
busreset <= auxout.busreset;
busainen <= gr1553b_txout.busA_rxen;
gr1553b_rxin.busA_rxP <= busainp;
gr1553b_rxin.busA_rxN <= busainn;
busaouten <= gr1553b_txout.busA_txen;
busaoutp <= gr1553b_txout.busA_txP;
busaoutn <= gr1553b_txout.busA_txN;
busBinen <= gr1553b_txout.busB_rxen;
gr1553b_rxin.busB_rxP <= busBinp;
gr1553b_rxin.busB_rxN <= busBinn;
busBouten <= gr1553b_txout.busB_txen;
busBoutp <= gr1553b_txout.busB_txP;
busBoutn <= gr1553b_txout.busB_txN;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/spi/spi2ahb.vhd | 1 | 2940 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb
-- File: spi2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.spi.all;
entity spi2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb;
architecture rtl of spi2ahb is
signal spi2ahbi : spi2ahb_in_type;
begin
bridge : spi2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter,
cpol => cpol,
cpha => cpha)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
spii => spii,
spio => spio,
spi2ahbi => spi2ahbi,
spi2ahbo => open);
spi2ahbi.en <= '1';
spi2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
spi2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
end architecture rtl;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/i2c/i2c.vhd | 1 | 10223 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: i2c
-- File: i2c.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: I2C interface package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package i2c is
type i2c_in_type is record
scl : std_ulogic;
sda : std_ulogic;
end record;
type i2c_out_type is record
scl : std_ulogic;
scloen : std_ulogic;
sda : std_ulogic;
sdaoen : std_ulogic;
enable : std_ulogic;
end record;
-- AMBA wrapper for OC I2C-master
component i2cmst
generic (
pindex : integer;
paddr : integer;
pmask : integer;
pirq : integer;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
dynfilt : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
component i2cmst_gen
generic (
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
dynfilt : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
prdata : out std_logic_vector(31 downto 0);
irq : out std_logic;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end component;
-- I2C slave
component i2cslv
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
hardaddr : integer range 0 to 1 := 0;
tenbit : integer range 0 to 1 := 0;
i2caddr : integer range 0 to 1023 := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
-- I2C to AHB bridge
type i2c2ahb_in_type is record
haddr : std_logic_vector(31 downto 0);
hmask : std_logic_vector(31 downto 0);
slvaddr : std_logic_vector(6 downto 0);
cfgaddr : std_logic_vector(6 downto 0);
en : std_ulogic;
end record;
type i2c2ahb_out_type is record
dma : std_ulogic;
wr : std_ulogic;
prot : std_ulogic;
end record;
component i2c2ahb
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
component i2c2ahb_apb
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
component i2c2ahbx
generic (
-- AHB configuration
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type;
--
i2c2ahbi : in i2c2ahb_in_type;
i2c2ahbo : out i2c2ahb_out_type
);
end component;
component i2c2ahb_gen
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(31 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(31 downto 0);
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end component;
component i2c2ahb_apb_gen
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
--ahbi : in ahb_mst_in_type;
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(31 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(31 downto 0);
-- APB slave interface
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_irq : out std_logic;
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end component;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/greth/greth2.in.vhd | 4 | 198 | -- Gaisler Ethernet core
constant CFG_GRETH2 : integer := CONFIG_GRETH2_ENABLE;
constant CFG_GRETH21G : integer := CONFIG_GRETH2_GIGA;
constant CFG_ETH2_FIFO : integer := CFG_GRETH2_FIFO;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/clkinv.vhd | 1 | 1888 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkinv
-- File: clkinv.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler Research
-- Description: SET protected inverters for clock tree
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkinv is
generic(tech : integer := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkinv is
begin
tec : if has_clkinv(tech) = 1 generate
saed : if (tech = saed32) generate
x0 : clkinv_saed32 port map (i => i, o => o);
end generate;
dar : if (tech = dare) generate
x0 : clkinv_dare port map (i => i, o => o);
end generate;
end generate;
gen : if has_clkinv(tech) = 0 generate
o <= not i;
end generate;
end architecture;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-avnet-xc2v1500/config.vhd | 1 | 5629 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (16);
constant CFG_DDRSP_RSKEW : integer := (0);
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 1;
constant CFG_PCIVID : integer := 16#1AC8#;
constant CFG_PCIDID : integer := 16#0054#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/stratixiii/adq_dqs/bidir_dq_iobuf_inst.vhd | 3 | 7694 | -- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_bidir
-- ============================================================
-- File Name: bidir_dq_iobuf_inst.vhd
-- Megafunction Name(s):
-- altiobuf_bidir
--
-- Simulation Library Files(s):
-- stratixiii
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2007 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altiobuf_bidir CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix III" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=8 OPEN_DRAIN_OUTPUT="FALSE" USE_DIFFERENTIAL_MODE="FALSE" USE_DYNAMIC_TERMINATION_CONTROL="TRUE" USE_TERMINATION_CONTROL="FALSE" datain dataio dataout dynamicterminationcontrol oe
--VERSION_BEGIN 7.2SP3 cbx_altiobuf_in 2007:08:30:02:46:00:SJ cbx_mgl 2007:08:03:23:48:12:SJ cbx_stratixiii 2007:06:29:01:16:20:SJ VERSION_END
LIBRARY stratixiii;
USE stratixiii.all;
--synthesis_resources = stratixiii_io_ibuf 8 stratixiii_io_obuf 8
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bidir_dq_iobuf_inst_iobuf_bidir_8jr IS
PORT
(
datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
dataio : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
dynamicterminationcontrol : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
oe : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END bidir_dq_iobuf_inst_iobuf_bidir_8jr;
ARCHITECTURE RTL OF bidir_dq_iobuf_inst_iobuf_bidir_8jr IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_ibufa_i : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_ibufa_o : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_obufa_dynamicterminationcontrol : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_obufa_i : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_obufa_o : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_obufa_oe : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT stratixiii_io_ibuf
GENERIC
(
bus_hold : STRING := "false";
differential_mode : STRING := "false";
lpm_type : STRING := "stratixiii_io_ibuf"
);
PORT
(
i : IN STD_LOGIC := '0';
ibar : IN STD_LOGIC := '0';
o : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_io_obuf
GENERIC
(
bus_hold : STRING := "false";
open_drain_output : STRING := "false";
shift_series_termination_control : STRING := "false";
lpm_type : STRING := "stratixiii_io_obuf"
);
PORT
(
dynamicterminationcontrol : IN STD_LOGIC := '0';
i : IN STD_LOGIC := '0';
o : OUT STD_LOGIC;
obar : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
parallelterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
seriesterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
dataio <= wire_obufa_o;
dataout <= wire_ibufa_o;
wire_ibufa_i <= dataio;
loop0 : FOR i IN 0 TO 7 GENERATE
ibufa : stratixiii_io_ibuf
GENERIC MAP (
bus_hold => "false",
differential_mode => "false"
)
PORT MAP (
i => wire_ibufa_i(i),
o => wire_ibufa_o(i)
);
END GENERATE loop0;
wire_obufa_dynamicterminationcontrol <= dynamicterminationcontrol;
wire_obufa_i <= datain;
wire_obufa_oe <= oe;
loop1 : FOR i IN 0 TO 7 GENERATE
obufa : stratixiii_io_obuf
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false"
)
PORT MAP (
dynamicterminationcontrol => wire_obufa_dynamicterminationcontrol(i),
i => wire_obufa_i(i),
o => wire_obufa_o(i),
oe => wire_obufa_oe(i)
);
END GENERATE loop1;
END RTL; --bidir_dq_iobuf_inst_iobuf_bidir_8jr
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bidir_dq_iobuf_inst IS
PORT
(
datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
dyn_term_ctrl : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
dataio : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END bidir_dq_iobuf_inst;
ARCHITECTURE RTL OF bidir_dq_iobuf_inst IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT bidir_dq_iobuf_inst_iobuf_bidir_8jr
PORT (
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
dataio : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
dynamicterminationcontrol : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(7 DOWNTO 0);
bidir_dq_iobuf_inst_iobuf_bidir_8jr_component : bidir_dq_iobuf_inst_iobuf_bidir_8jr
PORT MAP (
datain => datain,
oe => oe,
dynamicterminationcontrol => dyn_term_ctrl,
dataout => sub_wire0,
dataio => dataio
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
-- Retrieval info: CONSTANT: number_of_channels NUMERIC "8"
-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
-- Retrieval info: CONSTANT: use_differential_mode STRING "FALSE"
-- Retrieval info: CONSTANT: use_dynamic_termination_control STRING "TRUE"
-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
-- Retrieval info: USED_PORT: datain 0 0 8 0 INPUT NODEFVAL "datain[7..0]"
-- Retrieval info: USED_PORT: dataio 0 0 8 0 BIDIR NODEFVAL "dataio[7..0]"
-- Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]"
-- Retrieval info: USED_PORT: dyn_term_ctrl 0 0 8 0 INPUT NODEFVAL "dyn_term_ctrl[7..0]"
-- Retrieval info: USED_PORT: oe 0 0 8 0 INPUT NODEFVAL "oe[7..0]"
-- Retrieval info: CONNECT: @datain 0 0 8 0 datain 0 0 8 0
-- Retrieval info: CONNECT: @dynamicterminationcontrol 0 0 8 0 dyn_term_ctrl 0 0 8 0
-- Retrieval info: CONNECT: @oe 0 0 8 0 oe 0 0 8 0
-- Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
-- Retrieval info: CONNECT: dataio 0 0 8 0 @dataio 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dq_iobuf_inst.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dq_iobuf_inst.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dq_iobuf_inst.cmp FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dq_iobuf_inst.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL bidir_dq_iobuf_inst_inst.vhd FALSE FALSE
-- Retrieval info: LIB_FILE: stratixiii
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/sim/sram.vhd | 1 | 5400 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram
-- File: sram.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity sram is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- Clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(7 downto 0);
ce1 : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram is
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**Abits)-1)) of BYTE;
signal DINT,DI,DO : BYTE;
constant ahigh : integer := abits - 1;
signal wrpre : std_ulogic;
function Vpar(vec : std_logic_vector) return std_ulogic is
variable par : std_ulogic := '1';
begin
for i in vec'range loop --'
par := par xor vec(i);
end loop;
return par;
end;
begin
RAM : process(CE1,WE,DI,A,OE,D)
variable MEMA : MEM;
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
begin
if FIRST then
if clear = 1 then MEMA := (others => X"00"); end if;
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
if index = 6 then
recaddr(31 downto abits) := (others => '0');
ai := conv_integer(recaddr);
for i in 0 to 15 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
elsif (index = 4) or (index = 5) then
recaddr(31 downto abits+1) := (others => '0');
ai := conv_integer(recaddr)/2;
for i in 0 to 7 loop
MEMA(ai+i) := recdata((i*16+(index-4)*8) to (i*16+(index-4)*8+7));
end loop;
else
recaddr(31 downto abits+2) := (others => '0');
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
MEMA(ai+i) := recdata((i*32+index*8) to (i*32+index*8+7));
end loop;
end if;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
else
if (TO_X01(not CE1) = '1') then
if not is_x(a) then ai := conv_integer(A(abits-1 downto 0)); else ai := 0; end if;
dint <= mema(ai);
end if;
if (TO_X01(CE1 or WE) = '1') then
if wrpre = '1' then
mema(ai) := to_x01(std_logic_vector(DI));
end if;
end if;
end if;
wrpre <= TO_X01((not CE1) and (not WE));
DI <= D;
end process;
BUFS : process(CE1,WE,DINT,OE)
variable DRIVEB : std_logic;
begin
DRIVEB := TO_X01((not CE1) and (not OE) and WE);
case DRIVEB is
when '1' => D <= DINT after tacc * 1 ns;
when '0' => D <= "ZZZZZZZZ" after 8 ns;
when others => D <= "XXXXXXXX";
end case;
end process;
end sim;
-- pragma translate_on
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-kc705/testbench.vhd | 1 | 19016 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library micron;
use micron.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := true;
USE_MIG_INTERFACE_MODEL : boolean := false
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal adv : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1 , rxd1 , dsurx : std_logic;
signal txd2 , rxd2 , dsutx : std_logic;
signal ctsn1 , rtsn1 , dsuctsn : std_ulogic;
signal ctsn2 , rtsn2 , dsurtsn : std_ulogic;
signal phy_gtxclk : std_logic := '0';
signal phy_txer : std_ulogic;
signal phy_txd : std_logic_vector(7 downto 0);
signal phy_txctl_txen : std_ulogic;
signal phy_txclk : std_ulogic;
signal phy_rxer : std_ulogic;
signal phy_rxd : std_logic_vector(7 downto 0);
signal phy_rxctl_rxdv : std_ulogic;
signal phy_rxclk : std_ulogic;
signal phy_reset : std_ulogic;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_col : std_ulogic;
signal phy_int : std_ulogic;
signal phy_rxdl : std_logic_vector(7 downto 0);
signal phy_txdl : std_logic_vector(7 downto 0);
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal clkethp : std_ulogic := '0';
signal clkethn : std_ulogic := '1';
signal txp1 : std_logic;
signal txn : std_logic;
signal rxp : std_logic := '1';
signal rxn : std_logic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(63 downto 0);
signal ddr3_dqs_p : std_logic_vector(7 downto 0);
signal ddr3_dqs_n : std_logic_vector(7 downto 0);
signal ddr3_addr : std_logic_vector(13 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_cs_n : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(7 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(6 downto 0); -- I/O port
constant lresp : boolean := false;
signal tdqs_n : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_rx_clk : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
adv : out std_logic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_gtxclk : out std_logic;
--phy_txer : out std_ulogic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
--phy_txclk : in std_ulogic;
--phy_rxer : in std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
phy_int : in std_ulogic
);
end component;
component ddr3_model
generic(
ADDR_BITS : integer := 14;
BA_BITS : integer := 3;
DM_BITS : integer := 1;
DQ_BITS : integer := 8;
DQS_BITS : integer := 1
);
port(
rst_n : in std_logic;
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic;
ba : in std_logic_vector(2 downto 0);
addr : in std_logic_vector(13 downto 0);
dq : inout std_logic_vector(7 downto 0);
dqs : inout std_logic;
dqs_n : inout std_logic;
tdqs_n : out std_logic_vector(0 to 0);
odt : in std_logic
);
end component;
begin
-- clock and reset
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
clkethp <= not clkethp after 4 ns;
clkethn <= not clkethp after 4 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch(2 downto 0) <= "000";
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
testahb => testahb,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL
)
port map (
reset => rst,
clk200p => clk200p,
clk200n => clk200n,
address => address,
data => data,
oen => oen,
writen => writen,
romsn => romsn,
adv => adv,
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
dsurx => dsurx,
dsutx => dsutx,
dsuctsn => dsuctsn,
dsurtsn => dsurtsn,
button => button,
switch => switch,
led => led,
iic_scl => iic_scl,
iic_sda => iic_sda,
gtrefclk_p => clkethp,
gtrefclk_n => clkethn,
phy_gtxclk => phy_gtxclk,
--phy_txer => phy_txer,
phy_txd => phy_txd(3 downto 0),
phy_txctl_txen => phy_txctl_txen,
--phy_txclk => phy_txclk,
--phy_rxer => phy_rxer,
phy_rxd => phy_rxd(3 downto 0),
phy_rxctl_rxdv => phy_rxctl_rxdv,
phy_rxclk => phy_rxclk'delayed(1 ns),
phy_reset => phy_reset,
phy_mdio => phy_mdio,
phy_mdc => phy_mdc,
phy_int => phy_int
);
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 22, fname => promfile)
port map (address(21 downto 0), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
-- Memory Models instantiations
gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddr3mem : if (CFG_MIG_SERIES7 = 1) generate
gen_mem: for i in 0 to 7 generate
u1: ddr3_model
generic map(
ADDR_BITS => 14,
BA_BITS => 3,
DM_BITS => 1,
DQ_BITS => 8,
DQS_BITS => 1
)
port map (
rst_n => ddr3_reset_n,
ck => ddr3_ck_p(0),
ck_n => ddr3_ck_n(0),
cke => ddr3_cke(0),
cs_n => ddr3_cs_n(0),
ras_n => ddr3_ras_n,
cas_n => ddr3_cas_n,
we_n => ddr3_we_n,
dm_tdqs => ddr3_dm(i),
ba => ddr3_ba,
addr => ddr3_addr,
dq => ddr3_dq((8*i+7) downto (8*i)),
dqs => ddr3_dqs_p(i),
dqs_n => ddr3_dqs_n(i),
tdqs_n => open,
odt => ddr3_odt(0)
);
end generate gen_mem;
end generate ddr3mem;
end generate gen_mem_model;
mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
end generate mig_mem_model;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
phy_int <= '0';
p0: phy
generic map (address => 7)
port map(phy_reset, phy_mdio, phy_txclk, phy_rxclk, phy_rxd,
phy_rxctl_rxdv, phy_rxer, phy_col, phy_crs, phy_txd,
phy_txctl_txen, phy_txer, phy_mdc, phy_gtxclk);
end generate;
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
wait on led(3); -- DDR3 Memory Init ready
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ; -- this should be a failure
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
switch(3) <= '0';
wait for 2500 ns;
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
dsurst <= '1';
switch(3) <= '1';
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- Wait for DDR3 Memory Init ready
end if;
report "Start DSU transfer";
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- Reads from memory and DSU register to mimic GRMON during simulation
l1 : loop
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU read memory " & tost(w32);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU Break and Single Step register" & tost(w32);
end loop l1;
wait;
-- ** This is only kept for reference --
-- do test read and writes to DDR3 to check status
-- Write
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
report "* Read " & tost(w32);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
-- Register 0x90000000 (DSU Control Register)
-- Data 0x0000202e (b0010 0000 0010 1110)
-- [0] - Trace Enable
-- [1] - Break On Error
-- [2] - Break on IU watchpoint
-- [3] - Break on s/w break points
--
-- [4] - (Break on trap)
-- [5] - Break on error traps
-- [6] - Debug mode (Read mode only)
-- [7] - DSUEN (read mode)
--
-- [8] - DSUBRE (read mode)
-- [9] - Processor mode error (clears error)
-- [10] - processor halt (returns 1 if processor halted)
-- [11] - power down mode (return 1 if processor in power down mode)
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
end;
begin
dsuctsn <= '0';
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/eth/core/eth_rstgen.vhd | 1 | 1946 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: eth_rstgen
-- File: eth_rstgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Reset generation with glitch filter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity eth_rstgen is
generic (acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end;
architecture rtl of eth_rstgen is
signal r : std_logic_vector(4 downto 0);
signal rst : std_ulogic;
begin
rst <= not rstin when acthigh = 1 else rstin;
rstoutraw <= rst;
reg1 : process (clk, rst) begin
if rising_edge(clk) then
r <= r(3 downto 0) & clklock;
rstout <= r(4) and r(3) and r(2);
end if;
if rst = '0' then r <= "00000"; rstout <= '0'; end if;
end process;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-xc3sd-1800/config.vhd | 1 | 7530 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (25);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#001234#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (125);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (32);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (128);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SVGA controller
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/clkand.vhd | 1 | 3752 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkand
-- File: clkand.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock gating
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkand is
generic( tech : integer := 0;
ren : integer range 0 to 1 := 0); -- registered enable
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end entity;
architecture rtl of clkand is
signal eni : std_ulogic;
begin
re : if ren = 1 generate
renproc : process(i)
begin
if falling_edge(i) then eni <= en; end if;
end process;
end generate;
ce : if ren = 0 generate eni <= en; end generate;
struct : if has_clkand(tech) = 1 generate
xil : if is_unisim(tech) = 1 generate
clkgate : clkand_unisim port map(I => i, en => eni, O => o);
end generate;
ut : if (tech = ut25) generate
clkgate : clkand_ut025crh port map(I => i, en => eni, O => o);
end generate;
rhl : if (tech = rhlib18t) generate
clkgate : clkand_rh_lib18t port map(I => i, en => eni, O => o, tsten => tsten);
end generate;
ut13 : if (tech = ut130) generate
clkgate : clkand_ut130hbd port map(I => i, en => eni, O => o, tsten => tsten);
end generate;
ut09 : if (tech = ut90) generate
clkgate : clkand_ut90nhbd port map(I => i, en => eni, O => o, tsten => tsten);
end generate;
n2x : if (tech = easic45) generate
clkgate : clkand_n2x port map(i => i, en => eni, o => o, tsten => tsten);
end generate;
saed : if (tech = saed32) generate
clkgate : clkand_saed32 port map(i => i, en => eni, o => o, tsten => tsten);
end generate;
dar : if (tech = dare) generate
clkgate : clkand_dare port map(i => i, en => eni, o => o, tsten => tsten);
end generate;
end generate;
gen : if has_clkand(tech) = 0 generate
o <= i and (eni or tsten);
end generate;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkrand is
generic( tech : integer := 0);
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end entity;
architecture rtl of clkrand is
signal eni : std_ulogic;
begin
ut13 : if (tech = ut130) generate
eni <= en or tsten;
clkgate : clkrand_ut130hbd port map(I => i, en => en, O => o);
end generate;
nonut13 : if (tech /= ut130) generate
clkgate : clkand generic map (tech, 1)
port map (i, en, o, tsten);
end generate;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/iu3.vhd | 1 | 131748 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libfpu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0;
bp : integer range 0 to 2 := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
attribute sync_set_reset of rstn : signal is "true";
end;
architecture rtl of iu3 is
constant ISETMSB : integer := log2x(isets)-1;
constant DSETMSB : integer := log2x(dsets)-1;
constant RFBITS : integer range 6 to 10 := log2(NWIN+1) + 4;
constant NWINLOG2 : integer range 1 to 5 := log2(NWIN);
constant CWPOPT : boolean := (NWIN = (2**NWINLOG2));
constant CWPMIN : std_logic_vector(NWINLOG2-1 downto 0) := (others => '0');
constant CWPMAX : std_logic_vector(NWINLOG2-1 downto 0) :=
conv_std_logic_vector(NWIN-1, NWINLOG2);
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := (cp = 1);
constant MULEN : boolean := (v8 /= 0);
constant MULTYPE: integer := (v8 / 16);
constant DIVEN : boolean := (v8 /= 0);
constant MACEN : boolean := (mac = 1);
constant MACPIPE: boolean := (mac = 1) and (v8/2 = 1);
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := (dsu = 1);
constant TRACEBUF : boolean := (tbuf /= 0);
constant TBUFBITS : integer := 10 + log2(tbuf) - 4;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := (pwd /= 0); --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := (is_fpga(FABTECH) /= 0);
constant DYNRST : boolean := (rstaddr = 16#FFFFF#);
constant CASAEN : boolean := (notag = 0) and (lddel = 1);
signal BPRED : std_logic;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto PCLOW);
subtype rfatype is std_logic_vector(RFBITS-1 downto 0);
subtype cwptype is std_logic_vector(NWINLOG2-1 downto 0);
type icdtype is array (0 to isets-1) of word;
type dcdtype is array (0 to dsets-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock, dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(ISETMSB downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
divrdy: std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
bp, nobp : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
bp : std_ulogic;
rfe1, rfe2 : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
casa : std_ulogic;
casaz : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(DSETMSB downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
ipmask : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(TBUFBITS-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(NWIN-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
dbp : std_ulogic; -- disable branch prediction
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := (others => '0');
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and TRACEBUF then -- trace buffer control reg
tbufcnt := dbg.ddata(TBUFBITS-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := (others => '0');
addr(RFBITS-1 downto 0) := dbg.daddr(RFBITS+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(NWINLOG2-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(NWIN-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto PCLOW);
when "0101" => -- NPC
npc := dbg.ddata(31 downto PCLOW);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
if bp = 2 then s.dbp := dbg.ddata(27); end if;
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if MACEN then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := zero32;
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if bp = 2 then asr17(27) := r.w.s.dbp; end if;
if notag = 0 then asr17(26) := '1'; end if; -- CASA and tagged arith
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if v8 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(nwin-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := (others => '0'); cwp := (others => '0');
cwp(NWINLOG2-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if TRACEBUF then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
data(TBUFBITS-1 downto 0) := dsur.tbufcnt;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
if dbgi.daddr(11) = '0' then
data := rfo.data1(31 downto 0);
else data := rfo.data2(31 downto 0); end if;
else
data := fpo.dbg.data;
end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(IMPL, 4) & conv_std_logic_vector(VER, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(NWIN-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto PCLOW) := r.f.pc;
when "0101" =>
data(31 downto PCLOW) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif MACEN and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
di : out tracebuf_in_type;
ierr : in std_ulogic;
derr : in std_ulogic
) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if TRACEBUF then
di.addr(TBUFBITS-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & dco.scanen & "00";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if DBGUNIT then
if (r.x.rstate = dsu2)
then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant dc_in_res : dc_in_type := (
signed => '0',
enaddr => '0',
read => '0',
write => '0',
lock => '0',
dsuen => '0',
size => (others => '0'),
asi => (others => '0'));
constant pipeline_ctrl_res : pipeline_ctrl_type := (
pc => (others => '0'),
inst => (others => '0'),
cnt => (others => '0'),
rd => (others => '0'),
tt => (others => '0'),
trap => '0',
annul => '1',
wreg => '0',
wicc => '0',
wy => '0',
ld => '0',
pv => '0',
rett => '0');
constant fpc_res : pctype := conv_std_logic_vector(rstaddr, 20) & zero32(11 downto PCLOW);
constant fetch_reg_res : fetch_reg_type := (
pc => fpc_res, -- Needs special handling
branch => '0'
);
constant decode_reg_res : decode_reg_type := (
pc => (others => '0'),
inst => (others => (others => '0')),
cwp => (others => '0'),
set => (others => '0'),
mexc => '0',
cnt => (others => '0'),
pv => '0',
annul => '1',
inull => '0',
step => '0',
divrdy => '0'
);
constant regacc_reg_res : regacc_reg_type := (
ctrl => pipeline_ctrl_res,
rs1 => (others => '0'),
rfa1 => (others => '0'),
rfa2 => (others => '0'),
rsel1 => (others => '0'),
rsel2 => (others => '0'),
rfe1 => '0',
rfe2 => '0',
cwp => (others => '0'),
imm => (others => '0'),
ldcheck1 => '0',
ldcheck2 => '0',
ldchkra => '1',
ldchkex => '1',
su => '1',
et => '0',
wovf => '0',
wunf => '0',
ticc => '0',
jmpl => '0',
step => '0',
mulstart => '0',
divstart => '0',
bp => '0',
nobp => '0'
);
constant execute_reg_res : execute_reg_type := (
ctrl => pipeline_ctrl_res,
op1 => (others => '0'),
op2 => (others => '0'),
aluop => (others => '0'),
alusel => "11",
aluadd => '1',
alucin => '0',
ldbp1 => '0',
ldbp2 => '0',
invop2 => '0',
shcnt => (others => '0'),
sari => '0',
shleft => '0',
ymsb => '0',
rd => (others => '0'),
jmpl => '0',
su => '0',
et => '0',
cwp => (others => '0'),
icc => (others => '0'),
mulstep => '0',
mul => '0',
mac => '0',
bp => '0',
rfe1 => '0',
rfe2 => '0'
);
constant memory_reg_res : memory_reg_type := (
ctrl => pipeline_ctrl_res,
result => (others => '0'),
y => (others => '0'),
icc => (others => '0'),
nalign => '0',
dci => dc_in_res,
werr => '0',
wcwp => '0',
irqen => '0',
irqen2 => '0',
mac => '0',
divz => '0',
su => '0',
mul => '0',
casa => '0',
casaz => '0'
);
function xnpc_res return std_logic_vector is
begin
if v8 /= 0 then return "100"; end if;
return "011";
end function xnpc_res;
constant exception_reg_res : exception_reg_type := (
ctrl => pipeline_ctrl_res,
result => (others => '0'),
y => (others => '0'),
icc => (others => '0'),
annul_all => '1',
data => (others => (others => '0')),
set => (others => '0'),
mexc => '0',
dci => dc_in_res,
laddr => (others => '0'),
rstate => run, -- Has special handling
npc => xnpc_res,
intack => '0',
ipend => '0',
mac => '0',
debug => '0', -- Has special handling
nerror => '0',
ipmask => '0'
);
constant DRES : dsu_registers := (
tt => (others => '0'),
err => '0',
tbufcnt => (others => '0'),
asi => (others => '0'),
crdy => (others => '0')
);
constant IRES : irestart_register := (
addr => (others => '0'), pwd => '0'
);
constant PRES : pwd_register_type := (
pwd => '0', -- Needs special handling
error => '0'
);
--constant special_register_res : special_register_type := (
-- cwp => zero32(NWINLOG2-1 downto 0),
-- icc => (others => '0'),
-- tt => (others => '0'),
-- tba => fpc_res(31 downto 12),
-- wim => (others => '0'),
-- pil => (others => '0'),
-- ec => '0',
-- ef => '0',
-- ps => '1',
-- s => '1',
-- et => '0',
-- y => (others => '0'),
-- asr18 => (others => '0'),
-- svt => '0',
-- dwt => '0',
-- dbp => '0'
-- );
--XST workaround:
function special_register_res return special_register_type is
variable s : special_register_type;
begin
s.cwp := zero32(NWINLOG2-1 downto 0);
s.icc := (others => '0');
s.tt := (others => '0');
s.tba := fpc_res(31 downto 12);
s.wim := (others => '0');
s.pil := (others => '0');
s.ec := '0';
s.ef := '0';
s.ps := '1';
s.s := '1';
s.et := '0';
s.y := (others => '0');
s.asr18 := (others => '0');
s.svt := '0';
s.dwt := '0';
s.dbp := '0';
return s;
end function special_register_res;
--constant write_reg_res : write_reg_type := (
-- s => special_register_res,
-- result => (others => '0'),
-- wa => (others => '0'),
-- wreg => '0',
-- except => '0'
-- );
-- XST workaround:
function write_reg_res return write_reg_type is
variable w : write_reg_type;
begin
w.s := special_register_res;
w.result := (others => '0');
w.wa := (others => '0');
w.wreg := '0';
w.except := '0';
return w;
end function write_reg_res;
constant RRES : registers := (
f => fetch_reg_res,
d => decode_reg_res,
a => regacc_reg_res,
e => execute_reg_res,
m => memory_reg_res,
x => exception_reg_res,
w => write_reg_res
);
constant exception_res : exception_type := (
pri => '0',
ill => '0',
fpdis => '0',
cpdis => '0',
wovf => '0',
wunf => '0',
ticc => '0'
);
constant wpr_none : watchpoint_register := (
addr => zero32(31 downto 2),
mask => zero32(31 downto 2),
exec => '0',
load => '0',
store => '0');
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(RFBITS-5 downto 0) :=
conv_std_logic_vector(NWIN, RFBITS-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(RFBITS -1 downto 4) := globals;
else
ra(NWINLOG2+3 downto 4) := cwp + ra(4);
if ra(RFBITS-1 downto 4) = globals then
ra(RFBITS-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = Zero32(31 downto 2)) then
exc := '1';
end if;
end if;
end loop;
if DBGUNIT then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := zero32 & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := zero32; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not MACEN then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not MULEN then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not DIVEN then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY =>
if rd(4) = '1' and rd(3 downto 0) /= "0010" then -- %ASR16-17, %ASR19-31
privileged_inst := not r.a.su;
end if;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when CASA =>
if CASAEN then
illegal_inst := inst(13);
if (inst(12 downto 5) /= X"0A") then privileged_inst := not r.a.su; end if;
else illegal_inst := '1'; end if;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := r.a.ctrl.tt;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if MACEN then wy := '1'; end if;
when UMULCC | SMULCC =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if DIVEN and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or
(r.x.rstate = dsu2)
or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(NWINLOG2-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(NWIN-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(NWIN-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not CWPOPT) and (r.d.cwp = CWPMIN) then ncwp := CWPMAX;
else ncwp := r.d.cwp - 1 ; end if;
else
if (not CWPOPT) and (r.d.cwp = CWPMAX) then ncwp := CWPMIN;
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
function icc_valid(r : registers) return std_logic is
variable not_valid : std_logic;
begin
not_valid := '0';
if MULEN or DIVEN then
not_valid := r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul);
end if;
not_valid := not_valid or (r.a.ctrl.wicc or r.e.ctrl.wicc);
return(not not_valid);
end;
procedure bp_miss_ex(r : registers; icc : std_logic_vector(3 downto 0);
ex_bpmiss, ra_bpannul : out std_logic) is
variable miss : std_logic;
begin
miss := (not r.e.ctrl.annul) and r.e.bp and not branch_true(icc, r.e.ctrl.inst);
ra_bpannul := miss and r.e.ctrl.inst(29);
ex_bpmiss := miss;
end;
procedure bp_miss_ra(r : registers; ra_bpmiss, de_bpannul : out std_logic) is
variable miss : std_logic;
begin
miss := ((not r.a.ctrl.annul) and r.a.bp and icc_valid(r) and not branch_true(r.m.icc, r.a.ctrl.inst));
de_bpannul := miss and r.a.ctrl.inst(29);
ra_bpmiss := miss;
end;
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn, de_wcwp : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex, bp, nobp, de_fins_hold : out std_ulogic;
iperr : std_logic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_logic;
variable icc_check_bp, y_hold, mul_hold, bicc_hold_bp, fins, call_hold : std_ulogic;
variable de_fins_holdx : std_ulogic;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0'; y_hold := '0'; bp := '0'; mul_hold := '0';
icc_check_bp := '0'; nobp := '0'; fins := '0'; call_hold := '0';
if (r.d.annul = '0')
then
case op is
when CALL =>
call_hold := '1'; nobp := BPRED;
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check_bp := '1';
end if;
if (op2 = BICC) then nobp := BPRED; end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
nobp := BPRED;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if MACPIPE then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
when SDIV | SDIVCC | UDIV | UDIVCC =>
if DIVEN then y_check := '1'; nobp := op3(4); end if; -- no BP on divcc
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0'; fins := BPRED;
when JMPL => call_hold := '1'; nobp := BPRED;
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') and (op3(5) = '0') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" =>
ldcheck2 := not i;
if (op3(5) and op3(2) and not op3(3)) = '1' then ldcheck1 := '0'; ldcheck2 := '0'; end if; -- STF/STC
when others => ldchkex := '0';
if CASAEN and (op3(5 downto 3) = "111") then
ldcheck2 := '1';
elsif (op3(5) = '1') or ((op3(5) & op3(3 downto 1)) = "0110") -- LDST
then ldcheck1 := '0'; ldcheck2 := '0'; end if;
end case;
if op3(5) = '1' then fins := BPRED; end if; -- no BP on FPU/CP LD/ST
when others => null;
end case;
end if;
if MULEN or DIVEN then
chkmul := mulinsn;
mul_hold := (r.a.mulstart and r.a.ctrl.wicc) or (r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
if (MULTYPE = 0) and ((icc_check_bp and BPRED and r.a.ctrl.wicc and r.a.ctrl.wy) = '1')
then mul_hold := '1'; end if;
else chkmul := '0'; end if;
if DIVEN then
y_hold := y_check and (r.a.ctrl.wy or r.e.ctrl.wy);
chkmul := chkmul or divinsn;
end if;
bicc_hold := icc_check and not icc_valid(r);
bicc_hold_bp := icc_check_bp and not icc_valid(r);
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (MACPIPE and (r.e.mac = '1')) or ((MULTYPE = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
de_fins_holdx := BPRED and fins and (r.a.bp or r.e.bp); -- skip BP on FPU inst in branch target address
de_fins_hold := de_fins_holdx;
ldlock := ldlock or y_hold or fpc_lock or (BPRED and r.a.bp and r.a.ctrl.inst(29) and de_wcwp) or de_fins_holdx;
if ((icc_check_bp and BPRED) = '1') and ((r.a.nobp or mul_hold) = '0') then
bp := bicc_hold_bp;
else ldlock := ldlock or bicc_hold or bicc_hold_bp; end if;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic; rabpmiss, exbpmiss, iperr : std_logic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl, inhibit_current : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0'; inhibit_current := '0';
if (r.d.annul = '0')
then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (CPEN and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (CPEN and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true or (BPRED and orv(cond) and not icc_valid(r)); end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul_next or annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN and (MULTYPE /= 0) then mulstart := '1'; end if;
if MULEN and (MULTYPE = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
case r.d.cnt is
when "00" =>
hold_pc := '1'; pv := '0';
if r.d.divrdy = '0' then
cnt := "01"; divstart := '1';
end if;
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if PWRD1 then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD/CASA
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
(CASAEN and (op3(5 downto 4) = "11")) or -- CASA
((CPEN or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if ((exbpmiss and r.a.ctrl.annul and r.d.pv and not hold_pc) = '1') then
annul_next := '1'; pv := '0';
end if;
if ((exbpmiss and not r.a.ctrl.annul and r.d.pv) = '1') then
annul_next := '1'; pv := '0'; annul_current := '1';
end if;
if ((exbpmiss and not r.a.ctrl.annul and not r.d.pv and not hold_pc) = '1') then
annul_next := '1'; pv := '0';
end if;
if ((exbpmiss and r.e.ctrl.inst(29) and not r.a.ctrl.annul and not r.d.pv ) = '1')
and (r.d.cnt = "01") then
annul_next := '1'; annul_current := '1'; pv := '0';
end if;
if (exbpmiss and r.e.ctrl.inst(29) and r.a.ctrl.annul and r.d.pv) = '1' then
annul_next := '1'; pv := '0'; inhibit_current := '1';
end if;
if (rabpmiss and not r.a.ctrl.inst(29) and not r.d.annul and r.d.pv and not hold_pc) = '1' then
annul_next := '1'; pv := '0';
end if;
if (rabpmiss and r.a.ctrl.inst(29) and not r.d.annul and r.d.pv ) = '1' then
annul_next := '1'; pv := '0'; inhibit_current := '1';
end if;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or (ldlock and not inhibit_current) or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current or inhibit_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current and not inhibit_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((CPEN or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA | CASA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(IMPL,4) &
conv_std_logic_vector(VER,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(NWINLOG2-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(NWIN-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_logic
) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0, i : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
rs1 := r.a.ctrl.inst(18 downto 14); i := r.a.ctrl.inst(13);
rs2 := r.a.ctrl.inst(4 downto 0); rd := r.a.ctrl.inst(29 downto 25);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if MULEN then mulins := '1'; end if;
when UMAC | SMAC =>
if MACEN then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if DIVEN then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA | CASA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(5) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB
end if;
if CASAEN and (r.m.casa = '1') then
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word; id : std_logic) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
if CASAEN and (r.a.ctrl.cnt = "10") and ((r.m.casa and not id) = '1') then ldbp := '1'; end if;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif (r.m.ctrl.wreg = '1') and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and (r.x.ctrl.wreg = '1') and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when LDST =>
if CASAEN and (r.m.casa = '1') and (r.a.ctrl.cnt = "10") then
cin := '1';
end if;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if DIVEN then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif MACPIPE and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
function st_align(size : std_logic_vector(1 downto 0); bpdata : word) return word is
variable edata : word;
begin
case size is
when "01" => edata := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
when "10" => edata := bpdata(15 downto 0) & bpdata(15 downto 0);
when others => edata := bpdata;
end case;
return(edata);
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if MULEN and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if MACEN then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz, mzero : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
variable azero : std_logic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
if addout(32 downto 1) = zero32 then azero := '1'; else azero := '0'; end if;
mzero := azero;
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
-- if aluresult = zero32 then icc(2) := '1'; end if;
icc(2) := azero;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = zero32 then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load, mcasa : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su, lock : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
mcasa := '0';
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when CASA => if CASAEN then dci.size := SZWORD; dci.lock := '1'; end if;
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if CPEN then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul or r.e.ctrl.trap) = '0' then
case op is
when CALL => link_pc := '1';
when FMT3 =>
if r.e.ctrl.trap = '0' then
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
end if;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP/CASA
load := op3(3) or not op3(2);
--dci.enaddr := '1';
dci.enaddr := (not op3(2)) or op3(2)
or (op3(3) and op3(2));
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if (CASAEN and (op3(5 downto 4) = "11")) or -- CASA
(op3(3 downto 2) = "11") then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP/CASA
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
if (CASAEN and (op3(5 downto 4) = "11")) then mcasa := '1'; end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not CPEN) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
if CASAEN and (r.m.casa = '1') and (r.e.ctrl.cnt = "10") then
edata2 := r.e.op1; eres2 := r.e.op1;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(DSETMSB downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(NWINLOG2-1 downto 0);
variable cwpx : std_logic_vector(5 downto NWINLOG2);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto NWINLOG2); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if (trap = '1') and (r.m.ctrl.pv = '1') then
if op = LDST then nullify := '1'; end if;
end if;
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if CPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if CPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif CPEN and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA | CASA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = zero32(31 downto 2)))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd
;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif MACEN and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
if bp = 2 then s.dbp := r.x.result(27); end if;
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(NWINLOG2-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(NWIN-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then s.cwp := CWPMAX;
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if MACPIPE and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif v8 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if v8 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if MULEN then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if MULEN then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if MACEN and not MACPIPE then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if DIVEN then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if DIVEN then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
begin
BPRED <= '0' when bp = 0 else '1' when bp = 1 else not r.w.s.dbp;
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo,
mulo, divo, dummy, rp, BPRED)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable fe_pc, fe_npc : std_logic_vector(31 downto PCLOW);
variable npc : std_logic_vector(31 downto PCLOW);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable de_bpannul : std_ulogic;
variable de_fins_hold : std_ulogic;
variable de_iperr : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ra_bpmiss : std_ulogic;
variable ra_bpannul : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, ex_result3, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable ex_bpmiss : std_ulogic;
variable ex_cdata : std_logic_vector(31 downto 0);
variable ex_mulop1, ex_mulop2 : std_logic_vector(32 downto 0);
variable me_bp_res : word;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_newtt, xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable xc_dflushl : std_ulogic;
variable xc_dcperr : std_ulogic;
variable st : std_ulogic;
variable icnt, fcnt : std_ulogic;
variable tbufcntx : std_logic_vector(TBUFBITS-1 downto 0);
variable bpmiss : std_ulogic;
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0'; fcnt := '0';
xc_waddr := (others => '0');
xc_waddr(RFBITS-1 downto 0) := r.x.ctrl.rd(RFBITS-1 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error; xc_dflushl := '0';
if r.x.mexc = '1' then xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 2) := r.w.s.tba & xc_vectt & "00";
else
xc_trap_address(31 downto 2) := r.w.s.tba & "00000000" & "00";
end if;
xc_trap_address(2 downto PCLOW) := (others => '0');
xc_wreg := '0'; v.x.annul_all := '0';
if (not r.x.ctrl.annul and r.x.ctrl.ld) = '1' then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
elsif MACEN and MACPIPE and ((not r.x.ctrl.annul and r.x.mac) = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if DBGUNIT
then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if PWRD2 then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (dbgm
) /= '0' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
if (r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
if (r.x.ctrl.inst(31 downto 30) = FMT3) and
((r.x.ctrl.inst(24 downto 19) = FPOP1) or
(r.x.ctrl.inst(24 downto 19) = FPOP2))
then fcnt := holdn; end if;
end if;
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0010";
if r.w.s.et = '1' then
v.w.s.et := '0'; v.x.rstate := run;
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := CWPMAX;
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0)
then
xc_trap_address(31 downto PCLOW) := ir.addr;
vir.addr := npc_gen(r)(31 downto PCLOW);
v.x.rstate := dsu2;
end if;
if DBGUNIT then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0)
then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if DBGUNIT then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto PCLOW) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
dci.flushl <= xc_dflushl;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi, '0', xc_dcperr);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(RFBITS-1 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.diag <= dco.testen & dco.scanen & "00";
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
irqo.idle <= '0';
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dbgo.fcnt <= fcnt;
dbgo.optype <= r.x.ctrl.inst(31 downto 30) & r.x.ctrl.inst(24 downto 21);
dci.intack <= r.x.intack and holdn;
if (not RESET_ALL) and (xc_rstn = '0') then
v.w.except := RRES.w.except; v.w.s.et := RRES.w.s.et;
v.w.s.svt := RRES.w.s.svt; v.w.s.dwt := RRES.w.s.dwt;
v.w.s.ef := RRES.w.s.ef;
if need_extra_sync_reset(fabtech) /= 0 then
v.w.s.cwp := RRES.w.s.cwp;
v.w.s.icc := RRES.w.s.icc;
end if;
v.w.s.dbp := RRES.w.s.dbp;
v.x.ipmask := RRES.x.ipmask;
v.w.s.tba := RRES.w.s.tba;
v.x.annul_all := RRES.x.annul_all;
v.x.rstate := RRES.x.rstate; vir.pwd := IRES.pwd;
vp.pwd := PRES.pwd; v.x.debug := RRES.x.debug;
v.x.nerror := RRES.x.nerror;
if svt = 1 then v.w.s.tt := RRES.w.s.tt; end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
end if;
if (index /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
v.x.npc := "100";
end if;
-- kill off unused regs
if not FPEN then v.w.s.ef := '0'; end if;
if not CPEN then v.w.s.ec := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
st := '0';
if CASAEN and (r.m.casa = '1') and (r.m.ctrl.cnt = "00") then
v.x.ctrl.inst(4 downto 0) := r.a.ctrl.inst(4 downto 0); -- restore rs2 for trace log
end if;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or st or not dco.mds) = '1' then
for i in 0 to dsets-1 loop
v.x.data(i) := dco.data(i);
end loop;
v.x.set := dco.set(DSETMSB downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if (lddel /= 2) then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
if (not RESET_ALL) and (is_fpga(fabtech) = 0) and (xc_rstn = '0') then
v.x.data := (others => (others => '0')); --v.x.ldc := '0';
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if MACEN and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2)
then
me_nullify2 := '0'; v.x.set := dco.set(DSETMSB downto 0);
end if;
if (not RESET_ALL) and (xc_rstn = '0') then
v.x.ctrl.trap := '0'; v.x.ctrl.annul := '1';
end if;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.lock <= (r.m.dci.lock and not r.m.ctrl.annul);
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if MULTYPE = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load, v.m.casa);
ex_jump_address := ex_add_res(32 downto PCLOW+1);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz, v.m.casaz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, ex_result3);
v.m.result := ex_result3;
cwp_ex(r, v.m.wcwp);
if CASAEN and (r.e.ctrl.cnt = "10") and ((r.m.casa and not v.m.casaz) = '1') then
me_nullify2 := '1';
end if;
dci.nullify <= me_nullify2;
ex_mulop1 := (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
ex_mulop2 := (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
if is_fpga(fabtech) = 0 and (r.e.mul = '0') then -- power-save for mul
-- if (r.e.mul = '0') then
ex_mulop1 := (others => '0'); ex_mulop2 := (others => '0');
end if;
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (DBGUNIT and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
bp_miss_ex(r, r.m.icc, ex_bpmiss, ra_bpannul);
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl and not r.a.ctrl.trap;
v.e.ctrl.annul := r.a.ctrl.annul or ra_bpannul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul and not r.a.ctrl.trap;
v.e.ctrl.wreg := r.a.ctrl.wreg and not (ra_bpannul or v.x.annul_all);
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not (ra_bpannul or v.x.annul_all);
v.e.rfe1 := r.a.rfe1; v.e.rfe2 := r.a.rfe2;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, ex_result3, v.x.result, xc_df_result, zero32,
r.a.rsel1, v.e.ldbp1, ra_op1, '0');
op_mux(r, rfo.data2, ex_result3, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2, '1');
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2
);
cin_gen(r, v.m.icc(0), v.e.alucin);
bp_miss_ra(r, ra_bpmiss, de_bpannul);
v.e.bp := r.a.bp and not ra_bpmiss;
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if ISETS > 1 then de_inst := r.d.inst(conv_integer(r.d.set));
else de_inst := r.d.inst(0); end if;
de_icc := r.m.icc; v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
if CASAEN and (de_inst(31 downto 30) = LDST) and (de_inst(24 downto 19) = CASA) then
case r.d.cnt is
when "00" | "01" => de_inst(4 downto 0) := "00000"; -- rs2=0
when others =>
end case;
end if;
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := (others => '0'); de_raddr2 := (others => '0');
if RS1OPT then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(RFBITS-1 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(RFBITS-1 downto 0));
v.a.rfa1 := de_raddr1(RFBITS-1 downto 0);
v.a.rfa2 := de_raddr2(RFBITS-1 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
de_iperr := '0';
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, de_wcwp, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex, v.a.bp, v.a.nobp, de_fins_hold, de_iperr);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart,
ra_bpmiss, ex_bpmiss, de_iperr);
v.a.bp := v.a.bp and not v.a.ctrl.annul;
v.a.nobp := v.a.nobp and not v.a.ctrl.annul;
v.a.ctrl.inst := de_inst;
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1,
false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2,
imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
v.a.ctrl.wicc := v.a.ctrl.wicc and (not v.a.ctrl.annul)
;
v.a.ctrl.wreg := v.a.ctrl.wreg and (not v.a.ctrl.annul)
;
v.a.ctrl.rett := v.a.ctrl.rett and (not v.a.ctrl.annul)
;
v.a.ctrl.wy := v.a.ctrl.wy and (not v.a.ctrl.annul)
;
v.a.ctrl.trap := r.d.mexc
;
v.a.ctrl.tt := "000000";
if r.d.mexc = '1' then
v.a.ctrl.tt := "000001";
end if;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(RFBITS-1 downto 0) := r.a.rfa1;
de_raddr2(RFBITS-1 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if DBGUNIT then
if (dbgi.denable = '1') and (r.x.rstate = dsu2) then
de_raddr1(RFBITS-1 downto 0) := dbgi.daddr(RFBITS+1 downto 2); de_ren1 := '1';
de_raddr2 := de_raddr1; de_ren2 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
ici.inull <= de_inull
;
ici.flush <= me_iflush;
v.d.divrdy := divo.nready;
ici.fline <= r.x.ctrl.pc(31 downto 3);
dbgo.bpmiss <= bpmiss and holdn;
if (xc_rstn = '0') then
v.d.cnt := (others => '0');
if need_extra_sync_reset(fabtech) /= 0 then
v.d.cwp := (others => '0');
end if;
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
bpmiss := ex_bpmiss or ra_bpmiss;
npc := r.f.pc; fe_pc := r.f.pc;
if ra_bpmiss = '1' then fe_pc := r.d.pc; end if;
if ex_bpmiss = '1' then fe_pc := r.a.ctrl.pc; end if;
fe_npc := zero32(31 downto PCLOW);
fe_npc(31 downto 2) := fe_pc(31 downto 2) + 1; -- Address incrementer
if (xc_rstn = '0') then
if (not RESET_ALL) then
v.f.pc := (others => '0'); v.f.branch := '0';
if DYNRST then v.f.pc(31 downto 12) := irqi.rstvec;
else
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
end if;
end if;
elsif xc_exception = '1' then -- exception
v.f.branch := '1'; v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc; v.f.branch := r.f.branch;
if bpmiss = '1' then
v.f.pc := fe_npc; v.f.branch := '1';
npc := v.f.pc;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
end if;
elsif (ex_jump and not bpmiss) = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
elsif (de_branch and not bpmiss
) = '1'
then
v.f.pc := branch_address(de_inst, r.d.pc); v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := bpmiss; v.f.pc := fe_npc; npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to isets-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(ISETMSB downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if DBGUNIT then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul and
not r.a.ctrl.trap and not ra_bpannul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= ex_mulop1; --(ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= ex_mulop2; --(mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if MACPIPE then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul and
not r.a.ctrl.trap and not ra_bpannul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else dsign := r.e.ctrl.inst(19); end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if DBGUNIT then
dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if TRACEBUF then tbi <= tbufi; else
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0'; tbi.addr <= (others => '0');
tbi.data <= (others => '0'); tbi.enable <= '0';
tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
dbgo.error <= dummy and not r.x.nerror;
dbgo.wbhold <= '0'; --dco.wbhold;
dbgo.su <= r.w.s.s;
dbgo.istat <= ('0', '0', '0', '0');
dbgo.dstat <= ('0', '0', '0', '0');
if FPEN then
if (r.x.rstate = dsu2) then vfpi.flush := '1'; else vfpi.flush := v.x.annul_all and holdn; end if;
vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or de_bpannul or r.d.annul or de_fins_hold
;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto PCLOW) := r.d.pc(31 downto PCLOW);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto PCLOW) := r.a.ctrl.pc(31 downto PCLOW);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul or (ex_bpmiss and r.e.ctrl.inst(29))
;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto PCLOW) := r.e.ctrl.pc(31 downto PCLOW);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto PCLOW) := r.m.ctrl.pc(31 downto PCLOW);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto PCLOW) := r.x.ctrl.pc(31 downto PCLOW);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv;
if (lddel = 2) then vfpi.lddata := r.x.data(conv_integer(r.x.set)); else vfpi.lddata := r.x.data(0); end if;
if (r.x.rstate = dsu2)
then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
end if;
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= PRES.error;
if RESET_ALL then
if (index /= 0) and (irqi.run = '0') then
rp.pwd <= '1';
else
rp.pwd <= '0';
end if;
end if;
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
if RESET_ALL then
r <= RRES;
if DYNRST then
r.f.pc(31 downto 12) <= irqi.rstvec;
r.w.s.tba <= irqi.rstvec;
end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
r.x.rstate <= dsu1; r.x.debug <= '1';
end if;
end if;
if (index /= 0) and irqi.run = '0' then
r.x.rstate <= dsu1;
end if;
else
r.w.s.s <= '1'; r.w.s.ps <= '1';
if need_extra_sync_reset(fabtech) /= 0 then
r.d.inst <= (others => (others => '0'));
r.x.mexc <= '0';
end if;
end if;
end if;
end if;
end process;
dsugen : if DBGUNIT generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if rstn = '0' then
if RESET_ALL then
dsur <= DRES;
elsif need_extra_sync_reset(fabtech) /= 0 then
dsur.err <= '0'; dsur.tbufcnt <= (others => '0'); dsur.tt <= (others => '0');
dsur.asi <= (others => '0'); dsur.crdy <= (others => '0');
end if;
end if;
end if;
end process;
end generate;
nodsugen : if not DBGUNIT generate
dsur.err <= '0'; dsur.tbufcnt <= (others => '0'); dsur.tt <= (others => '0');
dsur.asi <= (others => '0'); dsur.crdy <= (others => '0');
end generate;
irreg : if DBGUNIT or PWRD2
generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then ir <= irin; end if;
if RESET_ALL and rstn = '0' then ir <= IRES; end if;
end if;
end process;
end generate;
nirreg : if not (DBGUNIT or PWRD2
)
generate
ir.pwd <= '0'; ir.addr <= (others => '0');
end generate;
wpgen : for i in 0 to 3 generate
wpg0 : if nwp > i generate
wpreg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then wpr(i) <= wprin(i); end if;
if rstn = '0' then
if RESET_ALL then
wpr(i) <= wpr_none;
else
wpr(i).exec <= '0'; wpr(i).load <= '0'; wpr(i).store <= '0';
end if;
end if;
end if;
end process;
end generate;
wpg1 : if nwp <= i generate
wpr(i) <= wpr_none;
end generate;
end generate;
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
if (fpu /= 0) then
op := r.x.ctrl.inst(31 downto 30); op3 := r.x.ctrl.inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
else
fpins := false; fpld := false;
end if;
valid := (((not r.x.ctrl.annul) and r.x.ctrl.pv) = '1') and (not ((fpins or fpld) and (r.x.ctrl.trap = '0')));
valid := valid and (holdn = '1');
if (disas = 1) and rising_edge(clk) and (rstn = '1') then
print_insn (index, r.x.ctrl.pc(31 downto 2) & "00", r.x.ctrl.inst,
rin.w.result, valid, r.x.ctrl.trap = '1', rin.w.wreg = '1',
rin.x.ipmask = '1');
end if;
end process;
-- pragma translate_on
dis0 : if disas < 2 generate dummy <= '1'; end generate;
dis2 : if disas > 1 generate
disasen <= '1' when disas /= 0 else '0';
cpu_index <= conv_std_logic_vector(index, 4);
x0 : cpu_disasx
port map (clk, rstn, dummy, r.x.ctrl.inst, r.x.ctrl.pc(31 downto 2),
rin.w.result, cpu_index, rin.w.wreg, r.x.ctrl.annul, holdn,
r.x.ctrl.pv, r.x.ctrl.trap, disasen);
end generate;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/tech/cycloneiii/simprims/cycloneiii_components.vhd | 2 | 38350 | -- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
package CYCLONEIII_COMPONENTS is
--
-- cycloneiii_ff
--
component cycloneiii_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--
-- cycloneiii_ram_block
--
component cycloneiii_ram_block
generic
(
operation_mode : string := "single_port";
mixed_port_feed_through_mode : string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name : string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout : string := "none";
data_interleave_width_in_bits : integer := 1;
data_interleave_offset_in_bits : integer := 1;
port_a_logical_ram_depth : integer := 0;
port_a_logical_ram_width : integer := 0;
port_a_address_clear : string := "none";
port_a_data_out_clock : string := "none";
port_a_data_out_clear : string := "none";
port_a_first_address : integer := 0;
port_a_last_address : integer := 0;
port_a_first_bit_number : integer := 0;
port_a_data_width : integer := 1;
port_a_data_in_clock : string := "clock0";
port_a_address_clock : string := "clock0";
port_a_write_enable_clock : string := "clock0";
port_a_read_enable_clock : string := "clock0";
port_a_byte_enable_clock : string := "clock0";
port_b_logical_ram_depth : integer := 0;
port_b_logical_ram_width : integer := 0;
port_b_data_in_clock : string := "clock1";
port_b_address_clock : string := "clock1";
port_b_address_clear : string := "none";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_data_out_clock : string := "none";
port_b_data_out_clear : string := "none";
port_b_first_address : integer := 0;
port_b_last_address : integer := 0;
port_b_first_bit_number : integer := 0;
port_b_data_width : integer := 1;
port_b_byte_enable_clock : string := "clock1";
port_a_address_width : integer := 1;
port_b_address_width : integer := 1;
port_a_byte_enable_mask_width : integer := 1;
port_b_byte_enable_mask_width : integer := 1;
power_up_uninitialized : string := "false";
port_a_byte_size : integer := 0;
port_b_byte_size : integer := 0;
safe_write : string := "err_on_2clk";
init_file_restructured : string := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
-- REMStratix IV -- REMArria II GX -- REMHardCopy III clock_duty_cycle_dependence : STRING := "Auto";
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
port
(
portawe : in std_logic := '0';
portare : in std_logic := '1';
portabyteenamasks : in std_logic_vector (port_a_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbbyteenamasks : in std_logic_vector (port_b_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbre : in std_logic := '1';
portbwe : in std_logic := '0';
clr0 : in std_logic := '0';
clr1 : in std_logic := '0';
clk0 : in std_logic := '0';
clk1 : in std_logic := '0';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
ena2 : in std_logic := '1';
ena3 : in std_logic := '1';
portadatain : in std_logic_vector (port_a_data_width - 1 DOWNTO 0) := (others => '0');
portbdatain : in std_logic_vector (port_b_data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : in std_logic_vector (port_a_address_width - 1 DOWNTO 0) := (others => '0');
portbaddr : in std_logic_vector (port_b_address_width - 1 DOWNTO 0) := (others => '0');
portaaddrstall : in std_logic := '0';
portbaddrstall : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
portadataout : out std_logic_vector (port_a_data_width - 1 DOWNTO 0);
portbdataout : out std_logic_vector (port_b_data_width - 1 DOWNTO 0)
);
end component;
--
-- CYCLONEIII_LCELL_COMB
--
component cycloneiii_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
end component;
--
-- CYCLONEIII_CLKCTRL
--
component cycloneiii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
--
-- CYCLONEIII_ROUTING_WIRE
--
component cycloneiii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
end component;
--
-- CYCLONEIII_PLL
--
COMPONENT cycloneiii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
lpm_type : string := "cycloneiii_pll";
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
--REM_MF -- VITAL generics
--REM_MF XOn : Boolean := DefGlitchXOn;
--REM_MF MsgOn : Boolean := DefGlitchMsgOn;
--REM_MF MsgOnChecks : Boolean := DefMsgOnChecks;
--REM_MF XOnChecks : Boolean := DefXOnChecks;
--REM_MF TimingChecksOn : Boolean := true;
--REM_MF InstancePath : STRING := "*";
--REM_MF tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
--REM_MF tipd_ena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_pfdena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_areset : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_fbin : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scanclk : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scandata : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_configupdate : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
--REM_MF tipd_phasestep : VitalDelayType01 := DefPropDelay01;
--REM_MF tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT (
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- cycloneiii_mac_mult
--
component cycloneiii_mac_mult
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
end component;
--
-- cycloneiii_mac_out
--
component cycloneiii_mac_out
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
end component;
--
-- cycloneiii_termination Model
--
COMPONENT cycloneiii_termination
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END COMPONENT;
--
-- CYCLONEIII_IO_IBUF
--
COMPONENT cycloneiii_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_IO_OBUF
--
COMPONENT cycloneiii_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_DDIO_OE
--
COMPONENT cycloneiii_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- CYCLONEIII_DDIO_OUT
--
COMPONENT cycloneiii_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiii_pseudo_diff_out
--
COMPONENT cycloneiii_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_IO_PAD
--
component cycloneiii_io_pad
generic (
lpm_type : STRING := "cycloneiii_io_pad"
);
PORT (
padin : in std_logic := '1';
padout: out std_logic
);
end component;
--
--
-- CYCLONEIII_RUBLOCK
--
--
component cycloneiii_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type: string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end component;
--
--
-- CYCLONEIII_APFCONTROLLER
--
--
component cycloneiii_apfcontroller
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic; --REM_TARPON
nceout : out std_logic
);
end component;
--
-- CYCLONEIII_JTAG
--
component cycloneiii_jtag
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
--REM_CYCyclone III ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end component;
--
--
-- CYCLONEIII_CRCBLOCK
--
--
component cycloneiii_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end component;
--
--
-- CYCLONEIII_OSCILLATOR
--
--
component cycloneiii_oscillator
generic
(
lpm_type: string := "cycloneiii_oscillator"
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end component;
end cycloneiii_components;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-kc705/ahbrom.vhd | 18 | 8961 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800015";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A033";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539AE1B";
when 16#00069# => romdata <= X"8410A260";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800005";
when 16#00074# => romdata <= X"03200000";
when 16#00075# => romdata <= X"0539A81B";
when 16#00076# => romdata <= X"8410A260";
when 16#00077# => romdata <= X"C4204000";
when 16#00078# => romdata <= X"05000080";
when 16#00079# => romdata <= X"82100000";
when 16#0007A# => romdata <= X"80A0E000";
when 16#0007B# => romdata <= X"02800005";
when 16#0007C# => romdata <= X"01000000";
when 16#0007D# => romdata <= X"82004002";
when 16#0007E# => romdata <= X"10BFFFFC";
when 16#0007F# => romdata <= X"8620E001";
when 16#00080# => romdata <= X"3D1003FF";
when 16#00081# => romdata <= X"BC17A3E0";
when 16#00082# => romdata <= X"BC278001";
when 16#00083# => romdata <= X"9C27A060";
when 16#00084# => romdata <= X"03100000";
when 16#00085# => romdata <= X"81C04000";
when 16#00086# => romdata <= X"01000000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-asic/leon3mp.vhd | 1 | 18140 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
library techmap;
use techmap.gencomp.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
scantest : integer := CFG_SCAN
);
port (
resetn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
clk : in std_ulogic;
lock : out std_ulogic;
errorn : inout std_ulogic;
wdogn : inout std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data / scanout
dsurx : in std_ulogic; -- DSU rx data / scanin
dsuen : in std_ulogic;
dsubre : in std_ulogic; -- DSU break / scanen
dsuact : out std_ulogic; -- DSU active / NT
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
i2c_scl : inout std_ulogic;
i2c_sda : inout std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector(1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdio : inout std_logic;
emdc : out std_ulogic;
testen : in std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic
);
end;
architecture rtl of leon3mp is
signal lresetn : std_ulogic;
signal lclksel : std_logic_vector (1 downto 0);
signal lclk : std_ulogic;
signal llock : std_ulogic;
signal lerrorn : std_ulogic;
signal laddress : std_logic_vector(27 downto 0);
signal ldatain : std_logic_vector(31 downto 0);
signal ldataout : std_logic_vector(31 downto 0);
signal ldataen : std_logic_vector(31 downto 0);
signal lcbin : std_logic_vector(7 downto 0);
signal lcbout : std_logic_vector(7 downto 0);
signal lcben : std_logic_vector(7 downto 0);
signal lsdclk : std_ulogic;
signal lsdcsn : std_logic_vector (1 downto 0);
signal lsdwen : std_ulogic;
signal lsdrasn : std_ulogic;
signal lsdcasn : std_ulogic;
signal lsddqm : std_logic_vector (3 downto 0);
signal ldsutx : std_ulogic;
signal ldsurx : std_ulogic;
signal ldsuen : std_ulogic;
signal ldsubre : std_ulogic;
signal ldsuact : std_ulogic;
signal ltxd1 : std_ulogic;
signal lrxd1 : std_ulogic;
signal ltxd2 : std_ulogic;
signal lrxd2 : std_ulogic;
signal lramsn : std_logic_vector (4 downto 0);
signal lramoen : std_logic_vector (4 downto 0);
signal lrwen : std_logic_vector (3 downto 0);
signal loen : std_ulogic;
signal lwriten : std_ulogic;
signal lread : std_ulogic;
signal liosn : std_ulogic;
signal lromsn : std_logic_vector (1 downto 0);
signal lbrdyn : std_ulogic;
signal lbexcn : std_ulogic;
signal lwdogn : std_ulogic;
signal lgpioin : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal lgpioout : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal lgpioen : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal li2c_sclout : std_ulogic;
signal li2c_sclen : std_ulogic;
signal li2c_sclin : std_ulogic;
signal li2c_sdaout : std_ulogic;
signal li2c_sdaen : std_ulogic;
signal li2c_sdain : std_ulogic;
signal lspi_miso : std_ulogic;
signal lspi_mosi : std_ulogic;
signal lspi_sck : std_ulogic;
signal lspi_slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lprom32 : std_ulogic;
signal lspw_clksel : std_logic_vector (1 downto 0);
signal lspw_clk : std_ulogic;
signal lspw_rxd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_rxs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_txd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_txs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lgtx_clk : std_ulogic;
signal lerx_clk : std_ulogic;
signal lerxd : std_logic_vector(7 downto 0);
signal lerx_dv : std_ulogic;
signal letx_clk : std_ulogic;
signal letxd : std_logic_vector(7 downto 0);
signal letx_en : std_ulogic;
signal letx_er : std_ulogic;
signal lerx_er : std_ulogic;
signal lerx_col : std_ulogic;
signal lerx_crs : std_ulogic;
signal lemdint : std_ulogic;
signal lemdioin : std_logic;
signal lemdioout : std_logic;
signal lemdioen : std_logic;
signal lemdc : std_ulogic;
signal ltesten : std_ulogic;
signal ltrst : std_ulogic;
signal ltck : std_ulogic;
signal ltms : std_ulogic;
signal ltdi : std_ulogic;
signal ltdo : std_ulogic;
signal ltdoen : std_ulogic;
-- Use for ASIC
--constant padvoltage : integer := x33v;
--constant padlevel : integer := ttl;
-- Use for FPGA
constant padvoltage : integer := x18v;
constant padlevel : integer := cmos;
begin
-- TODO: Move PAD options to 'xconfig'
pads0 : entity work.pads
generic map (
padtech => CFG_PADTECH,
padlevel => padlevel,
padstrength => 4,
jtag_padfilter => pullup,
testen_padfilter => pulldown,
resetn_padfilter => schmitt,
clk_padfilter => 0,
spw_padstrength => 12,
jtag_padstrength => 4,
uart_padstrength => 4,
dsu_padstrength => 4,
padvoltage => padvoltage,
spw_input_type => CFG_SPW_INPUT,
oepol => padoen_polarity(CFG_PADTECH)
)
port map (
---------------------------
--to chip boundary
---------------------------
resetn => resetn ,
clksel => clksel ,
clk => clk ,
lock => lock ,
errorn => errorn ,
address => address ,
data => data ,
cb => cb ,
sdclk => sdclk ,
sdcsn => sdcsn ,
sdwen => sdwen ,
sdrasn => sdrasn ,
sdcasn => sdcasn ,
sddqm => sddqm ,
dsutx => dsutx ,
dsurx => dsurx ,
dsuen => dsuen ,
dsubre => dsubre ,
dsuact => dsuact ,
txd1 => txd1 ,
rxd1 => rxd1 ,
txd2 => txd2 ,
rxd2 => rxd2 ,
ramsn => ramsn ,
ramoen => ramoen ,
rwen => rwen ,
oen => oen ,
writen => writen ,
read => read ,
iosn => iosn ,
romsn => romsn ,
brdyn => brdyn ,
bexcn => bexcn ,
wdogn => wdogn ,
gpio => gpio ,
i2c_scl => i2c_scl ,
i2c_sda => i2c_sda ,
spi_miso => spi_miso ,
spi_mosi => spi_mosi ,
spi_sck => spi_sck ,
spi_slvsel => spi_slvsel,
prom32 => prom32 ,
spw_clksel => spw_clksel,
spw_clk => spw_clk ,
spw_rxd => spw_rxd ,
spw_rxs => spw_rxs ,
spw_txd => spw_txd ,
spw_txs => spw_txs ,
gtx_clk => gtx_clk ,
erx_clk => erx_clk ,
erxd => erxd ,
erx_dv => erx_dv ,
etx_clk => etx_clk ,
etxd => etxd ,
etx_en => etx_en ,
etx_er => etx_er ,
erx_er => erx_er ,
erx_col => erx_col ,
erx_crs => erx_crs ,
emdint => emdint ,
emdio => emdio ,
emdc => emdc ,
testen => testen ,
trst => trst ,
tck => tck ,
tms => tms ,
tdi => tdi ,
tdo => tdo ,
------------------------- ---
--to core
----------------------------
lresetn => lresetn ,
lclksel => lclksel ,
lclk => lclk ,
llock => llock ,
lerrorn => lerrorn ,
laddress => laddress ,
ldatain => ldatain ,
ldataout => ldataout ,
ldataen => ldataen ,
lcbin => lcbin ,
lcbout => lcbout ,
lcben => lcben ,
lsdclk => lsdclk ,
lsdcsn => lsdcsn ,
lsdwen => lsdwen ,
lsdrasn => lsdrasn ,
lsdcasn => lsdcasn ,
lsddqm => lsddqm ,
ldsutx => ldsutx ,
ldsurx => ldsurx ,
ldsuen => ldsuen ,
ldsubre => ldsubre ,
ldsuact => ldsuact ,
ltxd1 => ltxd1 ,
lrxd1 => lrxd1 ,
ltxd2 => ltxd2 ,
lrxd2 => lrxd2 ,
lramsn => lramsn ,
lramoen => lramoen ,
lrwen => lrwen ,
loen => loen ,
lwriten => lwriten ,
lread => lread ,
liosn => liosn ,
lromsn => lromsn ,
lbrdyn => lbrdyn ,
lbexcn => lbexcn ,
lwdogn => lwdogn ,
lgpioin => lgpioin ,
lgpioout => lgpioout ,
lgpioen => lgpioen ,
li2c_sclout => li2c_sclout,
li2c_sclen => li2c_sclen ,
li2c_sclin => li2c_sclin ,
li2c_sdaout => li2c_sdaout,
li2c_sdaen => li2c_sdaen ,
li2c_sdain => li2c_sdain ,
lspi_miso => lspi_miso ,
lspi_mosi => lspi_mosi ,
lspi_sck => lspi_sck ,
lspi_slvsel => lspi_slvsel,
lprom32 => lprom32 ,
lspw_clksel => lspw_clksel,
lspw_clk => lspw_clk ,
lspw_rxd => lspw_rxd ,
lspw_rxs => lspw_rxs ,
lspw_txd => lspw_txd ,
lspw_txs => lspw_txs ,
lgtx_clk => lgtx_clk ,
lerx_clk => lerx_clk ,
lerxd => lerxd ,
lerx_dv => lerx_dv ,
letx_clk => letx_clk ,
letxd => letxd ,
letx_en => letx_en ,
letx_er => letx_er ,
lerx_er => lerx_er ,
lerx_col => lerx_col ,
lerx_crs => lerx_crs ,
lemdint => lemdint ,
lemdioin => lemdioin ,
lemdioout => lemdioout ,
lemdioen => lemdioen ,
lemdc => lemdc ,
ltesten => ltesten ,
ltrst => ltrst ,
ltck => ltck ,
ltms => ltms ,
ltdi => ltdi ,
ltdo => ltdo ,
ltdoen => ltdoen
);
-- ASIC Core
core0 : entity work.core
generic map (
fabtech => CFG_FABTECH,
memtech => CFG_MEMTECH,
padtech => CFG_PADTECH,
clktech => CFG_CLKTECH,
disas => CFG_DISAS,
dbguart => CFG_DUART,
pclow => CFG_PCLOW,
scantest => CFG_SCAN,
bscanen => CFG_BOUNDSCAN_EN,
oepol => padoen_polarity(CFG_PADTECH)
)
port map (
----------------------------
-- ASIC Ports/Pads
----------------------------
resetn => lresetn ,
clksel => lclksel ,
clk => lclk ,
lock => llock ,
errorn => lerrorn ,
address => laddress ,
datain => ldatain ,
dataout => ldataout ,
dataen => ldataen ,
cbin => lcbin ,
cbout => lcbout ,
cben => lcben ,
sdclk => lsdclk ,
sdcsn => lsdcsn ,
sdwen => lsdwen ,
sdrasn => lsdrasn ,
sdcasn => lsdcasn ,
sddqm => lsddqm ,
dsutx => ldsutx ,
dsurx => ldsurx ,
dsuen => ldsuen ,
dsubre => ldsubre ,
dsuact => ldsuact ,
txd1 => ltxd1 ,
rxd1 => lrxd1 ,
txd2 => ltxd2 ,
rxd2 => lrxd2 ,
ramsn => lramsn ,
ramoen => lramoen ,
rwen => lrwen ,
oen => loen ,
writen => lwriten ,
read => lread ,
iosn => liosn ,
romsn => lromsn ,
brdyn => lbrdyn ,
bexcn => lbexcn ,
wdogn => lwdogn ,
gpioin => lgpioin ,
gpioout => lgpioout ,
gpioen => lgpioen ,
i2c_sclout => li2c_sclout,
i2c_sclen => li2c_sclen ,
i2c_sclin => li2c_sclin ,
i2c_sdaout => li2c_sdaout,
i2c_sdaen => li2c_sdaen ,
i2c_sdain => li2c_sdain ,
spi_miso => lspi_miso ,
spi_mosi => lspi_mosi ,
spi_sck => lspi_sck ,
spi_slvsel => lspi_slvsel,
prom32 => lprom32 ,
spw_clksel => lspw_clksel,
spw_clk => lspw_clk ,
spw_rxd => lspw_rxd ,
spw_rxs => lspw_rxs ,
spw_txd => lspw_txd ,
spw_txs => lspw_txs ,
gtx_clk => lgtx_clk ,
erx_clk => lerx_clk ,
erxd => lerxd ,
erx_dv => lerx_dv ,
etx_clk => letx_clk ,
etxd => letxd ,
etx_en => letx_en ,
etx_er => letx_er ,
erx_er => lerx_er ,
erx_col => lerx_col ,
erx_crs => lerx_crs ,
emdint => lemdint ,
emdioin => lemdioin ,
emdioout => lemdioout ,
emdioen => lemdioen ,
emdc => lemdc ,
testen => ltesten ,
trst => ltrst ,
tck => ltck ,
tms => ltms ,
tdi => ltdi ,
tdo => ltdo ,
tdoen => ltdoen ,
----------------------------
-- BSCAN
----------------------------
chain_tck => OPEN ,
chain_tckn => OPEN ,
chain_tdi => OPEN ,
chain_tdo => '0',
bsshft => OPEN ,
bscapt => OPEN ,
bsupdi => OPEN ,
bsupdo => OPEN ,
bsdrive => OPEN ,
bshighz => OPEN
);
-- BSCAN
-- TODO: ADD BSCAN
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/unisim/tap_unisim.vhd | 1 | 24308 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_xilinx
-- File: tap_xilinx.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: Xilinx TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex_tap is
component BSCAN_VIRTEX
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX
port map (
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2; tapo_capt <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex2_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex2_tap is
component BSCAN_VIRTEX2
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX2
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_SPARTAN3;
-- pragma translate_on
entity spartan3_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan3_tap is
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_SPARTAN3
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX4;
-- pragma translate_on
entity virtex4_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex4_tap is
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX5;
-- pragma translate_on
entity virtex5_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex5_tap is
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex6_tap is
component BSCAN_VIRTEX6
generic (
DISABLE_JTAG : boolean := FALSE;
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity spartan6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan6_tap is
component BSCAN_SPARTAN6
generic (
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity kintex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of kintex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity artix7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of artix7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3/cpu_disasx.vhd | 1 | 2451 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: cpu_disasx
-- File: cpu_disasx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.cpu_disas;
-- pragma translate_on
entity cpu_disasx is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of cpu_disasx is
component cpu_disas
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end component;
begin
u0 : cpu_disas
port map (clk, rstn, dummy, inst, pc, result, index, wreg, annul, holdn, pv, trap, disas);
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/memctrl/srctrl.vhd | 1 | 16113 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: srctrl
-- File: srctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Marko Isomaki - Gaisler Research
-- Description: 32-bit SRAM memory controller with read-modify-write
-- Supports also 64-bit AHB read/write accesses
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity srctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0; -- read-modify-write enable
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of srctrl is
constant VERSION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SRCTRL, 0, VERSION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ramaddr, '1', '1', rammask),
6 => ahb_membar(ioaddr, '0', '0', iomask),
others => zero32);
type srcycletype is (idle, read1, read2, write1, write2, write3, rmw1, rmw2, rmw3);
type prom8cycletype is (idle, read1, read2);
function byteswap (rdata, wdata : std_logic_vector(31 downto 0); addr, size : std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector(31 downto 0);
variable a : std_logic_vector(1 downto 0);
begin
tmp := rdata; a := addr(1 downto 0);
if size(0) = '0' then
case a is
when "00" => tmp(31 downto 24) := wdata(31 downto 24);
when "01" => tmp(23 downto 16) := wdata(23 downto 16);
when "10" => tmp(15 downto 8) := wdata(15 downto 8);
when others => tmp(7 downto 0) := wdata(7 downto 0);
end case;
else
if addr(1) = '0' then tmp(31 downto 16) := wdata(31 downto 16);
else tmp(15 downto 0) := wdata(15 downto 0); end if;
end if;
return(tmp);
end;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 2);
bdrive : std_ulogic;
nbdrive : std_ulogic;
srstate : srcycletype;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(63 downto 0);
hwdata : std_logic_vector(63 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
read : std_ulogic;
oen : std_ulogic;
ramsn : std_ulogic;
romsn : std_ulogic;
vramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
vromsn : std_logic_vector(1 downto 0);
writen : std_ulogic;
wen : std_logic_vector(3 downto 0);
mben : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
iosn : std_ulogic;
-- 8-bit prom access
pr8state : prom8cycletype;
data8 : std_logic_vector(23 downto 0);
ready8 : std_ulogic;
bwidth : std_logic_vector(1 downto 0);
end record;
signal r, ri : reg_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sri, rbdrive)
variable v : reg_type; -- local variables for registers
variable dqm : std_logic_vector(3 downto 0);
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable roms : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hrdata : std_logic_vector(63 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable vramws, vromws, viows : std_logic_vector(3 downto 0);
-- 8-bit prom access
variable romsn : std_ulogic;
variable bdrive : std_ulogic;
variable oen : std_ulogic;
variable writen : std_ulogic;
variable hready : std_ulogic;
variable ws : std_logic_vector(3 downto 0);
variable prom8sel : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable sbdrive : std_ulogic;
begin
-- Variable default settings to avoid latches
v := r; v.hresp := HRESP_OKAY; v.hrdata(31 downto 0) := sri.data;
hrdata := r.hrdata;
vramws := conv_std_logic_vector(ramws, 4); vbdrive := rbdrive;
vromws := conv_std_logic_vector(romws, 4);
viows := conv_std_logic_vector(iows, 4);
v.bwidth := sri.bwidth;
if (prom8en = 1) and (r.bwidth = "00") then prom8sel := '1';
else prom8sel := '0'; end if;
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans; v.hburst := ahbsi.hburst;
v.hsel := '1'; v.hmbsel := ahbsi.hmbsel(0 to 2);
v.haddr := ahbsi.haddr; v.hready := '0';
else
v.hsel := '0';
end if;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
end if;
-- chip-select decoding
adec := haddr(banksz+14 downto banksz+13);
rams := '0' & decode(adec);
case srbanks is
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others => null;
end case;
roms := haddr(romasel) & not haddr(romasel);
-- generate write strobes
if rmw = 1 then dqm := "0000"; else
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "1110";
when "01" => dqm := "1101";
when "10" => dqm := "1011";
when others => dqm := "0111";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "1100"; else dqm := "0011"; end if;
when others => dqm := "0000";
end case;
end if;
-- main FSM
case r.srstate is
when idle =>
if (v.hsel = '1') and not
(((v.ramsn or r.romsn) = '0') or ((v.romsn or r.ramsn) = '0')) and not
((v.hmbsel(0) and not hwrite and prom8sel) = '1' and prom8en = 1)
then
v.hready := '0';
v.ramsn := not v.hmbsel(1); v.romsn := not v.hmbsel(0);
v.iosn := not v.hmbsel(2);
v.read := not hwrite;
if hwrite = '1' then
if (rmw = 1) and (hsize(1) = '0') and (v.hmbsel(1) = '1') then
v.srstate := rmw1; v.read := '1';
else v.srstate := write1; end if;
elsif ahbsi.htrans = "10" then v.srstate := read1;
else v.srstate := read2; end if;
v.oen := not v.read;
else
v.ramsn := '1'; v.romsn := '1'; v.bdrive := '1'; v.oen := '1';
v.iosn := '1';
end if;
if v.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
when read1 =>
v.srstate := read2;
v.hrdata(63 downto 32) := r.hrdata(31 downto 0);
when read2 =>
v.ws := r.ws -1; v.oen := '0';
if r.ws = "0000" then
if (r.size /= "11") or (r.haddr(2) = '1') or (AHBDW = 32) then
v.srstate := idle; v.hready := '1'; v.haddr := ahbsi.haddr;
v.ramsn := not (ahbsi.hmbsel(1) and ahbsi.htrans(1));
v.romsn := not (ahbsi.hmbsel(0) and ahbsi.htrans(1));
v.oen := not (ahbsi.hsel(hindex) and ahbsi.htrans(1) and not ahbsi.hwrite);
else
v.srstate := read1; v.haddr(2) := '1';
if v.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
end if;
end if;
when write1 =>
if r.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
v.srstate := write2; v.bdrive := '0'; v.wen := dqm; v.writen := '0';
v.hwdata(31 downto 0) := ahbsi.hwdata(31 downto 0);
if not ((r.size = "11") and (r.haddr(2) = '1')) then
v.hwdata(63 downto 32) := ahbsi.hwdata(63 mod AHBDW downto 32 mod AHBDW);
end if;
when write2 =>
if r.ws = "0000" then
if (r.size /= "11") or (r.haddr(2) = '1') or (AHBDW = 32) then
v.srstate := idle; v.bdrive := '1'; v.hready := '1';
else
v.srstate := write3;
end if;
v.wen := "1111"; v.writen := '1';
end if;
v.ws := r.ws -1;
when write3 =>
v.haddr(2) := '1'; v.hwdata(63 downto 32) := r.hwdata(31 downto 0);
v.srstate := write1;
when rmw1 =>
if (rmw = 1) then v.oen := '0';
v.srstate := rmw2;
v.hwdata(31 downto 0) := ahbsi.hwdata(31 downto 0);
v.hwdata(63 downto 32) := ahbsi.hwdata(63 mod AHBDW downto 32 mod AHBDW);
end if;
when rmw2 =>
if (rmw = 1) then
v.ws := r.ws -1;
if r.ws = "0000" then v.oen := '1'; v.srstate := rmw3; end if;
end if;
when rmw3 =>
if (rmw = 1) then
v.hwdata(63 downto 32) := byteswap(r.hrdata(31 downto 0), r.hwdata(63 downto 32), r.haddr, r.size);
v.srstate := write2; v.bdrive := '0'; v.wen := dqm; v.writen := '0';
end if;
if r.romsn = '0' then v.ws := vromws; else v.ws := vramws; end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- 8-bit PROM access FSM
if prom8en = 1 then
hready := '0'; ws := v.ws; v.ready8 := '0';
bdrive := '1'; oen := '1'; writen := '1'; romsn := '1';
if r.ready8 = '1' then
v.data8 := r.data8(15 downto 0) & r.hrdata(31 downto 24);
case r.size is
when "00" => hrdata(31 downto 0) := r.hrdata(31 downto 24) &
r.hrdata(31 downto 24) & r.hrdata(31 downto 24) & r.hrdata(31 downto 24);
when "01" => hrdata(31 downto 0) := r.data8(7 downto 0) & r.hrdata(31 downto 24) &
r.data8(7 downto 0) & r.hrdata(31 downto 24);
when others => hrdata(31 downto 0) := r.data8 & r.hrdata(31 downto 24);
end case;
end if;
case r.pr8state is
when idle =>
if ( (v.hsel and v.hmbsel(0) and not hwrite and prom8sel) = '1')
then
romsn := '0'; v.pr8state := read1; oen := '0';
end if;
when read1 =>
oen := '0'; romsn := '0'; v.pr8state := read2; ws := vromws;
when read2 =>
oen := '0'; ws := r.ws - 1; romsn := '0';
if r.ws = "0000" then
v.haddr(1 downto 0) := r.haddr(1 downto 0) + 1;
if (r.size = "00") or ((r.size = "01") and (r.haddr(0) = '1'))
or r.haddr(1 downto 0) = "11"
then
hready := '1'; v.pr8state := idle; oen := '1';
else
v.pr8state := read1;
end if;
v.ready8 := '1';
end if;
when others =>
v.pr8state := idle;
end case;
v.romsn := v.romsn and romsn; v.bdrive := v.bdrive and bdrive;
v.oen := v.oen and oen; v.writen := v.writen and writen;
v.hready := v.hready or hready; v.ws := ws;
end if;
if (v.oen or v.ramsn) = '0' then v.ramoen := not rams;
else v.ramoen := (others => '1'); end if;
if v.romsn = '0' then v.vromsn := not roms;
else v.vromsn := (others => '1'); end if;
if v.ramsn = '0' then v.vramsn := not rams;
else v.vramsn := (others => '1'); end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wen; end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then sbdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else sbdrive := r.bdrive; vbdrive := (others => v.bdrive); end if;
if (r.size /= "11") or (AHBDW = 32) then hrdata(63 downto 32) := hrdata(31 downto 0); end if;
-- reset
if rst = '0' then
v.srstate := idle; v.hsel := '0'; v.writen := '1';
v.wen := (others => '1'); v.hready := '1'; v.read := '1';
v.ws := (others => '0');
if prom8en = 1 then v.pr8state := idle; end if;
end if;
ribdrive <= vbdrive;
ri <= v;
sro.address <= r.haddr;
sro.bdrive <= (others => sbdrive);
sro.vbdrive <= rbdrive;
sro.ramsn <= "111" & r.vramsn;
sro.ramoen <= "111" & r.ramoen;
sro.romsn <= "111111" & r.vromsn;
sro.iosn <= r.iosn;
sro.wrn <= r.wen;
sro.oen <= r.oen;
sro.read <= r.read;
sro.data <= r.hwdata(63 downto 32);
sro.writen <= r.writen;
sro.ramn <= r.ramsn;
sro.romn <= r.romsn;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
end process;
sdo.sdcsn <= "11"; sdo.sdcke <= "11"; sdo.sdwen <= '1'; sdo.rasn <= '1';
sdo.casn <= '1'; sdo.dqm <= (others => '1'); sdo.address <= (others => '0');
sdo.data <= (others => '0'); sdo.conf <= (others => '0'); sdo.odt <= (others => '0');
sdo.cal_pll <= (others => '0'); sdo.cal_inc <= (others => '0');
sdo.cal_en <= (others => '0'); sdo.sdck <= (others => '0');
sdo.ba <= (others => '0'); sdo.cb <= (others => '0');
sdo.vbdrive <= (others => '0'); sdo.qdrive <= '0'; sdo.bdrive <= '0';
sdo.oct <= '0';
sdo.ce <= '0'; sdo.moben <= '0'; sdo.cal_rst <= '0';
sdo.xsdcsn <= (others => '0'); sdo.vcbdrive <= (others => '0');
sdo.cbdqm <= (others => '0'); sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0'); sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0'); sdo.regwrite <= (others => '0');
sro.mben <= r.mben;
sro.sdram_en <= '0';
sro.rs_edac_en <= '0';
sro.ce <= '0';
sro.sddata <= (others => '0');
sro.svbdrive <= (others => '0');
sro.sa <= (others => '0');
sro.cb <= (others => '0');
sro.scb <= (others => '0');
sro.vcdrive <= (others => '0');
sro.svcdrive <= (others => '0');
sro.scb <= (others => '0');
regs : process(clk,rst)
begin
if rising_edge(clk) then r <= ri; rbdrive <= ribdrive; end if;
if rst = '0' then
r.ramsn <= '1';
r.romsn <= '1'; r.oen <= '1';
r.bdrive <= '1'; r.nbdrive <= '0';
r.vramsn <= (others => '1'); r.vromsn <= (others => '1');
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("srctrl" & tost(hindex) &
": 32-bit PROM/SRAM controller rev " & tost(VERSION));
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/sim/sram16.vhd | 1 | 2363 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram16
-- File: sram16.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 16-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram16 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(15 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram16 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+1, abits, tacc, fname, clear)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index, abits, tacc, fname, clear)
port map (a, d(15 downto 8), cex(1), we, oe);
end sim;
-- pragma translate_on
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep2sgx90-av/prgmem.vhd | 3 | 5738 | ------------------------------------------------------
-- Program-Memory
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use std.textio.all;
-- Important NOTE:
-- ---------------
--
-- The ROM_BITS generic controls the size of the internal
-- ROM. The ROM is located in upper part of program memory
-- and is initialized by the given (intel-).hex-file.
-- If there's no such file, everything is filled up with
-- 'null'. Everything before the ROM is always nulled.
-- If you don't want a System-ROM, just set ROM_BITS to 0.
entity prgmem is
generic (
INIT_FILE_NAME : string; -- => init file for rom
PRGM_MEM : positive := 12; -- => 4k word
MEM_WIDTH : positive := 32
);
port (
-- common signals
clk : in std_logic; -- normal system clock
reset : in std_logic;
-- access (r)
addr : in std_logic_vector(PRGM_MEM-1 downto 0);
data : out std_logic_vector(MEM_WIDTH-1 downto 0)
);
end entity;
architecture Behavioral of prgmem is
-- some constants
constant MEM_DEPTH : positive := 2**PRGM_MEM;
-- constant MEM_WIDTH : positive := ;
-- constant ROM_DEPTH : positive := 2**ROM_BITS ;
-- constant ROM_POS : integer := rom_start(PRGM_MEM, ROM_BITS);
-- declare memory type
type MEM_TYPE is array(0 to MEM_DEPTH - 1) of std_logic_vector(MEM_WIDTH-1 downto 0);
type BYTE_STRING is array(1 downto 0) of character;
type WORD_STRING is array(3 downto 0) of character;
function CHAR_TO_INT ( char : in character) return integer is
variable r : integer := 0;
begin
case char is
when 'A' => r := 10;
when 'B' => r := 11;
when 'C' => r := 12;
when 'D' => r := 13;
when 'E' => r := 14;
when 'F' => r := 15;
when 'a' => r := 10;
when 'b' => r := 11;
when 'c' => r := 12;
when 'd' => r := 13;
when 'e' => r := 14;
when 'f' => r := 15;
when '1' => r := 1;
when '2' => r := 2;
when '3' => r := 3;
when '4' => r := 4;
when '5' => r := 5;
when '6' => r := 6;
when '7' => r := 7;
when '8' => r := 8;
when '9' => r := 9;
when others => null;
end case;
return r;
end function;
function BYTE_TO_INT ( bytechars : in string(1 to 2)) return integer is
begin
return CHAR_TO_INT(bytechars(1))*16+CHAR_TO_INT(bytechars(2));
end function;
function WORD_TO_INT ( wordchars : in string(1 to 4)) return integer is
begin
return BYTE_TO_INT(wordchars(1) & wordchars(2))*256+BYTE_TO_INT(wordchars(3) & wordchars(4));
end function;
-- function for loading the init values
impure function InitRamFromFile (file_name : in string) return MEM_TYPE is
FILE init_file : text;-- is in file_name;
variable rline : line;
variable memory : MEM_TYPE;
-- variable offs : integer := 0;
variable count : integer;
variable linemode : integer;
variable addr : integer;
variable tmp_chr : character;
variable tmp_byte : string(1 to 2);--BYTE_STRING;
variable tmp_word : string(1 to 4);--WORD_STRING;
variable tmp_addr : integer;
variable tmp_v : std_logic_vector(MEM_WIDTH-1 downto 0);
begin
-- first just null everything
for i in 0 to MEM_DEPTH-1 loop
memory(i) := (others => '0');
end loop;
file_open(init_file, file_name, READ_MODE);
-- read rom file
while (not endfile(init_file)) loop
readline (init_file, rline);
exit when endfile (init_file);
read (rline, tmp_chr);
if tmp_chr = ':' then --beginning of line is correct
--how much to read
read (rline, tmp_byte);
count := BYTE_TO_INT(tmp_byte);
--addr
read (rline, tmp_word);
addr := WORD_TO_INT(tmp_word);
--line mode
read (rline, tmp_byte);
linemode := BYTE_TO_INT(tmp_byte);
if linemode = 0 then
-- loop every PROGRAM-WORD
for i in 0 to (count/(MEM_WIDTH/8) - 1) loop
tmp_v := (others=>'0');
-- loop for every BYTE IN PROGRAM-WORD
for j in 0 to MEM_WIDTH/8-1 loop
read (rline, tmp_byte);
tmp_v((j+1)*8-1 downto j*8) := std_logic_vector(to_unsigned(BYTE_TO_INT(tmp_byte),8));
end loop;
-- store in memory
memory(addr/(MEM_WIDTH/8) + i) := tmp_v;
end loop;
end if;
end if;
end loop;
file_close(init_file);
return memory;
end function;
-- define memory and initialize it
signal memory : MEM_TYPE := InitRamFromFile(INIT_FILE_NAME);
signal mem_addr : std_logic_vector(PRGM_MEM-1 downto 0);
signal mem_doa : std_logic_vector(15 downto 0);
signal mem_we : std_logic;
-- output register
signal reg_cmd_out : std_logic_vector(MEM_WIDTH-1 downto 0);
signal reg_const_out : std_logic_vector(MEM_WIDTH-1 downto 0);
signal reg_lpmspm : std_logic_vector(MEM_WIDTH-1 downto 0);
begin
mem_addr <= addr;
---------------------------------------------------
-- infering the block ram
process(clk)
begin
if clk'event and clk = '1' then
data <= memory(to_integer(unsigned(addr)));
end if;
end process;
end architecture;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/bftLib/core_transform.vhdl | 1 | 3812 | --/////////////////////////////////////////////////////////////////////////
--// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
--//
--// XILINX CONFIDENTIAL PROPERTY
--// This document contains proprietary information which is
--// protected by copyright. All rights are reserved. This notice
--// refers to original work by Xilinx, Inc. which may be derivitive
--// of other work distributed under license of the authors. In the
--// case of derivitive work, nothing in this notice overrides the
--// original author's license agreeement. Where applicable, the
--// original license agreement is included in it's original
--// unmodified form immediately below this header.
--//
--// Xilinx, Inc.
--// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
--// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
--// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
--// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
--// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
--// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
--// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
--// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
--// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
--// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
--// AND FITNESS FOR A PARTICULAR PURPOSE.
--//
--/////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
entity coreTransform is
generic (
DATA_WIDTH : integer := 16
);
port (
clk : in std_logic;
x, xStep, u : in std_logic_vector (DATA_WIDTH-1 downto 0);
xOut, xOutStep : out std_logic_vector (DATA_WIDTH-1 downto 0)
);
--synthesis packing can change the resutls greatly
--setting up some attributes to force the mapping I want
--attribute register_duplication : string;
--attribute register_duplication of coreTransform : entity is "yes";
--attribute register_balancing : string;
--attribute register_balancing of coreTransform : entity is "yes";
----force a mapping to DSP48s
attribute use_dsp48 : string;
attribute use_dsp48 of coreTransform : entity is "yes";
----turn off resource sharing
----with resource sharing off this will map to two dsp48s. With it on, a dsp48 and some logic.
attribute resource_sharing : string;
attribute resource_sharing of coreTransform : entity is "no";
end entity coreTransform;
architecture aCT of coreTransform is
signal xReg, xStepReg, uReg : std_logic_vector (DATA_WIDTH-1 downto 0);
signal xOutReg, xOutStepReg, xOutRegTemp, xOutStepRegTemp: std_logic_vector (2*DATA_WIDTH -1 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
xStepReg <= xStep;
uReg <= u;
xReg <= x;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
xOutReg <= SXT(xReg, 2*DATA_WIDTH) + uReg*xStepReg;
xOutStepReg <= SXT(xReg, 2*DATA_WIDTH) - uReg*xStepReg;
end if;
end process;
-- xOut <= xOutReg(DATA_WIDTH-1 downto 0) xor xOutReg(2*DATA_WIDTH-1 downto DATA_WIDTH);
-- xOutStep <= xOutStepReg(DATA_WIDTH-1 downto 0) xor xOutStepReg(2*DATA_WIDTH-1 downto DATA_WIDTH);
xOut <= xOutReg(DATA_WIDTH-1 downto 0) xor xOutReg(2*DATA_WIDTH-1 downto DATA_WIDTH);
xOutStep <= xOutStepReg(DATA_WIDTH-1 downto 0) xor xOutStepReg(2*DATA_WIDTH-1 downto DATA_WIDTH);
end architecture aCT;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/inferred/mul_inferred.vhd | 1 | 4244 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gen_mul_61x61
-- File: mul_inferred.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Generic 61x61 multplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
entity gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of gen_mul_61x61 is
signal r1, r1in, r2, r2in : std_logic_vector(121 downto 0);
begin
comb : process(A, B, r1)
begin
-- pragma translate_off
if not (is_x(A) or is_x(B)) then
-- pragma translate_on
r1in <= std_logic_vector(unsigned(A) * unsigned(B));
-- pragma translate_off
end if;
-- pragma translate_on
r2in <= r1;
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if EN = '1' then
r1 <= r1in;
r2 <= r2in;
end if;
end if;
end process;
PRODUCT <= r2;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity gen_mult_pipe is
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1); -- '0': non-stallable; '1': stallable
port (
clk : in std_logic; -- register clock
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end ;
architecture simple of gen_mult_pipe is
subtype resw is std_logic_vector(A_width+B_width-1 downto 0);
type pipet is array (num_stages-1 downto 1) of resw;
signal p_i : pipet;
signal prod : resw;
begin
comb : process(A, B, TC)
begin
-- pragma translate_off
if notx(A) and notx(B) and notx(tc) then
-- pragma translate_on
if TC = '1' then
prod <= signed(A) * signed(B);
else
prod <= unsigned(A) * unsigned(B);
end if;
-- pragma translate_off
else
prod <= (others => 'X');
end if;
-- pragma translate_on
end process;
w2 : if num_stages = 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i(1) <= prod;
end if;
end if;
end process;
end generate;
w3 : if num_stages > 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i <= p_i(num_stages-2 downto 1) & prod;
end if;
end if;
end process;
end generate;
product <= p_i(num_stages-1);
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/eth/core/greth_pkg.vhd | 1 | 20055 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
package grethpkg is
--gigabit sync types
type data_sync_type is array (0 to 3) of std_logic_vector(31 downto 0);
type ctrl_sync_type is array (0 to 3) of std_logic_vector(1 downto 0);
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
--receiver constants
constant maxsizerx : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(1500, 16);
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
type ahb_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(4 downto 0);
write : std_ulogic;
data : std_logic_vector(31 downto 0);
waddress : std_logic_vector(4 downto 0);
end record;
type ahb_fifo_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type nchar_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(5 downto 0);
write : std_ulogic;
data : std_logic_vector(8 downto 0);
waddress : std_logic_vector(5 downto 0);
end record;
type nchar_fifo_out_type is record
data : std_logic_vector(8 downto 0);
end record;
type rmapbuf_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(7 downto 0);
write : std_ulogic;
data : std_logic_vector(7 downto 0);
waddress : std_logic_vector(7 downto 0);
end record;
type rmapbuf_out_type is record
data : std_logic_vector(7 downto 0);
end record;
type ahbc_mst_in_type is record
hgrant : std_ulogic; -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type ahbc_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_in_type is record
psel : std_ulogic; -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type gbit_host_tx_type is record
full_duplex : std_ulogic;
start : std_ulogic;
read_ack : std_ulogic;
data : std_logic_vector(31 downto 0);
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type gbit_rx_host_type is record
sync_start : std_ulogic;
done : std_ulogic;
write : std_logic_vector(3 downto 0);
dataout : data_sync_type;
byte_count : std_logic_vector(10 downto 0);
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
end record;
type gbit_host_rx_type is record
full_duplex : std_ulogic;
gbit : std_ulogic;
doneack : std_ulogic;
writeack : std_logic_vector(3 downto 0);
speed : std_ulogic;
writeok : std_logic_vector(3 downto 0);
rxenable : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_gtx_host_type is record
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
read : std_logic_vector(3 downto 0);
status : std_logic_vector(2 downto 0);
end record;
type gbit_host_gtx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
burstmode : std_ulogic;
txen : std_ulogic;
start_sync : std_ulogic;
readack : std_logic_vector(3 downto 0);
valid : std_logic_vector(3 downto 0);
data : data_sync_type;
len : std_logic_vector(10 downto 0);
end record;
type host_tx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
start : std_ulogic;
readack : std_ulogic;
speed : std_ulogic;
data : std_logic_vector(31 downto 0);
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
end record;
type tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type rx_host_type is record
dataout : std_logic_vector(31 downto 0);
start : std_ulogic;
done : std_ulogic;
write : std_ulogic;
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
lentype : std_logic_vector(15 downto 0);
mcasthash : std_logic_vector(5 downto 0);
end record;
type host_rx_type is record
writeack : std_ulogic;
doneack : std_ulogic;
speed : std_ulogic;
writeok : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_crs : std_ulogic;
rx_er : std_ulogic;
enable : std_ulogic;
end record;
component greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end component;
component greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end component;
component eth_rstgen is
generic(acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end component;
component greth_gbit_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in gbit_host_tx_type;
txo : out gbit_tx_host_type);
end component;
component greth_gbit_gtx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
gtxi : in gbit_host_gtx_type;
gtxo : out gbit_gtx_host_type
);
end component;
component greth_gbit_rx is
generic(
multicast : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in gbit_host_rx_type;
rxo : out gbit_rx_host_type);
end component;
component eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type);
end component;
component eth_edcl_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type
);
end component;
function mirror(din : in std_logic_vector) return std_logic_vector;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector;
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer;
function setburstlength(fifosize : in integer) return integer;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector;
end package;
package body grethpkg is
function mirror(din : in std_logic_vector)
return std_logic_vector is
variable do : std_logic_vector(din'range);
begin
for i in 0 to din'length-1 loop
do(din'high-i) := din(i+din'low);
end loop;
return do;
end function;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(16 downto 0);
variable vd2 : std_logic_vector(16 downto 0);
variable sum : std_logic_vector(16 downto 0);
begin
vd1 := '0' & d1; vd2 := '0' & d2;
sum := vd1 + vd2;
sum(15 downto 0) := sum(15 downto 0) + sum(16);
return sum(15 downto 0);
end function;
--16-bit one's complement adder for ip/tcp checksum detection
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(25 downto 0);
variable vd2 : std_logic_vector(25 downto 0);
variable sum : std_logic_vector(25 downto 0);
begin
vd1 := "0000000000" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic is
variable valid : std_ulogic;
begin
valid := '1';
if usesz = '1' then
if len > minpload then
if bcnt /= len then
valid := '0';
end if;
else
if bcnt /= minpload then
valid := '0';
end if;
end if;
end if;
return valid;
end function;
function setburstlength(fifosize : in integer) return integer is
begin
if fifosize <= 64 then
return fifosize/2;
else
return 32;
end if;
end function;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(17 downto 0);
variable vd2 : std_logic_vector(17 downto 0);
variable sum : std_logic_vector(17 downto 0);
begin
vd1 := "00" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
end package body;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-kc705/ddr_dummy.vhd | 8 | 5346 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2012 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Package: ddr_dummy
-- File:ddr_dummy.vhd
-- Author:Fredrik Ringhage - Gaisler Research
-- Description: Xilinx MIG wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUF;
-- pragma translate_on
library work;
entity ddr_dummy is
generic (
USE_MIG_INTERFACE_MODEL : boolean := false;
nCS_PER_RANK : integer := 1; -- # of unique CS outputs per rank
BANK_WIDTH : integer := 3; -- # of bank address
CKE_WIDTH : integer := 1; -- # of clock enable outputs
CS_WIDTH : integer := 1; -- # of chip select
DM_WIDTH : integer := 8; -- # of data mask
DQ_WIDTH : integer := 64; -- # of data bits
DQS_WIDTH : integer := 8; -- # of strobe pairs
ODT_WIDTH : integer := 1; -- # of ODT outputs
ROW_WIDTH : integer := 14 -- # of row/column address
);
port (
ddr_ck_p : out std_logic_vector(0 downto 0);
ddr_ck_n : out std_logic_vector(0 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_ras_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0)
);
end;
architecture rtl of ddr_dummy is
component OBUF generic (IOSTANDARD : string := "SSTL15");
port (O : out std_ulogic; I : in std_ulogic);
end component;
component IOBUF generic (IOSTANDARD : string := "SSTL15_T_DCI");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic);
end component;
component OBUFDS generic(IOSTANDARD : string := "DIFF_SSTL15");
port(O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
end component;
component IOBUFDS generic (IOSTANDARD : string := "DIFF_SSTL15");
port (O : out std_ulogic; IO, IOB : inout std_logic; I, T : in std_ulogic);
end component;
signal in_dq : std_logic_vector(DQ_WIDTH-1 downto 0);
signal in_dqs : std_logic_vector(DQS_WIDTH-1 downto 0);
begin
io_cas : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_cas_n, I => '0');
io_ras : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_ras_n, I => '0');
io_we : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_we_n, I => '0');
io_ck : OBUFDS generic map (IOSTANDARD => "DIFF_SSTL15")
port map (O => ddr_ck_p(0), OB => ddr_ck_n(0), I => '0');
io_addr_gen : for i in 0 to ROW_WIDTH-1 generate
begin
io_addr : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_addr(i), I => '0');
end generate io_addr_gen;
io_ba_gen : for i in 0 to BANK_WIDTH-1 generate
begin
io_addr : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_ba(i), I => '0');
end generate io_ba_gen;
io_cs_gen : for i in 0 to CS_WIDTH*nCS_PER_RANK-1 generate
begin
io_cs : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_cs_n(i), I => '0');
end generate io_cs_gen;
io_odt_gen : for i in 0 to ODT_WIDTH-1 generate
begin
io_odt : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_odt(i), I => '0');
end generate io_odt_gen;
io_dm_gen : for i in 0 to DM_WIDTH-1 generate
begin
io_dm : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_dm(i), I => '0');
end generate io_dm_gen;
io_cke_gen : for i in 0 to CKE_WIDTH-1 generate
begin
io_cke : OBUF generic map (IOSTANDARD => "SSTL15")
port map (O => ddr_cke(i), I => '0');
end generate io_cke_gen;
op_reset : OBUF generic map (IOSTANDARD => "LVCMOS15")
port map (O => ddr_reset_n, I => '1');
io_dq_gen : for i in 0 to DQ_WIDTH-1 generate
begin
io_dq : IOBUF generic map (IOSTANDARD => "SSTL15_T_DCI")
port map (O => in_dq(i), IO => ddr_dq(i), I => '0', T => '0');
end generate io_dq_gen;
io_dqs_gen : for i in 0 to DQS_WIDTH-1 generate
begin
io_dqs : IOBUFDS generic map (IOSTANDARD => "DIFF_SSTL15_T_DCI")
port map (O => in_dqs(i), IO => ddr_dqs(i), IOB => ddr_dqs_n(i), I => '0', T => '1');
end generate io_dqs_gen;
end architecture rtl; | gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/grlib/amba/dma2ahb_tp.vhd | 1 | 67479 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB_TestPackage (package declaration)
--
-- File name : dma2ahb_tp.vhd
--
-- Purpose : Interface package for AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : See DMA2AHB VHDL core
--
-- Library : {independent}
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 1.4 SH 1 Jul 2005 New package
-- 1.5 SH 1 Sep 2005 New library TOPNET
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.8 SH 10 Nov 2005 Updated DMA2AHB interface usage
-- 1.9 SH 4 Jan 2006 Burst routines added
-- Fault reporting priority and timing improved
-- 1.9.1 SH 12 Jan 2006 Correct DmaComp8
-- 1.9.2 SH ## ### #### Corrected compare to allow pull-up
-- Adjusted printouts
-- 1.9.3 JA 14 Dec 2007 Support for halfword and byte bursts
-- 1.9.4 MI 4 Aug 2008 Support for Lock
-- 1.9.5 SH 4 Mar 2011 Modifed burst accesses to mimic real hw
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.STDIO.all;
use GRLIB.DMA2AHB_Package.all;
use GRLIB.STDLIB.all;
package DMA2AHB_TestPackage is
-----------------------------------------------------------------------------
-- Vector of words
-----------------------------------------------------------------------------
type Data_Vector is array (Natural range <> ) of
Std_Logic_Vector(32-1 downto 0);
-----------------------------------------------------------------------------
-- Constants for comparison
-----------------------------------------------------------------------------
constant DontCare32: Std_Logic_Vector(31 downto 0) := (others => '-');
constant DontCare24: Std_Logic_Vector(23 downto 0) := (others => '-');
constant DontCare16: Std_Logic_Vector(15 downto 0) := (others => '-');
constant DontCare8: Std_Logic_Vector( 7 downto 0) := (others => '-');
----------------------------------------------------------------------------
-- Constant for calculating burst lengths
----------------------------------------------------------------------------
constant WordSize: integer := 32;
-----------------------------------------------------------------------------
-- Initialize AHB interface
-----------------------------------------------------------------------------
procedure DMAInit(
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
constant InstancePath: in String := "DMAInit";
constant ScreenOutput: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead16";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(15 downto 0);
variable RxData: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead8";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector( 7 downto 0);
variable RxData: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAReadBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMACompBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable CxData: in Data_Vector;
variable RxData: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
end package DMA2AHB_TestPackage;
package body DMA2AHB_TestPackage is
-----------------------------------------------------------------------------
-- Compare function handling '-'
-----------------------------------------------------------------------------
function Compare(O, C: in Std_Logic_Vector) return Boolean is
variable T: Std_Logic_Vector(O'Range) := C;
variable Result: Boolean;
begin
Result := True;
for i in O'Range loop
if not (To_X01(O(i))=T(i) or T(i)='-' or T(i)='U') then
Result := False;
end if;
end loop;
return Result;
end function Compare;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function Conv_Std_Logic_Vector(
constant i: Integer;
w: Integer)
return Std_Logic_Vector is
variable tmp: Std_Logic_Vector(w-1 downto 0);
begin
tmp := Std_Logic_Vector(To_UnSigned(i, w));
return(tmp);
end;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function Conv_Integer(
constant i: Std_Logic_Vector)
return Integer is
variable tmp: Integer;
begin
tmp := To_Integer(UnSigned(i));
return(tmp);
end;
-----------------------------------------------------------------------------
-- Synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure Synchronise(
signal Clock: in Std_ULogic;
constant Offset: in Time := 5 ns;
constant Enable: in Boolean := True) is
begin
if Enable then
wait until Clock = '1'; -- synchronise
if Offset > 0 ns then
wait for Offset; -- output offset delay
end if;
end if;
end procedure Synchronise;
-----------------------------------------------------------------------------
-- Initialize AHB interface
-----------------------------------------------------------------------------
procedure DMAInit(
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
constant InstancePath: in String := "DMAInit";
constant ScreenOutput: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Request <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '0';
dmai.Data <= (others => '0');
dmai.Size <= "10";
dmai.Lock <= '0';
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB initalised"));
WriteLine(Output, L);
end if;
end procedure DMAInit;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable L: Line;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Request <= '1';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '1';
dmai.Data <= Data;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
wait for 1 ns;
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
else
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Data <= Data;
loop
Synchronise(HCLK);
while dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR reponse "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
dmai.Lock <= '0';
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
dmai.Lock <= '0';
exit;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY/SPLIT reponse "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAWriteQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
begin
DMAWriteQuiet(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size, Lock);
if ScreenOutput and OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure DMAWrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Request <= '1';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '0';
dmai.Data <= (others => '0');
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
wait for 1 ns;
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
else
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
loop
Synchronise(HCLK);
while dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR reponse "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Data := (others => 'X');
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
Data := dmao.Data;
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
exit;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY/SPLIT reponse "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Temp, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size, Lock);
if ScreenOutput and OK then
Data := Temp;
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Data := (others => '-');
TP := False;
end if;
end procedure DMARead;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size, Lock);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
RxData := (others => '-');
elsif not Compare(Data, CxData) then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
Write (L, String'(" : expected: "));
HWrite(L, CxData);
Write (L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
RxData := Data;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
RxData := Data;
else
RxData := Data;
end if;
end procedure DMAComp;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWriteQuiet(Address, Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
end procedure DMAWriteQuiet16;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWrite(Address, Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
end procedure DMAWrite16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
if Address(1)='0' then
Data := Tmp(31 downto 16);
else
Data := Tmp(15 downto 0);
end if;
end procedure DMAQuiet16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead16";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMARead(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
if Address(1)='0' then
Data := Tmp(31 downto 16);
else
Data := Tmp(15 downto 0);
end if;
end procedure DMARead16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(15 downto 0);
variable RxData: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable TmpRx: Std_Logic_Vector(31 downto 0);
variable TmpCx: Std_Logic_Vector(31 downto 0);
begin
if Address(1)='0' then
TmpCx := CxData & "----------------";
else
TmpCx := "----------------" & CxData;
end if;
DMAComp(Address, TmpCx, TmpRx, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
if Address(1)='0' then
RxData := TmpRx(31 downto 16);
else
RxData := TmpRx(15 downto 0);
end if;
end procedure DMAComp16;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWriteQuiet(Address, Data & Data & Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
end procedure DMAWriteQuiet8;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWrite(Address, Data & Data & Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
end procedure DMAWrite8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
if Address(1 downto 0)="00" then
Data := Tmp(31 downto 24);
elsif Address(1 downto 0)="01" then
Data := Tmp(23 downto 16);
elsif Address(1 downto 0)="10" then
Data := Tmp(15 downto 8);
else
Data := Tmp( 7 downto 0);
end if;
end procedure DMAQuiet8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead8";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMARead(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
if Address(1 downto 0)="00" then
Data := Tmp(31 downto 24);
elsif Address(1 downto 0)="01" then
Data := Tmp(23 downto 16);
elsif Address(1 downto 0)="10" then
Data := Tmp(15 downto 8);
else
Data := Tmp( 7 downto 0);
end if;
end procedure DMARead8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector( 7 downto 0);
variable RxData: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable TmpRx: Std_Logic_Vector(31 downto 0);
variable TmpCx: Std_Logic_Vector(31 downto 0);
begin
if Address(1 downto 0)="00" then
TmpCx := CxData & "--------" & "--------" & "--------";
elsif Address(1 downto 0)="01" then
TmpCx := "--------" & CxData & "--------" & "--------";
elsif Address(1 downto 0)="10" then
TmpCx := "--------" & "--------" & CxData & "--------";
else
TmpCx := "--------" & "--------" & "--------" & CxData;
end if;
DMAComp(Address, TmpCx, TmpRx, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
if Address(1 downto 0)="00" then
RxData := TmpRx(31 downto 24);
elsif Address(1 downto 0)="01" then
RxData := TmpRx(23 downto 16);
elsif Address(1 downto 0)="10" then
RxData := TmpRx(15 downto 8);
else
RxData := TmpRx( 7 downto 0);
end if;
end procedure DMAComp8;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable L: Line;
constant Count: Integer := Data'Length*WordSize/Size;
variable GCount: Integer := Data'Length*WordSize/Size;
variable DCount: Integer := 1;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Data <= (others => '0');
dmai.Request <= '1';
dmai.Store <= '1';
if Count > 1 then
dmai.Burst <= '1';
else
dmai.Burst <= '0';
end if;
if Beat=1 then
dmai.Beat <= HINCR;
elsif Beat=4 then
dmai.Beat <= HINCR4;
elsif Beat=8 then
dmai.Beat <= HINCR8;
elsif Beat=16 then
dmai.Beat <= HINCR16;
else
report "Unsupported beat"
severity Failure;
end if;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
-- wait for first grant, indicating start of accesses
Synchronise(HCLK, 0 ns);
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
end if;
GCount := GCount-1;
-- first data
if Size=32 then
dmai.Data <= Data(0);
elsif Size=16 then
dmai.Data <= Data(0)(31 downto 16) & Data(0)(31 downto 16);
elsif Size=8 then
dmai.Data <= Data(0)(31 downto 24) & Data(0)(31 downto 24) &
Data(0)(31 downto 24) & Data(0)(31 downto 24);
end if;
loop
-- remove request when all grants received
if dmao.Grant='1' then
if GCount=0 then
dmai.Reset <= '0';
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
else
GCount := GCount-1;
end if;
end if;
Synchronise(HCLK, 0 ns);
while dmao.Grant='0' and dmao.Ready='0' and dmao.OKAY='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK, 0 ns);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK, 0 ns);
Synchronise(HCLK, 0 ns);
exit;
elsif dmao.OKAY='1' then
-- for each OKAY, provide new data
if DCount=Count then
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK, 0 ns);
while dmao.Ready='0' loop
Synchronise(HCLK, 0 ns);
end loop;
if GCount/=0 then
report "DMAWriteQuietBurst: Too few grants received!"
severity Failure;
end if;
exit;
else
if Size=32 then
dmai.Data <= Data(DCount);
elsif Size=16 then
dmai.Data <= Data(DCount/2)((31-16*(DCount mod 2)) downto (16-(16*(DCount mod 2)))) &
Data(DCount/2)((31-16*(DCount mod 2)) downto (16-(16*(DCount mod 2))));
elsif Size=8 then
dmai.Data <= Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4))));
end if;
DCount := DCount+1;
end if;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" RETRY/SPLIT response "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAWriteQuietBurst;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
begin
DMAWriteQuietBurst(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
if ScreenOutput and OK then
for i in 0 to Data'Length-1 loop
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write (L, String'(" : data: "));
HWrite(L, Data(i));
WriteLine(Output, L);
end loop;
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure DMAWriteBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable L: Line;
constant Count: Integer := Data'Length*WordSize/Size;
variable GCount: Integer := Data'Length*WordSize/Size;
variable DCount: Integer := 1;
variable DataPart: Integer := 0;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Data <= (others => '0');
dmai.Request <= '1';
dmai.Store <= '0';
if Count > 1 then
dmai.Burst <= '1';
else
dmai.Burst <= '0';
end if;
if Beat=1 then
dmai.Beat <= HINCR;
elsif Beat=4 then
dmai.Beat <= HINCR4;
elsif Beat=8 then
dmai.Beat <= HINCR8;
elsif Beat=16 then
dmai.Beat <= HINCR16;
else
report "Unsupported beat"
severity Failure;
end if;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
if Address(1 downto 0) = "00" then
DataPart := 0;
else
DataPart := 1;
end if;
elsif Size=8 then
dmai.Size <= HSIZE8;
if Address(1 downto 0) = "00" then
DataPart := 0;
elsif Address(1 downto 0) = "01" then
DataPart := 1;
elsif Address(1 downto 0) = "10" then
DataPart := 2;
else
DataPart := 3;
end if;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
-- wait for first grant, indicating start of accesses
Synchronise(HCLK, 0 ns);
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
end if;
GCount := GCount-1;
loop
-- remove request when all grants received
if dmao.Grant='1' then
if GCount=0 then
dmai.Reset <= '0';
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
else
GCount := GCount-1;
end if;
end if;
Synchronise(HCLK, 0 ns);
while dmao.Grant='0' and dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK, 0 ns);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" ERROR response"));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
-- for each READY, store data
if Size=32 then
Data(DCount-1) := dmao.Data;
elsif Size=16 then
Data((DCount-1)/2)((31-16*((DCount-1) mod 2)) downto (16-(16*((DCount-1) mod 2)))) :=
dmao.Data((31-16*DataPart) downto (16-16*DataPart));
DataPart := (DataPart + 1) mod 2;
elsif Size=8 then
Data((DCount-1)/4)((31-8*((DCount-1) mod 4)) downto (24-(8*((DCount-1) mod 4)))) :=
dmao.Data((31-8*DataPart) downto (24-8*DataPart));
DataPart := (DataPart + 1) mod 4;
end if;
if DCount=Count then
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
if GCount/=0 then
report "DMAQuietBurst: Too few grants received!"
severity Failure;
end if;
exit;
else
DCount := DCount+1;
end if;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" RETRY/SPLIT response "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAQuietBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAReadBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Data_Vector(0 to Data'Length-1);
begin
DMAQuietBurst(Address, Temp, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
if ScreenOutput and OK then
Data := Temp;
for i in 0 to Data'Length-1 loop
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write (L, String'(" : data: "));
HWrite(L, Temp(i));
WriteLine(Output, L);
end loop;
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Temp := (others => (others => '-'));
Data := Temp;
TP := False;
end if;
end procedure DMAReadBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMACompBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable CxData: in Data_Vector;
variable RxData: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Data_Vector(0 to CxData'Length-1);
begin
DMAQuietBurst(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
Data := (others => (others => '-'));
RxData := Data;
else
for i in 0 to Data'Length-1 loop
if not Compare(Data(i), CxData(i)) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write(L, String'(" : data: "));
HWrite(L, Data(i));
Write(L, String'(" : expected: "));
HWrite(L, CxData(i));
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write(L, String'(" : data: "));
HWrite(L, Data(i));
WriteLine(Output, L);
end if;
end loop;
RxData := Data;
end if;
end procedure DMACompBurst;
end package body DMA2AHB_TestPackage; --======================================--
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/srmmu/mmutlb.vhd | 1 | 21508 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutlb
-- File: mmutlb.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU TLB logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmutlb is
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 1;
mmupgsz : integer range 0 to 5 := 0;
ramcbits: integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type;
ramcclk: in std_ulogic;
ramcin : in std_logic_vector(ramcbits-1 downto 0);
ramcout: out std_logic_vector(ramcbits-1 downto 0)
);
end mmutlb;
architecture rtl of mmutlb is
constant M_TLB_FASTWRITE : integer range 0 to 3 :=
conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant entries_log : integer := log2(entries);
constant entries_max : std_logic_vector(entries_log-1 downto 0) :=
conv_std_logic_vector(entries-1, entries_log);
type states is (idle, match, walk, pack, flush, sync, diag, dofault);
type tlb_rtype is record
s2_tlbstate : states;
s2_entry : std_logic_vector(entries_log-1 downto 0);
s2_hm : std_logic;
s2_needsync : std_logic;
s2_data : std_logic_vector(31 downto 0);
s2_isid : mmu_idcache;
s2_su : std_logic;
s2_read : std_logic;
s2_flush : std_logic;
s2_ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
walk_use : std_logic;
walk_transdata : mmuidc_data_out_type;
walk_fault : mmutlbfault_out_type;
nrep : std_logic_vector(entries_log-1 downto 0);
tpos : std_logic_vector(entries_log-1 downto 0);
touch : std_logic;
sync_isw : std_logic;
tlbmiss : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : tlb_rtype := (
s2_tlbstate => idle,
s2_entry => (others => '0'),
s2_hm => '0',
s2_needsync => '0',
s2_data => (others => '0'),
s2_isid => id_icache,
s2_su => '0',
s2_read => '0',
s2_flush => '0',
s2_ctx => (others => '0'),
walk_use => '0',
walk_transdata => mmuidco_zero,
walk_fault => mmutlbfault_out_zero,
nrep => (others => '0'),
tpos => (others => '0'),
touch => '0',
sync_isw => '0',
tlbmiss => '0');
signal c,r : tlb_rtype;
-- tlb cams
component mmutlbcam
generic (
tlb_type : integer range 0 to 3 := 1;
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
tlbcami : in mmutlbcam_in_type;
tlbcamo : out mmutlbcam_out_type
);
end component;
signal tlbcami : mmutlbcami_a (entries-1 downto 0);
signal tlbcamo : mmutlbcamo_a (entries-1 downto 0);
-- least recently used
component mmulru
generic (
entries : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
lrui : in mmulru_in_type;
lruo : out mmulru_out_type
);
end component;
signal lrui : mmulru_in_type;
signal lruo : mmulru_out_type;
-- data-ram syncram signals
signal dr1_addr : std_logic_vector(entries_log-1 downto 0);
signal dr1_datain : std_logic_vector(29 downto 0);
signal dr1_dataout : std_logic_vector(29 downto 0);
signal dr1_enable : std_logic;
signal dr1_write : std_logic;
begin
p0: process (rst, r, tlbi, two, tlbcamo, dr1_dataout, lruo)
variable v : tlb_rtype;
variable finish, selstate : std_logic;
variable cam_hitaddr : std_logic_vector(entries_log-1 downto 0);
variable cam_hit_all : std_logic;
variable mtag,ftag : tlbcam_tfp;
-- tlb cam input
variable tlbcam_trans_op : std_logic;
variable tlbcam_write_op : std_logic_vector(entries-1 downto 0);
variable tlbcam_flush_op : std_logic;
-- tw inputs
variable twi_walk_op_ur : std_logic;
variable twi_data : std_logic_vector(31 downto 0);
variable twi_areq_ur : std_logic;
variable twi_aaddr : std_logic_vector(31 downto 0);
variable twi_adata : std_logic_vector(31 downto 0);
variable two_error : std_logic;
-- lru inputs
variable lrui_touch : std_logic;
variable lrui_touchmin : std_logic;
variable lrui_pos : std_logic_vector(entries_log-1 downto 0);
-- syncram inputs
variable dr1write : std_logic;
-- hit tlbcam's output
variable ACC : std_logic_vector(2 downto 0);
variable PTE : std_logic_vector(31 downto 0);
variable LVL : std_logic_vector(1 downto 0);
variable CAC : std_logic;
variable NEEDSYNC : std_logic;
-- wb hit tlbcam's output
variable wb_i_entry : integer range 0 to entries-1;
variable wb_ACC : std_logic_vector(2 downto 0);
variable wb_PTE : std_logic_vector(31 downto 0);
variable wb_LVL : std_logic_vector(1 downto 0);
variable wb_CAC : std_logic;
variable wb_fault_pro, wb_fault_pri : std_logic;
variable wb_WBNEEDSYNC : std_logic;
variable twACC : std_logic_vector(2 downto 0);
variable tWLVL : std_logic_vector(1 downto 0);
variable twPTE : std_logic_vector(31 downto 0);
variable twNEEDSYNC : std_logic;
variable tlbcam_tagin : tlbcam_tfp;
variable tlbcam_tagwrite : tlbcam_reg;
variable store : std_logic;
variable reppos : std_logic_vector(entries_log-1 downto 0);
variable i_entry : integer range 0 to entries-1;
variable i_reppos : integer range 0 to entries-1;
variable fault_pro, fault_pri : std_logic;
variable fault_mexc, fault_trans, fault_inv, fault_access : std_logic;
variable transdata : mmuidc_data_out_type;
variable fault : mmutlbfault_out_type;
variable savewalk : std_logic;
variable tlbo_s1finished : std_logic;
variable wb_transdata : mmuidc_data_out_type;
variable cam_addr : std_logic_vector(31 downto 0);
begin
v := r; v.tlbmiss := '0';
cam_addr := tlbi.transdata.data;
wb_i_entry := 0;
wb_ACC := (others => '0');
wb_PTE := (others => '0');
wb_LVL := (others => '0');
wb_CAC := '0';
wb_fault_pro := '0';
wb_fault_pri := '0';
wb_WBNEEDSYNC := '0';
if (M_TLB_FASTWRITE /= 0) and (tlbi.trans_op = '0') then
cam_addr := tlbi.transdata.wb_data;
end if;
wb_transdata.finish := '0';
wb_transdata.data := (others => '0');
wb_transdata.cache := '0';
wb_transdata.accexc := '0';
finish := '0';
selstate := '0';
cam_hitaddr := (others => '0');
cam_hit_all := '0';
mtag.TYP := (others => '0');
mtag.I1 := (others => '0');
mtag.I2 := (others => '0');
mtag.I3 := (others => '0');
mtag.CTX := (others => '0');
mtag.M := '0';
ftag.TYP := (others => '0');
ftag.I1 := (others => '0');
ftag.I2 := (others => '0');
ftag.I3 := (others => '0');
ftag.CTX := (others => '0');
ftag.M := '0';
tlbcam_trans_op := '0';
tlbcam_write_op := (others => '0');
tlbcam_flush_op := '0';
twi_walk_op_ur := '0';
twi_data := (others => '0');
twi_areq_ur := '0';
twi_aaddr := (others => '0');
twi_adata := (others => '0');
two_error := '0';
lrui_touch:= '0';
lrui_touchmin:= '0';
lrui_pos := (others => '0');
dr1write := '0';
ACC := (others => '0');
PTE := (others => '0');
LVL := (others => '0');
CAC := '0';
NEEDSYNC := '0';
twACC := (others => '0');
tWLVL := (others => '0');
twPTE := (others => '0');
twNEEDSYNC := '0';
tlbcam_tagin.TYP := (others => '0');
tlbcam_tagin.I1 := (others => '0');
tlbcam_tagin.I2 := (others => '0');
tlbcam_tagin.I3 := (others => '0');
tlbcam_tagin.CTX := (others => '0');
tlbcam_tagin.M := '0';
tlbcam_tagwrite.ET := (others => '0');
tlbcam_tagwrite.ACC := (others => '0');
tlbcam_tagwrite.M := '0';
tlbcam_tagwrite.R := '0';
tlbcam_tagwrite.SU := '0';
tlbcam_tagwrite.VALID := '0';
tlbcam_tagwrite.LVL := (others => '0');
tlbcam_tagwrite.I1 := (others => '0');
tlbcam_tagwrite.I2 := (others => '0');
tlbcam_tagwrite.I3 := (others => '0');
tlbcam_tagwrite.CTX := (others => '0');
tlbcam_tagwrite.PPN := (others => '0');
tlbcam_tagwrite.C := '0';
store := '0';
reppos := (others => '0');
fault_pro := '0';
fault_pri := '0';
fault_mexc := '0';
fault_trans := '0';
fault_inv := '0';
fault_access := '0';
transdata.finish := '0';
transdata.data := (others => '0');
transdata.cache := '0';
transdata.accexc := '0';
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
savewalk := '0';
tlbo_s1finished := '0';
tlbcam_trans_op := '0'; tlbcam_write_op := (others => '0'); tlbcam_flush_op := '0';
lrui_touch := '0'; lrui_touchmin := '0'; lrui_pos := (others => '0');
dr1write := '0';
fault_pro := '0'; fault_pri := '0'; fault_mexc := '0'; fault_trans := '0'; fault_inv := '0'; fault_access := '0';
twi_walk_op_ur := '0'; twi_areq_ur := '0'; twi_aaddr := dr1_dataout&"00";
finish := '0';
store := '0'; savewalk := '0'; tlbo_s1finished := '0';
selstate := '0';
cam_hitaddr := (others => '0');
cam_hit_all := '0';
NEEDSYNC := '0';
for i in entries-1 downto 0 loop
NEEDSYNC := NEEDSYNC or tlbcamo(i).NEEDSYNC;
if (tlbcamo(i).hit) = '1' then
cam_hitaddr(entries_log-1 downto 0) := cam_hitaddr(entries_log-1 downto 0) or conv_std_logic_vector(i, entries_log);
cam_hit_all := '1';
end if;
end loop;
-- tlbcam write operation
tlbcam_tagwrite := TLB_CreateCamWrite( two.data, r.s2_read, two.lvl, r.s2_ctx, r.s2_data);
-- replacement position
reppos := (others => '0');
if tlb_rep = 0 then
reppos := lruo.pos(entries_log-1 downto 0);
v.touch := '0';
elsif tlb_rep = 1 then
reppos := r.nrep;
end if;
i_reppos := conv_integer(reppos);
-- tw
two_error := two.fault_mexc or two.fault_trans or two.fault_inv;
twACC := two.data(PTE_ACC_U downto PTE_ACC_D);
twLVL := two.lvl;
twPTE := two.data;
twNEEDSYNC := (not two.data(PTE_R)) or ((not r.s2_read) and (not two.data(PTE_M))); -- tw : writeback on next flush
case r.s2_tlbstate is
when idle =>
if (tlbi.s2valid) = '1' then
if r.s2_flush = '1' then
v.s2_tlbstate := pack;
else
v.walk_fault.fault_pri := '0';
v.walk_fault.fault_pro := '0';
v.walk_fault.fault_access := '0';
v.walk_fault.fault_trans := '0';
v.walk_fault.fault_inv := '0';
v.walk_fault.fault_mexc := '0';
if (r.s2_hm and not tlbi.mmctrl1.tlbdis ) = '1' then
if r.s2_needsync = '1' then
v.s2_tlbstate := sync;
else
finish := '1';
end if;
if tlb_rep = 0 then
v.tpos := r.s2_entry; v.touch := '1'; -- touch lru
end if;
else
v.s2_entry := reppos;
v.s2_tlbstate := walk; v.tlbmiss := '1';
if tlb_rep = 0 then
lrui_touchmin := '1'; -- lru element consumed
end if;
end if;
end if;
end if;
when walk =>
if (two.finish = '1') then
if ( two_error ) = '0' then
tlbcam_write_op := decode(r.s2_entry);
dr1write := '1';
TLB_CheckFault( twACC, r.s2_isid, r.s2_su, r.s2_read, v.walk_fault.fault_pro, v.walk_fault.fault_pri );
end if;
TLB_MergeData( mmupgsz, tlbi.mmctrl1, two.lvl , two.data, r.s2_data, v.walk_transdata.data );
v.walk_transdata.cache := two.data(PTE_C);
v.walk_fault.fault_lvl := two.fault_lvl;
v.walk_fault.fault_access := '0';
v.walk_fault.fault_mexc := two.fault_mexc;
v.walk_fault.fault_trans := two.fault_trans;
v.walk_fault.fault_inv := two.fault_inv;
v.walk_use := '1';
if ( twNEEDSYNC = '0' or two_error = '1') then
v.s2_tlbstate := pack;
else
v.s2_tlbstate := sync;
v.sync_isw := '1';
end if;
if tlb_rep = 1 then
if (r.nrep = entries_max) then v.nrep := (others => '0');
else v.nrep := r.nrep + 1;
end if;
end if;
else
twi_walk_op_ur := '1';
end if;
when pack =>
v.s2_flush := '0';
v.walk_use := '0';
finish := '1';
v.s2_tlbstate := idle;
when sync =>
tlbcam_trans_op := '1';
if ( v.sync_isw = '1') then
-- pte address is currently written to syncram, wait one cycle before issuing twi_areq_ur
v.sync_isw := '0';
else
if (two.finish = '1') then
v.s2_tlbstate := pack;
v.walk_fault.fault_mexc := two.fault_mexc;
if (two.fault_mexc) = '1' then
v.walk_use := '1';
end if;
else
twi_areq_ur := '1';
end if;
end if;
when others =>
v .s2_tlbstate := idle;
end case;
if selstate = '1' then
if tlbi.trans_op = '1' then
elsif tlbi.flush_op = '1' then
end if;
end if;
i_entry := conv_integer(r.s2_entry);
ACC := tlbcamo(i_entry).pteout(PTE_ACC_U downto PTE_ACC_D);
PTE := tlbcamo(i_entry).pteout;
LVL := tlbcamo(i_entry).LVL;
CAC := tlbcamo(i_entry).pteout(PTE_C);
transdata.cache := CAC;
--# fault, todo: should we flush on a fault?
TLB_CheckFault( ACC, r.s2_isid, r.s2_su, r.s2_read, fault_pro, fault_pri );
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
if finish = '1' and (r.s2_flush = '0') then --protect flush path
fault.fault_pro := fault_pro;
fault.fault_pri := fault_pri;
fault.fault_access := fault_access;
fault.fault_mexc := fault_mexc;
fault.fault_trans := fault_trans;
fault.fault_inv := fault_inv;
end if;
if (M_TLB_FASTWRITE /= 0) then
wb_i_entry := conv_integer(cam_hitaddr(entries_log-1 downto 0));
wb_ACC := tlbcamo(wb_i_entry).pteout(PTE_ACC_U downto PTE_ACC_D);
wb_PTE := tlbcamo(wb_i_entry).pteout;
wb_LVL := tlbcamo(wb_i_entry).LVL;
wb_CAC := tlbcamo(wb_i_entry).pteout(PTE_C);
wb_WBNEEDSYNC := tlbcamo(wb_i_entry).WBNEEDSYNC;
wb_transdata.cache := wb_CAC;
TLB_MergeData( mmupgsz, tlbi.mmctrl1, wb_LVL, wb_PTE, tlbi.transdata.data, wb_transdata.data );
--# fault, todo: should we flush on a fault?
TLB_CheckFault( wb_ACC, tlbi.transdata.isid, tlbi.transdata.su, tlbi.transdata.read, wb_fault_pro, wb_fault_pri );
wb_transdata.accexc := wb_fault_pro or wb_fault_pri or wb_WBNEEDSYNC or (not cam_hit_all);
end if;
--# merge data
TLB_MergeData( mmupgsz, tlbi.mmctrl1, LVL, PTE, r.s2_data, transdata.data );
--# reset
if (not RESET_ALL) and (rst = '0') then
v.s2_flush := '0';
v.s2_tlbstate := idle;
if tlb_rep = 1 then
v.nrep := (others => '0');
end if;
if tlb_rep = 0 then
v.touch := '0';
end if;
v.sync_isw := '0';
end if;
if (finish = '1') or (tlbi.s2valid = '0') then
tlbo_s1finished := '1';
v.s2_hm := cam_hit_all;
v.s2_entry := cam_hitaddr(entries_log-1 downto 0);
v.s2_needsync := NEEDSYNC;
v.s2_data := tlbi.transdata.data;
v.s2_read := tlbi.transdata.read;
v.s2_su := tlbi.transdata.su;
v.s2_isid := tlbi.transdata.isid;
v.s2_flush := tlbi.flush_op;
v.s2_ctx := tlbi.mmctrl1.ctx;
end if;
-- translation operation tag
mtag := TLB_CreateCamTrans( cam_addr, tlbi.transdata.read, tlbi.mmctrl1.ctx );
tlbcam_tagin := mtag;
-- flush/(probe) operation tag
ftag := TLB_CreateCamFlush( r.s2_data, tlbi.mmctrl1.ctx );
if (r.s2_flush = '1') then
tlbcam_tagin := ftag;
end if;
if r.walk_use = '1' then
transdata := r.walk_transdata;
fault := r.walk_fault;
end if;
fault.fault_read := r.s2_read;
fault.fault_su := r.s2_su;
fault.fault_isid := r.s2_isid;
fault.fault_addr := r.s2_data;
transdata.finish := finish;
transdata.accexc := '0';
twi_adata := PTE;
--# drive signals
tlbo.wbtransdata <= wb_transdata;
tlbo.transdata <= transdata;
tlbo.fault <= fault;
tlbo.nexttrans <= store;
tlbo.s1finished <= tlbo_s1finished;
twi.walk_op_ur <= twi_walk_op_ur;
twi.data <= r.s2_data;
twi.areq_ur <= twi_areq_ur;
twi.adata <= twi_adata;
twi.aaddr <= twi_aaddr;
twi.tlbmiss <= r.tlbmiss;
if tlb_rep = 0 then
lrui.flush <= r.s2_flush;
lrui.touch <= r.touch;
lrui.touchmin <= lrui_touchmin;
lrui.pos <= (others => '0');
lrui.pos(entries_log-1 downto 0) <= r.tpos;
lrui.mmctrl1 <= tlbi.mmctrl1;
end if;
dr1_addr <= r.s2_entry;
dr1_datain <= two.addr(31 downto 2);
dr1_enable <= '1';
dr1_write <= dr1write;
for i in entries-1 downto 0 loop
tlbcami(i).mmctrl <= tlbi.mmctrl1;
tlbcami(i).tagin <= tlbcam_tagin;
tlbcami(i).trans_op <= tlbi.trans_op; --tlbcam_trans_op;
tlbcami(i).wb_op <= tlbi.wb_op; --tlbcam_trans_op;
tlbcami(i).flush_op <= r.s2_flush;
tlbcami(i).mmuen <= tlbi.mmctrl1.e;
tlbcami(i).tagwrite <= tlbcam_tagwrite;
tlbcami(i).write_op <= tlbcam_write_op(i);
tlbcami(i).mset <= '0';
end loop; -- i
c <= v;
end process p0;
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
-- tag-cam tlb entries
tlbcam0: for i in entries-1 downto 0 generate
tag0 : mmutlbcam
generic map ( tlb_type, mmupgsz )
port map (rst, clk, tlbcami(i), tlbcamo(i));
end generate tlbcam0;
-- data-ram syncram
dataram : syncram
generic map ( tech => tech, dbits => 30, abits => entries_log, custombits => ramcbits)
port map ( clk, dr1_addr, dr1_datain, dr1_dataout, dr1_enable, dr1_write,
tlbi.testin, ramcclk, ramcin, ramcout );
-- lru
lru0: if tlb_rep = 0 generate
lru : mmulru
generic map ( entries => entries)
port map ( clk, rst, lrui, lruo );
end generate lru0;
end rtl;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep3c25-eek/config.vhd | 1 | 7326 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0039#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000011#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (8);
constant CFG_DDRSP_RSKEW : integer := (2500);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0#;
constant CFG_GRGPIO_WIDTH : integer := (5);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- PS/2 interface
constant CFG_PS2_ENABLE : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- LCD SVGA controller
constant CFG_LCD_ENABLE : integer := 1;
-- LCD 3-wire serial interface
constant CFG_LCD3T_ENABLE : integer := 1;
-- SVGA controller
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/easic.vhdl | 2 | 15 | set vhdlList {
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/syncram_2pbw.vhd | 1 | 9245 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram_2pbw
-- File: syncram_2pbw.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous 2-port ram with tech selection and 8-bit write
-- strobes
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram_2pbw is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_logic_vector((dbits/8-1) downto 0);
raddress : in std_logic_vector((abits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
wclk : in std_ulogic;
write : in std_logic_vector((dbits/8-1) downto 0);
waddress : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector((dbits/8)*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector((dbits/8)*custombits-1 downto 0));
end;
architecture rtl of syncram_2pbw is
constant nctrl : integer := abits*2 + 2 + 2*dbits/8;
signal dataoutx : std_logic_vector((dbits -1) downto 0);
signal databp, testdata : std_logic_vector((dbits -1) downto 0);
signal renable2 : std_logic_vector((dbits/8-1) downto 0);
constant SCANTESTBP : boolean := (testen = 1) and (tech /= 0) and (tech /= ut90);
constant iwrfst : integer := (1-syncram_2p_write_through(tech)) * wrfst;
signal xrenable,xwrite : std_logic_vector(dbits/8-1 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xrenable <= renable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
s2pbw : if has_sram_2pbw(tech) = 1 generate
no_wrfst : if iwrfst = 0 generate
scanbp : if SCANTESTBP generate
comb : process (waddress, raddress, datain, renable, write, testin)
variable tmp : std_logic_vector((dbits -1) downto 0);
variable ctrlsigs : std_logic_vector((nctrl -1) downto 0);
begin
ctrlsigs := testin(1 downto 0) & write & renable & raddress & waddress;
tmp := datain;
for i in 0 to nctrl-1 loop
tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i);
end loop;
testdata <= tmp;
end process;
reg : process(wclk) begin
if rising_edge(wclk) then databp <= testdata; end if;
end process;
dmuxout : for i in 0 to dbits-1 generate
x0 : grmux2 generic map (tech)
port map (dataoutx(i), databp(i), testin(3), dataout(i));
end generate;
end generate;
noscanbp : if not SCANTESTBP generate dataout <= dataoutx; end generate;
-- Write contention check (if applicable)
wcheck : for i in 0 to dbits/8-1 generate
renable2(i) <= '0' when ((sepclk = 0 and syncram_2p_dest_rw_collision(tech) = 1) and
(renable(i) and write(i)) = '1' and raddress = waddress) else renable(i);
end generate;
end generate;
wrfst_gen : if iwrfst = 1 generate
-- No risk for read/write contention. Register addresses and mux on comparator
no_contention_check : if syncram_2p_dest_rw_collision(tech) = 0 generate
wfrstblocknoc : block
type wrfst_type is record
raddr : std_logic_vector((abits-1) downto 0);
waddr : std_logic_vector((abits-1) downto 0);
datain : std_logic_vector((dbits-1) downto 0);
write : std_logic_vector((dbits/8-1) downto 0);
renable : std_logic_vector((dbits/8-1) downto 0);
end record;
signal r : wrfst_type;
begin
comb : process(r, dataoutx, testin) begin
for i in 0 to dbits/8-1 loop
if (SCANTESTBP and (testin(3) = '1')) or
(((r.write(i) and r.renable(i)) = '1') and (r.raddr = r.waddr)) then
dataout(i*8+7 downto i*8) <= r.datain(i*8+7 downto i*8);
else dataout(i*8+7 downto i*8) <= dataoutx(i*8+7 downto i*8); end if;
end loop;
end process;
reg : process(wclk) begin
if rising_edge(wclk) then
r.raddr <= raddress; r.waddr <= waddress;
r.datain <= datain; r.write <= write;
r.renable <= renable;
end if;
end process;
end block wfrstblocknoc;
renable2 <= renable;
end generate;
-- Risk of read/write contention. Use same comparator to gate read enable
-- and mux data.
contention_safe : if syncram_2p_dest_rw_collision(tech) /= 0 generate
wfrstblockc : block
signal col, mux : std_logic_vector((dbits/8-1) downto 0);
signal rdatain : std_logic_vector((dbits-1) downto 0);
begin
comb : process(mux, renable, write, raddress, waddress, rdatain,
dataoutx, testin)
begin
for i in 0 to dbits/8-1 loop
col(i) <= '0'; renable2(i) <= renable(i);
if (write(i) and renable(i)) = '1' and raddress = waddress then
col(i) <= '1'; renable2(i) <= '0';
end if;
if (SCANTESTBP and (testin(3) = '1')) or mux(i) = '1' then
dataout(i*8+7 downto i*8) <= rdatain(i*8+7 downto i*8);
else dataout(i*8+7 downto i*8) <= dataoutx(i*8+7 downto i*8); end if;
end loop;
end process;
reg : process(wclk) begin
if rising_edge(wclk) then
rdatain <= datain; mux <= col;
end if;
end process;
end block wfrstblockc;
end generate;
end generate wrfst_gen;
custominx(custominx'high downto custombits) <= (others => '0');
custominx(custombits-1 downto 0) <= customin;
nocust: if has_sram_2pbw(tech)=0 or syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
co0: if has_sram_2pbw(tech)=1 generate
customout(custombits-1 downto 0) <= customoutx(custombits-1 downto 0);
customout(customout'high downto custombits) <= (others => '0');
end generate;
n2x : if tech = easic45 generate
x0 : n2x_syncram_2p_be generic map (abits, dbits, sepclk, iwrfst)
port map (rclk, renable2, raddress, dataoutx, wclk,
write, waddress, datain);
end generate;
-- pragma translate_off
noram : if has_2pram(tech) = 0 generate
x : process
begin
assert false report "synram_2pbw: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram_2pbw: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
generic_check : process
begin
assert sepclk = 0 or wrfst = 0
report "syncram_2pbw: Write-first not supported for RAM with separate clocks"
severity failure;
wait;
end process;
-- pragma translate_on
end generate;
nos2pbw : if has_sram_2pbw(tech) /= 1 generate
rx : for i in 0 to dbits/8-1 generate
x0 : syncram_2p generic map (tech, abits, 8, sepclk, wrfst, testen, words, custombits)
port map (rclk, renable(i), raddress, dataout(i*8+7 downto i*8), wclk, write(i),
waddress, datain(i*8+7 downto i*8), testin,
customclk, customin((i+1)*custombits-1 downto i*custombits),
customout((i+1)*custombits-1 downto i*custombits));
end generate;
end generate;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/grpci1/pcidma.vhd | 1 | 4065 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_dma
-- File: pci_dma.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: PCI master and target interface with DMA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use gaisler.pcilib.all;
entity pcidma is
generic (
memtech : integer := DEFMEMTECH;
dmstndx : integer := 0;
dapbndx : integer := 0;
dapbaddr : integer := 0;
dapbmask : integer := 16#fff#;
dapbirq : integer := 0;
blength : integer := 16;
mstndx : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
slvndx : integer := 0;
apbndx : integer := 0;
apbaddr : integer := 0;
apbmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0; -- 0 little, 1 big
class_code: integer := 16#0B4000#;
rev : integer := 0;
irq : integer := 0;
irqmask : integer := 0;
scanen : integer := 0;
hostrst : integer := 0;
syncrst : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
dapbo : out apb_slv_out_type;
dahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of pcidma is
signal ahbsi2 : ahb_slv_in_type;
signal ahbso2 : ahb_slv_out_type;
begin
dma : dmactrl generic map (hindex => dmstndx, slvindex => slvndx, pindex => dapbndx,
paddr => dapbaddr, pirq => dapbirq, blength => blength)
port map (rst, clk, apbi, dapbo, ahbmi, dahbmo, ahbsi, ahbso, ahbsi2, ahbso2);
pci : pci_mtf generic map (memtech => memtech, hmstndx => mstndx, dmamst => dmstndx,
fifodepth => fifodepth, device_id => device_id, vendor_id => vendor_id,
hslvndx => slvndx, pindex => apbndx, paddr => apbaddr, irq => irq, irqmask => irqmask,
haddr => haddr, hmask => hmask, ioaddr => ioaddr, abits => abits, syncrst => syncrst,
dmaabits => dmaabits, nsync => nsync, oepol => oepol, endian => endian,
class_code => class_code, rev => rev, scanen => scanen, hostrst => hostrst)
port map (rst, clk, pciclk, pcii, pcio, apbi, apbo, ahbmi, ahbmo, ahbsi2, ahbso2);
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml501/svga2ch7301c.vhd | 3 | 10192 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "10.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll1: label is CLKIN_PERIOD_ST;
attribute CLKIN_PERIOD of dll2: label is CLKIN_PERIOD_ST;
signal clk_l, clk_m, clk_n, clk_o : std_logic;
signal dll0lock, dll1lock, dll2lock : std_logic;
signal dllrst : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk_fb)
begin -- process
if rising_edge(vgaclk_fb) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25_fb when clksel(1) = '0' else lclk40_65;
lclk40_65 <= lclk40 when clksel(0) = '0' else lclk65;
bufg01 : BUFG port map (I => clk40_fb, O => lclk40);
bufg02 : BUFG port map (I => clk65_fb, O => lclk65);
dllrst <= not rstn;
-- Generate clocks
clkdiv : process(clk_m, rstn)
begin
if (rstn and dll1lock) = '0' then clkval <= "00";
elsif rising_edge(clk_m) then
clkval <= clkval + 1;
end if;
end process;
clk25 <= clkval(1);
dll0lock <= '1';
bufg03 : BUFG port map (I => clk_l, O => clk_m);
dll1 : DCM
generic map (CLKFX_MULTIPLY => 4, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_m, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_l,
CLKFX => clk40, LOCKED => dll1lock);
bufg04 : BUFG port map (I => clk_n, O => clk_o);
dll2 : DCM
generic map (CLKFX_MULTIPLY => 13, CLKFX_DIVIDE => 20,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_o, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_n,
CLKFX => clk65, LOCKED => dll2lock);
locked <= dll0lock and dll1lock and dll2lock;
end rtl;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys2/leon3mp.vhd | 1 | 17843 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
error : out std_ulogic;
-- memoria
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 16);
ramsn : out std_logic;
mben : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
RamAdv : out std_logic;
RamClk : out std_logic;
RamCRE : out std_logic;
--RamLB : out std_logic;
--RamUB : out std_logic;
--memoria
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd2 : out std_ulogic; -- UART1 tx data
rxd2 : in std_ulogic; -- UART1 rx data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
pio : inout std_logic_vector(17 downto 0); -- I/O port
-- switch : in std_logic_vector(7 downto 0); -- switches
-- button : in std_logic_vector(2 downto 0); -- buttons
ps2clk : inout std_logic;
ps2data : inout std_logic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic;
vid_g : out std_logic;
vid_b : out std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+
CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, nerror : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, rst : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
--signal txd1,txd2 : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clkval : std_logic_vector(1 downto 0);
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 0;
signal stati : ahbstat_in_type;
signal dac_clk, clk1x, vid_clock, video_clk, clkvga : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
RamAdv <= '0';
RamClk <= '0';
RamCRE <= '0';
--RamLB <= '0';
--RamUB <= '0';
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
nerror <= not dbgo(0).error;
error_pad : outpad generic map (tech => padtech) port map (error, nerror);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_JTAG = 1 generate -- UART
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
-- ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
-- ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
-- port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
-- open, open, open, open, open, open, open, gnd(0));
-- end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
rommask => 16#000#, iomask => 16#000#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
ramsa_pad : outpad generic map (tech => padtech)
port map (ramsn, memo.ramsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.ramoen(0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.wrn(0));
mben_pads : outpadv generic map (tech => padtech, width => 4)
port map (mben, memo.mben);
data_pads : iopadvv generic map (tech => padtech, width => 16)
port map (data, memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd2, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd2, u1o.txd);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
dac_clk <= not video_clk;
b1 : techbuf generic map (2, virtex2) port map (clkval(0), video_clk);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
clkvga <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (clkvga, video_clk);
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 20000, clk2 => 25000)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_JTAG), clk_sel);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpad generic map (tech => padtech)
port map (vid_r, vgao.video_out_r(7));
video_out_g_pad : outpad generic map (tech => padtech)
port map (vid_g, vgao.video_out_g(7));
video_out_b_pad : outpad generic map (tech => padtech)
port map (vid_b, vgao.video_out_b(7));
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
pio_pads : iopadvv generic map (width => 18, tech => padtech)
port map (pio, gpioo.dout(17 downto 0), gpioo.oen(17 downto 0),
gpioi.din(17 downto 0));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+FG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_version
generic map (
msg1 => "LEON3 Digilent XC3S1000 Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/ddr/ddr2buf.vhd | 1 | 6717 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2buf
-- File: ddr2buf.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Convenience wrapper for syncram2p with data width conversion
--------------------------------------------------------------------------------
-- 2^rabits x rdbits determines amount of RAM.
--
-- If 2^wabits x wdbits is larger than this, the lowest bits of waddress are
-- used for sub-size writes. writebig ignores these lower bits and writes the
-- full data vector at once.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
entity ddr2buf is
generic (tech : integer := 0; wabits : integer := 6; wdbits : integer := 8;
rabits : integer := 6; rdbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((rabits-1) downto 0);
dataout : out std_logic_vector((rdbits-1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
writebig : in std_ulogic;
waddress : in std_logic_vector((wabits-1) downto 0);
datain : in std_logic_vector((wdbits-1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end;
architecture rtl of ddr2buf is
function xlog2(x: integer) return integer is
variable q,r: integer;
begin
r := 0; q := 1;
while x > q loop
q := q+q; r := r+1;
end loop;
return r;
end xlog2;
function xmax(a,b: integer) return integer is
begin
if a>b then return a; else return b; end if;
end xmax;
function xmin(a,b: integer) return integer is
begin
if a<b then return a; else return b; end if;
end xmin;
constant membits : integer := (2**rabits) * rdbits;
constant wabitsbig : integer := xlog2(membits/wdbits);
constant wdbitsbig : integer := wdbits;
constant wabitssml : integer := wabits;
constant wdbitssml : integer := membits / (2**wabits);
constant totdwidth: integer := xmax(wdbitsbig,rdbits);
constant partdwidth: integer := wdbitssml;
constant nrams : integer := totdwidth/partdwidth;
constant dbits : integer := wdbitssml;
constant abits : integer := xlog2(membits/(dbits*nrams));
constant rdratio : integer := rdbits/dbits;
constant wdratio : integer := wdbitsbig/dbits;
type dv_type is array (0 to nrams-1) of std_logic_vector(dbits-1 downto 0);
signal do: dv_type;
signal di: dv_type;
signal we: std_logic_vector(0 to nrams-1);
signal prev_raddress: std_logic_vector(rabits-1 downto 0);
begin
regs: process(rclk)
begin
if rising_edge(rclk) then
prev_raddress <= raddress;
end if;
end process;
comb: process(prev_raddress,write,writebig,waddress,datain,do)
type rdvx_type is array (0 to totdwidth/rdbits-1) of std_logic_vector(rdbits-1 downto 0);
variable rdvx: rdvx_type;
variable vdo: std_logic_vector((rdbits-1) downto 0);
variable vdi: dv_type;
variable vwe: std_logic_vector(0 to nrams-1);
variable we1: std_logic_vector(0 to wdbitsbig/wdbitssml-1);
variable we2: std_logic_vector(0 to wdratio-1);
begin
vdi := (others => (others => '0'));
vwe := (others => '0');
-- Generate rdvx from do
for x in 0 to nrams-1 loop
if rdbits > dbits then
rdvx(x/rdratio)(rdbits-1-(x mod rdratio)*dbits downto rdbits-dbits-(x mod rdratio)*dbits) := do(x);
else
for y in 0 to dbits/rdbits-1 loop
rdvx(x*dbits/rdbits + y) := do(x)(dbits-1-y*rdbits downto dbits-rdbits-y*rdbits);
end loop;
end if;
end loop;
-- Generate dataout from rdvx and prev_address
vdo := rdvx(totdwidth/rdbits-1);
if totdwidth > rdbits then
for x in 0 to totdwidth/rdbits-2 loop
if prev_raddress(log2(totdwidth/rdbits)-1 downto 0) =
std_logic_vector(to_unsigned(x,log2(totdwidth/rdbits))) then
vdo := rdvx(x);
end if;
end loop;
end if;
-- Generate vdi from datain
for x in 0 to nrams-1 loop
vdi(x) := datain(wdbits-(x mod wdratio)*dbits-1 downto wdbits-(x mod wdratio)*dbits-dbits);
end loop;
-- Generate we2 from write/writebig
we2 := (others => writebig);
if wdbitsbig > wdbitssml then
for x in 0 to wdbitsbig/wdbitssml-1 loop
if write='1' and waddress(log2(wdbitsbig/wdbitssml)-1 downto 0) =
std_logic_vector(to_unsigned(x,log2(wdbitsbig/wdbitssml))) then
we2(x*wdbitssml/dbits to (x+1)*wdbitssml/dbits-1) := (others => '1');
end if;
end loop;
else
if write='1' then we2:=(others => '1'); end if;
end if;
-- Generate write-enable from we2
vwe := (others => '0');
if totdwidth > wdbitsbig then
for x in 0 to totdwidth/wdbitsbig-1 loop
if waddress(log2(totdwidth/wdbitssml)-1 downto log2(wdbitsbig/wdbitssml))=
std_logic_vector(to_unsigned(x,log2(totdwidth/wdbitsbig))) then
vwe(x*wdratio to (x+1)*wdratio-1) := we2;
end if;
end loop;
else
vwe := we2;
end if;
dataout <= vdo;
di <= vdi;
we <= vwe;
end process;
ramgen: for x in 0 to nrams-1 generate
r: syncram_2p generic map (tech,abits,dbits,sepclk,wrfst,testen)
port map (rclk => rclk,renable => renable,
raddress => raddress((rabits-1) downto (rabits-abits)),
dataout => do(x),wclk => wclk,write => we(x),
waddress => waddress((wabits-1) downto (wabits-abits)),
datain => di(x), testin => testin);
end generate;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/ambatest/ahbtbm.vhd | 1 | 14241 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbm
-- File: ahbtbm.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AHB Testbench master
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use work.ahbtbp.all;
entity ahbtbm is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in ahbtbm_ctrl_in_type;
ctrlo : out ahbtbm_ctrl_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end;
architecture rtl of ahbtbm is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
type reg_type is record
-- new /*
grant : std_logic;
grant2 : std_logic;
retry : std_logic_vector(1 downto 0);
read : std_logic; -- indicate
dbgl : integer;
use128 : integer;
hsize : std_logic_vector(2 downto 0);
ac : ahbtbm_access_array_type;
retryac : ahbtbm_access_type;
curac : ahbtbm_access_type;
haddr : std_logic_vector(31 downto 0); -- addr current access
hdata : std_logic_vector(31 downto 0); -- data currnet access
hdata128 : std_logic_vector(127 downto 0); -- data currnet access
hwrite : std_logic; -- write current access
hrdata : std_logic_vector(31 downto 0);
hrdata128 : std_logic_vector(127 downto 0);
status : ahbtbm_status_type;
dvalid : std_logic;
oldhtrans : std_logic_vector(1 downto 0);
-- new */
start : std_ulogic;
active : std_ulogic;
end record;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal r, rin : reg_type;
begin
ctrlo.rst <= rst;
ctrlo.clk <= clk;
comb : process(ahbmi, ctrli, rst, r)
-- new /*
variable v : reg_type;
variable update : std_logic;
variable hbusreq : std_ulogic; -- bus request
variable kblimit : std_logic; -- 1 kB limit indicator
-- new */
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(3 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(31 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(10 downto 0); -- next sequential address
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
-- new /*
v := r; update := '0'; hbusreq := '0';--v.retry := '0';
v.dvalid := '0'; xhirq := (others => '0');
hprot := "1110";
--v.hrdata := ahbmi.hrdata;
--v.hrdata128 := ahbmi.hrdata128;
v.hrdata := ahbmi.hrdata(31 downto 0);
v.hrdata128 := ahbread4word(ahbmi.hrdata);
-- pragma translate_off
if ahbmi.hready = '1' and ahbmi.hresp = HRESP_ERROR then
v.hrdata := (others => 'X');
v.hrdata128 := (others => 'X');
end if;
-- pragma translate_on
v.status.err := '0';
--v.oldhtrans := r.ac(1).htrans;
kblimit := '0';
-- Sample grant when hready
if ahbmi.hready = '1' then
v.grant := ahbmi.hgrant(hindex);
v.grant2 := r.grant;
v.oldhtrans := r.ac(1).htrans;
end if;
-- 1k limit
if (r.ac(0).htrans = HTRANS_SEQ
and (r.ac(0).haddr(10) xor r.ac(1).haddr(10)) = '1')
or (r.retryac.htrans = HTRANS_SEQ
and (r.retryac.haddr(10) xor r.ac(1).haddr(10)) = '1' and r.retry = "10") then
kblimit := '1';
end if;
-- Read in new access
--if ((ahbmi.hready = '1' and ahbmi.hresp = HRESP_OKAY and r.grant = '1')
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = '0' then
--if ahbmi.hready = '1' and ((ahbmi.hresp = HRESP_OKAY and r.grant = '1')
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
if ahbmi.hready = '0' and (ahbmi.hresp = HRESP_RETRY or ahbmi.hresp = HRESP_SPLIT) and r.grant2 = '1' then
if r.retry = "00" then
v.retryac := r.ac(1);
v.ac(1) := r.curac;
v.ac(1).htrans := HTRANS_IDLE;
v.ac(1).hburst := "000";
v.retry := "01";
elsif r.retry = "10" then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
end if;
elsif ahbmi.hready = '1' and ( r.grant = '1'
or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
-- elsif ahbmi.hready = '1' and (( r.grant = '1' and
-- (ahbmi.hresp = HRESP_OKAY or ahbmi.hresp = HRESP_ERROR))
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
v.ac(1) := r.ac(0); v.ac(0) := ctrli.ac;
v.curac := r.ac(1);
v.hdata := r.ac(1).hdata; v.haddr := r.ac(1).haddr;
v.hwrite := r.ac(1).hwrite; v.dbgl := r.ac(1).ctrl.dbgl;
v.use128 := r.ac(1).ctrl.use128;
if v.use128 = 0 then
v.hdata128 := r.ac(1).hdata & r.ac(1).hdata & r.ac(1).hdata & r.ac(1).hdata;
else
v.hdata128 := r.ac(1).hdata128;
end if;
v.hsize := r.ac(1).hsize;
v.read := (not r.ac(1).hwrite) and r.ac(1).htrans(1);
update := '1';
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
elsif ahbmi.hready = '0' and (ahbmi.hresp = HRESP_RETRY or ahbmi.hresp = HRESP_SPLIT) and r.grant2 = '1' then
if r.retry = "00" then
v.retryac := r.ac(1);
v.ac(1) := r.curac;
v.ac(1).htrans := HTRANS_IDLE;
v.ac(1).hburst := "000";
v.retry := "01";
elsif r.retry = "10" then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
end if;
elsif r.retry = "01" then
v.ac(1).htrans := HTRANS_NONSEQ;
v.ac(1).hburst := r.curac.hburst;
v.read := '0';
v.retry := "10";
elsif ahbmi.hready = '1' and r.grant = '1' and r.retry = "10" then
v.read := (not r.ac(1).hwrite) and r.ac(1).htrans(1);
--if ahbmi.hresp = HRESP_OKAY then
--if ahbmi.hresp = HRESP_OKAY or ahbmi.hresp = HRESP_ERROR then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
v.retry := "00";
--end if;
end if;
-- NONSEQ in retry
--if r.retry = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
-- NONSEQ if burst is interrupted
if r.grant = '0' and r.ac(1).htrans = HTRANS_SEQ then
v.ac(1).htrans := HTRANS_NONSEQ;
end if;
--if r.ac(1).htrans /= HTRANS_IDLE or r.ac(0).htrans /= HTRANS_IDLE then
-- hbusreq := '1';
--end if;
if r.ac(1).htrans = HTRANS_NONSEQ
or (r.ac(1).htrans = HTRANS_SEQ
and r.ac(0).htrans /= HTRANS_NONSEQ and kblimit = '0') then
hbusreq := '1';
end if;
--if r.grant = '0' then -- fix dvalid if grant deasserted *** ???
if r.grant = '0' and ahbmi.hready = '1' then
v.read := '0';
end if;
-- Check read data
if r.read = '1' and ahbmi.hresp = HRESP_OKAY and ahbmi.hready = '1' then
v.dvalid := '1';
if r.use128 = 0 then
--if r.hdata /= ahbmi.hrdata then
if r.hdata /= ahbmi.hrdata(31 downto 0) then
v.status.err := '1';
end if;
else
if r.hsize = "100" then
--if r.hdata128 /= ahbmi.hrdata128 then
if r.hdata128 /= ahbread4word(ahbmi.hrdata) then
v.status.err := '1';
end if;
else
--if r.hdata128(63 downto 0) /= ahbmi.hrdata128(63 downto 0) then
--if r.hdata128(63 downto 0) /= ahbmi.hrdata(63 downto 0) then
if r.hdata128(63 downto 0) /= ahbreaddword(ahbmi.hrdata) then
v.status.err := '1';
end if;
end if;
end if;
elsif r.read = '1' and ahbmi.hresp = HRESP_ERROR and ahbmi.hready = '1' then
v.status.err := '1';
end if;
-- new */
if rst = '0' then
v.ac(0).htrans := (others => '0');
v.ac(1).htrans := (others => '0');
v.retry := (others => '0');
v.read := '0';
v.ac(1).haddr := (others => '0');
v.ac(1).htrans := (others => '0');
v.ac(1).hwrite := '0';
v.ac(1).hsize := (others => '0');
v.ac(1).hburst := (others =>'0');
end if;
rin <= v;
ctrlo.update <= update;
ctrlo.status <= r.status;
ctrlo.hrdata <= r.hrdata;
ctrlo.hrdata128 <= r.hrdata128;
ctrlo.dvalid <= r.dvalid;
ahbmo.haddr <= r.ac(1).haddr;
ahbmo.htrans <= r.ac(1).htrans;
ahbmo.hbusreq <= hbusreq;
--ahbmo.hwdata <= r.hdata;
--ahbmo.hwdata128 <= r.hdata128;
ahbmo.hwdata <= ahbdrivedata(r.hdata128);
ahbmo.hconfig <= hconfig;
ahbmo.hlock <= '0';
ahbmo.hwrite <= r.ac(1).hwrite;
ahbmo.hsize <= r.ac(1).hsize;
ahbmo.hburst <= r.ac(1).hburst;
ahbmo.hprot <= r.ac(1).hprot;
ahbmo.hirq <= xhirq;
ahbmo.hindex <= hindex;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
-- pragma translate_off
if r.read = '1' and ahbmi.hready = '1' then --and r.oldhtrans /= HTRANS_IDLE then
if ahbmi.hresp = HRESP_OKAY then
if rin.status.err = '0' then
if r.dbgl >= 2 then
if r.use128 = 0 then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata(31 downto 0)));
else
if r.hsize = "100" then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata));
else print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbreaddword(ahbmi.hrdata))); end if;
end if;
end if;
else
if r.dbgl >= 1 then
if r.use128 = 0 then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata(31 downto 0))
& " != " & tost(r.hdata));
else
if r.hsize = "100" then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata)
& " != " & tost(r.hdata128));
else print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbreaddword(ahbmi.hrdata))
& " != " & tost(r.hdata128(63 downto 0)));
end if;
end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_RETRY then
if r.dbgl >= 3 then
print(ptime & "Read[" & tost(r.haddr) & "]: [RETRY]");
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Read[" & tost(r.haddr) & "]: [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_ERROR then
if r.dbgl >= 1 then
print(ptime & "Read[" & tost(r.haddr) & "]: [ERROR]");
end if;
end if;
end if;
if r.hwrite = '1' and ahbmi.hready = '1' and r.oldhtrans /= HTRANS_IDLE then
if ahbmi.hresp = HRESP_OKAY then
if r.dbgl >= 2 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata));
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128));
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0))); end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_RETRY then
if r.dbgl >= 3 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata) & " [RETRY]");
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128) & " [RETRY]");
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0)) & " [RETRY]"); end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata)
& " [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata)
& " [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_ERROR then
if r.dbgl >= 1 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata) & " [ERROR]");
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128) & " [ERROR]");
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0)) & " [ERROR]"); end if;
end if;
end if;
end if;
end if;
-- pragma translate_on
end if;
end process;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-de2-ep2c35/leon3mp.vhd | 1 | 22216 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.mypackage.all; --contains type
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic; --key[0]
clock_50 : in std_logic;
errorn : out std_logic; --ledr[0], error from LEON3 DSU
fl_addr : out std_logic_vector(21 downto 0);
fl_dq : inout std_logic_vector(7 downto 0);
dram_addr : out std_logic_vector(11 downto 0);
dram_ba_0 : out std_logic;
dram_ba_1 : out std_logic;
dram_dq : inout std_logic_vector(15 downto 0);
dram_clk : out std_logic;
dram_cke : out std_logic;
dram_cs_n : out std_logic;
dram_we_n : out std_logic; -- sdram write enable
dram_ras_n : out std_logic; -- sdram ras
dram_cas_n : out std_logic; -- sdram cas
dram_ldqm : out std_logic; -- sdram ldqm
dram_udqm : out std_logic; -- sdram udqm
uart_txd : out std_logic; -- DSU tx data
uart_rxd : in std_logic; -- DSU rx data
dsubre : in std_logic; --key[1], used to put processor in debug mode.
dsuact : out std_logic; --ledr[1]
fl_oe_n : out std_logic;
fl_we_n : out std_logic;
fl_rst_n : out std_logic;
fl_ce_n : out std_logic;
lcd_data : inout std_logic_vector(7 downto 0);
lcd_blon : out std_logic;
lcd_rw : out std_logic;
lcd_en : out std_logic;
lcd_rs : out std_logic;
lcd_on : out std_logic;
gpio_0 : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port 0
gpio_1 : inout std_logic_vector(CFG_GRGPIO2_WIDTH-1 downto 0); -- I/O port 1
ps2_clk : inout std_logic;
ps2_dat : inout std_logic;
vga_clk : out std_ulogic;
vga_blank : out std_ulogic;
vga_sync : out std_ulogic;
vga_hs : out std_ulogic;
vga_vs : out std_ulogic;
vga_r : out std_logic_vector(9 downto 0);
vga_g : out std_logic_vector(9 downto 0);
vga_b : out std_logic_vector(9 downto 0);
sw : in std_logic_vector(0 to 2) := "000"
);
end;
architecture rtl of leon3mp is
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
--AMBA bus standard interface signals--
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl, lclk, rst : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal stati : ahbstat_in_type;
signal gpti : gptimer_in_type;
signal gpioi_0, gpioi_1 : gpio_in_type;
signal gpioo_0, gpioo_1 : gpio_out_type;
signal dsubren : std_logic;
signal tck, tms, tdi, tdo : std_logic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal video_clk, clk40 : std_logic;
signal lcdo : lcd_out_type;
signal lcdi : lcd_in_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz, used in clkgen
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz (current 50Mhz)
constant IOAEN : integer := 1;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clock_50, lclk);
clkgen0 : entity work.clkgen_de2
generic map (clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV,
clk_freq => BOARD_FREQ, sdramen => CFG_SDCTRL)
port map (inclk0 => lclk, c0 => clkm, c0_2x => clk40, e0 => sdclkl,
locked => cgo.clklock);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (dram_clk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
rst0 : rstgen -- reset generator (reset is active LOW)
port map (rst, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
devid => ALTERA_DE2, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
----- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
--ledr[0] lit when leon 3 debugvector signals error
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit (slave)
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsubren);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); --ledr[1] is lit in debug mode.
dsui.break <= not dsubren;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; --no timer freeze, no light.
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= uart_rxd when sw(0) = '0' else '1';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= '0'; memi.bwidth <= "00";
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => 0, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL, iomask => 0,
sdbits => 32 + 32*CFG_MCTRL_SD64, rammask => 0 ,pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 22, tech => padtech)
port map (fl_addr, memo.address(21 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (fl_ce_n, memo.romsn(0)); --PROM chip select
oen_pad : outpad generic map (tech => padtech)
port map (fl_oe_n, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (fl_we_n, memo.writen); --write strobe
fl_rst_pad : outpad generic map (tech => padtech)
port map (fl_rst_n, rstn); --reset flash with common reset signal
data_pad : iopadvv generic map (tech => padtech, width => 8, oepol => OEPOL)
port map (fl_dq, memo.data(31 downto 24), memo.vbdrive(31 downto 24), memi.data(31 downto 24));
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111";
end generate;
sdctrl0 : if CFG_SDCTRL = 1 generate -- 16-bit SDRAM controller
sdc : sdctrl16 generic map (hindex => 3, haddr => 16#400#, hmask => 16#FF8#, -- hmask => 16#C00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => 0,
sdbits => 16, pageburst => 2)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 12, tech => padtech)
port map (dram_addr, sdo2.address(13 downto 2));
ba0_pad : outpad generic map (tech => padtech)
port map (dram_ba_0, sdo2.address(15));
ba1_pad : outpad generic map (tech => padtech)
port map (dram_ba_1, sdo2.address(16));
sd_pad : iopadvv generic map (width => 16, tech => padtech, oepol => OEPOL)
port map (dram_dq(15 downto 0), sdo2.data(15 downto 0), sdo2.vbdrive(15 downto 0), sdi.data(15 downto 0));
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, sdo2.sdcke(0));
sdwen_pad : outpad generic map (tech => padtech)
port map (dram_we_n, sdo2.sdwen);
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, sdo2.sdcsn(0));
sdras_pad : outpad generic map (tech => padtech)
port map (dram_ras_n, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (dram_cas_n, sdo2.casn);
sdldqm_pad : outpad generic map (tech => padtech)
port map (dram_ldqm, sdo2.dqm(0) );
sdudqm_pad : outpad generic map (tech => padtech)
port map (dram_udqm, sdo2.dqm(1));
end generate;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (fl_ce_n, gnd(0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
lcd : apblcd
generic map(pindex => 4, paddr => 4, pmask => 16#fff#, oepol => OEPOL, tas => 1, epw => 12)
port map(rstn, clkm, apbi, apbo(4), lcdo, lcdi);
rs_pad : outpad generic map (tech => padtech)
port map (lcd_rs, lcdo.rs);
rw_pad : outpad generic map (tech => padtech)
port map (lcd_rw, lcdo.rw);
e_pad : outpad generic map (tech => padtech)
port map (lcd_en, lcdo.e);
db_pad : iopadv generic map (width => 8, tech => padtech, oepol => OEPOL)
port map (lcd_data, lcdo.db, lcdo.db_oe, lcdi.db);
blon_pad : outpad generic map (tech => padtech)
port map (lcd_blon, gnd(0));
on_pad : outpad generic map (tech => padtech)
port map (lcd_on, vcc(0));
----------------------------------------------------------------------------------------
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, flow => 0,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
u1i.rxd <= '1' when sw(0) = '0' else uart_rxd;
end generate;
uart_txd <= duo.txd when sw(0) = '0' else u1o.txd;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate;
apbo(2) <= apb_none;
end generate;
--Timer unit, generates interrupts when a timer underflow.
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO0 unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi_0, gpioo_0);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio_0(i), gpioo_0.dout(i), gpioo_0.oen(i), gpioi_0.din(i));
end generate;
end generate;
nogpio0: if CFG_GRGPIO_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
gpio1 : if CFG_GRGPIO2_ENABLE /= 0 generate -- GR GPIO1 unit
grgpio1: grgpio
generic map( pindex => 10, paddr => 10, imask => CFG_GRGPIO2_IMASK, nbits => CFG_GRGPIO2_WIDTH)
port map( rstn, clkm, apbi, apbo(10), gpioi_1, gpioo_1);
pio_pads : for i in 0 to CFG_GRGPIO2_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio_1(i), gpioo_1.dout(i), gpioo_1.oen(i), gpioi_1.din(i));
end generate;
end generate;
nogpio1: if CFG_GRGPIO2_ENABLE = 0 generate apbo(10) <= apb_none; end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(1 to NAHBSLV-1) <= (others => '0');
stati.cerror(0) <= memo.ce; --connect as many fault tolerans units as specified by nftslv generic.
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_dat, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clk40, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vga_clk, video_clk);
video_clk <= not clk40;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, --1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 8)
port map(rstn, clkm, clk40, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
video_clk <= not clk40;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vga_clk, video_clk);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
video_clk <= not clkm;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vga_clk, video_clk);
end generate;
blank_pad : outpad generic map (tech => padtech)
port map (vga_blank, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vga_sync, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vga_vs, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vga_hs, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vga_r(9 downto 2), vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vga_g(9 downto 2), vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vga_b(9 downto 2), vgao.video_out_b);
vga_r(1 downto 0) <= "00";
vga_g(1 downto 0) <= "00";
vga_b(1 downto 0) <= "00";
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 7, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(7));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera DE2-EP2C35 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-vc707/config.vhd | 1 | 11156 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex7;
constant CFG_MEMTECH : integer := virtex7;
constant CFG_PADTECH : integer := virtex7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex7;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (8);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 1 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 3;
constant CFG_ILOCK : integer := 1;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 3;
constant CFG_DLOCK : integer := 1;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 0;
constant CFG_MIG_RANKS : integer := 1;
constant CFG_MIG_COLBITS : integer := 10;
constant CFG_MIG_ROWBITS : integer := 13;
constant CFG_MIG_BANKBITS: integer := 2;
constant CFG_MIG_HMASK : integer := 16#F00#;
-- Xilinx MIG Series 7
constant CFG_MIG_SERIES7 : integer := 1;
constant CFG_MIG_SERIES7_MODEL : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- USB Host Controller
constant CFG_GRUSBHC : integer := 0;
constant CFG_GRUSBHC_NPORTS : integer := 1;
constant CFG_GRUSBHC_EHC : integer := 0;
constant CFG_GRUSBHC_UHC : integer := 0;
constant CFG_GRUSBHC_NCC : integer := 1;
constant CFG_GRUSBHC_NPCC : integer := 1;
constant CFG_GRUSBHC_PRR : integer := 0;
constant CFG_GRUSBHC_PR1 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1/4);
constant CFG_GRUSBHC_PR2 : integer := 0*2**26 + 0*2**22 + 0*2**18 + 0*2**14 + 0*2**10 + 0*2**6 + 0*2**2 + (1 mod 4);
constant CFG_GRUSBHC_ENDIAN : integer := 1;
constant CFG_GRUSBHC_BEREGS : integer := 0;
constant CFG_GRUSBHC_BEDESC : integer := 0;
constant CFG_GRUSBHC_BLO : integer := 3;
constant CFG_GRUSBHC_BWRD : integer := 16;
constant CFG_GRUSBHC_UTM : integer := 2;
constant CFG_GRUSBHC_VBUSCONF : integer := 1;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := 1;
constant CFG_GRUSBDC_NEPO : integer := 1;
constant CFG_GRUSBDC_I0 : integer := 1024;
constant CFG_GRUSBDC_I1 : integer := 1024;
constant CFG_GRUSBDC_I2 : integer := 1024;
constant CFG_GRUSBDC_I3 : integer := 1024;
constant CFG_GRUSBDC_I4 : integer := 1024;
constant CFG_GRUSBDC_I5 : integer := 1024;
constant CFG_GRUSBDC_I6 : integer := 1024;
constant CFG_GRUSBDC_I7 : integer := 1024;
constant CFG_GRUSBDC_I8 : integer := 1024;
constant CFG_GRUSBDC_I9 : integer := 1024;
constant CFG_GRUSBDC_I10 : integer := 1024;
constant CFG_GRUSBDC_I11 : integer := 1024;
constant CFG_GRUSBDC_I12 : integer := 1024;
constant CFG_GRUSBDC_I13 : integer := 1024;
constant CFG_GRUSBDC_I14 : integer := 1024;
constant CFG_GRUSBDC_I15 : integer := 1024;
constant CFG_GRUSBDC_O0 : integer := 1024;
constant CFG_GRUSBDC_O1 : integer := 1024;
constant CFG_GRUSBDC_O2 : integer := 1024;
constant CFG_GRUSBDC_O3 : integer := 1024;
constant CFG_GRUSBDC_O4 : integer := 1024;
constant CFG_GRUSBDC_O5 : integer := 1024;
constant CFG_GRUSBDC_O6 : integer := 1024;
constant CFG_GRUSBDC_O7 : integer := 1024;
constant CFG_GRUSBDC_O8 : integer := 1024;
constant CFG_GRUSBDC_O9 : integer := 1024;
constant CFG_GRUSBDC_O10 : integer := 1024;
constant CFG_GRUSBDC_O11 : integer := 1024;
constant CFG_GRUSBDC_O12 : integer := 1024;
constant CFG_GRUSBDC_O13 : integer := 1024;
constant CFG_GRUSBDC_O14 : integer := 1024;
constant CFG_GRUSBDC_O15 : integer := 1024;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 32;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (1);
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-nuhorizons-3s1500/nuhosp3.vhd | 3 | 4925 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: nuhosp3
-- File: nuhosp3.vhd
-- Author: Jiri Gaisler - Gaisler Reserch
-- Description:
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
entity nuhosp3 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
ioaddr : integer := 16#200#;
iomask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
nui : in nuhosp3_in_type;
nuo : out nuhosp3_out_type
);
end;
architecture rtl of nuhosp3 is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_NUHOSP3, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
others => zero32);
type fstate is (idle, read1, read2, leadout);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
haddr : std_logic_vector(31 downto 0);
hmbsel : std_logic_vector(0 to 1);
ws : std_logic_vector(2 downto 0);
flash_a : std_logic_vector(20 downto 0);
flash_wd : std_logic_vector(15 downto 0);
flash_oen : std_ulogic;
flash_wen : std_ulogic;
flash_cen : std_ulogic;
flash_rd : std_logic_vector(31 downto 0);
flash_state : fstate;
smsc_wd : std_logic_vector(31 downto 0);
smsc_ncs : std_ulogic;
end record;
constant romws : std_logic_vector(2 downto 0) := "011";
signal r, c : reg_type;
begin
comb : process (ahbsi, r, rst, nui)
variable v : reg_type;
begin
v := r;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.hready := not v.hsel;
v.hwrite := ahbsi.hwrite;
v.haddr := ahbsi.haddr;
v.hmbsel := ahbsi.hmbsel(0 to 1);
end if;
v.flash_rd(15 downto 0) := nui.flash_d;
case r.flash_state is
when idle =>
v.flash_wen := '1'; v.flash_oen := '1';
if (r.hsel = '1') then
v.flash_cen := not r.hmbsel(0);
v.smsc_ncs := not r.hmbsel(1);
v.flash_state := read1;
v.flash_oen := r.hwrite; v.flash_a := r.haddr(20 downto 0);
v.flash_wd := ahbsi.hwdata(31 downto 16);
v.smsc_wd := ahbsi.hwdata(31 downto 0);
end if;
when read1 =>
v.flash_state := read2; v.ws := romws; v.flash_wen := not r.hwrite;
v.flash_rd(31 downto 16) := r.flash_rd(15 downto 0);
when read2 =>
v.ws := r.ws - 1;
if r.ws = "000" then
if (r.flash_a(0) = '0') and (r.hwrite = '0') then
v.flash_state := read1; v.flash_a(0) := '1';
else
v.hready := '1'; v.flash_state := leadout; v.flash_oen := '1';
v.flash_wen := '1'; v.flash_cen := '1'; v.smsc_ncs := '1';
end if;
end if;
when leadout =>
v.flash_state := idle;
end case;
if rst = '0' then v.hready := '1'; v.flash_state := idle; end if;
c <= v;
nuo.flash_oen <= r.flash_oen;
nuo.flash_wen <= r.flash_wen;
nuo.flash_cen <= r.flash_cen;
nuo.flash_a <= r.flash_a;
nuo.flash_d <= r.flash_wd;
nuo.smsc_ncs <= r.smsc_ncs;
nuo.smsc_nbe <= (others => r.flash_wen);
nuo.smsc_ben <= r.flash_wen;
nuo.smsc_data <= r.smsc_wd;
nuo.smsc_addr <= r.flash_a(14 downto 0);
ahbso.hready <= r.hready;
ahbso.hrdata <= r.flash_rd;
end process;
nuo.smsc_resetn <= rst;
nuo.smsc_nwr <= '1';
nuo.smsc_nrd <= '1';
nuo.smsc_wnr <= '1';
nuo.smsc_cycle <= '1';
nuo.smsc_aen <= '1';
nuo.smsc_lclk <= '1';
nuo.smsc_rdyrtn <= '1';
nuo.smsc_nads <= '0';
nuo.lcd_en <= '0';
nuo.lcd_ben <= '1';
nuo.lcd_backl <= '1';
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk, rst)
begin
if rising_edge(clk ) then r <= c; end if;
if rst = '0' then
r.flash_cen <= '1'; r.smsc_ncs <= '1'; r.flash_wen <= '1';
end if;
end process;
-- pragma translate_off
bootmsg : report_design
generic map (msg1 => "huhosp3" & tost(hindex) &
": Nuhorizons Spartan3 board interface",
fabtech => tech_table(fabtech), memtech => tech_table(memtech));
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/boards/terasic-de4/sgmii2gmii.vhd | 2 | 17900 | -- megafunction wizard: %Triple-Speed Ethernet v13.1%
-- GENERATION: XML
-- sgmii2gmii.vhd
-- Generated using ACDS version 13.1 162 at 2013.11.29.14:56:05
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sgmii2gmii is
port (
ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
clk : in std_logic := '0'; -- control_port_clock_connection.clk
reset : in std_logic := '0'; -- reset_connection.reset
address : in std_logic_vector(4 downto 0) := (others => '0'); -- control_port.address
readdata : out std_logic_vector(15 downto 0); -- .readdata
read : in std_logic := '0'; -- .read
writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
waitrequest : out std_logic; -- .waitrequest
tx_clk : out std_logic; -- pcs_transmit_clock_connection.clk
rx_clk : out std_logic; -- pcs_receive_clock_connection.clk
reset_tx_clk : in std_logic := '0'; -- pcs_transmit_reset_connection.reset
reset_rx_clk : in std_logic := '0'; -- pcs_receive_reset_connection.reset
gmii_rx_dv : out std_logic; -- gmii_connection.gmii_rx_dv
gmii_rx_d : out std_logic_vector(7 downto 0); -- .gmii_rx_d
gmii_rx_err : out std_logic; -- .gmii_rx_err
gmii_tx_en : in std_logic := '0'; -- .gmii_tx_en
gmii_tx_d : in std_logic_vector(7 downto 0) := (others => '0'); -- .gmii_tx_d
gmii_tx_err : in std_logic := '0'; -- .gmii_tx_err
tx_clkena : out std_logic; -- clock_enable_connection.tx_clkena
rx_clkena : out std_logic; -- .rx_clkena
mii_rx_dv : out std_logic; -- mii_connection.mii_rx_dv
mii_rx_d : out std_logic_vector(3 downto 0); -- .mii_rx_d
mii_rx_err : out std_logic; -- .mii_rx_err
mii_tx_en : in std_logic := '0'; -- .mii_tx_en
mii_tx_d : in std_logic_vector(3 downto 0) := (others => '0'); -- .mii_tx_d
mii_tx_err : in std_logic := '0'; -- .mii_tx_err
mii_col : out std_logic; -- .mii_col
mii_crs : out std_logic; -- .mii_crs
set_10 : out std_logic; -- sgmii_status_connection.set_10
set_1000 : out std_logic; -- .set_1000
set_100 : out std_logic; -- .set_100
hd_ena : out std_logic; -- .hd_ena
led_crs : out std_logic; -- status_led_connection.crs
led_link : out std_logic; -- .link
led_col : out std_logic; -- .col
led_an : out std_logic; -- .an
led_char_err : out std_logic; -- .char_err
led_disp_err : out std_logic; -- .disp_err
rx_recovclkout : out std_logic; -- serdes_control_connection.export
txp : out std_logic; -- serial_connection.txp
rxp : in std_logic := '0' -- .rxp
);
end entity sgmii2gmii;
architecture rtl of sgmii2gmii is
component sgmii2gmii_0002 is
port (
ref_clk : in std_logic := 'X'; -- clk
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(15 downto 0); -- readdata
read : in std_logic := 'X'; -- read
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
waitrequest : out std_logic; -- waitrequest
tx_clk : out std_logic; -- clk
rx_clk : out std_logic; -- clk
reset_tx_clk : in std_logic := 'X'; -- reset
reset_rx_clk : in std_logic := 'X'; -- reset
gmii_rx_dv : out std_logic; -- gmii_rx_dv
gmii_rx_d : out std_logic_vector(7 downto 0); -- gmii_rx_d
gmii_rx_err : out std_logic; -- gmii_rx_err
gmii_tx_en : in std_logic := 'X'; -- gmii_tx_en
gmii_tx_d : in std_logic_vector(7 downto 0) := (others => 'X'); -- gmii_tx_d
gmii_tx_err : in std_logic := 'X'; -- gmii_tx_err
tx_clkena : out std_logic; -- tx_clkena
rx_clkena : out std_logic; -- rx_clkena
mii_rx_dv : out std_logic; -- mii_rx_dv
mii_rx_d : out std_logic_vector(3 downto 0); -- mii_rx_d
mii_rx_err : out std_logic; -- mii_rx_err
mii_tx_en : in std_logic := 'X'; -- mii_tx_en
mii_tx_d : in std_logic_vector(3 downto 0) := (others => 'X'); -- mii_tx_d
mii_tx_err : in std_logic := 'X'; -- mii_tx_err
mii_col : out std_logic; -- mii_col
mii_crs : out std_logic; -- mii_crs
set_10 : out std_logic; -- set_10
set_1000 : out std_logic; -- set_1000
set_100 : out std_logic; -- set_100
hd_ena : out std_logic; -- hd_ena
led_crs : out std_logic; -- crs
led_link : out std_logic; -- link
led_col : out std_logic; -- col
led_an : out std_logic; -- an
led_char_err : out std_logic; -- char_err
led_disp_err : out std_logic; -- disp_err
rx_recovclkout : out std_logic; -- export
txp : out std_logic; -- txp
rxp : in std_logic := 'X' -- rxp
);
end component sgmii2gmii_0002;
begin
sgmii2gmii_inst : component sgmii2gmii_0002
port map (
ref_clk => ref_clk, -- pcs_ref_clk_clock_connection.clk
clk => clk, -- control_port_clock_connection.clk
reset => reset, -- reset_connection.reset
address => address, -- control_port.address
readdata => readdata, -- .readdata
read => read, -- .read
writedata => writedata, -- .writedata
write => write, -- .write
waitrequest => waitrequest, -- .waitrequest
tx_clk => tx_clk, -- pcs_transmit_clock_connection.clk
rx_clk => rx_clk, -- pcs_receive_clock_connection.clk
reset_tx_clk => reset_tx_clk, -- pcs_transmit_reset_connection.reset
reset_rx_clk => reset_rx_clk, -- pcs_receive_reset_connection.reset
gmii_rx_dv => gmii_rx_dv, -- gmii_connection.gmii_rx_dv
gmii_rx_d => gmii_rx_d, -- .gmii_rx_d
gmii_rx_err => gmii_rx_err, -- .gmii_rx_err
gmii_tx_en => gmii_tx_en, -- .gmii_tx_en
gmii_tx_d => gmii_tx_d, -- .gmii_tx_d
gmii_tx_err => gmii_tx_err, -- .gmii_tx_err
tx_clkena => tx_clkena, -- clock_enable_connection.tx_clkena
rx_clkena => rx_clkena, -- .rx_clkena
mii_rx_dv => mii_rx_dv, -- mii_connection.mii_rx_dv
mii_rx_d => mii_rx_d, -- .mii_rx_d
mii_rx_err => mii_rx_err, -- .mii_rx_err
mii_tx_en => mii_tx_en, -- .mii_tx_en
mii_tx_d => mii_tx_d, -- .mii_tx_d
mii_tx_err => mii_tx_err, -- .mii_tx_err
mii_col => mii_col, -- .mii_col
mii_crs => mii_crs, -- .mii_crs
set_10 => set_10, -- sgmii_status_connection.set_10
set_1000 => set_1000, -- .set_1000
set_100 => set_100, -- .set_100
hd_ena => hd_ena, -- .hd_ena
led_crs => led_crs, -- status_led_connection.crs
led_link => led_link, -- .link
led_col => led_col, -- .col
led_an => led_an, -- .an
led_char_err => led_char_err, -- .char_err
led_disp_err => led_disp_err, -- .disp_err
rx_recovclkout => rx_recovclkout, -- serdes_control_connection.export
txp => txp, -- serial_connection.txp
rxp => rxp -- .rxp
);
end architecture rtl; -- of sgmii2gmii
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2013 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_eth_tse" version="13.1" >
-- Retrieval info: <generic name="deviceFamilyName" value="Stratix IV" />
-- Retrieval info: <generic name="core_variation" value="PCS_ONLY" />
-- Retrieval info: <generic name="ifGMII" value="MII_GMII" />
-- Retrieval info: <generic name="enable_use_internal_fifo" value="true" />
-- Retrieval info: <generic name="max_channels" value="1" />
-- Retrieval info: <generic name="use_misc_ports" value="true" />
-- Retrieval info: <generic name="transceiver_type" value="LVDS_IO" />
-- Retrieval info: <generic name="enable_hd_logic" value="true" />
-- Retrieval info: <generic name="enable_gmii_loopback" value="false" />
-- Retrieval info: <generic name="enable_sup_addr" value="false" />
-- Retrieval info: <generic name="stat_cnt_ena" value="true" />
-- Retrieval info: <generic name="ext_stat_cnt_ena" value="false" />
-- Retrieval info: <generic name="ena_hash" value="false" />
-- Retrieval info: <generic name="enable_shift16" value="true" />
-- Retrieval info: <generic name="enable_mac_flow_ctrl" value="false" />
-- Retrieval info: <generic name="enable_mac_vlan" value="false" />
-- Retrieval info: <generic name="enable_magic_detect" value="true" />
-- Retrieval info: <generic name="useMDIO" value="false" />
-- Retrieval info: <generic name="mdio_clk_div" value="40" />
-- Retrieval info: <generic name="enable_ena" value="32" />
-- Retrieval info: <generic name="eg_addr" value="11" />
-- Retrieval info: <generic name="ing_addr" value="11" />
-- Retrieval info: <generic name="phy_identifier" value="0" />
-- Retrieval info: <generic name="enable_sgmii" value="true" />
-- Retrieval info: <generic name="export_pwrdn" value="false" />
-- Retrieval info: <generic name="enable_alt_reconfig" value="false" />
-- Retrieval info: <generic name="starting_channel_number" value="0" />
-- Retrieval info: <generic name="phyip_pll_type" value="CMU" />
-- Retrieval info: <generic name="phyip_en_synce_support" value="false" />
-- Retrieval info: <generic name="phyip_pma_bonding_mode" value="x1" />
-- Retrieval info: <generic name="nf_phyip_rcfg_enable" value="false" />
-- Retrieval info: <generic name="enable_timestamping" value="false" />
-- Retrieval info: <generic name="enable_ptp_1step" value="false" />
-- Retrieval info: <generic name="tstamp_fp_width" value="4" />
-- Retrieval info: <generic name="AUTO_DEVICE" value="Unknown" />
-- Retrieval info: </instance>
-- IPFS_FILES : sgmii2gmii.vho
-- RELATED_FILES: sgmii2gmii.vhd, sgmii2gmii_0002.v, altera_eth_tse_pcs_pma_lvds.v, altera_tse_align_sync.v, altera_tse_dec10b8b.v, altera_tse_dec_func.v, altera_tse_enc8b10b.v, altera_tse_top_autoneg.v, altera_tse_carrier_sense.v, altera_tse_clk_gen.v, altera_tse_sgmii_clk_div.v, altera_tse_sgmii_clk_enable.v, altera_tse_rx_encapsulation.v, altera_tse_tx_encapsulation.v, altera_tse_rx_encapsulation_strx_gx.v, altera_tse_pcs_control.v, altera_tse_pcs_host_control.v, altera_tse_mdio_reg.v, altera_tse_mii_rx_if_pcs.v, altera_tse_mii_tx_if_pcs.v, altera_tse_rx_sync.v, altera_tse_sgmii_clk_cntl.v, altera_tse_colision_detect.v, altera_tse_rx_converter.v, altera_tse_rx_fifo_rd.v, altera_tse_top_rx_converter.v, altera_tse_top_sgmii.v, altera_tse_top_sgmii_strx_gx.v, altera_tse_top_tx_converter.v, altera_tse_tx_converter.v, altera_tse_top_1000_base_x.v, altera_tse_top_1000_base_x_strx_gx.v, altera_tse_top_pcs.v, altera_tse_top_pcs_strx_gx.v, altera_tse_top_rx.v, altera_tse_top_tx.v, altera_tse_lvds_reset_sequencer.v, altera_tse_lvds_reverse_loopback.v, altera_tse_pma_lvds_rx_av.v, altera_tse_pma_lvds_rx.v, altera_tse_pma_lvds_tx.v, altera_tse_false_path_marker.v, altera_tse_reset_synchronizer.v, altera_tse_clock_crosser.v, altera_tse_a_fifo_13.v, altera_tse_a_fifo_24.v, altera_tse_a_fifo_34.v, altera_tse_a_fifo_opt_1246.v, altera_tse_a_fifo_opt_14_44.v, altera_tse_a_fifo_opt_36_10.v, altera_tse_gray_cnt.v, altera_tse_sdpm_altsyncram.v, altera_tse_altsyncram_dpm_fifo.v, altera_tse_bin_cnt.v, altera_tse_ph_calculator.sv, altera_tse_sdpm_gen.v, altera_tse_dc_fifo.v
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/inferred/lpddr2_phy_inferred.vhd | 1 | 9958 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: generic_lpddr2phy_wo_pads
-- File: lpddr2_phy_inferred.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic LPDDR2/LPDDR3 PHY (simulation only), without pads
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clkswitch is
port (clk1,clk2,sel: in std_ulogic;
clko: out std_ulogic);
end;
architecture sim of clkswitch is
signal c1en,c2en: std_ulogic := '0';
begin
clko <= (clk1 and c1en) or (clk2 and c2en);
p1: process(clk1)
begin
if falling_edge(clk1) then
c1en <= (not sel) and (not c2en);
end if;
end process;
p2: process(clk2)
begin
if falling_edge(clk2) then
c2en <= (sel) and (not c1en);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity generic_lpddr2phy_wo_pads is
generic (
tech : integer := 0;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0;
oepol: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- clkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture beh of generic_lpddr2phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
signal extclkb,extclkn,extclk,intclkb,intclkn,intclk: std_ulogic;
signal gextclk,gextclkn: std_ulogic;
signal clkoutb,clkoutn: std_ulogic;
signal llockb,llockn,llock: std_ulogic;
signal dqsout,dqsoen,dqsand,dqoen,dqsien,dqsiend: std_ulogic;
signal dqsin,dqsind: std_logic_vector(dbits/8-1 downto 0);
signal tmeas: time := 0 ns;
signal tdqsck: time := 0 ns;
begin
bootpll: sim_pll
generic map (clkmul => clkratio,
clkdiv1 => 1, clkphase1 => 180,
clkdiv2 => 1, clkphase2 => 90,
clkdiv3 => clkratio, clkphase3 => 0)
port map (i => clkin2, o1 => extclkb, o2 => intclkb,
o3 => clkoutb, lock => llockb, rst => rst);
pll0: sim_pll
generic map (clkmul => clkratio,
clkdiv1 => 1, clkphase1 => 180,
clkdiv2 => 1, clkphase2 => 90,
clkdiv3 => clkratio, clkphase3 => 0)
port map (i => clkin, o1 => extclkn, o2 => intclkn,
o3 => clkoutn, lock => llockn, rst => rst);
llock <= llockb and llockn;
lock <= llock;
clkout2 <= '0';
cs0: entity work.clkswitch port map (extclkn, extclkb, boot, extclk);
cs1: entity work.clkswitch port map (intclkn, intclkb, boot, intclk);
cs2: entity work.clkswitch port map (clkoutn, clkoutb, boot, clkout);
gextclk <= extclk and (llock and not ckstop);
gextclkn <= not gextclk;
dqsout <= gextclk and dqsand;
ddr_dqs_out <= (others => dqsout);
ddr_dqs_oen <= (others => dqsoen);
ddr_dq_oen <= (others => dqoen);
ddr_clk <= (others => gextclk);
ddr_clkb <= (others => gextclkn);
dqsiend <= dqsien after tdqsck;
dqsin <= ddr_dqs_in when dqsiend='1' else (others => '0');
dqsind <= dqsin after tmeas * 0.25;
wrreq <= wrpend(1+clkratio-1-1 downto 1-1);
outregs: process(clkoutret,intclk,dqsind)
variable phase: integer;
variable wrpend_samp: std_logic_vector(1 downto 0);
variable rdpend_prev: std_ulogic;
type intarr is array(natural range <>) of integer;
variable dl: intarr(dbits/8-1 downto 0) := (others => 0);
variable dqq: std_logic_vector(3*dbits*2-1 downto 0);
variable lt: time := 0 ns;
variable dqsind_prev: std_logic_vector(dbits/8-1 downto 0) := (others => '0');
variable i: integer;
begin
if dqsind /= dqsind_prev then
for x in dqsind'range loop
if (dqsind(x)='1' and dqsind_prev(x)='0') or (dqsind(x)='0' and dqsind_prev(x)='1') then
for y in 5 downto 1 loop
dqq(x*8+dbits*y+7 downto x*8+dbits*y) := dqq(x*8+dbits*(y-1)+7 downto x*8+dbits*(y-1));
end loop;
dqq(x*8+7 downto x*8) := ddr_dq_in(x*8+7 downto x*8);
if dqsind(x)='0' then
dl(x) := dl(x)+1;
end if;
end if;
end loop;
dqsind_prev := dqsind;
end if;
if rising_edge(clkoutret) then
dqsien <= rdpend(1);
phase := 0;
wrpend_samp := wrpend(1 downto 0);
rdvalid <= (others => '0');
dqin <= (others => '-');
i := clkratio;
for x in dl'range loop
if dl(x)<i then i:=dl(x); end if;
end loop;
for x in dl'range loop
dl(x) := dl(x)-i;
end loop;
for x in 2*i-1 downto 0 loop
for y in dbits/8-1 downto 0 loop
dqin(x*dbits+y*8+7 downto x*dbits+y*8) <= dqq((x+dl(y))*dbits+y*8+7 downto (x+dl(y))*dbits+y*8);
end loop;
end loop;
rdvalid(i-1 downto 0) <= (others => '1');
end if;
if falling_edge(clkoutret) then
dqsoen <= not (wrpend_samp(1) or wrpend_samp(0));
rdpend_prev := rdpend(0);
end if;
if rising_edge(intclk) then
dqsand <= wrpend_samp(0);
dqoen <= not wrpend_samp(0);
tmeas <= now - lt;
lt := now;
end if;
if rising_edge(intclk) or falling_edge(intclk) then
-- DDR outputs
ddr_ca <= ca(ca'high-10*phase downto ca'high-10*phase-9);
ddr_dm <= dm(dm'high-dbits/8*phase downto dm'high+1-dbits/8*(phase+1));
ddr_dq_out <= dqout(dqout'high-dbits*phase downto dqout'high+1-dbits*(phase+1));
if rising_edge(intclk) then
-- SDR outputs
ddr_cke <= cke(cke'high-ncs*(phase/2) downto cke'high+1-ncs*(phase/2+1));
ddr_csb <= csn(csn'high-ncs*(phase/2) downto csn'high+1-ncs*(phase/2+1));
end if;
if phase < 2*clkratio-1 then
phase := phase+1;
end if;
end if;
end process;
dqsckproc: process
variable t: time;
begin
wait until dqsien='1';
loop
t := now;
if dqsin/=(dqsin'range => '0') then
wait until dqsin=(dqsin'range => '0');
end if;
wait until dqsin=(dqsin'range => '1');
tdqsck <= tdqsck + (now-t)-0.25*tmeas;
wait until dqsin=(dqsin'range => 'X') and dqsien='1';
end loop;
end process;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/spi/spictrl.vhd | 1 | 11134 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spictrl
-- File: spictrl.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Wrapper for SPICTRL core
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.spi.all;
entity spictrl is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0; -- APB address
pmask : integer := 16#fff#; -- APB mask
pirq : integer := 0; -- interrupt index
-- SPI controller configuration
fdepth : integer range 1 to 7 := 1; -- FIFO depth is 2^fdepth
slvselen : integer range 0 to 1 := 0; -- Slave select register enable
slvselsz : integer range 1 to 32 := 1; -- Number of slave select signals
oepol : integer range 0 to 1 := 0; -- Output enable polarity
odmode : integer range 0 to 1 := 0; -- Support open drain mode, only
-- set if pads are i/o or od pads.
automode : integer range 0 to 1 := 0; -- Enable automated transfer mode
acntbits : integer range 1 to 32 := 32; -- # Bits in am period counter
aslvsel : integer range 0 to 1 := 0; -- Automatic slave select
twen : integer range 0 to 1 := 1; -- Enable three wire mode
maxwlen : integer range 0 to 15 := 0; -- Maximum word length
netlist : integer := 0; -- Use netlist (tech)
syncram : integer range 0 to 1 := 1; -- Use SYNCRAM for buffers
memtech : integer := 0; -- Memory technology
ft : integer range 0 to 2 := 0; -- Fault-Tolerance
scantest : integer range 0 to 1 := 0; -- Scan test support
syncrst : integer range 0 to 1 := 0; -- Use only sync reset
automask0 : integer := 0; -- Mask 0 for automated transfers
automask1 : integer := 0; -- Mask 1 for automated transfers
automask2 : integer := 0; -- Mask 2 for automated transfers
automask3 : integer := 0; -- Mask 3 for automated transfers
ignore : integer range 0 to 1 := 0 -- Ignore samples
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
end entity spictrl;
architecture rtl of spictrl is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant SPICTRL_REV : integer := 5;
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPICTRL, 0, SPICTRL_REV, pirq),
1 => apb_iobar(paddr, pmask));
-----------------------------------------------------------------------------
-- Component
-----------------------------------------------------------------------------
component spictrlx
generic (
rev : integer := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
syncram : integer range 0 to 1 := 1;
memtech : integer range 0 to NTECH := 0;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
syncrst : integer range 0 to 1 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0;
ignore : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spii_ignore : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end component;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal apbo_pirq : std_ulogic;
begin
ctrl_rtl : if netlist = 0 generate
rtlc : spictrlx
generic map (
rev => SPICTRL_REV,
fdepth => fdepth,
slvselen => slvselen,
slvselsz => slvselsz,
oepol => oepol,
odmode => odmode,
automode => automode,
acntbits => acntbits,
aslvsel => aslvsel,
twen => twen,
maxwlen => maxwlen,
syncram => syncram,
memtech => memtech,
ft => ft,
scantest => scantest,
syncrst => syncrst,
automask0 => automask0,
automask1 => automask1,
automask2 => automask2,
automask3 => automask3,
ignore => ignore)
port map (
rstn => rstn,
clk => clk,
-- APB signals
apbi_psel => apbi.psel(pindex),
apbi_penable => apbi.penable,
apbi_paddr => apbi.paddr,
apbi_pwrite => apbi.pwrite,
apbi_pwdata => apbi.pwdata,
apbi_testen => apbi.testen,
apbi_testrst => apbi.testrst,
apbi_scanen => apbi.scanen,
apbi_testoen => apbi.testoen,
apbo_prdata => apbo.prdata,
apbo_pirq => apbo_pirq,
-- SPI signals
spii_miso => spii.miso,
spii_mosi => spii.mosi,
spii_sck => spii.sck,
spii_spisel => spii.spisel,
spii_astart => spii.astart,
spii_cstart => spii.cstart,
spii_ignore => spii.ignore,
spio_miso => spio.miso,
spio_misooen => spio.misooen,
spio_mosi => spio.mosi,
spio_mosioen => spio.mosioen,
spio_sck => spio.sck,
spio_sckoen => spio.sckoen,
spio_enable => spio.enable,
spio_astart => spio.astart,
spio_aready => spio.aready,
slvsel => slvsel);
end generate ctrl_rtl;
ctrl_netlist : if netlist /= 0 generate
netlc : spictrl_net
generic map (
tech => netlist,
fdepth => fdepth,
slvselen => slvselen,
slvselsz => slvselsz,
oepol => oepol,
odmode => odmode,
automode => automode,
acntbits => acntbits,
aslvsel => aslvsel,
twen => twen,
maxwlen => maxwlen,
automask0 => automask0,
automask1 => automask1,
automask2 => automask2,
automask3 => automask3)
port map (
rstn => rstn,
clk => clk,
-- APB signals
apbi_psel => apbi.psel(pindex),
apbi_penable => apbi.penable,
apbi_paddr => apbi.paddr,
apbi_pwrite => apbi.pwrite,
apbi_pwdata => apbi.pwdata,
apbi_testen => apbi.testen,
apbi_testrst => apbi.testrst,
apbi_scanen => apbi.scanen,
apbi_testoen => apbi.testoen,
apbo_prdata => apbo.prdata,
apbo_pirq => apbo_pirq,
-- SPI signals
spii_miso => spii.miso,
spii_mosi => spii.mosi,
spii_sck => spii.sck,
spii_spisel => spii.spisel,
spii_astart => spii.astart,
spii_cstart => spii.cstart,
spio_miso => spio.miso,
spio_misooen => spio.misooen,
spio_mosi => spio.mosi,
spio_mosioen => spio.mosioen,
spio_sck => spio.sck,
spio_sckoen => spio.sckoen,
spio_enable => spio.enable,
spio_astart => spio.astart,
spio_aready => spio.aready,
slvsel => slvsel);
end generate ctrl_netlist;
spio.ssn <= (others => '0');
irqgen : process(apbo_pirq)
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
irq := (others => '0'); irq(pirq) := apbo_pirq;
apbo.pirq <= irq;
end process;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"spictrl" & tost(pindex) & ": SPI controller, rev " &
tost(SPICTRL_REV) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml510/config.vhd | 2 | 7874 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (2);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#C00#;
constant CFG_AHB_MON : integer := 1;
constant CFG_AHB_MONERR : integer := 1;
constant CFG_AHB_MONWAR : integer := 1;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0034#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000035#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (512);
constant CFG_DDR2SP_DELAY0 : integer := (8);
constant CFG_DDR2SP_DELAY1 : integer := (8);
constant CFG_DDR2SP_DELAY2 : integer := (8);
constant CFG_DDR2SP_DELAY3 : integer := (8);
constant CFG_DDR2SP_DELAY4 : integer := (8);
constant CFG_DDR2SP_DELAY5 : integer := (8);
constant CFG_DDR2SP_DELAY6 : integer := (8);
constant CFG_DDR2SP_DELAY7 : integer := (8);
constant CFG_DDR2SP_NOSYNC : integer := 1;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0060#;
constant CFG_GRGPIO_WIDTH : integer := (12);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 3;
constant CFG_PCIVID : integer := 16#1AC8#;
constant CFG_PCIDID : integer := 16#0054#;
constant CFG_PCIDEPTH : integer := 128;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 1;
constant CFG_PCI_ARBAPB : integer := 1;
constant CFG_PCI_ARB_NGNT : integer := (8);
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 1;
constant CFG_PCITBUF : integer := 4096;
-- SVGA controller
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- AMBA Wrapper for Xilinx System Monitor
constant CFG_GRSYSMON : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-jopdesign-ep1c12/leon3mp.vhd | 1 | 31579 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic;
can_rxd : in std_logic;
can_stb : out std_logic;
spw_clk : in std_logic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbmsp : integer := NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
constant BOARD_FREQ : integer := 20000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := CFG_SDCTRL + CFG_CAN;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_SDCTRL_INVCLK + CFG_MCTRL_INVCLK;
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*20000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= '0';
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sdc : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data, sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data, sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm);
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) and (CFG_SDCTRL = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 8, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(8));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(8) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 8)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdis_pad : outpad generic map (tech => padtech)
port map (emddis, vcc(0));
eepwrdwn_pad : outpad generic map (tech => padtech)
port map (epwrdwn, gnd(0));
esleep_pad : outpad generic map (tech => padtech)
port map (esleep, gnd(0));
epause_pad : outpad generic map (tech => padtech)
port map (epause, gnd(0));
ereset_pad : outpad generic map (tech => padtech)
port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FFF#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_lclk);
spw_rxtxclk <= spw_lclk;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, rmapbufs => CFG_SPW_RMAPBUF,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, ports => 1, dmachan => CFG_SPW_DMACHAN,
spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME)
port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxd(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxs(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/sim/pwm_check.vhd | 1 | 31865 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: pwm_check
-- File: pwm_check.vhd
-- Author: Jonas Ekergarn - Aeroflex Gaisler (parts are copied from
-- grtestmod.vhd)
-- Description: Simulation unit that examines the PWMs generated by the GRPWM
-- when software/leon3/grpwm.c is run. Note that pwm_check
-- requires that the system includes an I/O memory interface
-- and that grtestmod.vhd is instantiated in the system testbench.
-- If the subtests in software/leon3/grpwm.c is modified then the
-- configuration below and the procedure verify_subtest must be
-- changed as well.
-------------------------------------------------------------------------------
-- pragma translate_off
library ieee, grlib, gaisler;
use ieee.std_logic_1164.all;
use std.textio.all;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
use gaisler.sim.all;
entity pwm_check is
port (
clk : in std_ulogic;
address : in std_logic_vector(21 downto 2);
data : inout std_logic_vector(31 downto 0);
iosn : in std_ulogic;
oen : in std_ulogic;
writen : in std_ulogic;
pwm : in std_logic_vector(15 downto 0)
);
end;
architecture sim of pwm_check is
signal ior, iow : std_ulogic;
signal addr : std_logic_vector(21 downto 2);
signal ldata : std_logic_vector(31 downto 0);
signal pwmh : std_logic_vector(1 downto 0);
signal pwmh0 : integer := 0;
signal pwmh1 : integer := 1;
-----------------------------------------------------------------------------
-- Configuration of the PWMs that should be verified
-----------------------------------------------------------------------------
-- Number of "useful" words in the waveform ram. The core will read address
-- 0 - (STX_WRAMSIZE-1).
constant ST3_WRAMSIZE : integer := 32;
constant ST4_WRAMSIZE : integer := 32;
-- Number of periods to verify for each subtest. Verification of the very
-- first period after PWM is started is skipped because there is no way of
-- knowing exactly when it starts. It is assumed that the first period is
-- correct. If it isn't then the verification of the other periods will fail
-- as well.
constant ST1_NPER : integer := 10;
constant ST2_NPER : integer := 10;
constant ST3_NPER : integer := 2*ST3_WRAMSIZE;
constant ST4_NPER : integer := 2*ST4_WRAMSIZE;
type st1_vector is array (0 to ST1_NPER) of integer;
type st2_vector is array (0 to ST2_NPER) of integer;
type st3_vector is array (0 to ST3_NPER) of integer;
type st4_vector is array (0 to ST4_NPER) of integer;
type st1_array is array (0 to 7) of st1_vector;
type st2_array is array (0 to 7) of st2_vector;
type st3_array is array (0 to 7) of st3_vector;
type st4_array is array (0 to 7) of st4_vector;
type wram_type is array (0 to 8191) of integer;
-- Polarity for each PWM in the different subtests
constant ST1_POL : std_logic_vector(7 downto 0) := (others=>'1');
constant ST2_POL : std_logic_vector(7 downto 0) := (others=>'1');
constant ST3_POL : std_logic_vector(7 downto 0) := (others=>'1');
constant ST4_POL : std_logic_vector(7 downto 0) := (others=>'1');
-- Period, compare, and dead band values for each pwm period in subtest 1,
-- in clock cycles
constant ST1_PER : st1_array := (
0 => (others=>200),
1 => (others=>201),
2 => (others=>202),
3 => (others=>203),
4 => (others=>204),
5 => (others=>205),
6 => (others=>206),
7 => (others=>207));
constant ST1_COMPA : st1_array := (
0 => (others=>100),
1 => (others=>101),
2 => (others=>102),
3 => (others=>103),
4 => (others=>104),
5 => (others=>105),
6 => (others=>106),
7 => (others=>107));
constant ST1_DB : st1_array := (
0 => (others=>10),
1 => (others=>11),
2 => (others=>12),
3 => (others=>13),
4 => (others=>14),
5 => (others=>15),
6 => (others=>16),
7 => (others=>17));
-- Period, compare, and dead band values for each pwm period in subtest 2,
-- in clock cycles
constant ST2_PER : st2_array := (
0 => (others=>200),
1 => (others=>202),
2 => (others=>204),
3 => (others=>206),
4 => (others=>208),
5 => (others=>210),
6 => (others=>212),
7 => (others=>214));
constant ST2_COMPA : st2_array := (
0 => (others=>50),
1 => (others=>51),
2 => (others=>52),
3 => (others=>53),
4 => (others=>54),
5 => (others=>55),
6 => (others=>56),
7 => (others=>57));
constant ST2_DB : st2_array := (
0 => (others=>10),
1 => (others=>11),
2 => (others=>12),
3 => (others=>13),
4 => (others=>14),
5 => (others=>15),
6 => (others=>16),
7 => (others=>17));
-- Period, compare, and dead band values for each pwm period in subtest 3,
-- in clock cycles. (Only the PWM with the highest index is active during
-- subtest 3, but since we here don't know how many PWM outputs there are,
-- all get the same value)
constant ST3_WRAM : wram_type := (
32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,
56,57,58,59,60,61,62,63,
others=>0);
constant ST3_PER : st3_array := (
0 => (others=>200),
1 => (others=>200),
2 => (others=>200),
3 => (others=>200),
4 => (others=>200),
5 => (others=>200),
6 => (others=>200),
7 => (others=>200));
constant ST3_DB : st3_array := (
0 => (others=>10),
1 => (others=>10),
2 => (others=>10),
3 => (others=>10),
4 => (others=>10),
5 => (others=>10),
6 => (others=>10),
7 => (others=>10));
-- Period, compare, and dead band values for each pwm period in subtest 4,
-- in clock cycles. (Only the PWM with the highest index is active during
-- subtest 4, but since we here don't know how many PWM outputs there are,
-- all get the same value)
constant ST4_WRAM : wram_type := (
32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,
56,57,58,59,60,61,62,63,
others=>0);
constant ST4_PER : st4_array := (
0 => (others=>200),
1 => (others=>200),
2 => (others=>200),
3 => (others=>200),
4 => (others=>200),
5 => (others=>200),
6 => (others=>200),
7 => (others=>200));
constant ST4_DB : st4_array := (
0 => (others=>10),
1 => (others=>10),
2 => (others=>10),
3 => (others=>10),
4 => (others=>10),
5 => (others=>10),
6 => (others=>10),
7 => (others=>10));
type pwm_int_array is array (0 to 7) of integer;
type pwm_bool_array is array (0 to 7) of boolean;
procedure verify_subtest (
constant subtest : in integer;
constant npwm : in integer range 1 to 8;
signal clk : in std_ulogic;
signal pwm : in std_logic_vector(15 downto 0);
signal pwmh : in std_logic_vector(1 downto 0)) is
variable cnt : pwm_int_array := (others=>0);
variable cnt2 : pwm_int_array := (others=>0);
variable pcnt : pwm_int_array := (others=>0);
variable parta : pwm_bool_array := (others=>false);
variable partb : pwm_bool_array := (others=>false);
variable partc : pwm_bool_array := (others=>false);
variable partd : pwm_bool_array := (others=>false);
variable done : pwm_bool_array := (others=>false);
variable ST2_COMPB : st2_array;
variable ST4_COMPB : st4_array;
variable addr : integer;
variable il, ih : integer;
begin
case subtest is
when 1 =>
-------------------------------------------------------------------------
-- Subtest 1: npwm assymmetric PWM pairs are generated, all with
-- different periods, compare values, and dead band values. Verify
-- periods, compare matches, and dead band times.
-------------------------------------------------------------------------
for i in 0 to 7 loop
if npwm < i+1 then done(i) := true; end if;
-- no dead band time is inserted in the very first pwm period after
-- startup
parta(i) := true;
end loop;
while not(done(0) and done(1) and done(2) and done(3) and
done(4) and done(5) and done(6) and done(7)) loop
wait until rising_edge(clk);
for i in 0 to npwm-1 loop
cnt(i) := cnt(i)+1;
end loop;
wait until (pwm'event or falling_edge(clk));
if clk = '1' then
for i in 0 to npwm-1 loop
if (not done(i)) then
if (not parta(i)) then
-- pwm is in time period between period start and when paired
-- output goes active (after dead band time)
if pwm(2*i+1) = ST1_POL(i) then
parta(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= ST1_DB(i)(pcnt(i)) then
Print("ERROR: Wrong dead band (1) detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)) & ", should be " &
tost(ST1_DB(i)(pcnt(i))));
end if;
end if;
end if;
elsif (not partb(i)) then
-- pwm is in time period between paired output going active and
-- paired output going inactive
if pwm(2*i+1) = (not ST1_POL(i)) then
partb(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= ST1_COMPA(i)(pcnt(i)) then
Print("ERROR: Wrong compare match detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)) & ", should be " &
tost(ST1_COMPA(i)(pcnt(i))));
end if;
if ST1_DB(i)(pcnt(i)) = 0 then
partc(i) := true;
if pwm(2*i) /= ST1_POL(i) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
end if;
end if;
elsif (not partc(i)) then
-- pwm is in time period between paired output going inactive and
-- output going active (after dead band time)
if pwm(2*i) = ST1_POL(i) then
partc(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= (ST1_COMPA(i)(pcnt(i)) +
ST1_DB(i)(pcnt(i))) then
Print("ERROR: Wrong dead band (2) time detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)-ST1_COMPA(i)(pcnt(i))) &
", should be " & tost(ST1_DB(i)(pcnt(i))));
end if;
end if;
end if;
else
-- pwm is in time period between output going active and period end
-- (output going inactive)
if pwm(2*i) = (not ST1_POL(i)) then
parta(i) := false; partb(i) := false; partc(i) := false;
if pcnt(i) /= 0 then
if cnt(i) /= ST1_PER(i)(pcnt(i)) then
Print("ERROR: Wrong PWM period detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)) & ", should be " &
tost(ST1_PER(i)(pcnt(i))));
end if;
end if;
if pcnt(i) = ST1_NPER then
done(i) := true;
end if;
pcnt(i) := pcnt(i)+1;
cnt(i) := 0;
if pcnt(i) < ST1_NPER then
if ST1_DB(i)(pcnt(i)) = 0 then
parta(i) := true;
if pwm(2*i+1) /= ST1_POL(i) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
end if;
end if;
end if;
end if;
end loop;
end if;
end loop;
when 2 =>
-------------------------------------------------------------------------
-- Subtest 2: npwm symmetric PWM pairs are generated, all with
-- different periods, compare values, and dead band values. Verify
-- periods, compare matches, and dead band times
-------------------------------------------------------------------------
for i in 0 to 7 loop
for j in 0 to ST2_NPER loop
ST2_COMPB(i)(j) := ST2_PER(i)(j)-ST2_COMPA(i)(j);
end loop;
if npwm < i+1 then done(i) := true; end if;
end loop;
while not(done(0) and done(1) and done(2) and done(3) and
done(4) and done(5) and done(6) and done(7)) loop
wait until rising_edge(clk);
for i in 0 to npwm-1 loop
cnt(i) := cnt(i)+1; cnt2(i) := cnt2(i)+1;
end loop;
wait until (pwm'event or falling_edge(clk));
if clk = '1' then
for i in 0 to npwm-1 loop
if (not done(i)) then
if (not parta(i)) then
-- pwm is in time period between period start and when paired
-- output goes inactive
if pwm(2*i+1) = (not ST2_POL(i)) then
parta(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= ST2_COMPA(i)(pcnt(i)) then
Print("ERROR: Wrong compare match 1 detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)) & ", should be " &
tost(ST2_COMPA(i)(pcnt(i))));
end if;
if ST2_DB(i)(pcnt(i)) = 0 then
partb(i) := true;
if pwm(2*i) /= ST2_POL(i) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
end if;
end if;
elsif (not partb(i)) then
-- pwm is in time period between paired output going inactive and
-- output going active (after dead band time)
if pwm(2*i) = ST2_POL(i) then
partb(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= (ST2_COMPA(i)(pcnt(i)) +
ST2_DB(i)(pcnt(i))) then
Print("ERROR: Wrong dead band (1) time detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)-ST2_COMPA(i)(pcnt(i))) &
", should be " & tost(ST2_DB(i)(pcnt(i))));
end if;
end if;
end if;
elsif (not partc(i)) then
-- pwm is in time period between output going active and
-- output going inactive
if pwm(2*i) = (not ST2_POL(i)) then
partc(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= ST2_COMPB(i)(pcnt(i)) then
Print("ERROR: Wrong compare match (2) detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)) & ", should be " &
tost(ST2_COMPB(i)(pcnt(i))));
end if;
if ST2_DB(i)(pcnt(i)) = 0 then
partd(i) := true;
if pwm(2*i+1) /= ST2_POL(i) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
else
if ST2_DB(i)(0) = 0 then
cnt2(i) := 0;
partd(i) := true;
end if;
end if;
end if;
elsif (not partd(i)) then
-- pwm is in time period between output going inactive and
-- paired output going active (after dead band time)
if pwm(2*i+1) = ST2_POL(i) then
partd(i) := true;
if pcnt(i) /= 0 then
if cnt(i) /= (ST2_COMPB(i)(pcnt(i)) +
ST2_DB(i)(pcnt(i))) then
Print("ERROR: Wrong dead band (2) time detected for pwm " &
tost(i+1) & " in period = " & tost(pcnt(i)) &
". Is " & tost(cnt(i)-ST2_COMPB(i)(pcnt(i))) &
", should be " & tost(ST2_DB(i)(pcnt(i))));
end if;
else
cnt2(i) := 0;
end if;
end if;
end if;
end if;
end loop;
end if;
for i in 0 to npwm-1 loop
if (not done(i)) then
if partd(i) then
-- pwm is in time period between paired output going active
-- and period end
if pcnt(i) /= 0 then
if cnt(i) = ST2_PER(i)(pcnt(i)) then
parta(i) := false; partb(i) := false;
partc(i) := false; partd(i) := false;
pcnt(i) := pcnt(i)+1;
cnt(i) := 0;
end if;
else
if (cnt2(i)+ST2_COMPB(i)(0)+ST2_DB(i)(0)) =
ST2_PER(i)(0) then
parta(i) := false; partb(i) := false;
partc(i) := false; partd(i) := false;
pcnt(i) := pcnt(i)+1;
cnt(i) := 0;
end if;
end if;
if pcnt(i) = ST2_NPER then
done(i) := true;
end if;
end if;
end if;
end loop;
end loop;
when 3 =>
-------------------------------------------------------------------------
-- Subtest 3: One asymmetric waveform PWM is generated. Verify period,
-- compare matches and dead band time
-------------------------------------------------------------------------
parta(npwm-1) := true;
while not done(npwm-1) loop
wait until rising_edge(clk);
cnt(npwm-1) := cnt(npwm-1)+1;
wait until (pwmh'event or falling_edge(clk));
if clk = '1' then
addr := pcnt(npwm-1) - (pcnt(npwm-1)/ST3_WRAMSIZE)*ST3_WRAMSIZE;
if (not parta(npwm-1)) then
-- pwm is in time period between period start and when paired
-- output goes active (after dead band time)
if pwmh(1) = ST3_POL(npwm-1) then
parta(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= ST3_DB(npwm-1)(pcnt(npwm-1)) then
Print("ERROR: Wrong dead band (1) detected for pwm " &
tost((npwm-1)+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)) & ", should be " &
tost(ST3_DB(npwm-1)(pcnt(npwm-1))));
end if;
end if;
end if;
elsif (not partb(npwm-1)) then
-- pwm is in time period between paired output going active and
-- paired output going inactive
if pwmh(1) = (not ST3_POL(npwm-1)) then
partb(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= ST3_WRAM(addr) then
Print("ERROR: Wrong compare match detected for pwm " &
tost((npwm-1)+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)) & ", should be " &
tost(ST3_WRAM(addr)));
end if;
if ST3_DB(npwm-1)(pcnt(npwm-1)) = 0 then
partc(npwm-1) := true;
if pwmh(0) /= ST3_POL(npwm-1) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
end if;
end if;
elsif (not partc(npwm-1)) then
-- pwm is in time period between paired output going inactive and
-- output going active (after dead band time)
if pwmh(0) = ST3_POL(npwm-1) then
partc(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= (ST3_WRAM(addr) +
ST3_DB(npwm-1)(pcnt(npwm-1))) then
Print("ERROR: Wrong dead band (2) time detected for pwm " &
tost((npwm-1)+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)-ST3_WRAM(addr)) &
", should be " & tost(ST3_DB(npwm-1)(pcnt(npwm-1))));
end if;
end if;
end if;
else
-- pwm is in time period between output going active and period end
-- (output going inactive)
if pwmh(0) = (not ST3_POL(npwm-1)) then
parta(npwm-1) := false; partb(npwm-1) := false; partc(npwm-1) := false;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= ST3_PER(npwm-1)(pcnt(npwm-1)) then
Print("ERROR: Wrong PWM period detected for pwm " &
tost((npwm-1)+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)) & ", should be " &
tost(ST3_PER(npwm-1)(pcnt(npwm-1))));
end if;
end if;
if pcnt(npwm-1) = ST3_NPER then
done(npwm-1) := true;
end if;
pcnt(npwm-1) := pcnt(npwm-1)+1;
cnt(npwm-1) := 0;
if pcnt(npwm-1) < ST3_NPER then
if ST3_DB(npwm-1)(pcnt(npwm-1)) = 0 then
parta(npwm-1) := true;
if pwmh(1) /= ST3_POL(npwm-1) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
end if;
end if;
end if;
end if;
end loop;
when 4 =>
-------------------------------------------------------------------------
-- Subtest 4: One symmetric waveform PWM is generated. Verify period,
-- compare matches, and dead band time
-------------------------------------------------------------------------
for j in 0 to ST4_NPER loop
addr := j - (j/ST4_WRAMSIZE)*ST4_WRAMSIZE;
ST4_COMPB(npwm-1)(j) := ST4_PER(npwm-1)(j)-ST4_WRAM(addr);
end loop;
while not done(npwm-1) loop
wait until rising_edge(clk);
cnt(npwm-1) := cnt(npwm-1)+1; cnt2(npwm-1) := cnt2(npwm-1)+1;
wait until (pwmh'event or falling_edge(clk));
if clk = '1' then
addr := pcnt(npwm-1) - (pcnt(npwm-1)/ST4_WRAMSIZE)*ST4_WRAMSIZE;
if (not parta(npwm-1)) then
-- pwm is in time period between period start and when paired
-- output goes inactive
if pwmh(1) = (not ST4_POL(npwm-1)) then
parta(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= ST4_WRAM(addr) then
Print("ERROR: Wrong compare match 1 detected for pwm " &
tost(npwm-1+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)) & ", should be " &
tost(ST4_WRAM(addr)));
end if;
if ST4_DB(npwm-1)(pcnt(npwm-1)) = 0 then
partb(npwm-1) := true;
if pwmh(0) /= ST4_POL(npwm-1) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
end if;
end if;
elsif (not partb(npwm-1)) then
-- pwm is in time period between paired output going inactive and
-- output going active (after dead band time)
if pwmh(0) = ST4_POL(npwm-1) then
partb(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= (ST4_WRAM(addr) +
ST4_DB(npwm-1)(pcnt(npwm-1))) then
Print("ERROR: Wrong dead band (1) time detected for pwm " &
tost(npwm-1+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)-ST4_WRAM(addr)) &
", should be " & tost(ST4_DB(npwm-1)(pcnt(npwm-1))));
end if;
end if;
end if;
elsif (not partc(npwm-1)) then
-- pwm is in time period between output going active and
-- output going inactive
if pwmh(0) = (not ST4_POL(npwm-1)) then
partc(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= ST4_COMPB(npwm-1)(pcnt(npwm-1)) then
Print("ERROR: Wrong compare match (2) detected for pwm " &
tost(npwm-1+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)) & ", should be " &
tost(ST4_COMPB(npwm-1)(pcnt(npwm-1))));
end if;
if ST4_DB(npwm-1)(pcnt(npwm-1)) = 0 then
partd(npwm-1) := true;
if pwmh(1) /= ST4_POL(npwm-1) then
Print("ERROR: Both outputs did not switch simultaneously"
& " even though dead band time was zero");
end if;
end if;
else
if ST4_DB(npwm-1)(0) = 0 then
cnt2(npwm-1) := 0;
partd(npwm-1) := true;
end if;
end if;
end if;
elsif (not partd(npwm-1)) then
-- pwm is in time period between output going inactive and
-- paired output going active (after dead band time)
if pwmh(1) = ST4_POL(npwm-1) then
partd(npwm-1) := true;
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) /= (ST4_COMPB(npwm-1)(pcnt(npwm-1)) +
ST4_DB(npwm-1)(pcnt(npwm-1))) then
Print("ERROR: Wrong dead band (2) time detected for pwm " &
tost(npwm-1+1) & " in period = " & tost(pcnt(npwm-1)) &
". Is " & tost(cnt(npwm-1)-ST4_COMPB(npwm-1)(pcnt(npwm-1))) &
", should be " & tost(ST4_DB(npwm-1)(pcnt(npwm-1))));
end if;
else
cnt2(npwm-1) := 0;
end if;
end if;
end if;
end if;
if partd(npwm-1) then
-- pwm is in time period between paired output going active
-- and period end
if pcnt(npwm-1) /= 0 then
if cnt(npwm-1) = ST4_PER(npwm-1)(pcnt(npwm-1)) then
parta(npwm-1) := false; partb(npwm-1) := false;
partc(npwm-1) := false; partd(npwm-1) := false;
pcnt(npwm-1) := pcnt(npwm-1)+1;
cnt(npwm-1) := 0;
end if;
else
if (cnt2(npwm-1)+ST4_COMPB(npwm-1)(0)+ST4_DB(npwm-1)(0)) =
ST4_PER(npwm-1)(0) then
parta(npwm-1) := false; partb(npwm-1) := false;
partc(npwm-1) := false; partd(npwm-1) := false;
pcnt(npwm-1) := pcnt(npwm-1)+1;
cnt(npwm-1) := 0;
end if;
end if;
if pcnt(npwm-1) = ST4_NPER then
done(npwm-1) := true;
end if;
end if;
end loop;
when others => null;
end case;
end verify_subtest;
begin
ior <= iosn or oen;
iow <= iosn or writen;
data <= (others => 'Z');
addr <= to_X01(address) when rising_edge(clk) else addr;
ldata <= to_X01(data) when rising_edge(clk) else ldata;
pwmh <= pwm(pwmh1 downto pwmh0);
process
variable vid, did, subtest : integer;
variable npwm : integer := 8;
begin
pwmh0 <= 2*(npwm-1);
pwmh1 <= 2*(npwm-1)+1;
wait until ((rising_edge(ior) nor falling_edge(ior)) and rising_edge(iow));
case addr(7 downto 2) is
when "000000" =>
vid := conv_integer(ldata(31 downto 24));
did := conv_integer(ldata(23 downto 12));
when "000010" =>
subtest := conv_integer(ldata(7 downto 0));
if vid = VENDOR_GAISLER and did = GAISLER_PWM then
if subtest > 246 then
-- set npwm
npwm := 255 - subtest;
else
verify_subtest(subtest, npwm, clk, pwm, pwmh);
end if;
end if;
when others =>
end case;
end process;
end sim;
-- pragma translate_on
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/misc.vhd | 1 | 45771 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: misc
-- File: misc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Misc models
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
package misc is
-- reset generator with filter
component rstgen
generic (acthigh : integer := 0; syncrst : integer := 0;
scanen : integer := 0; syncin : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0');
end component;
type gptimer_in_type is record
dhalt : std_ulogic;
extclk : std_ulogic;
wdogen : std_ulogic;
end record;
type gptimer_in_vector is array (natural range <>) of gptimer_in_type;
type gptimer_out_type is record
tick : std_logic_vector(0 to 7);
timer1 : std_logic_vector(31 downto 0);
wdogn : std_ulogic;
wdog : std_ulogic;
end record;
type gptimer_out_vector is array (natural range <>) of gptimer_out_type;
constant gptimer_in_none : gptimer_in_type := ('0', '0', '0');
constant gptimer_out_none : gptimer_out_type :=
((others => '0'), (others => '0'), '1', '0');
component gptimer
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0;
ewdogen : integer := 0;
glatch : integer := 0;
gextclk : integer := 0;
gset : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end component;
-- 32-bit ram with AHB interface
component ahbram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type);
end component;
type ahbram_out_type is record
ce : std_ulogic;
end record;
component ftahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer := 1;
autoscrub : integer := 0;
errcnten : integer := 0;
cntbits : integer range 1 to 8 := 1;
ahbpipe : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ftahbram2 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
testen : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ahbdpram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 2;
abits : integer range 8 to 19 := 8;
bytewrite : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
clkdp : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
enable : in std_ulogic; -- active high chip select
write : in std_logic_vector(0 to 3) -- active high byte write enable
); -- big-endian write: bwrite(0) => data(31:24)
end component;
component ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component ahbtrace_mb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmi : in ahb_mst_in_type; -- Trace
tahbsi : in ahb_slv_in_type
);
end component;
component ahbtrace_mmb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
ntrace : integer range 1 to 8 := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmiv : in ahb_mst_in_vector_type(0 to ntrace-1); -- Trace
tahbsiv : in ahb_slv_in_vector_type(0 to ntrace-1)
);
end component;
type ahbmst2_request is record
req: std_logic; -- Request enable bit
wr: std_logic;
hsize: std_logic_vector(2 downto 0);
hburst: std_logic_vector(2 downto 0);
hprot: std_logic_vector(3 downto 0);
addr: std_logic_vector(32-1 downto 0);
burst_cont: std_logic; -- Set for all except the first request in a burst
burst_wrap: std_logic; -- High for the request where wrap occurs
end record;
constant ahbmst2_request_none: ahbmst2_request := (
req => '0', wr => '0', hsize => "010", hburst => "000", burst_cont => '0',
burst_wrap => '0', addr => (others => '0'), hprot => "0011");
type ahbmst2_in_type is record
request: ahbmst2_request;
wrdata: std_logic_vector(AHBDW-1 downto 0);
-- For back-to-back transfers or bursts, this must be set when done is high
-- and then copied over to request after the rising edge of clk.
next_request: ahbmst2_request;
-- Insert busy cycle, must only be asserted when request and next_request
-- are both part of the same burst.
busy: std_logic;
hlock: std_logic; -- Lock signal, passed through directly to AMBA.
keepreq: std_logic; -- Keep bus request high even when no request needs it.
end record;
type ahbmst2_out_type is record
done: std_logic;
flip: std_logic;
fail: std_logic;
rddata: std_logic_vector(AHBDW-1 downto 0);
end record;
component ahbmst2 is
generic (
hindex: integer := 0;
venid: integer;
devid: integer;
version: integer;
dmastyle: integer range 1 to 3 := 3;
syncrst: integer range 0 to 1 := 1
);
port (
clk: in std_logic;
rst: in std_logic;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
m2i: in ahbmst2_in_type;
m2o: out ahbmst2_out_type
);
end component;
type gpio_in_type is record
din : std_logic_vector(31 downto 0);
sig_in : std_logic_vector(31 downto 0);
sig_en : std_logic_vector(31 downto 0);
end record;
type gpio_in_vector is array (natural range <>) of gpio_in_type;
type gpio_out_type is record
dout : std_logic_vector(31 downto 0);
oen : std_logic_vector(31 downto 0);
val : std_logic_vector(31 downto 0);
sig_out : std_logic_vector(31 downto 0);
end record;
type gpio_out_vector is array (natural range <>) of gpio_out_type;
component grgpio
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0;
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#;
pirq : integer := 0;
irqgen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end component;
type ahb2ahb_ctrl_type is record
slck : std_ulogic;
blck : std_ulogic;
mlck : std_ulogic;
end record;
constant ahb2ahb_ctrl_none : ahb2ahb_ctrl_type := ('0', '0', '0');
type ahb2ahb_ifctrl_type is record
mstifen : std_ulogic;
slvifen : std_ulogic;
end record;
constant ahb2ahb_ifctrl_none : ahb2ahb_ifctrl_type := ('1', '1');
component ahb2ahb
generic(
memtech : integer := 0;
hsindex : integer := 0;
hmindex : integer := 0;
slv : integer range 0 to 1 := 0;
dir : integer range 0 to 1 := 0; -- 0 - down, 1 - up
ffact : integer range 0 to 15:= 2;
pfen : integer range 0 to 1 := 0;
wburst : integer range 2 to 32 := 8;
iburst : integer range 4 to 8 := 8;
rburst : integer range 2 to 32 := 8;
irqsync : integer range 0 to 2 := 0;
bar0 : integer range 0 to 1073741823 := 0;
bar1 : integer range 0 to 1073741823 := 0;
bar2 : integer range 0 to 1073741823 := 0;
bar3 : integer range 0 to 1073741823 := 0;
sbus : integer := 0;
mbus : integer := 0;
ioarea : integer := 0;
ibrsten : integer := 0;
lckdac : integer range 0 to 2 := 0;
slvmaccsz : integer range 32 to 256 := 32;
mstmaccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
ifctrlen : integer range 0 to 1 := 0;
fcfs : integer range 0 to NAHBMST := 0;
fcfsmtech : integer range 0 to NTECH := inferred;
scantest : integer range 0 to 1 := 0;
split : integer range 0 to 1 := 1;
pipe : integer range 0 to 128 := 0);
port (
rstn : in std_ulogic;
hclkm : in std_ulogic;
hclks : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbso2 : in ahb_slv_out_vector;
lcki : in ahb2ahb_ctrl_type;
lcko : out ahb2ahb_ctrl_type;
ifctrl : in ahb2ahb_ifctrl_type := ahb2ahb_ifctrl_none
);
end component;
component ahbbridge
generic(
memtech : integer := 0;
ffact : integer range 0 to 15 := 2;
-- high-speed bus
hsb_hsindex : integer := 0;
hsb_hmindex : integer := 0;
hsb_iclsize : integer range 4 to 8 := 8;
hsb_bank0 : integer range 0 to 1073741823 := 0;
hsb_bank1 : integer range 0 to 1073741823 := 0;
hsb_bank2 : integer range 0 to 1073741823 := 0;
hsb_bank3 : integer range 0 to 1073741823 := 0;
hsb_ioarea : integer := 0;
-- low-speed bus
lsb_hsindex : integer := 0;
lsb_hmindex : integer := 0;
lsb_rburst : integer range 16 to 32 := 16;
lsb_wburst : integer range 2 to 32 := 8;
lsb_bank0 : integer range 0 to 1073741823 := 0;
lsb_bank1 : integer range 0 to 1073741823 := 0;
lsb_bank2 : integer range 0 to 1073741823 := 0;
lsb_bank3 : integer range 0 to 1073741823 := 0;
lsb_ioarea : integer := 0;
--
lckdac : integer range 0 to 2 := 2;
maccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
fcfs : integer range 0 to NAHBMST := 0;
scantest : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
hsb_clk : in std_ulogic;
lsb_clk : in std_ulogic;
hsb_ahbsi : in ahb_slv_in_type;
hsb_ahbso : out ahb_slv_out_type;
hsb_ahbsov : in ahb_slv_out_vector;
hsb_ahbmi : in ahb_mst_in_type;
hsb_ahbmo : out ahb_mst_out_type;
lsb_ahbsi : in ahb_slv_in_type;
lsb_ahbso : out ahb_slv_out_type;
lsb_ahbsov : in ahb_slv_out_vector;
lsb_ahbmi : in ahb_mst_in_type;
lsb_ahbmo : out ahb_mst_out_type);
end component;
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer;
type ahbstat_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
end record;
component ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
type nuhosp3_in_type is record
flash_d : std_logic_vector(15 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_ardy : std_ulogic;
smsc_intr : std_ulogic;
smsc_nldev : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
end record;
type nuhosp3_out_type is record
flash_a : std_logic_vector(20 downto 0);
flash_d : std_logic_vector(15 downto 0);
flash_oen : std_ulogic;
flash_wen : std_ulogic;
flash_cen : std_ulogic;
smsc_addr : std_logic_vector(14 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_nbe : std_logic_vector(3 downto 0);
smsc_resetn : std_ulogic;
smsc_nrd : std_ulogic;
smsc_nwr : std_ulogic;
smsc_ncs : std_ulogic;
smsc_aen : std_ulogic;
smsc_lclk : std_ulogic;
smsc_wnr : std_ulogic;
smsc_rdyrtn : std_ulogic;
smsc_cycle : std_ulogic;
smsc_nads : std_ulogic;
smsc_ben : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
lcd_rs : std_ulogic;
lcd_rw : std_ulogic;
lcd_en : std_ulogic;
lcd_backl : std_ulogic;
lcd_ben : std_ulogic;
end record;
component nuhosp3
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
ioaddr : integer := 16#200#;
iomask : integer := 16#fff#);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
nui : in nuhosp3_in_type;
nuo : out nuhosp3_out_type
);
end component;
-- On-chip Logic Analyzer
component logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0;
usediv : integer range 0 to 1 := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic;
clk : in std_logic;
tclk : in std_logic;
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end component;
type ps2_in_type is record
ps2_clk_i : std_ulogic;
ps2_data_i : std_ulogic;
end record;
type ps2_out_type is record
ps2_clk_o : std_ulogic;
ps2_clk_oe : std_ulogic;
ps2_data_o : std_ulogic;
ps2_data_oe : std_ulogic;
end record;
component apbps2
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 0;
oepol : integer range 0 to 1 := 0);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end component;
type apbvga_out_type is record
hsync : std_ulogic; -- horizontal sync
vsync : std_ulogic; -- vertical sync
comp_sync : std_ulogic; -- composite sync
blank : std_ulogic; -- blank signal
video_out_r : std_logic_vector(7 downto 0); -- red channel
video_out_g : std_logic_vector(7 downto 0); -- green channel
video_out_b : std_logic_vector(7 downto 0); -- blue channel
bitdepth : std_logic_vector(1 downto 0); -- Bith depth
end record;
component apbvga
generic(
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
vgaclk : in std_ulogic; -- VGA clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type
);
end component;
component svgactrl
generic(
length : integer := 384; -- Fifo-length
part : integer := 128; -- Fifo-part lenght
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8;
ahbaccsz : integer := 32;
asyncrst : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0);
arst : in std_ulogic := '1'
);
end component;
constant vgao_none : apbvga_out_type :=
('0', '0', '0', '0', "00000000", "00000000", "00000000", "00");
constant ps2o_none : ps2_out_type := ('1', '1', '1', '1');
-- component ahbrom
-- generic (
-- hindex : integer := 0;
-- haddr : integer := 0;
-- hmask : integer := 16#fff#;
-- pipe : integer := 0;
-- tech : integer := 0;
-- kbytes : integer := 1);
-- port (
-- rst : in std_ulogic;
-- clk : in std_ulogic;
-- ahbsi : in ahb_slv_in_type;
-- ahbso : out ahb_slv_out_type
-- );
-- end component;
component ahbdma
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
dbuf : integer := 0);
port (
rst : in std_logic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for FIFO controller
-----------------------------------------------------------------------------
type FIFO_In_Type is record
Din: Std_Logic_Vector(31 downto 0); -- data input
Pin: Std_Logic_Vector( 3 downto 0); -- parity input
EFn: Std_ULogic; -- empty flag
FFn: Std_ULogic; -- full flag
HFn: Std_ULogic; -- half flag
end record;
type FIFO_Out_Type is record
Dout: Std_Logic_Vector(31 downto 0); -- data output
Den: Std_Logic_Vector(31 downto 0); -- data enable
Pout: Std_Logic_Vector( 3 downto 0); -- parity output
Pen: Std_Logic_Vector( 3 downto 0); -- parity enable
WEn: Std_ULogic; -- write enable
REn: Std_ULogic; -- read enable
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR FIFO Interface
-----------------------------------------------------------------------------
component grfifo is
generic (
hindex: Integer := 0;
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
dwidth: Integer := 16; -- data width
ptrwidth: Integer range 16 to 16 := 16; -- 16 to 64k bytes
-- 128 to 512k bits
singleirq: Integer range 0 to 1 := 0; -- single irq output
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
ahbi: in AHB_Mst_In_Type;
ahbo: out AHB_Mst_Out_Type;
fifoi: in FIFO_In_Type;
fifoo: out FIFO_Out_Type);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for CAN controllers
-----------------------------------------------------------------------------
type Analog_In_Type is record
Ain: Std_Logic_Vector(31 downto 0); -- address input
Din: Std_Logic_Vector(31 downto 0); -- data input
Rdy: Std_ULogic; -- adc ready input
Trig: Std_Logic_Vector( 2 downto 0); -- adc trigger inputs
end record;
type Analog_Out_Type is record
Aout: Std_Logic_Vector(31 downto 0); -- address output
Aen: Std_Logic_Vector(31 downto 0); -- address enable
Dout: Std_Logic_Vector(31 downto 0); -- dac data output
Den: Std_Logic_Vector(31 downto 0); -- dac data enable
Wr: Std_ULogic; -- dac write strobe
CS: Std_ULogic; -- adc chip select
RC: Std_ULogic; -- adc read/convert
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR ADC/DAC Interface
-----------------------------------------------------------------------------
component gradcdac is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
awidth: Integer := 8; -- address width
dwidth: Integer := 16; -- data width
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
adi: in Analog_In_Type;
ado: out Analog_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AMBA wrapper for System Monitor
-----------------------------------------------------------------------------
type grsysmon_in_type is record
convst : std_ulogic;
convstclk : std_ulogic;
vauxn : std_logic_vector(15 downto 0);
vauxp : std_logic_vector(15 downto 0);
vn : std_ulogic;
vp : std_ulogic;
end record;
type grsysmon_out_type is record
alm : std_logic_vector(2 downto 0);
ot : std_ulogic;
eoc : std_ulogic;
eos : std_ulogic;
channel : std_logic_vector(4 downto 0);
end record;
constant grsysmon_in_gnd : grsysmon_in_type :=
('0', '0', (others => '0'), (others => '0'), '0', '0');
component grsysmon
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
caddr : integer := 16#000#; -- Base address for configuration area
cmask : integer := 16#fff#; -- Area mask
saddr : integer := 16#001#; -- Base address for sysmon register area
smask : integer := 16#fff#; -- Area mask
split : integer := 0; -- Enable AMBA SPLIT support
extconvst : integer := 0; -- Use external CONVST signal
wrdalign : integer := 0; -- Word align System Monitor registers
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "sysmon.txt");
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sysmoni : in grsysmon_in_type;
sysmono : out grsysmon_out_type
);
end component;
-----------------------------------------------------------------------------
-- AMBA System ACE Interface Controller
-----------------------------------------------------------------------------
type gracectrl_in_type is record
di : std_logic_vector(15 downto 0);
-- brdy : std_ulogic;
irq : std_ulogic;
end record;
type gracectrl_out_type is record
addr : std_logic_vector(6 downto 0);
do : std_logic_vector(15 downto 0);
cen : std_ulogic;
wen : std_ulogic;
oen : std_ulogic;
doen : std_ulogic; -- Data output enable to pad
end record;
constant gracectrl_none : gracectrl_out_type :=
((others => '1'), (others => '1'), '1', '1', '1', '1');
component gracectrl
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
haddr : integer := 16#000#; -- Base address
hmask : integer := 16#fff#; -- Area mask
split : integer range 0 to 1 := 0; -- Enable AMBA SPLIT support
swap : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0; -- Output enable polarity
mode : integer range 0 to 2 := 0 -- 16/8-bit mode
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
clkace : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
acei : in gracectrl_in_type;
aceo : out gracectrl_out_type
);
end component;
-----------------------------------------------------------------------------
-- General purpose register
-----------------------------------------------------------------------------
component grgpreg is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer range 1 to 64 := 16;
rstval : integer := 0;
rstval2 : integer := 0;
extrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gprego : out std_logic_vector(nbits-1 downto 0);
resval : in std_logic_vector(nbits-1 downto 0) := (others => '0')
);
end component;
component grgprbank is
generic (
pindex: integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
regbits: integer range 1 to 32 := 32;
nregs : integer range 1 to 32 := 1;
rstval: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
rego : out std_logic_vector(nregs*regbits-1 downto 0)
);
end component;
-----------------------------------------------------------------------------
-- EDAC Memory scrubber
-----------------------------------------------------------------------------
type memscrub_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
clrcount: std_logic;
start : std_logic;
end record;
component memscrub is
generic(
hmindex : integer := 0;
hsindex : integer := 0;
ioaddr : integer := 0;
iomask : integer := 16#FFF#;
hirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3;
memwidth: integer := AHBDW;
-- Read block (cache line) burst size, must be even mult of 2
burstlen: integer := 2;
countlen: integer := 8
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
scrubi: in memscrub_in_type
);
end component;
type ahb_mst_iface_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type ahb_mst_iface_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
component ahb_mst_iface is
generic(
hindex : integer;
vendor : integer;
device : integer;
revision : integer);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
msti : in ahb_mst_iface_in_type;
msto : out ahb_mst_iface_out_type
);
end component;
-----------------------------------------------------------------------------
-- Clock gate unit
-----------------------------------------------------------------------------
component grclkgate
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
ungateen : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0); -- Only used with shared FPU
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2)*(ncpu/2-1) downto 0); -- Only used with shared FPU
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic);
end component;
component grclkgate2x
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
clk2xen : integer := 0; -- Enable double clocking
ungateen : integer := 0
);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2x : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0); -- Only used with shared FPU
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_ulogic;
clkahb2x : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2)*(ncpu/2-1) downto 0); -- Only used with shared FPU
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic
);
end component;
component ahbwbax is
generic (
ahbbits: integer;
blocksz: integer := 16;
mstmode: integer := 0
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
-- Wide-side slave inputs
wi_hready: in std_ulogic;
wi_hsel: in std_ulogic;
wi_htrans: in std_logic_vector(1 downto 0);
wi_hsize: in std_logic_vector(2 downto 0);
wi_hburst: in std_logic_vector(2 downto 0);
wi_hwrite: in std_ulogic;
wi_haddr: in std_logic_vector(31 downto 0);
wi_hwdata: in std_logic_vector(AHBDW-1 downto 0);
wi_hmbsel: in std_logic_vector(0 to NAHBAMR-1);
wi_hmaster: in std_logic_vector(3 downto 0);
wi_hprot: in std_logic_vector(3 downto 0);
wi_hmastlock: in std_ulogic;
-- Wide-side slave outputs
wo_hready: out std_ulogic;
wo_hresp : out std_logic_vector(1 downto 0);
wo_hrdata: out std_logic_vector(AHBDW-1 downto 0);
-- Narrow-side slave inputs
ni_hready: out std_ulogic;
ni_htrans: out std_logic_vector(1 downto 0);
ni_hsize: out std_logic_vector(2 downto 0);
ni_hburst: out std_logic_vector(2 downto 0);
ni_hwrite: out std_ulogic;
ni_haddr: out std_logic_vector(31 downto 0);
ni_hwdata: out std_logic_vector(31 downto 0);
ni_hmbsel: out std_logic_vector(0 to NAHBAMR-1);
ni_hmaster: out std_logic_vector(3 downto 0);
ni_hprot : out std_logic_vector(3 downto 0);
ni_hmastlock: out std_ulogic;
-- Narrow-side slave outputs
no_hready: in std_ulogic;
no_hresp: in std_logic_vector(1 downto 0);
no_hrdata: in std_logic_vector(31 downto 0)
);
end component;
component ahbswba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_type;
ahbsi_slv: out ahb_slv_in_type;
ahbso_slv: in ahb_slv_out_type
);
end component;
component ahbswbav is
generic (
slvmask: integer;
ahbbits: integer;
blocksz: integer
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_vector;
ahbsi_slv: out ahb_slv_in_vector_type(NAHBSLV-1 downto 0);
ahbso_slv: in ahb_slv_out_vector
);
end component;
component ahbmwba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbmo_mst : in ahb_mst_out_type;
ahbmi_mst: out ahb_mst_in_type;
ahbmo_bus: out ahb_mst_out_type;
ahbmi_bus: in ahb_mst_in_type
);
end component;
-----------------------------------------------------------------------------
-- GRPULSE
-----------------------------------------------------------------------------
component grpulse
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1; -- Interrupt index
nchannel: Integer := 24; -- Number of channels
npulse: Integer := 8; -- Channels with pulses
imask: Integer := 16#ff0000#; -- Interrupt mask
ioffset: Integer := 8; -- Interrupt offset
invertpulse: Integer := 0; -- Invert pulses
cntrwidth: Integer := 10; -- Width of counter
syncrst: Integer := 1; -- Only synchronous reset
oepol: Integer := 1); -- Output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpioi: in gpio_in_type;
gpioo: out gpio_out_type);
end component;
-----------------------------------------------------------------------------
-- GRTIMER
-----------------------------------------------------------------------------
component grtimer is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1;
sepirq: Integer := 1; -- separate interrupts
sbits: Integer := 10; -- scaler bits
ntimers: Integer range 1 to 7 := 2; -- number of timers
nbits: Integer := 32; -- timer bits
wdog: Integer := 0;
glatch: Integer := 0;
gextclk: Integer := 0;
gset: Integer := 0);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpti: in gptimer_in_type;
gpto: out gptimer_out_type);
end component;
-----------------------------------------------------------------------------
-- GRVERSION
-----------------------------------------------------------------------------
component grversion
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
versionnr: Integer := 16#0123#;
revisionnr: Integer := 16#4567#);
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AHBFROM - Microsemi/Actel Flash ROM
-----------------------------------------------------------------------------
component ahbfrom is
generic (
tech: integer := 0;
hindex: integer := 0;
haddr: integer := 0;
hmask: integer := 16#fff#;
width8: integer := 0;
memoryfile: string := "from.mem";
progfile: string := "from.ufc");
port (
rstn: in std_ulogic;
clk: in std_ulogic;
ahbi: in ahb_slv_in_type;
ahbo: out ahb_slv_out_type);
end component;
-----------------------------------------------------------------------------
-- Interrupt generator
-----------------------------------------------------------------------------
component irqgen
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ngen : integer range 1 to 15 := 1
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
-- function nandtree(v : std_logic_vector) return std_ulogic;
end;
package body misc is
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_membar(memaddr, prefetch, cache, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_iobar(memaddr, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
-- function nandtree(v : std_logic_vector) return std_ulogic is
-- variable a : std_logic_vector(v'length-1 downto 0);
-- variable b : std_logic_vector(v'length downto 0);
-- begin
--
-- a := v; b(0) := '1';
--
-- for i in 0 to v'length-1 loop
-- b(i+1) := a(i) nand b(i);
-- end loop;
--
-- return b(v'length);
--
-- end;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml403/config.vhd | 1 | 6294 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (13);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (1);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (0);
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (14);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/uart/libdcom.vhd | 1 | 5314 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libdcom
-- File: libdcom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Types, functions and components for DSU uart
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.uart.all;
use gaisler.misc.all;
package libdcom is
type dcom_uart_in_type is record
read : std_ulogic;
write : std_ulogic;
data : std_logic_vector(7 downto 0);
end record;
type dcom_uart_out_type is record
dready : std_ulogic;
tsempty : std_ulogic;
thempty : std_ulogic;
lock : std_ulogic;
enable : std_ulogic;
data : std_logic_vector(7 downto 0);
end record;
component dcom_uart
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ui : in uart_in_type;
uo : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in dcom_uart_in_type;
uarto : out dcom_uart_out_type
);
end component;
component dcom
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : out ahb_dma_in_type;
dmao : in ahb_dma_out_type;
uarti : out dcom_uart_in_type;
uarto : in dcom_uart_out_type;
ahbi : in ahb_mst_in_type
);
end component;
-- pragma translate_off
procedure rxc(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time);
procedure rxi(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time; lresp : boolean);
procedure txc(signal txd : out std_logic; td : integer;
txperiod : time);
procedure txa(signal txd : out std_logic; td1, td2, td3, td4 : integer;
txperiod : time);
procedure txi(signal rxd : in std_logic; signal txd : out std_logic;
td1, td2, td3, td4 : integer; txperiod : time;
lresp : boolean);
-- pragma translate_on
end;
-- pragma translate_off
package body libdcom is
procedure rxc(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time) is
variable rxdata : std_logic_vector(7 downto 0);
begin
wait until rxd = '0'; wait for TXPERIOD/2;
for i in 0 to 7 loop wait for TXPERIOD; rxdata(i):= rxd; end loop;
wait for TXPERIOD ;
d := rxdata;
end;
procedure rxi(signal rxd : in std_logic; d: out std_logic_vector;
txperiod : time; lresp : boolean) is
variable rxdata : std_logic_vector(31 downto 0);
variable resp : std_logic_vector(7 downto 0);
begin
for i in 3 downto 0 loop
rxc(rxd, rxdata((i*8 +7) downto i*8), txperiod);
end loop;
d := rxdata;
if LRESP then
rxc(rxd, resp, txperiod);
-- print("RESP : 0x" & tosth(resp));
end if;
end;
procedure txc(signal txd : out std_logic; td : integer;
txperiod : time) is
variable txdata : std_logic_vector(10 downto 0);
begin
txdata := "11" & conv_std_logic_vector(td, 8) & '0';
for i in 0 to 10 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
end;
procedure txa(signal txd : out std_logic; td1, td2, td3, td4 : integer;
txperiod : time) is
variable txdata : std_logic_vector(43 downto 0);
begin
txdata := "11" & conv_std_logic_vector(td4, 8) & '0'
& "11" & conv_std_logic_vector(td3, 8) & '0'
& "11" & conv_std_logic_vector(td2, 8) & '0'
& "11" & conv_std_logic_vector(td1, 8) & '0';
for i in 0 to 43 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
end;
procedure txi(signal rxd : in std_logic; signal txd : out std_logic;
td1, td2, td3, td4 : integer; txperiod : time;
lresp : boolean) is
variable txdata : std_logic_vector(43 downto 0);
begin
txdata := "11" & conv_std_logic_vector(td4, 8) & '0'
& "11" & conv_std_logic_vector(td3, 8) & '0'
& "11" & conv_std_logic_vector(td2, 8) & '0'
& "11" & conv_std_logic_vector(td1, 8) & '0';
for i in 0 to 43 loop wait for TXPERIOD ; txd <= txdata(i); end loop;
if LRESP then
rxc(rxd, txdata(7 downto 0), txperiod);
-- print("RESP : 0x" & tosth(txdata(7 downto 0)));
end if;
end;
end;
-- pragma translate_on
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-asic/testbench.vhd | 1 | 14731 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use gaisler.jtagtst.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 20; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2; -- number of ram banks
testen : integer := 0;
scanen : integer := 0;
testrst : integer := 0;
testoen : integer := 0
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal cb : std_logic_vector(15 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdogn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic := '0';
signal lock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal roen, roout, nandout, promedac : std_ulogic;
constant lresp : boolean := false;
signal gnd : std_logic_vector(3 downto 0);
signal clksel : std_logic_vector(1 downto 0);
signal prom32 : std_ulogic;
signal spw_clksel : std_logic_vector(1 downto 0);
signal spw_clk : std_ulogic := '0';
signal spw_rxd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal i2c_scl : std_ulogic;
signal i2c_sda : std_ulogic;
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
signal spi_sck : std_logic;
signal spi_slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal trst,tck,tms,tdi,tdo: std_ulogic;
signal gtx_clk : std_ulogic := '0';
signal erx_clk : std_ulogic;
signal erxd : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal etx_clk : std_ulogic;
signal etxd : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal emdint : std_ulogic;
signal emdio : std_logic;
signal emdc : std_ulogic;
begin
-- clock and reset
test <= '0' when testen = 0 else '1';
rxd1 <= '1' when (testen = 1) and (testoen = 1) else
'0' when (testen = 1) and (testoen = 0) else txd1;
dsuen <= '1' when (testen = 1) and (testrst = 1) else
'0' when (testen = 1) and (testrst = 0) else '1', '0' after 1500 ns;
dsubre <= '1' when (testen = 1) and (scanen = 1) else
-- '0' when (testen = 1) and (scanen = 0) else '1';
'0' when (testen = 1) and (scanen = 0) else '0';
clksel <= "00";
spw_clksel <= "00";
error <= 'H';
gnd <= "0000";
clk <= not clk after ct * 1 ns;
spw_clk <= not spw_clk after ct * 1 ns;
gtx_clk <= not gtx_clk after 8 ns;
rst <= dsurst;
bexcn <= '1'; wdogn <= 'H';
gpio(2 downto 0) <= "HHL";
-- gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
gpio(15 downto 11) <= "HLLHH"; --19
gpio(10 downto 8) <= "HLL"; --4
gpio(7 downto 0) <= (others => 'L');
cb(15 downto 8) <= "HHHHHHHH";
spw_rxd <= spw_txd; spw_rxs <= spw_txs;
roen <= '0';
promedac <= '0';
prom32 <= '1';
rxd2 <= txd2;
d3 : entity work.leon3mp
generic map (
fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (
rst, clksel, clk, lock, error, wdogn, address, data,
cb(7 downto 0), sdclk, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact,
txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
i2c_scl, i2c_sda,
spi_miso, spi_mosi, spi_sck, spi_slvsel,
prom32,
spw_clksel, spw_clk, spw_rxd, spw_rxs, spw_txd, spw_txs,
gtx_clk, erx_clk, erxd, erx_dv, etx_clk, etxd, etx_en, etx_er, erx_er, erx_col, erx_crs, emdint, emdio, emdc ,
test, trst, tck, tms, tdi, tdo);
-- optional sdram
sdcke <= "11";
sd0 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
emdint <= '0';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 0,
base1000_x_hd => 0,
base1000_t_fd => 0,
base1000_t_hd => 0,
rmii => 0,
rgmii => 0
)
port map(rst, emdio, etx_clk, erx_clk, erxd,
erx_dv, erx_er, erx_col, erx_crs, etxd,
etx_en, etx_er, emdc, gtx_clk);
end generate;
spimem0: if (CFG_SPICTRL_ENABLE = 1) generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0)
port map (spi_sck, spi_mosi, spi_miso, spi_slvsel(0));
end generate spimem0;
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
bst0: process
begin
trst <= '0';
tck <= '0';
tms <= '1';
tdi <= '0';
wait for 2500 ns;
trst <= '1';
if to_x01(error) = '1' then wait on error; end if;
if CFG_BOUNDSCAN_EN /= 0 then bscantest(tdo,tck,tms,tdi,10); end if;
assert false
report "*** IU in error mode, simulation halted ***"
severity failure ;
wait;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
cb <= buskeep(cb) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := clkperiod*16 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait; -- remove to run the DSU UART
wait for 5010 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#06#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/altera_mf/clkgen_altera_mf.vhd | 1 | 7109 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity altera_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of altera_pll is
component altpll
generic (
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
extclk0_multiply_by : positive := 1;
extclk0_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
extclkena : in std_logic_vector(3 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
extclk : out std_logic_vector(3 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
signal extclk : std_logic_vector (3 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 2) <= (others => '0');
noclk2xgen: if (clk2xen = 0) generate clkena(1 downto 0) <= "01"; end generate;
clk2xgen: if (clk2xen /= 0) generate clkena(1 downto 0) <= "11"; end generate;
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1); e0 <= extclk(0);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_altera_mf is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_altera_mf is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
-- altera pll
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
e0 : out std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : altera_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_altera" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_altera" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-digilent-xc7z020/leon3_zedboard_stub_sim.vhd | 3 | 9633 | -------------------------------------------------------------------------------
-- leon3_zedboard_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity leon3_zedboard_stub is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_arready : out STD_LOGIC;
S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arvalid : in STD_LOGIC;
S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_awready : out STD_LOGIC;
S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awvalid : in STD_LOGIC;
S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_bready : in STD_LOGIC;
S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_bvalid : out STD_LOGIC;
S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_rlast : out STD_LOGIC;
S_AXI_GP0_rready : in STD_LOGIC;
S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_rvalid : out STD_LOGIC;
S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_wlast : in STD_LOGIC;
S_AXI_GP0_wready : out STD_LOGIC;
S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_wvalid : in STD_LOGIC
);
end leon3_zedboard_stub;
architecture STRUCTURE of leon3_zedboard_stub is
signal clk : std_logic := '0';
signal clk0 : std_logic := '0';
signal clk1 : std_logic := '0';
signal rst : std_logic := '0';
type memstatetype is (idle, read1, read2, read3, write1, write2, write3);
type blane is array (0 to 2**18-1) of natural;
type memtype is array (0 to 3) of blane;
constant abits : integer := 20;
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**abits)-1)) of BYTE;
type regtype is record
memstate : memstatetype;
addr : integer;
arlen : integer;
mem : memtype;
rcnt : integer;
end record;
signal S_AXI_GP0_rvalid_i : std_logic;
signal r, rin : regtype;
begin
clk0 <= not clk0 after 6.0 ns; -- 83.33 MHz
clk1 <= not clk1 after 2.5 ns; -- 200 MHz
rst <= '1' after 1 us;
S_AXI_GP0_rvalid <= S_AXI_GP0_rvalid_i;
FCLK_CLK0 <= clk0;
clk <= clk0;
FCLK_CLK1 <= clk1;
-- FCLK_CLK2 <= clk2;
-- FCLK_CLK3 <= clk3;
FCLK_RESET0_N <= rst;
mem0 : process(clk)
variable MEMA : MEM;
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is "ram.srec";
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable memstate : memstatetype;
variable addr : integer;
-- variable len : integer;
-- variable mem : memtype;
variable rcnt : integer;
begin
if FIRST then
-- if clear = 1 then MEMA := (others => X"00"); end if;
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
recaddr(31 downto abits) := (others => '0');
ai := conv_integer(recaddr);
for i in 0 to 15 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
elsif rising_edge(clk) then
case memstate is
when idle =>
S_AXI_GP0_arready <= '0'; S_AXI_GP0_rvalid_i <= '0'; S_AXI_GP0_rlast <= '0';
S_AXI_GP0_awready <= '0'; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '0';
if S_AXI_GP0_arvalid = '1' then
memstate := read1; S_AXI_GP0_arready <= '1';
elsif S_AXI_GP0_awvalid = '1' then
memstate := write1; S_AXI_GP0_awready <= '1';
end if;
when read1 =>
addr:= conv_integer(S_AXI_GP0_araddr(19 downto 0));
len := conv_integer(S_AXI_GP0_arlen);
S_AXI_GP0_arready <= '0'; memstate := read2; rcnt := 23;
when read2 =>
if rcnt /= 0 then rcnt := rcnt - 1;
else
S_AXI_GP0_rvalid_i <= '1';
if len = 0 then S_AXI_GP0_rlast <= '1'; end if;
if (S_AXI_GP0_rready and S_AXI_GP0_rvalid_i) = '1' then
if len = 0 then
S_AXI_GP0_rlast <= '0'; S_AXI_GP0_rvalid_i <= '0';
memstate := idle;
else
addr := addr + 4; len := len - 1;
if len = 0 then S_AXI_GP0_rlast <= '1'; end if;
end if;
end if;
for i in 0 to 3 loop
S_AXI_GP0_rdata(i*8+7 downto i*8) <= MEMA(addr+3-i);
end loop;
end if;
when write1 =>
addr:= conv_integer(S_AXI_GP0_awaddr(19 downto 0));
len := conv_integer(S_AXI_GP0_awlen);
S_AXI_GP0_awready <= '0'; memstate := write2; rcnt := 0;
when write2 =>
if rcnt /= 0 then rcnt := rcnt - 1;
else
memstate := write3;
S_AXI_GP0_wready <= '1';
end if;
when write3 =>
if S_AXI_GP0_wvalid = '1' then
for i in 0 to 3 loop
if S_AXI_GP0_wstrb(i) = '1' then
MEMA(addr+3-i) := S_AXI_GP0_wdata(i*8+7 downto i*8);
end if;
end loop;
if (len = 0) or (S_AXI_GP0_wlast = '1') then
memstate := idle; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '1';
else
addr := addr + 1; len := len - 1;
end if;
end if;
when others =>
end case;
end if;
end process;
S_AXI_GP0_bid <= (others => '0');
S_AXI_GP0_bresp <= (others => '0');
S_AXI_GP0_rresp <= (others => '0');
S_AXI_GP0_rid <= (others => '0');
DDR_addr <= (others => '0');
DDR_ba <= (others => '0');
DDR_cas_n <= '0';
DDR_ck_n <= '0';
DDR_ck_p <= '0';
DDR_cke <= '0';
DDR_cs_n <= '0';
DDR_dm <= (others => '0');
DDR_dq <= (others => '0');
DDR_dqs_n <= (others => '0');
DDR_dqs_p <= (others => '0');
DDR_odt <= '0';
DDR_ras_n <= '0';
DDR_reset_n <= '0';
DDR_we_n <= '0';
FIXED_IO_ddr_vrn <= '0';
FIXED_IO_ddr_vrp <= '0';
FIXED_IO_mio <= (others => '0');
FIXED_IO_ps_clk <= '0';
FIXED_IO_ps_porb <= '0';
FIXED_IO_ps_srstb <= '0';
end architecture STRUCTURE;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/fmf/flash/flash.vhd | 3 | 5307 | library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.ALL;
USE ieee.vital_primitives.ALL;
library fmf;
use fmf.gen_utils.all;
use fmf.conversions.all;
package flash is
component s25fl064a
generic (
tipd_SCK : VitalDelayType01 := VitalZeroDelay01;
tipd_SI : VitalDelayType01 := VitalZeroDelay01;
tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
tpd_SCK_SO : VitalDelayType01Z := UnitDelay01Z;
tpd_CSNeg_SO : VitalDelayType01Z := UnitDelay01Z;
tpd_HOLDNeg_SO : VitalDelayType01Z := UnitDelay01Z;
tsetup_SI_SCK : VitalDelayType := UnitDelay;
tsetup_CSNeg_SCK : VitalDelayType := UnitDelay;
tsetup_HOLDNeg_SCK : VitalDelayType := UnitDelay;
tsetup_WNeg_CSNeg : VitalDelayType := UnitDelay;
thold_SI_SCK : VitalDelayType := UnitDelay;
thold_CSNeg_SCK : VitalDelayType := UnitDelay;
thold_HOLDNeg_SCK : VitalDelayType := UnitDelay;
thold_WNeg_CSNeg : VitalDelayType := UnitDelay;
tpw_SCK_posedge : VitalDelayType := UnitDelay;
tpw_SCK_negedge : VitalDelayType := UnitDelay;
tpw_CSNeg_posedge : VitalDelayType := UnitDelay;
tperiod_SCK_rd : VitalDelayType := UnitDelay;
tperiod_SCK_fast_rd : VitalDelayType := UnitDelay;
tdevice_PP : VitalDelayType := 3 ms;
tdevice_SE : VitalDelayType := 3 sec;
tdevice_BE : VitalDelayType := 384 sec;
tdevice_WR : VitalDelayType := 60 ms;
tdevice_DP : VitalDelayType := 3 us;
tdevice_RES : VitalDelayType := 30 us;
tdevice_PU : VitalDelayType := 10 ms;
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
mem_file_name : STRING := "s25fl064a.mem";
UserPreload : BOOLEAN := FALSE;
LongTimming : BOOLEAN := TRUE;
TimingModel : STRING := DefaultTimingModel
);
port (
SCK : IN std_ulogic := 'U';
SI : IN std_ulogic := 'U';
CSNeg : IN std_ulogic := 'U';
HOLDNeg : IN std_ulogic := 'U';
WNeg : IN std_ulogic := 'U';
SO : OUT std_ulogic := 'U'
);
end component;
component m25p80
generic (
tipd_C : VitalDelayType01 := VitalZeroDelay01;
tipd_D : VitalDelayType01 := VitalZeroDelay01;
tipd_SNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
tpd_C_Q : VitalDelayType01 := UnitDelay01;
tpd_SNeg_Q : VitalDelayType01Z := UnitDelay01Z;
tpd_HOLDNeg_Q : VitalDelayType01Z := UnitDelay01Z;
tsetup_D_C : VitalDelayType := UnitDelay;
tsetup_SNeg_C : VitalDelayType := UnitDelay;
tsetup_HOLDNeg_C : VitalDelayType := UnitDelay;
tsetup_C_HOLDNeg : VitalDelayType := UnitDelay;
tsetup_WNeg_SNeg : VitalDelayType := UnitDelay;
thold_D_C : VitalDelayType := UnitDelay;
thold_SNeg_C : VitalDelayType := UnitDelay;
thold_HOLDNeg_C : VitalDelayType := UnitDelay;
thold_C_HOLDNeg : VitalDelayType := UnitDelay;
thold_WNeg_SNeg : VitalDelayType := UnitDelay;
tpw_C_posedge : VitalDelayType := UnitDelay;
tpw_C_negedge : VitalDelayType := UnitDelay;
tpw_SNeg_posedge : VitalDelayType := UnitDelay;
tperiod_C_rd : VitalDelayType := UnitDelay;
tperiod_C_fast_rd : VitalDelayType := UnitDelay;
tdevice_PP : VitalDelayType := 5 ms;
tdevice_SE : VitalDelayType := 3 sec;
tdevice_BE : VitalDelayType := 20 sec;
tdevice_WR : VitalDelayType := 15 ms;
tdevice_DP : VitalDelayType := 3 us;
tdevice_RES1 : VitalDelayType := 3 us;
tdevice_RES2 : VitalDelayType := 1.8 us;
tdevice_VSL : VitalDelayType := 10 us;
tdevice_PUW : VitalDelayType := 10 ms;
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
mem_file_name : STRING := "m25p80.mem";
UserPreload : BOOLEAN := FALSE;
DebugInfo : BOOLEAN := FALSE;
LongTimming : BOOLEAN := TRUE;
TimingModel : STRING := DefaultTimingModel
);
port (
C : IN std_ulogic := 'U';
D : IN std_ulogic := 'U';
SNeg : IN std_ulogic := 'U';
HOLDNeg : IN std_ulogic := 'U';
WNeg : IN std_ulogic := 'U';
Q : OUT std_ulogic := 'U'
);
end component;
end flash;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/eth/wrapper/greth_gen.vhd | 1 | 13863 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gen
-- File: greth_gen.vhd
-- Author: Marko Isomaki
-- Description: Generic Ethernet MAC
------------------------------------------------------------------------------
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library eth;
use eth.ethcomp.all;
entity greth_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 31 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic
);
end entity;
architecture rtl of greth_gen is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl = 1) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahbg,
ramdebug => ramdebug,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ehgrant,
ehready => ehready,
ehresp => ehresp,
ehrdata => ehrdata,
--edcl ahb mst out
ehbusreq => ehbusreq,
ehlock => ehlock,
ehtrans => ehtrans,
ehaddr => ehaddr,
ehwrite => ehwrite,
ehsize => ehsize,
ehburst => ehburst,
ehprot => ehprot,
ehwdata => ehwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => rmii_clk,
tx_clk => tx_clk,
tx_dv => tx_dv,
rx_clk => rx_clk,
rxd => rxd(3 downto 0),
rx_dv => rx_dv,
rx_er => rx_er,
rx_col => rx_col,
rx_en => rx_en,
rx_crs => rx_crs,
mdio_i => mdio_i,
phyrstaddr => phyrstaddr,
mdint => mdint,
--ethernet output signals
reset => reset,
txd => txd(3 downto 0),
tx_en => tx_en,
tx_er => tx_er,
mdc => mdc,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
--scantest
testrst => testrst,
testen => testen,
testoen => testoen,
edcladdr => edcladdr,
edclsepahb => edclsepahb,
edcldisable => edcldisable,
speed => speed);
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
ft1 : if ft /= 0 generate
tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
edclramft1 : if (edcl /= 0) and (edclft /= 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
end architecture;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/arith/arith.vhd | 1 | 4771 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: arith
-- File: arith.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Declaration of mul/div components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package arith is
type div32_in_type is record
y : std_logic_vector(32 downto 0); -- Y (MSB divident)
op1 : std_logic_vector(32 downto 0); -- operand 1 (LSB divident)
op2 : std_logic_vector(32 downto 0); -- operand 2 (divisor)
flush : std_logic;
signed : std_logic;
start : std_logic;
end record;
type div32_out_type is record
ready : std_logic;
nready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(31 downto 0); -- div result
end record;
type mul32_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
acc : std_logic_vector(39 downto 0);
--y : std_logic_vector(7 downto 0); -- Y (MSB MAC register)
--asr18 : std_logic_vector(31 downto 0); -- LSB MAC register
end record;
type mul32_out_type is record
ready : std_logic;
nready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(63 downto 0); -- mul result
end record;
component div32
generic (scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
divi : in div32_in_type;
divo : out div32_out_type;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1'
);
end component;
component mul32
generic (
tech : integer := 0;
multype : integer := 0;
pipe : integer := 0;
mac : integer := 0;
arch : integer range 0 to 3 := 0;
scantest: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
muli : in mul32_in_type;
mulo : out mul32_out_type;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1'
);
end component;
function smult ( a, b : in std_logic_vector) return std_logic_vector;
function umult ( a, b : in std_logic_vector) return std_logic_vector;
end;
package body arith is
function smult ( a, b : in std_logic_vector) return std_logic_vector is
variable sa : signed (a'length-1 downto 0);
variable sb : signed (b'length-1 downto 0);
variable sc : signed ((a'length + b'length) -1 downto 0);
variable res : std_logic_vector ((a'length + b'length) -1 downto 0);
begin
sa := signed(a); sb := signed(b);
-- pragma translate_off
if is_x(a) or is_x(b) then
sc := (others => 'X');
else
-- pragma translate_on
sc := sa * sb;
-- pragma translate_off
end if;
-- pragma translate_on
res := std_logic_vector(sc);
return(res);
end;
function umult ( a, b : in std_logic_vector) return std_logic_vector is
variable sa : unsigned (a'length-1 downto 0);
variable sb : unsigned (b'length-1 downto 0);
variable sc : unsigned ((a'length + b'length) -1 downto 0);
variable res : std_logic_vector ((a'length + b'length) -1 downto 0);
begin
sa := unsigned(a); sb := unsigned(b);
-- pragma translate_off
if is_x(a) or is_x(b) then
sc := (others => 'X');
else
-- pragma translate_on
sc := sa * sb;
-- pragma translate_off
end if;
-- pragma translate_on
res := std_logic_vector(sc);
return(res);
end;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-sp605/leon3mp.vhd | 1 | 35477 | -----------------------------------------------------------------------------
-- LEON3 Xilinx SP605 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.ODDR2;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.pcie.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk27 : in std_ulogic; -- 27 MHz clock
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
clk33 : in std_ulogic; -- 32 MHz clock from sysace
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_reset_n : out std_logic;
ddr_we : out std_ulogic; -- ddr write enable
ddr_ras : out std_ulogic; -- ddr ras
ddr_cas : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_dqs_n : inout std_logic_vector (1 downto 0); -- ddr dqs_n
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 ctsn
rtsn1 : out std_ulogic; -- UART1 trsn
button : inout std_logic_vector(3 downto 0); -- I/O port
switch : inout std_logic_vector(3 downto 0); -- I/O port
led : out std_logic_vector(3 downto 0); -- I/O port
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_mii_int_n : in std_ulogic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
ddc_scl : inout std_ulogic;
ddc_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic;
--pcie
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
--attribute syn_netlist_hierarchy : boolean;
--attribute syn_netlist_hierarchy of rtl : architecture is false;
component ODDR2
generic (
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port (
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic := 'H';
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic := 'L';
S : in std_ulogic := 'L'
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG+CFG_PCIEXP;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal egtx_clk :std_ulogic;
signal negtx_clk :std_ulogic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk : std_ulogic;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal spmi2 : spimctrl_in_type;
signal spmo2 : spimctrl_out_type;
constant BOARD_FREQ : integer := 33000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_GRACECTRL;
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
signal video_clk : std_ulogic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
ethclk <= lclk;
clk_pad : clkpad generic map (tech => padtech) port map (clk33, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, open, open);
reset_pad : inpad generic map (tech => padtech) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, lock, rstn, rstraw);
lock <= cgo.clklock and calib_done when CFG_MIG_DDR2 = 1 else cgo.clklock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
led1_pad : odpad generic map (tech => padtech) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= button(3);
dsuact_pad : outpad generic map (tech => padtech) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl_gen : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(24 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 16)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc); --ahbso(0) <= ahbso_none;
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_sp605 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 4, paddr => 4,
vgamst => CFG_SVGA_ENABLE, vgaburst => 64)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_reset_n=> ddr_reset_n,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n=> ddr_dqs_n(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqs_n(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
ahbmi => vahbmi,
ahbmo => vahbmo,
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_p => clk200p,
clk_mem_n => clk200n,
clk_125 => egtx_clk,
clk_50 => video_clk
);
end generate;
led(2) <= calib_done;
led(3) <= lock;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP:pcie_master_target_sp605
generic map (
master => CFG_PCIE_SIM_MAS,
hmstndx => CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG,
hslvndx => 7,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
nsync => 2, -- 1 or 2 sync regs between clocks
pcie_bar_mask => 16#FFE#,
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(7),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG)
);
end generate;
----------------------------------------------------------------------
-----------------PCI-EXPRESS-Master-FIFO------------------------------------------
pcie_mf_dma : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG,
dapbndx => 7, dapbaddr => 7,dapbmask => 16#FFF#, dapbirq => 4, blength => 12,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
slvndx => 7, apbndx => 5, apbaddr => 5, apbmask =>16#FFF#, haddr => 16#A00#, hmask => 16#FFF#,
nsync => 2, pcie_bar_mask => 16#FFE#
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(7),
dahbmo =>ahbmo(CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG),
apbi =>apbi,
apbo =>apbo(5),
ahbmi =>ahbmi,
ahbsi =>ahbsi,
ahbso =>ahbso(7)
);
end generate;
pcie_mf: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_sp605
generic map (
memtech => memtech,
hslvndx => 7,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
nsync => 2, -- 1 or 2 sync regs between clocks
pcie_bar_mask => 16#FFE#,
haddr => 16#A00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#)
port map(
rst => rstn,
clk => clkm,
-- System In
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Expre
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(7),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5)
);
end generate;
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 5, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(16);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, '0');
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, '0');
end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 8, hirq => 10,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT, mode => 2)
port map (rstn, clkm, lclk, ahbsi, ahbso(8), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (tech => padtech, width => 8)
port map (sysace_d, aceo.do(7 downto 0), aceo.doen, acei.di(7 downto 0));
acei.di(15 downto 8) <= (others => '0');
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => 0)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
-- video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_JTAG,
clk0 => 20000, clk1 => 0, --1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 0, clk3 => 0, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, vahbmi,
vahbmo, clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
-- b0 : techbuf generic map (2, fabtech) port map (clk50, video_clk);
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (clkm, vgao, video_clk, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 11)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 3 generate
pio_pad : iopad generic map (tech => padtech)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 4 to 6 generate
pio_pad : iopad generic map (tech => padtech)
port map (button(i-4), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
negtx_clk <= not egtx_clk;
x0 : ODDR2 port map ( Q => phy_gtx_clk, C0 => egtx_clk,
C1 => negtx_clk, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
e1 : grethm generic map( hindex => CFG_NCPU+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_JTAG), apbi => apbi, apbo => apbo(14),
ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_mii_int_n, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG+CFG_PCIEXP) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx SP605 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep3sl150/testbench.vhd | 1 | 12987 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Altera Stratix-III LEON3 Demonstration design test bench
-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1; -- number of ram banks
dbits : integer := CFG_DDR2SP_DATAWIDTH
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
constant lresp : boolean := false;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal Rst : std_logic := '0'; -- Reset
signal clk : std_logic := '0';
signal clk125 : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal txd1, rxd1 : std_ulogic;
-- PSRAM and FLASH control
signal sram_advn : std_logic;
signal sram_csn : std_logic;
signal sram_wen : std_logic;
signal sram_ben : std_logic_vector (0 to 3);
signal sram_oen : std_ulogic;
signal sram_clk : std_ulogic;
signal sram_adscn : std_ulogic;
signal sram_psn : std_ulogic;
signal sram_adv_n : std_ulogic;
signal sram_wait : std_logic_vector(1 downto 0);
signal flash_clk, flash_cen, max_csn : std_logic;
signal flash_advn, flash_oen, flash_resetn, flash_wen : std_logic;
-- DDR2 memory
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (8 downto 0); -- ddr dm
signal ddr_dqsp : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (15 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (2 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (71 downto 0); -- ddr data
signal ddr_dq2 : std_logic_vector (71 downto 0); -- ddr data
--signal ddra_cke : std_logic;
--signal ddra_csb : std_logic;
--signal ddra_web : std_ulogic; -- ddr write enable
--signal ddra_rasb : std_ulogic; -- ddr ras
--signal ddra_casb : std_ulogic; -- ddr cas
--signal ddra_ad : std_logic_vector (15 downto 0); -- ddr address
--signal ddra_ba : std_logic_vector (2 downto 0); -- ddr bank address
--signal ddrb_cke : std_logic;
--signal ddrb_csb : std_logic;
--signal ddrb_web : std_ulogic; -- ddr write enable
--signal ddrb_rasb : std_ulogic; -- ddr ras
--signal ddrb_casb : std_ulogic; -- ddr cas
--signal ddrb_ad : std_logic_vector (15 downto 0); -- ddr address
--signal ddrb_ba : std_logic_vector (2 downto 0); -- ddr bank address
--signal ddrab_clk : std_logic_vector(1 downto 0);
--signal ddrab_clkb : std_logic_vector(1 downto 0);
--signal ddrab_odt : std_logic_vector(1 downto 0);
--signal ddrab_dqsp : std_logic_vector(1 downto 0); -- ddr dqs
--signal ddrab_dqsn : std_logic_vector(1 downto 0); -- ddr dqs
--signal ddrab_dm : std_logic_vector(1 downto 0); -- ddr dm
--signal ddrab_dq : std_logic_vector (15 downto 0);-- ddr data
-- Ethernet
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk125 <= not clk125 after 4 * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
address(0) <= '0';
ddr_dq(71 downto dbits) <= (others => 'H');
ddr_dq2(71 downto dbits) <= (others => 'H');
ddr_dqsp(8 downto dbits/8) <= (others => 'H');
ddr_dqsn(8 downto dbits/8) <= (others => 'H');
ddr_rdqs(8 downto dbits/8) <= (others => 'H');
ddr_dm(8 downto dbits/8) <= (others => 'H');
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow, 50000, dbits)
port map (rst, clk, clk125, error, dsubren, dsuact,
-- rxd1, txd1,
gpio, address(25 downto 1), data, open,
sram_advn, sram_csn, sram_wen, sram_ben, sram_oen, sram_clk, sram_psn, sram_wait,
flash_clk, flash_advn, flash_cen, flash_oen, flash_resetn, flash_wen,
max_csn, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web,
ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq,
open, open,
-- ddra_cke, ddra_csb, ddra_web, ddra_rasb, ddra_casb, ddra_ad(14 downto 0), ddra_ba, ddrb_cke,
-- ddrb_csb, ddrb_web, ddrb_rasb, ddrb_casb, ddrb_ad(14 downto 0), ddrb_ba, ddrab_clk, ddrab_clkb,
-- ddrab_odt, ddrab_dqsp, ddrab_dqsn, ddrab_dm, ddrab_dq,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n
);
ddr2delay : delay_wire
generic map(data_width => dbits, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => ddr_dq(dbits-1 downto 0), b => ddr_dq2(dbits-1 downto 0));
ddr0 : ddr2ram
generic map(width => dbits, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0),
odt => ddr_odt(0), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm(dbits/8-1 downto 0), ba => ddr_ba(1 downto 0),
a => ddr_ad(12 downto 0), dq => ddr_dq2(dbits-1 downto 0),
dqs => ddr_dqsp(dbits/8-1 downto 0), dqsn =>ddr_dqsn(dbits/8-1 downto 0));
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31 downto 16),
gnd, gnd, flash_cen, flash_wen, flash_oen);
-- -- 32 bit prom
-- prom0 : for i in 0 to 3 generate
-- sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
-- port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), flash_cen,
-- flash_wen, flash_oen);
-- end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), sram_csn,
sram_wen, sram_oen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, sram_oen, sram_wen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 |
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