repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
Project-Bonfire/EHA | RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/New_SHMU_on_Node/LBDR_packet_drop_checkers/Cx_Reconf_pseudo_checkers.vhd | 9 | 7729 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in /= '0') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (reconfig_cx_in /= '1') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Cx_reconf_PE)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (Temp_Cx_in /= Cx_reconf_PE) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
end; | gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e_@p@p@e_@s@s@e_@c@t@r@l/_primary.vhd | 3 | 1007 | library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_SSE_CTRL is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
xfer_din_mux : in vl_logic_vector(31 downto 0);
PPE2SSE_PADDR_reg_move_target: in vl_logic;
PPE2SSE_PWDATA_LSB_reg_move_target: in vl_logic;
PPE2SSE_PWDATA_MSB_reg_move_target: in vl_logic;
PPE2SSE_wr : in vl_logic;
PPE2SSE_rd_hold_en: in vl_logic;
PPE2SSE_sel : in vl_logic;
PPE2SSE_en : in vl_logic;
PPE2SSE_PRDATA : in vl_logic_vector(15 downto 0);
PPE2SSE_PSEL : out vl_logic;
PPE2SSE_PENABLE : out vl_logic;
PPE2SSE_PWRITE : out vl_logic;
PPE2SSE_PADDR : out vl_logic_vector(11 downto 0);
PPE2SSE_PWDATA : out vl_logic_vector(15 downto 0);
PPE2SSE_PRDATA_rdhold: out vl_logic_vector(15 downto 0)
);
end F2DSS_ACE_PPE_SSE_CTRL;
| gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e_@m@i@s@c_@f@d@e@t12/_primary.vhd | 3 | 330 | library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_FDET12 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic_vector(11 downto 0);
FALL : out vl_logic_vector(11 downto 0)
);
end F2DSS_ACE_MISC_FDET12;
| gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/read_analog_io/_primary.vhd | 3 | 253 | library verilog;
use verilog.vl_types.all;
entity read_analog_io is
port(
serial_in : in vl_logic;
read_enb : in vl_logic;
parallel_out : out vl_logic_vector(63 downto 0)
);
end read_analog_io;
| gpl-3.0 |
quicky2000/top_mandelbrot_1b | mandel_loop.vhd | 1 | 3829 | --
-- This file is part of top_mandelbrot_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mandel_loop is
Port ( clk : in std_logic;
rst : std_logic;
x : in STD_LOGIC_VECTOR (15 downto 0);
y : in STD_LOGIC_VECTOR (15 downto 0);
nb_iter_max : in STD_LOGIC_VECTOR (5 downto 0);
ok : out STD_LOGIC;
ready : out std_logic);
end mandel_loop;
architecture Behavioral of mandel_loop is
signal x_n_plus_1 : std_logic_vector(15 downto 0) := (others => '0'); -- x * x
signal y_n_plus_1 : std_logic_vector(15 downto 0) := (others => '0'); -- y * y
signal x_n : std_logic_vector(15 downto 0) := (others => '0'); -- x * x
signal y_n : std_logic_vector(15 downto 0) := (others => '0'); -- y * y
signal x_square_in : std_logic_vector(15 downto 0) := (others => '0'); -- x * y
signal y_square_in : std_logic_vector(15 downto 0) := (others => '0'); -- x * y
signal x_square_out : std_logic_vector(15 downto 0) := (others => '0'); -- x * y
signal y_square_out : std_logic_vector(15 downto 0) := (others => '0'); -- x * y
begin
x_x_mult : entity work.mult_16_8
port map (
a => x_square_in,
b => x_square_in,
p => x_square_out);
y_y_mult : entity work.mult_16_8
port map (
a => y_square_in,
b => y_square_in,
p => y_square_out);
inst_mandel_iter : entity work.mandel_iter
port map (
x_n => x_n,
y_n => y_n,
x_square_in => x_square_out,
y_square_in => y_square_out,
a => x,
b => y,
x_n_plus_1 => x_n_plus_1,
y_n_plus_1 => y_n_plus_1);
compute_process : process (clk, rst)
variable l_nb_iter : natural range 0 to 127:= 0; -- current iteration
begin -- process compute_process
if rising_edge(clk) then -- rising clock edge
if rst = '1' then -- asynchronous reset (active low)
ok <= '0';
l_nb_iter := 0;
x_square_in <= x;
y_square_in <= y;
x_n <= x;
y_n <= y;
ready <= '0';
ok <= '0';
else
-- if l_nb_iter /= 0 then
x_square_in <= x_n_plus_1;
y_square_in <= y_n_plus_1;
x_n <= x_n_plus_1;
y_n <= y_n_plus_1;
-- else
-- x_square_in <= x;
-- y_square_in <= y;
-- end if;
if unsigned(x_square_out) + unsigned(y_square_out) > 16#400# then
ready <= '1';
ok <= '0';
else
if l_nb_iter /= unsigned(nb_iter_max) then
l_nb_iter := l_nb_iter +1;
ready <= '0';
ok <= '0';
else
ready <= '1';
ok <= '1';
end if;
end if;
end if ;
end if;
end process compute_process;
end Behavioral;
| gpl-3.0 |
Project-Bonfire/EHA | RTL/Router/credit_based/RTL/New_SHMU_on_Node/plasma.vhd | 3 | 15290 | ---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
-- 0x10000000 - 0x100fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been instantiated!
-- * some changes has been applied to the ports of the CPU to facilitate the new NI!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 0;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(7 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address, ram_address_late : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r, ram_data_r_ni : std_logic_vector(31 downto 0);
signal NI_irq_out : std_logic;
--signal NI_read_flag : std_logic;
--signal NI_write_flag : std_logic;
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
constant reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
constant reserved_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant reserved_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, ram_address_late, ram_data_r_ni,
data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w)
begin
case cpu_address(30 downto 28) is
when "000" => --internal RAM
if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address)
or (ram_address_late = reserved_counter_address)) then
cpu_data_r <= ram_data_r_ni;
else
cpu_data_r <= ram_data_r;
end if;
when "001" => --external RAM
if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address)
or (ram_address_late = reserved_counter_address)) then
cpu_data_r <= ram_data_r_ni;
else
cpu_data_r <= ram_data_r; --cache
end if;
else
cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others =>
cpu_data_r <= gpioA_in;
end case;
when "011" => --flash
cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO;
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
counter_reg <= bv_inc(counter_reg);
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
elsif cpu_address(6 downto 4) = "110" then
counter_reg <= cpu_data_w;
end if;
end if;
end if;
end if;
end process;
process(ram_address, reset, clk)begin
if reset = '1' then
ram_address_late <= (others => '0');
elsif clk'event and clk = '1' then
ram_address_late <= ram_address;
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w, data_read)
begin
if cache_access = '1' then --Check if cache hit or write through
ram_enable <= '1';
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & address_next(11 downto 2);
ram_data_w <= cpu_data_w;
elsif cache_miss = '1' then --Update cache after cache miss
ram_enable <= '1';
ram_byte_we <= "1111";
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & cpu_address(11 downto 2);
ram_data_w <= data_read;
else --Normal non-cache access
if address_next(30 downto 28) = "000" then
ram_enable <= '1';
else
ram_enable <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
u2_ram: ram
generic map (memory_type => memory_type, stim_file => stim_file)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r);
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail);
dma_gen: if ethernet = '0' generate
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
dma_gen2: if ethernet = '1' generate
u4_eth: eth_dma
port map(
clk => clk,
reset => reset,
enable_eth => gpio0_reg(24),
select_eth => enable_eth,
rec_isr => irq_eth_rec,
send_isr => irq_eth_send,
address => address, --to DDR
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => eth_pause_in,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
E_RX_CLK => gpioA_in(20),
E_RX_DV => gpioA_in(19),
E_RXD => gpioA_in(18 downto 15),
E_TX_CLK => gpioA_in(14),
E_TX_EN => gpio0_out(28),
E_TXD => gpio0_out(27 downto 24));
end generate;
u4_ni: NI
generic map(current_address => current_address, SHMU_address => 0)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r_ni,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
irq_out => NI_irq_out,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX,
link_faults => link_faults,
turn_faults => turn_faults,
Rxy_reconf_PE => Rxy_reconf_PE,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command
);
end; --architecture logic
| gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@d@s@s@a@b/_primary.vhd | 3 | 6424 | library verilog;
use verilog.vl_types.all;
entity DSSAB is
generic(
DAC_RESOLUTION : integer := 0
);
port(
DIGEN0 : in vl_logic;
DIGEN1 : in vl_logic;
DIGEN2 : in vl_logic;
DIGEN3 : in vl_logic;
DIGEN4 : in vl_logic;
DIGEN5 : in vl_logic;
DIGEN6 : in vl_logic;
DIGEN7 : in vl_logic;
DIGEN8 : in vl_logic;
DIGEN9 : in vl_logic;
DIGEN10 : in vl_logic;
DIGEN11 : in vl_logic;
DIGOUT0 : out vl_logic;
DIGOUT1 : out vl_logic;
DIGOUT2 : out vl_logic;
DIGOUT3 : out vl_logic;
DIGOUT4 : out vl_logic;
DIGOUT5 : out vl_logic;
DIGOUT6 : out vl_logic;
DIGOUT7 : out vl_logic;
DIGOUT8 : out vl_logic;
DIGOUT9 : out vl_logic;
DIGOUT10 : out vl_logic;
DIGOUT11 : out vl_logic;
ADCIN0 : in vl_logic;
ADCIN1 : in vl_logic;
ADCIN2 : in vl_logic;
ADCIN3 : in vl_logic;
ADCIN4 : in vl_logic;
ADCIN5 : in vl_logic;
ADCIN6 : in vl_logic;
ADCIN7 : in vl_logic;
ADCIN8 : in vl_logic;
ADCIN9 : in vl_logic;
ADCIN10 : in vl_logic;
ADCIN11 : in vl_logic;
DACOUT0 : out vl_logic;
DACOUT1 : out vl_logic;
DACOUT2 : out vl_logic;
AV1Q0 : in vl_logic;
AV1Q1 : in vl_logic;
AV1Q2 : in vl_logic;
AV1Q3 : in vl_logic;
AV1Q4 : in vl_logic;
AV1Q5 : in vl_logic;
AV2Q0 : in vl_logic;
AV2Q1 : in vl_logic;
AV2Q2 : in vl_logic;
AV2Q3 : in vl_logic;
AV2Q4 : in vl_logic;
AV2Q5 : in vl_logic;
ATQ0 : in vl_logic;
ATQ1 : in vl_logic;
ATQ2 : in vl_logic;
ATQ3 : in vl_logic;
ATQ4 : in vl_logic;
ATQ5 : in vl_logic;
ACQ0 : in vl_logic;
ACQ1 : in vl_logic;
ACQ2 : in vl_logic;
ACQ3 : in vl_logic;
ACQ4 : in vl_logic;
ACQ5 : in vl_logic;
ATRTN01 : in vl_logic;
ATRTN23 : in vl_logic;
ATRTN45 : in vl_logic;
VAREF0 : in vl_logic;
VAREF1 : in vl_logic;
VAREF2 : in vl_logic;
VAREFOUT : out vl_logic;
GNDREF : in vl_logic;
TVC0 : in vl_logic_vector(7 downto 0);
TVC1 : in vl_logic_vector(7 downto 0);
TVC2 : in vl_logic_vector(7 downto 0);
STC0 : in vl_logic_vector(7 downto 0);
STC1 : in vl_logic_vector(7 downto 0);
STC2 : in vl_logic_vector(7 downto 0);
MODE0 : in vl_logic_vector(3 downto 0);
MODE1 : in vl_logic_vector(3 downto 0);
MODE2 : in vl_logic_vector(3 downto 0);
VAREFSEL : in vl_logic;
START0 : in vl_logic;
START1 : in vl_logic;
START2 : in vl_logic;
PWRDWN0 : in vl_logic;
PWRDWN1 : in vl_logic;
PWRDWN2 : in vl_logic;
ADCRESET0 : in vl_logic;
ADCRESET1 : in vl_logic;
ADCRESET2 : in vl_logic;
CHNUMBER0 : in vl_logic_vector(4 downto 0);
CHNUMBER1 : in vl_logic_vector(4 downto 0);
CHNUMBER2 : in vl_logic_vector(4 downto 0);
BUSY0 : out vl_logic;
BUSY1 : out vl_logic;
BUSY2 : out vl_logic;
CALIBRATE0 : out vl_logic;
CALIBRATE1 : out vl_logic;
CALIBRATE2 : out vl_logic;
DATAVALID0 : out vl_logic;
DATAVALID1 : out vl_logic;
DATAVALID2 : out vl_logic;
SAMPLE0 : out vl_logic;
SAMPLE1 : out vl_logic;
SAMPLE2 : out vl_logic;
RESULT0 : out vl_logic_vector(11 downto 0);
RESULT1 : out vl_logic_vector(11 downto 0);
RESULT2 : out vl_logic_vector(11 downto 0);
ADCCLK0 : in vl_logic;
ADCCLK1 : in vl_logic;
ADCCLK2 : in vl_logic;
OBDIN0 : in vl_logic;
OBDIN1 : in vl_logic;
OBDIN2 : in vl_logic;
OBDCLK0 : in vl_logic;
OBDCLK1 : in vl_logic;
OBDCLK2 : in vl_logic;
OBDEN0 : in vl_logic;
OBDEN1 : in vl_logic;
OBDEN2 : in vl_logic;
ACMPOUT0 : out vl_logic;
ACMPOUT1 : out vl_logic;
ACMPOUT2 : out vl_logic;
ACMPOUT3 : out vl_logic;
ACMPOUT4 : out vl_logic;
ACMPOUT5 : out vl_logic;
ACMPOUT6 : out vl_logic;
ACMPOUT7 : out vl_logic;
ACMPOUT8 : out vl_logic;
ACMPOUT9 : out vl_logic;
ACMPOUT10 : out vl_logic;
ACMPOUT11 : out vl_logic;
ABPWRON : in vl_logic;
ACBRESET : in vl_logic;
ACBADDR : in vl_logic_vector(7 downto 0);
ACBWRE : in vl_logic;
ACBWDATA : in vl_logic_vector(7 downto 0);
ACBRDATA : out vl_logic_vector(7 downto 0)
);
end DSSAB;
| gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_v8_0_synth_comp.vhd | 9 | 18409 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Hrnq8dCJaKDcbWju4fCWpvTyG/jpOPI76yiyms4zR5rhP18uroxd2pidKHfd49ncBUe0MqqZynp4
90W9Rrrc/A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
C+vg4HAYcic4aGtZRxGMdzYD0fogeP7Z6MVwbh/q+v5PQNn91tf0Fe2jPpVduDUHCEn+fROm/5qv
HY5HNo7MmV7DyzFb0MzI1uxRMJ3VYZnG5tTtwEcxTvoEV5vP9EL19RhtKRBGVo4ZgVV5gGk0JKOF
+TqBUjFvIiA4vwpbMWk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
JzgROPSPVeAOVRLayuXSpdp1weNvhVEo91AUmW62iTMGytjydIGArwh/IlChZF3aEHMk+8YMqUam
Xk+SFFfqw+3hOxLduRdCs/0PE71UaAFke9g8pRLsAWRGhTcL3HjGGAoMD5XfprmZ7n0LPuo5e/Xr
FS6ENXD34CULnNTIC53qRXsWJ/P5hMwdUcUMedqpcjgwszObQs66Wr4Zln10aNzbmR4mFKXMYQWm
QbiZDff6DJw7m7dAy2eZGY3pNETlIASxB9c7Q6eX8oYoOBNO5HuBW4SBFoU7CpBabxn2JM71BtGs
YJW6BCHHtuXJ1WlJWrsxqTZRpoxSW2TNHd4p1Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
wUrFF/b01kfuHOSDIcBE3mA1IqhbqTBO8gfarlSE1mp/QLV+nqvxWRSJHOa0L8fx3h0xd3EXyWLV
otTsqh6P0/0U5990yziMzvmsCY5YjI94HV4U6pZPE06SgvnvmSDk8WtUXhCBMCitKLgwVUnzv7nL
yq7NeaZmrMyWKwH9bn8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
soDkukFMAh2Srgb+iZhmw1cTZfk1UzET6uR72TaeHvTRbZwA4tb9QP8RcQatKIw6L7eScVTDrS9G
TeYNjpJL/DzJm8yGgHbE++9FhpXm7gMc5SjxCchkAJI78G5j8MxjO4yKOkT9Bzi2dhU4TBKCmyb2
DA0vHWKmcuGWazGM/VMrGBaBtjHrjTZvrM/qUPOGDzpNncoJFtsoheP0gn/NR3/1da01ChgudW8l
neP9MXpNmmJfth4TBgYp4pnag8gMizcERWu16CHypd0TJmJDK+l1GAOeuTZsj4r4b1OpdnI+34sU
xpU9H+30x6Xg1yDD9xAPdrsS2lPiLKJt7ry9ww==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11888)
`protect data_block
OIINs9fnuccRyVNpUz9fi04o+5ToAci+VxRQlMhFFYei2XQRrnYajrdMXLI2q3AGF3NBeUa+tgCe
ItPXhDEmesTtP9ngvB4q3dDaQ4UIDPEN5tMiep6j6FcpFI7xLHBrI6mGQKhTuS6TTlGWzrmae7IJ
KKKuRbRzII7xl0CXIUilUrKwufm9G262phEERHKkAT5OFpRsRMx2oZik9aDIXfaVOOtZGEdPFiKA
QqlVTKQb+YPgUGSsPi2ytgp8HqlTbm5Bno1yov9u9W03tS/pp3ChugCnis3/g/67aHRQ2pUzAK5J
IUkS8p5rIqtSiV1AdACs2ThfJ1KfiU/QCNp4p4zlG4NFaW+UPYqOUbDUzi8919aXrCPxiMUvjBFr
3A4pCqbNvzYhzjn7b6EgtLJOecaPh13E2F/O9SOJ1hu62tG1Rw4c/21jzlASWgR/y2EmrG9Rb2Om
Epi0qmAocVg4nVYEeEZRlEcz5SK9jSKSi4FQFJkQScZ3EbJGzN2UYQNZM9SsE9t48e5CAH/VROT1
BTawCkMcuaozH6bz3JnRRiZYKQqieWj0r/LsRA74I4BVza2vNDvsfAin6/DROAWrJW1oo94cj+Hk
263//O+4IvnXHVwmZjlMQMqlvZ5ASytzya5y7P9IEwDbO7+JAfuQbXHbNF058dhYl1pKcFLq9x3N
sOE8MvDN+ZoOtHNkM9+tKvj7mhvprPepjEvnkYCEcmm8r/jP9oVB/rFmqkM/ITIiZtLiSh77zpSX
DAT3TV5H8lNAs0Q5zZ/fI6GbZpYXzy5v9HSfFETp3PJ5H1Xzf8xqUIu2b4sTg9095OOGljVWSx24
KNrqwm04L8l5b1GrYfk51hpowLZOsDzWheyKruLPmjs4UyF87J3kYEQgWM2J9+wlw5QKW21xgPVl
x8okMh3DUY4QvG6/3uB8JNrrxkMiHoVzXuq6zp6zepMj21kD9FGREFnN+UtRs1mcFiF4nSSjVX4D
ecHGNvRy/nGAdPW/pRQcIhscK59JoRz2hjzyuOQqh+5Ibgbv02LKGFFvbk9BnkgF0UTMfM69Mxiv
ViEYpIB23Y35gnnVa50yKmvqkAaiM8KxhUWLEHNsGPkZgRvoFMsKm02iFpAgdj5j5liu1BC5rTFo
T9TpmDpGFYNk1xHn9yOPEjzjYAivhbNZEQCemEakcxGb1dd3ykgAkPl16mdpZ1sMXw02cgAW59hK
k3I5UkFVMYL23py0FTGm/TyugzmzkrJx8H776c61sbUi1Ss17sKUShSxU5lvsQSv2KMl6QS6Y8ck
ttKE/FyAJQDV4no8u6pYM4IiRE36Z0IoiVJb0dlDUWQ3PC6F/cxj1r7cVdN15qSflePE/f215njQ
DOsOqq376O+vy0pDlZbKAHM8DczNPjqFNsbeCy3hUWnYaDCZbOT7hSf6nHjT7e9HVswN5nIAf1kK
QLlURDy0ycFceRbxQ4NIee5sr9Z0hQ8jCyl9zub3cO8CmRVRnbQ4+ALVX5X6Ie+lw3yofRVv3HTk
t/JbU1XqursLRombwbssf6pw61YFTSrccXEWBdhI2REzVuo3uNtx73PtD4p43Q5t+RE1rcuFyFpM
n7jHxAmGEnKi+hrmCXBS3rMArX6awYi54DKhEieP+doUjWZShXFgxEtjHEhJrfIvBCgd7d2uq/tO
4IQPtZjAH3vs66muyCuJeheN5OJgUrSyLw9OjAvpkqYUGyIpK7tyI6Qf63Qdm/9lUGRkRJF0wxzP
epD2n/5MzoKudi95xDAeVDiaTvw15XkJskpK2jNKVW10D/jm8n7Q3c9LO1q2mBkHBRPaz62IlNUl
ZRmj00aye+IlljJskrBqMkiFmTLZQ2r6lreogKjU3EMjjCK7VjjavyJ2HcBwDUCRK6INUK2vxrz0
H4ks02SQQ8/U9czYQlsGvDp+dujXvNEF+W8YTjHNOmGPtAioIC/BieU9TJ/RJbkzS/d1CJ1ni0hV
LuOtdvEFALlaoGb4r8Tq+IAxNGAvSMxn/MgQPLZ7mgvKj8bNo/0OBui6kQwrhks2EeDirGqz6OvR
/rUJfp7Hg9WXtqn6xsbLsm6PJKPSXayBPjuugfDBUU9pKB1T/4RhBG/bjCI3dxE4iXpatcbuMTys
SgHxOdv5smCryzJOrlWYX2JFYctYkEyXqZP4Htwr+cxB0df9P8K45BStufzKID34qu0w0ZUU4icH
I86bUdsWHkLDrCZZye6w5j+jjxJFi0Ve09RdApduqyJJg6g9R8rIOb6hbeJDsBAzk9mfwQWH/OWz
hUDACkrwKVcaC49hjh+TODlg3Pzdry3krrhAlvvQME3i7BTlKs6MxjR1Ugfwc6cUuHDYDMjakWd9
FTB/sLAT+HjXPj7I2OqNuuUlTq6sK5lnM/3tmDEJdH9sfOx3d02nZWRS+cRzD5hIs/JHw2X+BxNo
UCpJx2LDEaa2PACfO63EOL9+uipuefHSqUTramj2N7pVw8z0TtceDY3yDbSXMy6z95Rz/mL+vWve
XRypngVWc4J0TVm4mx5a19FPZvxYJiqaV8/cox70SHHe6PjlW2JgpSPj+4BcEUCWz7y5g7y4PZtN
+bt1QX771FFO2y4CNTHhFbTsYWx+Y4upP0kergFLr1uQlti3TiZCqRZnxw6C9MkcIfo0wUKvcYYD
WHnLgnqzlfUJPDKFSvssCfyPpvWcQzyEyyF4o1LmNODymP9eCCe7d4bZh0d6XxQ6yXNbZ3njXJtm
zn5+bcrksR54eeh8EZpya+tVXj9zjt1PiY/EXIvX1vYd2lTpYyrkIAXNwSFQHDm3npoFBeBseA8n
mY3AoXGt86ircqEXKpSgzYZcxGGM3bOnz02/NdF98JBCjNlNvC3uTD0EdZm0peeFi1DvFj3n01Dp
jaM8jHhfCBMWei7oCjhytu1q10ptYZxbccHBXMgbs3MFZVzTKSuCJxtAnpbtpIf05SB25MEiHyps
vlLI3KAxcIkHcm1cuJARHeZhGGn7wPfT86ZFO9mgI8iHpxKaFcll7WHjBpX43pOcu5mj3tythfUC
AaS6quomQMqgA7e8cFMyQ2evRy5QoYhejjrFVjO0YYgSCC7V2hXw9xv8/GL/GukvRq1hr41spBbH
WsSW7Kk3B2xfe3YX2FSsDmdwOXJ9r832BS92t1iYz7OsfNRb1z5nnL2NbRL4soLUHxmaYZ7ndMje
R3SHpJfbsvcYdnrEql8K0njJKprIcjqGtqCKDwMYYZLZHSRuLIBUhhQV3xB6F4nxoq8nUimT4Uh8
gSneClk6l30rDUf8fd4AWQ7PgWymTSaD3uVO4cC5oz8VX0KLmosXYDMx/ZbH55WZGxQw/x7JfOD5
o+9L7/gGFlohgxy0/9kqdkAcGKhm0UB1nVCbw9VrhjPb9xZP+yDdfMiLPnQAm+kpcP4M0xjJdcKU
NfehVJCZ15G1MC+QMF0zgmcCqxEUDbB8Gs9M/7oMJ30HGbFa6cIixsTI9uvURpRXihjdoHl63P2t
Po1Zhty+6jdH5JDRodV7Y3k8aI2LvA2vA8Wh3TLnJLXa8279Uvq7e1fleOBEs49y10YNHec1Ln6e
U4h2EiloNhtmsuPe5gmZ7tE8YPScI52gjtSOZUGwAqCkulAkwd0+1rohCzFGvvppXHlgXhRBB6kR
LUJs3ycQyzpkPIS8UfciGK/TOl9jus/FlYnGJ/i4iI1oDSrNMRAyzS6GUmsx4mqKvdXdIsTBRNhO
Nnp1myTcBq51tQeFWSs6mZn5LbyD5uGA0Fi4/oAJuGcTGVbDSYr0AzXDEGrzi8nJJNBqjY2et9Vy
Evmv5p+9WcuRDv69b++3GZT4OwUEZE0Z/6aRb/0fw894WDIpST83PldIvdtCcK48f6PD5nlRZJRh
qQqjJt5w/zBPH8WSaQVAnG8Th1VJu1Jy6D+l8L0XLbB0e51ib9txJVKsNg0a5a7tMjjMvha0toRY
7GUem4oOfmScjmG2gSocoXezOzLJ58FXcjE05RAxz4jv4YD+aEqH5q+T934ku1BFDdPdLfcfmQtf
NRW1miqZm9wLswCzyy4dZOik7HqIUYV1TtVn6chpfK0VJ+8DZGhBpA7XW1Fmj6lGiOPQ1Djy6oIx
ef9qX+v3gGpC3QCebvoRlq30YI3DOLYhS6ks5MGi6q9GZhGbl+9XscInjxfTY0cK+h/J5K3iqll/
eAsaWR80t2YDA3OU2EzXiao2MezphPrEDK2Fb6PEbD4of/Pr7HUEAjnTf0Fn90jJawIn7kCh1oN6
syY95F9hBRVYszHs3lPdzS/ZYsk8lr86uOH3rJMgnjFS7xSme7pULKhYZE75FdSIv+6LlZG2pDvS
13FKbMRurCdu3mV+VoBOjp9U5qN8JxYNjSga/ZvbX2yW8D0I/8Z3JNZNQY3Mglpgu8lAZANuHPgv
JzqCMgf9Dv3ysoL0s/aCGGwcskBsgDnJZlOjN38fbzJMj74U+qBZehr0NdilsYKeJkRxOH+9+/pp
7pFVT35jlfkfEV5wfbtE12wLw0+9JwFwJsrAZnHJJ7T5nkTBOla6Trv2/UqVe5r6IOyXtHPFUdg3
lBpEnxOPZl5/0iUVMfYVe3/nHWf2GRV8KBffwVDNQZ15hVATnk9T411gkNlqDH6fZXY0K4yTBjkc
hIlMQaRdOWTbruKsA+/XDw3KpWOX3b151D/Kj80T8vVyrC5dW+ixWmwv9fivtYtBXOehDwtgdCr/
EvUlh2qkK2wOyvbFRyZ8JnDrvFob+TJgWNNub8hmij3jyndq3GeBdkd6cvbegaRoK4pKlRl+Ztvq
r28Bpy8Qh0jnTfpFRp812qPYmRnXQEUFcu2+NoYFOZXkk/5Rka1+/gzqaLghCUDbGjajqwKJDzM2
ku23KZQhC38tQwLlSVUQ06aYwizAtPujFjkwNVtCGk9xMx41+S9grwVj5rJ3S3fzeOSgRP6UYXX8
kJ8gr+Gntqkhdo7kROV9D3ncWSLsRMMl2p8gGTevhGLbnosBbeFmJgZZwHBV+YTgrInJzCPL3+67
VMLRiN0gUXRnwlyMKKgDywSJo+41zx7pfoHbBHNlTPPGPqK+Nj4RcVtJPH0dUYdAvw0k1FQJiGuM
YZSRts78tLo3XRvEwhKj0eJ1X9ccBSEz69F4dr/1lC79GN3EeFFoPSswJ8w0FDqEovzkxp7eOjq8
DPnTI/MBrXRjTK+n+BfvdzUhCULzGYayBTuet/ie/NP2n4ujTyEgYVpqvPEVEfGtNlsz7kJmzePK
7f4mrGAV8Ocpr7/Q63yK2zUaRO2AhyKl84docBfIxppjRuRtgZKU6b7CVzfrhNHUXNZAldGIvTHB
QFAW4xBn6C88PJOJKgmiDDS79/ztQqlxpgmygtL6yg5+DikVFCxSrio0EcNyXGNYQ2MTsIqVnuhi
VmDulYlvmjH9uXaSWBKLyNGNADIOtcxQZkY5ezIdnqmLbJ+6a1zhcQkRbjTZj+IwhdsMNxWLX+dK
PjfKp8Povh/edAYZqt11sNdz8vY9MIekAhmPWOI6Vp7b23FjnlF0tYDwkUxMvZa7GDbRujWeMzFT
j6zhI6U4sKDbq7rpqA8Mr+FE5UcukLgHvGJuklS07ETMHEB2UnymIcFwaKlSBJhzOG4n9xj5a0I1
axjOg3Vzj7ssAaGjM5viiPl2FWocMSiTPyMcXpbXCiXtpFVVO6SyvXnaGHxfIWg3EopfsU3hgGFJ
nMvsB21rnLmcnHqcYfWRes7ohthCedH9J7ymel6+ILCs8W/0K5TcSxbAboZhBp+LXEufgzBcJ5O8
RcsHiYP5Q994nr2J4luiBeg3GphfNdMAC1TrtXx0v+HJD400ejNjLkqBtxDGSu/mAy+xwJ11pR+a
L70Q4RZdB/rFPASGgOfGicv+WEotYl0WgwzGBMQZDUYsp/vpo7csRIQaQzv5PdyzPD0YyA9f7DIP
Llw/wu8GH374o5Ikpc+ofZD3XYMYxauPit6cKk4At/aD9t//9pI/0R78PXIi3EJUcCB3lbfZYfRD
kA2yAxWROCEhlspjLCcyRYjp+kOhXEQyK0ZT6dJPclYz0sAk/vuMVrTunn82TRcsfNWVFR7SONft
EapBj7cO0D/B57HOTzOLK9ZVm/NQ0/X7lhdNCphYbhniVKvnvmVxqQOGueO5sLzm+P0GYeJAbrw0
7nl+BJfXZCAopEhKpPs3S6gzKSiJ7KGd7hzCatWALBxyVfnSK6gIw7JGvihpohSvmsRpVgd+MrLn
YRHNqxFpW9rmlcut7rvahDHsD4v9fZtXzY3VmsMhw+WqKxgG8upq4pW2ayPjEPbxlOq9WgiV9zIE
Tfqa+aL62aEI5ScGPmNNNSPsaQd4uNzYqHOIJ3KdXq47qOaCU44Pc5ZhA8ttTFYrBneAwNkQNoDy
zDjRiqiJysGTSRDXHw/PaaygAyYKmWuya/Zoqxh5NbqZjsJjW2bBxGkPkWVxpnb2wIIW65OAXnuY
3f0C9oGw2JBqKEopZgkftzhS/OMjJeb3/POD+QnvbiitTY2HCANKXxllqGTZmNrcE+sm19DlXQNE
XVIIpM0ArZrrFeJFDULEr9vuU5ZvhWUuN0oLjzS8ptU5sbg0GbZ2wUn7pKtycL2A1vF0//FMFeFv
6KT4Qj75N9e2l7mcSzzpEt5KOh7lR5o9btnzG9oEiMs+TO6HEXacSW5tuqRz20Fbfcl/xQjqU0Ed
sfWwIx+7QruewK50Xa8ze2LKT2gNPhNWjYGUDFGKD4WnNfJymBptm9NEj1FkMZL6aSJasTCnKGo6
ofidtNU19flGfGkMqBW38ncY8qijhTv1ABl4E4GTrSrpR6mFYliuC5qk+CkFVV5mtEQ/hN4qSIWf
ggGsE0+NwFW0BRi623YXjOdNyDHI+qSwjGLiq5eEM8fse88Rzr/En4RMkcWbBfJ7GxvfRKaACISG
SFuQ4KeJA0g+sDhZCXDJQmijd2HoSdaq0WIeMsf54v5IFgqDL/pEtpY35IYQjb8lIfKkhhJ7CusT
vIQ9Zpz08Lvqk9j03bwQbzJrw7dTTMo8q3EjYx/75P38GCFTn7k42CMxaoujHJp+hQ+sW/w9bmnv
bLZ4EIxRR3nVGkKbbe5N1jDu9FQlGX9ZjMll6WdhLSK5x0pJZhfFGbffNLd3EPfCmkG1CAs4gs0h
lqr1U61/Me31jkv2XRuMQGkm1SI+ehR0nubohjJB/tcNzWNmV9avCossi0MfyC1muAdBJky6eYb5
/XvXLJJtKDYCXl6FrBn+JXvpFh5u+YMAT65t4jXu0qHpgGJAeTWcG4htqvkDUiqkoPu3wChCMmNM
+hHx+lDO1jTqCzFqkrBJeUksuW4i5rQoCTyYdHnty2pbfdbXC8JfpTZYCVdpknl97+YoqKFI474c
ArKIvQiA4TgTARvax8SuC7j5vqBjV8F5xg7t81vomQXd+K288UlAXdgcV91skE6u6RRc2Y0djfZ0
XxbwnRVlHXoJr2VmXGJ+5llpKYlHAECaA4sy2wCsIt67YJBKYT2LLhXwSjfdfAcON702eCNIOMv8
s8o8912yiJqqy0MQvsDe9Q+KtKGSIxeb76zyO+lN0iYqki9qeHY0bhVMBd6sJDNFCqaO28IKshns
MyMzKzSO8TQZkSBo0egdMIFoGiNdiJ1dZFHKz3tcqYoE0HLCrNhaG5lWC9i+E5c3ZSqeNFQukTAO
Zml1zed4ZAiKPpYHyOpVThekv9W7RrgcZ2RQA53+2MwlDEqZ4pyINw8rBEYW6TVMjJOmXlza10Cp
VuQ01GA2+crpCxPBkuTubSTY8532ZUZ/D/EsR7IKj/BnkmTkD7swqVrYHQ5cEmnxzDQyMrxvFUXJ
gZ3N2lYx/xbafmTA8WQqqtIW2o3hpJhskIWFNLfybRtVMgpmODMLT4GG3FRpeqg6kFHqxN9y5hcW
bZXCxJXTfFxyHkoQBzMpbjDwHyxBwDX8PPgsTbF4FTmBik+LraEX+QDejdw+Pi2/eReINzQlDDPL
xjBqTDTg+PItk4mZHnk4IEoqKWoDrputVoSF9/a4hLmYGDQ6TFcA26Pd+M1Q847mOFbPlWlfeg2Q
vfC24gfEyQBqDR2AaLtWp87OM3gmegV779l/sLIXLOL2jdWze+ihQGIwBbUiA1hT0m1ewU0EQRim
3wefD8PJgG1sUJDPn02DeBZCuY5PkAW84jwFOHczua1b5VNncgIZxUlajJQ38P94Qro7PC6k2tUj
kZbfGlYyTFxPfY9lavYo3YM5vq2sD/kFasKbSnPSP7eiyP/6mYMOglZUwUIelQfN5qZ59Lx2CcfR
NbybdadXo2WrqFEV7NWDbwxnYhywgzG9ggp6YjVslBDswSRMDK9E21Wk+1cNRQ1FKNKYvnGrABpK
gRy/ZSmjysjy3N0nu64vXTK88i2FKQskWPtSM/FxlTUMP5aJYzV0sYq/tCj0CgXVVx3TVpDpxeVZ
c5htpW5iYr238Usu8XsdgZdoRSa3AnSN81othuizD3EJVTvx93oHhrK4+Cz/Z/257F67E774fK7z
iAnnqJatIB5jXgXxWVskdmeNKbLoLouJhQ48L/txq0LT5Fbqk+1rNQjbdfmf0M8zdMH2/fgWQeHd
Qbc5iaJC37x14cWe1y/KYLxAiZZsbDNXrW2c+g/NioZX39gOEZw8brGEvwM6xOEN5B/yuPsXryEh
Thg5QqvFIad8VSMEOBq+QP5GOFmdkFs1s8OhV/VvSlC1Augo9mHLZZrs5xA2Xbr1R0xt0W5tax0I
xUUqTKC0hk/0ZJHO0KmSAHIfnsi4lIqWtA+sFsk5T5+ZjpE1Gq1pZ2OGabpMFt89tWvQ+uo6CsID
d8ID8DJ8LpD5FxiT2iIjzvHMTGwIjrnXC5s3A9hi2KyHNU9Sklsiz071k6SthEMu98FDcznCze0E
RMMlkaCrBmtpKDODSrDAJGTw8D2MNNBNUQL+qjlCiYbvJ2u0BJzhba4Fj2Q2gkV6A2fOQ9fwfSbK
ovdS86a9JJdHemeEtId5nxIpP1jozo04lEysBIzxAWrzGjo97nZHUkuKetf5Trjlq8ZK66wO30ov
k6S/tqGZncVxEH1vrO4lcuLtIEg12xQCk0O8HQRPBpE9f3Rkh5+u3pLPnqBA1DstvaRE3FjEq2zn
tFS5GCNMCjOv05v0zamH2kSdWnYxoCabXIIo178pwDtfhjCtZ84LtxkE3gACA9MeYitmu07uXNW6
J2sK6kUpwmeKV6dSzbkHNnoOTUZ0DrZ42UOIvlqL7Xt4Uvhby9zwcCkHhLWuKeipTbyVY44LofK4
Yrs2KahRene0yzzGaea7P4dNWm6OsgIpHHNHcLBsM2DojOaR09xFKgGM00HYTszXCaogT+0R9c9d
04ud2IuLXR+JLdPduDsPQi9dQusWSJabuAlQSGmb74hIlie0xh27O6FdGzuxiTiUTWTZvvzTihWC
J33jq6YAd3iILuYVCrqDelBvorOXE+5QaOMfahRoXHP4PdaD8WEqUAZmxoH96bIkgsBldGIvBrkS
CMUuwRJLFP5XX1xDDJAf33Wc6qoinIvsRA7ovYVK43iYjP678XSWXA+wwj+HDTzl+ymzn/tx4Psv
F+OSny5fS/rh5B2wGzkWvWUvwR4JIsgV8k2UwttxXURaTNqc6Rz2Wls0eT5e0cUB3UP9Shv9GBB4
W/uu2nrFO7jUsiNTWZZlLWnlvrDfgJbhBMBD4up1XAIM11QU8QZB+SkqvQob15quH5YqzNeeiQfy
AEt0JQ4focwH+RnzVsye3vxAWvxfaBOhQv02D+iLcjreESqGzbRCc8hRSbQJqMprakxWcXcf0TBf
N72V91K5uofrmocsD39oSEqMDLmsRfckEvy5Agbz1RFEqv3pHX6l6fr+B6BPL/y9T3rogyz45BwV
m8DQ+inDyJU1udvvx/rqXEjNYfG2jLC+Zz0u0lmaiiDFWQEXnSmqxY0ZCfwXOFoiR226z+qPrrdG
FcZEWjsj1LAkf6ffOEdKpeeA+FJIYVbqwvjKMTlOjWfKHTw0irLaAGApkjJ/8kvkvNNO6P7vA+Cb
yTyRMt6hyK1Qb5wQDMMW7fRBqo2R5wMa0bZ8hNn53q/Y37P8ttKVWxaFmzMB/l3T0LsprrXqD7Lz
gKRMo+o8hDWmrJfFwFZgbJtkXwZVNNF9WLfMz7S20MJzB2Y0ac4+hvyFw3Dh0GxPeQVrP8bD0Ysd
mJqvp6v8MaQgVBWfVlBesbfolPOJ9HgUk1843005lz3EQCDprpoxswAD4uKnP3OFAjSWBLqwZp00
ieaaFsBS9OMlDffJDgF8rrn8UdhVCMoDPij+2odvtQfJ6gu+Z6k7pa1m/6/wAl3LEe0M7uGdmRHV
suurt2kYOAseQE4zA3fFmDVdXCbIpTm68Ts5ksJhEnPkgDpl9Cd/3eU8lu+vZeU9kasWbjuJ388l
3RSEFOoS0DCLPQbp30FSjmmTJEaXWPolPeg7jv7DLIa5Qa7WKj/6G3Aw0mv4e2dp83BWOasmWw83
myWXFVceuJhePJ7QqhqpFPnubW4YdKcFtsZOARJdv4N6hSlq9kLmJ7qcsGDpXIT1H5tUIXfbpi0v
K3J8aPYpDCJW+FQzYAvMm0PxtMGolqEJ/BQ/+veJHVfyuNBDjpCKy1hrOBegElrpTq/LDyjMtHxZ
NiZA51eIjmXzZk3pmjcFg0wBCzaHkdzZKbIiJUErvYG3ep1ZDtmJUw+f8eGp1KWLdGptvr3x3BOn
tHHRnQeUdMMMKMyxK1Hh629vNcbIV4jADz2k9KsFerAcWvqmg5kKUct7FxhzzT45R1qQ3+J3WrNx
wTBPdS+ujd0hNnty4ILY7EVus1qDxSJRJ1umtcaSWwNmdHEgkrXldSlGwlajimGGKwYfj9w/ViXf
7v2fanYu624ZDzUWvAf9YtGdlm/YE+bhd/LRZttZ+3iZGmepmqYnnXjTPpiOKdnfpFUc7d+1sfXC
88uImypg8OCuCRDTo3QxIEh2IT2MVAm4D7Jl4RhHhuRkr5RUkG5Ma6VAvXWuLxLzrvKuPbl5cCB2
Ml1dPuwrG4NFpJ0GjQETI+WZUoJF9WueFVEoQJ6JJmRwDLJusewmtYalDtI/IKoSbsgNuquog37x
Y/M0vesTR6meoptwA6zM2g1DgUy8BTXNLRm9bXL1Cc11ziaS0FXtD6nVK+8vQAaHzSbV3C1mgP14
JEXSPDkZ9BD4jHmb1czXYYd3SywLMY7PBxqV5WDsqZX+PjCaCrxOF6fWgPVJEVBZ59Ucz0ferZFW
zSer8hXENb5Bm4VTYdDrhrpUnUX634XhgkXqlSYXK/IDOM8YyOmQRYp8Z25nizX1KcvKlVnDYADR
wGprTaOqDugs2hnCk8NQQbzEMc/+mrMfJMowY7QCkqMkrqfrL7xNEGEru1vOaPqgHj4L0yxfvN54
nMwiwq5GH7N2JX9ffavB7kR0mAxmkEJmiv5TCC/5BH0eTE8RsaIikR5L5QFCZvqAarGHgjqiNurj
f5a1ffmIMaEg80vz23BJMvZHBt7D3m4gEyME5JL0wG0g+kbi5+0vH2jd7qJl+OsToN9Hc51ZO4MW
HGJmwGrjjnFLjPxasAEBTbjD57b6yFMEqIIciuwDQm8Y/mAiqBHZSZ2Jw6N7IQ9/iPZSDjs8okgk
YE2dt3Fjc+GbM2bix0x2KFYbukq8CIo45WFc/Gl6+RZ17wUQx4h6vv4gkFMQ2e6+CAyJ/6Rs0T5q
yRzx/Bz+zVBEgNBh0qPN4wArETZojkuFzZXZoaJx6zO0lfaIKrplxNVEfeWoRK24i5CFP0S1+rMZ
V/dsxoPATUPcAAJMKBSCAVapOsSiLKoG4IGQOJgtUlsV9gsy6la7kiK2Lix5VJFupVFA8EDkYQKs
E/DQuuwnTEbJr0qaweVm6O7C+RfvQI8JxaWrrV00leMQGxLVSVgknIDXkwzsUuj6sxDYgc1t0rW4
tIfAmKx4cAqEkikB2sptKMjiAT7y6mb4/DR/SWWpOF3faK8Tfk9scJIDw6RVF1PjoSJzzbCf5nE/
BP/rDwVtQIOoooyWZqperWjmADsosa9VbcsWKnUGg4n83q020DEEqq+YkVDV8mdSeciew2y/WR2s
uWfYvnsZLK8QeTWtimOlxvbUWxRDcSsY318KAxokJXEMbM0pE1CQIZoSvCRSjG5q5Mgt6UkKLarH
4SO11AagAwmOdu/oqCTuFXdsnqfOQrVx6CITHHue9Syu1BC53NVG5kp9mm2eR+aB/4J5t9vATgNf
fakesI+dCz/d75zfWsAkRIIq8S/BeQ2z9QJhOsrXSZIjnuV0m9R9okn/pDw+JHZA4F6VbVQviYIF
Fzgruf3wgczCDgeRCwKe0JVcvTg82+qNvtOwtPWRfAciDk70Hty0//bC2ubrbwsDUswVnoKskpF6
2mLLKxX0NWEOWBhcz9DX2jLweD2LEm3x4XIOxOWhEWJ1VTQwXhA9A/pN+XppRnTubF0wP45er1uj
CO2WgvO6Lt1Co4UoVdVb8My1Od7rXs03fCaTUYua6IuGrGpjmJwhaz5tKhOD/lF7MQE9ZWjhacLd
VUl7uqVgLe2vP3JKQxlz8MPf2/VtVxJaY3jl2g/BE/NiwdbO3Tscvrzd8jAIYF+Y8bUQ/vtrCRpg
t7QLOrwYATrK1WfN/KQIhM9PDrJR7DGmlWPxj4yHjcvgcEbHhkoHzWRPC9Yyl20ZPvulP1p2p32J
P/2ACy/dywGMmbyYxCLtJ/+Xv5WWK3OKSuHbaGWZPRcZU2aNmOiCYjui4F4SZ4s8+bNnCG0hRDor
FkC8yarFgLlNzQLinYsAr6Kaca02wHCviHQj7K3Odn31Dhqn7HY/9PydWZXJ1tYxV8iktQDVBahx
a9G9wN0e6hbbD4TAJJMpjLCsRTnGUChdnUSsLsq3BIuq5UvSuv0MvirlhJBUcmYELWaTJhZqrviq
/uqp9EU80UHMK/XWdyAjR8ttZl9N94qtL+MDgRJbADVq1lywuJQJROM+4ez85pSFeV1ufWOfqhWK
gu95PHbVWcefO4LoDP9oBzP29QmaNEi3eb6ybCGope4vaBwwq7BBwEfvt/gKJKKD0vno74gzBQP4
P+jXmr38faFOO+NC6rEV+gc89dgJUDMbltf0zJRPU+eIiBWefRQVvzLp9Qz6oZYwHGMCI/DscVqr
IBCyaz7ma2Brlj+KZzLL+ryFMhqDDLfiqOzM+yy2O3jEuXjq2xG3XjyQKkO3+XUOyUqyMPsVght6
8LvC/oJWqY6YjW/HnpnQnA8rsy52NrT8egtJLENoNAgRa6M7Ov91n2OTvq9du9utptHRaIailsGr
hqjKHqKhlGrv0mdOJvSv9OD+Y1hpCoPRjrIximC3bOVP990DJHIfV346gvmn//8lSVCZp2ZhSg/3
isyY4WDt8bjnAWbB0Uy4iJ91RqvuiA6apdiphl62FEVrvgApGXtqEjaY2zvIgopcg9tQKEq+KLfc
KwmrH7G3ZDipb6Jl/2gMhJLRJvCxBlxTRYCGW4uhmrSylHWj5QbNhOoHj94Y9+HeUqrtd9RUCK4Y
b6oxAJ5DVsrtQYFf/In3l8OGfUGd35D+2RaqE4DYxrvsClAYizO2lyax4/PjFDQvjJXeEne0utkE
R6Rqv8CEDzjwsO8/VBSYZ5UzUxMZvnldU+pmiAHNKN2gh2R0PWm2l3OqA/B+DfSko4mfw4/tjJRn
UaemJUePIE2//yh6nwDDGAuUTU2ham2lPlCusJl/MUcSOiHIoE0BovYg5cu9BQ2XfXaZlYsh28Hk
IXoKKBuWyUE2Byou3BHiL6h6sf4DTfkMKTTKyc+4DlKL398gnnhQ30UDdbJraaLdQseIroVbQprk
wx+EiKojB4x/DnPnLg/ALfarqp6EafCdcpIqWxhtPTHZrjdEc+tZ+sYhD5ZyKYvTFYbroxo1HfuX
93uc2pWJOIV0r+eDB4AA+KOg/cvgtdLr0gzXSTXYOuXzpIx3b8xo/lK/m29kcxK37YKrPKHOwzxr
V0zbl/cnirVRNNYnY4rZtsw5tWnSCHnZKXCAtEtkL1Fa5c+S3cdqbyP16p5zn95FUl9vcFUQ6gti
67+nXfs9tsoxtTZDVSOcXWfGkhYeR3cXD1SN/5iq1+CNoHxzKUN1H0WUa3cPOXa5VAHVri3qupYi
dMYoRY7EYlnhAZ90VbSqpv4RqlCthQ6VEJDKucSmpjZ3ANXXvZGRxTEH/85FZPJHN3ONTS1J+fxg
oAr96/37g1uhyJqtTl3VagNHZOHOt9wmOT3dFVcXvhAQQcBSodiamnxc8sGK5Vg/+GyrZxFQ9LuB
wJ7pKVyw/iMY3nPqN9sLSumbA0F23UqI/M8KZ7D6v3tr4A2Om9ecR9bGYrQaL7x0sGUPtEtO+0VP
wHgVNvaOESncnhmMMFfPZHO+1pYrzTG//qEQJfJEfg9kYKvRJx7QdDLTVaswZUztDiG+xgtinda/
pa4zx8+oRs3gbarh+6cVb35ZagtdhFabgDhdUxdZTMLRfXaEyPGhQnZqRlUjGQLHPg7yM6xlGuy0
XD0n3ebqLkcEmoF9ESW2SfRrok6luK+5CqlKU69FnTxDs7M2rW65BCsDrZWDGacuF9Jt+dfkX2s6
BoCQdhSrTqCekcMCVxouIsYYO825mOD1m9V6bangCMJzwyxmRdgXxtseRvRefLXNgSPIJvXwlRlQ
H8y0fVGdCmFsITKnKmK3/JS9oSQ3NHnnhkJe4x/dPb+pypJbNb/u2Cq11BQHPyEm2qFxaPsHZxDI
Vs7PNLGolvdn7EHa1TvwBax1sFvs2mqqCVaGPFswK89SxdcmAz1Tr36TeqjAzpBwrIhATuq3s7ne
tEP0BlJrA4MH1Kqnvw2GOrcj3WqajuQ5PPaVCKFtxOsiaYTqdl467x2GTIYJ+RyqDPtubkz0LDPS
yFkUnIq/KaZNCk7kUBaYuij/XW99mof4EsgCHNEZIgJEB6jVaKqhuryMtSy4q5AyapzswTldwJ5d
xkRaBEnC0uecfe1TYYp3W/8M0Q2IP0U+ela1yAUM9iq1WQT1M1zFFqkNWv0IDDyanT7crVQ9vPQe
KlB4c/R2Kssbhg6XUMTB4GplHWXQeu0TMWsQRaoHxZbQGPqkJmnSknHXRsjLicu/rUoV7RzFPbTF
Mma3amkb3nZeRuTuDQXswi6V5BXr7Wf1sfzVSxYb71H9uCpC6VTuMIyNQSRTSBXa/vOmcoFVD1Ml
rVKtsGjkk3f6dNlURHF9SXihCINwVjXq1TvyX2uHvD+yK07Av9ZqEh4Iv68X7YpUv7DDZdfk/sIZ
IcSN5+BkMC+N8OUH85Js86pGhM3yUznNVC0nTFZBqeogQYGTmdt9hzkvTZFfZEMwPpCW2kaumSmS
RpqM3TzRJqbGNdSbOI3ZsThDegkQFoJuhLYqYrfJb6xO68NJuXKEDqZn6hAL/qJhZ1+PCMIwflGh
bem79JaBmxds4lddW2eC7vKsVz/U8N1sE/18jN83PxjLOhU5RXebCMTagJSz2G4xroWPyB+pGhhI
brNEPxRoveKCGFOisUDUnxKtAR5RinnSSTcKfSAbiqHjEkwm+FdVbOEwR63Vn9dpiZOyNY9DMIOO
YY6jF347piWB7+PvbVT/KfD4Go9ah/2RAth7y9fplT3q/hp9iBX49SxEMTKALa9R9rhIUtqNylZ+
vk3mU8MqFc3iUxX49jd+Cyry/v9T95dOHCN8z57plufWYSlbZqwHH8eP/W6i2OWki3p/v1Tmm8r7
Sib5U8Z+WX7TgWohPmN7BIaTntlJ1AsJTVQsmObo7XFwXMCXx6Z4X941lCRVne8B5/8dh2K0sV5N
AEcMcD2nNU29yRa4yxs5BSiTUfgwFTEtKZ26h/14FZw=
`protect end_protected
| gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_v8_0.vhd | 9 | 19058 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
hWeX0mv/9Qx3M4UIGIDkVTB/xgtUl9ZDZFIg5O3XHhobPBlKtKTl+fyCvGFf5vLRrNSlXlHJU1rz
FXdOqCANuA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
aOhE05LX1Z874CJygIFb5DH1GIlaxC9tDWYlZD63Qqn7XbP6Z7dgoWgNdH2kVDhzW050Mwzw9GtG
Dua7KP+dapwNPC0zwZB0gDwmQrHu/8Lsm/1+11f/S1aUv42hRRQ49OvSnvEifV8Mx3NzsNP9APDn
MUPvURHKUV73+6ZuiLo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QExf05LSMyideRXJSUpQGT/1C97RLsLWt7GaZ70aZO6SLMEwH5TnRVfbDDH7GGw7nmN5VdvI3CXd
Ohrtbh2exRVkM5VBFCXh2fGx+vEMmtYCCEwGudvZPoGRRyCBW1IrsTolCJJxvHpveDHx9X05S+AZ
I7J5s3DGHcufX/l2QvQubE8A8im9fDAA+aJMxUwKrQGLw8aN7gnkGdtmdtYZPff3wbYL7TKV3VjQ
h9wSSADn/qx8Az2xpHr2lXwU968hDmORjgPzn9lxd9FM69EXbeoLrMHYXNO6KSEGG6nXC3TjO+lj
MjcbkrOfVT6kbCe02MlhvQpZQY+XMl4HOK914Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
HJp734XfV9rUYZjItE1YCuSf14mpvib0w9M+m4AaNKlXWjk1WsDafIsxg19VrZMiErdpy71Alt9J
sbUHx/oQiJRYeO9K4pmdSlSxKVM9jk0vpLh5u0vWzOqmSkYQWfbDnrqzkx7OlCPafc92aIC6OJHd
THzXTmg29U8sxMEn6hI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
t7U72jnghLdnhyooIGMnjTUH074rZ3mBDbbBszkfMDop77t2cGxgoJvZRbN6WdECZWX/IcA0QVXN
9DOVGEvSrp7W5JfAwrY1CEkvW075JVH8cL2uc+eyiXwog60NiGGkLURFzQ6bYQkd1RKWfAy5gotC
tS+Ujwdetildul2b32XW5fDfU9XePdhbmN+QUfTe5cJ35jqC2y98um1Dccs7tK09gY7ROZasml/q
hCXwAU6YCzcn9TsMhRQ7ZbLAd8FknaTGpITWk6cb9VYeEvWTH8RxLDFagQ7NU0/ZOvRpiu0i3ng8
m7pnf938tMdJ1nbDQNQ7w84MEzpMKBRM1RdBMA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12368)
`protect data_block
JQNglCE+ITUJ0QcIdqc94ZDesJxPtvMwpNL1MDnCEKi12D+OWL2TqLlG7c1GDBaNVLXzTnJ5S66H
a1Dr5KuGGKPWIIDMAHamTb3a4SKMvlQMB0CxrMz0Pq1aAEDlbovzZHthlDWceixJPQT1aPdsAR/o
xqH5qte/8eMRf6EPrNjh7Y0sGOS6tp4cpPFyQno+tdafof2JIG8A4Drzk83Yc/LUH5xDqo6lw71o
/943vIR78KKv2s8GO3IRKA8Hj8pk7S5K64ubbDWIhOjdbp8N0QW0JLP5n8d/7c4DmH2sv/XGBaOy
OzKchOpHZKIrxRd3YEs93/c9THzVVYXlDMqNU+v8ZWJmeo0aAOU+ZamoQSkFIMILheomMi+lga6W
2U5W05VOzIuGeis9AE8MYl2NYO9YtgOC7+5bMP+xWE0kDfjPRZmf7WAQI1DoNxXdeCY4AQReglW5
ndfblHHPS/mR0P4wpp3tl/pVoTph/FrIB6UNa/p0XQp8DsFUbBO2YyUdlcH/rmq+Qgj3XEPioNrw
wXyjF9ZbhkQzNfUyw90AaVzwM7BYHibRFX2zR6IVS1L/FkJW2PZNu8lil8e/TsC9IM0k4Std67QR
HCh8QaH+TGlujFUxeZxuZB52JijosDNu1WScAE4so4IJ7QzB+a/koYzJDCccz4b1d0637I8mbu0g
pZmrydkP0X9D8gxCLwYHOnUfyB8ShuWnBQvXeyeAWDRyc4yy65gmPbePUfiPCKhzVUOqS+3MUhty
eGzySw560TZYPnuwct369D7L9nfRVq3IdP6oxHv75Tic4SKDbzym4omc84Qp7IckKCqiqLgunGUp
GRRSORXz+Z+mgW/sTrNcuzUxZVZBfr2lwo4dGXJzU3NVR33B9ITsu44E3dI0uAxamEPP+4zfFpI1
l/cYM2PhckABQ6Ih9ozZuLiGoAU2co8GOOYkXkpqlaCgS3EnRItfpXSa0ja0vE7PXiTgKIw3iZxN
R80AjNxpQ+GsmMiS84wJcBwL8JX9+sRWjbSHPMnKEziOPaj01KcZgDEpM96La6PUyS9CZYSvis7O
D6ELREkc66OCjcastl1wok99TBSaeEhEsh0OjIHyTW4VBkqSHbnOxNuDqyNHOLXHGZA1XvEKlejj
igeKOVr7djFjq7yf8/NEGhH1PBnABB7XnHOPplVkDlP49oBXt+xy7kdTAPAikVEvIbnl3kDOdsVZ
HuzyVDJfi9/3kZjid+hLrXpzepBA2mMIAOhuvxwS9ALvDE8HKt6Gnr2i61DEXtwZVCBCOC50VtOS
dywN9laUSWwfApgLg3CgFZz7judroKbgsf8VPSh21tonGD7TDz2KwN32wbxsy3wZ8ZDG54+YXEkW
HRupZQd4Tc+12gbnOc+MrqMq/3klERH3SgMGYB9KtoS/li4OqjqBpeZWkPw9VAIVyEIbVMUivtsS
PPousTQcmh8IizN8r0TeBX8hJ3F8JPjqkc6A36+cduzgDSdBddnod00vjbtlBgDP+Iv5JxIIIZTV
uc6ygncfzTgubMJdY5RNQsxryo09/auvia0m79TSPbTKYjec+Oc8hWijNO3pNFCb48LpuUbR/y+n
mbyLuokNMzGlofAI91HQwM9Y8DX95MBfPcJYLj/jMoPsyjrToE3SyeoNkUCykcK+FCMs8XjmJF7b
agdIhHYSOMynjv9LNXSBTi7UViGDa5RW9UnGxoJglJmCItv2SsrWAGgJnSEC+G0grkLCn91RWMqu
lxZ10jivM4ahHJPl8eG3n3guDQrXEq/7IxoEVnMJuFxpZV8oNt1WXz1iMA0Z9nf0dB18JgenFW0B
XfER+1PXD9a42NxsfBg/CK9bNvt/WP4volporozAxuC2v0dpaH9fmtgaoXVNf/cGZcL3ClAPcj/i
xvC0CQcVVX3B0E94UvTm4yjPYI1Kz0WFwXOm2/605N/QGSecurpzomVZLbhZtXNLfWeyGrVUMzah
aAiRY+EDEYhjsJ5jCwsiullRIy105muYhlwOOvvytJzm+mp7oCxggv8DZr6EbqHnDrtMQ7qWg8gV
K0RF0Wcrwrs5GCITPoS/XUzOPLRiOSGS3du3YeUzb8Klh9yY/rtH005np9yxYY+hF6wy0fijh7kF
YZvU5BZS1Ge8rL1qs1RmwVFuxjamGJOm8tAImXFXHM3ClSuK1FjNmUnkI3a/FQdZRSKKJwX94R0K
xerBKa4jHm5ksJk9LsqOlBzfo+RHIXXdHvl88YapmfztsLQyZOQxotdptK2xVIBPkUD22N/rVVzb
2Grr+cAxz5iOGoqObPn25kOpanY5Fnu9qTNVLDm5NlgQcJ91Tv4yLGkSeEPHBp04cWk9lErcZ4m4
KDCg4fjafEJf6ShHf1yZXNV0Gsp3cl90CynE5f4Ziw+9MuHZP53YhzBspvypgVyz0cYIMTGZqqdc
FSH5Bq/DnHH3oVgQ1Z+E1Y+kwFftwVxutLkmNdYoxkyPuzE6TEHimU9voJBOE5TD/u19KiMxhLB3
HBK75vdRytwvfckEnwuMcox2pdLck+Pr6cdQ93/atfPHHaA8/N01xko5iaDozMdg258zjIebVq5c
EXlyPSOyJDYb5MJO7W9Ij5Li+n6Dwkgr/193LoFZctmSWz4FjDGv9zFp6BfXtGy+th1XOfn2u8L4
AlU+6f2f/GEdFDaJnj7Scczr8ViTjSVYub+4beQgCYFGo247fGneeJJNRfP5qVFRJuE6Ytc67cns
DYDQo/Qo3p6CpiZ0D0/0D25d4suXmKdRFhNFpHLOKvnX9uZHk5fPYvJRQdIPhs/GLW1poJxLluzw
lYrgu9tcnJxibqPIDeNFoyqTHfE35iGl/azOAX7Z/qwivYvXQFvjC4YLUDf0IGDnQypojDTjD2Wa
Srdlqvjw+rISL6ljjA6NfuMD8EJE7TbGtx26q0YdpLVOUhnUB0/scwSzFcJ79dUw3h/HNnp7cHxf
fsFcLA/ZwfiRFlXJYA0qWIbAa96iGq1dg5nWd9YSpfOMK1CVbJGAWErFOrVRrWwtC1f+ivp9dnLv
tFd15N3TNTEx+5MZ+ZgjMC/L0b9SQ5im/hSIagRHGA2gHD6aHqDX9vi9IesbuN9FpvA0PcS1wLto
hr7PmImYHvN+9FvE6n1XdodBT6VVby3D82zUAHXLNbKL6TYrtWGtSkYGOMONWuQZM78kk5/4Pbvh
Jsum/tFc5nkB5hwDhm7e5/gwNH6HSXBf1koEu9rHv/BzUIIT4xxc7z77U0udQrA8/X3bNFk7+dy3
2rCDni+lYBDNhbzTmNUZgyLBJcGVweTDxxDqLzyjwuUs+02qh1YBC7CsYIy6s/iZz4tnNmgfurVJ
T7cQHxeVzJrn6K4lHCY4UBhe6ML/B0wfdZWiRUaogTkq4tj9vH8mGZzQzWCif5o0HEG0zr5VCiLK
/u32srwxWV+C7Nah2f6rhraJUe7/UWMRMzi4muGR9SehUZwS4YyMPoXy0tdJznGnF0dA0GyK41Cy
Rrr4yp15VSgwiJ8LmUqvdRRl1iQH5guFnHHtB4Nuxop2sAivqyVGf6A8KhzFDff7KbtJlVm0XCrD
lypa/ZiQ4YHyzC9LV8glsvpNRHj+k4+uqBwT/oYUckADnXOT9R3mhaPuvI3l/uFn7YTbNYfe1gUJ
3ujh6zvAotgxTVwvzRMFVTX1x4c6harij9exypMJdtO1t16JRkPmwJE4qH3baVOAqNrmvizn0O7h
1Sbp3lP+GIPAWzWwGUrvH6KyTnDRlFlq09xOzeorG/XXaDYXFxseJFTmCD0VTmwRwCy/cKA3/aFU
NsmOfNr3Zi+3gsOi6Eovrp4HqAxIw7L+A6UOSVRDbFurJU14583hBlOTkpDOpESP9w8uRt5W4xwE
wzO//+huzerCF03+Y11YglAPzdNhQAK0y56vlw0zgLZDpeaqZEZ7fzmq2BAVS8Z276Si5I7fJnNZ
8iUrcaGiwJufltiMN8Ihb5/Vau5y7bmpYLTFLoXIRVCZm9FTTy9gKn6SRcHcsm7xfE/pbcqFO7bG
gu7wIu5cDmZ6IisvbmhipM0Av3/46ZYVYLnsYEkapRLXycr7ZRqx0jvRwyLmONakC8SBJwYeNNTN
/ekckFKo7+/jdWYsDXYGUEVA++I41Q5BxG4E+CeZ4HYHcBJK0aVb7pUSrU3XZP60ZjEtZEXE+iJQ
4mKJn2ZgJYGLV60rM7SQZga0Mn4rC5es8rTbEE0WX0U00wIZeP5qEYev8A5FXEgQF+bruygoPKqX
GDQZuYv0+QYZcIb6oiZsq+uPNMmIkLhe23hFE9O/De8cnV2QZL6Nlg5gNK0v8klLiKj2L7WCq4+S
Rld91jhy8SySwQOOR8DVA3bgw1J/fRmgOmKzNyUWqxetWjthbv+0gC02TRBWDJ3gn2T9fSdaQK6+
e59PGB/fa8PWBO43Hys+ysJmNfbIMBR1oeBjgTHRJpWXFsWGJeSGgDHGK8loWzTrts3QdhAHimEG
JSIifBCzHqSV2dUgg65AcyPnT3Cp+4LKSA5KCOoyjs/iPNxgegVSGz116WstFAKa9YSe/90HCA25
jENUJxPuQ4Xoam23ebxbkIHDkQ9Sd8tYrHjIMJads10bYqr1TD+CV/B4ZjcOuD1ICmG7Z/tkxdN5
V16tbnC1nJEt2BERiGfoJPe0QhUCxOHGCMQlZi8t3Eu9KZGGHdytRIR0/CL7+OquZ6/Lo5NbP3iP
anvMn2LhVE1uXqB0kyeG8ANbCHPdiVzrdiZgNzOLxfeXzCZgMcQ4FvXAhEsEgSwrrT30mOxR1+SE
IkFaPZlQ6iTNnGGBW1CjEcQdEXrEsDCQn2wRkp8HNx+4DrVt1qAODynZJ5Ydci8+7n9btoODS0JP
StJg0ZuKQjQJX2IWb/XYJY0D7ajbKwpzvR6W5T60Q4slRMvagS922aoLSvR9ryJXcQCKC8EUmJDd
Rss9WcwbU7VyDku0nNVBF47ZiqLNZSQOBryUChtMs8dtAu2p7Mo7urKflri8ghLHamSlK+/czF9O
Ze4d81KqDnXmW+MyYqqs6xAz4ta8eKXdxPgpOCeH9ipeddmv7EMC4T19G25re5h3qYoqPBzhxvRo
Z2tRWO6o/MCXtgCYI91/CsBn6uq8NKdaq1uiyVEi72UMEaPMN/KDhloWjxu/H73KBF6k0skvNpJx
/Npye59clyp2pOqAwTuvbtPbkbg4G5X6P+Z42tPdFSab4oYxCyqP9pNs7/qjLbJV9ejE37w1cSEB
O+CzqYqRwVAsSgPEdj9QILa9tBiRqZK8tiUulhQAq9T0N7EP3U+RhDCdvkSHJgFjuqDvGRZWVxFK
07I0qyvBVGiJmWhY7WB67+7q1BKRBC10AgD+Vhgma7d5SdM+DweE3NtpSpaah8uj+2uV47u6SwSP
nYfdsEwWBaiG1x6HcMtLpmRjTC37u0RYLsiRdOynL2diSKIjrirmCGhUf84ZZfKHmnps8akjt8aR
Te06BJabu43xWSdeHvGkPO1hvOt48OjPwLE8Dd5cIg2r3gLDZZXVLxf/60sfhlTe+O1kVoPS0hBi
dbCK7187QxV2iVQmXf0gtD97EcHaGcFfJp0Lfgr1gx6+OHaiNdov+6woENXPVy/g+ubCT8P4NAI4
FzgkyD2nV8CM6loRMQ0eWyglw6o2WTJfIwjkTjucqx+LNgBzdCtqc96BuSq8Lzzr5DVBYosos+Pi
Qp7+/dKxL7t9gb0EVQG0Mx+4ZZftIZ7/5ZDU4dWLr0IoEnuO2Bm4mRj79a1eFznxZRk/GLcoZgWL
RoAJy9RAoGzdul/kYS2673+5eu9JhsREdeHUPgtIc7KhNO+EOCtvJNywZP/8kOxKaLTzw1vT1jMu
49BVrqz1vPdQfsdELuqknI3dKfSM3esFcGmQpBvPRHpWZXmR1HT17pIwCQJX9IYPa8EvYknRUEcB
BeLwol2UqJz05VAPBRI4PitKIgfSSJuLi9Ew/+1Rp/+1PkO1PDpl9WCkefWJM5dvb1BjcKOzTzKS
OHMJUOrOoG+mofR92M9hxyuWI5krdcIUJr21QgHq/Vyl7zrSqa5K6PnGovIBgNJZapPPL0yohE/H
j5tA/bW79juXthN1WWR699sa9deroMvrLIeLWUOjQ/CZhALj0WB5Mx8y0PkUB4opmF/HJ4G744Zn
G74lFg0TlN2DQBJ182gP2yOJf9hPN/6pO/zImRWjHlutj7izil7sjqp82I0kLvkJn4XxU0/iDoVV
RlEcxAjtWjsyyyhItADDeIdk+IsKJBcS9P+zX/rr2UMREAUu5NBv3TeZ/gA4d4dqHwhqHPxf+vfr
KH5axqojcTas74ldq5orlqWFAGpr9Cz5l2W8/XQKaNvVLaJc3boC4uZD5blXHOAJkB5LCu6ZcRA2
9i0fpUHIm57KExwA5j5sHyFxiQVA7csZ8sGC8swcjDNXYeUn+r4gkdNd5xDXGsP4B2/jeLaHFwce
wHmPB53mreS/k3HOJrjhOw+Rfx/iprHtaDq9fpsHHymRyfDTTSpRo4iGlqqbpf64J063bjqE8Abr
5oAyeB+NaJeIe2WWAy7w6APV99u8EX+vGaDanJ769kDxibkolBCn/4p9lt7MLrCxbL4FZzIpBRBJ
FvuBbJqdgO6szm/VLfManh28dUpkoJCZ5dneMMGM7uXAE9hm+uEK6qRZo5Y1GCq43iZpEg3Z9S3U
k+Zcj24836eDGp1BNKzwXCfnlugiGL44iIfqpwqWfjcfbysVedhCGE0bYb0US/nhYQSs/5527cBB
VR3FYlgMNGbX9ni5eior9CGiN9O+ZuJxmD2UxPO397Ll8cG+e17ojHfahy8PPzPHs9F5qKoJVYM8
nJm6Lv936wOKFM7U/bGCI1+a2fzq980EGoGS7n900uWjKTnzFRpSF310+tsHQuf+EL3OJFIh0RWJ
S8saPYHBMtyosRnqBDaYps5RZr7qeq+nh1xI533xYM3h78JzqEUy4AF2LxMZxFkmcz8o09ykAhZO
dx/dI+oxh2OrMx2s6H0/RBB6iXsQ+2+PgCrzDGrQsWkyXmiNEI1V00tGU5gTbPF1/18E96Z1N1+0
oCuKOdN8xU6aMRJsVCX6+U4shcl6BJXB6OKzq2Q96LQSsOtbAb+dv/kfA8Fj7p+zmNeMx6v8MqZO
5/xueMUV7kT2OV3BVPaGTH96mIrFYy12QaeLgUj1kJla/egkpyjgtO9mjzBQLnbSl+K87uWTPNvY
Y+HJxIB68KaQ01irCV5QDDwHnjIUD1/6j6F7D75CiZJ1esgF4ZgAV/J5KZaiZaC2Pw6b2ppE+eVp
78Uxnbi/Za1b4WZbt1+M/moJJd1gig0XgN2h/FND3Z3X+oN678sVUUhQviDCMY3XbZqTBSkbjxXL
+QzphutmCA4TeinLUbsJ0IIzXf2M1yZACecfOvH9jjBJDj+qTXTLmidqgP74mPduKZqEntD0JS8P
r2PvGMpYZeWZfXmBSeZHffXzERtSGhqoACtkE9mcMRnS9rnbX51+dU5SjI3rYJtYdcaG+5Q1qH8h
MygYm1ZoRnOq0veWGX2p7PrDQ1WjWlIOd5dxQ6wMpVy2XisEvU0+VBx2ofWFJ6KSzegfyAW34CE/
IMAQvhSFg3BJpAs1GvLoU8MoocMsm5jCy1v40b7QruQ3aYSBcpkQcFp2o/5RueC9Hy+0IizR+CmV
CwicP4B9OkwHpgqz7ftdotwr89wT0EruOG3rD/Byod89Ukr8vvZDIrslExeJ17eRJMqy0NyOd3Gc
JzIXqDBGXsRBYRz5t+6797Qpln1vTuc2Ll8Y0rGhwD86GrszkzbY24Fqiea5ghpHg39XOEtQhGGj
/7paLtUU6jCLNZesOd09RZOUawCqcV7jZFaJ9XzfFKmlVOcz6FzuAQ90xoRkCynmsFv+BRFRNrx3
etcxcbsT+8efEiEMNsIDgBkjuMufxSC1Tdf2UJsN53NIRXGMno3hHEJyIxFiA4lgWHGEYfafIx9X
+jW8v1VdZgLEuvsZj2qqdlbbPhdEdKulArYxAf+UMoLdy/guGFgc7SWGfEjgh1AT3flok7zA3s1M
XBhCNWtbctEP+/Zq3xmb2vQlsJV9Lz+BH4N2GMyyMk8k0ZO+bgvPSNPdDvyPXb02pVlUrMW2H/4B
IPaYmMKZlTEsDMFFBK+M62IBlsm6jHRtKDg7PRJPQu19fV7Zk0O/VwGKmKR4GcAE7SCH8mzNAG2+
Yn6fQXw3RBOeAJzbEFutTVc6OwS4noJFTDiLoq9XpGoFugCo7hEa/DwoZYYEjayyJi+UwdutFxOE
G6HVakx7dUqADkOqpu9pqexKUBKQWwuc9G7jAU0GLpXuMea2xFvXsF5MNhnRiu65D6PbByqUhidu
XH9vKjldT1WVw/S52AHf9IUBRfdhA9eh256Wl7UkMO+fLftlqEsRWSaR7AOlveOIErY5L6731lr5
k7sa+n9vdHWF5CkokIzxeDM9BHeiBTSU2d/icc8J72G9jJLSN7kXbkwYZt4CZxyRkiuaAHbvYgFZ
r208DnqVuXzazN8iw7Z6XD3YLrTu4rBzc9k2U0nElkx3iFOWo/1BomJEUC0i+532sCz9r1IF/jaL
w4WR2LtJQtSe8Teqfv2eCvoKBYWUpKOocTSmh+e4Dya8zi9qv7zFzDHhedfUxnl1Y1wyj2EQ8keU
jWcdNXPHYbUZii8YP1b9CqKBsFi2P4m3InbcbWhn0ZvXvDTyV+Pfm5F2ng3uFCEqHlZ9F8DKWHbZ
mA7oUYBUlrXhwhXkx3jQx+a0WCZernzAAZJi0mXznU8+mHFHVUIL3mdZclGjAssxT4vabRSON5nh
D7hF6UDQt3M0SFyZM059nmPUKELf85iscB2HRovF5hYz/nuKWzaS6teTXKKZDoEI6E8ykTjf8lhH
aaGeGtgP4UH0SOt2jevPa0YhfmKXBw0cAO7IqmfnaZpu8bLSUooc/VWrZmv5iVtrQCDKuCuPdTiQ
ZXaq2CA46SYBn3djpCJcFUNs6QQca1aQ8r6/X9mrnZ4hwWq0vRA/Js5pT1yFBHF/3+ChoV7auRLN
LThyhopyv2ChEcQbPB1SRiizpJi+9gdcPZQt7jCN9O+tnJR67jwvhdMLPcIsao8/q24WZwMsWqf/
IhN5QS0IFjAp7XK9emynaw7+tJnFVKTQgaEt6GqRM1qmRRyHsCkr6FXfbY818rXPn2N/sKdnK+jG
8UUNFf9vSAIyL8G504MVs7gU3H/NhTLd4SE1+iNHVTfCRC/VQ7RvPEe/GilteTLA4EqIgET0umBr
qQ2BppM4vEu6CoOAt/rIC9D4Jv4fVAVp8K7xNMpWysngw42R+Lr6cMnXb3r6UL/boyloTNWsAatH
7AOBBChhwuRQVTR2dUv36LGOZC94ffHptu7FbWXd5JHzx416bVYwUEi7avaX3nI+PaUmX0IUWPu/
0bmbGxK62uKn2KEdlKoCiXASiHe0i6gZkHh/NuPBqOVoN1+7MtgjjL+itEuPZDaqc5OulNUMzSGY
ar7uGi8xwcoqoMGdtRiKRzRWROEZs2ssHrFHNg0rbDmRG01kp7l6LOPMV82FMcsFcUjXg9/zMEmA
wy+iHqm+eY0gSIuZK9j4X92hBBBbORkcCICovylBl5Zh21VLKHM2YLnohFveMdUzeovlvgrhXDpj
AmgGni8nwQd710FbQFPpUY2Q6ysBMWTk6DVhGTrz0qEwxImbjeepo8RQkoHilPWG+seZuU+ZSdGP
wBN4anjgPziIaGWJ89N9hGfDjSbebYwLlXJEpUuNsIMlS2CXytxdTlKjVTWtymgdJdHqWWxihjUQ
L9ME2Wqzz5yuLwUMfQAHI6UWNzVB3D/Bu3dTUt8Nw1wQ/5zxpNdgEpwtL3wm50veAwYAonZlqh/7
IoHchP4+sHPJa0RW0g/5gYRokIiYd0gdWSb0Hcp+ZPwqVKO6TEU54BLrBMZluk9mlhBUTT0Q/CM2
2AQ5enWGtoZROv5OCIbxTVFLtRIpD25wwZgWtOAj0btAEUPRqs1xkCqD2Cb03Bshx0O3ubtKnw0B
aSFLTgz27UutcbpRx/47FhvChGwyz113DAhWZUo6gBLhCvdkk4H7Q58WNNbFo4Z34vjYq6x9osfs
yb8G0kY9KdpViblevr2QNQ/SkbcwV1Sfrmff2pctQHwyGuhQH9VSbFJnkTLTuMEyG3C1+B1ii0Ca
seSwxwn5/ZuyTJtFRuitALP9mmI+/HbUjehXmi3vRZX3uzCzM+aKhuMj9zMkX+1Jm/SduKXALsu8
DQB+2K0DmTsFM+Azx0MDwExtRzgbYdH7UrIoBuR+fBVkKCrxqKkC0Dz/GRu31+ML8AdLWe9u/Uwg
o3C1LUZWBaH48ODgXQeHhLX39OVRvv+IYkG/xDU5IuyubIW3zHC2f7sjjcFsKxOE0okDvnD4jz9w
wrK/QAcW+CeluzgltDbZEOmUD/bZo0c9GKcOVcfbWQM40jQlWD1en35Xc71pIKFULEknxIxSVhz0
w6UjDxYri5RxI/XpD7LnrG0tHjtU/xvSEBkklhkTWOYpfO2Q903JYLzpKyrZYFJaJ3tGXhxEb5cY
9tFJEag3fA+fmk1McajFSuYBgyGeIu7fgxxMJtFBiTx8C2PaRvEOQ+YANybaWmZBLdzuWQWm80Tl
bcwn8IfH9J0BYl2Y5kj+zDu4iMPLclXa4jZS535advQjPiTk0UxoRP674uyyRNj/ccNjgnjG5m3d
EYFGDFuupnKN6TPOHKjoCn00+OEpuQyq+JjCPn8Q+RR+kX4Xe7M/6Bwp78zPCFBA1HenbW4Hf8r9
XgbEZTxllt7U34FQV99P24PSVQ8SFqyJg8s+cVzrmP/t/yzKCnuuZcgm5RWDE+xqmXSnrjRcoW0b
hW9stCSdIIumWsvtYZlDDg19s1YTty2MjuE/JheiGtP6MBC5HIwhSrdLTwcspbMdACJxBQzW7oi5
7JGkjpVloDA8ttmt+9usl80aDgNlLhgcFNEbvim9MPmW2nj+WBtxcfZLhSoCpM01ljkF6J7dQ9+b
VHGbO28Q2ZfNuEfH33HPQoqwj9IL6ig6jwyhEmvsXOwaKi2QrD02GCA31yZH+uUjwmPKolUuKUbY
G4oWn5bxtx81IhjF6ZXwzFNcwqdD80EBR8uGOVwe8DAZ8j3aHw5N/qlp1+er08IysJctc9VsUvrN
QLXExBJHqgR2l7rDuFh3Muj3sFR8ApLgQEbRxNERxhOEBYW+34XhaGmNQ9R2xg4MpcqC4cjXyJ9l
8TeH5t6Y7u3QlYqtL4Sx5gwwgvNXvwY7fwBWyIzm+UG5ezLY6kviRBVFZICbAsu8/O1+J+iQzdL2
TFgzLZBwFfFeV2SqCLXmMj45RQ6Oxp7ZgD5tTydTC/DUeZD4YCpeUlQ2SmkNTuA5W0FFnjUkVpjf
XY20vfmFWFB3O0edUUDHxNT+fjzKuDNBVev/XQifBBRXIYVo2CvY9PKffxxVQFb+ITGCmJL5jGfL
F79LPXFkf73MB2ZgKLQ+6T4i/VXZNgmS0t8mMB+XZzY0WAYjbhyz8Q/XTZIJ26+ztotp+L6EzNTN
cQGtBNPLR3L//nNjv3QE1+78d6pgeLZdI6R+OCc97GoHnnH/X1F6u159rg119LNncZR8ZQ1wy6T3
dWzm9gw9cAPX0O0CrcdAw6zRrqNC3kgC/r5bzaUfm/aJWg2hrjadB+MdFpWp2WKZKORWrDuLNPSx
HDyYdyLVdE8ZAuLiiTB3lFlQkgWsabxMHBFknDcjXFW3yU89VJ3SwUr8IbOGviTjeiX6TXN/3C2I
bC16kAzaqUETZSZG3ag8VrwALp31WlzE1xLNWfGTAIWaRmXQnCfAvVKgY412Gq7V22Vtuk2rVvDP
Tq+kqw49wQvVYlb66nilRbF04fpvBe/29VUxD2Zoa5w4cVcNavn7M6NdFfM081RHWbn5f7mFOdly
eJU1VTLg0R1+tskc7HJcQ/BLE/3zPJ139UrZcW6Vjv9KVC2p3e3dXTcxM23Ugl52o57/z6Ku75ce
xXLkYbHWfZthkaFm0Pg3jHcyNn7S/hqNiMSGQcnXrGzi1H3r2QXlBDQ6vTLR0XQujExGmTa/rzTO
CSmtFRB8vC/v2BoPXi0ZCjE/NFr0fXfnwRJUzxV2AxWYQgu5wm/Tged9MF6mf5m7q4d5GzJ8YIVC
LWxNnbF/0IyTYIkZsJrx3qfpocCeFvxnn7boRxh51mB8DYO479qYlXb4gTpx3Oj3wIjikotu38e7
Fsq4KMuRSxRksDPnmEK1Hb5lkwZCbBOdlA6TsVWHox1W8stUH5UztYR2EtzFA0fNOZn5ThnYgwOL
eGrgTifCDFNprQuNyHZa+7izldfI6i7vvlzbz66lpfKB9zL7aGLUhiCmvd+m/gKb6fX75g26348X
Odpa0TcEGA4Poiqv9/oH3IRb5q2vOAqzc4/Z9xPdLntSP1oCrtW18/OaMNB7FIt3q1eW/B7Bn1cq
6OcrecbFgubrzHA4BN3uJoFTjng2wkaZoctZt6JMnEuLYg+XjxNQEIx75JGv7NOguocOqxbEi1Ai
o9YIl587IhOnqkDAY08FuB6KTX/m0NhHyC0fcio+ySGu0cJDCcJqQ+TC9EwsHWpuwWRcVwglwfrk
L0bHyj9FmknK0gI+bu0kesekJMo78q7Vj27MUirXD5lZ4bJpQ4qND1QpHXL2BFjTd9D/mwI8t5Ns
+I4AK1XhM2Tt00kJ+7c0LfYuUK+08gwTsWz9shnYLAxFeiK1FcgZNKt7tJGkN8cu4b5JezmVXWzx
Cg/73UZ5Qd5vb10h8wylLFV1XBqavwdix1Q8HH5MATbm84LmlHNhI6uGIJbeTT+5IpjML/wQ9YUX
ttNU4NHnRduJvpcvUE98okrGbr5o3trTFT4JqXmWCSllrIwIBS+dCBEqmE75DEAHd8Rl3Wufxg/x
ZiuNSBsFRuUUV8faZtljnNIP3cxgrFRQXjqITLuzBNy94un2Z+6V1w/ycUcWGSFicgxXpotXnSMK
h3MosU5sXKfvUhhvQsIZYXyLq5yRPB40qCcMI6cN8Ko7Ey4P7Cs3YhG3R3SvzA8z8a8nKNbPCWsT
XxL5XjJvKuXKV8TjKOSl3Jx+euCZYhsvoArTrsp7s7g/ogn/HoULna1Z34P9acYg20opniSdLqd/
3jOONYJfe/K8dIRWrZd8B7h7QbKrhbufXJ4UQ8C/qG1bGoFLQhOVx0tpL/lIVC6NtxodHhhD1gC0
XsbQaIj2CXr2L8WN44Tuj39gmjEAjpZwOIL0BMfjrnYMPrXbx6N3D6Xy8reQ+QoA0/TUJztpdRQ/
tijMU33fSu52lUafvci8pJKUt5ReKVAwe21ZxJby7aLhmzjM7VqdAy8RMbSCi7ogGOcPzjGT9Bcq
0pmzPQI+qmG9JLWa58eyXYPIZQEOcq5+EcMc6Ha3n+6t2AosN6iSfnzdGyNSddAZWiGWkFdorEi/
0YbdSM3yOgEqK7IV5FtFv2YGkO3vuMrV6i9+LDI9lbQPiGN1f7zel1LYA8Kl/BCY9jNYKeS9vF+A
6Siyn7GbYse9NS/G7U9FPgq+UMxlmdZpYhGJozaq6gBEOAfhFS9w6qtBS0mwdl1i8eRhwWSIhpFg
NhLEQ3JwSiJdJDR2te2jbKSOUFyaAlqSzVC/MrMm/xN3sIVwcSfT7YzssCjqj5XmZdnpNglv4pKg
c4DGmFz9p2L6/Nrtc2PE0qzDlX1wgt0ReCWAruvs8yECw4rHVPwG/1zXB5v1XDBMnYzSNZM32nuI
nKgLP3HaRrFI66DELTYOfm1FsAJo9I0L0MKasX5iIgc4gzof/iqUtw8Kc4zf0CMVYkdz5tLL1zov
shjr7hx37qCe6SwqI/egGX/W6+lkKrF9nqAjy/l72A8OauCNhjhm/WXO4GitroFs1ZjiBeIRmsu4
F0N4rgUKieJAApY3FL0db6YgyHLORupCmjVBfVR66RmMN7iUL/gIpZwq6x+cTTjZGwVD1dm48479
ZHUarOa2ROBoIT/Del8GqGZhIVEOtle8ybOTxl4wMaXGrTebSlJTByM7OUo5GJ36fp0A/LYERjtK
NHYHAjUGGG4VjBJc1Udf9b8aQXcbaynq3SczCMBNuxdhBhgCwGOzH2TmneGSgkH/hgcYYuOnIE0c
hGnda6H1JvNrQK56wIfyEQh6uAj0yPuywLlvHKOlr6ugn9BjEWragzpi7stKAuwGeK5yxLSpRaXS
+oNQekcgGhades1cy8AYJBbSm4DZP41GaMST0JIq8dASlRi3PoD07Eiv3iEjsK66ZENeSRVP12lv
M8p4la52wOhP4kIWiA57RNyFa6A2dsiuYJqbSQS/LGZvUoHHYMhz0ZcS84yGzfuogY1YWs8Yv84z
6xsBlIG6gpdhOr9VYap/yIK0hVVpFws90I9n4GJXPQ0r0eOrC3yIBroYiMSeyiNlendZg1n8x0x4
4Tc3hboWSMHVEgJ6C4w4E4hwT1aOuA4OWpYsnA2XzOLFWBXvGPedVr6TOoUBBWALpVfmYAZ+tiy2
Awz7fKqo++puHvq4QCH82zRQ1jmge5t7TvZQ+5aGkyD2InyxcQWLpO/ZeiDTt4qFTDTa9EduQxQS
75GEDcjGKjWTpm1qxbB2N53d54v65PbIjWrskswFh8SEqXMqZfJjODbhrzIV3LLarmkZkHmjUVcS
a54k8J5kItVUmuSXJtW5OubkMGkoMFnpZvxKn0pKAYQFnUi9F17vRBfHsBijn6h7kcptTqYebJd3
OhJnKSoPvb2SOEjvpOY6imqVxPmHFhbAGg2qaQEg7iTkWMKV5+lCP7CDiMN/dF4J/e8kVgasrRG0
xkK+s/ovlyQlUudmYcyce5vUtXpfd8qn0xxUOCVYrOBxFOUsgnBehOcAFHYVGiQExoEV6e8f9J5w
2/9iiQ1uE41D+gWP1o434NnbL0SWU2riYQliM87mNF54rLGxQOWnE3AOHYGaTUtAR2n6hzFYgMrU
n0T6EucBaVaIRUrKskXyqHL3XWWER58/zIxbhXkTBKrYy5cuwmyxK1MHUoxpoD+vqPiVADPtHWTY
yr1R+VfXcKlLyoVE7FTmhXs+jfiPB4rSC9k1wLROPBmz4ezETWB5M+PlGpEMhiQ698h8zl+1DbgB
mQ7TdzN+QQ5H8yNU7NPnyB9yOPi6m56OdIadPZCgb97RPpmzINHfPr0D4cWsICCmkmFNUzT0q7jv
SjMZL3VtkmzkuGA9mHvqNCj3Ikhw64YOJXwFK3yY9zns8odkk7GaODDIktXo9rLOSfWmKVGimib1
lVUxLdWV0TAJ3K4yAQgBDSzmgCHhLMYw/fxaKWw+Ch8EcmnxvqvIxTXUE93lNLLqwTNlnrX9WhXP
3J8rIrhrhx02UYApGYTS+E0noRr8R9bJmpIPAYqyT9kFHQ4Vp3467QjPOITma2/1jHTxc0y5stcM
5DT03tzLDEk5GJgCEjF7U4dX1Y7zoow/vnYO1uSnzg9KRBGUg9Emj2thLi+b1EwEovoMczUjLIDF
TxV+h9t9uqoJPA5YyEGBE/wx9ooi7TWZmog6xi+/qj/34uORyCmqHttqLVe0PA2G3+TLmARj+O4m
l/r/2KZq9k8DLgrQtn8kOFsXYeQj6/fVgARza+WfOyNNHqAqgYPbk8hmDwDB1O7qgsBQ9H5IqU+y
J1FRuYsx1/vcKLcgZSfBfGycgAArWprvLZVc0oMzK47eAhKDwK0X8EbaomFvlZpM2HUkJgr2jMxs
NHe8ALd9R3X5LkIsTMKYuoKUSJsGLHJQiSVb0Ghzofz/iMV7n8NWsqbEfJG+gxVwAWx5BnLzS8D2
QIjOsVdCLOIXaCs9rXF42r//qY8u33wb2C48qZ/zdBAOhaGLs2SHkcVw8CtOM3TgTu9bT+kF/t1T
oYIVXSGlcZ7L/rndviOVlf20Pmb7EXc409Yt+02K0zRfDk1+yWRoO7/ECSTH1dlslGUe4dKNYmZn
YrA571zdOO40k2mFGdYQyyO3Gj6G0So4JGwOmh4aOZgSLeIkS3GwS6ibLgK0CnwYAp7HARDBzqox
E7/ezuzlDlQD5o+DzqCL4isqJnP5cKKbaWvMe84MrAibAp5MnPXWZt57AbnbmquQqMqDX1GtOT2d
FqM40OgneOpUaVfRToI7B3wjtmz7I5f5bFAiSMF8GT4uYhRNsQ6tXvBo5dUps1NivB+j7AWfN7pJ
zeV1scoT+Be9fPWxuRevNEJBm4zcqEVWBHKmr3qUiPxbhywu9ziVAMCN7Id1nj5gcfLDxJSAmJX+
8RF0ng/GeNvM78vrwPvmK3aLX+amSCuJc1891cIQKO7UvuOYpUTzAqhP7lfY0Lm5JjA8JJG4PP4y
0/CqitkjiUhTK/V033p/Z93JVVu/pN+Twhwb04LAtV1FXAdkmNO8KjuDJntbYMZBNFMZ/tcowK0Y
oIooi8tCiBZG3gFNOne7NO3UPsn82gCaOzbeNiVqntdn57AjOvwl5YmYMHpmjjOX
L9e2omdy0kM=
`protect end_protected
| gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/reset_blk_ramfifo.vhd | 9 | 34296 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Rj+AdZYW+VUNXAOz3XP0Xp6iw2LXzjpEDFsEuGU5GAH+XonxCbUrPhYORH4FVIuHxzCprQRbJGzO
eMJpaEHzbA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cTcVm6s0DGxAAMCtdFyx41slUgDDOkCBFnG9hTEM5KWONsrIyDhEFPtt1A09mtlRb3+AKjeg0LZE
QLUjEwDoH6AjwVNz/0cpFuaQ4WKQK3jyXFw2yWh6HM7gj0bp1x/fEO11BmQpBY29AK4pvkfvhs/n
Br2mIb709NZHQxXWARg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
DLaCV849AbxcVKmbzKR6hG0c8ks3pP5bUlTlbiQNm2ZnSuIbRwxGzlnl9kCTJ4RrZqHgUhcwnQkK
KPLteF6xlV87r9WKv9kPEUdWHZEt4WXeWqyyuHySlO7nWt85AjoHSlW4Y3iZ4zdSLyXGn6V7u56T
UM7/fBQWLiPCAWez0B/71bfUq+2ltHtFY+/OzGTdm+5qb7DPAHA8QUq/YTag6iRctvrFEilJRATe
qRtQI+pD/MMwp4Cr15iJydmtw4/tg9W6kuNsa4r7QZxMnV6B8R84uXsaDh7leGH7IdoT8gI5a322
civH5jMoNpLeeFPJ9j+adkRWtlbNl8nhMU/l5A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WGiRuSTb99wWbTUkGbaflGglYU0XLEiDl1o/pQVWtssiIWXPJdE8vXDZJrMxtWcriMSUKKeHz5Tg
w8XNGXV51p/kQp5tV8JZOAzCWyXzHP5ZVlQBXfnXp1v2vNeCAqKagA8U++IR8fMk0JvhSgIvGqNP
xgSTySyAuaLR3SrZNuM=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qj/xydO74HwkhcEvzqBQ1eiF/Hw+vsggtXGUFOwhzVihvSNhKxTjIvdvB1VJXYwlUCqyYnRqqDj2
41vijtHm+4XO7qI8pMw7CGKmv7IyZ7YQtXkUgHnArYeRfI9Ps0WvOMvJRvu1UXtaHhCB4ae/OqxZ
SnHivzrrb4wqIls3OdRMP/o48zY9lnqVAsoeiL5Zu6VN/rRlqdcVlOCrGGkw7VzAN96bMfFgCwY2
iucbdGEdAR8fcL01x+/yiduys+NiSdMCvMsPb15qGzNj/P8JKFqKmNqRzLHudKtVsOTqgpQ4WgPz
MNEoCx3kWPDmsjHvxm2399dnFhqLtV3t0G7Ndw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23648)
`protect data_block
2/aRFvIsllp3fSjtVHRlyV3UBtXey3LE27c6z0X06dub5JaTOFBpF9WFOkIJoDQ1V/qfKQ8dZx0g
NJzFhBthApE2T8DfVgWgd4VhjYeZzzkCAgNiPDeXR7gRyVpxCTYJFQZWB9FdRtcRWZs5DGHvRIvf
c7rOFbz0QbHh2WltON3eViW1Dglrl69m0Q0QhSoBeJohd0qBOsjsmUzEgpCyQLLBZAKSVL73535r
bZvXt4fEUkAAoDY7/XcU92+pZwLNC9EPHVZ2r8t1AoKF6w0xb3KB0K5tEDug2eeQknG4ah8GYTv1
FsVZWUryDymoSohQwny+k+tIh/LiksbDPfGY/rbKkgrQxS4RWBXST+kCdkMaIt7wEh2ZSXFcs3Dz
m+APUA4SR6uhYvHLfOkYCBcLDaZ+QKLqOL3Y6HI1jdU/1sOEbBHo315cLagG7IzoRF9U3wOBhOkS
U0vL385x8JHPAgrmaytmoBu99MXQt4oTNDvfLShIrANXx0Nejl8mBWVy0OX87p1h5Qa6by1uP7mb
Xjlts9g3vBQdt8Le00/pKbB2rBaOMRfPJWIXNXhUOSqCrSx3uiL7R5BZf8CFRawySq9wOTP41MjS
nDFAGSKM6OcjQDnMXgX9bi1XrWu+82Ed2zlVK19QHmO73cYdCzLVDkDrwer6QJw0rn+n1Ml1oH+m
0aunGrQXVx4SKhQUQc+1x/P860jULJWvq5J3FlBS8U0QGZ8u0IZWc2FupGHJ08V6nnzmbue3uls+
2W6dxhWlwJwzXHGvSffgjIJbcF1uxKrlL7VoSdGTLFWRm03TznmxQZJ3xyAhbAF7rtZrVTqD9kio
UpdgmbSnhfUeQRZ188iO4WfkCCEF1rj19cOwQHAxuiIJw7k1ngcYDE6V7uxaphl+66tWHFD5238C
VbZlG4EoN9TT+twQmdk4RFdeQYq9mERMf5HQA/c2n7s658xWFmPpefcuPsK5wiZTqKmwZaqnP951
THgT288ry8fXAeiTq05sZTY4MAjj4cTCpZnEEnC1w4D7SEQcmZOJPd/8xDJ69NywR78OmiWIlaBr
Eo8M29VSJcHdCfLcgjE+ZpIUaz7MbNYZwG1iUMbj8CuSVPEaXYBWPdNln7RDkDiqBzNaQbpvc6bl
GM5CFx2955Xtn4ghjcN0Kbke16c9dbxwQdxPUIun2sbuygwYhnEac9pqDgcti6XL98SpdPcrM/Mw
Mp9Niw5uJtgcGeDL68PsJzSpwlggmWgnO3Ma8skMnLwe+6x3YSV5qEPbesy3fO4LLaSn0o4D91mz
rCqFWeJk/806FJqB5DI/IudIjUVkMP+ueBxmOmrIN7qDZTKPYahhX6R11mOtyDph7jrqiazAUfF3
M+BuIMUUT1pAPAkjEQhVvX5JHsKXDZdFQNIavCA09euw8SnBvFW59k+l84VtizHbLMlXMNU+Nxlt
4XG6+g5s5ccBsn4jf1J1tmDmFAC5S5LHMppQeeNWJtYsR1eI0iFTq5HQF1yvM0GonkgsXFSN1AxL
PmSj8p0hx9DzlEOfJPjxHPLr/iSTB5ACJrPajQcRsGlnahqLsMFZz6v+/JeCNAPd8TRh2BeTxlhc
4MEFTTczoYHDoP3rb76DLyGnlHgRtRYgQlFQvYbK9s9qCHXuiu0iwz8vPeuNLVwV6bH/PbA3eUHN
i3hCVZzl0PBpVRDcN4r0rmv+JeVstKZJii6Qp7N7OPzrlC6cU4aDlvNtQ/aEIqeXBP6ofVvQ1IJl
JCz6g/KQ7pUdlubQLhnR/uPuIekHgygYadXfe/IuKqW43iA26RWYBMbelVXxdXF+uqy4njGknWZD
YDLQlWfoC01JcYQCrJBYHnpgn4i2+zmO1pNNCv1tA7H7GBAUkb4g+3xZHmcJi3cZmXe5imOaKyoo
cujbYnQcmybhjrkPh514tRdX6hLvnK4QkgrUW1DDJ83ykXG7Qq/Y4kgNLJVfzrJ6fn0IS5VdZbYt
h0ta9b31YHhbPmKb3pE5Tm29dVfhmPA8lVPtJaFi0jJ6wZnErcmtHWUaUgPms5ja661FuzgPwaBT
spBystI7uQbg/5qFv3Su+Ed0Ncguj3V1j1/PxCdisXVZ6YC43qGkOF8DDqFwwQgqi3b+c1SXCl3r
Bi8Axc4Zr5KaukR0uUCqZ9MzI72ZFFj8jYE4rqqj/MjYX+uMpaLRJXm8k8Fo2WrKAhM0HinoHTP1
YMapzCdslN3aF2hIvXXrJi+v7djhuBiT95nx+xmKhHfxOEWxZpVFLVw1/nBzeyp6SbUlGeOZAXYT
MmtaHLy6RgnmYzjNaXFFSjXlub7hr35Ix4Ec5jtEki9AXb3JmcE9YkMD+dX8M5QfZRhw9BCQvP4o
8W0rlIMUZYm9UsIeqdBtTc8ha4EG2HViLFPW+a8fzm63lMhJQ37cGAkvEYSZsvfF4g/Eo0kPUGPU
nQV9WdG0EaLB0A5JBAS//utx5ceUIb8OluTaIsVGp/j5pslTtyaYj8XPxKS7o1RQwmkgrVAxQhKa
I6m5x1RPUUjSZV56cbEVntJyXap84Rtyh7dqvb+Ix60o801OeOIDJNdoo/y84P3J5PlOwf1LEW7N
EzFSXvI0+NHYO2VaTluMtUd2s2fxULqcDrx3t4v+VyUqKuEGE1MUeGyCwclQJu9jwmqiyHGVK5Aq
j0v6JyySSqXZSCTJqEOa37irq30J5aWUwL8AqYUY6bai5Nb57GGRvpAblvC6SfMcHZiTGa1cPH3i
cVj/oJIFknowlgcdDt1Uzg8kSX8RTVcqSJwvujqALSlEU03CdYwCd2sYhT4hR1H+gXiR4r2V/OLL
RLKRSCEVXjI+E6d2S+CVzf4ZNeovUBL1vunj9iQ0sl3A7W/vV7rzmFVDhnNC0UlDUPD2mvFEsZrK
SlMVbzfaRg+PiuAzCvXlbH7hc0UnEGT622TWdXjus71Mi5D6eSWhHlAnMp0fzFvN9YAvbRjSLRhU
MupF0OK6tpXdw5warDRiyg28Eo3D+3kQhaKWUg08nHEX35oW2apNmpCcB5qGm0xON2UZodjTYciz
/xsQG2amfvvRICaWEZa1b0pfQdpAcWKTZKBvkjVqFQYlFCaStl+Z3LKk6IvHhJmNu/tMSuQUfYJr
A77uFHdnNf8A4QpCvwQpll+7Nf2QiLpnYs61laa0eGqkz17x6iUElqYrgfrnZ0ahF2bYuWx3pNsC
xQTYzwSs/iWvjmDZ235UFR7fZ+Kr7fyRSpSqLATdCEwlwvzr12EFJVQlYzh3oIEj9ZfAnibDHX+W
0RvmifGf8FNgxIWh0oQQ/KGlAskJVQI65U9XzNni4/qo1CHLgvQfFX02imu3Em93NICkoKZe0NwZ
/CO+lXE4RCKod+NW0AlnDSNEPNKp/hkFhg2XD/hkvPxwMEhOH+KlwgoKkaoMp81GmhuydSGZZhls
fYCngtF1+B8zW4IvRnXAgCjFsYqGdPp90yAcfZ+hwG1CDKi8+LqATcG1WzX3B08KTeqzRjLJkZPj
NMZFeN5XtbnLAzDlxNVulJeEydJ60c4VgcPF+UM9DxBfHXW5p6nFOAb2JhBBew1w5a+TocGwzILQ
5O+/Yz5qpRlHOEN9/WkRlNUzVhODl9f2y9JnhvspHCW3z9myuIRt3mHKbkV+xsJByJAGqrRaGekL
n8znoxYCgvQPFRG8QYhRMIrQ77uDjT8yPXyBrqUAzQhLkrlLla295KSccW0kc/VIxlDnQYpP9rKJ
/phsTy7N0AQqpNfiaWojqhvsfOrNjrHB5ydsGJGt2JAZCAuZ/eXjB3czEUc9fo+9PH6bju28Ivid
ZZL6zNp8klGsSZtFnCI6IOCKo+iYGbBrZK+F9QpbelliqwCBL7UQBhnYdoyN9b4EkbqPc5DcN8/k
nafCvjRz62gslECbDphstPdrolbpPTdAtHtWiFqWURoVMSAkBbgWZr/zsM8DOlbhwQxdFb7Wzp4q
k5HROYDDeR+GExPqIGMXXiJKoM/HX6wGsXHJhP5x7ucao7XKhLvuEb5063GNUlbSbrzwdgA3SlmY
EnTMDN+Nb3hqROzl+pmF7DaFHPXEeb0UmrNdHjXQr9Zk6q71wKkzqF4rkWUxKEMkdB5s+dUeucnl
JHe/h8aA3hUv8MlOR2Ntk7cHJfc8ndYC5U1cjtk0+OgWf1W9ejpsuQ5L9ZvHbXo6JysTsZLolnVC
EtxaDgl/CxnQiTuKvqMECJZbojVrp6J/T7GegpIBVQJklbcMejaAeQ8My8UVbfZ1JDqbshVt3Iqo
sO3u10kMSjTqnehlFzat9oywPkhXLnyhM6/pep63qaz6ciSnd2yNfHws2G/KMHATP+FFXlmba5zP
An8pYnmQcBS+hR9DsCsQ900gLmQLbTN5DvkJR/q4SE6RrFBYk0Odx7I/ukv8lbNK7bV+mQIqD9Wh
J3OX+A2mgsAaZWHviLa4N8yyL9GW4WfZuWDhbhUEgQaVGDxUDo3lkOpHw9uh54nYGmlgs1U615LL
PQnKCDZ9CXi5tpbG+cUUyGWfZArgbFNs2RhPOnf8P8K/Z2Cey3B1St1otFlTkjvrjfROipuHaxNV
7sRVN0v6vfz7X4PhA7Ujq6l9B4NzKl0irvRGHjpRlJL2oMWJQNbnGZbTwUFFqAtEtjCBskhn2H2F
eYVoId0RS/dPuH2wFY1wAiR7sRYPKYIiSGAv+i15bFduNxgFKYUx4nBwUu1H5sDTrj5JbpvMIYcI
IUXrqS9DqqSyssf4XNRirtvwBEb5JovuvgNGLJBRWIASrg330DwEy99f5ZD/Bf7HoHdag835IJgz
EHvCxAU/45RyDCfu6NMuvEV+v9hUP94GOXBu4aw+BNCcQIisxHEzbBKdVeMxPvc4Stn+pxsyV9jd
Qa3x4KUDZQ0Iul1/lk6lD9drFJut4IO7VMAUpblxKUa1WPomxxZTTOCsGZesu8xJyCY+knuUTgpU
iZo1zlZ9tAUPdPUYrGGXuoFFhXbhMS3Vqo/NDN710ArW2XaMSxbr8gJZX0gURdTwxyRsUFS9v0VY
uAxbtagIso55VnIo8h6O84bTSrzGeg4NUVFP7D4oWMcHZRQCsfWWYH8GEWxtlr+5Yr/4CnWp07X5
VxLpaL9BDhUAExmOj1MJBIN6JY3eIGp35FKkoF11uzaAwXhHb7OHFdYp8cTTCh4zXbTM6jBOtvrX
S0+Uc4+RmrS1Io43Ii6cDSeq1dTWcTX4VWRdKQT9GkLKLGqkdq7C+pwj1IP39OidFfYaN3UsVoWb
FvVYAsrwbp2SmOoe2bmiEuzuH4eVYhPaYYdTaENMyTM7mOatKlFyC+WNmQZehBbVWMPudnC8evZo
MDzDS+H8FkqfSt+Q3mUx6C2sR1lN+z7yLmdH+L89H4IIZW1I7DRs5ZZ9Nr/DYIIdx7bfd/aj0G/8
fDj3/9FRP/wQ227ansD3EPszyWvx6NCw0WZck3L5vXN+UQqlh9+0CvZw/50LxGV1L2IhawVuSMte
imYsE0iMM6unW5+QIalNtoNP+vuPi0TQgRAQvaj9tKfS6r1mEHVNeoD9t37r1tonfWg6IL/SdhAO
MKjujdNAEnF1JsfmlKsb6pYk/B1NH4+CUvGQAgA1EmKhK2DaaSUKm+X/3Iylv0lgExUIatsLCzP7
92RqAZzsqJyuE0kth2frG6CwXjg0y4G/bSrgI4C1jGu4ZNbwyD+3Ld23hA/1jl+xUUAQnBcruYui
LXvy2jK6yvyVhrmtLcX6PmtkjOw72IkNSBoAOUKg0f1NrKMCx6y9tHM6kBd2gQDhSjqEB4bGZr4w
BXW/vJtAgAWwCHfvHdiN3UxhAyLYfVVal7kwCCI2mJlSB9JpvIpCSPYvHWmBfQ5xzd0JtiEvinOp
5FGuMXvmtDq/2HqTt8vtK5j7EDSQH4ChIyHH/eG5P4Gcohv92aYvcxT+syJAHJRCLAx6MGwFjrLy
kl+U1cvgN2MnDtbQ4DBOBm6tQ7MTgPGhK3d+apj5Qm49qgyGjuxFIyAj3MY8MMlHJedCmphLBxGo
IG+AsLaRSYgmLATwLUVMdWNiTcUjYHvZAkHdEE/Fc5KOWwCGNffeOaydyuxzd90fRqG5VMeMh28W
5PsZNDUBteqJDi1sq2Aq2FZ4AjlT7ZwhMQAMDmSXDQ2eUT8+/YDLEzB72ivlg+/d63CuzzmAC+KV
4oe23ebTA8z48e8PpwKoetLVQId71qgxlmsrDZ7Wts9VgE66+8PCPNvwV6X6+FPzlEHp2RDjOP29
I2dqdyUw6yQdK0zebMGEFHqRxw0BjBGWxpPYa7IyE7WQ5LkpDvjMzoUZpe2Ob18eJZbf+ln0iDfF
sruSmVlEi1TTAVzHkmJLJ9dupV7yA82rz3Y55WXdmF5km+f8nPyt2qQXGr3ERoA2MfufBqa9bgxY
b7Pnaa30gYr7WCY8iO4ohw0GBBfqGnt9nLgDcPkd5B9OeZWpBZuY4HamesBBKlB9hzPIylAO7Dui
IWtxYBJKCfvTmIkQGmCQki0a7dx3dzHAgWDb5Y4sn5LjxTLR7uz3QihWF6sK9lpgm6qxmaRrFGdv
Cc4YS53e8QM8tHkQSu0+W0lsW9cWOFIimLwaT6YgFD6ivr9xSWdR8zBOI2dFQ+y3/pC+p2tIV3nh
URL7sPnWimylDzWuk5ATYmDg1aDH54U6oaBewEyQ+/qm6chUNO7JsY/v1Bm8eXM460UUADbTzyOn
lE3hTvqUXwgKCk8kjkUliYvIrJ0ncCgGhq5QbPJcaEXeWxs8324fb2BVzxYFqqk61y715T9cNO/O
p0I1WmXPBxSNFnSu38fY6ToWPYbL7rY4sERUt6yxkop1ekFtoSWhu5R/H3hUSLpCHCSUO/pxiVSi
UBbeP0gEZKJP2lvXWRR5YF7HWPQkYsqrVMxP8Iye+2RTTNdQDE/0q8SgFQCq5+RfOk55UvIWRZqq
03RrUwufTBHUwfMgSGP/m08Eq9lcBAie+VqbZkqllTGbr41nPBFr9Q1MF/zL4F348HFB9Vr//yji
ZoH8XPu6dz1n7/p41c5FVXo9CjM07pichU/wlfbA9YGdRTBnWWxFXXWJOmJEfQgGrFBdl3mnhqEY
x0jJ9MiCDjEfWFmM+jfyj07pc6L+RsjakQUTj/Bdr7xhCF1aYRS4hYEjBVxjbplimEigtIGxRg7m
ZCHkR4MAU1tXUuVxgjtT9P7nt7S7HfFUDKKakE7X1uFmvzvcLEMg6A0nHQhsmyvkPRvSsCqZ3pkl
gQSUEbfUkb6em4ZnBIt3eoGkwJZb3QaRsDQvpswIRCOMzBraCtLWJF7FnPyPUoIfDu3XECGcewHA
/noLfNA5LpodXZRsWmgAOLpKfR1UDuv+n2QqT/sMrPa0NbA4ZsASqfWEo+Kab7sY2BWcMI0ojca1
jbSeMYBr/Sz11Hi4fUfUreuJ0UPzaXOdg3MC/TqNSd8ZN/V2R5QeKBCrE33fwDJEXJlUwWjW0Ql+
nF4rKy/QtJ/qKoGY690YSNvZRm4Zu0hnrEnRzamlZrTL5lcfxi6p7o3d5mkWRMcU5yp221PY4il1
ZcrEeueruVEhr+4tqfTkCNjBkiNdLAb33YxBqqEiqCKW9WjMcUpm3RY5mcAxkUoQqxsy/LHGJLqn
b5LcSXyAmQNrCQZuR7h/USXb+Ag1Ker2mqkdZbWD6bXFKnpk9jZAIVnGryAvCD1MmuczSbnZB8j3
WwX+jGoPF1LT1ab4SCZ66pdOKNWTAfXZBHS3EBV4G3CBCbvtEu0GI9Ht2nWl6VhWOW9SdZDCNpM1
dpk6JOmvl2MEhnKDvXKgnCNIy9r8m7TtAWutc5bNFweAc9OI4bYUeJ/LEAr0xAmYfQkYI+NDTVvg
ydTF1Cu8h6lxUmo+quCyp6T7kI9A50m6naljWcrMYNaKEuKK1XZO1e6HLHQBUQYO07RoJBR4zWE5
wYkFVpKSua+bIJx/PsHGhS+ImSsybFC4/KEj93FH+bciCrTSW3FS5OSFpVtXlFZ9lpgHi7Fxdkqf
SMhwcuWiPNNkbXkhn6Lq+VQoN4Ror9nQN+nvrbK37EAhj3i4qOwgm2wJ8MfY2y2Ixtr4V3yEVGly
uoNtUWUbla8ec0nv+Ra4Pa6GB7YBXS7FFL1WNMXllEt7zQv6/HQpOuPzXMgZ2G1BtNOqjdggEQ6t
e1TAFQEjGhTfvacdesPSTxpMarDl+r7cpnV/92mkxe0pFP2QeGYzcWuq//Gvxq+JpjSiEEYhAmx2
VURhGmPePhDlnfm8hQA9w0dcemhORQ+OrSIjNoJJU4ZSvPIq8GMtGT+0K/Xl9K6EbKAS76qjDrws
4g6CnkZxZ2xBT1Wf/1hiDr4/cQFlNs2TxXUxmyOKRnIuBqtmlh59hQDgh/n6hxa3BRfPkoCQC0pl
0emn0W6xh0oIobGXWfx3HZxsEQWF5BGLFY1r8ufpofwZB5/yz+pHYKfSWDw0WPvY96OEprSMRALa
Rel3C/0deFSrVlKXuCC9zMaY3PCOv8WgeOBbuBLmLXUUxXeI9aJ4Y5dE43Q4PBVEp21SecDxiGHE
ak2FUmLUKICJVaGJj5pp0ran4J7Fmn3zoq/F6t2ivJx8Y95inbGtmuwQBieU2YzPDPCSST4Ypogg
3KBWkqUaiiuCEdencl7fH8T++ns0T1pKqs/rt1y8LDQxuHvMuc3tFDB4ZS+a7lxfvmklF//+Dmhx
fsBiNE2dH+AORiplZ0B/yb2rXZ8o+S1vOXZTSG+A9g5Sl5oV4+i6IbRlEbLMLOZX+9cIONxAFjHq
VD1p8nyiUfg7obrNg9X3OsCZe95fQktyyk21zWJ89jU6kf2j56ie618tErKYxUoxdyBYnLwmY9Xu
S/o9mZVu8PTpBVTpe2zxHMgahxzXBITJlcwWLGTQCi7j3Nml3KtXpfpyT2dYFyzEfsnpRmFYnDtL
FUCQPLQVF9od+N22WAdKQTpPmQrxETksyiQEhLVrPT3EUrO6/z3dLxZrRIHTnrei0fzzJottMIEJ
OWA3JSxisNEeRrj1l/th9ta47/0BIjHR1VN+EPqKbL809hAGrnxVcY5rwQE0ed0KqwdSui5I/eVK
K+5mg+4QwVpBFow0J5fuyyl2rWX4Zkt1nY9NoCv94o+mVI4tGKP9BQCdUPCBPGja55M6ULZQstD8
TkjK7GIF3jgk4XWR0MVBCdJkleSTwv1BAKz4FOdUK61LvYnBP0MNas9iiPSMEIjpE6cjAkmSvAYI
IGG9KZWIReHlmEkJT3A8TNr7v7I1lj6+EK+qk/WB2hnZz9SrGX0EOCQ3ZnH5oZg0ft7/9Ofu1c8l
uvxZdMQkrbxOnR8Zf1i/WJObVzSW+jA9X8Ajn+0Qar3mlf7fzFq69bZsDQbUKHEMyTi5+9ryBHG9
NkYlACLiIwnfwu6qFcI5El1KovB+iMaQOtoSKiKNMthXXsv6vbsq+cUYRT/Bx1Dcz5BnpW+CN6AO
7ij48a4ZlQSGmpHxkGFMT6p4R2D0/eFVcpov3LaNfzigR9cI/0s8ThNuGh4YT7nZXoKZdxstiWWu
UFPobFy8JmfpE13Buo1JhJyBGlXDKxRFsM46x6KOwtE38zFXakOJReykRnR/gSrhrbNgM4lah0aF
MWYdhXlBVCojhf1aLNw7KOFRvGI9GV+y/oKswCj3i79tcPzPhe3QBFNNzWiveQt2Hku5NAFPnpBz
1G4E482eLiUNp9jpfBPh5rOFImvc1IJk75QVsGF1kXzNFN0W2zVBD6taJm03zJ2ed0QErndVS10H
oDVORdC7kM2dLOYPiN2EHa0VQjCoKWuf2gT16TIrECkoU/xfRRsB+fPyXcyJcKG/q+OpUTcT/eJi
wxbnzwch3K+WE089SU1XmMzV3GGqTOlSc0n9olyEq/kjRP/Hbhd1P8cMdRYQYYCCN08KpOZCO++5
/EWRpyWKWfvQUGQo1B9GJFA4sQMnyJzAZfpjda5N74SFkCJyMSDJNNIrBuviXbKKkL6G29jNBOHo
VUwB2nxJX4RlkEh8pbsi2guqafFKN9TAtdfCWA3pkCF0fmYc8DQb72hqfCWDZF3d/TQq4B996sEo
g6ZXy/W5l48cbULQIYrnicJpa+GMwpf7qZdrMl0fiEgOEBXTM2N5HCetb3OB1GkoE2p82YHofimR
UtM3ZMCNV4Uj6s7JImHttk+7MUrNoy5o/hklVgDPpUcDXqrpk1EZGtqkLQjhTde4uw/gtzgzkBJd
lhPtQYwUH5t29Tlob3KHkxprCFSEU0FNl8L7NO1riXRPrdQo8NSWVcR/bh6mclgjwh9Yb0aAyHA6
V4ZNSyp/kCX6yip1cFrkNzbKZBNUND1RlJSt11afcfFNPHkL8ZDJlxHWvCKV9yFhd+CwfP6b3TQD
U3mkHrYySqC8vPGbHQZN63s8rgm/fSQm6gCYeFy0POug7V/leXujQH1ACOooaNq7vPCnSqVOKiIf
h84PD5iaxqmwmWxPVbYhh+mZ0hfa9Gft+/FzF5hPPH9wvPth2I4z1joiSfQy2NkDjU7kbUWL9Y3H
xsSotyYZzmgT6IkIPxRKSpC1k0TFReaY8Fz5RgxNSMgi5EFqSc1MCnRRO61/WpFsUwGErjoC4baS
9PR1Dnk+ovs24tzgsc8QnBSgG3K/bcQJwG6htj/4oXaRWcQyh+cEH22368aFuj0Ev06H9DojxuJN
kU+EnGaFi97fN5wrqPLo1HrDVLIGKykzpaJeJqBiqLt3sJxoSSSAVCbZ5L7c1LnD586UBmo2OV15
OY1sM/Qx2pkm2CPr7R0OOzjltaMLydAdt/feQHqtVsUUwSsuaqFWfB93+iMvp0Swqx5BcjYH3z/h
7jJOaDyGcoYnQd1AfzpmqPW8eYhV8xs/AutquL/xv+wx9L3qR3gRXl7q6KA0FA1cmrASnwjOvmL6
FG6QoDkBAW2LRfJuaFJve+MXltWPmFBsWVt7Hfnr3CF9vFiMtpcHpUjOYMEZtCh+Vbz7o+JH6Mha
Dg0gW265NEYCu8RLqeBPdEuovPWToJZuL2gQpLKMuZwZCC2ivIfoL194rk/qp3eUiz9jOtcpfd3L
yojofEXg51iSVAhFkJ3z+ab15fNtNTZoWd1FF/C4gUlCjtg3r2DFIbJSf7qHFM+Liy6o0Yw2AsDu
hbkoJy9esAMtmfgw+ToPDu/VQ1hrBJ7RNkRia9d5WjS8llWpo1al+KvCgibYXODlP3VBWMfEweTZ
GDmrzJ/kPBielQ5RtrkLNr+5lXWxuMrZ52O7hYBTDSnOQpRhiMcnbMm8eZmuIoS8WG7/1+OiBElc
QWcH+ly+nf4gpUiqBHyy0t40GvCofAY5gd02578UbZxVJGrzx3hvP6PV6zN7RihGe8Y7QZ0uUX1n
n6YvlHK8k9Y4fvqlJgvC+P2p3iX5s2jmODLj355DVs5xEA6iBjLVg+8ZCzw/IalYl52cNJDr2Kg5
m0a7PSYlzeHFqKCaUFb3NibKklnhrftC6z0W13x0fvLLxhQPB7nnTc1k2AG2oA7deamTCl0cKPtE
9zNxMC/uOHIFx2CKGqMhKws6eA61/A4qsh56MFTizC6FB0Yporqfnxjj93FIdkf6rb9rh/EoNdda
5mXQ4/UbMCzkPi5VFfcxqm18ErsUHCihH7ZvYkWWTDFk0Zj2OyUVLygxFB/pJ3OXqVVRCVxdSZTv
YkU8rehOjBA4/J/ic6e6gF96dyGxEUnfaF1F/Mx6w1IA8XDOIF8ix6keCgfVJAkyVE8ziq1kTpCa
b3n1gRIEUsdpDbUcH/01KgJChCOYyNi35gvek6AJt2jTqF8W66Lp3p5uvagsn7emaovASLdbrO86
gqLbFNkIj9KMCuenBtE5onmxg7j+5g23jEUy8euTe4eU6RfSXEI6JB26uOfDOsIC9OT1gKMDyJd7
NHQ5ImjnLmVy5KTWXUyo4IQO1aKhC6LsJ9kQFIjNnjut0dsZc27zzCCUTXqIaG0oLfaFbV8scsGe
KK5Mo0Sg4XljJrPyoVqDXfVqD+i8UahnzPGE0WQsaVuMXAPwR0uAReUQuqm6zvz2kuozBxCr3Nhv
Rbo13Ju+3m029YnDWXqBh4bTZBaN+BGQM67JAk3UWk4b/Kid//oD+lPAIW95py0OTB+xxHUPHr/1
P/b5dG7nL4gIziJ6IF+dGvXUdzH0zJ38FQSPRSk8/DxcfWFzoAFnUcOSzH2WVQduHLXncuQBJf/r
ipISLaIFFBUYeWs3ota/UQqVHV3QjULUn7PTTDl3vpmC/59OvubBENK5P4Oehkrgp5qL5v3O4rUU
/9MUOZkrZla3HwKU5rOc1jnMPNO52Ne3EYGmcSw1o1fWchVfxz7xdTgBiNDh/n4+4/Eg2jxWA1O1
7DR8zrrFIS3LyUsFDt9aUQXFRc/WxesjUz7c1EKNt6DiyU1njvBT+GbhkXNygjAN2wic41U8GBmG
A+Ehd6DMzK0mzF6mDMSgO4abzMIsJyYUFuYiRNUGEPHwUCoZeY3zJiJykgLI0h8397kWA5pmVz8m
Hde/4z+5Utq4kIMOAax8Dec2x/G9HWmkaN8InnhYtNBhRCDq7wm+NMclmnLiciXRcVdw87UWu7iw
zVcYu/OxePZnPzODDCyjYBEhbmE6kPZF3cXVYQeY1PK8xr9u9kYhZpRgj+FBj6juiFO2a15k9BtD
ueIxv5Ue24U8k6fZo4n8WEdjGKctjvklhDP1uE8Txshx+i8D4tSrOEiwEvlTIRlvko2ldBYidT2g
tI400T7lDpo++AN6WYk0VCO8EElncKO1rP4Okyl4pTe+n46uc97F61iGmlTk8w4V83vv3hrA6m3X
1+DPWPr/K5vC6cBVVbymtQM7YNsAjC3zFv4KJh8TkFmJc60WWeN4Ks0/jQyXn1pl4yTZ3liZ3aRQ
z+zzZ6pbomVZAUDfykhBRv+yzbPmnJbNIrM3ptcoMWnDkOSO7gqNrafZYocuNuQ3z0RoatF0jh8U
iKIZzw+jrZ+iBQkIPv5dwdxxKJlw0oK8hko+cSGAKoR5wBbBDYb1//1uK2s2riZ5u1WdAyKSPYlW
Z3XWjf6Le/bHhf7Pmj+Rb3oGmbbJgF6kV4Rd91Xsco2ap4pPSIL/H+UbB/wPJty2KmHGa366ogoB
bqj8uZJBpsOZ5zLGY8K6JZJKQb77WxRwM9xWaIl9uuqmDSRtT3+40siR+8dByWVoX57bqnUIcVrS
YG2F9Ii3hI6du/1afipRMNlAC2QWre76CMUBF7Tj2x07SdBLyXKNfSDW6XfmLKtNR1oYEtyZ7lFQ
hsj/nYgOJrME06pu4RfaTyHhNkD/V+fxhl/aLAdLoCdOf+DvAQ6FA6OJbGSb8pFMKnaLMffLw922
fyTVsnDdkBCAncyr/yawOSB5r4jylondo6TgleViU5lVruZSUodMIJCAPxHcLZQotnA26Mk/igtj
sc/k8t0+xSLhMgUw7E7hC22/aNfaLxiBwRcdtM0B00F8sCveKnxBEQWrvdQrds0c8dFs8IcRFeWR
zPaQS1A5rTdKZ0hbMVKSYMDG/l8SUpcARWhVVqzX74MjVJxbEBZLo9V0JF7MctXAO1QhVwOU0pV/
crecmfO/RqDtcaPugy58ahOEEvEaze45XbfUh5Nw92A0W2jSeVM4zSHD77RcdoIaCwpTCxhXTOsV
oIliawRU00+C987eIbLntUT5884xBaq5q16EvdoVAWCllAz5o+JpQUiC3Ynux50SxJUmnHPwiPFx
XLvBRtescTBfWLuwEHuKZFITruAswnehTi/Ma+BwxxCLkKmLr1A5/gFyLCgjBWzleg7x5k6ANvXz
XttAgT62Xfw67eFu8YT8bHD6upkA3cCd8iulCgvZW5S3Bbpf5aooUYwcbWqn8rXJGOWKINWYyVWr
YTwxu5CJwZRkZfHrotIum9+bpWlRUUGwOSN4eXkkInhHBApfWaDAIXvVQPweb1GzNeLupPnAGaib
DZzqsd96X5XQvHqyDINjmBnAJHYtA2I5gx1stxDKZT0U6Xps+LrPrgNXXuSy95SFbjbSRyUccfvI
+8dyrvVyhFwxge85cjXSBPmPwHgxiG5bT4mjQdcc72RNSpwRZDG1aHMmdQJsN8uTOhKwhj3gBkzl
welNY0ZQPnmNrMn/glzF3xCEaTcdGnS91m+e/h3cywpGubYwuSMBTbTUU7vxiqtArtKiHr4sUUEr
s++2WDkdPWsjfYw7Pq8PWv47ztixm4ECYpUppkGeU5k0qcF5R6puURM9z+wVWOGV80Twr8TW9ear
CW29kprt9n51GWgLJKn5mce2bGY/Ebr3zpx9b8gmyFWV2UzNAqTgH2nWrF46Cl9WiEJfmVAlFT/B
Ootjvr0+jIBAQOX3b33zpqP4yQNOl8ilqnkDptZ/ri3Cr0rI3U1zMuSOS5sNqHe5bfZ5vgQliy0V
tFgrXfh3ClihOIyVaWgF5JWmZG4sZKSpzEopyn+GEZGexMbhmhO5orrF0hhRzO88QTb1NWG3MqrR
a9xViBAOjebkcDZR7njJj4Y3YegEF8sEpu6oIcSgqqL8+qAta99QNJfB50PDuGeurygMZChmZuv/
COydhNlATvR66Fb79iDue5ecum9XjEzqERwnxBDc6JIwNOW1HXJm+FWaAGAV51/pIKuNF+3lNrq1
0tEqrzW1+Nf1CVrRMHAHNd85GbYG9YwGkSLa3v60l9wToS36/wY++dnbjC8vfn/23TBM2wROyaqC
DWOZD6Xoo/d1gjWNJN3j2O68AKEnqwxM9sambNFRag9kbrDlb9mRPlcIXLSJHmlqGKTiHOfu6SeZ
DzTOpPVfC+MwrlA06sdTjD4fRJBBkFqunSAMjN6pexrfzyo1bRTbjQ2ptBJJWU+sPIHu3CK0qekr
kD9KkBXgHHlq6EWlB2bXp0+RKDqe7b1xgsLitVYrUBz0KImABYPhEwv+ePYNhys0bgVVfP1O/+4W
ZDvkb7KiivBJYhDaB3WfkmQ5CW91d86n4eZ2wIgbi9Vrf6FbRQU/BygB1yQdsXsY9m3kwtS2adxx
9wezm/i96VZd0I89owRcFcM13my5o0B9QkrNtTzbVI/NDE5Z+4H8G2I54+aFz0jmUWiheKAAtw7Q
7CjwjTcezFY9yfxtwaSivMzkr1VbjGFktag245EWQCIysIXF+elPneaEZjccyGOwpwe53J1LQWoO
jMXz97MgUGmSj6yvKE189rZpAbwOPjnK6y7ft3qUj5hyxTbwhEn1YZrL2ys8mfeMNrykJ1k9Ui4f
/jOpbJ5uIefBsLM+lHR5/16g2qiF25VO2BctSYLEyzTjREs4KxKv5lio0/iDh3pEI38PFjSvZQjw
RFBzeANjO4TpruPQ6E1GPBMAvo1N4GvRGXfwEhTM9bTkNYtEaWhHgShCDik0OHpfbQwUf0t3dgL/
7fwj4yLkE7/+JibodHSSzP5DGvhYmlt8VQe3izk0zF/YKYGmHFBAnwqagVTmFjJ5u1GVbx5sbcca
0OQ/U7Gt1Bg7wWb9xQfJG9XYEhXbCpMQ20GqFaVNICerw5c+WPtdHHXeMS6T4xVpoJpqe0/Tkhia
m1R2AC6mz99VDZqftUM0PAf3JDuwHebBrFKjeTbFNshDgG0ErwgPPQn2RS3ryDVDZjFeDqb7qjDf
dyhdb3lx5nvfk7ciVWo2KULEKOAO1C1mMb6Ds+J4eyfeeTCSIAenOGB+BJDKi4im1s9ncQAqpCs3
H87R8nhE93ZALg5ss5ZkBl3mMkuzdO8k8TKMt6bERrAXwIu+vkHoJXCM8RZKm6T5XDtu9ohgmso5
z6jIHKs2QC4CexyBjfOrsthNpwQr03x2OnaL5VvxI78OScjhh8lphXHZsiNKvIgHEJLpA8fZeCHW
HLvKkUkOk0XzBbXEseK0MVQTy+YJQxqUpYz1eXI9mkg8ZvCdgGMBA4ozr8NBLtcazCiXZFvXXhMq
j9BiGKZe+GzXWvhcapMlvVk1kNzUZFWuqIQ1TsRhWLquRfYUR8gwJkHrsrYngoOhgyR/hHb1/Eim
ZXaKBJUuWk6silG1VJ24iDvFrmt6Z1I1vXoAv7GftsTK62mcOw1s1ZDpAZZiPTsmfFrdzTLk677H
w5lZdyeY616qnTXDXUj4ANuZXkL+f6DgAZmGI/aHgwNVYhcfYW80Lrjit1QfWtrG+yEqLq6/z2+F
IGWpUl7AYSudtxWQUGw45ET4/W4EOlTgTBmPK1i5KeCB0byjmRDcQHzDX5KzmRTfd04EdkFK2MMJ
rjd5ApghXTB1gA5+F0a0Hek7XtNw+0LMTQ1dTZA8yLxH+qq1T+co34hKcJ7O2opaHaMp5Bn3AmqE
KK/1sxL3CZ5Cn0Q+khwwuFchklYItbYJyoT9uHWeCMmmDlTRhLEArplztLy+MDtdKbR3b/Lr81eB
hkorJ9/Zc/Bcl2kLkbNWokpZbohmbkJ/5thvlIGP6An+eYiy9ZIhx5E/37pg2VFW5Jw7xSWlu5gm
SNvMm8ehkMJF91s+G2gh7ei/TpKLuaOOP8koStqPi/5TmdkOkRYZYj/P7uVSMDXkg8DPOfOextGj
Ktzd01b0BfA5zvf4sPh1yjJR3E6oZkbMKMrBjAjwzOBwcPMkzgYCmvZUAp6M8yUEjQr5tyoWcSoQ
Yf2D8pUVv79QUULyK68XWdrONq3AuBh8nPNPj39rznn1CSwgSmm+uSahYrA7misdrzRBz7FkmnWg
eJz90eYmjdH5UAda/bF4zB8/RV36V8GWAfqeG8K8woOq1R/8DlnXa4lPtVPCh9uKVlo+bH3ZD13N
ohro22CiJbtZ0didO3O1NVLLc6J8vN80AzLb6pktSjB9Sh/mS00oX6WKlFw8H+/UELAwr+1OXMtU
gq5upN7u61ZC/bcf/HHmyH6OW2qg391aTIq+JCrwq4zHysZz8BBuykUooCQAVKQRt2Q+87QUbjnO
rA5L9s6M+wvrln7OVMyMn2K7FJtAqhyFhrp+6SQXHX/1LbElN/HdAm8gS1fAx2TIQO22Ac+GXy11
hp7rnRHUsJ/gXGBxSdr5A7j2KjU4Lc5IwrNFjzB0v/xt1RHfQPnU0xKvz5+r74J25RpFXDgd0P5m
vR4v1QKbamwKjuEalnf0eOsdWFCepOi8pUQjtBEp/CUZ2w/cGgJrBAZX6AqEAH7DgivDww+7yJ21
SFnsONJZarAU7bTcBwY/LhsuPLervRvrfCuU/1FfqMTU15EXSJV1pqrgWDZBtP75yuYmckq2o9k9
JmKmMv/A4wgCEg7medtitYF8vzjklIz0bCxU3/5VqFWEnP+UrNij/FaEgQ4IGgRrDhT6U6FX7khG
mkgbb8BSVujci13iZougiS5J93ujSJBEsE0nAwd5e3rmx7+tRM4qIskLSiT0Rvl9I4MX14xTIdtS
rg+fABmyesls4xnTMdL8Yv3Fx3t1hffwqOBjrUKxGHSC4BiXOVpngKy0Q+oH/wgUKa4R2seVtw80
maAFzQ20Lq/ZMZj6APgw6+gqMM5cl+p5bOAvY//VhRa777/8m8zVPv3wPTjCU5tLRgMmkfYOz40F
m3tUQvWtd/JFcxDCoHPJ9eREA1xC7s2TfMAlsa9t9ZjBUdBV8zoahcc1Y9w3QQNA9hGt3XIkB/2L
dtUAaEWvZepcCdSL/Dto6OqDC8gVEbmFm8d3Id+rlExRTdPBpgo8AvNuevLAceg+9i1EaVO6+U7P
MkXHp9S3LZsUtUKIrsWhWbE7q+87NNGd0/GshQRqqVl9vkASgmwiJelg3iVCy/159Y8fjOJbZB+y
7Ms5MYowz+MZNUazO+wxwlg8+rbco4xXrf7BW2k2N6isVN6yVdez+98aMxeQGSGkJHftH8jft1Oz
BKtOqZZCKFpULDx1EFw/ruXnYhMTdfZ8rC6aZ21fgw0xYe+RgFIbs0NjV8zP0/k3AZjSHjan89oA
iUUNvXWj8qGtJ7EewQ5SeL6qvyQJSZ+jl6SKL7VGnSkPysRvhp5eSsieCqfK99c1hbkEiYbmV9/l
Bj9u2LzsZapD1ci0/cZ+IFZg5g5M7q/VUJQvGcpr8GAxokiSs2oKo9q6f7tZGAqZbVyp1TuvZu0l
gYkWB8jvcOTnzi1EL9qBtJvyZ51GjOZmSvu1dKXdv3IyQr0itUDvJHbVYlAXNF8evRMq6p2lrDMU
tIVs2cevgBkSbUB84Ks+j0fnPtbkChKCnixRHm0P7kl8neAp21hvkFC4C40EUA3XevVjSHt/eD4y
v3LT3nntrCDlq+9gAM0VY2h7VRPs9xzmZzXxB3oe6orYpjykVXc+8l1Lu2Vy/mY/rrG8vq+ZUqeP
RPmcH2l5iuwifSxKhzyHVnnq56KlVHZ9er0Ktc4Gyzj3skFdQEDdwJJao+1UOOADr5CJW3vfeMmY
lZkRupHziemqnuSkNp1UTfpOirMSAXHMmBdNB7tr9llm29DUIwgRsU7VVao19AtLKwOGbigt4wnV
Tb84pOL1+YIslXT/86yQ9MVc1hjuSFb70QKEI7kiWNAZB7w1CGskd+bRpIS9HM4hEi3JvYs51sjD
4sSZ9GMSHeddv63GTqNxKY6C0KgkNBU52oJJbffC6ADxwqkTPr5IWBirvnIeNjBdauPu6yvtp7Vx
bXm7CJGAAW0BsXCqSyiv6+t5KgD9FPyUn27hnC8nmRkI+uPneAODVitimkQNZQed5uZrfo0leU0K
RxGUy1kP89y9q6lDmbCq5pfQ7wEgWDPvkZxinQkI9RbiSxpwXXFGXpY1xY91Y5LGLrWQZzmhpJ+y
Ndz78MyyhuC2PMui299kJr7hjPuZvT59IqTzAn8sDXEydGnN6NJXz8O3wBJ1oYlrvRX1XEJOl29+
83eUy0fsQezLLU/AjS32VitqH6PAfRO0CMjTWZKqtSBba1RWiULJ4RFOPlOFr1U5y4B5/VaMATCq
oa+nmmkuBI4xJmLxR3FgejWwras8QZmPppTtR1mYjuBq00d8FJ8cFW528Ji5f5XmC//o6qvvomMZ
iUqFxgIO90q6Riv+QAAFc7xEI8vBnQydR2mNh8rewP4lfxyuaDJrR/Oz8EWrSmGNpmbtaE4OYAc8
wjFmRuxYX0LWCLf+v+gV2Gro2y1TALW7xc0boHL2ckVRs+FuxCu3IPQ4rITPRAjOVpzikn32FEKI
OYcUE0O1zOayJxPpRQsdLiaTO6PSFIFs6kqbAZy3qzSSSaokp8bef2vM96DGf1387oDeCzdbTmo7
pyfrBThyDI4wb4poSzOXpfJJJJjJfIZDeYJf8MjJl6Gq2nHP0BxX8PnI1h6o5qqcJ8dUXvgn0lEH
0amPgDSA3axWeScEO1vkiA4Hm1kggJlcSLPvKS4VDUltKj/BMiRUyYUlBZ2TUnUVEtKlwPMd43yb
5Mc07mscTdI7QNzhwnuxpEOyuIolhEhzuiryQSZ8Qri0+w6N6IqM+A6KWbz68uUmDjQ2JRljpxBw
fdHVdzXlJM/gpRnZIYzcU5O2Z8I5AgxB1Ru+LUyF+XbE8Dg2u/ng9SwhN5QCuQ2+/2+DMgnS3mKm
fyAn91CGuIAaHIqDa8Kts3iAY3CJNj3GJ4CWbhkOBptw7kwHLI8Nb4AKTqzT+2GnzpnuaPoMTrpn
5Jb5CwUBi60Kmz2+aMTeNqG8LBtPiDiWjDmzeO75Y9qbwBMxHSimSP3M/C0g62xhuTPWFKou3LsB
i036Rc9KPzyAtcIE2fAFyhbi9cRELMewQW30JeHuMuxKCc4B8d2WIC/luXJt3eu26PR7hkv9LfZp
8qIiMAeMvI/PiwWEoG4qb/dYxLUugyvRRtKb/MvZM9bKhm/H5W2rmcSrqc1sXRpuZ17zHFnhbtoT
BrspSj+XN8VgYZhrRomkQmPs656xgkY5BsY/zRhlcXpt4eQHOATVuPk0eYsH+A2jb7gELqXAYX7L
u41fagg7GMY7+2gr4IETIBGU85ieUGiX5vPQm9DWJ7d46agSUrR3zkmhkLN5a603fxRzgw73ER1X
xh/tszSi6LH2SLalT70N4RIthJIehy7ek9rUNdLWTT3Quo/z+2snm5Q5Ne0D253N5WaPf0D3IvE+
KY0Cemqv7gdzsUBD0cF3SUW4LWf31Ux7O/Ov/KF1xSw3KVi00bldtAIlA0WeLpZKB5MVL06u7UaJ
ZZ6q/emEVq3lWuS4dHJ2oeu13zlxJrZFeajouuWY+nKN2LfxZ3hF18S26CeykzCHFl0ELwIhRi2a
Kg9PXVXRea6954itfOLjGxkfJ5tIDuaIVa3PQpbnRvQbqSweljiLraaUVNsXZVpagBpmXrsAgNkX
nPmjpPv9fsjgK5HmBG/IH2HoGtyyaMY0oSkm7DrqYjWdvN5dSSYK6BASR2npO+s+tFtthhe2wwJC
wQQdXe/bWTi9VxxSK5cakWgLBhe3G1VQ5iDPG2EzHD/aDABonG43GtfCU6XEfqqyTRnAericDeHX
r3cCsWJPimnlQGVEivbGN1Lvrfxn9WhkvnF4hwA09qWFmQ2mCbizElFG+eAdA6qC8rgRYmKQrFVM
5WUJUuzIOg6i+v++cANR9hMbn/EpmqptrpRo4UKjA4nG0h6YyfOERcNlqzAZ9v+V7UfSeLtG7WRV
EDRALt24U13fqvkSjXyhLVeSNlJCUj8Hn7usPg/ZAnnB2gv9CU4mEQ9voaElWzfqalMdmbkbzjOk
OIaF57pt4l3u64MRqV217MPRaVAdMupjnglIEgmtqJoXaJQDj5qeHcEN32CKZibfMISr/ccKDdn+
uWAD4Ba090Ek5ra0FuvWoEX5NgjyFcU5EAyTGCmFbmAAonBWFbD9z88B5bcWFFn8olQt+vO4uiPP
8KBaiUePGOVzbP1GG4B7Hqvhvs0QgBbC4NGCPwO1hz7d3Z+Bpf8YSk3szAjvIwyRsvAouI4ijvCA
rxbqbMEn7t2jkrR+YlGu9i8FnVdTjS6X46TDFOd+14N24ciPRamiYBW3qbrNPmE+ZAR2zjivAC8K
+08SotuMbfn6eaGk+BdRXuVZPER0G/HsWLF7gRfPCDHvxl2/Am+Jji3loWFLI4g9Z3Owir2gWeas
xhSXJw6mEWwWjN/A0zQhI/cTa846YdbcMfzK26ch6/YtEgD5qWY8TN6H8JJJfdNUOU1XKLgCXvyL
bhYkVcBnmN93ZlmfsfPVyNHzkLXmWr+3tCekQnzrv62xRPiUi5uXmmpzElbxqGmTPqoj57yJ1O+7
jYA9Iv83E993nPhjm/IEVUtAcAt2u7uvebvqP0MoKYzKMkGJYzzcqp/1u22dfJn1ViXAjdScCjMm
btVZBcHBjwZyG+DVVoVY8/f/XC8EZVYdttn8Un7zHEzu6+O0wkHpm/NggMol8RaMAbHzQ1rDr4fd
xJh+HCZQk4moc+Vv2Ct1ENEh3csMcAhCQrRDbG9pgnDhQdeCbUC8ttna9nzZConSOdj72TxMTcBS
KMJ+XCjUTb+sOPtxY7ARPkXqhlkAXuAgcVlUFh5YKfp5IMRBF2DTPtbC09DyBJwMyL2yRedQRyMM
y02HASVx8U8ZVQJzhRi6ap8SLyjCO4PlDW9CyxGbUlaNY/smnZgm8+axtT2uf7DEy/vkx7dJ12RL
hAmOl/otdg3Y6m+SJQWNvdiBnUBba1wbde7qRA4XHnOlxv1ufl3ap/+YSacNxmUWxBzf65t7zHme
hm819zm0ntuAQ6MN+iieMtEQabBb5n4xcruXfNJDyCGD5SEoFQLjb4+y6FsPvaGpp3B2etSF6uta
3wHZIP9B6Kx7SDgt+g5sf3Ap8Ga1AdY1W83+X3oZOB2MZPG85PeOeu6PVs/QCzVyUTytMRnL5UIN
e+HU4l8VXXQ+qvOnqgGnCr6usF48o87TyAU+PNZTvuT+jx6rYeCu+NmIWJ83UpKA369aI4WvJ0Qo
wy5R7cu/znINVSkDVHVwZ/3FMdT+LCJglKD30HUdnL1JSJXI70E6fWBiZ9WFkCPOBDtGZr5ygJpZ
XwrgSEdmRuSbWwdfubWFD9k80xSmMIwNvku5eGcIviKpdvIBkLCfgtbsJeffxwwbx+ftG6bjy508
YhbfakIaCjzM6m3YVSu3uzg7HMrkvUGaWMV6jxuaS5fZshete+9v/NIjfqvpeBpCDVXG4ibD8357
09Wduv6wXIswH3qLPFaLGA9u12kdhCXhYVwu2f38qu780LDLzMW7gdJFtPza+3SPV0YCasLpliHA
j1WKtvEdcN5LgOQr+NXBE/nRGC78mZxCq0MgVwJ9BW17BH/P/Q9wiTqySBdRRRc5qY0lcl1IKF6d
4JXmC0szI+pS/XHiEa039WQIwtnno39mHEEUq2xOZnn+mzQoCATrwWCxBX4aEaKUS+alii0nr0FE
f+Zvj5fxdn9E2PvGSyvqtXuFhoW6UOlylvnUZzk1D7pxykCm3Ez+3sMZbHiiWBvfPyCBmbUG4ycS
hE5AM4XJ/tz3sN+e7tehOCWE16+XFwV8e4ZvYdrQgI0usMFdKCNSUPAGIuFTVEAgTlGH0R8eLY4A
FLbd4NXBXVk12L1aCnYmnanbuAHKVlIt8AUcmhsfWTXZwh5Fwsya9GDpISROkGug0tyc1wmo08Mj
57KT1PxuQgxE/4miYSNbUQaBXXNeAyMYeK2h/HuBXb/oF+72wLMVhvJUjfN6YaYvor575qyeQjJq
CdIctjH7ej/2BLPjtgfl3Ho+bMMwudAcM1awgojKKQb/0rLAGkZLZzfKtonVeGUK7gtSLyBy6WGy
Kj7tnPczPWvgxrJygvCkquA1qaqHt1FwYt9bQS9jaRYo1C8dJcbGfUUF04nObGFAZfYLY+hmuuBd
cgm5Bz6upntHV4rJeKoL/GgepQw0zA/7s+wH1JZSebM4yYq74CnrPHB3ku1GE5cs1QjKxOELH4St
dz3I2Um6PfttdjZQm4YmcUHB2A9tltKYPGbwtwDI1kb26vBqffO5KqP/SEfK5GqF3xu18z6WKmQo
Kg7fUPJmmohK63jyU46I8fMWDro2BAQEqnEsImigw5v9Nqle8K/rJjkoqCSeT/Nn3YUe2YNfa+z+
V1M7KkZwYiS1U013T1ohf/1PoI2F2TP6M0ql/zNrrvyl8bviIMlHH6meliNAzc9jEsswVto7fx7t
Bt/97Toaw5hm9UpUlkH/kqeOolGsaUbSlsx72+/D0ErWtFzi/qraxYGhjUyfPk+SqctubrCHNvA0
j+CJsJYCFK5a33RuYkS7Ywj7Hpi17jxegT0DWDmS3xD5xuEYaUBxpVMkIA+xewbIw0yZudXw5Q8X
yBcpy5kE7gTb3e3gYURuY72QVyttBWkAaPh6bK5BCdgnfy8VmLJFob9w8RygbfNPvdtX2A/jVfMy
Fc7GmgKTj6OUe5I+criBH7G+wa1o9BqhpsscOPzD67L04165TQ2dOdiLIC6ka8c6M/ymrylmzOgP
rGNI8gp1yO+9IE0JXRkat5iQd6gU3s/7Uix8WgniiXn835dMFkMkYWsIbW3JcJ8Lr8TS4Ymi+isc
erW0tjpPfb011tOhDKF7g9Ik7gOY/Ak1K/06FaYLjhcdx5wQAMPlGgsLLSYKk4k2WcutJks38/Mn
scR/aFZhPmfdf3tzSCQ3nEwk0E/COEF0gu89zMv/Y2aND0y5qTmB3MbtdsSYj/ydImt1CsiPMrQa
7mCzwilxAiwpyyjVhm89Es4cFYyaJBjHYPVMypFPCo6SnJ9LOrY1N89Xv8sP1s/0Pg9M/BmYtB11
VbhAP9dWrB44EJiDjnUoRfTv4h3dAOuSlszJ96xrthuqo5dV6hyx9xxtouG9zcP+gNrmSmi5KcIC
fY5ipEfjZyCZGeH+Au2TAynnCnqG0cQYNB3FpRp/oada/uiYkOIpwWO/pV7IMNc4tMgGpI/mJ5Vl
c3kiRDXLDIe21SPtvXTUNJw3k3meTvcXGTTzG9bFADgIRoAY8pVEBb7oEtOwWXaXAK/+V6NEZLii
SvTWI2Z5fFq7Cl9JkvZKdJ87QsXT2wv4TGSHzIULQe98z+XqILeL+ZeVHaFX1k9Qx9cgQrodlAUL
3vY6L6Z77qYAbsJfBVUuQCRBqJohkn3vfxt+ZKe9Ffu3cEq2gRumTCFfNDBUuZCabtDv9qt/ADI+
5dvyZ+NLzqze749/aXKPNwueBbXfwF0yqzR9BbUPksBzvmACY9ut3597BcOlHgumQ1yxBvS8f1Q0
TH42i/bGgjxmp7g3Pvp2rSd1fSrz0EzabqV43k+YTshZol5XWiGnv5Hd7J0Q6rx1MmgNStk/RWAQ
yNbheh8k9rfuts7yW3HfUxqXymMyupJUgxuTkIhxhs9nJMJKWWe8F+GX4ZSHUEeGCga5pmGYYqkM
clXjBT0Kv4+7cnQWXOk8ewDskoiVMV9wvo0MR0yxaCk1HYXxC2TnugaD+cmtMqrMDWxYvORR4SwX
syD5Vk2C97UAJQ2kZeDhlc/tSybko0s1f1+07xzmOjQje6POB1IWZkjyoin7GhmyUCvuhq0bU+7W
iWovQUCmckoOXydFu8y7Cdarr/ZddgY4uFL47NEz7D28Ihedk5zAdTQrqCNzRn4oOFceuDRpfVnZ
xGoO8wiiZ5I8yRaiL0kIU0aB9wXl5i/EMCPefF4Y+SLHBQjD3gxzsZhW5vdqL6Q/Uw6b2J5pdLfe
pXy5BYiPMGBKWOrAvckhGGRRi7Is48S3ZtsNCAWR1RgPDDpV5i7csb0voSWhEm0XGpwThmqWPXQ8
C6RQiBxL2HKI+gJxWpUuQ68EYyxqiNskJEQYmaGquFaxuw4HGwiXgfOQrgnUtZLNtjnUC7Bk72oa
kembPtRZBm2ZpBsUdQ4fIHvRDiNoGGOKrPCMctWQeZs8yi2oRrJlNSRTa+dcWljGxpPuDO8eTMZ0
ER0sFqrCl7AZxpgOeFuzTaeHHeOVYrfINrdbeQutWigsW04WjALtEW7IB2vWoGVQ1eSwpraqGnO1
DuFjK+QmCCruqUAvL/rLArE3VdCxvW2fwsJYZANtouej4TpNQKlg3iINSVP1EvFagxGjWCXMWqZ+
xKeE08YdWLnBcsvBhRGYy0i8ei0KdfcEDiKUVp2AiIsGX0L31CWuCphDJnWHbH07m5sZav5kfJfv
sL2t8WO+2Uu2sS/mMdAqUBsY34bLhQFIJD77PC0QgNWxHE/SE/qap9fHc0EmqFoiXUnS1Ep28edC
bHxeyObINjvm0p2YltwlgAdE8QKJI56rvLNeMTJowduSyOxzf3dGiLCAMAs33d0OfxEs1/gY6kPQ
t+vUBLCvuPoudqXbBWunm4MBNPnK831NV79w7ZKyVYEdROgs+Vo1DPfk3Rt1Ok99iLMhYh3u7jGn
IGlSyTfmiXBYAiWqNC4rs/TCQpc3OiL4cX+ftoegFGjE1OT0oTNlvyNoekeDVEd26rZgv5xJKdP+
R8WJ1gBwy0JBpPSLX64kqKGpgt7SXN6UE8IUsVm9NYxtfUzX52pHkM/Jap7PwTgBBTQYLNoe0IBP
xCp4W/j/YRlMAUOnxRXQAicKEtOa/CfdrmrYOQpwoutVw0ffB4WU7IVAO3JGUcWGEczVIsCRCC8s
B/PuXFRbQY7aqYez7ei154sQ7TcRAXsSzO6QtP2QsWZUuc/PJjOXUIyPnIhmLaRrLJ3SUyGdXsjz
OCJrr39XCIGe8sxpQuhmksPHJxkUUuK7IWzrKQtPxIpuy8z/OhNldDaY6Bfq11YJNveNrrfqVrtR
ESgHEkweRIFa4Rt0gFo58mil2bQuF671Qpnss5izAO+VzHEZAEDnZ4463fT6pt7UrRgdkVntz5Ww
YtkVzfS5M0BzbqSUvDg4UaOApDN/XzoBK5hSltv6GPC349P2MMmFrysj3dPnFdAVV0P70OuTYWTw
cTwO64033SyrAMEPH1d859sXc3edtdIuexVybzRWCGBVE2RLCB/7SwmhoVOPfGnrur94cT2GQuUQ
iklIeG/+YRPIC7twzeFcrOw8Q9F7cn/eXtw0mNKOLb/hK22IVyir+iZ8RUxYNENP1Sr+XEEKMklV
P/tXOFuZ+5S2/GUSXuWg+wFnyPc6mI0pz118Jbm88OA/duitWungxPBV9CeGoA/slKL30c0qELml
jgy3f6wccDZgGwdR9EHOdZsADXF0T5FC2P1zdZEDjqqITtcoZ3JGl22k9OqE1wznH9/qJUH1Hv2Q
9Gq6ksDVeldCVDbSTXBxc4EbXdpLOqHJdLwTXxu3AgUOHKi4LKqLkJyofcXd9ilkv1tVxNMZhl6C
TCZWI9fVuYfD1DBDmCwkVQfRu2tOATnndO5NRoO9G0M4K0KLjQ43pj3sifyynvKYqZkKE7QFlnW1
LBfQqVHoSqnVE7Ah/Q2/LNkMZ4ebs1QwfgGxCpR3bENgfq/zDWEik0OFJI+4jnSzPKE1WD2g3M8y
Ao/Bsd0GiGL4RuVSTyY37EhCBfsB2+W/BHwx3FXhtwGKz0kUrU4ZAXnhuE+7oBfrnhE3vnu6ZZX9
0PjflbCBLYL0mIt8Pg+TZ1czgNW8Xnc6fIirrMAOaA09GfOEZ0mbJW6jmRh1mhuKqHGM8QIpOgFn
YBjCa5VRNUJIJXoPmPRtMuJ5SQyU5oL5zNU9beA0gleNyYfH4GnsKhpOa6wl/VoqjRnCBxQuDtSw
cjUQiXShnZp8L91Jbg2FQ56+IUnmRLCS+siOOkvgP2SZQmYUMtX7nv6AIvOeKAflA3k5IP5S3Gv4
hO6t6xxZCUfOx2M30UgFuCQUff2hwJxt4A5+ROCNyEbal0/ppfgBE3a7ws7c4ad2YQze+Nw8xhaa
zbT0PQKro6H35YcAHlEZNVaqmRD9foZvqa2mtRqBLVhRnzvS7oMTv/6Fuiu8dFV2jUMRu3uxQbv0
NlM4n58igJ2OwQyHUZ2R+1T+we9hsjrz96gwFteLXefn/UH2/LObvobzgmYy+gHg9pKI+4AhtxcI
Aexm85KbOPf761WWz4Q9GlIZLwRM84+mRWKBEbNGSdVlDtKKWZxCP95xJkIsGiwSmMAbTxnjz1+M
d/j7J1G/w+icThIjmTUfS8yBWQKnRh0MryGkS5t5/LDkr7kKumFCYUBTOLumeXHkJysgig4pVsJj
p8fHIrRr37r8PQh0BGCCIM3qZLTWtwjM/TEfMyuZtXVJc2PTZjU1wbR0rUNgd95tSx8AYXoR0wSr
3lnE7EnjmWvQA13yqR164UBx/G2RcRv/1g1oyn7YhBsoZKKeZ8ELfktsO++Fo/RVuCzQz5mn4nAk
NxbSwJsg7yzj+aQbmPnNvYAOCbEbUEGJ8+tbKsxhE0LD6k8xz7hTgZ5OzJw+THndahutkT7muqOd
QOnL/UDaf3Y4RfYcS1DfgK5GrMTGMIdJiDoV5wWe342IZ+5N98NNPIH0Xe54ynAyLk9vYY8fgaXv
h1FcNJj5AzJp1jQo0O8CqoJWRbk8FGorF19fCmKzKkrmQAs9gZ7o0NpPjm05M9P1ycI2V8LxQrh+
0FBZ9w+dTxuQKpUmUyU6criwJhwhA3nVTZ2v4a+TM5RDn+ma+qDPKK3tuk4+2qN3jj44XEUI2G3G
chMuP43Xh2GY1Pyk4Xt1suOBffmhCAfjSec5tEkHv0GZueRk4kwzvJNB5Bqwo2X4Nltyi+UicImH
zXXwMax65PKRs6nILKYjuI5XRM3qIxxF5E8zOKh4D8bZLwFSTNcjOHDn/EvHZzQqoIk95phrmA6q
egnVk/FjTmLvVU9BA4vIKW6EzpLz/s1/t5LyNDvKAQEC05/7CVk2BtCAAqaGcA1EDYrhWmPfkvsR
r1QpH1PZc7ar583JnjqiQ57VHg17hOjURJr9NdeZbOn6IiSOy1IPveQ4HWz4Ch0xXr6s3LDEQybK
Wyj0jWYgk15PADX2UL6T75H7kfI/HMXazgvw7kLxMOPtgPFcBTTXvWkuRGScT7SkcQ8hiNDnJ5wj
mtQ55wc7PGsNQtPnujqzNtS5ywCGt+x3a80KrToKzi58QpZJIwgZXdPKdIAIXYs4B5Mr1aSVpoVk
wDVLHIiv9iiJlJTZ2Krwb7Pi2FB5KMD2bY/wH9Ewy//fKefahyK8B5WjSJzo6EKCm6FCBTDIz/W6
Yuln9oDjm1M0k76yKNnKXv+pLzXx7mktwtxLCbcsRfbKGN0a9AKCXAxuEp6lvr+qat/MTMnuYNLm
v2wGUIlDowqTFnb2bT1R2/bN3fG/xO4bIaKAcJYK278HRlwTlUjnsl1nSr7ZCF10bb4E3vqnboEq
Cjrl0Bjaw552fy/Uq2VY8u5oNclVgh1JsLg+WmfFyMgInBchOq4F7YYQYKNNEMli4nN9cREevuTz
STHJswqJZQs8GiTvF8lobgnQvPU5ZIXbg7sqtN1niqxgeTvGJAPsexHZtl/m7Z0+gOs5uDmZ8zu+
4elRwg+KSKQmacwkDZ/9caNS13ZvaW0J+3aJlD3qNCRjnG4MdcHuL3Ovq6EvCpao0l68dyM+pAwH
NKDePmVs33i5pyS3RzXsXU3+/v3mYV8wWf/cJz8YAVHPphxxVN6MhLLNfnANuB3IibXiBzjen+wi
7LuiekKYMqLMDL7DBR0UnUCCKoDGdXokPATlAjUACFAc5W/YaHhkiih9YTgf7WRuN7WFARIS13l6
CYIuYteLXkTP5V4TgdnLNXnFQHFRYdF3eQnDWuev3qmuOYhgPVVU4XCpH2X/UizSc9tYct5KgwqI
ASb2dSsNHcMpEsVQdSA5dAWfZVSS9pt8ahzTreapkVk0uYl8sScwScIki7mDR0a02LED6zuE+LTa
bfY88LJL8wJwvvfc/1mD3nGKAYjkue22QIQHvdLWv+emXpVRVmGjgC+Ek9G8QluEV8Oq4ZqcA10g
YLKjh/KZOL6Tc7gXWoKOzayMIDBwFbmb9kx+dsJ6786Qn6rjpkB1WvjC6SPrPfE011BUO2UfZXoK
eh1zAdIlhVy3rbqxPt3ZwMlykl/nFwzaPX4lb9WJDrHMWEQWEnsq9ioJj/dSauQTkznBc+8XMW5b
sC1mbHBJqtoXOv9QDHbGq0LWek6BgpQajToWqikWkWrCelVpqsjiq56MNimF7+3h68zRSHaKy5zS
hKn3XjjUYHLgndPvjUDqf1nAf78kpkPbAzPPi3GHTwQg3bP5QFAFkLMI+50RmcjFmOP1rpxlZCnn
f+iiUMP97ZusohMelI9XTPqQPfFyKfihq9Xfql2UqLBve4UY4wGO5G9R5ng4E5F4B8EfKnqCcWwT
282cbNeUcG7mReZkB21j+3wQ8/mMtIo2f3v71f13ey6TUo+y2gNHPhHDRg/TJF4a9803DuhzBz6U
vo4FvFCyqVA9Q3RjPgAPnbkrs9nLwjPDJTclYOxUVoP07ciM9Htm5dm0F6rNRgPJtwymZo/IJ0fs
ywhd2IRjaWavAYLRV29KpvYzM6nCnn44UBmFWGZu88KX2bm7bibKpTErk5sYbsUGEtsDqJ/hgxuJ
Kd+QhHruC9SuGRjP++lUPrFcFKH2+eiESwc3qcYanAoXOs/Z8Y8E732GLp1JL27bH6sakYxZI8+Q
feANt8oHe3evpxn92Coaq9Sbbrh9grPBrzzAOFXoCI2JCYBYKZYyQeaVxXfaHJtyMeC0l26EmlOm
e8it65XwDd6e179CuZO8tdx3SYnc6287zk8aL+RGWQ+r4HxE49FeeVMeQEqlbK8OKBKIRb/M5k0d
eGw0gQhkPK7d7DcFHkKb13qxc4+2lIRdWjwklxXE+S70WmowgFEq54JZz20B4TqL0guSqTFw9qd6
eDpqKS/ZcZ23vvCKQ/xjBUbd/aoNaP3/Sz6Xx6FGA1gTHq5F09kQCA5izDR2yVeMvOPVSiS8jWDb
hOL/2m8xG5nfFIeyv2eEA2EXiai6g1EE7qTvvq5tVvaJkQAakOutaOFNbt691XtBHAsuSIN/wxVS
jDzh5L7pRigV5fWt6PCdugcIARYGPIe+upCRWGJrzvoIpupuEnxDcigvBNsO/kiBsZs9X4ulNC2W
9a79ady4MEBBXLIU9cBu+kgONvJ30jkx41PPHhyvP+raZUmAA2mAnvZvjtCzIDEQO0XzgPqCwdrn
+4VtQs0pRymvdvYbEIxaqkPjWMfy/h5QkH8xFZVl25fpCAptMVwxRnYvMzx+8S3hlitFBfLq2ZIK
dXUkk5H8eRHxaw+zyWINiX5qQcw/ZhuEl887xpMP70gBp5VusxlzT1A4hyf9coXqUKB5dlTEHKn/
kCT9dFdALc8ppAWnjT+e0EwsN0Hax0g0SJW1iaBY9M2mCP1Uy2MZR5nMnqRlFkxVO+OyRQZrZNpu
4VidRGM1aVpr2PpCSDfbRs6/P0IGpefHNjYmUvz0/ot9NtJUrX8vC/UuGK2BnKc5BfOlltaaxWUO
/X0sa38yMnLVMGFCgqt7xxZf/TkplSRXRKC7w4TQ2CSo81z6p1Lo9bj7RA9Me0bYJJSeLfDOfJPk
dgKqWElIdy5wzY3tkjhgun4ajfOiw6ERzsChUBJsf0I0HhqY3vczzqk2kCBk3kxJXhBrKNd93xly
YSd0Lr7TLXF3AfQB3mb1F1txw8XdJqsit1URpv3o18UD/iBGxa9DjEipD5diTxOEGVIhSlOAsB+D
Ot88E2NZgEau1+fQnDe1WMFyPbsXIl7Qk+bgbEDy32wYMYY3okMV2/Jj1/Xlj8VnctT+BflZZYsa
PiTbW0F7F2HYOLu3jt6jDhBcXWktmwz5p4uUZpVwmps48Y+ZxQwhSlQcOz+lBja+En9xxL5TJGqI
1v+hUAxtUHgdQuX7F+2TQeAj0zcW91d9pPihkfX4s8rkX9YLZ8FKBAhfY78Yx/VTuf5VoUWnk3NR
b0uleXu1UfIAJJpgJG9tYeFP4JQS30hsy0KxLbMrnFeY6KaNYp4lHBJmNaOfrXRt7/EYMswkjWwn
Ugys714ZnHIzcg6UY6BPMbYqbZYd66veXP8NG7c+h3e3HuWuGU4htb/Ry0JVTuA1ifmRYdN6Nc/V
akzlFGG2vHeNnd6C1jmxENsp0y3fNQ1Kf6V27Kh92Rt8cf+Wz4KIdCiDaVqcsGUWorZj02MVhRx+
gp5YTxjNh0561Cnxj0LFBomckV4nNdFpGhoskkUrD+oYjl3T88tefmzVCDmpEtk8nMmORkdN/zJS
/RM7bQewR8z57xIGh15vyBJLhKA2a0nLxzRSxOd/oekEUIVK4PzwuilzQCabYOO06zjodxpClJNz
idv2ePIIUy63QTQ2DKozcXwEOnxmoxPtC9ajXRzg31YteZiBUh1ZhwOEQ4HDbta+IWjjUT/zjT4e
e8kdYWKP5bwxxGG5j2Pa/Ct3yEtF+o2LosbMWUHgkNvIPi9bcMeuyPyzpoR367/0o2/oWZ4cA1iI
BkCWVG5Yg4YNBaOU0Wv44o4Hc1mvcut2JZo/PVXdFrRrzH6jj/u882H1MxPWOlbt3xY6/ZGsthzA
CIKuPRjqPSSHmYXF7LixSEWeKlq1E7f7oxWA5A88Qlomc9yCitRKUIWbjAk8wsdCGe2QC91Gj0li
06v7hWVVHKv59eubxtXABc/jpGiIZQOzZ/RVTHZv242D2ZUpt/W1Rv6mj1OjfMb5cW8kZ7QI+W56
iUbQvusAygoGQFiDmLBouCxLQYvCIRkTeRy+txMpJuzQYYzTUJ5f8LwndDzFtfwh
Mfo=
`protect end_protected
| gpl-3.0 |
1995parham/FPGA-Homework | HW-4/src/p7/d-flipflop.vhd | 1 | 760 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 05-05-2016
-- Module Name: d-flipflop.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity d_flipflop is
port ( clk, reset, preset : in std_logic;
d : in std_logic;
q, qbar : out std_logic);
end entity d_flipflop;
architecture rtl of d_flipflop is
signal b : std_logic;
begin
process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
b <= '0';
elsif preset = '1' then
b <= '1';
else
b <= d;
end if;
end if;
end process;
q <= b;
qbar <= not b;
end architecture;
| gpl-3.0 |
1995parham/FPGA-Homework | HW-1/src/p4-5/p4-5.vhd | 1 | 1063 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 04-03-2016
-- Module Name: p4-5.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity counter is
generic (N : natural := 4);
port (clk : in std_logic;
d : out std_logic_vector(N - 1 downto 0));
end entity counter;
architecture structural of counter is
component t_flipflop is
port( t, clk : in std_logic;
q, q_bar : out std_logic);
end component;
signal C : std_logic_vector(N - 1 downto 0);
signal B : std_logic_vector(N - 1 downto 0) := (others => '0');
for all:t_flipflop use entity work.t_flipflop;
begin
C(0) <= '1';
c0: t_flipflop port map ('1', clk, B(0), open);
cs: for I in 1 to N - 1 generate
C(I) <= C(I - 1) and B(I - 1);
cI: t_flipflop port map (C(I), clk, B(I), open);
end generate;
Bs: for I in 0 to N - 1 generate
d(I) <= B(I);
end generate;
end architecture structural;
| gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/drive_analog_input/_primary.vhd | 3 | 218 | library verilog;
use verilog.vl_types.all;
entity drive_analog_input is
port(
parallel_in : in vl_logic_vector(63 downto 0);
serial_out : out vl_logic
);
end drive_analog_input;
| gpl-3.0 |
1995parham/FPGA-Homework | HW-3/src/p6/p6-3.vhd | 1 | 2172 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 25-04-2016
-- Module Name: p6-3.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity seq_detector_3 is
port (reset, clk, w : in std_logic
z : out std_logic);
end entity;
architecture rtl of seq_detector_3 is
type state is (rst, s_1, s_10, s_11, s_100, s_111)
signal current_state, next_state : state;
begin
process (clk)
begin
if reset = '1' then
current_state <= rst;
elsif clk'event and clk = '1' then
currnet_state <= next_state;
end if;
end process;
process (current_state, w)
begin
if current_state = rst then
if w = '1' then
next_state <= s_1;
else
next_state <= rst;
end if;
elsif currnet_state = s_1 then
if w = '1' then
next_state <= s_11;
else
next_state <= s_10;
end if;
elsif current_state = s_11 then
if w = '1' then
next_state <= s_111;
else
next_state <= s_10;
end if;
elsif current_state = s_10 then
if w = '1' then
next_state <= s_1;
else
next_state <= s_100;
end if;
elsif current_state = s_100 then
if w = '1' then
next_state <= s_1;
else
next_state <= rst;
end if;
elsif current_state = s_111 then
if w = '1' then
next_state <= s_1;
else
next_state <= S_10;
end if;
end if;
end process;
process (current_state, w)
begin
if current_state = rst then
if w = '1' then
z <= '0';
else
z <= '0';
end if;
elsif currnet_state = s_1 then
if w = '1' then
z <= '0';
else
z <= '0';
end if;
elsif current_state = s_11 then
if w = '1' then
z <= '0';
else
z <= '0';
end if;
elsif current_state = s_10 then
if w = '1' then
z <= '0';
else
z <= '0';
end if;
elsif current_state = s_100 then
if w = '1' then
z <= '1';
else
z <= '0';
end if;
elsif current_state = s_111 then
if w = '1' then
z <= '1';
else
z <= '0';
end if;
end if;
end process;
end architecture;
| gpl-3.0 |
Project-Bonfire/EHA | RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/AsyncDataRegisterAdapter.vhd | 3 | 3159 | --Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AsyncDataRegisterAdapter is
Generic ( Size : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
-- Data interface
DI : in STD_LOGIC_VECTOR (Size-1 downto 0);
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)
);
end AsyncDataRegisterAdapter;
architecture AsyncDataRegisterAdapter_arch of AsyncDataRegisterAdapter is
signal DI_sync_first, DI_sync: STD_LOGIC_VECTOR (Size-1 downto 0);
signal sreg_do: STD_LOGIC_VECTOR (Size-1 downto 0);
signal sreg_so: STD_LOGIC;
signal sticky_flags, sticky_flags_mux: STD_LOGIC_VECTOR (Size-1 downto 0);
signal flag_mask_strobe: STD_LOGIC;
component SReg is
Generic ( Size : positive := 7);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end component;
begin
sticky_flags_mux <= (sticky_flags or DI_sync) and not sreg_do when flag_mask_strobe = '1' else sticky_flags or DI_sync;
synchronizer_di : process(TCK,RST)
begin
if RST = '1' then
DI_sync_first <= (others => '0');
DI_sync <= (others => '0');
elsif TCK'event and TCK = '1' then
DI_sync_first <= DI;
DI_sync <= DI_sync_first;
end if ;
end process ; -- synchronizer
sticky_flag_update : process(TCK,RST)
begin
if RST = '1' then
sticky_flags <= (others => '0');
elsif TCK'event and TCK = '1' then
sticky_flags <= sticky_flags_mux;
end if ;
end process ;
sticky_flag_update_strobe : process(TCK)
begin
if TCK'event and TCK = '1' then
flag_mask_strobe <= SEL and UE;
end if;
end process;
SO <= sreg_so;
DO <= sreg_do;
shiftreg : SReg
Generic map ( Size => Size)
Port map ( -- Scan Interface scan_client ----------
SI => SI, -- Input Port SI = SI
SO => sreg_so,
SEL => SEL,
----------------------------------------
SE => SE,
CE => CE,
UE => UE,
RST => RST,
TCK => TCK,
DI => sticky_flags,
DO => sreg_do);
end AsyncDataRegisterAdapter_arch; | gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_StratixIV_OrphanedGland/top/ip/pll.vhd | 4 | 14818 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 157 04/27/2011 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 11,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 25000,
intended_device_family => "Stratix IV",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
using_fbmimicbidir_port => "OFF",
width_clock => 10
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "2"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "220.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "40.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "220.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "25000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
-- Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/wr_pf_as.vhd | 9 | 27228 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
oN0wWrBe0rGnQ0ZpmkHwkCAUrYr/Gio1+Il/P3mSrzFjyZ0gie82Yw7x94FIXMRv8N6PeTNfKpl9
5/Y8ky3xhQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
QtY7k/NolrYKkecpqallF9Cek/S8HeKmSLIzCRo85yPnV+ZHMQR9E5Y+AKXGtTh7Df6gTThcfZwA
R93ZUBnlyewMZb5HEDc05neqsbfC0s/c28ug1OUpnHi96wykhCKHOumKaJz8wr0xV4s6RDETZ8yd
UXmKpTZhuOjqrjBiGsc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
riZ2QfK4b8k+oYQG5Wo4CKz973rOyhtOr1QXKv7/MEwziqm1q1Bh7K8LmsmZpGgDmiC1Vq7kcwuL
GAKHc1zF+UiqaZdWtVspPRudCMUAk9r5chQ4g3t/HkeuPFQk0JQ4SrblXFI6EawVP4QBSwV7xIfU
SNsI1cvKQWT3SY0j6uCBrAAjnIOSfngoqkD/hZpdUt4NgzBPU+5/fEVv5WDm95vtARo7Y5nYSMmU
CFW+7UB4Myochkit6sR3a2jh6323qbOc+2quTKLILnX3i8XHRWAJIItphSZePeHdEcPtC+73UcoB
i5dA6qb78DTz8IZw9ODf49EILW6bE8530ur8rA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
aHi1Tov0QXJ8SIa7qtita5zw5uWWuN6+jqNwMOl5sQJgakVugpx4nVipbKv1FYoTZqXWItvyaMT9
F+wPEFY8fNCyZ/RXGISVyoLDhV9sHgItN5siikbg9rLT/PcfcRqYOoHEHGgsORMBVZOc6mbiROdM
EBf9TWw9vhUy5NoUNxU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
VvViFGiowFGbhMhTclPDuxqtUkmDgZ9whgNHH1GYsHcvA24QEza8DQiK18eTyIQVFiJRJq9b17NK
inScoEaVuWgNeAMTC25Zuwc3InUAYhwML3+VVLWNFC/k8c1X60CTf8DMTZFw291WiJGuamyFgZ/N
M1V20OCudXHsN6N+kq3bFwmpfHc2d9ok62B8VR8uW+WowbykU+M2c08oSeuQTjmp1pSfey6cVfFo
IKk+Ys2VTIXmwDu0YzL540hrtZhDaZJRHMrsYYpzPJ7ZZtIk0q2hrT12eV6SXSvD2SC+qhE1P6gk
FsqiK+wmcMf9EqbM3VYRRcfEHk60hIi1xkI6mg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18416)
`protect data_block
0HQMWTEyLV96RaDLAzvOq/1tYciRlXv5dszj0ULUAfBJh79wmw2uTq/LAEo9QQVsOqhYY3cSJcRl
/MScS69oftC6aeZkJVV2GOOios+8MgBnSTnGLB9h2mneDEHM7kQSkP6sdtntY+I5IE/VfGzTMhd4
rLLCfHRUE5RXyCLxfosu/xJCG6AM0s0x1X3mDWJvg6eDQlP4Iba+xHk8KGYBObC9hkYSytBLEyK/
gwA/e9Rr/uDI8BCg6Q1hgzT2OIM9BpnACsAOB51DKgn2KmBzkNW7rvs4Z7Xwrt0o4KuS9kkkOCva
L4g+uUIps0hlqB+YhfCYH8Cbrx/YjtajYgmVgqrM4RIB7x32mykcSamQwdERu1nnnwdivGEDhpG4
g1VTx2obALnvGlrwApesBdE4oWKPCD+kDYS4NvKfswAfenVfq2hzOZLHolNnZKYkuE2oF1vGwEkA
LVl1AXaM+oYXqBjNk/MYLJ8S/qNpyM9uN/kSl6ls2hZCFTM8eAI8JaVRsH9QCCPMdq75anbH5KFK
DehwnLw+iuiKU2YaAOT45aDC6KHFMEXKuqbhy2ErAD9GDFJeQdv07N6OLDhe+KG1k64+gajSCQqB
oZ5rs80kphBgBN2CRFH5hYQqTuLG68v33gJhoAf8eL0XruoHUZTu4w6EHDqjQd4CpnLVLrlpNTQN
JqyKQT1HzOd8e0UBhoNiLd6b0LtHepEZaM822Ghwt4tDzLaMVpOWt/tJGJjOPElfjZ0I05MIOzLL
ORmCaCYYb8+T+iPCGJ4au/VunFCzXmqO/qUY3jAeV1RcZTUw+nvneEYRLs9fRoum94btm/I0VhAB
3tVbL+g+e2mZGjLgbWJ6BzyrI7JogGIpaPpUeBIBc9ARWMscsOsseT89v2tKCnj2V4s7carXg6jN
s5CNjS0zMNFALWJR/FJuDfA/qn65Hr1H3uhMqg6D6q/s9YAgq6yrm9nMx9Ks0hdGUn2iBBAgQ+bk
21yNhGA1EoOyJlEc6zPLxKuW3OaVYFGUm2mXInwvKio+g0kghiE7kOsiuu/nebpP0lVkoFAOlCIK
sPApXreGy3cjSbOWQ1t+eEH5wBO47822gH9MYUOAEESERV6Ei6McuKc1G5tsUh6EKUHaK8G+mAuW
DcH+r/eCdo0SRQFHzOg/bpqiuQIMVJYOC24S/neGOsIJ8y+jeKEBTFVaONqVnHhgQzHjwlv1xqCs
ZBn3C+NyVNF1YtYGuzLqD9Up+apI8LsyxIz16sQreTWT3Kp14Gpo/QJH0i5z0FhA541g1cPmHpuu
KAR6MH3O/Ck96+eORXnZ5oDJU2w7j47T5gdfIkIo9o1Pc5Di7s0bmWEvSoMkTpYvx7Nsjn5JQfiN
hZJZYW9FAwAYmKcTgYmvqaWKxurl0khq7ZEOvkr/PFyMOkHsOm6p/NHMe2BRcDtiFC56cI4z3MkJ
eHxmXGTVL8vxNbaKoFALXfKw0BZJBI5HwtYNvvTXrKDeh9Hzmdmw9p/qr7fQvORkZH28WkNZOd/z
/4hN452QUz6KbH55Z54sRZX2Ah4+unPMGJ54ZwyUVbnRaA33A8AYiwuwtX8CivEaxcLi40Xw1bhg
v9IiI//Tf95KYsZqA9hp2YTRvJ3SqZLe4rZy8tlzMo9LiuaLqgnmiA8D6Jln8umtopK3qQvFuD7m
KTzAdVWNE2Kv0c7fGFqZzhKRbaQFpEMtNGBSeGefFEBwS6F+D70mNDzDUfrGbtYeQS03LisSrr18
lkGnFAtGKqUfTlt7IyoEDhkgDmTKn9NBkm3j5GaOzlJhA5AwLbuqME9qUWmPdveQNBkJES6kWn1S
rYw5TbxrluLbwCQPPuq/gsFwdCBkYVXC7Ou3IQj74dMbyD3KmX61W7RLaVyZxBQiSfkO1zM4hDko
6wY/9Z5PMW5aNqMA6GRzp/DI/15+9XTLsOuwxAvBIrhCd40zkK+68iXo8d2ReTWYdJrzlNjS+v+z
GkRMuyN4IrvU2p/7OblZWyA/p9pBxcpADBqXOv/7fO3tUDjNCRtl/Fw6zdQTeFkxMP8VH5B0x0Fd
WVUOTxp+EBVYoF6fyEVCTUSFxzSJGp+ROTrDAa2PqUY2k8AexAI03UGroHx6NsYQoZosHxtolAyN
EsTxwTf5ST6dlUN8qK2DMT4LcjxyiCmEkVnBs78DRuDKIEVsnymb3YwYbg3k8SwfruyBeD2Cx4Ai
+86JdMNLOmYMrn/Gm3zLuzRHU5DZYDcOw4G1bPBhoWKj1OuQ1S1luNgRXQ8lH6xc8nqPRy7txr/N
F2jetEuVZlkl6vE5vBpe+RoMRs19R5ZVAiANqbaLaDqTkeXzTpkvTcRAah95cD7it1kVb40VMB6r
8ZbudbP5buwHjawcg5SkjcagOrniMZeEE+rIGJaE4lsecGSHIvyaraWlCo0r8FZwPFTDEw/6oe2G
S9/bF6B8NmVTOEyO3SDgqQuc3LyUkA2QQ84CjjkIVLcnzE4ccTDWDE7cytMoVg3gpECWRAIronwJ
AM8xLk+dti3b/Fl+WZIztXjv2ZPaZcXvX6dFAJpUIGlbYRs7Y1xKbNFkkMB2suoctz6bFU4ABwz9
en5k7dbjXe+P8/ZSBh+iG3RWJin4IWVBP0wI162fDcW/Nn5+11s7L5mBaUpKGaUsBRWr2eV8yJaT
4Q1qrKH1B6rCId8KBdgGAjoHWZRn16mL8b9N+r/OyJfshFAPn+ikwEl5lEH321z3GwwrFxkEXFm3
x9VHrx4Ef83+5EvMRbd97YPX2dDhbrCZJfqm9VPcnICWVLYuNy9YkXhs1RJUYymH6Tb6ENzHvqz3
clm9gJX2ct/EuX4cHBzArWcSo3LZCRrHuOj+osF8pXUCCIwISB1YVSWfMy06wzKqQruXlKSQfOOU
8SyuRu9ebdmlBh2U75DAf1cdN/AskP9Z+lBZ2vY/ra4ql1z8iMG1pX0ABh9uNo/JqYZDeivCIbhU
jf4SeCyq7wypwq69BwTQPLTrx3SeHn6POfgwFcx8t4FjEmUvkHcgS9ucs/CgkumQFiKwYIehLgm4
uD3b/K9lkUdd7rsRDhZ8hKWihlihDjbJW+fTAffsS/kybH1zZm3nNHX6aBJXjVM2PhMuoThkamNq
alkcn8U4AnhiUWlI/UopkpZsgxypGJJWgCkvCfPmsrBg/b+48tylvvm3A3VZPtARgrh2h74w12N4
1szDXzKrKcKshjz4AFztNEfIvDr8AJTI0Z5lyDmiIr3mVPBZagnaspQRUaE/dBf2LJey8Q+/wDM7
jbDYwST2dhJuTl/2zLG8/XubXAhezxZpxtP7GWUMNBU3OFudx5Oy/zSpwjyWzaCG7DF0ZSYBzdby
SkAKhFfp9zCWlvt2YNbCRQ4+tMEGvNWK2TROBr08pzamqlB5SEdRD/lfTLiV/A7w9zx4Exm2nTHe
4/XMb2MZqeUXN0dDYv2KSBsc01IfYn0xfB9e2SK2p5zJWYFo0C7aaCO5UPPJ8XeZc4QgK5l5XA/k
mKoXYRc0xCCni1RZljGejQQHYLIznyIeLVUIcWn/qIGVNMfVCI7Qto6N86SwKDYesIBRUZBdP7Oe
9lFxmts4UWjtr5fH5bohWugfhSWYoFoWT7/aR/jhV/HdFmK+RgyxsNHvjEbl2prZ6CHC5nZlMcGh
lscikgNLSJqGVQ9iv96qGlNlRJJXQ4puJ3yZ+hmh9Hb5t/VPWgtCg+TUh+OHUWcnSodwDhMLXhbA
a95WzZ0Z/MjS1r6R5dLPH9A2FqAnJ0xyrVrdawhCKq0XGboevt3jecR15eCUko2IcRJMmMdGmajt
cw081PYBvt9yoiL9Xd4SQ3sBOsA0WlnZhiA24enlvStF3bHUq4pl98UZp+sVODqBg4p5Duwaulpv
i43xfnXfZtoMoxAfkc3wbnAeMdaqRiZ2ZVy820vCiNOIwgnCNiOgiVefUVBPe9cKibBDnDrLkE7p
f8E577qCuLkpQbnuUEXwazPLhpAURXySjaSSyI6v97qLAi55wJkWRoRZ4E8UsZQ0zK2z3Upeyexc
5bj74lOBbg0pLfDXDJ8mvlwyd2UYCy52Ed513/X/i1chgq1XbpFRrG265cNd2m+zerVdBZEnMZym
yAHcL4AYAEJRn/hJ3npgKM3pPvWOjgVFvSnDhRC9P8gc48TJP2iPZOY5B2B4iydOMOvWI/rPpr+d
nXODXa8pRDjB88uwyKsPDkANd6c7NU36n5DgC9rdluDvhohBbhNGjAO/QJQ15xuJAAXsk084NOpP
hI2MVMyFwvFUh3dO69ByABNT4yJqMESTIODVVxj0gwRwibtDVxQMUTSzfN94A5ykVddNiyp0VFZd
eRfqWW5xXAnpfRORVElCJ4zuHeGbU6XePCkRVcOKmcq+WaNgl0gx0R4+Is+aWIdTwC9m+pxvcVXb
QpYlJdqdZ0fMZFW3ep+SG8Ha3aj5yFuoN3OMtjRCZ8CwOqJTfDhTpJq9AMIwXBUC7ZysPPOPgPts
OYfOHnlrBBESHCCFukkQHwFS3wRlovEBG9/AeLQxN+SdOdNeQFL8Hn7W3QC86QWNnybW2/GrQpgc
rtjUli9Yy58r4oGyBH2DTebbLFRXDr58c31dxNY1JzUvBh4Vm8C3w7BV886ICnv5ybovF0i+AekY
cnf+nNJp5x8BYMjED6lvZPAr4w9xX2trYL07+HFSfL3CsuxUOIHlJIeVDWKISSAjzBLHAawJWb/3
2U6jXpYH0QdwLKyZkgq7SWRc6UwLYml5RKawhZ0L07J5PosiBfeOgyTbmjGuyA6vDMX+JeUHWeur
fwQ/fuLlwZ2ILgp0lLuwTj50P5+sMURCEX/RKwJAHaCwLif4VPIAC0vAFtSKmjVGobTO4g+495TF
Hxoh/fRui+MGCyltDGOMfI+5Ew8yOEX8jwR7wFYS3pKZ51i6M0Y2T8Q0ogfvaS6Y5D0Ct+c4oZZD
+Qod8L/1BZ3fKUGZcu0wa1n876rMls40VgSg83H17IhTGGtED71Sfjem1vcub6AWXrY6Agsw5rci
AkFy6ZmJIKXFk4qPuggznSuW5ke4L0p4QuRoZktt91ypGCMf2j5UMFTpSAZXAhRXak0NYglc/Ot0
oJyvkTvXacMwPzdSpl6J6lJ14Urcaa9VjtxPxjcXzv71Rr/w+vyx8Mus7+c5yvN2kRSh9T/M7l4X
VMME/s6spYT25luigTihBC1HQUlt0MKa6KeIoXsvHyAhorbqgb8Nnq2zd2V2I605Fnr0MNk3FOSj
QrOVfm2uJVUgLu2i+fTL7+7gt1CXjs0641QgVk7vw7a75Lyryp/Z4UTEsIb4iAIq1FKJZvR5u81+
DU4neWsDLBo+1clXJ3yart2Ilsfa7MARFrugtUc5ES1ujP6Mk3ap9znR6+9bxzXHRJBYJ1Y26OsB
rgRG9YkN/IERsh0ylXY+F6zVPEA7GykaQf971M302uoAjMzkHAr/fmsMhIM0J85f9cJBb2BsEMh1
hC89ifiqRj/Npn26IAhEhhZ6l9ftiMhTlvvP1bUtVpeQ6yumqtE1T84PeY9Qu0Hpwq0mi47t0WNa
izuwlZmmaXCHDh0zJm/BksK93/ogSEacONxDwLW/9UQvVOY+FzcrmGef3l7gbUzfVqrM/8x7Nd3p
IJzGtJtptRD5x8M41pkREH2suiOzNLZeRCv2BHto5lkDOEAl4Cq25guYnHGfFNY2SX0WhzjryXe6
Hopy0j1G4P++asSXe6MWCfXRAYeIARmbFs1BxMIztjJqmI5kMDWQ0Y7XMtr5ICHHPDfHBFVpi9ca
ZBDAx95gxdJScZr1UBsoF46E/bNaxIoHiFnvZowki4hqFJCboHp/4m3x3DP+VCJVKCWDo0rln74e
ZGiRmxkr0LpZDpj5jbOOiWIZjoyZOf49zNNc3STFTiOaxihEYfg6dYneIOmD4B5uoEMRGTPOv+mA
x+VKr6qD9DwXpJaxdp4ac/I0+YofSWkZZmV7F7tGzCdhTf1WXEn3UtDkIuXck6X+vLwclbf0EYga
6FVJ4MhLCo+jfburkVnW52ClWfgIik23L6hxLfeLe+uPoxVDbLUqiIhZ0r3g+MTlZ8+YNZro+iBP
3DOl3tTcLoec0ZUa/ekIFXuT8Ha2KyUO/eBY/iuBweffXGg3u6grEf77ylAjQsvZcwoiNBUSPwIs
d4uK9/Y9BcHc4R3IAc8yyskxVy0VW/wjHMjvQqehXVNxW+LX4qcMyo6YRb0bHDfSG6vfxuB0H2eT
VToyKZ1NSmQRqk+ZBlH2puPNYwbTImx5yDXgIEaUfhSt4zo6VxeKFT2McKIWptg7L4TjCKpluKJ+
sZO1W63CDCxwryZiwkSbRR7uSK7vF1BjTgTVFt4PpwpgFsrdCOFYEgOmAL/meH3BsqG6ofaGQBTm
B1dNVH6z3LgwjXQrvlBMiGtyGa/SQDAfwst1EqIya3DvGwcZ+KtbUnSkCRz1/w6BxoMliV2s9Jv1
AIiT3jGtRo9DLnQjrdhX2iv5uFpZVAAXxOzvNrXbZ108ES7BQq8s1m/gnKU2XSTGdeBVc/SD4low
uLUGPslxUFaJGcLDluGHxYepTtBqxqZbxeSuW1sa5ylbnx7U8vDfQyOy4GXWkLdlseU4Tjb2ng4i
dlrFux9FrZ4soJoise3DnF6DUXjVNOI+YPUa8Nure3s19PC7H3HZEwWVjkCtliS16LyBmKJIaBEQ
EdHljPeatjBYUx+WfQYSBkyjcFwrazXA63Bkxqyhb0+yV6xKHhNX+Zt3miY/oTijdOoSEy+k7T+M
qFpCDVLc9wRqA8yR8merrdz/BLq0JNh7fqiC2RHSMMCrbQyomOInp7pk1EX9idEOZdCr9GvgK8zs
4E3ND24VliwzF8z+4tkTMxMxXtRhhSjsW3Bqpy72r+5NVClzRRowMvv9pWUllH9wal3UcwPPMzSq
YYoyXr4np7rt3QVQro9gEUpDcr/OsK73u5rpY4CJCboVqzXVmLJJV8Jo447+pbUBJZCHIdh12rZ9
3mO4LbqlONneyEO/Z+65auI9NAHwMonQbVf1ggjEg2s22PFR89s5ThKTmD4jEPIE7/j76vv/iCL4
fFzJZ+A6XfTtAqLRwapjS05P02BhR7Y56yr5yrI/o8njcI2YE01D81VksBBB8fLMkwPzmdQohlxg
ghwtlFZv4QvC8Be2v+dlSmqT++xJmgbJCC+xauYBcNhnLCzdfW9npn7zEj8SZ5wqmCEK4FaFkN3C
/9Zbm6vtw4KukBkepYi5NrPugP8wvp3Uln7Oajs0aqvEC71hnz1waSv4/4C5lfAM8XPaESmkW02h
8WEgrSc2ehEYnPXz9/eJZ2f428lycpAgYXCVKpyPBOPqMi4C8lefuuaMPYiKWeuCx8+pFFXKAeG2
b6ClOCp23zHgkRC5TnobupfBA1RAJe2zxney2C6x0vZa8ZsHVoxqmx3fzmTzvkhP2hHiHhyHNHyD
dzoeOchpRpiEkTv8VxfpRXJbXChUDmwHhhojM8nkzigOTbKP/qv3saBTNc230c344ZSSTsvs9pBW
puYLq/Q/OAMAKDDTuOMAjZz0/kAavZSPT3zKfmX6ghR8vFjnTPEJwmnH/5dKoV++xXQagaivZ/RO
kT88JKppH1PSGeOI6Xwe1RlqCLJVyH2z4cO5PTFT3bdkDyt46OihmgOX2KlXDIltoPHbKNUqJbLw
DbW1j5T3FGexvtWbsb5zyGU8b4m44/rv9iniimqok2oKQKEHOxvH1s5qLx5AIRk5qhaE9pEZwkFt
8wMVpBIJzW4LEQ2TAAkLj4ezsuNctLj9YW2mIbUThHFkT+KXBpvd0M7ufPiMHqOr8RQan53izqQ5
pc5BCwf1samcqB9j7PYPFJsd4YYz0jaKo5gG2J1fVeF77GkQg+U4LK81eL6xuoOAukaj7ge45hOP
eZunSKg2qnR5VibQVJBuNLNRENh7VT5tbLlGRQ8rzhqqiGNpfYZB7gJDRju3HmvkgZ16J02Q64ZM
CmBikRj3Kh/0wjXxCX8aFwREe8/xXwOtDSwceuMyb+MkhGIlgOF/ZH0law2LKTTxvo2zppzM/wH7
AQbG6gpWbV9tHKWDTHYMjB7IiSE+ilsHaoSUwZwEkRPrz8odbCmXF9FwX9dB/TX/P9HOtLXrLS2h
35rH+54+7W5MEBQgLrFXNzSefRcXpHGUGuTcmsDocciUy8IILPxUiX2f4/cufKwhDpMExmjO5WHw
BFYbTjS5QkpyOgpkwrT9oczHx5tZbV0IcigkmJjUa/4/hw/7koUM59H8LYBsMYgLREs7DQwp1nOg
QSX7huki53sHpXFA3HoRpg5O3Jjnlb6hZoEENDXU3wI1n89VM7fCnxOq5E8igXhbWorR079kFfmK
3yoeZpMQl28qkRfThHeJzX54VfapVMCHgAy0Tw2c2gtN4O36o5Yd5r6BSwWy08IjR9Vgqw9cVCOg
Mnzj3FvBQ6bjQuCz8bYWq9ZSMR1CNhZfCgT5ARV1bZvCXQeu0XbPG4QUsEN1GdKfiBvFfpmcfhBe
0nrSUkzPKe6RyCIEYLCK7lKFndx3oeoCz76wP6Ma+pGoY9TAhA3CJKANNvaBVFZDKohDvz6AXiQL
mCF9zIZNk/U5XnLnJdtJJdmri6nGQv5ZSnQgKKq9W0ShnuGXOTnCfZ+GjSlIZ1BRgwo1ReGxgPeo
+4xPs+G+PdOj6N1StTzPAsYXiHDmGbujs60PrCTbGwKtfwbdeKSEySqpQX85lvegSimUcBDnHVsn
Rma7GkO2wg0rm17tYfZnMz0pJQezI5PRruPQSOtI5CJ0rIEvX+3RcI2deG51AtXDgqgfXSkyIVIK
/bj+7TqB2OWmxf634QzzQbdU2Q+AuZmdJrngdjjBYKYv/1KmzSXP39JjelmefekH36NgetrHTG0G
3k1SE+hhoKTxWbKZOEAAQlUS2P8EL1eukNcXhbHgeXb8qd7g0BpWppUYiCG8hjcSpsN2fh3KIu1U
8w6IYquWG3r7r3okrZ3vP4Xw42jc58FsOVCfBIdXOpuxwXpwcceiWI9HAexfpvfgWJlZsKEv6Zxv
VZJdoCaUmgK9rTPtc6YPpjhqTF2fQBB1le304phx3Cli71Yp2pInnNyCsOUIZhQEhGODJph0W/Zc
vZ70qZICgAB5BpSfRtJ0E8qOn6JGmphd/VFceyNXcdKgOJKtq5N4FE7nHe5ru4EkjN7nH9SAT6e0
Tzm+1svoIR+krVMNhkzARoLkfTit2IHVk4cxsddWSnO7I3Mmb1XCzoAVvk23UYDf6LBBy3ewSa0R
JpIRYaejLmC0h83xPZzzM1nnMh5vhS/PShtFD49jjbr7BGNcZN7Oe3DU1LMcr7G6NimmDBajNh+A
txxyoTDT0QFfcXuRAX7iVDURKHeQbyxkUy2otrOb+FSHBWUnpXErq+vX+wxywbeOEJLQvzei1+cy
WeeMdrm9F5jUZSthxLQ4P2hmvPTiHVbQp4480NALKSs6ZpmJuk51vLbE3VJ7J/yyoXynrE57hR/h
ebEboYjVMLPwnRuRrfgM2yyBbXO3oI9yP7RpGumfAQxM4SH23NQZB/jpliqQR6eXDHVBmwYNOc7u
SN+1vTB0oFjR39C/NpQjTNrYskYEvB4hSe43XAx2su1thGRXOX0HA3Heg9PTD6HjHTkEpZJRs3Yc
c24XXD0AZ2gKvM2u44TAmiRnIeaoaf+DsalZDCwDkfpSGfbmgEbKrq81lxskcIU8gETKeHNVpxQ0
7iafdJ/e859JOIyVlWoRCLDGygNFstIeqrjN5qfv0QUqdBdk4QU9TZ4VY3dX/n3GcjcnJJfhFvjw
PwZYYBoEISIgIn1PiobvZX6syZvbuDAGMsrYuLsdMW8bnObRvay0lsBNZR+kNfUjcAD59rhIvy/K
wA7iPtLeAPBzefVLyq/x3DXKHPOiAPC5e864EtwqPORAs0XV+Sx5wj48+kZt0xe/u3YLl+Jo/y+/
elSkM4JgsqZpERbSOHBWbflURO38mWa16xlHlZ+wDAf6/wSZm+KN0/xOQK3Kvl/OLZ2bqZmuKsVC
xpeYwQd1wOTX2aNcumUhxt1Hy3nMhX0hoXdXHjaXK3KQfV/7kXnr4h4qORIHoLOEjzODR0RJgrrc
qg0bNnq2FBA/gaEy4qRswx8Mo/Lqeml6ugnvhoyeefsgahucaJU5dcNfCvkSS9MViG0StzCN1vDw
Xsex5Avkhte2gRP6qh19zK5AwSbrZhSdtf4V6GWOUj7BStRc9Q/k2iygkhXUBblKKMKbQE9dA3Uc
XdkLudyq8MHkkKErXYh9Unt0ffOIqs8NBqsPhSagbd4P0boR07sTZrgI4B4HfoptF7XGWBto4fcS
De04J7zsx4dh9HH+1TOoSE+S4t0JGgOiMeDgMWB8U0KPzHCSbWvjQhhDy7XXYcGSJj70G22B9Qln
l7M+NNMpqhio0p9rYwQ1EI6Xbqvjc9sSUXyeSHv5C3ewdS+mnDbgd4YErhEoSva0IDKr97zxrkH7
eh2A2PaudKyAz+Sm06TUQ9MeH/IbwZtWSgeca1ZXAF8Wh+NsSMy/sD+8yrt4G/oXEbXrKNuxPDyX
AKUCMPluHBLUiGzsc2pi1P1lYR+agxxKoYM2e+3vJyGF6LEIWF8YEKYZW8LRJtVjru6C6clVsw41
iVDyVvB2EfnNlB6mMR62r9+ARVTp1v8JBBZFLHXN8qGSYMO3b1NNhI1uAs/F6htUphmSJkhNsWNq
hdGwWsbfwjrNL5KPM/q3mrIyo17UH5Ef37OB+SveRSyWgLqc/ZnPcB1zrvNIqoItfYvymGnBAMX4
lZp8/CtT593uz4+cIjw+reZrD8UeTDlNB4pfUMA686RubfQbw0CIleisFdfh4Rnv1pIO2bH1GK7Q
vbHi0PBPe1dLuvJH2dOWXqwk5anWO+wr8gfqSki0jVYURQlF6EoBqUdngpJGaSm5fNqe7IrG/K3j
x58ObzhFUYK5gErufQGQrsqBPIaAkqWLWQYdZpEevHGAueW4eYSPOaumaMMO1uByrBEmPirV7IH/
KOu5OGc6mKYLrhTchAu+w/gmabh+yN6F52nXduzWw9sIfi5JJnYZYBH5h9sVPSOHigb3x5GTHTDP
YY5vovjRPTQnDGrSe8vvOZQpqvOchH2ZVnCBc1JJBFLjGiu3rySmif6or7X4HsEFBeJGfGWxspO/
m9xbyUQ9/1d1glyTMCzHcEySZdcRSP0aGSdup5lD9Gvo9dkgpo1pivuEupLIkATIUJ6C1mBQ8R7M
dW1kkQ2eU2B1zNqmo5ZILApWsj4dh45gJc99EmqUfFM9Hvr21WyipQtK1eFwwlKVulRFvcWoMJ+g
0kk1t8a4H/nOXPU4s/WlZCoObLPzDfQZD0mTn3SL1uz7GNSRso+RmX44hPjp2xkl5qNvxgQhgR5H
NGbySp1UptwRm3ac/OKC16CwNtfpo/ECVuXMF1f1iYpwpYvs9g81ZE+SsUJCO8hQiG3h+a8LpAMx
jfPesFdJEoXXXcEZRSEClhpU3Bk4y6tVNfFDtb4eFFaeIkfMIXNZEEtDp8i7AqCN2wad714b7LD0
jjtmVR/biExB6YqBZPOKAu5EHteZRmGvOiebEZ4Vcorgoa5aplEDxkDPBlg8hmqs2g4ie4HylfUl
q0UqgoQDGOqUBp/k/eAgaNVTzn8w6bjVebsIBimbWsgVAm89IxB21kUuCwm2IdXHWAckKx/GfIY8
pqjf5flBOWNi7i8HgWfu3NpzWml+pB/Cc8wB6H7ae8naVN52Um2ZWQhd7fUx4RoK20EokJwlQsur
bmY7BPV+9XKEtPd02Acn0VXbjGefSWXfrtDDTRThNCqYnHa/h/Jewt3QCLfYRuGDKgrYuFB5Obnu
bQ3RM6byExP3de5lBGqHs9Wa3Gwa5Uy6OmVPZ6I2UgkYoA/wiNUTjify4P3NZwPVqneJN3oxeESh
sUfaALq1KiefCLA/imPRnfA71SFIiXS3PAJjnGSHf/UDk7Cl04lTTakkA4779BAAFPaqjjnVpHcm
krFINGiAhnYIq3LCeq2Gg02sminrM2BuNUarPqwNY8uIWSSMG+Emj2Deel9GGIbjNiKh51sweSOj
XVymOWcA9VtOlOGwsUQAIPSen9gXj5aKtffq2FdrjdnbzuQRHXaV7Ecs0OpMJwmbsDo7z8vTzRcT
6ll8EfErXvGPR9MlOkQ5rsrUmIKYyxa/Tr7w5IIA27Bn3XHA6vtVIB7b9KUpREfNL0eodlUNPVtL
3nwdX783fQhjJNr2gw6iBQ6SQ8Ry4wWVvCe9lttABGgBSmyHS/0mNXL7+l19Zk/Lsh7O1D1pZ1id
2g+1enExLT8vp3v8xpfu84g4jCHD0fPkpCRccOudLN/LajXLvgv7nuYILpPywn738RkfBiQIQDWy
b30E5QIHdXJ6jSR/wCRH1OM9F31oySU3EdXFTsXvcFXEVXEw5+hWbTv2QNNoGCat+TSrMg4yvlqX
2E1BoGuyshgD/5ehZ4jaEEAIxszIJhF3rxhF5s2POWg0Ml7WuOJMZkY2PC8NlJnp8aHM4pLN0nmy
CSGrWv3cHqq/baMcj7XWTC5Mpxniel2J9bqjskLNOf5Z5RtLA1NJ9Z4BsotzpmxHxWd5JJGSOztq
BqOjz4/cEKsQcCDvVOzjSyTdsOPyEYC1l8qLAXve2tbo09cLkzfXwNzZ5JGmB749BX/Y7ZBAaWNn
IpxWwoLTQ6/sPSHLO8J1Nl4WzGEhGQW5PW9UmCsoKFt7ablNxzsTmboYIHtVQiCNQpPYeefhL2m4
rmCeXhFCDwf6TioCShlqtEjAP2QKC6EC/TVzPQDojF8iX/cQrTljGL6xDPiJDTXbVa178y5tjLTZ
o+9eFsiO8iaZycTei/IVu2j8epl1M7ZtCjDjjnexbeovGJVo+aE/5O2O8JbYnejhnriEjfknhyly
EyO9AsQ0cBtm3vIazJHA1qIX7JPkb0wLNNVkxqF06eMw5YF1VJQE5ZSpU1bQQ5KX5i7jaytVM92u
s1f9keaXxfP5laDUSMxSmtGaGF/CZ7kDWF/DAuCTF+/Texm5YqfaqOMVUisJ/KDpSFQpd6FviTYA
PKP5N/2MJR235qaaI6qFnzbr+AGmTfAMbNMeJkBBLqloaKmIYpaPZFFnu7loI3EOBDgfuedGuT3v
WyvJYnyypIBeqxWteok9VxZI+5tttj2Gexn6B4/GFZ5QmJOP83BjtZRHYbX+w4p5KjGj9nWAkbhQ
QD1ZctsUBSveheXDBtbK7ETVubiHOQYQITEhRVFsDrLpI00WD2gEW9mysoINtbhjX4uBXN/ID8N4
//arAK9wXXsH6c8Dd62VrFTmG03Rx5bNQCoIYmdR/mIbNrYNZtRapWyJlCqmKbTk002fMIX0SqJx
tdXK2ujJ4y3lHLhsYO9d1vM8PmsKTbeOK1y8b41texKt+dL1KHtGK1+uhY2BvMRcTd3oVINVc9rU
/lfem7BtAoc1hLT2WwC6Z6x1L5RnsfXoJTY4Z728xRlMH2HcLJUmqyHZeU/GRsQyxy0c4SuS40b6
wuLMqMKx+Jb0DzVb/C4jGuIiOncf7R/1dcLGoumMj1I1BZiED+Yz5PKGvPYeIVTgT2MzcXW/h7l5
0O0q7WtnZQ9kZ+OxjWkPCugw1RkoWIPsOc6+6Xg8lBtOX9uxuGeyq31SJpO6ziJBHl7ludnsxPg6
yac4BrJcTqxryHcPcussyBCR7SimOphPQwoCoYsz2c8WG0uZgE9xyAOXy1k9HZ3BYDf9/FHKd3Rq
kT4t4HGZK+VlFcuEchVFJy5gVEdM9i+tQOaf4uMlwiY1As+1e3HoeXrPPldrChlgKB3z1iftd/QJ
r1f2hbV3Tn9sdvZZ6lTYO5MXUJhzPaf5UyOpSKWCotiSbZdGu5Lv6cbExDKK8z1L9hdDjiDQ7LZ1
fT1lTQyHBed6xawqp5HFd8i/X0cKzshFQRK5i7BzvCjt/zJa8hioVBl0CXW7CSQqHI9aOhaIAbzO
8ROxWtCLzWLBbriHKYhuTFrM6aUUNdZajuJs4nO5Xg4rrJp3Gc7kzmEcKovWXa8AVUvJZMWEg4oF
Y8i/Gt1k5fId5kthd0u3erJExIm450JPZ4QSkm7UBjkcQLhDv5DbYNEXmm3wS9mNU42xPvhhKNec
yFI3ynl4zwm31sz9zF9dV3QKxWCuKQb/iZpQ4IgqgwfKzrjQDDEVcZO33tjkEvlBc/kVhgJGwKOK
U27HfRkEQQzI0S/y6r/EWMt8DcGGTDu684QlrSPmEAxsXE/OWcVK3cxB+ZC2MQLoSu15ZaLdHlFl
ENuo+rScfSUTuhDhroMyCQgd1XrtzwmSXqHaMZCwsCxfZq+Zc8BWT1TED8Ro6SRdAKtsIuFYU0Vq
zaxzaQgh2TPtLXLnQrXQ4mhYyeYLK6AM+DOzmjt8W/riur+O/yENXTQxVKBey4USEunlegW4aK3C
3TxTYrc4XKg7BgQKkM03GQ5XgN2lR0oyeGkzpVh4G4GYaU+Q2aW1UKTGVO9KxgXXUE06Tl+ce/aQ
vZs0cNwAAkGIl1iDmk3eAwAO6rKdMlyVwXdOQptXSPBQbcnFBefWevodSZd68sIoCW6N6EaswXbz
aKKVW5q7HFJoioDA9u7HndEgcbSw79UkN528nNxY+oRzkQ4EgM2sWnl3gCWvCACVO73yPG/keTLC
GwOqML8r9zKHqp+PUOI7vCE/+NXtHh2dUXWkLJBJ1/S3CWRkt7dO24Gj6T4zOna4AYOBhYYgyA7r
Ih1uSr0cbdIUJfJIIvIwlLBXcMAs/c10od3UzOtUHVW6DfViYP2IcgqWWNJer1Nd9eRVN17JG2lG
yplYmWn8NoZ9bDtlkDDAGuqmkudUza2/ei4tZH1bc5PgJt546FtInYq4pPvh4Wylov31lZhAeaMn
iYfeOHs5fKI3vT34MJr5RH8IaLG57RSBH/ROJgQx/ylMEwqJ64nVrmzqRS+O6ZTXj2a9eyVQepg1
0l0INifw9lhe6WItvMgfTk+Z6b9s8PjkclTDvn/rm7ZFV5ydiPx1nnmsMfRErJMUYaxu4gMj541s
d2+5dKx1P2zYhUasviT7XeygUwakeW8sKbumT+U25ljf9EEneL9MiLoqu1NDz/o8aq2tssyCiP0m
mfSpmx605R08ZlxLpUVVVjFUXYEvWcbsYCZVtHj2ITqICX3j8ilJa2GokE4HA9xE6JLcpz3xxuZ7
LXdRE7yv/N3LTlfwaCs6OT1lXmEa47bEY5PmJ01cM6bPi1Y8v0SOYkOwcnXvvJFbpWW0o8raDG6v
5S0AjngmibcL9NyQvUh72BGsIk4g+9gP4avsR2Q48iNrRJiuI1VmQmpF0x3WwnJ/08u3B6HiiPTb
Q5XKNeBsAZV36F6AZV3mCry6u8k9E7bnAFl5US1zkNGO9+ypCc52vLga1f5bVYbljjZKK6El1H2o
LfEWXucA0o/2mczWZlPWDE0gfUFuzuhi8flp/so/F7iB669VxW31lx+CLMQH1UCCV8HJDoKFKepk
/wk5tLNiyPsR+zpJLVo0OEowSFdGefP/Mu9BFpoQd0FGNPD4hMD2vuP9e4NYdtMBBnkKaC6wR41l
nWAuVP3ph5q9mVyz2krzSIYwP4zfc7TLXdW+HySS1QadN19Q9scqrsrtgxDW2UOT44vQTnmnMpR7
jo9wyuD08kC51c8IlF8z2z9RqLi5SqHJZHoN5UQVyWyXFXszBmUCMY8wL8RcYZOfbDEQImgKC0NK
HUNmuSRzxp1EY0KB+KWug7KsgD5Fm8K0BjHScGdnUHjEqJZDAcyGtuAlOSgR1LZ6eJ00ZKGEUOC/
LdWCggVNtmOm4S+g/5kH6s+cOoYBx3qDMmJz2AaADCH8af/IVWbJeJg3Cv3z/Pe2mVymjo+1NT6c
QF3xaS40SUJ7O8VqPnLhKwqYKWTQcieKEbghC05rQ0XAcQfLUf0jZpQk0HjYvbVsCvLv8aZe2djc
Umh0wJKw2glUP4yLJv52SoEEukSNoIZpCuRMhI1upm/53jLHYrEfRu9bTYgge3C/Lk/lKoIViBfQ
r43mkctbtR5P1n39fKMSJHaNkseg5mgNvj4quXdJCha4834kwbcgfTgnac/2BImF+vVjsXVcp3EX
qe5rRYu838AuWTt1L33w+TphsQamPd7+zuEkDxhEsq4zhMKqK/Sd0p1PW5O2+06Gni+Gx/TZMMgM
6wkEh5t5oIrfCSckA9znQCADYPkD9fBrKfn/v64XL2cs5pkQmW59RPHT+8j+b0VDYTJL89OTgMZS
auKeulxg9bqo00s5I1Ui6fIEv7L23gWMAahnkDH89prDfyPzy4+QcRYsdF0LEEnEVP9MDdGfFbRs
4FtYGxqofxdJeG0jdeEmDEDrmFx2sXlDw55wr6WULoO0gyvf6ac1UjO5s22SsaFAHSVwCtu/kRkK
r592kEHwHVzImOJa4xFcDbjsiDAWcM8dPOMCcBZu84WjlXGx0WGcUS8110gUhbvsVRuNhqBJ880/
YSmcwPmSXD9ooRW1ejPJy6tksnMrg+ERxBL1IyJ8yLrZ8J/kdhbKgksYxVUmxQnsevM1kHsoaD9/
UJXHyCo2v/BRO11wwXu/p9RbQ3OpkGhmHXnv3MSdcZKPqxvvhNZ/gs9llIVl+CWkbiNUYciNZfRr
7Shdb23B64rh2mS5G5q6+/l3u7s2dNVNvATNXv4H6F54aBYXC+Zr1sFsbf57QTfDQqg54sn0+rGy
mXZYguwI04faQAtZtocyAgHqcQ17IAkn12w6wseiVwofzGUQIzzWibim8Buy/k6b2IDMHnuR8WNJ
oQ6fzvVhrS9ErrTvZlNO9jqk4s1HoYGCdobcjoTevLIqWMVz9T8uhHNzb6wR/3VLl+s/tw3Vm5Wj
QY0VxooQuSIP0fb3IOx4haUrSy/PfF0pouXnzAC1IW3mmCmdYgGy2SmpeUzOLlpLerFjFNk9ofUA
oLs0+XygQ8gUGHJblmRGVPSD9Mpd/WXKkSZeP3hQ/L3j9HjrRSZJ5KJvn+0GzoR9yOmmXKLtU352
GMBrH734wpk+qMVXdDPW5p7QWIqCPxWcvy9R/C5V3v60XJzJLYP1K5DrU/mYqf5Rs3DMctDJ2v59
puoENEI7ABUMDp4tS0yl0lbuzxT6xfECcVbZIqcqBwygkm9T2MhFty6HZhx1UvhYUe/TdB/U33P/
JLvQ6uudHBPcQTDFk1VZTHwlgRuh0XMsgqNWW7QmlsmBGumgk8JXiAwqi/gXi0UMyY3My0ZWeVeM
SCHI4Ep/1JS44H7RYnsRowjNbV8PzdJpEdzGsTNYDcMd7IRoc8+TVtaHFXgrhW74qN+9GbswXE6b
3JEgNEGkow/c24a1My10/K3YLTil+pFDrt5kB21CRVPFBI9lIkK8xIvqfIZfFA4vT+vTNgOukorq
Ue3LtQEyxybcfqjkGV/9xXSbceZezKKsJ7rQAPllO90deaKIjaPjZDbB+CbXipZLjHBH4LrsatfJ
UFPw7dZWZaMDcrtckCFpj8UWvUhA+diHyjFI7YJ9g6oLkmwDm/3+0uZ5/bPsnVDrhjz4m7MyugYa
SRuNnrw5CwG6Q5wRrsd/gALwvKRtVvfkuF80Bc2sPibegE5AyqSkzOxBHfpVJoIG3EFEgM5cyWQD
lysvWH2gxmMRecaYYX3Jar+QnokvScM8dOahtLitjEf1QvMhmroNcxGQnJP6rCHf9xNBZq9dKLkG
H0aH78FxMxJNouUqGzaGPl2kLYcuXQGmvMYR1OB3PffO9QOmOTZ+aEcVBa8sS4HG11pff0dhU/Qw
mfFRPGRtdcLz52aFLHPDQLONTL2Mtbsj1hyhi4VyW3Pv1ailyT2UJHlmOFt2tU8/OIsIapB+VMWR
4/6vv9MCsPPnvSrtj3cx/dPjR+ICorBIoA0H28njC2+bGPKHsP/gFMg7xFy2AR4EZrqo3OKeEWRa
3GwNHLG4PzB/CAz9Lq5XvZGX1Rp4BKi6DuRVfBsSfImB5u//R1GjohbWZHaYrpN6pmA8qhAaSXH4
8o/AO/WqkOz/pK7y8bpWNfGX9NfGuMFzLUC5qJtEKjKPXlsE29LAyLg/6h6hzkOFci+zS8HE79GK
2XPei9D6ro+08PyitVXMt8JJ1KnB1EidAr0TTJthAsxNvxNXucySg9QDHn0uhdDXMBLuf5nPYEhI
XbZnesbU8JeQJ7Ze1ywR9L3kgF38xkARM9t2v1wkWglI1Kz6FkdMopb35YoGDbr3GHL/vxgQJavm
CoxJ2uvU1aPgODNaW5Mh0dJXclXXT8TElrXwKs2HbwhfU9+2DD7P27mRSUBt2H/DxMEoCIq0zdEt
EYCpi2Ln3AwXTyMU6GQlwUmUEdUlFBdqmGlByiSfw7QWZMrSAHbQGoJDAvMH1sE19RB/pI/m6mvc
YYwYb0F2d9BT/rugakSBXEo4ezfgDBjaVlJEXAU/S1kHPIJpg4f18d2L1x37LR0A6BKksaghJak0
CV0XrtDpDk4xfm992QUAdyWi3t60fhG3MH5TFlVrIs0zre3C3KE2goHReMqbR1jK5pAniC6J0muY
MqOzlKh2CCaQv69aDkFQcQCkQdWasGan/89uPpJcF9e9GGk2l/Dxso8v3RILgsmHDQl1gpkKpR8E
YNd7AoxKgS4VNqihcH4sbcqGLrzkLSUtQu9OHdfHEx/HpupgjQGYlc+ISXUtvJFeQdUqBN0o0JpI
Mr9K9a6GxH2ZqSu0mpTbbxmAkF3r1jC7F7wi1klLpAdo73nUz7SinTUgnxpF/CeBytpsrXs9DcNm
5PSRDYJXM2n8jDvbU0W7c54jabarivqAlWO0ohBu3s2yMzVZplkadpFnYT0KWqpAb8vdBdrTDoxc
lrql6jvI9FkHFQ+m3mUAXjgT/rPc/oJqQz9NrKb3IOAxxzF/2LP7vjy0+NrLqTgy211hHOt/K6vA
gocKlefeJz/APg3A4yRGVjMJEQhRMBO3/dTY90T7q11CuYTBtsZ/Dtr7T7Z9jq7gOB/G2szE9EVh
CYxrn+GGYOqhjcaO9mbnmrEJ3LV9/hS8t1xBbbKYxnCXN6W14OULEKkScBvzQNN7G4aUNqShCRw7
zOgGLYNt3REAvfuI5CZMA2Sq/fwgh1FFTzvL8lhlvNKA3zKTuDjYZgM1480qOCBuBcYLtVODHmrE
4yDET+2xmmVb0YIO7uzorQ9zNPpVA3GwGXs993+wiqZE3iTCoQ5F+/C+eeIODCWOuwaBxBcl2IFV
/hucnAXLpDYDWVTl1x7xmjRiY1cLVHXU2kDG3jtde8/qb73/mJxMiJmSY1eaxnKs1YNNX4Cmgv1B
xDu4OBXG7JeZVc7jKdO0wVg68+a/wPj4A96TEsn00SwYfO4T2RAQXuyLZ1PViXO/VPwK6dBFK90R
qGbrzmxsIU/fW9uSSR3R3n2b6jCr1QD/vINi/fgdmtY1l2z3yAErDCjbP9rcBVuOY1HvTec6OSlR
67v59Z1Yyl9NUEURk3kLLnMWaXq+XUUofsdcqZ3pBAhfhfRExMnY+CGX11wTUizUL03p/mgYmV5s
hz2ZM4BgBRbBqXGvZYHSxWqy3/clERnbQZIYdCb6eeHeQYw0Y754Ypk31/JCXgvVD7HiP2+1Jnnf
JJWq3hObn0DBX2iYBH0zybGwFefCMZZeK54Y2NA+pzIlPuurVSyg8fcgKgkPLKjW2rnSKIa4/2xg
mAFYTrWyxiGjwsNBtX2pFNT5SQ+d6/GpEgb2vIiQJNugj9fELKcwvBFyZIx00UgN3BQ/C3MPkHQ3
RzydB/JP52qX70D1PrVN/cg1eYtE3PQuXKlMYSljwxBu3Qf2cu5HJotq9mw8GVkT2gqKnwVem/S2
P+5NivBAwfEMNaJlc/+v8zyK9uIkV0UujogBFyLoTVZBlYYl35Iqjor9Mh4udGty774DYwFpLyNx
wAR6TdPTj9M6dhfUH0e/U8knT5cm8GTEfm1wvmUvlbHHq1zew4jSzKVxQNusRUSOl/TEiV6wyMiS
IOUQ0ixzsXXXN9GpvZ+NHpg4v1sAQpGrz4WaYXyjJvJIbO0ydpnbFNSlIkjgcYKDgiohMSm3qTMf
me6jqZAOQVD5H6DsgX3vDOMQYBJB3qBQV9rVhipAdbcahi432elYS4wpxYzxh0stAhiE+NGOHGBz
SLhEcQoRTVoJnkJd+1AFcE7skR5TMBDOtfmnW+6UXZM4q2qhjKEg6f1sWKVpbfWwmEX4C4LB4k1M
Mhn93RjpmWx9Mnr0S+dEVzmDxl8exihV2IH/nyWtX6/Ym2j7Mv3TtcyeMmSyKd6Ikm0dcHsF6Jtk
uFjmcFNzra018x/hi6FGAz/e4A0bdrL206XzI1DHGSRU06zouPywRzl0jzATPSVCwq9Se3WdodXP
z4bWthkhMQQL3I0XYN85M94rChgP9o6Ak7TUiRV20RJKTJgnEcAe//1BbKkSntbSBO93Lwrtji4q
fHSdC230qmYXI+rVvaRYzjHHESvAC+POatkdCNSt9BASDQHdhXT3SmlR6ND4Sw4jw/sCAITTPk6/
GsA3NsV5NtOgFscgfxucr6E5b2WdJzPfm3DYqYIE700uzxdQt8F81jGPmfl9bN6pSadHMCxfv6eX
BBYq9dhKdZ0gIOYwYEzawxbzzxmUqsR3Zx1vKnBvIT8K1cp8XuYtkBykjlAvwHnZaZmjM4vpeFMC
SbD5I7kF9FysOBkoMAMiOHXsjuLoTHqIbYAcRBwvTOmHfzJMaaKERdz9FEVDmX39cs+Dd/z6JC3G
pcgyDgudbFkuBtY3lnxtMvCMHWqdWe7bUNV0gBHMucpLl6VYFJ1LAxLkP9AKK3F8eAVKL6Zc4uqa
1kV961PH8SD5p2Lpjl6f+/qDLXugZYxXkD4Dyj/jEWbZvsVVQZReMnzT9qirCjwkYX3oRJdUMVfd
K1wOKX3+aXvFSD+CZd8/6NNgCNPpfA2uL+XsAJf8H95zWKunUcFy5KH5HM5QbZHLqCIfaa/NN484
56F9Vy0lVfMdHArn4JtanygVumHmp7wqIWdOLJ2wX+rGtrR9q25WTuFvnQlb0/314hB71zVuQSI1
Icg/mOZ6p3A7NvIXNJ6IS24jN+9rSDkV1unzXG8Ccj7TbAh3OaIu70fZITxzyRgkyHz40LYGoeD9
ay7MF66OWWjwmvzt2ukk7YeCpS88i7bHTBhG6YWlLjVh8J945WkIWJuW2220Ofqm4jHosWV011xX
hkWeC4lWDBAHW8EHpro6UuvVkq41qHd45kNaniNWJlPZ7eBMERlOJQl8VIZfWuQ4ChvwSGpMQvI7
Nk79aB6lnn6OxOI8ttYw1ZU8Ob7cu3uJOG/7puidQ2t9zv0KfTUxW5smNZXPBTz5iC3X4mWO/tsx
YYTAtlofgHofkImVUdI78Alzqq/41uAimOXwLPTO4x0PGVlaVO2lTp41TPaMMcdfp+ekJg0RUv5K
cuTBatK1Fm8yyNws2xEHVh5YgCGbttawM/1r4uNv+2QPnS8JgKPNu1FSIXBevzhcyJnX2YfztQS0
a8HFCGM0Rvm1dRY3iG4OfFMGZUEMXWSnGSnZIyyjWtHW5oE1eXwim7/J9hCXohTeWXRI/zM9rcsF
/c8oa94IGaQ2G9xlDoOojZIrYy58b5lMFZ+ulBeXkEr8h6YztCUQm2T1PrFy3eRJtfV5W3/AAzoC
Pu5JqSWO7DVf1iS7bKpdnr/3CwKcXcExPL7udq9EKbn1xQlMIC8QldWnT2x5RN0ux8z3wrz0QV9Y
Q0LTgo8D6pq7soJb1gvZN6wpKM+w8rVph7+US5zsbhBsbgZ6f+astca5eIkBxdZdgTxIY7SWDq1u
5vGFy5674XlB6F0gelxQ+jVHjytkeARoyNeGhC5AF2woZCzovbVXAkctE5/M6gOROqlV9OSkYMTy
RWMZsnUmsBTtE6/FND9SBo7RJ1IrXk16Hx6jyXueH3agLjMi3ybpTsV4JYqv7plTvuWh1M2pR79W
38XFM9CckFEv8SbdZ/8cbMqgUDWrMQniNmTI406pqFZsklX/1hqnPFjCG45kZaS9aLEJ+kmzocOA
HNu08Ye/BCOFsXxHXW1yWIfFDOop0audvLd+UzwDTf5tu9+739rpUtjlmDflUzHnigXWs9QUJc6Y
LNt/CrUrh24o8KMHsAIbi9qWnuYSvxKVArtxe4z+eyhDJ/48jXCV4fggWg43KCktl8ah4EP+3K92
Qra7QWCAG1XY3xoCtj4KJKedfXAAxnbqFGVlGpJTxsNyIBk78VgCOMyYZ7qM7yvUaTvVAEL6Ch3s
cwxmjtzOLbdy6WRMpysOUG8e2k7JgSNlQgZ4h+YA1aQwG8oGsAC0LQELP2yKB3HqjgQHa3fRz30b
7SS3vcMnU0Yb5BfuauhneYqlJMg8sSy6kXetw1WJAN0B70yvdzxOHZnlb+agqG7pYd0ILDaeeGKu
RfRjwEPkmMjASazoOw7e8R/ISvP1J6g5ozw7jDWSAxRYCnowSlL/VKTCOuSJcldxT5pRDf6Cf6il
CRLxRWq15PdH2dWpUYdZto70MwGHXmerWabkzmeKnt+ZmsgQc/Qu4tGf577/qAnoED14CREaDG+L
q8W28zlnncPtgQ9Ut61OlW5wfrfL0A8kFZDhTboxqlI/MaDOWuci42w2bZ2lXPLEWdxueUgMEmW/
zEC8TCj2JoWFUmz7Cv+ZtCIZLjr4FVuHMyg+yjoFqeP41DIODyR3QCKFUOoh1aLYMn3KsiKd55zu
5O94XiSIPyCwfD4gg84jYSWSfrNL3mjKu2+iL5D9j9FPuZPOOZuL1Sxd5Y4z0gY53CWkMWYvI3aS
8E5/0ZYcPGBWiSCWaCZLLj3aasueGAyM/MdYpAD7DueMmP+cQ8g3if01PgpOFkG0JJVm5/8J9rbN
keDSFxFtEeUTa9rnTdanDhLFDAq1bfM41SLRoUS4gFFLNjDsj4TEoFv2KB0JJyoV/HUT+sVXFm6Y
ebMw1DSB2Et6zUIefJnwJlvzyBxBGPChlwBD1+OQz8Z+UmcCydBzU29ZX3KXW4wBUSJFgM7uM4t9
jQnh7VcD0kCtM1MTJwazz42eIdKT0FlGPlnlOlFw+exSdEDe+Q1KeyL9+iFsixAnz3c9iLPWbXL2
ULe1OfncVp1m5vKHKOkrPFPVX8gbQICQs8svFkIcyx4gsWV52yosCChQxCa8cOgepmkGIp/wUNhv
eoAjo8CcE1tvFXY2F3P1jR6PyPB0Q2SdIfFGuurg3T2cyH1UcQqD0GmNWEthK3gyt7UXWO183xvL
K7b4zUKd73BLXceUkSmngovBRN/oKNlDs1c33y0hWvQ45ZRQTrxXwq9PWa/SX/DLmbVsvR3NZwgX
zgqmmvC5CUM3hoZ+8zzmaF2foUHkRPJgZ68mbETwYt8D7lgn/ZPpv/3ZixL5vTscoX/M87lpyJuX
pydo3ns7BP7b+gTSFZMtGJrjX3t7bwP0N6nidtyqStbKc835hI7I5KbhXBme639LPeiWShUhS5Hy
5/EWsR3KxwriWwspHQYTRgFU7Zj3Oj5Ex3vjeLae/CPKGdqtP8jY0aO4b4pL/0taafXQbHjiiZQp
bhHkS6VJdsy4N43VPWboye2CrZ4i5Bt15bKvzbn5LYxrYkbtGyqjygaRFQUJwnS/8mc4jaMYaAVZ
bI5J2/qkFnmv/Dp3pF6fHpcjrhqh0lct/WkQIyaBCrDYSOY1p6KyS0ZfEMwZ/k1QyH6FJC7OEs/l
tknJ1E0ZY2N5DHGFh9L3KoStodm007JMkDOlWjIk/muPK+6MzhhoFF2T95JAn1Kr7gxhV+BkY0Ki
TfaJZWDxhZWzW+kgQZfCpcJAyqy7psb0fR6Y8JyvXjaD7u4jZ8VI+RiwQMJKilgUHvIp/Y4ksCxe
haHQiyHlmuI/2CyCTuHJxBiqT6dgRWwTXMwBdamDhNFiFZD/Rclee83eIcwnKz2Z4i9wAHr/hqH3
TOZcWsBmGwnnOe981IjEZpKaxA5d9gv9JmAEHMgTccedKgT86HTlEOK/l0vQEUcF9g5cT4VmxYyB
vD4e9losKhb4SJo4a1V6HMdD5LidyMcn5hY184O41RrqUHe//nbt5qsbUFIFON/5tBN039oRLTN2
Jfe9YNgOoRxhwEK0pM3Vwp2LG9ZHZB7PEojfEuwp2vahILMObE4f+/XjfYCpyI8fTFjLaP2bWIUg
ifzRJEpBRy5ayhcnHvefAXoXRwurKn/BIGITEmV3p9vsBLFpl9im9HTYHh44qyF7GIqZnFgvvSLn
N7nGpyi1sNGdk8dr4z9AJUqa4ddbzSa9HdNrGevbqmIxewkyVZQ6yFw9FbfeF30gqvHk4vUuwObI
tN3KWKhHv+VmdeV+/lFlnM9JDI2LbHNNEaTL0DMgiRrEXsv1LUKBBDaEiiN6Jjig/UzgnZacrbt3
UWOBrvTRHodllJJmTwp8mYakgajw0WcVujbNPoAGqFTg0o8AUx++B8bV1kv5EgtcSc6PVpeytifl
4i0qrrhM/KPlg5oIqMPpluEn/o5oM62pR5pTZbuhatXgvWQ9XWBuqsbUNQH1EUjLwXpTXrf1pbeX
H+UhB0Q=
`protect end_protected
| gpl-3.0 |
1995parham/FPGA-Homework | HW-4/src/p5/p5.vhd | 1 | 687 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 07-05-2016
-- Module Name: p5.vhd
--------------------------------------------------------------------------------
process (sel, sel_2, sel_3, a, b)
begin
if sel = '1' then
f <= a;
if sel_2 = '1' then
g <= not a;
else
g <= not b;
if sel_3 = '1' then
g <= a xor b;
end if;
end if;
else
if sel_2 = '1' then
g <= a and b;
else
if sel_3 = '1' then
g <= a nand b;
-- preventing from transparent latch creation
else
g <= ...;
end if;
end if;
f <= b;
end if;
end process;
| gpl-3.0 |
1995parham/FPGA-Homework | BCD/binary-to-bcd.vhd | 1 | 2754 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity binary_to_bcd is
port(
binary: in std_logic_vector(7 downto 0);
bcd: out std_logic_vector(7 downto 0)
);
end entity;
architecture struct of binary_to_bcd is
component n_bit_adder
generic(N: integer);
port(
a: in std_logic_vector(N - 1 downto 0);
b: in std_logic_vector(N - 1 downto 0);
cin: in std_logic;
res: out std_logic_vector(N - 1 downto 0);
cout: out std_logic
);
end component;
signal binary_s_1: std_logic_vector(7 downto 0);
signal binary_s_2: std_logic_vector(7 downto 0);
signal binary_s_3: std_logic_vector(7 downto 0);
signal binary_s_4: std_logic_vector(7 downto 0);
signal binary_s_5: std_logic_vector(7 downto 0);
signal binary_s_6: std_logic_vector(7 downto 0);
signal binary_s_7: std_logic_vector(7 downto 0);
signal binary_s_8: std_logic_vector(7 downto 0);
signal binary_s_9: std_logic_vector(7 downto 0);
signal fully_fake_signal: std_logic_vector(8 downto 0);
begin
subtractor_1: n_bit_adder generic map(8)
port map(binary, "00000101", '1', binary_s_1, fully_fake_signal(0));
subtractor_2: n_bit_adder generic map(8)
port map(binary_s_1, "00000101", '1', binary_s_2, fully_fake_signal(1));
subtractor_3: n_bit_adder generic map(8)
port map(binary_s_2, "00000101", '1', binary_s_3, fully_fake_signal(2));
subtractor_4: n_bit_adder generic map(8)
port map(binary_s_3, "00000101", '1', binary_s_4, fully_fake_signal(3));
subtractor_5: n_bit_adder generic map(8)
port map(binary_s_4, "00000101", '1', binary_s_5, fully_fake_signal(4));
subtractor_6: n_bit_adder generic map(8)
port map(binary_s_5, "00000101", '1', binary_s_6, fully_fake_signal(5));
subtractor_7: n_bit_adder generic map(8)
port map(binary_s_6, "00000101", '1', binary_s_7, fully_fake_signal(6));
subtractor_8: n_bit_adder generic map(8)
port map(binary_s_7, "00000101", '1', binary_s_8, fully_fake_signal(7));
subtractor_9: n_bit_adder generic map(8)
port map(binary_s_8, "00000101", '1', binary_s_9, fully_fake_signal(8));
bcd <= binary when to_integer(unsigned(binary)) < 10 else
binary_s_1 when to_integer(unsigned(binary)) < 20 else
binary_s_2 when to_integer(unsigned(binary)) < 30 else
binary_s_3 when to_integer(unsigned(binary)) < 40 else
binary_s_4 when to_integer(unsigned(binary)) < 50 else
binary_s_5 when to_integer(unsigned(binary)) < 60 else
binary_s_6 when to_integer(unsigned(binary)) < 70 else
binary_s_7 when to_integer(unsigned(binary)) < 80 else
binary_s_8 when to_integer(unsigned(binary)) < 90 else
binary_s_9 when to_integer(unsigned(binary)) < 100 else
"XXXXXXXX";
end struct;
| gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/analog_mux_@f060/_primary.vhd | 3 | 2243 | library verilog;
use verilog.vl_types.all;
entity analog_mux_F060 is
generic(
WARNING_MSGS_ON : integer := 1
);
port(
CHNUMBER_I : in vl_logic_vector(4 downto 0);
AV01 : in vl_logic_vector(63 downto 0);
AV02 : in vl_logic_vector(63 downto 0);
AC0 : in vl_logic_vector(63 downto 0);
AT0 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_0 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_1 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_2 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_3 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_4 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_5 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_6 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_7 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_8 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_9 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_10: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_11: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_12: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_13: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_14: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_15: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_16: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_17: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_18: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_19: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_20: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_21: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_22: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_23: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_24: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_25: in vl_logic_vector(63 downto 0);
DAC_VECTOR : in vl_logic_vector(63 downto 0);
MUXOUT : out vl_logic_vector(63 downto 0)
);
end analog_mux_F060;
| gpl-3.0 |
Project-Bonfire/EHA | RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/Allocator_with_checkers/Arbiter_in_one_hot_with_checkers.vhd | 12 | 12952 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
-- Is this like the old arbiter in the router with handshaking FC ??
entity Arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in;
architecture behavior of Arbiter_in is
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in : STATE_TYPE := IDLE;
SIGNAL X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic; -- needed for connecting output ports
-- of Arbiter_in to checker inputs
component Arbiter_in_one_hot_checkers is
port (
req_X_N :in std_logic;
req_X_E :in std_logic;
req_X_W :in std_logic;
req_X_S :in std_logic;
req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N :in std_logic;
X_E :in std_logic;
X_W :in std_logic;
X_S :in std_logic;
X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end component;
begin
-- Becuase of checkers we did this
X_N <= X_N_sig;
X_E <= X_E_sig;
X_W <= X_W_sig;
X_S <= X_S_sig;
X_L <= X_L_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
-- Arbiter_in Checkers module instantiation
ARBITER_IN_CHECKERS: Arbiter_in_one_hot_checkers port map (
req_X_N => req_X_N, -- _sig not needed, because it is an input port
req_X_E => req_X_E, -- _sig not needed, because it is an input port
req_X_W => req_X_W, -- _sig not needed, because it is an input port
req_X_S => req_X_S, -- _sig not needed, because it is an input port
req_X_L => req_X_L, -- _sig not needed, because it is an input port
state => state, -- _sig not needed, because it is an input port
state_in => state_in, -- _sig not needed, because it is an internal signal
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
-- Checker outputs
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => err_IDLE_Req_N,
err_IDLE_grant_N => err_IDLE_grant_N,
err_North_Req_N => err_North_Req_N,
err_North_grant_N => err_North_grant_N,
err_East_Req_E => err_East_Req_E,
err_East_grant_E => err_East_grant_E,
err_West_Req_W => err_West_Req_W,
err_West_grant_W => err_West_grant_W,
err_South_Req_S => err_South_Req_S,
err_South_grant_S => err_South_grant_S,
err_Local_Req_L => err_Local_Req_L,
err_Local_grant_L => err_Local_grant_L,
err_IDLE_Req_E => err_IDLE_Req_E,
err_IDLE_grant_E => err_IDLE_grant_E,
err_North_Req_E => err_North_Req_E,
err_North_grant_E => err_North_grant_E,
err_East_Req_W => err_East_Req_W,
err_East_grant_W => err_East_grant_W,
err_West_Req_S => err_West_Req_S,
err_West_grant_S => err_West_grant_S,
err_South_Req_L => err_South_Req_L,
err_South_grant_L => err_South_grant_L,
err_Local_Req_N => err_Local_Req_N,
err_Local_grant_N => err_Local_grant_N,
err_IDLE_Req_W => err_IDLE_Req_W,
err_IDLE_grant_W => err_IDLE_grant_W,
err_North_Req_W => err_North_Req_W,
err_North_grant_W => err_North_grant_W,
err_East_Req_S => err_East_Req_S,
err_East_grant_S => err_East_grant_S,
err_West_Req_L => err_West_Req_L,
err_West_grant_L => err_West_grant_L,
err_South_Req_N => err_South_Req_N,
err_South_grant_N => err_South_grant_N,
err_Local_Req_E => err_Local_Req_E,
err_Local_grant_E => err_Local_grant_E,
err_IDLE_Req_S => err_IDLE_Req_S,
err_IDLE_grant_S => err_IDLE_grant_S,
err_North_Req_S => err_North_Req_S,
err_North_grant_S => err_North_grant_S,
err_East_Req_L => err_East_Req_L,
err_East_grant_L => err_East_grant_L,
err_West_Req_N => err_West_Req_N,
err_West_grant_N => err_West_grant_N,
err_South_Req_E => err_South_Req_E,
err_South_grant_E => err_South_grant_E,
err_Local_Req_W => err_Local_Req_W,
err_Local_grant_W => err_Local_grant_W,
err_IDLE_Req_L => err_IDLE_Req_L,
err_IDLE_grant_L => err_IDLE_grant_L,
err_North_Req_L => err_North_Req_L,
err_North_grant_L => err_North_grant_L,
err_East_Req_N => err_East_Req_N,
err_East_grant_N => err_East_grant_N,
err_West_Req_E => err_West_Req_E,
err_West_grant_E => err_West_grant_E,
err_South_Req_W => err_South_Req_W,
err_South_grant_W => err_South_grant_W,
err_Local_Req_S => err_Local_Req_S,
err_Local_grant_S => err_Local_grant_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_no_grants => err_request_no_grants,
err_no_Req_N_grant_N => err_no_Req_N_grant_N,
err_no_Req_E_grant_E => err_no_Req_E_grant_E,
err_no_Req_W_grant_W => err_no_Req_W_grant_W,
err_no_Req_S_grant_S => err_no_Req_S_grant_S,
err_no_Req_L_grant_L => err_no_Req_L_grant_L
);
-- Main Logic of Arbiter_in
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L)
begin
X_N_sig <= '0';
X_E_sig <= '0';
X_W_sig <= '0';
X_S_sig <= '0';
X_L_sig <= '0';
case state is
when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S)
-- Here it seems N has the higest priority, is it fine ?
if req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
else
state_in <= state;
end if;
when North =>
if req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
else
state_in <= state;
end if;
when East =>
if req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
else
state_in <= state;
end if;
when West =>
if req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
else
state_in <= state;
end if;
when South =>
if req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
else
state_in <= state;
end if;
when others =>
if req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
else
state_in <= state;
end if;
end case;
end process;
end;
| gpl-3.0 |
1995parham/FPGA-Homework | HW-3/src/p10/p10.vhd | 1 | 1673 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 25-04-2016
-- Module Name: p10.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu is
port (a, b : in std_logic_vector (3 downto 0);
alucode : in std_logic_vector (2 downto 0);
result : out std_logic_vector (3 downto 0);
z, o : out std_logic);
end entity;
architecture rtl of alu is
begin
process (alucode, a, b)
variable im : std_logic_vector (4 downto 0);
begin
case alucode is
-- ADD
when "000" =>
im := ('0' & a) + ('0' & b);
result <= im(3 downto 0);
z <= im(4);
-- SUB
when "001" =>
im := ('0' & a) - ('0' & b);
result <= im(3 downto 0);
z <= im(4);
-- AND
when "010" =>
im(3 downto 0) := (a(0) and b(0)) & (a(1) and b(1)) & (a(2) and b(2)) & (a(3) and b(3));
if im(3 downto 0) = "111" then
z <= '1';
else
z <= '0';
end if;
result <= im(3 downto 0);
-- CMP
when "011" =>
if a < b then
result <= a;
z <= '0';
elsif a = b then
result <= a;
z <= '1';
else
result <= b;
z <= '0';
end if;
-- RT
when "100" =>
result <= '0' & a(2 downto 0);
z <= a(3);
-- RR
when "101" =>
result <= a(3 downto 1) & '0';
z <= a(0);
-- Parity
when "110" =>
result <= a;
z <= a(0) xor a(1) xor a(2) xor a(3);
when others =>
result <= (others => '0');
z <= '0';
o <= '0';
end case;
end process;
end architecture;
| gpl-3.0 |
Project-Bonfire/EHA | RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/network_2x2_customized_packet_drop_SHMU_credit_based_with_checkers_with_PE_top.vhd | 3 | 23284 | --Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x: 2
-- network size y: 2
-- Data width: 32
-- Parity: False
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
use work.component_pack.all;
entity network_2x2_with_PE is
generic (DATA_WIDTH: integer := 32;
DATA_WIDTH_LV: integer := 11;
memory_type : string :=
"TRI_PORT_X"
-- "DUAL_PORT_"
-- "ALTERA_LPM"
-- "XILINX_16X"
);
port (reset: in std_logic;
clk: in std_logic;
-- IJTAG network for fault injection and checker status monitoring
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- GPIO for Node 0
GPIO_out: out std_logic_vector(15 downto 0);
GPIO_in: in std_logic_vector(21 downto 0);
-- UART for all Plasmas
uart_write_0 : out std_logic;
uart_read_0 : in std_logic;
uart_write_1 : out std_logic;
uart_read_1 : in std_logic;
uart_write_2 : out std_logic;
uart_read_2 : in std_logic;
uart_write_3 : out std_logic;
uart_read_3 : in std_logic;
-- Monitor connections
temperature_control : out std_logic_vector(2 downto 0);
iddt_control : out std_logic_vector(2 downto 0);
slack_control : out std_logic_vector(2 downto 0);
slack_data : in std_logic_vector(31 downto 0);
voltage_control : out std_logic_vector(2 downto 0);
voltage_data : in std_logic_vector(31 downto 0)
);
end network_2x2_with_PE;
architecture behavior of network_2x2_with_PE is
constant RAMDataSize : positive := 32;
constant RAMAddrSize : positive := 12;
constant path : string(1 to 12) := "Testbenches/"; --uncomment this if you are SIMULATING in MODELSIM, or if you're synthesizing.
-- constant path : string(positive range <>) := "/home/tsotne/ownCloud/git/Bonfire_sim/Bonfire/RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/"; --used only for Vivado similation. Tsotnes PC.
component immortal_sensor_IJTAG_interface is
Port ( -- Scan Interface client --------------
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
temperature_control : out std_logic_vector(2 downto 0);
temperature_data : in std_logic_vector(12 downto 0);
iddt_control : out std_logic_vector(2 downto 0);
iddt_data : in std_logic_vector(12 downto 0);
slack_control : out std_logic_vector(2 downto 0);
slack_data : in std_logic_vector(31 downto 0);
voltage_control : out std_logic_vector(2 downto 0);
voltage_data : in std_logic_vector(31 downto 0));
end component;
component SIB_mux_pre_FCX_SELgate is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC); -- From an AND of all C flags in the underlying network segment
end component;
component RAMAccessInstrument is
Generic ( DataSize : positive := 8;
AddressSize : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in std_logic; -- ScanInPort
SO : out std_logic; -- ScanOutPort
SEL : in std_logic; -- SelectPort
----------------------------------------
SE : in std_logic; -- ShiftEnPort
CE : in std_logic; -- CaptureEnPort
UE : in std_logic; -- UpdateEnPort
RST : in std_logic; -- ResetPort
TCK : in std_logic; -- TCKPort
MEM_SIB_SEL : out std_logic;
-- RAM interface
RAM_data_read : in std_logic_vector (DataSize-1 downto 0);
RAM_data_write : out std_logic_vector (DataSize-1 downto 0);
RAM_address_out : out std_logic_vector (AddressSize-1 downto 0);
RAM_write_enable : out std_logic);
end component;
-- Monitor signals
signal temperature_data : std_logic_vector(12 downto 0);
signal iddt_data : std_logic_vector(12 downto 0);
-- Declaring network component
-- Declaring NoC_Node component (with Plasma, RAM, NI and UART)
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
-- NI testing signals
--------------
--signal Rxy_reconf: std_logic_vector (7 downto 0) := "01111101";
--signal Reconfig: std_logic := '0';
--------------
signal not_reset: std_logic;
signal link_faults_0, link_faults_1, link_faults_2, link_faults_3 : std_logic_vector(4 downto 0);
signal turn_faults_0, turn_faults_1, turn_faults_2, turn_faults_3 : std_logic_vector(19 downto 0);
signal Rxy_reconf_PE_0, Rxy_reconf_PE_1,Rxy_reconf_PE_2, Rxy_reconf_PE_3 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_0, Cx_reconf_PE_1, Cx_reconf_PE_2, Cx_reconf_PE_3 : std_logic_vector(3 downto 0);
signal Reconfig_command_0, Reconfig_command_1, Reconfig_command_2, Reconfig_command_3 : std_logic;
signal GPIO_out_FF_in, GPIO_out_FF : std_logic_vector(15 downto 0);
signal UART_0_W_in, UART_0_W_out, UART_0_R_in, UART_0_R_out : std_logic;
signal UART_1_W_in, UART_1_W_out, UART_1_R_in, UART_1_R_out : std_logic;
signal UART_2_W_in, UART_2_W_out, UART_2_R_in, UART_2_R_out : std_logic;
signal UART_3_W_in, UART_3_W_out, UART_3_R_in, UART_3_R_out : std_logic;
-- IJTAG-related signals
signal SO_NoC , SO_sensors , SO_RAM : std_logic;
signal toF_NoC, toF_sensors, toF_RAM : std_logic;
signal toC_NoC, toC_sensors, toC_RAM : std_logic;
signal SIB_RAM_toSI, SIB_RAM_toTCK, SIB_RAM_toRST, SIB_RAM_toSEL, SIB_RAM_toUE, SIB_RAM_toSE, SIB_RAM_toCE : std_logic;
signal RAM0_SO, RAM1_SO, RAM2_SO, RAM3_SO : std_logic;
signal RAM0_write_enable, RAM1_write_enable, RAM2_write_enable, RAM3_write_enable : std_logic;
signal RAM0_address, RAM1_address, RAM2_address, RAM3_address : std_logic_vector(RAMAddrSize-1 downto 0);
signal IJTAG_ram_0_select : std_logic;
signal IJTAG_ram_0_clk : std_logic;
signal IJTAG_ram_0_reset : std_logic;
signal IJTAG_ram_0_enable : std_logic;
signal IJTAG_ram_0_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_0_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_0_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_0_data_read : std_logic_vector(31 downto 0);
signal IJTAG_ram_1_select : std_logic;
signal IJTAG_ram_1_clk : std_logic;
signal IJTAG_ram_1_reset : std_logic;
signal IJTAG_ram_1_enable : std_logic;
signal IJTAG_ram_1_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_1_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_1_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_1_data_read : std_logic_vector(31 downto 0);
signal IJTAG_ram_2_select : std_logic;
signal IJTAG_ram_2_clk : std_logic;
signal IJTAG_ram_2_reset : std_logic;
signal IJTAG_ram_2_enable : std_logic;
signal IJTAG_ram_2_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_2_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_2_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_2_data_read : std_logic_vector(31 downto 0);
signal IJTAG_ram_3_select : std_logic;
signal IJTAG_ram_3_clk : std_logic;
signal IJTAG_ram_3_reset : std_logic;
signal IJTAG_ram_3_enable : std_logic;
signal IJTAG_ram_3_write_byte_enable : std_logic_vector(3 downto 0);
signal IJTAG_ram_3_address : std_logic_vector(31 downto 2);
signal IJTAG_ram_3_data_write : std_logic_vector(31 downto 0);
signal IJTAG_ram_3_data_read : std_logic_vector(31 downto 0);
begin
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3,
link_faults_0, turn_faults_0, Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0,
link_faults_1, turn_faults_1, Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1,
link_faults_2, turn_faults_2, Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2,
link_faults_3, turn_faults_3, Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3,
TCK, RST, SEL, SO_sensors, SE, UE, CE, SO_NoC, toF_NoC, toC_NoC
);
process (not_reset, clk)
begin
if not_reset = '1' then
GPIO_out_FF <= (others => '0');
UART_0_W_out <= '0';
UART_1_W_out <= '0';
UART_2_W_out <= '0';
UART_3_W_out <= '0';
UART_0_R_out <= '0';
UART_1_R_out <= '0';
UART_2_R_out <= '0';
UART_3_R_out <= '0';
elsif clk'event and clk = '1' then
GPIO_out_FF <= GPIO_out_FF_in;
UART_0_W_out <= UART_0_W_in;
UART_1_W_out <= UART_1_W_in;
UART_2_W_out <= UART_2_W_in;
UART_3_W_out <= UART_3_W_in;
UART_0_R_out <= UART_0_R_in;
UART_1_R_out <= UART_1_R_in;
UART_2_R_out <= UART_2_R_in;
UART_3_R_out <= UART_3_R_in;
end if;
end process;
GPIO_out <= GPIO_out_FF;
uart_write_0 <= UART_0_W_out;
uart_write_1 <= UART_1_W_out;
uart_write_2 <= UART_2_W_out;
uart_write_3 <= UART_3_W_out;
UART_0_R_in <= uart_read_0;
UART_1_R_in <= uart_read_1;
UART_2_R_in <= uart_read_2;
UART_3_R_in <= uart_read_3;
not_reset <= not reset;
-- instantiating and connecting the PEs
PE_0: NoC_Node
generic map( current_address => 0,
stim_file => path & "code_0.txt",
log_file => path & "output_0.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_0_R_out,
uart_write => UART_0_W_in,
credit_in => credit_out_L_0,
valid_out => valid_in_L_0,
TX => RX_L_0,
credit_out => credit_in_L_0,
valid_in => valid_out_L_0,
RX => TX_L_0,
link_faults => link_faults_0,
turn_faults => turn_faults_0,
Rxy_reconf_PE => Rxy_reconf_PE_0,
Cx_reconf_PE => Cx_reconf_PE_0,
Reconfig_command => Reconfig_command_0,
GPIO_out => GPIO_out_FF_in,
GPIO_in => GPIO_in,
IJTAG_select => IJTAG_ram_0_select,
IJTAG_clk => IJTAG_ram_0_clk,
IJTAG_reset => IJTAG_ram_0_reset,
IJTAG_enable => IJTAG_ram_0_enable,
IJTAG_write_byte_enable => IJTAG_ram_0_write_byte_enable,
IJTAG_address => IJTAG_ram_0_address,
IJTAG_data_write => IJTAG_ram_0_data_write,
IJTAG_data_read => IJTAG_ram_0_data_read
);
PE_1: NoC_Node
generic map( current_address => 1,
stim_file => path & "code_1.txt",
log_file => path & "output_1.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_1_R_out,
uart_write => UART_1_W_in,
credit_in => credit_out_L_1,
valid_out => valid_in_L_1,
TX => RX_L_1,
credit_out => credit_in_L_1,
valid_in => valid_out_L_1,
RX => TX_L_1,
link_faults => link_faults_1,
turn_faults => turn_faults_1,
Rxy_reconf_PE => Rxy_reconf_PE_1,
Cx_reconf_PE => Cx_reconf_PE_1,
Reconfig_command => Reconfig_command_1,
GPIO_out => open,
GPIO_in => (others => '0'),
IJTAG_select => IJTAG_ram_1_select,
IJTAG_clk => IJTAG_ram_1_clk,
IJTAG_reset => IJTAG_ram_1_reset,
IJTAG_enable => IJTAG_ram_1_enable,
IJTAG_write_byte_enable => IJTAG_ram_1_write_byte_enable,
IJTAG_address => IJTAG_ram_1_address,
IJTAG_data_write => IJTAG_ram_1_data_write,
IJTAG_data_read => IJTAG_ram_1_data_read
);
PE_2: NoC_Node
generic map( current_address => 2,
stim_file => path & "code_2.txt",
log_file => path & "output_2.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_2_R_out,
uart_write => UART_2_W_in,
credit_in => credit_out_L_2,
valid_out => valid_in_L_2,
TX => RX_L_2,
credit_out => credit_in_L_2,
valid_in => valid_out_L_2,
RX => TX_L_2,
link_faults => link_faults_2,
turn_faults => turn_faults_2,
Rxy_reconf_PE => Rxy_reconf_PE_2,
Cx_reconf_PE => Cx_reconf_PE_2,
Reconfig_command => Reconfig_command_2,
GPIO_out => open,
GPIO_in => (others => '0'),
IJTAG_select => IJTAG_ram_2_select,
IJTAG_clk => IJTAG_ram_2_clk,
IJTAG_reset => IJTAG_ram_2_reset,
IJTAG_enable => IJTAG_ram_2_enable,
IJTAG_write_byte_enable => IJTAG_ram_2_write_byte_enable,
IJTAG_address => IJTAG_ram_2_address,
IJTAG_data_write => IJTAG_ram_2_data_write,
IJTAG_data_read => IJTAG_ram_2_data_read
);
PE_3: NoC_Node
generic map( current_address => 3,
stim_file => path & "code_3.txt",
log_file => path & "output_3.txt",
memory_type => memory_type)
port map( not_reset, clk,
uart_read => UART_3_R_out,
uart_write => UART_3_W_in,
credit_in => credit_out_L_3,
valid_out => valid_in_L_3,
TX => RX_L_3,
credit_out => credit_in_L_3,
valid_in => valid_out_L_3,
RX => TX_L_3,
link_faults => link_faults_3,
turn_faults => turn_faults_3,
Rxy_reconf_PE => Rxy_reconf_PE_3,
Cx_reconf_PE => Cx_reconf_PE_3,
Reconfig_command => Reconfig_command_3,
GPIO_out => open,
GPIO_in => (others => '0'),
IJTAG_select => IJTAG_ram_3_select,
IJTAG_clk => IJTAG_ram_3_clk,
IJTAG_reset => IJTAG_ram_3_reset,
IJTAG_enable => IJTAG_ram_3_enable,
IJTAG_write_byte_enable => IJTAG_ram_3_write_byte_enable,
IJTAG_address => IJTAG_ram_3_address,
IJTAG_data_write => IJTAG_ram_3_data_write,
IJTAG_data_read => IJTAG_ram_3_data_read
);
-------------------------------------------
------- IJTAG stuff -----------------------
-------------------------------------------
-- Organization of IJTAG network (top level):
-- .----------. .-----------. .----------.
-- SI ----| sib_ram |---| sib_sens |---| sib_noc |-- SO
-- '----------' '-----------' '----------'
-- | |_________________________________________________.
-- | |
-- | .-----------. .-----------. .-----------. .-----------. |
-- '-| sib_ram_0 |-| sib_ram_1 |-| sib_ram_2 |-| sib_ram_3 |-'
-- '-----------' '-----------' '-----------' '-----------'
toF <= toF_NoC or toF_sensors;
toC <= toC_NoC and toC_sensors;
SO <= SO_NoC;
IJTAG_ram_0_enable <= '1';
IJTAG_ram_1_enable <= '1';
IJTAG_ram_2_enable <= '1';
IJTAG_ram_3_enable <= '1';
IJTAG_ram_0_clk <= TCK;
IJTAG_ram_1_clk <= TCK;
IJTAG_ram_2_clk <= TCK;
IJTAG_ram_3_clk <= TCK;
IJTAG_ram_0_reset <= RST;
IJTAG_ram_1_reset <= RST;
IJTAG_ram_2_reset <= RST;
IJTAG_ram_3_reset <= RST;
-- RAM Access SIB
SIB_RAM : SIB_mux_pre_FCX_SELgate
port map ( -- Scan Interface client --------------
SI => SI,
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SO_RAM,
toF => toF_RAM,
toC => toC_RAM,
-- Scan Interface host ----------------
fromSO => RAM3_SO,
toCE => SIB_RAM_toCE,
toSE => SIB_RAM_toSE,
toUE => SIB_RAM_toUE,
toSEL => SIB_RAM_toSEL,
toRST => SIB_RAM_toRST,
toTCK => SIB_RAM_toTCK,
toSI => SIB_RAM_toSI,
fromF => '0',
fromC => '1'
);
-- RAM Access instruments
RAM_instr0 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => SIB_RAM_toSI,
SO => RAM0_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_0_select,
RAM_data_read => IJTAG_ram_0_data_read,
RAM_data_write => IJTAG_ram_0_data_write,
RAM_address_out => RAM0_address,
RAM_write_enable => RAM0_write_enable);
IJTAG_ram_0_write_byte_enable <= (others => RAM0_write_enable);
IJTAG_ram_0_address <= "000000000000000000" & RAM0_address;
RAM_instr1 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => RAM0_SO,
SO => RAM1_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_1_select,
RAM_data_read => IJTAG_ram_1_data_read,
RAM_data_write => IJTAG_ram_1_data_write,
RAM_address_out => RAM1_address,
RAM_write_enable => RAM1_write_enable);
IJTAG_ram_1_write_byte_enable <= (others => RAM1_write_enable);
IJTAG_ram_1_address <= "000000000000000000" & RAM1_address;
RAM_instr2 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => RAM1_SO,
SO => RAM2_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_2_select,
RAM_data_read => IJTAG_ram_2_data_read,
RAM_data_write => IJTAG_ram_2_data_write,
RAM_address_out => RAM2_address,
RAM_write_enable => RAM2_write_enable);
IJTAG_ram_2_write_byte_enable <= (others => RAM2_write_enable);
IJTAG_ram_2_address <= "000000000000000000" & RAM2_address;
RAM_instr3 : RAMAccessInstrument
generic map ( DataSize => RAMDataSize,
AddressSize => RAMAddrSize)
port map ( SI => RAM2_SO,
SO => RAM3_SO,
SEL => SIB_RAM_toSEL,
SE => SIB_RAM_toSE,
CE => SIB_RAM_toCE,
UE => SIB_RAM_toUE,
RST => SIB_RAM_toRST,
TCK => SIB_RAM_toTCK,
MEM_SIB_SEL => IJTAG_ram_3_select,
RAM_data_read => IJTAG_ram_3_data_read,
RAM_data_write => IJTAG_ram_3_data_write,
RAM_address_out => RAM3_address,
RAM_write_enable => RAM3_write_enable);
IJTAG_ram_3_write_byte_enable <= (others => RAM3_write_enable);
IJTAG_ram_3_address <= "000000000000000000" & RAM3_address;
-- IMMORTAL sensors interface
immortal_sensors: immortal_sensor_IJTAG_interface
port map (
TCK => TCK,
RST => RST,
SEL => SEL,
SI => SO_RAM,
SE => SE,
UE => UE,
CE => CE,
SO => SO_sensors,
toF => toF_sensors,
toC => toC_sensors,
temperature_control => temperature_control,
temperature_data => temperature_data,
iddt_control => iddt_control,
iddt_data => iddt_data,
slack_control => slack_control,
slack_data => slack_data,
voltage_control => voltage_control,
voltage_data => voltage_data
);
temperature_data <= (others => '0');
iddt_data <= (others => '0');
end;
| gpl-3.0 |
1995parham/FPGA-Homework | HW-3/src/p12/p12.vhd | 1 | 2774 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 26-04-2016
-- Module Name: p12.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity drawstring is
port (p1, p2 : in std_logic;
clk, reset : in std_logic;
led : out std_logic_vector (9 downto 1));
end entity;
architecture rtl of drawstring is
type state is (led1, led2, led3, led4, led5, led6, led7, led8, led9);
signal current_state, next_state : state := led5;
begin
process (clk, reset)
begin
if reset = '1' then
current_state <= led5;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
process (current_state, p1, p2)
begin
case current_state is
when led1 =>
if p1'event and p1 = '1' then
next_state <= led2;
elsif p2'event and p2 = '1' then
next_state <= led1;
end if;
when led2 =>
if p1'event and p1 = '1' then
next_state <= led3;
elsif p2'event and p2 = '1' then
next_state <= led1;
end if;
when led3 =>
if p1'event and p1 = '1' then
next_state <= led4;
elsif p2'event and p2 = '1' then
next_state <= led2;
end if;
when led4 =>
if p1'event and p1 = '1' then
next_state <= led5;
elsif p2'event and p2 = '1' then
next_state <= led3;
end if;
when led5 =>
if p1'event and p1 = '1' then
next_state <= led6;
elsif p2'event and p2 = '1' then
next_state <= led4;
end if;
when led6 =>
if p1'event and p1 = '1' then
next_state <= led7;
elsif p2'event and p2 = '1' then
next_state <= led5;
end if;
when led7 =>
if p1'event and p1 = '1' then
next_state <= led8;
elsif p2'event and p2 = '1' then
next_state <= led6;
end if;
when led8 =>
if p1'event and p1 = '1' then
next_state <= led9;
elsif p2'event and p2 = '1' then
next_state <= led7;
end if;
when led9 =>
if p1'event and p1 = '1' then
next_state <= led9;
elsif p2'event and p2 = '1' then
next_state <= led8;
end if;
end case;
end process;
process (current_state)
begin
case current_state is
when led1 => led <= (1 => '1', others => '0');
when led2 => led <= (2 => '1', others => '0');
when led3 => led <= (3 => '1', others => '0');
when led4 => led <= (4 => '1', others => '0');
when led5 => led <= (5 => '1', others => '0');
when led6 => led <= (6 => '1', others => '0');
when led7 => led <= (7 => '1', others => '0');
when led8 => led <= (8 => '1', others => '0');
when led9 => led <= (9 => '1', others => '0');
end case;
end process;
end architecture;
| gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_status_flags_sshft.vhd | 9 | 19058 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
V0RhEmDneyx2bIYg5EkqMn5D103c8LY0JwOi4vIzIundV7pB4mhwtg3bWvXtJcqVzWoRpO0iu6hd
b5vQvw4OIw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
NPilDSqrDwgfnG8QwrK9pzdKc2EyBdnxvte2xUHdXc3XmUSDWcLQM8tlHwjTc0fmRllJEyeVIoy3
+OOdcqUxWRXdJnmylHty6xJAg+/Sjpcxt9Wndn8Uj6P+DnRcBtrGwDKuQj9OLMJ2nyzTdGslagCW
2MvrokQETmpzJTx+xn8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BIsdTK6SsXN9BbudzwhdR157/hy8fR+veNFLoFYP4d7KK59/1qX9WEKIjXxdh6jOd9oKlk3wq1R4
tCRvMmX9QIrfX9P0eZ0ywyvtLKYMELricLvzLddzGzGXy45L0UR5z6O6iyAmkbswbaxcV/rFdbfp
+MvPSi29zYu+Ik9PGyM0ZLMRujFCTsVjn0LMR+fwPr0R95gAkMGuKpIq0+RcQreroLO5g0p7eM5g
T/nITDKgCwo16W0hWmHYCWVIzSS+jaS6O+hzNbme01d4Haq/09X81kExJZmAz6suZ/M5pGiw45sW
uX/NO+nhlJA/4TP3Ii6Su4We30OsNmkV9XudsA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Zw5vs1IfRKfJY2nstDiEd4QSSb7enWH38yjPDIbhpMKIURm1dzfEQqhIvXlwk78QLnr5oU9yFaBT
ulET/5iZm6HXM5TLkrDD7mrsT1wRIzGsWjZJAEjdqivu/Cffrl7vEFxtjUAOwCu2hWlDOzxYA40p
EN3J2XA1bMOAqQafEN4=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dnOhe7VK3QkpSD5kx1h0DtWGGzmZirboP8jSaNNmyrqJDjh6AzuWE7WlC7GznQi6/XDLxfUKzLta
BUfpsw3uzYCN4o5mq3R7oEX/c/2vvZquACpkb+6ddj4+NjUwsUcyq3b1StXepqpUUAsSPsne7xiL
Wqm5ZYKFKZkGIY51iEY/x09IrCADOEbB8KNitAUfWXQ8jJU2/5YxLeLKEUA7bO/nIoZudUMSFc+m
CiGC9wGaqecuGX/ccHA4hcqekr1yT11hr+Wr7qi13IB0OVTjakXH7phfvhCBquh3C418MF8o1PD3
zPppyLec68s7ZGvu0bZsnINA5R381Y53bX0OGw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12368)
`protect data_block
vK6cYwjcQhndWcb9L7IQrZd9Li+VJB7JOgTTZDFG1KOeomh7cKgqDeszrDqvc+zsGAdox6KWCR9M
T6W/8TM5MtQIUpgr0PExzY6QfmHbNbGSxXwKXgaGdIEuHWNG6z56IJP6pXHnYVaGTVfqdY/T9axm
5QhH/5CMyPbIvhalNFLw9NhNoxVzBXH5qQgnJ4Hc3X3f1ReZ8bbyvtHO23jOhOeVgvmwmhIEhLbt
1QhmzpYJ2Joj9sbHmbuj35xCF7VZD7Wlb3lI/U4QO5TEsubd5V0wxgHHGj7H+uCo9uZwIr+dx4rI
ZKxAhKbJX0US/511QDpquP6PjvZpEO/0ARPsZJJS0Dr/KYycyuDCIxHmRMg1LJty9iJskWsbqyIC
dBMc9VQN+o9U4MSJVvAL+VI6FlMchxyhi+3QVFEasHiU2xakPs2kc2dkr1Xvl9pwonVDXXgZrwmh
POF9z1nbYdsi/qf8n+yZDoZSLF8isthAAX0GEahqg+eJel6ygvP303jCcGLbcBerBFPLBAhpFXdU
MTQnlSbBRaMWovDXgEJAX+dpePwfl1R4S1sIkkRZsJnmVxwyoUH569DMYLiNzCIIqrR2U64Q5xbp
ZpS/0E/xV/mep08zHyMuvb7ZQhaH5SQFFidhG0lJK5b9YzizGsoUr5WtPZ2ZJhPLrMSokOqwtUsW
nOn2XO9h+uf7Cextsujkhzo4DxKSrt+y2nbUx3Z5jbzZR9EIwrqaX7y2Y1uSjk0y45E9oiHJJKfQ
tfQteFvxnfDzVLd+O4YOuFWvR0n2i7bsHIg+xWlxrilQJusPMHkWlOsLeibI8ExhFKFnUTxQBk9q
u0D7OF2gBspTExKOJo0l3lsVrmnPHHB5ms1cuWIuG7H67+jbm3sVKG+Hm5IElRP49NLNqSHOgoyu
kRX66WlKB/p7smg6ZaiJv7WRi8t+0Bi9bZbIQ4RrgmaipEtzi+HMgnzFDy5DhcDB5dmczlfUPSA0
W5fH1iwzA2rutLeIaBUHc+Wk/si6T35ZyBn94+p00FStc7w+wlBLwSdXmWGVjlDled9N4v9pFxif
lt3U+lDXLfWf2tQL0MwECDexBmubhti0E4A/1JLewveeLTb8p84dfeoeYxHjrvpLodRvz6ubuT1a
M+gLNOPoO7hsBTZUiLv12AAZZgMV26ffY2lphcxHdCZ6TgcIudt7fGxoRq55kQOZ32sxUq3M09yH
gLAwEGrYebiqrdCJl0asQPu7QUTmZ2JCY3gVrclKWWomQofRgFOSOa2F84OwR4VooRvWZgWCrZMu
gbP4r6S0pkG2gO1CDOx0eAfpQIF03UpEkHEIxHjFlNPxUhkZMOkfD0LN53FexYqoi+vrx+5SdQtS
4qJwmounb07u08bTXuI8UAteFXFac4D/R1V99Fs9oQpjs5GetuuvbeHtm9S/0dc2edxIgRPe85hG
G55rXiY57PcEm/zs+VI5wjKoLF5hY9mwUpBe5Ph0YxJij+gvbxB7692e08nlCvMfzjRODZPp5puI
cN52I1O0YckAlBfBOkbZia95KW2M0Vz6qtJvyVTVVgY/Xnt+uw/neDy9rHwHQTuuEdNrQjhNJma7
c2PpD60gaqv1epFyV9X4C0k/+WJr6I/eizGEUEzQ+6aJxIY4sy3tZlC9mrPmjUjlffp4EKe7SnDP
OWKz4snr6jueIoQV/0BmC+23j4jxyyibA2pgG4dsbzVrkwMe85R69KpRMfDR7KaOJf6WzI1yaJ1m
WBVEL/DQ6n5sLvZamZs8W0VX6yjYqzsSmIkDNdZg8EdWQn2RBu6z++t4H4NCWwfAkxewP2C/cFG9
NZr7zfF8tE5rIjiWGsJ0mwGceUkyLrCDYfHisKhWN0dKZHjZG0E1iFx6E+8U/OZGjBvTB9uKzz9i
tA/a7RIk2xTraLI5gMGv/nwBIW5L8zP3TYC0d++MqR7/faN76Peb+IExlhm3G49Lucc56nKQxCuQ
7Q2wTaYFqHzQ8WFqeK0EdVEYF79atGGXkDA4cgEROjCbRp5r0Y3uBgJkO+We842JHY94hobQEKGk
iHcEiW1THw43AY8Kh2tXbOFkPbQ2+Djfr+0Wc/U2p9FZh13yiYZlcxb0Fz2JPIvAK0xEKkFFU1Ty
HA2og2pggv/DWWP/tyiGH6tVmruGkDqxcqu/NDs0QaZj6svyRAbfIMKL2tunDWd9Gm4wiA9+esJw
YTGitIYtkWU/afo1YTTEFWNR3oo5CjG8jWIAgBVHBX3/XBLQDDqFLy4Mj39m9BN5DDBi1Hxob/0z
5PuqutP941oNUoOLrjaApNrheeUoAWN9tdm8HZaNzvV5eIYVi8gucoFfQaCflc5YaIbPKjJiQWwl
abtTUzoFW2/SuKi3FfmkddXltt1b+7+ykXE8FqZOWlEoHB0zwulllTFrJ6cp+8fE+XgfWlWfjqAZ
mnfe04feQqeHMAFGfqGNTXZNl5Q1HQIwXmvqZOcNbbRyelRvDNVuLxvvFoALKzTMaB330U8JL2xj
pNloPShp0oDJv8mwFqHQ38yO0MTWSI7uVUoHqfaUN7hMPTfU5+6u8gWmTy0vPe8bibPasbPuqaU3
72S6/U9LEShHiiHQPB0uig8tv76uMaR5xdc8oCJVtc7H8vrdOjjEnDCTble4+VG9JQROS63HAp2B
SkP3jeDE5oTQtPS7c4zIW5W11wQzBmSBncokcWMFamTBJX+prWYKaJ14CYbq+e/b1rQUQkh89r9p
GN9C49s4jQD7n2RcnHJJ0eeEdrA60f7ajwZSUVT1w6QU++HalsF1KI824b2esd1Rr11/3p2hlJa1
4jITz3Qc6SZpyYp+PBlCDSMyx8Y7zY4pwen3vlUuypnWLDuI5psUht/RgrXO9YHzc9G3GCLZpbPW
SP/WbiVSzD21IN1GXYwxNEor54nIAIsmdB+Z0Ljq8K4zoKC+xxetorjqWqtjy7dQzSOfrRX1z7Nx
nbypNc81sj2tLm8a2vH/efpE6ZFZ+08btA+fKr1XhIdLuM0+5Vw6Nrbbup9O20fT/F2AsyZavShv
Lucy0Os/frhq97QlwVRaobBF1QT+rlDJ0sT3bETHYSCWhAfw7prgbgLIUEcuLsCELo4pZk8Due3a
zzjZGHLyJiGW8yhb6TlQ491n+/jVe3bBonoZrnepXP3y6fBFjIFNQHZJ25Fb4kiAhqvvASXQE5IJ
rbhkyDsvrOTuuRTlcDYPisAB7K1N+a8JwRNVrYxcI/kNRElVC6i27rpFN+Gaoi+v3nOmJrREfn/h
0JciozVg2PZaWWHYNBSfYfZdC/ikFzrszGHffDptcUbsLawjGFENrL+mmSwADLphMFPzfY9Nv9Vf
dRNczqx1/OOGL94cXABVt/LCKi3tm6iKhL+VGfbqFS9Icb6X3g02pm21TW8Tbu+CdRZMTcbKlj2X
W2P8Gh7N8AU98X1Em4pxL/P6pdEvBJg3Tu+CO/Rr0vnkaDF4iRJdNvdD0iBKSU7TTVkaD76kUcRq
3l3TExuzJ+z86Lv0rKNOjTWxNipThIpQn4BLT1ZrfOty16vYbVx+OVEMAFVNYHNHOcqORoSuhelY
WLsfgcbHLyyf5pEHQXOZbAHom5FSIQ+XkYBDDCnP8kM9d4o8no6UoELLvYAmgt+SmuBKBooc0y1h
YPHmGwolbwe3saeIUEScTnbg94ROm2PXptluaLWgmaHQL+Qlj1rdLRc5uIuEZZAqhR+cjJ3/m8ZU
0RnNchY72mS2aVHIkjxlHkEypVpQ5vkLYv9fb8hQS249pte32GZAp1DMFgYs9iJvi38cQcpGn6ob
Os5Pdt4hTEbCxElGJQ2yL4QcAAOrndq+CqR433YJzBFpnglTu/EyIBNwu1lGO/iu5tJNC+FEyI+k
aflf8fCvSB9NLj48bUdk2L9zg0wHXNiQjer9wf46Itw+Tk4q6q6LvYsVLsHwWIcOK38ZQ6DGplpa
2JM65M6TETekR9JOKudZ96/rxlOKQ3DqRqBBqu4/mfvVd4filhcNs8TcnEVLbhiktEWT1pI9J1MX
FcB9Zpgr64XrDGFTjOciLyOz45kGQunKNebe9ZYs+xexv92q7apmjEGLbAzNkCBdJXQKsZMlpMX8
pePY+USanTzRLZZSv3isLA83P8lHtjSkV6aT409oVnvJoiGJHkjCbtp9k1EufJ1DoqpS2FCgt4v0
puj76DQykO/EyZKf3JRm/jIODHIvU0x6quB5H/9QVXVb2sQzZXB+1BX6mbNqmH4t1ek+4zr8mz0n
lEZGWnZMp10R4iMm1AIqtjB2Nr1ZHEcwjNXtPzxQvX4JlN5A0DJOkT+Hw+5DIqsRswTrteMHoJsB
QaW23ny1dPKWSola1AMJhFgCYoA76am66CurD+VOFlV0PEvqaLjM4TT1iiZtgsaYKyO+UgpglkpM
uhc3CdNJ35yXuhfHVlaGIbhSauNat1jV8Hwel0iqeszHQp3XN0T8mL3e2/LSwdZswvBjfw/AQoqV
dJuDL0R8W4H91qeCG0fACekm6ar2ST+vB9EtvnRSaHAQj2wUK5uzSE6IhPpbvhtqSWz7gmD1ymEs
gSoVtQ+Qoil62X/RIfY6fJx2BHPzLO9nSAuXCTTs3sGjHz+4YPlpDzhJdLTOeFqKIXcHjzNo6SFQ
QG7ygaXM4DPl8RSyl4xgSc4u1rNeEYFjQYWhUmccOe05Xken+E9/aom1F/gIoOyJ+ZbqbOclCtl2
fc+3zrFnys7NkSk1kVXjFBdH/RmRwvmecRNYAcYkE1dXo0hSRvA6JPfShEKmMNViqUuOJ40x3Lrm
h5pa9uCFHdtgRtWTOHMg+YGQ7qZlhWNbGNfXpCX499rAoC5QHjnRrm07UpRsNnqyW5FlQSl/h+rU
Qx2hbg/HFWn0z+ia54y9iI6oc/f6vbPfMevXx2KkBSAcA+wdsnzu2/QKPQhWQMMxuhYiHUPyeBkB
oBRkfA/YwhTl1t4NcRIXVWaGu7wxW9pswwledu5NgSxP1VvLJt4x9Ez/AREoNs5mO/i4Ab0MG7G2
3DgGouONG8p2n67Gd8rX9IMmzeNAhDb6wdjP4q+/r+W9leHVzzuAE+gFA1YvtRkMwZhYyUgx3yfg
QzohJj1t1EawU5ZMEpLV6NpOF5QpXDvVsUaGXDxzjFuS0Tnw0+9Rr/4HOPcfi0vH0jiFZB+XhOen
S9nfCMFFRktF7E4YbbI1ScByW7Abb5EhpcqSsKBHS0mysyWq7XGOhM5HqRhV1FoLCbtdE0dLUXBu
fUT9uROmh3SjACZfpI5JPGChJ49oF9hxcbO6i0KE90MrnCMBfHozv+3AVmttU/ddCTD4Az3Pn3Ft
6Nk5cTXn0+dpbFFbIqZXUF2EJHr+Gk5O4g+F8BVO+ys8GsCFYUHVwsRq4JvMzf7sHP9K9axcV1Tf
DwfuWLToe5bi+lchDQ/rEW1P00g7TSmvv0+WsQMiP8CtHvXLgLXRUbsgz9utz3ZvKDGfTQFRupJO
fsyU6hE1UBkMiv9TCVmWVKWTKt/rWTKxPqF2mKA8CmSVpkzSx4/3AwXcDz3sGKtQLHTaEWTi/DiB
6WfjCYEWntnBXWwPbvY1RhZQOmgOXTpLdSrQTpSqzjb/2OW6qQftTra7STLSoCVypgDZiqRmgHkF
mfsWvpygv1ZO7F3lHMkE6U2s32G5bjyxTjytufvQUKmHeSj7t2syhL1vfXigoOrW59UZ2bvarXVD
VTrCvjTedmmye+hHz9iQtgDgLbcEczhjqJEXyyGZTrwk3Lo2nXnlakHoqq+dlVse0iTVUcIwlNoy
GgTViJ4FEeW7/pI9nt+4bquA/Y5A3yR6l1/GIRleCKjMxCgPin3YofJ2OpQKuWWEIfd3NdqctNcO
k5ygexZtw13XTDlC3BofexvGQee6moAv5aJA4t6n9vloqqWihg0B54HyLXvF11IBWv142tjMi5jW
qswDarf88paqpFnsjNkdPlQF8QjspXoFQyt5nAF2YHjbUMn9i+yVeCOMzx2D/OtX9/WOHpyavhMZ
VAHZcBY+bC+lS9pNp2o+pR9/w6rP7coWD4uBIIQqrO2e27OmCWCX4CcMdi7gUc769u31eg0DfVaL
zkQKE+DAUfPpFj5sGbjVOZJLqXjrAPoDSeGC73S2lZH4XbtXn3p6jSqYWwtRMol6eGBULyq6Bxu7
joPnntc6MTvdXuiNC+ZaB/q09SSEkjx2cwE3MzD867ggibGYeJ+miFjzcwlUvBOwSiZa45DYrvTT
j2yWM7e+vHchK6AArgV/q+vk1QAHbpwnOf2A5cHOZ7Pg1KfeJ0HjSmp0PCFYYHIjXZj5gJdi5jwK
l8VLWFglQ7gD6XcnxQuFQNxD9Myu6/teS/cdIGDzpVZ9/VSq8rJ7Ix3qf5Ax9Bdcb4zFIlsJLGJH
9piNV43r9x8g33YZl6TYf5iUXGGwsXtnYYlf/vM77RgGB+XlqD5BYZeNpqDA117GX28PyNiMZOrL
6AeAjCqZJKKVhuf7teqOpVAu72TpEBPhZZUnXCGVVyL32W86sUnNmFNIQs6oKCqT0xB7EzhxXHNu
74d7gI5MsABf/eoUbFeeFsZ8dILbyDa000N8e0WIhW9Fn1wU/+2xuhz5i8cbJxVLYJBff6KtAmj1
Ur8RjaKewPI/GrwDX9tToN8ABAE8asgpLdHWkUC8M6YtxX+ZCmozMSl2+wngQVt7rhz3a/TeMJw+
ThbJwYoqBa+QPutOgWd1ecnicdyAcdhxwOab1Wfxj3O8S4Sl0T18ur5Hwb+7A6D6ZSxJV2/EvPiN
MN20321WB3a3ltqY5RqItls1UyxKPAJhMjXOVSj24r4idARTxly8ZDBhgQixOH4UapyE4RCHcf+l
j8joyxw6rO4YP5H+5qDEwf64NNMvwdnahOWEEUYHFY/trJBNArL8f0t+vDI3dnCwMqp4bzY9i6Ua
/fgYrqJrkaORFdE/qDsS0hDvSN979ZhAIENjxY6qhUuwkFoH4UwZtwW+Vm3zEfEjs4hPtzMnuvfD
S1zAkQR2vigShkcIE3Lp+F5k7aEJ8lrIfgqp7Yk+3O9HaOBDYoIk5w1HqnqPazAyz7FXBuKJvBI2
QHxM/N9TFhCC50pwE0EFgMIT14Pwd+k36PLwvg+z9jNf1fdzo5mjXloUrznJ4xwq5zHjx7CUNn14
tkevtaqTPTkzeQSyttcPFGZcnCc0DWt9YH2/mQrQaIIsRMmmYlZEjSCyr9hiaPZADYsps72rOSwf
5t4AfyHKb4mp29UtOR0ap7FR4Wbt4PSkQ5/pVgIDienMINBkA9zXahMC2l/ZmCBQ8wBXWXnGv0oK
6vAKkTY+xdBniduASnELiDwVaZy8NkfLLT/s+rIf+keY4IuLJyBJsl6NvHDkpFEbvktC7PM1tqy2
uZaHHiWbctomlE3fjJAJJYYyblQREe0V+5WmE0saKz9Wea8lfHKQFk+sUCUuOrkOIkAJPhmgL+l4
e22R8QbNle8UUrWIVdmBs/yyjTF60o37Fddah20nSpCIeOBhe+bycPbXjnplCdkMiOCWiE4Zc1b2
OP4+1Hr8l7aBiHVPZ5ntVrNii2hIHMg6F7lI9cJIRtmRpumdywuY5ItSpaOosZ/Bz+fMnucb9W8b
6s0WrQi+auLBj6lRIXh4eWhCCfXLr0ryF1tZ6hJ3rppB1KD1+ul38QoWtgbtxdCOXpeFah8NFmPb
x/O8G2fLxTXTuGOYfETmCBhfEnU4zojecq3pVXN2+vP39hBrqdLX6TReZ/XLhAo7P5Eo81IAjtaH
0tIJIFRk4BDINaPq7H3uoRGbZbOtpa4I67A8bprhbHzD1J7W7nFYnAI0VM0jMj31VOeXVMBiSW+K
7zSS2tvEJEqtXru0EmYpdsQ4XU7LpFzD3YvYuEyKc75gjxSjfQa0X8+iUNdznYQ3mJup98kt6THq
2KAXKj+rFFzZc6MsedD/8Bemp6SJpJNexiRodu7lmtvQJJDPs/WA9ISYovet5KlvRv9e+03ykcgk
fzPIJjwqNz/qNUNPtMnqXVq7voifbLyHSe6uIwdAzq2Rw90lOHDn0TkS7XvZ0CpVHmX6eH2GDo4n
vkj886s2vf+SsBb9SJ6r7ejsW+HveN5lCSYZsiij+QB/AH5wnQporqvNrQ1Jqh0l6tYmdOSTzhdH
+eAk1UVr8VCbCHSPsawS7H83QWNya6+yB5s4TvcI+GST3vLs//RcFkAm7EW44q/twIS2bE/LVzmR
WsS5Lls6Nqbk7OHOlqjNHHabarx8BzXzBngRkxdwM5ybqa8rjLl0gI1FfGYkhIDHh4PUHinyqSK8
waqKMzlNzz96mvuFNqHfLfzokIaOERMgnVnvmWEURKvkeSEi7+tvraDQvV4Qo7E686FfDU+Ua96g
UdRXI04KPMGN0OnG6QnwS8dx/XDOpSWzEtOYjcPRRfWCbfEE6EJ+vyjkV80Xm250h8aPA67hhesi
6F0AVvp+KHEJeI8iCLcc0p9W6VRIN6qA4ww0QX0fcIfYndmy06qrbPvtyDuj2D1M57sKH1liEo6V
BksIJMSzdgKPiOByO2kKbvM1ZQXLxA36oiJd9D0duStgrCA2R+ITt5it37vV/tAA3iFhU61zL2Mc
0S8+8ekr6YV+qrE9toaJVGMhIZi/qOWNyDBZT3kUKRkoLCyUbGrjV9rxFNmxTXhQ0Hulxm20bxtq
QY9K6rXkkG78gtk/1G+DshijBztSI0FOrUmlWIyClfvjw/4CGEGuEIfWwQh9zL8RgeI4hU03gHYr
BWU5dJXZJU+hFTPCFoh3zLLLS+NlmLwyUlx9r+4H9Qo5fQqJwSBzb3A18W1V1JwLCH1STBw+XgA9
3C6V9t+wllv74zr6gSDbKpqFmYVEGb5FJdxCQPpClIazgpVHRma74TQfzmjbIDuXqQDUDpCLPgqy
tp47fq/Go4TL5TJiI++uU7uGMWo2VtGvFZGpJh8UnEC7lSY6tmsZ2VGcYTKqz5nsy+Q/WIQrRW5v
dkG9OZNfbl6/S9e2BCpUBVjag7hVBBNc8HZ2cbaGBomswsQa7AiGH7Eosy3Z0n/eu9do4KuR3G1q
iJ3XeH+720AplATIWo2tyExl9rKd7Bt+SdAh8BXhGnWQp254Nrp2LmV7g6FrcG7jNub2qCT2PyE6
wcjbYVwpNZxpXDWl7xgZbjsZRhofllkfBbiTd9eTl8By9ohQNtEtrUuanRZM7m/gU/uTBGjkc7Mp
/dsvmObd9uD+jef3f0+IHCZQ7vw2yhy4lJQhSq+/vOdgGCGw/p+R5Bep5Zq8Qp2Sf8BeXrnoEo3t
ZOcCMUXFqXlD05AvMC0u6lYQici5tNUASnTT4h/TILFkTG2L6CWiJpoS/JnT2Ot1dfI4FxtQqMX/
OxsZ13h8ISFICPGNPhRB0hbaYHL6SiQVikAEfERgVLKrP74CCTzT5gZ1FLhuwfLAF6Q3haYrVnEf
DFKq704Aqu9vbkeFmSb/p8HXp7dU6EYLS/fZC0NpVrZTJY5mbWWPg/BJ56jAnk35PC5FaaMeW5c3
7CvoTB6fYvtFr3Ci1pr2mAdDVqTlSgEtJxupjzL8y9K+VAmF6FeHGmLP5PDPIcHfdXiT5mjS7y+l
41wk5P0WdmBRsrmu9JIkReWIgVG2kf7KCAO87RtQZWEwPPfLXY0UMqI1h1vwsdWig2sXnq34PmsW
AYNb7bRIgZfgnFiv48rv5H+cxHeWiYN7nUubZ4o4f2NXBYAjLtp+rPMBxSsy/dLiezO3TgZQpUWl
Ys/w/lOjHjGRkI8XNUlLihl8YDqWfZd2fNUCLjMDw8vv3pKuc7RKTZeqHbbnSHYHlJdZC3yT7Pp/
xcujROSNjEFNT4xcmu2TfHncvJ6bvtw2nrypvtmdyjglaD4yWoHUK8NlJpsUtv+XOa4JSoVfIXAU
odZVRHC58DUXXLCo7Ns8W7jKsHrgscAGPpDaLvF7Nj223gC9c7gHLTvNbb/7DECS8EiyILi7GrHi
z02Qylc9YpnQlT4t3UvxCTNn+ZoXxG9AezuWyFctpeVNfF91SDf5QPafxsm33GRvy8IWFTa99+nu
4fDTit2ydIcInukMTVv9VeDyaqWdDzBu9EPwBTRHqqilxNqy/nWCOnCS3wo0damjIJK+zJ0OVi6h
Pj1F5tIxhFqvfd66sMFtTBc71gGuXu8K6KNYkdCnaVF6rSVIwcyZYDFlHU9F53UXZ0/bCeEDWPx4
CuZUdXLXFchNcF87lDFA8lfj331aYvAhuf01+uFgi4Lixb0/Q2uQvJOzOKMITF/x2CU2kRAWHYFs
ydH6RKhSLFsFlc2ubKBbCaZpcYa0ETvPbAxW/7OuEsVr7VP0GDKfa44RN4LTynTu510BtihdkOIq
kFB7PdAGMBDzBcAnSMbLr44tLzq7gD/NrWJw7NCTapu/rMmZY5EinYr2N9tAZ9ArK7k7y+sfo6r0
zVYp35FL9KTXKefp+O/D94yHH3hbtaWAk2hNjQomstNHYrQQZ4ClEOwBYgeP72fMrRoHuF8octTM
1ur4LaSqDRRmlpIBKEBAi/FEdLnHXvsAqjLTH0qXwLR7BTh4q9AIvEoS6dMonfO8jGVXNpuLpGTo
PdKVH46zxi8ewyRhi6fEbd6DsORrCgVvHhMwxFiaRokIWJzWAOB5fhPzDQaUhlrPgs8sRG3kuziL
+TbmFzkegUy6Uk2mRzI9Y3bzWDy+WLN7qbcDq3DjMvfHbZjtIHboO0ZPQMTHCjLqljxlywp1FHV4
cEClM84G9xRO3BDGDbfCP0eByz4E6yZSbhq9Sd1bvsU+3tPVohYypBXG59RUr9SpIrLGNQhmXaIe
JeHdfUzmr8FZ5wd/hXzPV/6gYbl4WuyYt/pawoKkJwHxZ5LR4kNzkg3PYN8ITblHnz8tybHFM+jm
0XlhXyUkBNJCnOtCCm5JQjHstdyLI4HqBv0nc7IyB3tajtdbkUfCh93hLsCUGnHxDDTpsZ4iRQba
EDswldXapuDFTCxU5QxNDGP/YUuBQHe+VaB7N2M/7Q69mGbhXfLkXB7nn8J0zZgyEVYVA0oq1Xn1
Fir7LLR5A2veZoxUdZA5/ZM3d0FRsHURehdMVIek/vaqAdr4U8qyzwiN7VtSIGC0Qk4ZW5f0ph8I
OkAAUaIDDut1Y+khPO/csoUjY2xLBGi+f0LutqbmAcVzpAuaba9ONLLhsRO8pY7PZZ5RVY3FD+FJ
VAyn+PjyOTkUDQtemudFCVBYtS0b8MiAKIXBQnAWe8YwT1zvSwrF5d02kxSj3mbegFh4kQ3NPrLi
sJW35VQK4ugHC6K++D/5Zm776MzZoui15sVeMcfWaRLAq8Id2tyMiLvftLIA8YVcuuxprDTwN2ZA
qLQIMr5nEm791rF/bgWMLkALokpHAzT2cc56+m5P8wu8wBIdIDOEAWp/DV0mHxDPTTrT31zqUCYE
nVAgSAtV+EAVwJc62Xg+eDdV3psIcxpxY4I6UNggnluCA3M3bsSkS36MUGrvf+fncJ7HMUTrp4u4
PgISyqZOxYbvIvPCGvqoflv0jRXod26q2DCqjX8SSv4suZn4uuyH4bJcMRh9qZq6q4+T5T9LD9ev
EJhqxa7KpKdj11/rIy/wUa0Y+BloEtIq5kXlR+B25mNNrt/OrGhUUJBuhVPl9IEWjMQeALtMM10D
L6p7/zsWDdV4yZOxb9nUJaSXw3dDqjnB8IgLzTbUv/M3+3pfgpB3dIL+3pBNaPVnC5B0cAaHrHQM
Ob/+v5oT7pz4Pjkj3BHxdb8fmfzVH0DuGjTzwvcjU8HyXBOAIdSkGeTq4Ap7u4D1rUf8cJSRSLc+
7PTmhiQiLTi12cDXX+jvNSkB37FkKJFiic4XF3TQDqOQFSeieBiusbGbU+Gsi5UcKQzNDIEyY5Ze
Ob2gF0pfbR68qkytNMq6aAWBSdR/IAJt03e0vjFfT80QpmJ7hr/Cm7LfTwAHpg+BN3H3h0zE5lHm
OjHUtXKVpaxqg6yrUvxPBJ+aPxfS+5uNzfsYNILCyDiH71dXZBF0MP0IBFKUluv4/2nGJPxZMEWS
tAcTnunhYYds8AD5a+hQanIL7AB9Hlsguf+yWsCxr/ybAPx58jh3BcrkcwpA+MBXFZ5vjNJLHIa4
fVAPfMlznkay8gd27FEBQA4f6Tv+uHxyVdQJMcN3jFZ5EjtdX82gfiqeM8D1qcoi1udVlRR+Xb3B
tdX52oOhwJIomm5WZYsDJG+OYAoFxQPmdRXuYwpfxS8K6A74QrEhGI7lx5SjlVkH5ad+SJZlz28k
AdqSeRagCBNJqPVTQY9fGAifmAQQdrKrewY026yLj2U1U5EOI+768Yw0+lC6ZylvzY9NhTwaZC91
vuPLlwrnWmlBk+nhXyfMIbm0A3WLHchPH+DJHV94pKWkhpSG2xv9ueVsw3mP37GePZDJEpBWeX/e
o7AsX6LPeAB5mtMXDdKVUhKfX4kSLWtCm933u/S4HlaPZYkk+bumllK6E88N5Pxb6eCN5T+ZuiFA
k5fYAxCCDArgr3ZGZGA6XMFD2Xy25cKeoLgY9Aez6ndoqK5Gpp8mlJQ6N18ymvRtNWHe6HcVHhr0
d2vjZ6z512gHeHF6VUxPjl601D4Q8v+zXTnrz58RBFo/C994Cy6petal8g/k4zjpNCofI8M0wImd
McgI3J3UMYqIMPiDf3fyZv1yO8QqxHalNw8S7XwSFuFzVO7qK/yym1gV85ypjjDRuOu/CjjfDyyA
BrQPSSTrx3tKwpJWtId8PgjW+erKHiEDW5k40WWQA7YAoa//pMT5+WrY+1Seq3dCG1cs9P/R842j
WIDdT9WSBwxUlfT94E70nVWQ6Ba/rLXwHAUm03XsyP8RlD7q1n/gG6oZdkQ0QJM32fzKrVWoP/Ew
GVul5qzFYrW6FJ3WmnpM0MRZFW6Iq6Q52YtJ+M0pf64T/MwMLCvx/wT1ZnNLPlS0YQdH8j5BLiw2
qDWtnXfwEiu0fpNaUOxirAKjSk7qE0+69Ai+Lm8sqoGZJ3AoI1J5vQRpeszl2vXJD4Yohg8gFlQ4
CJ9kgeE1CBaBqGVdJ7LToxqw0DHUNfbaiAnuGA4aWKCYubhFmtLdQ0clbW1RJ26S6Mk7uy6kV2UG
EOjHMy8i858iVF960IUJrEeZLrmA3kIIUxaytgtN3jrhTpebN/0lvynKpCSe/IFxfFsWv7w9uuvW
WFq0+azXKcuB5FTeYpk/pXWE4KJcHz4BhSvxvoHwkj42gnMTmiRVDg9j/qEwretVdNVspsXaHsTS
xNXResDrLzLtWoSlfDE3rEOUX6x4RrtPAKpjKVlQQWc/rsomNTaahkNt4DVbRkOCosfcI5wI9GFP
BWSddPqryGB2/Tl6CGTW+QFcI5WAgeahIvj0/Hnq9H08JAfs0szoAenEZf8XqQvrHYp22EMn4H/s
NCrHid8JS15QMWimvNvcQqtb/OETbd9Wlw35QnRav9AE/ccomRUsc8Gx1RuWCMig+oDekaOIlJ9L
J2dkoeabBgv463rfio80Aoqi5HiWSWdWAbTQSjAfn6hZSsUSK6ziDwZr4Ir55l3iQ1KIEq8aGMkE
hoASZhg7m17h3yMHyW5RTZNprHLf5iC5LqrCRtGx+WoeIQZ38XAuHrVolePrlIqcMVu829SKOHCl
8fvldXvO3QxFw5zi7fxbVAl+w9BB7rtAuAfJ1UeMCWVWlQMpVTqnJxvEZe3BAy8uDGlqKXFPafc7
Z/c3vrtJ0zs4Kf8QwYvDteZqh4xZJ1JzfvwVzO5EHJ8TJUBr9fZSw2iaOlHPuk1TjLEVAibXk1AN
pz4QyacZEFBvZX7ybL9F2HYo96khjMcL5QKXVpmskwPk3GFBfb4LZuX7fQhjrpVhkQa3iKiCfcKY
R86jHq+Culy/tw5bC9qdLEzqRLvkJ7up+T5ftCWy8QPKAT9QFNi0tmhZC3iFqYVbpp80i1DMUvaJ
jdmwMzzVyL+8ueOIdIP9p03TMBN2Z1BFI7vTTmv8DzNlSST9+LWU8XEi/yosuy5imhx1EFYyv3hL
gztus6q4N90YctfRVym+e7qENTjwChZNjUCT1Pua6OKCwj51JO5QQ2/9OIzLRDYyDt/8oWfr61PX
0dmE7/Hx5wppjh+gXPzjKTwhdQUVN3eSUESgJHd+tNfsb2rMteOLddT0ZK3KeRK9xZl3N8lpN5Wh
6qQeeEfP1z8vEe5tvNdOPSvh8/CbsJOnsc7yKGBRfOmZVGpoe4+/dVlHtE4WYqQYgYhV6lHVv++M
s0V2eNDrhGHctIuSfBNLJME8OeDS1PmLNDGTDaxuCq0XLLhJiPltj8HfS0fqcey0EExpMb3OranW
RVhMFCAf3rb2KCke0ZzXFm4bkVlXQtC271iJM8QaS+qgpb56fsjKoEzsxl1e2ZpYt+nod3DMhgdG
1Ktn/lnGiICHZbDUmmeeRaVTF1ps2ffx0fPTsrK3QKJL1JkkslGcrTF2j7rhetazf0xLL0Tqjc/7
q/4zVNwMNbyBYxPnjBPllpgWLn+A+eH9IpE1wTpxVzc6tAOB64DBs7gdbnyVd6WFJFhz7TBcHT6i
feQ9SqqVaWADe8sVpQBcXTau7zjeU1doC22MY/CksOklLCRhzazmhgNk9ON5MmOoWfhq0BEl18w1
7qIdnn/ju4Prk9fuEZmByMHT+QOUiUnjKjUK2xeLRaIVpTXsZ48wdgXZC4M6JxPhoknIhvoyQZmT
86eNT88UFEvDDUcw2ib1cPYstCkyyn+Dxb8BOFEGk4/Qo8h9ZRfZ9wIKkW5ojspro67KJY7n2kLv
E1M8eSujS6Z7w6yRfFIOm/Kwot45fUzWqUei3Sd1RmzY+1HapiNX+dbSloMxsq3/5kZAaU5YVdrJ
y9+VypwcisK/XZ60HUkhW1weXEVybUco8zMvcetJg4Df5GSt7ECepcnDj4MYuMCRseRgij2ynHnf
GRetzN7Xex79qLTnEtZxsROJKSEIXIT0bdePoPD3GhU3QJ0AsPMu2uYUKgW16qSyvhYZfw9rP8Qu
E7ZMYNXmKAHqcCw4eaxpfT/tZ0roYnseOI2C//jyzcbBG7siN1ynckMqUhI1Fl38gVeUs9HGoxc1
Af7k8xfIgD0oaKEStPJ4FfNewh1qcvBPTsBHfk/muF7PJDLr2arvOcOPSqTuwkXE90FaZgQUwv8s
K6xa/pSVGF0jGgGz8IckjZLIo7twjBRbb5wsxmBFxAyjZGY98dU0DQbJwuGsj+rCNQkVzLp6Z4qu
BUg+79034AD6tzZEP80HhhjrjGNmymJO0KqqyOf51Uy5qyV0UYY9kT4xB/qHKYeeGzotv6jBwllk
xDQVbdSvi/TvrL0u51UfsTdGGVebSgluMCr0XXJyPiM4r34dFQs+z20/2/mEloZfmjsUkVmgbF+e
mr68FWpupqdpD/geEJHKobwbUGclzffJue4kHq/ewWfZ4W0xTjhjPNwwKQpZ3fJtj8cV1f9ZwULA
QRlGu/oCgmmNSUxjbPgQnLrXLBfHKE4zIpFcbXbsg+BLgj27B3Rq3yE6CL6E9jz1eokc+TI9rIMT
pdCnuO9lQjCLrOvcNczdHTMMLPLqDCXT0pn9cihshxuE75y6Ct3nFuA9YfNLoJz5DEPzxzixEFvv
aqoPixSKxHHzmZHaf2Bvbmlprp3hQmz2/NMeNcCqRuV0NuglFGr/rFg80rorZFmYa5rUs1HUit3p
2c2iof/IDzJC11JeBxua2ugjjm0kLfDz23b6KDn8iM81AjdYT6Nr8Tk1XW9z3Oqw0D4yZkc1uMT2
+eDEqt8BPofyxxhHmjisOeJxkEJTuS2KPqlFK5lKA/PHVgcnrk8bcgnlm7WHK2Vo6Lm4GQzDmtGP
egiYbU8Hnx5H8Dki57Eb7kWRzizKI9otzNhEnBWVvCE/Mw7LnX+fkylqn4D0tL6p/HMoZsM1j4sp
h7rtkxXt6WqlMk3pt9mL0ZUt2vX/oC0LlwGTFr8eYp38J4W9r/Z9EQGQhVrHvQ1OJHnTYWEK/mkf
jvsQM/fWnf5sTRY2H95FqMahjiQrHqJpOi0tLwWFDMQ4TXJyYyhLBdsIQED9ZIs8UGzhgonymZVl
ZbISwf8J/Muwjdcq2V0orxEDw/qcoIMyKcle3Xvcz+zeUjyGl9gxAnJHD+tfoTwKvmF/Ep3Vk6JL
ceMKwUg390wYK9HCHVC+kl3Fjb4RsgzQIugmzlTa7G2iiv4PdomIQIX68+EczCWCOx0L2HUgNYWZ
/aAie8awQxorexs5uFsPS+rp78bzYf6WlMaI6QSnWQlCNuwgYwRX53AmJhZ+2fUfHXlISQJemkJ8
Pg60y3wqRsAlfxI92uGdD8wVHDwOoAsoAhewEuDkHHOtjmFGVSvMBNua6O4zC+b/x75AddGRMdJA
+REPf/dEGHCkxsMdE5mr0f0+RiEYm/XhzLGfYMimnaX3RhiavwV3fHruKlQsksoLO2KOQL/RoROt
1MN2Kpr7ZE1p2oO4QwMiovKElsS5Fb9eiZ52IIYgVUBH8TRNktV0L6xN8lywfOBX
/cXjPA2Dx6Q=
`protect end_protected
| gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@b@f@m_@a@h@b@s@l@a@v@e@e@x@t/_primary.vhd | 3 | 1635 | library verilog;
use verilog.vl_types.all;
entity MSS_BFM_AHBSLAVEEXT is
generic(
AWIDTH : integer := 10;
DEPTH : integer := 256;
EXT_SIZE : integer := 2;
INITFILE : string := " ";
ID : integer := 0;
ENFUNC : integer := 0;
ENFIFO : integer := 0;
TPD : integer := 1;
DEBUG : integer := 1;
NAME : string := ""
);
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
HSEL : in vl_logic;
HWRITE : in vl_logic;
HADDR : in vl_logic_vector;
HWDATA : in vl_logic_vector(31 downto 0);
HRDATA : out vl_logic_vector(31 downto 0);
HREADYIN : in vl_logic;
HREADYOUT : out vl_logic;
HTRANS : in vl_logic_vector(1 downto 0);
HSIZE : in vl_logic_vector(2 downto 0);
HBURST : in vl_logic_vector(2 downto 0);
HMASTLOCK : in vl_logic;
HPROT : in vl_logic_vector(3 downto 0);
HRESP : out vl_logic;
EXT_EN : in vl_logic;
EXT_WR : in vl_logic;
EXT_RD : in vl_logic;
EXT_ADDR : in vl_logic_vector;
EXT_DATA : inout vl_logic_vector(31 downto 0);
TXREADY : out vl_logic;
RXREADY : out vl_logic
);
end MSS_BFM_AHBSLAVEEXT;
| gpl-3.0 |
julioamerico/prj_crc_ip | src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/drive_current_inputs/_primary.vhd | 3 | 391 | library verilog;
use verilog.vl_types.all;
entity drive_current_inputs is
port(
current_vect : in vl_logic_vector(63 downto 0);
resistor_vect : in vl_logic_vector(63 downto 0);
temp_vect : in vl_logic_vector(63 downto 0);
ac : out vl_logic;
at : out vl_logic
);
end drive_current_inputs;
| gpl-3.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/dc_ss_fwft.vhd | 9 | 8986 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
pD5g5IL78/II1Ddkj6G/022UqTQlP0QKodXTLcH3WjUVB8ldXpgPYbNKQS11Pz1wwN0xFLjZgfyd
kTPstFYRtw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
XhSHrYc6YR2b1FmhZwZoA63xBZmoRHLlaVmmZx2N83Fome1QS9gV8BYEZ8E5GrFm7kujMeNBN+4N
7j+jCfsq3qpgmaO9o7zUfRKyWMghbiHc+rB9ZWh4ScsNSjgXNAGpkQmmD7aSosBogjcSZnENaVDL
yUj0a0R29dLDmyjahqo=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
0NVT5GGMgCCqcu0tzpFJOMSgoGbB/q46aSS0mvJqtiikX/gA7wV2jfLdgIq3+ABTfa46QYi99Ai5
AIeI+z8leNX2TAOjmc97ZWxdgfpEZhLKxMOcn5+hVVFfxShKc+1iILaXddWAOv00Wh8xkOn/KSJf
W3rPLstgiH4egMgsLwHheWeZ/pGhcy9WgI6emo+R5Me5NMGNb4+83eSC6pZkqGL1Z/zAbtq0NdKG
qUk2gVxtnCrSCBOaHdHfBxnDZcUhvZ5xumHON+R9ktD+KGncVl3fv/nQixNnI+5eUlHR5jt8LWkv
5NzhO6OS3+utriOYdr7rETSFK6cuGIu5ecg0hg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Kfe0qYfDcey0z70Ier/Uwp0K9jkRg23GJOzrgNiPHCI1cbT2ln+HF4w8NVk9IjghY4ZxZhJLOL3C
kGFsG5LJ7vfUxNoiWPzI9e4RGSOUcgQTMFfSs2m4aG/qJyp/sWmeQ8zHJub2Tee8XDYhOJI/Ez7S
tDhtnEAxP1cy7yGAxms=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
jbe7GWWTyc2lFuGmaWnib6gg7R/lKatMuVRsW1Zl4XGJFJ8KwwmC0PaN8Dgdw3G4rCIOLakfsf1x
vBaUoZPcjSHJHcTz0guoiL8eQCbpbfKiGX2GP/Wt7HUk9Qn5Rah1xfbP5KtiQ0cL24Qnr+pBo/Kp
t/Sszhda0q+LyVyF8ZKgyjkOlQJSHdxraU51X60NHwCvzUGfrIjiaOxqvRgl+UlxvydajllCIvSK
7dtHfCaomCYu6dVQQIE64K8xYNTpXR2DD7cevYmUJgR1TbPDgUKO7xw5MLQ6R57/2Vby8FGhnBc0
TeSwtn9sE/lgTU72YESxLGgR783RJvWC0TjzZg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4912)
`protect data_block
dUQhekVwqS5hcDF78Nftl3BmSxy/2h0XyCR0eizHzk5NEAgnWG0UGD64ZkJ8CqpgwmicGAGPKR38
c7ct8vfwwvHAjohhLX6kJw7xpSRBR9cpp2BzxAhRPeJDG/lucBNSJ6h1UENQll9r5MqrzEP5vzh+
RYiKu5qIhSOtVqjF2HZp7ACsaushzY7bjFRC8Km/kM8qWGwud0IISoJ8thXgO891lLvSW8rAGUxk
gdL9OB0RY1/5Pnlp3bEVx+cxQISKnj7NQyX8yXNd9xzgUbC/ZdLLCV9tGq/04s8wsrM3x3mXLndA
j3egwtJnwOcL+JsZx5TwtS9soY6foKQCUSEP7bKCJbausbB61CyNtVgNeSpm+7Iu8hkvX//kJ9pY
6DlTz4fKR2wXiN516XE5wUGJsS9ONj1+mx5mNpN/nkISBP4bGVl6X1PXKAjkZ7MKOhd13O5ZUrix
bRkVtj7gFjtI1cPsLTmdcSg+FmiJKR6Ko3+bkAdvy/hmKIxi0BaXapUMB3YaRyNMeAb5IlbKLdJz
9gQwrjoIHLUxd8/8JgvF9tF8SdZxdStryhkjD8Z1MBKkqFb+4F0xId4InuhunsgyFnCGL24ZouNi
XfcGfzH85MEuTD140995fS7ON7pbVUS7WHZLcC1/BdQqawO0dul5AyBsKxt4D+K+1F19sNC7KCuB
aCt8xG1Xkto17g8OPTbf/mtZw0v5lJYakh8DWB1R9TWaHhp7NvybaML6ccC8C8QQ0aR9bk+5/YzK
jNOYkgYJLasSjKyoCxNqlMad0ZoQ50h3gRgTV9QI8zbOaFgcnkHhhRdTzFwJuW0qZqG4zkp/YBw4
mSWR3rku0TcirX1s4MltOmVUblmXdEimzkgQCnCEGx9o+YxKmQNm1Ssr9CJDF2RvvXRsLs3Fi4Wv
Vg4FCVJQKbbth10qDhGziErSVfXSpPmc/Vhoa6AZZ2GA36/oHfPr8zb2ePz6AYAcM9z9k1SE+mBc
MW/hjNApy13/8m6khc89Usp4zunmbUd/7YKsFJRcWWL7sFrHtQNDifCQycTk1TbQvSNY2Fw4JDKZ
cjw9Hg6cndw2NDYArx/mqjFdzd8nxF45TYi3QewDC/P7s49XZI/qP+wenjhzjcmOaN0S9VlIjZBI
ql2nKNvFA6EM+fYl3Fu3dK9au+Jrictbxo0oUkmD31gK0n3eXTbCV9nqSMqvRa1nKDLw5zFFK5mI
PkQ16podvEOtMEhCrPFaRMfRPO64qJdB6E7Ta9qWKY1QuQw3MuH78IfgCxzvNe26b0wiDzZf935E
OBOy3CFKIbygmcyaehs0MPT3TEO4BfZWNc2i5reeKM7IIyjRudbC66XuLMPxC8XYciyHLRh9mwXB
0hMhKrzewKYZ3RAL/CGEts3tXTmkg4Te4iOKlH7eAGdATjQqw5bvoxMFICv0XvvCt8lMgxyNy4pm
neheWlC/oH9oWU6vUtTkPONx9Q9cakO7p7XEWvYEk+CRa6n9B9w/2FsxaUhRDx4/MuPyjsX8koY8
WA0/ddS3wWNZlZ+NWmpI0MB6nWn0+87xa7wkP4d/tqGz1k5w4MOmRLYlYkGQjHiiBn6oVzxlfiba
cAeFZGJAMOwgzAXfQ7APhKKP7Xj5uspMclL41Vf79o9tnZUHFAE/YiwOvXqXSrNTyF9ieB4zTxDU
WOolATFbgj+KS+0H9/8NH4moYRpXVQ/d5fAGmGD4ZPkLbJ4e2AHQG18nsVgKey6FInFC276W9it1
tSENmDVj0J0r6xHjLRv4ZYljga2+vG45QjQUxWCxFKXX4tNtm+mhUkYJFKKJH20+V1z4AoMk2nGs
t9hD94EBZxDy9RHV89qqFY2mJ5y1UU+pxNTrbz1+wje+qUspZFKPlLOnL0YCZbJM9fb3v2b8ZTqz
Hn3AIYw5PT8MZbHGg5xQCk1m6e5TNrg109Gsu0gyN+p0uwkABBle4o+OQxl323RYJ9XkTPSd715R
HfsCVBxKivm5VbP4Orc6MSBGDEFD+PA0R9h0VREO2URkk4zEIoOEuUDg+o8mLdHufU47UlnEnigW
M8IHDkqkF+FqCW29Ivu55ztsWUbeR5fcKbLftj98ePzBLFY92uu+OJTGSEDK22TcZM4kFqNbn149
5tYMkZNwaV6AtPGC2O7tVRlWBSjHEkdbvNqdR+UliIKVYl2RURQ/TXGypGM9LLDkNZFe+YnFdRSX
m6/yjEK48yRDccDG/bKZKCI36VOzDpgOPKfv2ck3Wftzjz9O3g6/4giLx+YpTkfwXNXEz7zLBJUV
awcA3uOLHPGUWb4DWUuXFwMgih/54Kw3lo+gxtMJe75+NNy7C9cg+L+bQ6n/OHOKxTqlgyq+PCiG
t7+jSYKkRGJIV4vAIvlASfQgBVlaEJg8jf6yuLVtdbhbt/Mmx0hbclD8KNzq/ky/jBYVpvds/DSg
g4LclNOyeQHFMhbYucAMPs/7Y9GNszdpBUNPcJL/YzdOcgKbTgDms3HczyuDqxvVJx9Aw4YVs37G
WuW90BSWR1A3yvT7qj+kWVEsz6Ei8DyPTu5YVcfX2MiMQLpC9Vf66foY0Cme0bE04ooX9xUtYDEa
obZgVC326aiDLhK4tip4djaLx6b4kh/sfmEIcOlhd5WATc5umBXcWY8DcnFop0zyZ5z8QMznhqF9
E7IesNv++mnrQt8/96ZKRHy7dnZ6drSqFCipH5RuRUqko7yWjMwcJRxTspO7+2+HnWbTYVqHGCHj
8wZUiXZkyEkn5KVqLEED5W7HnrTMXjxK7koiu/34wlwg6c65ySEZnfJjh+N6UBPWVPG5d6yz/1Wi
8oQWxwWeUeSVg0mjbnk9wKhBcVI+HcUr8WdlGQz7/naPmgd+1IPReeScJKkUupMxz71ztwahZOB+
bWWjFYXMbJdaVmJhTBw0q1JyG8O+eX3zN7C2XzXFzOj7aQ0iO2y39YgqkGffexO9lBHWGBx5jRcH
Us5VLWM0XXmrPRTGeJckojhC4/+Em2/xJ/YlLPH08ywWEmgxxASTLgfmAw5v98Ybrh1gKJxsKus0
0GzeLpcXB9PKc4Xz3XiBHb9iawfThnVkmDP1qeX62YvxsTMS58/2ZtWvOx7xr/gLQ9jdgrPqcBuM
jLUQNjyY6Cwc/OfJ/3fH0L19K5XcLcU9KVdKqBPerWW71Xb8Iia53FGppQhJJBxvE0JFazBmYzV0
KsftOt/b5yFiHvGdpmjnY+nMif+L0HS1IPIZrymFcgJgG7o+ae+EiAQPr+7FBtcgvAGgPa63uWQo
lhFQSEQDQ9ubq4ulwJDq2GVUxzcAnDYdG+vTBxsozpJKhiV/z7pLKq5HB7xVdg3OVyAOB+WahHWc
fb+rA14Hw3k7eWUTJAoHkKmeirA0boj3pdnroCXVutOv0jK/EhPcDbTO3YFJ2UfahKNb9KfceJy2
4/fGC7sZX/3+VkiKWVpvuVg/e0ZhHYeqQR93yaASbEBZ7MFbSu0dwpv0iXh/tLDezHOpgx0JjqO0
Chc6XzUrWcFIYP7t0/X62weITzn/YFFkgbIu4Sbz22i5fVSHa9lQOEKz4TmgM0H9ChTZAzJiHteh
PBf1mDgVx7IP360S0JG6GZZcgGNhm7nCU4RsBNqBBv2CGrwMntvPw4jsMWdgpNZHEYwVQFeof3aQ
4poKfOn5/aOSKvZ3dhhc7L3vHir+jFaxEHZEsUUdAq9XOuQh8s2mWAouh9v62YcEA+LKShw3F9X+
1B1PduzoEiv18PALm7DoZ4C77tUyTepSnAkOwJ1sfTobr4aqC7lOhgNz+WH1GPbs3MsISAEIj4fR
V+wLHi+r8ejEdlzn3c3WnvU6UEm/nuQJ24op2StBGW9nKuDWkJ8eVCVR+duZiQ5ryNI1Au0fdFNT
rg0JSlPra1Qe7hhkZ3uEevXkeuEwokLdB2FARfPnuXXWUSVceZo7MYwC7VlccqhEZOBj5U+eyzmD
kVI6M9R4xB7I6wkym4ykn7g51brtWZ3bCdM1Jal7W+GDP25QgYTE69lP9w3LF06z9mCxmsKQCZ/0
2qAxhtyWqGRiPRSJmQoEbzJLVDSeORKpcURU/OBKgLg4JWt7qI7vWfFgRJl6+2f4qBzpdEksdiDO
u975/v36A6QEr9axGnbg28pyScuQcMqRwaxt5QfJnG2Q6zaFbtg48Eov3WXHj2CYh1Vdd2h9kHpM
cDN2KgRsX/8e69mQ7YzYRo4PKRkThQVer3jGWHyISZuE1VvpheuTc+8RanwljZ3PqHTzEs/29Dqu
5NtGZB5ZEs2qMzjgcLE96F20UdAwju7ufI7srpWC2Zd7egtsHGpWvZardNKJ1ina4dxuOc27/ZAd
hDvSyiDSBOf2yHX7uP8zrnL60zKlgSdggt5F13YPz3Fb9mo6w9M2ENIQ3fJO35njFrEi0YkxYCdn
JgBSHUK0bGmfDHCCYd1rSTSmnwzsOfj8cWciMmJXjkgUjqvT5+hlLVbj91ugIL68uVk2J5EeLRdo
sygIc0EXLGTbeHUVWg9g49F8HeHXJdxkbWBysSpwIDs2WPG4VLCi25JpYwUzP+7zzkzcmg6Ux03z
Zo0ydfpRrzzWYRSH8hfAxwj0ZOwlJd5rL7UWSICrIBsASLkWVhluCkbU4L8NUlz/vwUZTNJX7qmk
YeIYIJu29OQtm9PoF1Y7s/J6QY2D0O1oC5j3R2hczCCZ8e76yKZXv3+ICMT5mgUzD3fGZ+LmWzL+
aSsydVpjee0v5/HyMdCoyMAdQoKWgW/ZFi51JvXrD9DvYuuTIkXXanIKhGdD+FddpqOJp46rWo1A
XMXt4PAYPp5tLHcf8OL3f/cy4C5WNGj7sEt3iQ6jQEPPSYEjloZO7msZQVhXwqSZXi8CLy1/wy6s
odZD07UWkeAE+FTntS/R3pfyCJsRnJSEj0Yv3gvUcjZ3BgN+NsFh413luM3x+DvQ3bpFpyphNwxL
G1b68BYwlTIILoNeS57aOR2436J/pkTkKoTB6/pQpmkRoNm2/AjoC/sOWUWVPAgxGG+ZVlOtTpjm
TTtWTvCzPYXrsyQbT4aVFj/PCIv5Y/DNOIy6X+/lrzn/KD5//yi9jY1xs1n1ouIfz39aIUixl8Xf
Mm9vs1Rq2jqkyn6JNhUwABSww4ghKMTR2HymTjc/iCgGAqxZXMrbRzpo3tPOjulYI75GU/24R0Lm
XDF6HXNt9BSYlITOxGFpuBYQP5jvWTcL+1vLfvk007ktLjsz5spwPYjaBX8ADM6EagQJAX9Q987p
X64lpPdTa+J9Yc0lDHrpTzdST6t/IXDLb3FJK5rGong//JvMxT6mj6LlHAu70mxIHg1x+o2NPkPz
28NjHNSoCNRVG3SGh0Ys80qKXMHLN7qNcKGoi9yXSqZHvJuqfdoJti//6Vn2xqQxQPfF09JCq8l0
C3IL6XdNjSieN4LJlrfXimIuBwqw1e3Vlnd4P6oVOmwMpzKzdJwnb79q0NcX0Gh8YqI75zEhoM4I
dCDtCGn8094x60APS1NSZsjbB6QBZ5uqr/gL11lIDaav/RV8XnYcE9uwgOKSbci8DacVlgAzWpul
LanESQksjD69qgSLctCR8JuQOs6Fz9vqohXYLxXXsUpF1rQ6AchK9X8rQI7GpewRgJRTqxVClTLj
K3KEukrkjD1wlMS5Mx7DvSO8rQMKOqVDrFc8JKz8qH3gDKa6j02YxXcC2jFQMOE2l3XwNZkt17Go
s6Ks7n/RJtLMz5ND0wQ3uqGiBLya2doWbRqMTHCGiUlpwE+f7X3cH9hz9rQ9pTkpDsdnBYMVtoKN
FtGgJC5Rtqu61mdyZvlyF5rOcm8XCuyjoLj4w4a8lgHT7veka72ruLWWphu009936T04EedLbR7U
fj81VXhpDPjRYSOAEC1ukPLU+9skScmF+fOIcRe67SyHO2yWqWoZhbrY0AYcZOH/e31IjJ5pk4lm
Fuh/BTMMMqjF308sl3EG+v/U1t3jLtTRXPXRXGRlYmMD53nr4EGMp9Ia/xEuiOwOFbf+5AP52xTG
NWplroXU+7oieCnD/1RFTNj0RaSFmhXbK2gQNFh6V8XLlPcuHEDJaON+HUGfD12fFz8ivO10BxVK
MosgKJ2nCuFCtVC9D50qkPArtUyACHSqZjzQaCHjgM51I/K3iO4cqWjvKWcz64LJ9d3Dy/VIDiJQ
f+f1FkuC07B0NuHwnh/O3BdLtS63BnwZbYMhjD41aLpvi0lrLr1ZvLYqprjPNkOZfWCW6sBNrI/0
e24e/P48On7ApzD92dWdDTEc9Z/SRBHXePYQcp5vX7cXvtTMPWKgK+xSatPZ5ucV/9oDDCGIV3vG
wwzPF/k5gvAAAxKiimdG1nKRZsVVKSL1WX02fo/+cTGhZYCX2x+GYmmSWsW64/VBnKcWBcGJZ5d5
jOXbmwbgs/wjyEJR/GksxnUi+jT1SLLthqECGIrLldVn7aQaTQyPhm47T/kFV1l9+u6YejB9/LBo
690SJqfMvoFsqy5PvD3mSmArhj/SyboxLWRlIjpre/2+dd54Dm2vXwrU9axZuePclYBq+IQAPiGi
Nlt/QYP+n9Lzkg==
`protect end_protected
| gpl-3.0 |
amerryfellow/dlx | basics/sgnext.vhd | 1 | 474 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SGNEXT is
generic (
INBITS: integer;
OUTBITS: integer
);
port(
DIN : in std_logic_vector (INBITS-1 downto 0);
DOUT : out std_logic_vector (OUTBITS-1 downto 0)
);
end SGNEXT;
architecture RTL of SGNEXT is
signal addon : std_logic_vector(OUTBITS-INBITS-1 downto 0);
begin
addon <= (others => '1') when ( DIN(INBITS-1) = '1' ) else (others => '0');
DOUT <= addon & DIN;
end RTL;
| gpl-3.0 |
amerryfellow/dlx | basics/nor2to1.vhd | 1 | 270 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nor2to1 is
port (
A: in std_logic;
B: in std_logic;
Z: out std_logic
);
end nor2to1;
architecture behavioral of nor2to1 is
begin
Z <= A nor B;
end behavioral; | gpl-3.0 |
amerryfellow/dlx | cu/testbench.vhd | 1 | 3028 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.cu.all;
entity cu_test is
end cu_test;
architecture TEST of cu_test is
component CU_UP is
port (
-- Inputs
Clk : in std_logic; -- Clock
Rst : in std_logic; -- Reset:Active-Low
IR : in std_logic_vector(31 downto 0);
JMP_PREDICT : in std_logic; -- Jump Prediction
JMP_REAL : in std_logic; -- Jump real condition
ICACHE_STALL: in std_logic; -- The WRF is busy
WRF_STALL: in std_logic; -- The WRF is busy
-- Outputs
MUXBOOT_CTR: out std_logic;
PIPEREG1_ENABLE: out std_logic;
MUXRD_CTR: out std_logic;
WRF_ENABLE: out std_logic;
WRF_CALL: out std_logic;
WRF_RET: out std_logic;
WRF_RS1_ENABLE: out std_logic;
WRF_RS2_ENABLE: out std_logic;
WRF_RD_ENABLE: out std_logic;
WRF_MEM_BUS: out std_logic;
WRF_MEM_CTR: out std_logic;
PIPEREG2_ENABLE: out std_logic;
MUXA_CTR: out std_logic;
MUXB_CTR: out std_logic;
ALU_FUNC: out std_logic_vector(1 downto 0);
PIPEREG3_ENABLE: out std_logic;
MUXC_CTR: out std_logic;
MEMORY_ENABLE: out std_logic;
MEMORY_RNOTW: out std_logic;
PIPEREG4_ENABLE: out std_logic;
MUXWB_CTR: out std_logic
);
end component;
-- Inputs
signal Clk : std_logic := '0'; -- Clock
signal Rst : std_logic; -- Reset:Active-Low
signal IR : std_logic_vector(31 downto 0);
signal JMP_PREDICT : std_logic; -- Jump Prediction
signal JMP_REAL : std_logic; -- Jump real condition
signal ICACHE_STALL: std_logic; -- Instruction cache stall
signal WRF_STALL: std_logic; -- The WRF is busy
-- Outputs
signal MUXBOOT_CTR: std_logic;
signal PIPEREG1_ENABLE: std_logic;
signal MUXRD_CTR: std_logic;
signal WRF_ENABLE: std_logic;
signal WRF_CALL: std_logic;
signal WRF_RET: std_logic;
signal WRF_RS1_ENABLE: std_logic;
signal WRF_RS2_ENABLE: std_logic;
signal WRF_RD_ENABLE: std_logic;
signal WRF_MEM_BUS: std_logic;
signal WRF_MEM_CTR: std_logic;
signal PIPEREG2_ENABLE: std_logic;
signal MUXA_CTR: std_logic;
signal MUXB_CTR: std_logic;
signal ALU_FUNC: std_logic_vector(1 downto 0);
signal PIPEREG3_ENABLE: std_logic;
signal MUXC_CTR: std_logic;
signal MEMORY_ENABLE: std_logic;
signal MEMORY_RNOTW: std_logic;
signal PIPEREG4_ENABLE: std_logic;
signal MUXWB_CTR: std_logic;
begin
-- instance of DLX
dut: CU_UP
port map (Clk, Rst, IR, JMP_PREDICT, JMP_REAL, ICACHE_STALL, WRF_STALL, MUXBOOT_CTR, PIPEREG1_ENABLE, MUXRD_CTR, WRF_ENABLE, WRF_CALL, WRF_RET, WRF_RS1_ENABLE, WRF_RS2_ENABLE, WRF_RD_ENABLE, WRF_MEM_BUS, WRF_MEM_CTR, PIPEREG2_ENABLE, MUXA_CTR, MUXB_CTR ,ALU_FUNC, PIPEREG3_ENABLE, MUXC_CTR,MEMORY_ENABLE, MEMORY_RNOTW, PIPEREG4_ENABLE ,MUXWB_CTR);
Clk <= not Clk after 10 ns;
Rst <= '0', '1' after 5 ns;
CONTROL: process(Clk)
begin
IR <= ITYPE_ADD & "00000000000000000000000000";
end process;
end test;
| gpl-3.0 |
amerryfellow/dlx | basics/fulladder.vhd | 1 | 386 | library ieee;
use ieee.std_logic_1164.all;
entity FULLADDER is
port (
A: in std_logic;
B: in std_logic;
Ci: in std_logic;
S: out std_logic;
Co: out std_logic
);
end FULLADDER;
-- Architectures
architecture BEHAVIORAL of FULLADDER is
begin
S <= A xor B xor Ci;
Co <= (A and B) or (B and Ci) or (A and Ci);
end BEHAVIORAL;
-- Configurations
| gpl-3.0 |
amerryfellow/dlx | alu/multiplier/testbench.vhd | 1 | 1213 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use WORK.constants.all;
entity MULTIPLIER_tb is
end MULTIPLIER_tb;
architecture TEST of MULTIPLIER_tb is
constant NBIT : integer := 16; -- :=8 --:=16
-- input
signal A_mp_i : std_logic_vector(NBIT-1 downto 0) := (others => '0');
signal B_mp_i : std_logic_vector(NBIT-1 downto 0) := (others => '0');
-- output
signal Y_mp_i : std_logic_vector(2*NBIT-1 downto 0);
-- MUL component declaration
--
--
component BOOTHMUL
generic(N:integer:=NBIT);
port(A:in std_logic_vector(N-1 downto 0);
B:in std_logic_vector(N-1 downto 0);
P:out std_logic_vector(2*N-1 downto 0)
);
end component;
begin
-- MUL instantiation
--
--
UNIT:BOOTHMUL
generic map(NBIT)
port map(A_mp_i,B_mp_i,Y_mp_i);
-- PROCESS FOR TESTING TEST - COMLETE CYCLE ---------
test: process
begin
-- cycle for operand A
NumROW : for i in 0 to 2**(NBIT)-1 loop
-- cycle for operand B
NumCOL : for i in 0 to 2**(NBIT)-1 loop
wait for 10 ns;
B_mp_i <= B_mp_i + '1';
end loop NumCOL ;
A_mp_i <= A_mp_i + '1';
end loop NumROW ;
wait;
end process test;
end TEST;
| gpl-3.0 |
amerryfellow/dlx | rwcache/testbench.vhd | 1 | 3545 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use std.textio.all;
use work.RWCACHE_PKG.all;
entity TBCACHE is
end TBCACHE;
architecture TB_1 of TBCACHE is
component RWCACHE is
port (
CLK : in std_logic;
RST : in std_logic; -- active high
ENABLE : in std_logic;
READNOTWRITE : in std_logic;
ADDRESS : in std_logic_vector(DATA_SIZE - 1 downto 0);
INOUT_DATA : inout std_logic_vector(DATA_SIZE - 1 downto 0);
STALL : out std_logic;
RAM_ISSUE : out std_logic;
RAM_READNOTWRITE : out std_logic;
RAM_ADDRESS : out std_logic_vector(DATA_SIZE - 1 downto 0);
RAM_DATA : inout std_logic_vector(2*DATA_SIZE - 1 downto 0);
RAM_READY : in std_logic
);
end component;
component ROMEM is
generic (
ENTRIES : integer := 48;
WORD_SIZE : integer := 32
);
port (
CLK : in std_logic;
RST : in std_logic;
ADDRESS : in std_logic_vector(WORD_SIZE - 1 downto 0);
ENABLE : in std_logic;
DATA_READY : out std_logic;
DATA : inout std_logic_vector(2*WORD_SIZE - 1 downto 0)
);
end component;
signal CLK : std_logic := '0';
signal RST : std_logic; -- active high
signal ENABLE : std_logic;
signal READNOTWRITE : std_logic;
signal ADDRESS : std_logic_vector(DATA_SIZE - 1 downto 0);
signal INOUT_DATA,INOUT_DATA_T : std_logic_vector(DATA_SIZE - 1 downto 0);
signal STALL : std_logic;
signal RAM_ISSUE : std_logic;
signal RAM_READNOTWRITE : std_logic;
signal RAM_ADDRESS : std_logic_vector(DATA_SIZE - 1 downto 0);
signal RAM_DATA : std_logic_vector(2*DATA_SIZE - 1 downto 0);
signal RAM_READY : std_logic;
begin
RST <= '1' , '0' after 1 ns;
--instr_from_m <= X"0001000F0001000A" after 25 ns;
--mem_busy <= '1' after 20 ns, '0' after 30 ns;
--pc <= X"00000002";--X"00000003" after 40 ns,X"00000004" after 60 ns,X"00000005" after 80 ns;
ENABLE <= '1';--,'0' after 20 ns,'1' after 30 ns,'0' after 40 ns,'1' after 50 ns,'0' after 60 ns, '1' after 70 ns;
p_clock: process (CLK)
begin -- process p_clock
CLK <= not(CLK) after 10 ns;
end process p_clock;
pc_ref:process
begin
READNOTWRITE <= '1';
ADDRESS <= X"00000002";
-- INOUT_DATA <= (others => 'Z');
wait until STALL = '0' and clk'event and clk='1';
ADDRESS <= X"00000003";
wait until STALL = '0' and clk'event and clk='1';
ADDRESS <= X"00000004";
wait until STALL = '0' and clk'event and clk='1';
ADDRESS <= X"00000005";
wait until STALL = '0' and clk'event and clk='1';
READNOTWRITE <= '0';
ADDRESS <= X"00000002";
INOUT_DATA <= X"AABBCCDD";
wait until STALL = '0' and clk'event and clk='1';
-- INOUT_DATA <= (others => 'Z');
READNOTWRITE <= '1';
ADDRESS <= X"00000003";
wait until STALL = '0' and clk'event and clk='1';
ADDRESS <= X"00000002";
wait until STALL = '0' and clk'event and clk='1';
READNOTWRITE <= '0';
ADDRESS <= X"00000003";
INOUT_DATA <= X"FFEEFFEE";
wait until STALL = '0' and clk'event and clk='1';
-- INOUT_DATA <= (others => 'Z');
READNOTWRITE <= '1';
ADDRESS <= X"00000002";
wait until STALL = '0' and clk'event and clk='1';
ADDRESS <= X"00000003";
end process pc_ref;
INOUT_DATA_T <= INOUT_DATA WHEN READNOTWRITE = '0' else (others=>'Z');
IRAM_G : ROMEM port map(CLK, RST, RAM_ADDRESS, RAM_ISSUE, RAM_READY, RAM_DATA);
IC_MEM_G : RWCACHE port map (CLK, RST, ENABLE, READNOTWRITE, ADDRESS, INOUT_DATA_T, STALL, RAM_ISSUE, RAM_READNOTWRITE, RAM_ADDRESS, RAM_DATA, RAM_READY);
end TB_1;
| gpl-3.0 |
amerryfellow/dlx | packages/constants.vhd | 1 | 384 | package CONSTANTS is
constant WORD_SIZE : integer := 32;
-- WRF
constant wrfNumBit : integer := 32; -- numBit;
constant wrfNumWindows : integer := 16; -- numWindows;
constant wrfNumRegsPerWin : integer := 8; -- numRegsPerWin;
constant wrfLogNumWindows : integer := 4; -- numWindows;
constant wrfLogNumRegsPerWin : integer := 3; -- LOG(numRegsPerWin)
end CONSTANTS;
| gpl-3.0 |
amerryfellow/dlx | basics/rca_generic.vhd | 1 | 970 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Generic N-bit Ripple Carry Adder
entity RCA_GENERIC is
generic (
NBIT : integer := 1
);
port (
A: in std_logic_vector(NBIT-1 downto 0);
B: in std_logic_vector(NBIT-1 downto 0);
Ci: in std_logic;
S: out std_logic_vector(NBIT-1 downto 0);
Co: out std_logic
);
end RCA_GENERIC;
-- Architectures
architecture STRUCTURAL of RCA_GENERIC is
signal STMP : std_logic_vector(NBIT-1 downto 0);
signal CTMP : std_logic_vector(NBIT downto 0);
component FULLADDER
port (
A: in std_logic;
B: in std_logic;
Ci: in std_logic;
S: out std_logic;
Co: out std_logic
);
end component;
begin
CTMP(0) <= Ci;
S <= STMP;
Co <= CTMP(NBIT);
-- Generate and concatenate the FAs
ADDER1: for I in 1 to NBIT generate
FAI : FULLADDER
port map (A(I-1), B(I-1), CTMP(I-1), STMP(I-1), CTMP(I));
end generate;
end STRUCTURAL;
-- Configurations deleted
| gpl-3.0 |
amerryfellow/dlx | basics/register_fde.vhd | 1 | 848 | library IEEE;
use IEEE.std_logic_1164.all;
-- Flipflop-based N-bit register
entity REGISTER_FDE is
generic (
N: integer := 1
);
port (
DIN: in std_logic_vector(N-1 downto 0); -- Data in
ENABLE: in std_logic; -- Enable
CLK: in std_logic; -- Clock
RESET: in std_logic; -- Reset
DOUT: out std_logic_vector(N-1 downto 0) -- Data out
);
end REGISTER_FDE;
-- Architectures
architecture ASYNCHRONOUS of REGISTER_FDE is
component FLIPFLOP
port (
D: in std_logic;
ENABLE : in std_logic;
CK: in std_logic;
RESET: in std_logic;
Q: out std_logic
);
end component;
signal INT_OUT : std_logic_vector(N-1 downto 0);
begin
REG_GEN_A : for i in 0 to N-1 generate
ASYNC_REG : FLIPFLOP
port map(DIN(i),ENABLE, CLK, RESET, INT_OUT(i));
end generate;
DOUT <= INT_OUT;
end ASYNCHRONOUS;
| gpl-3.0 |
amerryfellow/dlx | alu/adder/p4adder.vhd | 1 | 2070 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use WORK.alu_types.all;
-- Entity
entity P4ADDER is
generic(
N: integer:= NSUMG
);
port (
A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(N-1 downto 0);
OVERFLOW: out std_logic;
-- In case we need it,and it is only used for debugging the correct behaviour of the adder
Cout: out std_logic
);
end P4ADDER;
--
-- This is the structural architecture of a generic P4 adder.
--
-- TREE is a generic sparse radix-2 carry-merge that generates
-- every fourth carry in the adder.
--
-- SUMGENERATOR consists of (N/4 - 1) CSBs, each having
-- 2 4-bit Ripple Carry Adders. The carry select is thus
-- generic in terms of the number of carry select blocks.
--
architecture structural of P4ADDER is
signal CARRY, Ci: std_logic_vector(N/4 - 1 downto 0);
component TREE
generic(
N: integer := NSUMG;
LOGN: integer := LOG(NSUMG) -- For the LOG function refers to the P4ADDER_constants
);
port(
A: in std_logic_vector(N-1 downto 0); -- N bit input
B: in std_logic_vector(N-1 downto 0); -- N bit input
Cin: in std_logic;
C: out std_logic_vector(N/4-1 downto 0) -- Generate a carry every fourth bit
);
end component;
component SUMGENERATOR
generic(
NBIT: integer := NSUMG; --32
NCSB: integer := NCSUMG --8
);
port (
A: in std_logic_vector(NBIT-1 downto 0);
B: in std_logic_vector(NBIT-1 downto 0);
Ci: in std_logic_vector(NCSB-1 downto 0);
S: out std_logic_vector(NBIT-1 downto 0)
);
end component;
begin
SPARSE_TREE: TREE
generic map(N , LOG(N))
port map(A, B, Cin ,CARRY);
-- As C32 is not needed/ '0' is the first carry in (without propagate)
Ci <= CARRY((N/4)-2 downto 0) & Cin;
Cout <= CARRY((N/4)-1);
OVERFLOW <= CARRY((N/4)-1) XOR CARRY((N/4)-2);
SUM_GENERATOR: SUMGENERATOR
generic map(N , N/4)
port map(A,B,Ci,S);
end structural;
| gpl-3.0 |
nickg/nvc | test/regress/slice3.vhd | 5 | 589 | entity slice3 is
end entity;
architecture test of slice3 is
type bvv is array (integer range <>) of bit_vector(7 downto 0);
signal x : bvv(1 downto 0);
signal y : bit_vector(3 downto 0);
begin
process (y) is
begin
for i in x'range loop
x(i)(3 downto 0) <= y;
x(i)(7 downto 4) <= X"0";
end loop;
end process;
process is
begin
wait for 1 ns;
assert x = ( X"00", X"00" );
y <= X"f";
wait for 1 ns;
assert x = ( X"0f", X"0f" );
wait;
end process;
end architecture;
| gpl-3.0 |
nickg/nvc | test/lower/issue478.vhd | 1 | 309 | package test_pkg is
type t_slv_array is array (natural range <>) of bit_vector;
subtype t_word is bit_vector(15 downto 0);
subtype t_word_array is t_slv_array(open)(t_word'range);
constant C_NULL_DATA : t_word_array(0 to -1) := (others => (others => '0'));
end package;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_bram_ctrl_v4_0/hdl/vhdl/full_axi.vhd | 7 | 43438 | -------------------------------------------------------------------------------
-- full_axi.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: full_axi.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller when configured in a full AXI4 mode.
-- The rd_chnl and wr_chnl modules are instantiated.
-- The ECC AXI-Lite register module is instantiated, if enabled.
-- When single port BRAM mode is selected, the arbitration logic
-- is instantiated (and connected to each wr_chnl & rd_chnl).
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen_hsiao.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen_hsiao.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/15/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter and mappings on instantiated modules.
-- ^^^^^^
-- JLJ 2/18/2011 v1.03a
-- ~~~~~~
-- Update WE & BRAM data sizes based on 128-bit ECC configuration.
-- Plus XST clean-up.
-- ^^^^^^
-- JLJ 3/31/2011 v1.03a
-- ~~~~~~
-- Add coverage tags.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add signal, AW2Arb_BVALID_Cnt, between wr_chnl and sng_port_arb modules.
-- ^^^^^^
-- JLJ 4/20/2011 v1.03a
-- ~~~~~~
-- Add default values for Arb2AW_Active & Arb2AR_Active when dual port mode.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
use work.lite_ecc_reg;
use work.sng_port_arb;
use work.wr_chnl;
use work.rd_chnl;
------------------------------------------------------------------------------
entity full_axi is
generic (
-- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1;
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_ECC_TYPE : integer := 0; -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
ECC_Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- AXI Write Address Channel Signals (AW)
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
-- AXI Write Data Channel Signals (W)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
-- AXI Write Data Response Channel Signals (B)
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
-- AXI Read Address Channel Signals (AR)
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI-Lite ECC Register Interface Signals
-- AXI-Lite Clock and Reset
-- TBD
-- S_AXI_CTRL_ACLK : in std_logic;
-- S_AXI_CTRL_ARESETN : in std_logic;
-- AXI-Lite Write Address Channel Signals (AW)
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- BRAM Interface Signals (Port A)
BRAM_En_A : out std_logic;
BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-- BRAM Interface Signals (Port B)
BRAM_En_B : out std_logic;
BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0)
);
end entity full_axi;
-------------------------------------------------------------------------------
architecture implementation of full_axi is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH);
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-- Internal AXI Signals
signal S_AXI_AWREADY_i : std_logic := '0';
signal S_AXI_ARREADY_i : std_logic := '0';
-- Internal BRAM Signals
signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_En_A_i : std_logic := '0';
signal BRAM_En_B_i : std_logic := '0';
signal BRAM_WE_A_i : std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal BRAM_RdData_i : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
-- Internal ECC Signals
signal Enable_ECC : std_logic := '0';
signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers
signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Wr_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
--signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
--signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register
signal Wr_Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Wr_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Rd_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal Rd_Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Rd_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal FaultInjectECC : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal FaultInjectECC_i : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal Active_Wr : std_logic := '0';
signal BRAM_Addr_En : std_logic := '0';
signal Wr_BRAM_Addr_En : std_logic := '0';
signal Rd_BRAM_Addr_En : std_logic := '0';
-- Internal Arbitration Signals
signal Arb2AW_Active : std_logic := '0';
signal AW2Arb_Busy : std_logic := '0';
signal AW2Arb_Active_Clr : std_logic := '0';
signal AW2Arb_BVALID_Cnt : std_logic_vector (2 downto 0) := (others => '0');
signal Arb2AR_Active : std_logic := '0';
signal AR2Arb_Active_Clr : std_logic := '0';
signal WrChnl_BRAM_Addr_Rst : std_logic := '0';
signal WrChnl_BRAM_Addr_Ld_En : std_logic := '0';
signal WrChnl_BRAM_Addr_Inc : std_logic := '0';
signal WrChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal RdChnl_BRAM_Addr_Ld_En : std_logic := '0';
signal RdChnl_BRAM_Addr_Inc : std_logic := '0';
signal RdChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal bram_addr_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** BRAM Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: ADDR_SNG_PORT
-- Purpose: OR the BRAM_Addr outputs from each wr_chnl & rd_chnl
-- Only one write or read will be active at a time.
-- Ensure that ecah channel address is driven to '0' when not in use.
---------------------------------------------------------------------------
ADDR_SNG_PORT: if C_SINGLE_PORT_BRAM = 1 generate
signal sng_bram_addr_rst : std_logic := '0';
signal sng_bram_addr_ld_en : std_logic := '0';
signal sng_bram_addr_ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal sng_bram_addr_inc : std_logic := '0';
begin
-- BRAM_Addr_A <= BRAM_Addr_A_i or BRAM_Addr_B_i;
-- BRAM_Addr_A <= BRAM_Addr_A_i when (Arb2AW_Active = '1') else BRAM_Addr_B_i;
-- BRAM_Addr_A <= BRAM_Addr_A_i when (Active_Wr = '1') else BRAM_Addr_B_i;
-- Insert mux on address counter control signals
sng_bram_addr_rst <= WrChnl_BRAM_Addr_Rst;
sng_bram_addr_ld_en <= WrChnl_BRAM_Addr_Ld_En or RdChnl_BRAM_Addr_Ld_En;
sng_bram_addr_ld <= RdChnl_BRAM_Addr_Ld when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Ld;
sng_bram_addr_inc <= RdChnl_BRAM_Addr_Inc when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Inc;
I_ADDR_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (sng_bram_addr_rst = '1') then
bram_addr_int <= (others => '0');
elsif (sng_bram_addr_ld_en = '1') then
bram_addr_int <= sng_bram_addr_ld;
elsif (sng_bram_addr_inc = '1') then
bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12) <=
bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12);
bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <=
std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1);
end if;
end if;
end process I_ADDR_CNT;
BRAM_Addr_B <= (others => '0');
BRAM_En_A <= BRAM_En_A_i or BRAM_En_B_i;
-- BRAM_En_A <= BRAM_En_A_i when (Arb2AW_Active = '1') else BRAM_En_B_i;
BRAM_En_B <= '0';
BRAM_RdData_i <= BRAM_RdData_A; -- Assign read data port A
BRAM_WE_A <= BRAM_WE_A_i when (Arb2AW_Active = '1') else (others => '0');
-- v1.03a
-- Early register on WrData and WSTRB in wr_chnl. (Previous value was always cleared).
---------------------------------------------------------------------------
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr_A (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
---------------------------------------------------------------------------
GEN_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr_A (i) <= bram_addr_int (i);
end generate GEN_BRAM_ADDR;
end generate ADDR_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: ADDR_DUAL_PORT
-- Purpose: Assign each BRAM address when in a dual port controller
-- configuration.
---------------------------------------------------------------------------
ADDR_DUAL_PORT: if C_SINGLE_PORT_BRAM = 0 generate
begin
BRAM_Addr_A <= BRAM_Addr_A_i;
BRAM_Addr_B <= BRAM_Addr_B_i;
BRAM_En_A <= BRAM_En_A_i;
BRAM_En_B <= BRAM_En_B_i;
BRAM_WE_A <= BRAM_WE_A_i;
BRAM_RdData_i <= BRAM_RdData_B; -- Assign read data port B
end generate ADDR_DUAL_PORT;
BRAM_WrData_B <= (others => '0');
BRAM_WE_B <= (others => '0');
---------------------------------------------------------------------------
-- *** AXI-Lite ECC Register Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_REGS
-- Purpose: Generate default values if ECC registers are disabled (or when
-- ECC is disabled).
-- Include both AXI-Lite default signal values & internal
-- core signal values.
---------------------------------------------------------------------------
GEN_NO_REGS: if (C_ECC = 0) generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
-- No fault injection
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
-- Interrupt only enabled when ECC status/interrupt registers enabled
ECC_Interrupt <= '0';
ECC_UE <= '0';
Enable_ECC <= '0';
end generate GEN_NO_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_REGS
-- Purpose: Generate ECC register module when ECC is enabled and
-- ECC registers are enabled.
---------------------------------------------------------------------------
-- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate
-- For future implementation.
GEN_REGS: if (C_ECC = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_LITE_ECC_REG : entity work.lite_ecc_reg
generic map (
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width
C_FAULT_INJECT => C_FAULT_INJECT ,
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
-- TBD
-- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock
-- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn ,
Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
-- Add AXI-Lite ECC Register Ports
AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
Enable_ECC => Enable_ECC ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => CE_Failing_We ,
CE_CounterReg_Inc => CE_Failing_We ,
Sl_CE => Sl_CE ,
Sl_UE => Sl_UE ,
BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_En => BRAM_Addr_En ,
Active_Wr => Active_Wr ,
-- BRAM_RdData_A => BRAM_RdData_A (C_S_AXI_DATA_WIDTH-1 downto 0) ,
-- BRAM_RdData_B => BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0) ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC_i
);
BRAM_Addr_En <= Wr_BRAM_Addr_En or Rd_BRAM_Addr_En;
-- v1.03a
-- Add coverage tags for Wr_CE_Failing_We.
-- No testing on forcing errors with RMW and AXI write transfers.
--coverage off
CE_Failing_We <= Wr_CE_Failing_We or Rd_CE_Failing_We;
Sl_CE <= Wr_Sl_CE or Rd_Sl_CE;
Sl_UE <= Wr_Sl_UE or Rd_Sl_UE;
--coverage on
-------------------------------------------------------------------
-- Generate: GEN_32
-- Purpose: Add MSB '0' on ECC vector as only 7-bits wide in 32-bit.
-------------------------------------------------------------------
GEN_32: if C_S_AXI_DATA_WIDTH = 32 generate
begin
FaultInjectECC <= '0' & FaultInjectECC_i;
end generate GEN_32;
-------------------------------------------------------------------
-- Generate: GEN_NON_32
-- Purpose: Data widths match at 8-bits for ECC on 64-bit data.
-- And 9-bits for 128-bit data.
-------------------------------------------------------------------
GEN_NON_32: if C_S_AXI_DATA_WIDTH /= 32 generate
begin
FaultInjectECC <= FaultInjectECC_i;
end generate GEN_NON_32;
end generate GEN_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_ARB
-- Purpose: Generate arbitration module when AXI4 is configured in
-- single port mode.
---------------------------------------------------------------------------
GEN_ARB: if (C_SINGLE_PORT_BRAM = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_SNG_PORT : entity work.sng_port_arb
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_AWVALID => S_AXI_AWVALID ,
AXI_AWREADY => S_AXI_AWREADY ,
AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_ARVALID => S_AXI_ARVALID ,
AXI_ARREADY => S_AXI_ARREADY ,
Arb2AW_Active => Arb2AW_Active ,
AW2Arb_Busy => AW2Arb_Busy ,
AW2Arb_Active_Clr => AW2Arb_Active_Clr ,
AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt ,
Arb2AR_Active => Arb2AR_Active ,
AR2Arb_Active_Clr => AR2Arb_Active_Clr
);
end generate GEN_ARB;
---------------------------------------------------------------------------
-- Generate: GEN_DUAL
-- Purpose: Dual mode. AWREADY and ARREADY are generated from each
-- wr_chnl and rd_chnl module.
---------------------------------------------------------------------------
GEN_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
begin
S_AXI_AWREADY <= S_AXI_AWREADY_i;
S_AXI_ARREADY <= S_AXI_ARREADY_i;
Arb2AW_Active <= '0';
Arb2AR_Active <= '0';
end generate GEN_DUAL;
---------------------------------------------------------------------------
-- Instance: I_WR_CHNL
--
-- Description:
-- BRAM controller write channel logic. Controls AXI bus handshaking and
-- data flow on the write address (AW), write data (W) and
-- write response (B) channels.
--
-- BRAM signals are marked as output from Wr Chnl for future implementation
-- of merging Wr/Rd channel outputs to a single port of the BRAM module.
--
---------------------------------------------------------------------------
I_WR_CHNL : entity work.wr_chnl
generic map (
-- C_FAMILY => C_FAMILY ,
C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_ECC => C_ECC ,
C_ECC_WIDTH => C_ECC_WIDTH ,
C_ECC_TYPE => C_ECC_TYPE -- v1.03a
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
AXI_AWID => S_AXI_AWID ,
AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_AWLEN => S_AXI_AWLEN ,
AXI_AWSIZE => S_AXI_AWSIZE ,
AXI_AWBURST => S_AXI_AWBURST ,
AXI_AWLOCK => S_AXI_AWLOCK ,
AXI_AWCACHE => S_AXI_AWCACHE ,
AXI_AWPROT => S_AXI_AWPROT ,
AXI_AWVALID => S_AXI_AWVALID ,
AXI_AWREADY => S_AXI_AWREADY_i ,
AXI_WDATA => S_AXI_WDATA ,
AXI_WSTRB => S_AXI_WSTRB ,
AXI_WLAST => S_AXI_WLAST ,
AXI_WVALID => S_AXI_WVALID ,
AXI_WREADY => S_AXI_WREADY ,
AXI_BID => S_AXI_BID ,
AXI_BRESP => S_AXI_BRESP ,
AXI_BVALID => S_AXI_BVALID ,
AXI_BREADY => S_AXI_BREADY ,
-- Arb Ports
Arb2AW_Active => Arb2AW_Active ,
AW2Arb_Busy => AW2Arb_Busy ,
AW2Arb_Active_Clr => AW2Arb_Active_Clr ,
AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt ,
Sng_BRAM_Addr_Rst => WrChnl_BRAM_Addr_Rst ,
Sng_BRAM_Addr_Ld_En => WrChnl_BRAM_Addr_Ld_En ,
Sng_BRAM_Addr_Ld => WrChnl_BRAM_Addr_Ld ,
Sng_BRAM_Addr_Inc => WrChnl_BRAM_Addr_Inc ,
Sng_BRAM_Addr => bram_addr_int ,
-- ECC Ports
Enable_ECC => Enable_ECC ,
BRAM_Addr_En => Wr_BRAM_Addr_En ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => Wr_CE_Failing_We ,
Sl_CE => Wr_Sl_CE ,
Sl_UE => Wr_Sl_UE ,
Active_Wr => Active_Wr ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC ,
BRAM_En => BRAM_En_A_i ,
-- BRAM_WE => BRAM_WE_A ,
-- 4/13
BRAM_WE => BRAM_WE_A_i ,
BRAM_WrData => BRAM_WrData_A ,
BRAM_RdData => BRAM_RdData_A ,
BRAM_Addr => BRAM_Addr_A_i
);
---------------------------------------------------------------------------
-- Instance: I_RD_CHNL
--
-- Description:
-- BRAM controller read channel logic. Controls all handshaking and data
-- flow on read address (AR) and read data (R) AXI channels.
--
-- BRAM signals are marked as Rd Chnl signals for future implementation
-- of merging Rd/Wr BRAM signals to a single BRAM port.
--
---------------------------------------------------------------------------
I_RD_CHNL : entity work.rd_chnl
generic map (
-- C_FAMILY => C_FAMILY ,
C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_ECC => C_ECC ,
C_ECC_WIDTH => C_ECC_WIDTH ,
C_ECC_TYPE => C_ECC_TYPE -- v1.03a
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
AXI_ARID => S_AXI_ARID ,
AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_ARLEN => S_AXI_ARLEN ,
AXI_ARSIZE => S_AXI_ARSIZE ,
AXI_ARBURST => S_AXI_ARBURST ,
AXI_ARLOCK => S_AXI_ARLOCK ,
AXI_ARCACHE => S_AXI_ARCACHE ,
AXI_ARPROT => S_AXI_ARPROT ,
AXI_ARVALID => S_AXI_ARVALID ,
AXI_ARREADY => S_AXI_ARREADY_i ,
AXI_RID => S_AXI_RID ,
AXI_RDATA => S_AXI_RDATA ,
AXI_RRESP => S_AXI_RRESP ,
AXI_RLAST => S_AXI_RLAST ,
AXI_RVALID => S_AXI_RVALID ,
AXI_RREADY => S_AXI_RREADY ,
-- Arb Ports
Arb2AR_Active => Arb2AR_Active ,
AR2Arb_Active_Clr => AR2Arb_Active_Clr ,
Sng_BRAM_Addr_Ld_En => RdChnl_BRAM_Addr_Ld_En ,
Sng_BRAM_Addr_Ld => RdChnl_BRAM_Addr_Ld ,
Sng_BRAM_Addr_Inc => RdChnl_BRAM_Addr_Inc ,
Sng_BRAM_Addr => bram_addr_int ,
-- ECC Ports
Enable_ECC => Enable_ECC ,
BRAM_Addr_En => Rd_BRAM_Addr_En ,
CE_Failing_We => Rd_CE_Failing_We ,
Sl_CE => Rd_Sl_CE ,
Sl_UE => Rd_Sl_UE ,
BRAM_En => BRAM_En_B_i ,
BRAM_Addr => BRAM_Addr_B_i ,
BRAM_RdData => BRAM_RdData_i
);
end architecture implementation;
| gpl-3.0 |
nickg/nvc | test/model/alias1.vhd | 1 | 985 | entity alias1 is
end entity;
architecture test of alias1 is
signal x : bit_vector(7 downto 0);
alias x_top is x(7);
alias x_low is x(3 downto 0);
alias x_high is x(7 downto 4);
begin
process is
begin
x <= X"80";
wait for 1 ns;
assert x_top = '1';
assert x_low = X"0";
assert x_high = X"8";
x <= X"04";
wait for 1 ns;
assert x_top = '0';
assert x_low = X"4";
assert x_high = X"0";
x_top <= '1';
wait for 1 ns;
assert x_top = '1';
assert x_low = X"4";
assert x_high = X"8";
x_high <= X"f";
wait for 1 ns;
assert x_top = '1';
assert x_low = X"4";
assert x_high = X"f";
x_low <= X"b";
x_high <= X"1";
wait for 1 ns;
assert x_top = '0';
assert x_low = X"b";
assert x_high = X"1";
assert x = X"1b";
wait;
end process;
end architecture;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_sf.vhd | 3 | 50564 | -------------------------------------------------------------------------------
-- axi_datamover_wr_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Write (S2MM) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. This module buffers write data and provides status and
-- control features such that the DataMover Write Master is only allowed
-- to post AXI WRite Requests if the associated write data needed to complete
-- the Write Data transfer is present in the Data FIFO. In addition, the Write
-- side logic is such that Write transfer requests can be pipelined to the
-- AXI4 bus based on the Data FIFO contents but ahead of the actual Write Data
-- transfers.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_sfifo_autord;
-------------------------------------------------------------------------------
entity axi_datamover_wr_sf is
generic (
C_WR_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter indicates the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4
-- Write Address Channel will be the value assigned plus 2.
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
-- C_MAX_BURST_LEN : Integer range 16 to 256 := 16;
-- -- Indicates the max burst length being used by the external
-- -- AXI4 Master for each AXI4 transfer request.
-- C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- -- Indicates if the external Master is utilizing a DRE on
-- -- the stream input to this module.
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 16;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs -----------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
-------------------------------------------------------------------------
-- Slave Stream Input ------------------------------------------------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
sin2sf_error : In std_logic; --
-- Stream Underrun/Overrun error input --
-----------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
sin2sf_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. --
-----------------------------------------------------------------------------------
-- DataMover Write Side Address Pipelining Control Interface ----------------------
--
ok_to_post_wr_addr : Out Std_logic; --
-- Indicates that the internal FIFO has enough data --
-- physically present to supply one more max length --
-- burst transfer or a completion burst --
-- (tlast asserted) --
--
wr_addr_posted : In std_logic; --
-- Indication that a write address has been posted to AXI4 --
--
--
wr_xfer_cmplt : In Std_logic; --
-- Indicates that the Datamover has completed a Write Data --
-- transfer on the AXI4 --
--
--
wr_ld_nxt_len : in std_logic; --
-- Active high pulse indicating a new transfer LEN qualifier --
-- has been queued to the DataMover Write Data Controller --
--
wr_len : in std_logic_vector(7 downto 0); --
-- The actual LEN qualifier value that has been queued to the --
-- DataMover Write Data Controller --
-----------------------------------------------------------------------------------
-- Write Side Stream Out to DataMover S2MM ----------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic; --
-- Write LAST output to the Stream Master --
--
sf2sout_error : Out std_logic --
-- Stream Underrun/Overrun error input --
-----------------------------------------------------------------------------------
);
end entity axi_datamover_wr_sf;
architecture implementation of axi_datamover_wr_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_pwr2_depth
--
-- Function Description:
-- Rounds up to the next power of 2 depth value in an input
-- range of 1 to 8192
--
-------------------------------------------------------------------
function funct_get_pwr2_depth (min_depth : integer) return integer is
Variable var_temp_depth : Integer := 16;
begin
if (min_depth = 1) then
var_temp_depth := 1;
elsif (min_depth = 2) then
var_temp_depth := 2;
elsif (min_depth <= 4) then
var_temp_depth := 4;
elsif (min_depth <= 8) then
var_temp_depth := 8;
elsif (min_depth <= 16) then
var_temp_depth := 16;
elsif (min_depth <= 32) then
var_temp_depth := 32;
elsif (min_depth <= 64) then
var_temp_depth := 64;
elsif (min_depth <= 128) then
var_temp_depth := 128;
elsif (min_depth <= 256) then
var_temp_depth := 256;
elsif (min_depth <= 512) then
var_temp_depth := 512;
elsif (min_depth <= 1024) then
var_temp_depth := 1024;
elsif (min_depth <= 2048) then
var_temp_depth := 2048;
elsif (min_depth <= 4096) then
var_temp_depth := 4096;
else -- assume 8192 depth
var_temp_depth := 8192;
end if;
Return (var_temp_depth);
end function funct_get_pwr2_depth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant WSTB_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant EOP_ERR_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
-- Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
--WSTB_WIDTH +
TLAST_WIDTH +
EOP_ERR_WIDTH;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant DATA_OUT_LSB_INDEX : integer := 0;
-- Constant TSTRB_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
-- Constant TSTRB_OUT_MSB_INDEX : integer := (TSTRB_OUT_LSB_INDEX+WSTB_WIDTH)-1;
-- Constant TLAST_OUT_INDEX : integer := TSTRB_OUT_MSB_INDEX+1;
Constant TLAST_OUT_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant EOP_ERR_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant WR_LEN_FIFO_DWIDTH : integer := 8;
Constant WR_LEN_FIFO_DEPTH : integer := funct_get_pwr2_depth(C_WR_ADDR_PIPE_DEPTH + 2);
Constant LEN_CNTR_WIDTH : integer := 8;
Constant LEN_CNT_ZERO : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, LEN_CNTR_WIDTH);
Constant LEN_CNT_ONE : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, LEN_CNTR_WIDTH);
Constant WR_XFER_CNTR_WIDTH : integer := 8;
Constant WR_XFER_CNT_ZERO : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, WR_XFER_CNTR_WIDTH);
Constant WR_XFER_CNT_ONE : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, WR_XFER_CNTR_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector(WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_wr_addr_posted : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_wr_ld_nxt_len : std_logic := '0';
signal sig_push_len_fifo : std_logic := '0';
signal sig_pop_len_fifo : std_logic := '0';
signal sig_len_fifo_full : std_logic := '0';
signal sig_len_fifo_empty : std_logic := '0';
signal sig_len_fifo_data_in : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_data_out : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_len_out_un : unsigned(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_uncom_wrcnt : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_sub_len_uncom_wrcnt : std_logic := '0';
signal sig_incr_uncom_wrcnt : std_logic := '0';
signal sig_resized_fifo_len : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_num_wr_dbeats_needed : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_enough_dbeats_rcvd : std_logic := '0';
signal sig_sf2sout_eop_err_out : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Side (S2MM) Control Flags port connections
ok_to_post_wr_addr <= sig_ok_to_post_wr_addr ;
sig_wr_addr_posted <= wr_addr_posted ;
sig_wr_xfer_cmplt <= wr_xfer_cmplt ;
sig_wr_ld_nxt_len <= wr_ld_nxt_len ;
sig_len_fifo_data_in <= wr_len ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
sf2sout_error <= sig_sf2sout_eop_err_out ;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
sig_good_fifo_write <= sig_good_sin_strm_dbeat;
sig_strm_sin_ready <= not(sig_data_fifo_full);
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= sin2sf_error &
sin2sf_tlast &
-- sin2sf_tkeep &
sin2sf_tdata;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_ERR_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_err_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0');
signal lsig_partial_eop_err_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
-- Generate the stream ready
sig_strm_sin_ready <= not(lsig_packer_full) or
lsig_good_push2fifo ;
-- Format the FIFO input data
sig_data_fifo_data_in <= lsig_eop_err_or & -- MS Bit
lsig_tlast_or &
lsig_combined_data ; -- LS Bits
-- Generate a write to the Data FIFO input
sig_push_data_fifo <= lsig_packer_full;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_sin_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sin_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_sin_strm_dbeat and
(sin2sf_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(sin2sf_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_sin_strm_dbeat = '1' and
sin2sf_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_sin_strm_dbeat = '1' and
sin2sf_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sin2sf_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_sin_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice for the packer.
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= sin2sf_tdata;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= sin2sf_tlast & -- bit 1
sin2sf_error; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_err_or <= lsig_partial_eop_err_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_err_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_err_or(slice_index) <= lsig_partial_eop_err_or(slice_index-1) or
--lsig_partial_eop_err_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register outputs into a single
-- vector for input to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
-- FIFO Input attachments
-- sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= sin2sf_error &
-- sin2sf_tlast &
-- sin2sf_tkeep &
-- sin2sf_tdata;
-- FIFO Output to output stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid ;
sig_sf2sout_tdata <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
-- sig_sf2sout_tkeep <= sig_data_fifo_data_out(TSTRB_OUT_MSB_INDEX downto
-- TSTRB_OUT_LSB_INDEX);
-- When this Store and Forward is enabled, the Write Data Controller ignores the
-- TKEEP input so this is not sent through the FIFO.
sig_sf2sout_tkeep <= (others => '1');
sig_sf2sout_tlast <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_sf2sout_eop_err_out <= sig_data_fifo_data_out(EOP_ERR_OUT_INDEX) ;
-- FIFO Rd/WR Controls
sig_pop_data_fifo <= sig_sout2sf_tready and
sig_data_fifo_dvalid;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_10.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
--------------------------------------------------------------------
-- Write Side Control Logic
--------------------------------------------------------------------
-- Convert the LEN fifo data output to unsigned
sig_len_fifo_len_out_un <= unsigned(sig_len_fifo_data_out);
-- Resize the unsigned LEN output to the Data FIFO writecount width
sig_resized_fifo_len <= RESIZE(sig_len_fifo_len_out_un , DATA_FIFO_CNT_WIDTH);
-- The actual number of databeats needed for the queued write transfer
-- is the current LEN fifo output plus 1.
sig_num_wr_dbeats_needed <= sig_resized_fifo_len + UNCOM_WRCNT_1;
-- Compare the uncommited receved data beat count to that needed
-- for the next queued write request.
sig_enough_dbeats_rcvd <= '1'
When (sig_num_wr_dbeats_needed <= sig_uncom_wrcnt)
else '0';
-- Increment the uncommited databeat counter on a good input
-- stream databeat (Read Side of SF)
-- sig_incr_uncom_wrcnt <= sig_good_sin_strm_dbeat;
sig_incr_uncom_wrcnt <= sig_good_fifo_write;
-- Subtract the current number of databeats needed from the
-- uncommited databeat counter when the associated transfer
-- address/qualifiers have been posted to the AXI Write
-- Address Channel
sig_sub_len_uncom_wrcnt <= sig_wr_addr_posted;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_UNCOM_DBEAT_CNTR
--
-- Process Description:
-- Implements the counter that keeps track of the received read
-- data beat count that has not been commited to a transfer on
-- the write side with a Write Address posting.
--
-------------------------------------------------------------
IMP_UNCOM_DBEAT_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_uncom_wrcnt <= UNCOM_WRCNT_0;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_resized_fifo_len;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '0') then
sig_uncom_wrcnt <= sig_uncom_wrcnt + UNCOM_WRCNT_1;
elsif (sig_incr_uncom_wrcnt = '0' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_num_wr_dbeats_needed;
else
null; -- hold current value
end if;
end if;
end process IMP_UNCOM_DBEAT_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_ADDR_POST_FLAG
--
-- Process Description:
-- Implements the flag indicating that the pending write
-- transfer's data beat count has been received on the input
-- side of the Data FIFO. This means the Write side can post
-- the associated write address to the AXI4 bus and the
-- associated write data transfer can complete without CDMA
-- throttling the Write Data Channel.
--
-- The flag is cleared immediately after an address is posted
-- to prohibit a second unauthorized posting while the control
-- logic stabilizes to the next LEN FIFO value
--.
-------------------------------------------------------------
IMP_WR_ADDR_POST_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_wr_addr_posted = '1') then
sig_ok_to_post_wr_addr <= '0';
else
sig_ok_to_post_wr_addr <= not(sig_len_fifo_empty) and
sig_enough_dbeats_rcvd;
end if;
end if;
end process IMP_WR_ADDR_POST_FLAG;
-------------------------------------------------------------
-- LEN FIFO logic
-- The LEN FIFO stores the xfer lengths needed for each queued
-- write transfer in the DataMover S2MM Write Data Controller.
sig_push_len_fifo <= sig_wr_ld_nxt_len and
not(sig_len_fifo_full);
sig_pop_len_fifo <= wr_addr_posted and
not(sig_len_fifo_empty);
------------------------------------------------------------
-- Instance: I_WR_LEN_FIFO
--
-- Description:
-- Implement the LEN FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_WR_LEN_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => WR_LEN_FIFO_DWIDTH ,
C_DEPTH => WR_LEN_FIFO_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => aclk ,
Reset => reset ,
FIFO_Write => sig_push_len_fifo ,
Data_In => sig_len_fifo_data_in ,
FIFO_Read => sig_pop_len_fifo ,
Data_Out => sig_len_fifo_data_out ,
FIFO_Empty => sig_len_fifo_empty ,
FIFO_Full => sig_len_fifo_full ,
Addr => open
);
end implementation;
| gpl-3.0 |
nickg/nvc | test/perf/bigcase.vhd | 1 | 102941 | library ieee;
use ieee.std_logic_1164.all;
library work;
entity LogTable_0_10_74_F400_uid60 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(9 downto 0);
Y : out std_logic_vector(73 downto 0) );
end entity;
architecture arch of LogTable_0_10_74_F400_uid60 is
signal TableOut, TableOut_d1 : std_logic_vector(73 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
TableOut_d1 <= TableOut;
end if;
end process;
with X select TableOut <=
"11111111111111101111111111111100000000000000000000000000000000000000000000" when "0000000000",
"11111111111111101111111111111100000000000000000000000000000000000000000000" when "0000000001",
"00000000001111110000011111111101010101011001010101100010001001001100110101" when "0000000010",
"00000000011111110010000000000110101011101010110001000100111011110011100001" when "0000000011",
"00000000101111110100100000100000000101000100110000101110000000110100101101" when "0000000100",
"00000000111111111000000001010001100101011000100010110011010101111110010110" when "0000000101",
"00000001001111111100100010100011010001111000011110001110000111000111011111" when "0000000110",
"00000001100000000010000100011101010001011000011010110101010000001110000011" when "0000000111",
"00000001110000001000100111000111101100001110001001111111101010101110110111" when "0000001000",
"00000010000000010000001010101010101100010001101111001110001001010001100110" when "0000001001",
"00000010010000011000101111001110011100111101111000111101000100100011100011" when "0000001010",
"00000010100000100010010100111011001011010000011001011101111100011101010110" when "0000001011",
"00000010110000101100111011111001000101101010011111111000110000010001010100" when "0000001100",
"00000011000000111000100100010000011100010001010001010101010001000001001011" when "0000001101",
"00000011010001000101001110001001100000101110000010001100010000111011001010" when "0000001110",
"00000011100001010010111001101100100110001110101111100000110011000000001100" when "0000001111",
"00000011110001100001100111000010000001100110011000100001011101110101110001" when "0000010000",
"00000100000001110001010110010010001001001101011000010001110100100111110010" when "0000010001",
"00000100010010000010000111100101010101000001111111011011111001011111111011" when "0000010010",
"00000100100010010011111011000011111110101000101110001001111100011001010001" when "0000010011",
"00000100110010100110110000110110100001001100101110001000011001011000100110" when "0000010100",
"00000101000010111010101001000101011001100000001100110000001001110011001001" when "0000010101",
"00000101010011001111100011111001000101111100110101011001001011001110100110" when "0000010110",
"00000101100011100101100001011010000110100100001011110101011111100111000101" when "0000010111",
"00000101110011111100100001110000111101000000000110110100101001101001000100" when "0000011000",
"00000110000100010100100101000110001100100011001010101111101000101110011011" when "0000011001",
"00000110010100101101101011100010011010001001000100011101010111101111100110" when "0000011010",
"00000110100101000111110101001110001100010111000100001111110001111011000010" when "0000011011",
"00000110110101100011000010010010001011011100011000111001100001000110111001" when "0000011100",
"00000111000101111111010010110111000001010010101010111100011000110001111111" when "0000011101",
"00000111010110011100100111000101011001011110011000000000100001001010111101" when "0000011110",
"00000111100110111010111111000110000001001111001110010100010101110101101101" when "0000011111",
"00000111110111011010011011000001100111100000101000010101011011001001001110" when "0000100000",
"00000111110111011010011011000001100111100000101000010101011011001001001110" when "0000100001",
"00001000000111111010111011000000111100111010001000100010001110000000101110" when "0000100010",
"00001000011000011100011111001100110011101111110101010100110001011101010100" when "0000100011",
"00001000101000111111000111101110000000000010110101000110011101010110010111" when "0000100100",
"00001000111001100010110100101101010111100001101010011100110001111000110110" when "0000100101",
"00001001001010000111100110010011110001101000110000011111010011010111000000" when "0000100110",
"00001001011010101101011100101010000111100010110111010110110001101011101010" when "0000100111",
"00001001101011010100010111111001010100001001100000110101011111010101111100" when "0000101000",
"00001001111011111100011000001010010100000101011101001000111011010011111110" when "0000101001",
"00001010001100100101011101100110000101101111000111110100110001100100010100" when "0000101010",
"00001010011101001111101000010101101001001111000100110111010101111000010010" when "0000101011",
"00001010101101111010111000100010000000011110011101110111011100100010000001" when "0000101100",
"00001010111110100111001110010100001111000111011111011011110100101100000000" when "0000101101",
"00001011001111010100101001110101011010100101110110101100001000001000001010" when "0000101110",
"00001011001111010100101001110101011010100101110110101100001000001000001010" when "0000101111",
"00001011100000000011001011001110101010000111001110111011100100000111011100" when "0000110000",
"00001011110000110010110010101001000110101011101111011101001111001011111000" when "0000110001",
"00001100000001100011100000001101111011000110011001100010001111101001000011" when "0000110010",
"00001100010010010101010100000110010011111101100110100001100110101000110000" when "0000110011",
"00001100100011001000001110011011011111101011100110001010000011101011000001" when "0000110100",
"00001100110011111100001111010110101110011110111100111101110100011011000101" when "0000110101",
"00001101000100110001010111000001010010011011000010111000010100110011111110" when "0000110110",
"00001101010101100111100101100100011111011000100001111110000011010001101010" when "0000110111",
"00001101100110011110111011001001101011000101110101010110011101001101011011" when "0000111000",
"00001101100110011110111011001001101011000101110101010110011101001101011011" when "0000111001",
"00001101110111010111010111111010001101000111101000010000000111100101110100" when "0000111010",
"00001110001000010000111011111111011110111001010101001111000111110100100110" when "0000111011",
"00001110011001001011100111100010111011101101100101100101110000110110111000" when "0000111100",
"00001110101010000111011010101110000000101110110000110111101000101101010111" when "0000111101",
"00001110111011000100010101101010001100111111011100100111001010011100110110" when "0000111110",
"00001111001100000010011000100001000001011010111100001101101000111000101110" when "0000111111",
"00001111011101000001100011011100000000110101110000111101110110000011011000" when "0001000000",
"00001111101110000001110110100100101111111110001010010001010011110010001011" when "0001000001",
"00001111111111000011010010000100110101011100100110000000010001100100110000" when "0001000010",
"00001111111111000011010010000100110101011100100110000000010001100100110000" when "0001000011",
"00010000010000000101110110000101111001110100010001000100011100000001011101" when "0001000100",
"00010000100001001001100010110001100111100011101000000110100010001010010000" when "0001000101",
"00010000110010001110011000010001101011000100111000010110110101000000010011" when "0001000110",
"00010001000011010100010110101111110010101110100000110000100101101101011111" when "0001000111",
"00010001010100011011011110010101101110110011110011001000100110101101111100" when "0001001000",
"00010001100101100011101111001101010001100101010101100110110100010101010100" when "0001001001",
"00010001110110101101001001100000001111010001100100001011001001001101100110" when "0001001010",
"00010001110110101101001001100000001111010001100100001011001001001101100110" when "0001001011",
"00010010000111110111101101011000011110000101010010011101100011001111110000" when "0001001100",
"00010010011001000011011010111111110110001100001101101001011101011000000101" when "0001001101",
"00010010101010010000010010100000010001110001011110100100100010111010100011" when "0001001110",
"00010010111011011110010100000011101101000000001100000001000000111101101111" when "0001001111",
"00010011001100101101011111110100000110000011111101001011011010100100101011" when "0001010000",
"00010011011101111101110101111011011101001001011100010100000100010010100100" when "0001010001",
"00010011011101111101110101111011011101001001011100010100000100010010100100" when "0001010010",
"00010011101111001111010110100011110100011110111001100100001011110101001100" when "0001010011",
"00010100000000100010000001110111010000010100101101111110110000100101010101" when "0001010100",
"00010100010001110101110111111111110110111101111110101101010001101110100011" when "0001010101",
"00010100100011001010111001000111110000110001000000011000010110110010000010" when "0001010110",
"00010100110100100001000101011001001000000111111010101100010111011010011111" when "0001010111",
"00010101000101111000011100111110001001100001001100001010000111011001011001" when "0001011000",
"00010101000101111000011100111110001001100001001100001010000111011001011001" when "0001011001",
"00010101010111010001000000000001000011100000001110000011101011101000000110" when "0001011010",
"00010101101000101010101110101100000110101101111000100101011101001001111010" when "0001011011",
"00010101111010000101101001001001100101111001000111001011011111001110000111" when "0001011100",
"00010110001011100001101111100011110101110111011101000011001101010100000010" when "0001011101",
"00010110011100111111000010000101001101100101101001111001100110010100110010" when "0001011110",
"00010110011100111111000010000101001101100101101001111001100110010100110010" when "0001011111",
"00010110101110011101100000111000000110001000001110110101111001111001100000" when "0001100000",
"00010110111111111101001100000110111010101100000011100000111101000110110101" when "0001100001",
"00010111010001011110000011111100001000100110111011011001001011101001001000" when "0001100010",
"00010111100011000000001000100010001111011000001011010011011010101111001010" when "0001100011",
"00010111110100100011011010000011110000101001001111001000100011000011111010" when "0001100100",
"00010111110100100011011010000011110000101001001111001000100011000011111010" when "0001100101",
"00011000000110000111111000101011010000001110001111110000000110111001111101" when "0001100110",
"00011000010111101101100100100011010100000110101001000111111001111110011010" when "0001100111",
"00011000101001010100011101110110100100011101110000101000110000001010111110" when "0001101000",
"00011000111010111100100100101111101011101011011011101000011000110010000011" when "0001101001",
"00011001001100100101111001011001010110010100100110001000101011100001110110" when "0001101010",
"00011001001100100101111001011001010110010100100110001000101011100001110110" when "0001101011",
"00011001011110010000011011111110010011001011111001110100001100111110100011" when "0001101100",
"00011001101111111100001100101001010011010010010101001000001111110110000110" when "0001101101",
"00011010000001101001001011100101001001110111110010101100011000110010011011" when "0001101110",
"00011010010011010111011000111100101100011011110000110111101010010010100011" when "0001101111",
"00011010010011010111011000111100101100011011110000110111101010010010100011" when "0001110000",
"00011010100101000110110100111010110010101101111001100011011110010100110000" when "0001110001",
"00011010110110110111011111101010010110101110101010001100010011011111011001" when "0001110010",
"00011011001000101001011001010110010100101111111100000000010011011000100011" when "0001110011",
"00011011011010011100100010001001101011010101101100011011110111111111010100" when "0001110100",
"00011011101100010000111010001111011011010110100101110100010101111100101011" when "0001110101",
"00011011101100010000111010001111011011010110100101110100010101111100101011" when "0001110110",
"00011011111110000110100001110010100111111100101000010000110001100100011011" when "0001110111",
"00011100001111111101011000111110010110100101110010110001000100100001110100" when "0001111000",
"00011100100001110101011111111101101111000100101100100011011010001110001101" when "0001111001",
"00011100110011101110110110111011111011100001001110101000001000110011000000" when "0001111010",
"00011100110011101110110110111011111011100001001110101000001000110011000000" when "0001111011",
"00011101000101101001011110000100001000011001001101100100001100111011011000" when "0001111100",
"00011101010111100101010101100001100100100001000011100010001110011100110000" when "0001111101",
"00011101101001100010011101011111100001000100011010100010010100000000100000" when "0001111110",
"00011101101001100010011101011111100001000100011010100010010100000000100000" when "0001111111",
"00011101111011100000110110001001010001100110110110111000101011111011111011" when "0010000000",
"00011110001101100000011111101010001100000100100001111011010000100111001101" when "0010000001",
"00011110011111100001011010001101101000110010110100111110001110100110010001" when "0010000010",
"00011110110001100011100101111111000010100001000100011111110010111010100000" when "0010000011",
"00011110110001100011100101111111000010100001000100011111110010111010100000" when "0010000100",
"00011111000011100111000011001001110110011001001011100011000111110110110001" when "0010000101",
"00011111010101101011110001111001100100000000010111011010100110110010011111" when "0010000110",
"00011111100111110001110010011001101101010111110011100001100101011100000011" when "0010000111",
"00011111111001111001000100110101110110111101010101100101100101001101100001" when "0010001000",
"00011111111001111001000100110101110110111101010101100101100101001101100001" when "0010001001",
"00100000001100000001101001011001100111101100001001111111001011001010001110" when "0010001010",
"00100000011110001011100000010000101000111101100000011010100111001111000110" when "0010001011",
"00100000110000010110101001100110100110101001011000110000010001100010100001" when "0010001100",
"00100000110000010110101001100110100110101001011000110000010001100010100001" when "0010001101",
"00100001000010100011000101100111001111000111010000001101000100010100100000" when "0010001110",
"00100001010100110000110100011110010011001110101110101010111001100010100100" when "0010001111",
"00100001100110111111110110010111100110011000010100011001010010110110101100" when "0010010000",
"00100001111001010000001011011110111110011110000111110110010010111011111001" when "0010010001",
"00100001111001010000001011011110111110011110000111110110010010111011111001" when "0010010010",
"00100010001011100001110100000000010011111100100011110111101111000110011100" when "0010010011",
"00100010011101110100110000000111100001110011000110000101000000010001001110" when "0010010100",
"00100010110000001001000000000000100101100100111101100001011010010101010010" when "0010010101",
"00100010110000001001000000000000100101100100111101100001011010010101010010" when "0010010110",
"00100011000010011110100011110111011111011001111001100111010001000100010111" when "0010010111",
"00100011010100110101011011111000010001111110111001010011110001110010001000" when "0010011000",
"00100011100111001101101000001111000010100110111010100011111000111100011100" when "0010011001",
"00100011100111001101101000001111000010100110111010100011111000111100011100" when "0010011010",
"00100011111001100111001001000111111001001011101010000010001011000101100101" when "0010011011",
"00100100001100000001111110101111000000001110010011000101111000011000000011" when "0010011100",
"00100100011110011110001001010000100100111000010000000011010010001110010000" when "0010011101",
"00100100011110011110001001010000100100111000010000000011010010001110010000" when "0010011110",
"00100100110000111011101000111000110110111011111010101101011010011101000100" when "0010011111",
"00100101000011011010011101110100001000110101011101001001010011100011010110" when "0010100000",
"00100101010101111010101000001110101111101011100010110010111001100100101111" when "0010100001",
"00100101010101111010101000001110101111101011100010110010111001100100101111" when "0010100010",
"00100101101000011100001000010101000011010000001001110011101011011001100110" when "0010100011",
"00100101111010111110111110010011011110000001010100101011001100000010000110" when "0010100100",
"00100110001101100011001010010110011101001001111100001001100011101110001110" when "0010100101",
"00100110001101100011001010010110011101001001111100001001100011101110001110" when "0010100110",
"00100110100000001000101100101010100000100010100001011100001000110000100000" when "0010100111",
"00100110110010101111100101011100001010110010000000101100010111110101000001" when "0010101000",
"00100111000101010111110100111000000001001110100011110001000011111010101110" when "0010101001",
"00100111000101010111110100111000000001001110100011110001000011111010101110" when "0010101010",
"00100111011000000001011011001010101011111110010101010010000101110000110110" when "0010101011",
"00100111101010101100011000100000110101111000010011111110110010111110000101" when "0010101100",
"00100111101010101100011000100000110101111000010011111110110010111110000101" when "0010101101",
"00100111111101011000101101000111001100100101000110010111000100111100000011" when "0010101110",
"00101000010000000110011001001010100000011111101110100111010111110100111000" when "0010101111",
"00101000100010110101011100110111100100110110011110110111101001110101100100" when "0010110000",
"00101000100010110101011100110111100100110110011110110111101001110101100100" when "0010110001",
"00101000110101100101111000011011001111101011101101101101100011001011111000" when "0010110010",
"00101001001000010111101100000010011001110110101011000001101111001010101010" when "0010110011",
"00101001011011001010110111111001111111000100010101001000101110110011110110" when "0010110100",
"00101001011011001010110111111001111111000100010101001000101110110011110110" when "0010110101",
"00101001101101111111011100001110111101111000001110001111001101101100000110" when "0010110110",
"00101010000000110101011001001110010111101101010010001010000001011111111101" when "0010110111",
"00101010000000110101011001001110010111101101010010001010000001011111111101" when "0010111000",
"00101010010011101100101111000101010000110110101100011001111101000111001011" when "0010111001",
"00101010100110100101011110000000110000100000101110100011011111110111001100" when "0010111010",
"00101010111001011111100110001110000000110001100110111010101001111010011011" when "0010111011",
"00101010111001011111100110001110000000110001100110111010101001111010011011" when "0010111100",
"00101011001100011011000111111010001110101010010111100010111110100110100010" when "0010111101",
"00101011011111011000000011010010101010000111101101100011111101110000010100" when "0010111110",
"00101011011111011000000011010010101010000111101101100011111101110000010100" when "0010111111",
"00101011110010010110011000100100100110000010111000110001111101000000110001" when "0011000000",
"00101100000101010110000111111101011000010010100011101011101010010011011010" when "0011000001",
"00101100011000010111010001101010011001101011101011101100100000101010110001" when "0011000010",
"00101100011000010111010001101010011001101011101011101100100000101010110001" when "0011000011",
"00101100101011011001110101111001000110000010011001110011111000101100101100" when "0011000100",
"00101100111110011101110100110110111100001010111011100001011101111100111110" when "0011000101",
"00101100111110011101110100110110111100001010111011100001011101111100111110" when "0011000110",
"00101101010001100011001110110001011101111010011100000110110010110001100110" when "0011000111",
"00101101100100101010000011110110010000000111111110001110001100000001010000" when "0011001000",
"00101101110111110010010100010010111010101101010101110111001110010000110101" when "0011001001",
"00101101110111110010010100010010111010101101010101110111001110010000110101" when "0011001010",
"00101110001010111100000000010101001000101000000010101000110110001010110000" when "0011001011",
"00101110011110000111001000001010100111111010001010011001010101101111001100" when "0011001100",
"00101110011110000111001000001010100111111010001010011001010101101111001100" when "0011001101",
"00101110110001010011101100000001001001101011010100001100010000010001110000" when "0011001110",
"00101111000100100001101100000110100010001001100011100110011110111110010000" when "0011001111",
"00101111000100100001101100000110100010001001100011100110011110111110010000" when "0011010000",
"00101111010111110001001000101000101000101010010100011000101000000011010100" when "0011010001",
"00101111101011000010000001110101010111101011010110011111110010100111010000" when "0011010010",
"00101111101011000010000001110101010111101011010110011111110010100111010000" when "0011010011",
"00101111111110010100010111111010101100110011101010011101000001010000001100" when "0011010100",
"00110000010001101000001011000110101000110100011110000011011101101110011010" when "0011010101",
"00110000100100111101011011100111001111101010001001011101011111111101010100" when "0011010110",
"00110000100100111101011011100111001111101010001001011101011111111101010100" when "0011010111",
"00110000111000010100001001101010101000011101001100101000111010110100001100" when "0011011000",
"00110001001011101100010101011110111101100011001101001010011001000110010000" when "0011011001",
"00110001001011101100010101011110111101100011001101001010011001000110010000" when "0011011010",
"00110001011111000101111111010010011100011111110100011000010101010110101010" when "0011011011",
"00110001110010100001000111010011010110000101101101111101010111001010101101" when "0011011100",
"00110001110010100001000111010011010110000101101101111101010111001010101101" when "0011011101",
"00110010000101111101101101101111111110010111100110110010100000101010001001" when "0011011110",
"00110010011001011011110010110110101100101001001100010001010111000011101011" when "0011011111",
"00110010011001011011110010110110101100101001001100010001010111000011101011" when "0011100000",
"00110010101100111011010110110101111011100000001011111110010001010000101100" when "0011100001",
"00110011000000011100011001111100001000110101010011101010110111011001111010" when "0011100010",
"00110011000000011100011001111100001000110101010011101010110111011001111010" when "0011100011",
"00110011010011111110111100010111110101110101010001110000111110100011111100" when "0011100100",
"00110011100111100010111110010111100111000001110110000110001011110001000011" when "0011100101",
"00110011100111100010111110010111100111000001110110000110001011110001000011" when "0011100110",
"00110011111011001000100000001010000100010010110011001000001001101011010001" when "0011100111",
"00110100001110101111100001111101111000110110111111100001111100001111111111" when "0011101000",
"00110100001110101111100001111101111000110110111111100001111100001111111111" when "0011101001",
"00110100100010011000000100000001110011010101011000001010011101111100100000" when "0011101010",
"00110100110110000010000110100100100101101110000010011100010010000000111111" when "0011101011",
"00110100110110000010000110100100100101101110000010011100010010000000111111" when "0011101100",
"00110101001001101101101001110101000101011011001111000110110111100101011111" when "0011101101",
"00110101011101011010101110000010001011010010011101011001101001010011010100" when "0011101110",
"00110101011101011010101110000010001011010010011101011001101001010011010100" when "0011101111",
"00110101110001001001010011011010110011100101011110101000110101011010111001" when "0011110000",
"00110110000100111001011010001101111110000011011010001100011010010101001000" when "0011110001",
"00110110000100111001011010001101111110000011011010001100011010010101001000" when "0011110010",
"00110110011000101011000010101010101101111001110001111001010011100101011001" when "0011110011",
"00110110101100011110001101000000001001110101100110110101000011101000001111" when "0011110100",
"00110110101100011110001101000000001001110101100110110101000011101000001111" when "0011110101",
"00110111000000010010111001011101011100000100011110100100000110100000111100" when "0011110110",
"00110111000000010010111001011101011100000100011110100100000110100000111100" when "0011110111",
"00110111010100001001001000010001110010010101101000110010111001111111010001" when "0011111000",
"00110111101000000000111001101100011101111011000101011010000111011101001101" when "0011111001",
"00110111101000000000111001101100011101111011000101011010000111011101001101" when "0011111010",
"00110111111011111010001101111100110011101010101010111101111100011011010000" when "0011111011",
"00111000001111110101000101010010001011111111001101101000111110001000110101" when "0011111100",
"00111000001111110101000101010010001011111111001101101000111110001000110101" when "0011111101",
"00111000100011110001011111111100000010111001100110100010100101001101011000" when "0011111110",
"00111000110111101111011110001001111000000001111011100001001110001101001110" when "0011111111",
"00111000110111101111011110001001111000000001111011100001001110001101001110" when "0100000000",
"00111001001011101111000000001011001110101000100111011000101100001101010010" when "0100000001",
"00111001011111110000000110001111101101100111100010100100101010011110100011" when "0100000010",
"00111001011111110000000110001111101101100111100010100100101010011110100011" when "0100000011",
"00111001110011110010110000100110111111100011001100001111101010100010111100" when "0100000100",
"00111001110011110010110000100110111111100011001100001111101010100010111100" when "0100000101",
"00111010000111110110111111100000110010101011110011110110101100000011000101" when "0100000110",
"00111010011011111100110011001100111000111110100011001001101011110100110010" when "0100000111",
"00111010011011111100110011001100111000111110100011001001101011110100110010" when "0100001000",
"00111010110000000100001011111011001000000110101000101001000111111001000001" when "0100001001",
"00111011000100001101001001111011011001011110100010100000110101111111110111" when "0100001010",
"00111011000100001101001001111011011001011110100010100000110101111111110111" when "0100001011",
"00111011011000010111101101011101101010010001001010000000011010101000010010" when "0100001100",
"00111011101100100011110110110001111011011010111111010001001110011001011001" when "0100001101",
"00111011101100100011110110110001111011011010111111010001001110011001011001" when "0100001110",
"00111100000000110001100110001000010001101011010101101010011111111010100100" when "0100001111",
"00111100000000110001100110001000010001101011010101101010011111111010100100" when "0100010000",
"00111100010101000000111011110000110101100101100000100011100000010111011110" when "0100010001",
"00111100101001010001110111111011110011100010000000100100001001000100111011" when "0100010010",
"00111100101001010001110111111011110011100010000000100100001001000100111011" when "0100010011",
"00111100111101100100011010111001011011101111110001010100001000100011101110" when "0100010100",
"00111101010001111000100100111010000010010101010111101001000101100110001110" when "0100010101",
"00111101010001111000100100111010000010010101010111101001000101100110001110" when "0100010110",
"00111101100110001110010110001101111111010010010000010011100111000101110000" when "0100010111",
"00111101100110001110010110001101111111010010010000010011100111000101110000" when "0100011000",
"00111101111010100101101111000101101110011111111111001011101111011101010101" when "0100011001",
"00111110001110111110101111110001101111110011011110111100111010100110110100" when "0100011010",
"00111110001110111110101111110001101111110011011110111100111010100110110100" when "0100011011",
"00111110100011011001011000100010100110111110010001010001101101100000111000" when "0100011100",
"00111110100011011001011000100010100110111110010001010001101101100000111000" when "0100011101",
"00111110110111110101101001101000111011101111101111011111100110101011101010" when "0100011110",
"00111111001100010011100011010101011001110110011011110010111110110011001010" when "0100011111",
"00111111001100010011100011010101011001110110011011110010111110110011001010" when "0100100000",
"00111111100000110011000101111000110001000001010010111011101001000110111100" when "0100100001",
"00111111100000110011000101111000110001000001010010111011101001000110111100" when "0100100010",
"00111111110101010100010001100011110101000000111110011010000011000110111100" when "0100100011",
"01000000001001110111000110100111011101101001000111001101100011010110100010" when "0100100100",
"01000000001001110111000110100111011101101001000111001101100011010110100010" when "0100100101",
"01000000011110011011100101010100100110110001101001000011110111001111101100" when "0100100110",
"01000000110011000001101101111100010000011000000110001001111111111000101010" when "0100100111",
"01000000110011000001101101111100010000011000000110001001111111111000101010" when "0100101000",
"01000001000111101001100000101111011110100000111011011110111110001000011010" when "0100101001",
"01000001000111101001100000101111011110100000111011011110111110001000011010" when "0100101010",
"01000001011100010010111101111111011001011000110101101000011110001110001111" when "0100101011",
"01000001110000111110000101111101001101010110000110001001110011011011000110" when "0100101100",
"01000001110000111110000101111101001101010110000110001001110011011011000110" when "0100101101",
"01000010000101101010111000111010001010111001111001011101010100010011111101" when "0100101110",
"01000010000101101010111000111010001010111001111001011101010100010011111101" when "0100101111",
"01000010011010011001010111000111100110110001101101010000101000011110000110" when "0100110000",
"01000010101111001001100000110110111001111000100111100011111000011111101010" when "0100110001",
"01000010101111001001100000110110111001111000100111100011111000011111101010" when "0100110010",
"01000011000011111011010110011001100001011000101110001100010001011000101100" when "0100110011",
"01000011000011111011010110011001100001011000101110001100010001011000101100" when "0100110100",
"01000011011000101110111000000000111110101100011110111010001100100010001000" when "0100110101",
"01000011011000101110111000000000111110101100011110111010001100100010001000" when "0100110110",
"01000011101101100100000101111110110111100000001000000011001101101010010111" when "0100110111",
"01000100000010011011000000100100110101110011000001110000001000010001000000" when "0100111000",
"01000100000010011011000000100100110101110011000001110000001000010001000000" when "0100111001",
"01000100010111010011101000000100100111111001000111101111011110001100111000" when "0100111010",
"01000100010111010011101000000100100111111001000111101111011110001100111000" when "0100111011",
"01000100101100001101111100110000000000011100010011101100101001010010001010" when "0100111100",
"01000101000001001001111110111000110110011101111000001100000001111000001001" when "0100111101",
"01000101000001001001111110111000110110011101111000001100000001111000001001" when "0100111110",
"01000101010110000111101110110001000101010111111100001100010100101001000000" when "0100111111",
"01000101010110000111101110110001000101010111111100001100010100101001000000" when "0101000000",
"01000101101011000111001100101010101100111110110111001101011001101111110000" when "0101000001",
"01000101101011000111001100101010101100111110110111001101011001101111110000" when "0101000010",
"01000110000000001000011000110111110001100010101101111101000000000011011110" when "0101000011",
"01000110010101001011010011101010011011110000101111101001011110111001110110" when "0101000100",
"01000110010101001011010011101010011011110000101111101001011110111001110110" when "0101000101",
"01000110101010001111111101010100111000110100110011111011000001010100101100" when "0101000110",
"01000110101010001111111101010100111000110100110011111011000001010100101100" when "0101000111",
"01000110111111010110010110001001011010011010111001010011011101101010100010" when "0101001000",
"01000110111111010110010110001001011010011010111001010011011101101010100010" when "0101001001",
"01000111010100011110011110011010010110110000100100010101001100110011111000" when "0101001010",
"01000111101001101000010110011010001000100110011111010001010100010010110001" when "0101001011",
"01000111101001101000010110011010001000100110011111010001010100010010110001" when "0101001100",
"01000111111110110011111110011011001111010001111010011101010110110101000101" when "0101001101",
"01000111111110110011111110011011001111010001111010011101010110110101000101" when "0101001110",
"01001000010100000001010110110000001110101110001101010000111110111101011101" when "0101001111",
"01001000010100000001010110110000001110101110001101010000111110111101011101" when "0101010000",
"01001000101001010000011111101011101111011110010111101011110111101001111110" when "0101010001",
"01001000111110100001011001100000011110101110100100100100000110111011011110" when "0101010010",
"01001000111110100001011001100000011110101110100100100100000110111011011110" when "0101010011",
"01001001010011110100000100100001001110010101101100011101011110101100000100" when "0101010100",
"01001001010011110100000100100001001110010101101100011101011110101100000100" when "0101010101",
"01001001101001001000100001000000110100110110111001001001111000001110111110" when "0101010110",
"01001001101001001000100001000000110100110110111001001001111000001110111110" when "0101010111",
"01001001111110011110101111010010001101100011001001110011001110111111111110" when "0101011000",
"01001010010011110110101111101000011000011010110111101111001111010100100011" when "0101011001",
"01001010010011110110101111101000011000011010110111101111001111010100100011" when "0101011010",
"01001010101001010000100010010110011010001111011011111101001110001101010101" when "0101011011",
"01001010101001010000100010010110011010001111011011111101001110001101010101" when "0101011100",
"01001010111110101100000111101111011100100100110101001110011111010010010100" when "0101011101",
"01001010111110101100000111101111011100100100110101001110011111010010010100" when "0101011110",
"01001011010100001001100000000110101101110011001110111001011110010001000110" when "0101011111",
"01001011010100001001100000000110101101110011001110111001011110010001000110" when "0101100000",
"01001011101001101000101011101111100001001000101000011000000001100000100101" when "0101100001",
"01001011111111001001101010111101001110101010011101010001001011011010110000" when "0101100010",
"01001011111111001001101010111101001110101010011101010001001011011010110000" when "0101100011",
"01001100010100101100011110000011010011010111001110001110110000101001011010" when "0101100100",
"01001100010100101100011110000011010011010111001110001110110000101001011010" when "0101100101",
"01001100101010010001000101010101010001001000001010011111001001010000001010" when "0101100110",
"01001100101010010001000101010101010001001000001010011111001001010000001010" when "0101100111",
"01001100111111110111100001000110101110110010111010000011100011001010101010" when "0101101000",
"01001100111111110111100001000110101110110010111010000011100011001010101010" when "0101101001",
"01001101010101011111110001101011011000001011001000101011001100100011101101" when "0101101010",
"01001101010101011111110001101011011000001011001000101011001100100011101101" when "0101101011",
"01001101101011001001110111010110111110000100010001011011101100110110110001" when "0101101100",
"01001110000000110101110010011101010110010011001011000111000011011011011000" when "0101101101",
"01001110000000110101110010011101010110010011001011000111000011011011011000" when "0101101110",
"01001110010110100011100011010010011011101111110101001111100011000111010101" when "0101101111",
"01001110010110100011100011010010011011101111110101001111100011000111010101" when "0101110000",
"01001110101100010011001010001010001110010111000101111010000010000010001000" when "0101110001",
"01001110101100010011001010001010001110010111000101111010000010000010001000" when "0101110010",
"01001111000010000100100111011000110011001100011000001110110101010010110110" when "0101110011",
"01001111000010000100100111011000110011001100011000001110110101010010110110" when "0101110100",
"01001111010111110111111011010010010100011011011011101001110000011110101011" when "0101110101",
"01001111010111110111111011010010010100011011011011101001110000011110101011" when "0101110110",
"01001111101101101101000110001011000001011010000011111001100000111101011010" when "0101110111",
"01010000000011100100001000010111001110101001111001101110111101010111010001" when "0101111000",
"01010000000011100100001000010111001110101001111001101110111101010111010001" when "0101111001",
"01010000011001011101000010001011010101111010001100011100100001101101110110" when "0101111010",
"01010000011001011101000010001011010101111010001100011100100001101101110110" when "0101111011",
"01010000101111010111110011111011110110001001100100000110010001000000111110" when "0101111100",
"01010000101111010111110011111011110110001001100100000110010001000000111110" when "0101111101",
"01010001000101010100011101111101010011100111110100100010110101001110110110" when "0101111110",
"01010001000101010100011101111101010011100111110100100010110101001110110110" when "0101111111",
"01010001011011010011000000100100010111110111110001001101110110111110001100" when "0110000000",
"01010001011011010011000000100100010111110111110001001101110110111110001100" when "0110000001",
"01010001110001010011011100000101110001110001000001101100000110001111101101" when "0110000010",
"01010001110001010011011100000101110001110001000001101100000110001111101101" when "0110000011",
"01010010000111010101110000110110010101100001110111000001101110000100011010" when "0110000100",
"01010010000111010101110000110110010101100001110111000001101110000100011010" when "0110000101",
"01010010011101011001111111001010111100110001000001111011001100110100110110" when "0110000110",
"01010010011101011001111111001010111100110001000001111011001100110100110110" when "0110000111",
"01010010110011100000000111011000100110011111101001101001001011100101111111" when "0110001000",
"01010011001001101000001001110100010111001011000011101111101110110111001010" when "0110001001",
"01010011001001101000001001110100010111001011000011101111101110110111001010" when "0110001010",
"01010011011111110010000110110011011000101110101100101001011011010101111000" when "0110001011",
"01010011011111110010000110110011011000101110101100101001011011010101111000" when "0110001100",
"01010011110101111101111110101010111010100110000000111110101001110011010011" when "0110001101",
"01010011110101111101111110101010111010100110000000111110101001110011010011" when "0110001110",
"01010100001100001011110001110000010001101110010111110001100101001000000110" when "0110001111",
"01010100001100001011110001110000010001101110010111110001100101001000000110" when "0110010000",
"01010100100010011011100000011000111000101000111101011111001110000100000011" when "0110010001",
"01010100100010011011100000011000111000101000111101011111001110000100000011" when "0110010010",
"01010100111000101101001010111010001111011100101111110110000000010111001000" when "0110010011",
"01010100111000101101001010111010001111011100101111110110000000010111001000" when "0110010100",
"01010101001111000000110001101001111011111000011010100010010101010011000000" when "0110010101",
"01010101001111000000110001101001111011111000011010100010010101010011000000" when "0110010110",
"01010101100101010110010100111101101001010100010100110001011111110100101100" when "0110010111",
"01010101100101010110010100111101101001010100010100110001011111110100101100" when "0110011000",
"01010101111011101101110101001011001000110100011111101011011110110111101110" when "0110011001",
"01010101111011101101110101001011001000110100011111101011011110110111101110" when "0110011010",
"01010110010010000111010010101000010001001010100101100100000010100101100010" when "0110011011",
"01010110010010000111010010101000010001001010100101100100000010100101100010" when "0110011100",
"01010110101000100010101101101010111110110111111010000011100001100100111110" when "0110011101",
"01010110101000100010101101101010111110110111111010000011100001100100111110" when "0110011110",
"01010110111111000000000110101001010100001111011011000111111011100000101001" when "0110011111",
"01010110111111000000000110101001010100001111011011000111111011100000101001" when "0110100000",
"01010111010101011111011101111001011001010111110010111110100110101011111100" when "0110100001",
"01010111010101011111011101111001011001010111110010111110100110101011111100" when "0110100010",
"01010111101100000000110011110001011100001101011010110111000110100001001000" when "0110100011",
"01010111101100000000110011110001011100001101011010110111000110100001001000" when "0110100100",
"01011000000010100100001000100111110000100100011110101111101001000101110111" when "0110100101",
"01011000000010100100001000100111110000100100011110101111101001000101110111" when "0110100110",
"01011000011001001001011100110010110000001011000001111011101010010101000000" when "0110100111",
"01011000011001001001011100110010110000001011000001111011101010010101000000" when "0110101000",
"01011000101111110000110000101000111010101011000100100100111011100000110010" when "0110101001",
"01011000101111110000110000101000111010101011000100100100111011100000110010" when "0110101010",
"01011001000110011010000100100000110101101100101010000111101110010010010111" when "0110101011",
"01011001000110011010000100100000110101101100101010000111101110010010010111" when "0110101100",
"01011001011101000101011000110001001100111000000000101010100010011111101010" when "0110101101",
"01011001011101000101011000110001001100111000000000101010100010011111101010" when "0110101110",
"01011001110011110010101101110000110001110111101001010001110110100011101010" when "0110101111",
"01011001110011110010101101110000110001110111101001010001110110100011101010" when "0110110000",
"01011010001010100010000011110110011100011010100001010000011010011001001110" when "0110110001",
"01011010001010100010000011110110011100011010100001010000011010011001001110" when "0110110010",
"01011010100001010011011011011001001010010110001100010100100101001100001010" when "0110110011",
"01011010100001010011011011011001001010010110001100010100100101001100001010" when "0110110100",
"01011010111000000110110100101111111111101000111111110011001110101000011010" when "0110110101",
"01011010111000000110110100101111111111101000111111110011001110101000011010" when "0110110110",
"01011011001110111100010000010010000110011100001110110000101100100100010010" when "0110110111",
"01011011001110111100010000010010000110011100001110110000101100100100010010" when "0110111000",
"01011011100101110011101110010110101111000110010111001000010110010101111100" when "0110111001",
"01011011100101110011101110010110101111000110010111001000010110010101111100" when "0110111010",
"01011011111100101101001111010101010000001101001111110011001111011010100000" when "0110111011",
"01011011111100101101001111010101010000001101001111110011001111011010100000" when "0110111100",
"01011100010011101000110011100101000110101000010111101110011011001001100010" when "0110111101",
"01011100010011101000110011100101000110101000010111101110011011001001100010" when "0110111110",
"01011100101010100110011011011101110101100011000110000001011100000100110010" when "0110111111",
"01011100101010100110011011011101110101100011000110000001011100000100110010" when "0111000000",
"01011101000001100110000111010111000110011110111011000101100001001010010100" when "0111000001",
"01011101000001100110000111010111000110011110111011000101100001001010010100" when "0111000010",
"01011101011000100111110111101000101001010101110010101110000100000100001010" when "0111000011",
"01011101011000100111110111101000101001010101110010101110000100000100001010" when "0111000100",
"01011101101111101011101100101010010100011100010111010010111011100111001010" when "0111000101",
"01011101101111101011101100101010010100011100010111010010111011100111001010" when "0111000110",
"01011110000110110001100110110100000100100100010101111101000110001000101000" when "0111000111",
"01011110000110110001100110110100000100100100010101111101000110001000101000" when "0111001000",
"01011110000110110001100110110100000100100100010101111101000110001000101000" when "0111001001",
"01011110011101111001100110011101111100111110110011110110001111101001011110" when "0111001010",
"01011110011101111001100110011101111100111110110011110110001111101001011110" when "0111001011",
"01011110110101000011101100000000000111011110100100011011111000001011011000" when "0111001100",
"01011110110101000011101100000000000111011110100100011011111000001011011000" when "0111001101",
"01011111001100001111110111110010110100011010100000110110011110111100100000" when "0111001110",
"01011111001100001111110111110010110100011010100000110110011110111100100000" when "0111001111",
"01011111100011011110001010001110011010110000000000010101010111011101000110" when "0111010000",
"01011111100011011110001010001110011010110000000000010101010111011101000110" when "0111010001",
"01011111111010101110100011101011011000000101010001101111101101111001110000" when "0111010010",
"01011111111010101110100011101011011000000101010001101111101101111001110000" when "0111010011",
"01100000010010000001000100100010010000101011110110001011100000101101011010" when "0111010100",
"01100000010010000001000100100010010000101011110110001011100000101101011010" when "0111010101",
"01100000101001010101101101001011101111100010111100101010110101010101110100" when "0111010110",
"01100000101001010101101101001011101111100010111100101010110101010101110100" when "0111010111",
"01100001000000101100011110000000100110011001111111000000001110111101110111" when "0111011000",
"01100001000000101100011110000000100110011001111111000000001110111101110111" when "0111011001",
"01100001011000000101010111011001101101110010111111101010101101111001100110" when "0111011010",
"01100001011000000101010111011001101101110010111111101010101101111001100110" when "0111011011",
"01100001011000000101010111011001101101110010111111101010101101111001100110" when "0111011100",
"01100001101111100000011001110000000101000101001000111001111111001000111100" when "0111011101",
"01100001101111100000011001110000000101000101001000111001111111001000111100" when "0111011110",
"01100010000110111101100101011100110010011111001100111011100011101111000001" when "0111011111",
"01100010000110111101100101011100110010011111001100111011100011101111000001" when "0111100000",
"01100010011110011100111010111001000011001010000111010001011000000110000100" when "0111100001",
"01100010011110011100111010111001000011001010000111010001011000000110000100" when "0111100010",
"01100010110101111110011010011110001011001011011111010010100011110000110100" when "0111100011",
"01100010110101111110011010011110001011001011011111010010100011110000110100" when "0111100100",
"01100011001101100010000100100101100101101000001011110110111010100101011010" when "0111100101",
"01100011001101100010000100100101100101101000001011110110111010100101011010" when "0111100110",
"01100011100101000111111001101000110100100110111000001101111000100111011001" when "0111100111",
"01100011100101000111111001101000110100100110111000001101111000100111011001" when "0111101000",
"01100011100101000111111001101000110100100110111000001101111000100111011001" when "0111101001",
"01100011111100101111111010000001100001010010101010000001100010100001100010" when "0111101010",
"01100011111100101111111010000001100001010010101010000001100010100001100010" when "0111101011",
"01100100010100011010000110001001011011111101101000100110010100101011010001" when "0111101100",
"01100100010100011010000110001001011011111101101000100110010100101011010001" when "0111101101",
"01100100101100000110011110011010011100000011100101011000001011100000011101" when "0111101110",
"01100100101100000110011110011010011100000011100101011000001011100000011101" when "0111101111",
"01100101000011110101000011001110100000001100100101100101110000001110010010" when "0111110000",
"01100101000011110101000011001110100000001100100101100101110000001110010010" when "0111110001",
"01100101011011100101110100111111101110001111101101001010010101010011111010" when "0111110010",
"01100101011011100101110100111111101110001111101101001010010101010011111010" when "0111110011",
"01100101011011100101110100111111101110001111101101001010010101010011111010" when "0111110100",
"01100101110011011000110100001000010011010101101010110111001110110001011011" when "0111110101",
"01100101110011011000110100001000010011010101101010110111001110110001011011" when "0111110110",
"01100110001011001110000001000010100011111011100101101101010010011101001100" when "0111110111",
"01100110001011001110000001000010100011111011100101101101010010011101001100" when "0111111000",
"01100110100011000101011100001000111011110101101011100111001101010011010101" when "0111111001",
"01100110100011000101011100001000111011110101101011100111001101010011010101" when "0111111010",
"01100110111010111111000101110101111110010010000001010101011010110001110000" when "0111111011",
"01100110111010111111000101110101111110010010000001010101011010110001110000" when "0111111100",
"01100110111010111111000101110101111110010010000001010101011010110001110000" when "0111111101",
"01100111010010111010111110100100010101111011010011101100001100001111011110" when "0111111110",
"01100111010010111010111110100100010101111011010011101100001100001111011110" when "0111111111",
"10110110001110010111100110110111000000011110101100001011000011100000101000" when "1000000000",
"10110110011010010111100000110111001100011110011101001011011101111001100100" when "1000000001",
"10110110100110010111111110111000100000100010011100011000010000111101110111" when "1000000010",
"10110110110010011001000000111110010101000100000000011101110101111000000100" when "1000000011",
"10110110111110011010100111001100000010111010111111110000000000001100111000" when "1000000100",
"10110111001010011100110001100101000011011101110101111000111011010000011000" when "1000000101",
"10110111001010011100110001100101000011011101110101111000111011010000011000" when "1000000110",
"10110111010110011111100000001100110000100001101001101001011101101111011000" when "1000000111",
"10110111100010100010110011000110100100011010010010101010110100000100110110" when "1000001000",
"10110111101110100110101010010101111001111010011111010001100001110100011000" when "1000001001",
"10110111111010101011000101111110001100010011111010010001111010100001111010" when "1000001010",
"10111000000110110000000110000010110111010111010000110101110010011111111000" when "1000001011",
"10111000010010110101101010100111010111010100011000010011100111101100001010" when "1000001100",
"10111000011110111011110011101111001000111010010100000111000011010101011001" when "1000001101",
"10111000011110111011110011101111001000111010010100000111000011010101011001" when "1000001110",
"10111000101011000010100001011101101001010111011011101010110100100001011101" when "1000001111",
"10111000110111001001110011110110010110011001100000010100000100001110010111" when "1000010000",
"10111001000011010001101010111100101110001101110011001111000011000111010010" when "1000010001",
"10111001001111011010000110110100001111100001001011011101010001100110110111" when "1000010010",
"10111001011011100011000111100000011001100000001011110101000010100000110010" when "1000010011",
"10111001100111101100101101000100101011110111001001000010011000101100001100" when "1000010100",
"10111001110011110110110111100100100110110010001111101001100000001001000011" when "1000010101",
"10111001110011110110110111100100100110110010001111101001100000001001000011" when "1000010110",
"10111010000000000001100111000011101010111101101010001010100010111010011101" when "1000010111",
"10111010001100001100111011100101011001100101100111000110111010010000000001" when "1000011000",
"10111010011000011000110101001101010100010110011111000111111100011000110100" when "1000011001",
"10111010100100100101010011111110111101011100111011000111000111011010010100" when "1000011010",
"10111010110000110010010111111101110111100101111010010111101001100101111000" when "1000011011",
"10111010111101000000000001001101100101111110111000110001100111100111101001" when "1000011100",
"10111010111101000000000001001101100101111110111000110001100111100111101001" when "1000011101",
"10111011001001001110001111110001101100010101110100111110100001001001101000" when "1000011110",
"10111011010101011101000011101101101110111001010110100111010100000110000101" when "1000011111",
"10111011100001101100011101000101010010011000110100100011111111000100100000" when "1000100000",
"10111011101101111100011011111011111100000100011011001100100011011100001010" when "1000100001",
"10111011111010001101000000010101010001101101010010101011100111011000000110" when "1000100010",
"10111100000110011110001010010100111001100101100101010010011000010111111100" when "1000100011",
"10111100000110011110001010010100111001100101100101010010011000010111111100" when "1000100100",
"10111100010010101111111001111110011010100000100101101110001110101001010000" when "1000100101",
"10111100011111000010001111010101011011110010110101011111110001110101100010" when "1000100110",
"10111100101011010101001010011101100101010010001011010011011111100000100111" when "1000100111",
"10111100110111101000101011011010011111010101111001011011110011110100000000" when "1000101000",
"10111101000011111100110010001111110010110110110100001100110100110011001110" when "1000101001",
"10111101010000010001011111000001001001001111011000011001100000110101101110" when "1000101010",
"10111101010000010001011111000001001001001111011000011001100000110101101110" when "1000101011",
"10111101011100100110110001110010001100011011110001110010100000100011000000" when "1000101100",
"10111101101000111100101010100110100110111010000001100110011100101101111110" when "1000101101",
"10111101110101010011001001100010000011101010000101000011111000101011111101" when "1000101110",
"10111110000001101010001110101000001110001101111011111100110001100100111101" when "1000101111",
"10111110001110000001111001111100110010101001101111001011100010111010010000" when "1000110000",
"10111110001110000001111001111100110010101001101111001011100010111010010000" when "1000110001",
"10111110011010011010001011100011011101100011110111011001110001000000100110" when "1000110010",
"10111110100110110011000011011111111100000101000011101000011001101011110100" when "1000110011",
"10111110110011001100100001110101111011111000011111111001101011101001010001" when "1000110100",
"10111110111111100110100110101001001011001011111011111100100101000111011000" when "1000110101",
"10111111001100000001010001111101011000101111110001111001111010000111110110" when "1000110110",
"10111111001100000001010001111101011000101111110001111001111010000111110110" when "1000110111",
"10111111011000011100100011110110010011110111001101000011000010111011000110" when "1000111000",
"10111111100100111000011100010111101100011000010000100010010011000011001101" when "1000111001",
"10111111110001010100111011100101010010101011111110001100111001011100101011" when "1000111010",
"10111111111101110010000001100010110111101110011101010110101010001011111101" when "1000111011",
"10111111111101110010000001100010110111101110011101010110101010001011111101" when "1000111100",
"11000000001010001111101110010100001100111111000001100111010010001110011010" when "1000111101",
"11000000010110101110000001111101000100100000010001110001010101101101110011" when "1000111110",
"11000000100011001100111100100001010000111000001110101010111001010101010110" when "1000111111",
"11000000101111101100011110000100100101010000011010000111110111000111111011" when "1001000000",
"11000000111100001100100110101010110101010101111101110101111111010110101001" when "1001000001",
"11000000111100001100100110101010110101010101111101110101111111010110101001" when "1001000010",
"11000001001000101101010110010111110101011001110010011010100101110111101011" when "1001000011",
"11000001010101001110101101001111011010010000100110010001111100011101000001" when "1001000100",
"11000001100001110000101011010101011001010011000100110000011010101011011001" when "1001000101",
"11000001101110010011010000101101101000011101111101000101010011110001010000" when "1001000110",
"11000001101110010011010000101101101000011101111101000101010011110001010000" when "1001000111",
"11000001111010110110011101011011111110010010001001011111011010111110011100" when "1001001000",
"11000010000111011010010001100100010001110100110110010011010110111100111001" when "1001001001",
"11000010010011111110101101001010011010101111101001000011100100101011001000" when "1001001010",
"11000010100000100011110000010010010001010000100111101010001010011001100010" when "1001001011",
"11000010101101001001011010111111101110001010011111100100011011001011001110" when "1001001100",
"11000010101101001001011010111111101110001010011111100100011011001011001110" when "1001001101",
"11000010111001101111101101010110101010110100101101000000001011011100000010" when "1001001110",
"11000011000110010110100111011011000001001011100010001010110111001100110010" when "1001001111",
"11000011010010111110001001010000101011110000001110100010011010010111101000" when "1001010000",
"11000011011111100110010010111011100101101001000110000111111011101110000010" when "1001010001",
"11000011011111100110010010111011100101101001000110000111111011101110000010" when "1001010010",
"11000011101100001111000100011111101010100001101000110100001011000010101100" when "1001010011",
"11000011111000111000011110000000110110101010101001101101110011000000111111" when "1001010100",
"11000100000101100010011111100011000110111010010110100001011111010100111101" when "1001010101",
"11000100010010001101001001001010011000101100011110111011110111100101110001" when "1001010110",
"11000100010010001101001001001010011000101100011110111011110111100101110001" when "1001010111",
"11000100011110111000011010111010101010000010011100000101001111100101100111" when "1001011000",
"11000100101011100100010100110111111001100011010111111111001101011001111101" when "1001011001",
"11000100111000010000110111000110000110011100010101000100000101111111000100" when "1001011010",
"11000101000100111110000001101001010000100000010101101000010000101010001011" when "1001011011",
"11000101000100111110000001101001010000100000010101101000010000101010001011" when "1001011100",
"11000101010001101011110100100101011000001000100011011101010010001101111000" when "1001011101",
"11000101011110011010001111111110011110010100010111010111000000000011111110" when "1001011110",
"11000101101011001001010011111000100100101001100000110010011100000001001010" when "1001011111",
"11000101101011001001010011111000100100101001100000110010011100000001001010" when "1001100000",
"11000101110111111001000000010111101101010100001101011110101001010110010000" when "1001100001",
"11000110000100101001010101011111111011000111010001000111011011100011001100" when "1001100010",
"11000110010001011010010011010101010001011100001101000001111111100000011010" when "1001100011",
"11000110011110001011111001111011110100010011010111111011011111100011001011" when "1001100100",
"11000110011110001011111001111011110100010011010111111011011111100011001011" when "1001100101",
"11000110101010111110001001010111101000010100000101101001100011000001100011" when "1001100110",
"11000110110111110001000001101100110010101100101110111100101001111011010001" when "1001100111",
"11000111000100100100100010111111011001010010111001010100100101001100100110" when "1001101000",
"11000111010001011000101101010011100010100011011110110110101100010000100110" when "1001101001",
"11000111010001011000101101010011100010100011011110110110101100010000100110" when "1001101010",
"11000111011110001101100000101101010101100010110110000110010000011000101101" when "1001101011",
"11000111101011000010111101010000111001111100111001111110101110011110111110" when "1001101100",
"11000111110111111001000011000010011000000101010001101111111111111001101000" when "1001101101",
"11000111110111111001000011000010011000000101010001101111111111111001101000" when "1001101110",
"11001000000100101111110010000101111000110111011000111100101010110101110000" when "1001101111",
"11001000010001100111001010011111100101110110100111011010010010111111110111" when "1001110000",
"11001000011110011111001100010011101001001110011001010011101011000000110010" when "1001110001",
"11001000011110011111001100010011101001001110011001010011101011000000110010" when "1001110010",
"11001000101011010111110111100110001101110010010111001101000111010110000100" when "1001110011",
"11001000111000010001001100011011011110111110011110001010110011001100111000" when "1001110100",
"11001001000101001011001010110111101000110111000111111001001000000110100011" when "1001110101",
"11001001010010000101110010111110111000001001010010110111001000101110110000" when "1001110110",
"11001001010010000101110010111110111000001001010010110111001000101110110000" when "1001110111",
"11001001011111000001000100110101011010001010101010100010111111101010100110" when "1001111000",
"11001001101011111101000000011111011100111001101111101000100010101001000010" when "1001111001",
"11001001111000111001100110000001001110111110000000010001111010111100011100" when "1001111010",
"11001001111000111001100110000001001110111110000000010001111010111100011100" when "1001111011",
"11001010000101110110110101011110111111101000000000011010010011100110001101" when "1001111100",
"11001010010010110100101110111100111110110001100010000010101101111100100000" when "1001111101",
"11001010011111110011010010011111011100111101101101101000111101010011100110" when "1001111110",
"11001010011111110011010010011111011100111101101101101000111101010011100110" when "1001111111",
"11001010101100110010100000001010101011011001001010100000101010010011011010" when "1010000000",
"11001010111001110010011000000010111011111010000111001110011110100011000100" when "1010000001",
"11001011000110110010111010001100100001000000100010000101011001010011011110" when "1010000010",
"11001011000110110010111010001100100001000000100010000101011001010011011110" when "1010000011",
"11001011010011110100000110101011101101110110010001100110001101110011011000" when "1010000100",
"11001011100000110101111101100100110110001111001101000001001011110110010011" when "1010000101",
"11001011101101111000011110111100001110101001010100111001110011011001001000" when "1010000110",
"11001011101101111000011110111100001110101001010100111001110011011001001000" when "1010000111",
"11001011111010111011101010110110001100001100111011101100110011101110011010" when "1010001000",
"11001100000111111111100001010111000100101100101110011000010110111101101000" when "1010001001",
"11001100010101000100000010100011001110100101111101000110011010011111110001" when "1010001010",
"11001100010101000100000010100011001110100101111101000110011010011111110001" when "1010001011",
"11001100100010001001001110011111000001000000100011111001010101000101000100" when "1010001100",
"11001100101111001111000101001110110011101111010011011010101011001110111000" when "1010001101",
"11001100111100010101100110110110111111001111111001101100010010101001101100" when "1010001110",
"11001100111100010101100110110110111111001111111001101100010010101001101100" when "1010001111",
"11001101001001011100110011011011111100101011001010111011100101010011000110" when "1010010000",
"11001101010110100100101011000010000101110101001010010111000100110111110110" when "1010010001",
"11001101100011101101001101101101110101001101010011000110001111010110101001" when "1010010010",
"11001101100011101101001101101101110101001101010011000110001111010110101001" when "1010010011",
"11001101110000110110011011100011100101111110100001000011100101010100001000" when "1010010100",
"11001101111110000000010100100111110011111111011001111001000010101101010000" when "1010010101",
"11001110001011001010111000111110111011110010010101111110101010110100111011" when "1010010110",
"11001110001011001010111000111110111011110010010101111110101010110100111011" when "1010010111",
"11001110011000010110001000101101011010100101101001011011101000001010101001" when "1010011000",
"11001110100101100010000011110111101110010011101101001001100000110111110000" when "1010011001",
"11001110110010101110101010100010010101100011000111111010000000100001001011" when "1010011010",
"11001110110010101110101010100010010101100011000111111010000000100001001011" when "1010011011",
"11001110111111111011111100110001101111100110110111011110110111111100000000" when "1010011100",
"11001111001101001001111010101010011100011110011001110100010011110011010011" when "1010011101",
"11001111011010011000100100010000111100110101110110001101101010101101111101" when "1010011110",
"11001111011010011000100100010000111100110101110110001101101010101101111101" when "1010011111",
"11001111100111100111111001101001110010000110000110100100100011100011100100" when "1010100000",
"11001111110100110111111010111001011110010101000000101010010100101111100100" when "1010100001",
"11001111110100110111111010111001011110010101000000101010010100101111100100" when "1010100010",
"11010000000010001000101000000100100100010101011111011011111101010010010010" when "1010100011",
"11010000001111011010000001001111100111100111101100011000011000001111100010" when "1010100100",
"11010000011100101100000110011111001100011001001000111001001011011011001100" when "1010100101",
"11010000011100101100000110011111001100011001001000111001001011011011001100" when "1010100110",
"11010000101001111110110111110111110111100100110111101101110010000011100101" when "1010100111",
"11010000110111010010010101011110001110110011100110011001000100001010110010" when "1010101000",
"11010000110111010010010101011110001110110011100110011001000100001010110010" when "1010101001",
"11010001000100100110011111010110111000011011110110110001011011011111100110" when "1010101010",
"11010001010001111011010101100110011011100010001000100011010110100111010001" when "1010101011",
"11010001011111010000111000010001011111111001000010110110011011001001100100" when "1010101100",
"11010001011111010000111000010001011111111001000010110110011011001001100100" when "1010101101",
"11010001101100100111000111011100101110000001011101110100110111110000111010" when "1010101110",
"11010001111001111110000011001100101111001010101100010101100110110000100101" when "1010101111",
"11010010000111010101101011100110001101010010100101101000110010000011011011" when "1010110000",
"11010010000111010101101011100110001101010010100101101000110010000011011011" when "1010110001",
"11010010010100101110000000101101110011000101101111000110111001010101011100" when "1010110010",
"11010010100010000111000010101000001011111111100110000010011011001011011100" when "1010110011",
"11010010100010000111000010101000001011111111100110000010011011001011011100" when "1010110100",
"11010010101111100000110001011010000100001010101001011100000001111011101110" when "1010110101",
"11010010111100111011001101001000001000100000100011111001010101001011011000" when "1010110110",
"11010011001010010110010101110111000110101010010101011110010000100100000001" when "1010110111",
"11010011001010010110010101110111000110101010010101011110010000100100000001" when "1010111000",
"11010011010111110010001011101011101101000000011101101001000000110101110110" when "1010111001",
"11010011100101001110101110101010101010101011000101010000100111111010101001" when "1010111010",
"11010011100101001110101110101010101010101011000101010000100111111010101001" when "1010111011",
"11010011110010101011111110111000101111100010001000100110001000101110010000" when "1010111100",
"11010100000000001001111100011010101100001101100001011000011011110001100001" when "1010111101",
"11010100000000001001111100011010101100001101100001011000011011110001100001" when "1010111110",
"11010100001101101000100111010101010010000101010000111010101101001100111100" when "1010111111",
"11010100011011000111111111101101010011010001101010001101100101001000110011" when "1011000000",
"11010100101000101000000101100111100010101011011100001010111011010000100000" when "1011000001",
"11010100101000101000000101100111100010101011011100001010111011010000100000" when "1011000010",
"11010100110110001000111001001000110011111011111011110100010110010111010010" when "1011000011",
"11010101000011101010011010010101111011011101001110100100011000110101000110" when "1011000100",
"11010101000011101010011010010101111011011101001110100100011000110101000110" when "1011000101",
"11010101010001001100101001010011101110011010010100100010011010110010001010" when "1011000110",
"11010101011110101111100110000111000010101111010010111001010010111000100101" when "1011000111",
"11010101011110101111100110000111000010101111010010111001010010111000100101" when "1011001000",
"11010101101100010011010000110100101111001001011110010000101110100011100000" when "1011001001",
"11010101111001110111101001100001101011000111100101001001011010100011010111" when "1011001010",
"11010110000111011100110000010010101110111001111010011011111100101111101100" when "1011001011",
"11010110000111011100110000010010101110111001111010011011111100101111101100" when "1011001100",
"11010110010101000010100101001100110011100010011111111010011111111110101001" when "1011001101",
"11010110100010101001001000010100110010110101010000110101010010111011010000" when "1011001110",
"11010110100010101001001000010100110010110101010000110101010010111011010000" when "1011001111",
"11010110110000010000011001101111100111011000001100100001111010110011010000" when "1011010000",
"11010110111101111000011001100010001100100011100001000101011010110110001110" when "1011010001",
"11010110111101111000011001100010001100100011100001000101011010110110001110" when "1011010010",
"11010111001011100001000111110001011110100001110110000001010001011111100011" when "1011010011",
"11010111011001001010100100100010011010010000010111000011001100000101100001" when "1011010100",
"11010111011001001010100100100010011010010000010111000011001100000101100001" when "1011010101",
"11010111100110110100101111111001111101011110111110110111110010000111110010" when "1011010110",
"11010111110100011111101001111101000110110000100010000000001000111000010000" when "1011010111",
"11010111110100011111101001111101000110110000100010000000001000111000010000" when "1011011000",
"11011000000010001011010010110000110101011010111001101010010000011001010011" when "1011011001",
"11011000001111110111101010011010001001100111001110101100011010101100111010" when "1011011010",
"11011000011101100100110000111110000100010010000100100011011110010000100101" when "1011011011",
"11011000011101100100110000111110000100010010000100100011011110010000100101" when "1011011100",
"11011000101011010010100110100001100111001011100100010100000100100010000011" when "1011011101",
"11011000111001000001001011001001110100110111100111101110110101101001100010" when "1011011110",
"11011000111001000001001011001001110100110111100111101110110101101001100010" when "1011011111",
"11011001000110110000011110111011110000101110000100010111100010000110010011" when "1011100000",
"11011001010100100000100001111100011110111010110110101111001011011010110010" when "1011100001",
"11011001010100100000100001111100011110111010110110101111001011011010110010" when "1011100010",
"11011001100010010001010100010001000100011110001101100001001100110101110100" when "1011100011",
"11011001110000000010110101111110100111001100110100110011100100110111001011" when "1011100100",
"11011001110000000010110101111110100111001100110100110011100100110111001011" when "1011100101",
"11011001111101110101000111001010001101110000000001011010000000101101011101" when "1011100110",
"11011010001011101000000111111000111111100101111100001100001010101100001010" when "1011100111",
"11011010001011101000000111111000111111100101111100001100001010101100001010" when "1011101000",
"11011010011001011011111000010000000101000001101101011110111100011001000111" when "1011101001",
"11011010100111010000011000010100100111001011101000100000110101110000011101" when "1011101010",
"11011010100111010000011000010100100111001011101000100000110101110000011101" when "1011101011",
"11011010110101000101101000001011110000000001010110111001011001111111010001" when "1011101100",
"11011011000010111011100111111010101010010110000100001011110011010100110100" when "1011101101",
"11011011000010111011100111111010101010010110000100001011110011010100110100" when "1011101110",
"11011011010000110010010111100110100001110010101001011100011110101011000100" when "1011101111",
"11011011011110101001110111010100100010110101111000111010000000000111100100" when "1011110000",
"11011011011110101001110111010100100010110101111000111010000000000111100100" when "1011110001",
"11011011101100100010000111001001111010110100101001101001000001010101110000" when "1011110010",
"11011011111010011011000111001011110111111010000011010011011010111100101110" when "1011110011",
"11011011111010011011000111001011110111111010000011010011011010111100101110" when "1011110100",
"11011100001000010100110111011111101001000111101001111010101001110010010000" when "1011110101",
"11011100010110001111011000001010011110010101101001101101010001001101111101" when "1011110110",
"11011100010110001111011000001010011110010101101001101101010001001101111101" when "1011110111",
"11011100100100001010101001010001101000010011000010111111101011011111010000" when "1011111000",
"11011100110010000110101010111010011000100101110110001000001001001001011000" when "1011111001",
"11011100110010000110101010111010011000100101110110001000001001001001011000" when "1011111010",
"11011101000000000011011101001010000001101011001111011110000000101001011111" when "1011111011",
"11011101001110000001000000000101110110110111110011011100001111001010100000" when "1011111100",
"11011101001110000001000000000101110110110111110011011100001111001010100000" when "1011111101",
"11011101011011111111010011110011001100010111101010100111001011101011110000" when "1011111110",
"11011101101001111110011000010111010111001110101101110101101101011110110001" when "1011111111",
"11011101101001111110011000010111010111001110101101110101101101011110110001" when "1100000000",
"11011101110111111110001101110111101101011000110010011101100111000010000110" when "1100000001",
"11011110000101111110110100011001100101101001110110100011010110011110100010" when "1100000010",
"11011110000101111110110100011001100101101001110110100011010110011110100010" when "1100000011",
"11011110010100000000001100000010010111101110001101001101001100101101000100" when "1100000100",
"11011110010100000000001100000010010111101110001101001101001100101101000100" when "1100000101",
"11011110100010000010010100110111011100001010101010111001101100001100001101" when "1100000110",
"11011110110000000101001110111110001100011100110001111001100000101011100011" when "1100000111",
"11011110110000000101001110111110001100011100110001111001100000101011100011" when "1100001000",
"11011110111110001000111010011100000010111010111110101100110000110101001110" when "1100001001",
"11011111001100001101010111010110011010110100110100100011101010111100111010" when "1100001010",
"11011111001100001101010111010110011010110100110100100011101010111100111010" when "1100001011",
"11011111011010010010100101110010110000010011001010000010101101111100110100" when "1100001100",
"11011111101000011000100101110110100000011000010101101010001111101001011101" when "1100001101",
"11011111101000011000100101110110100000011000010101101010001111101001011101" when "1100001110",
"11011111110110011111010111100111001001000000011010100001100001100101001000" when "1100001111",
"11100000000100100110111011001010001001000001010101000101010101011101000111" when "1100010000",
"11100000000100100110111011001010001001000001010101000101010101011101000111" when "1100010001",
"11100000010010101111010000100101000000001011000111111010000010011010010001" when "1100010010",
"11100000010010101111010000100101000000001011000111111010000010011010010001" when "1100010011",
"11100000100000111000010111111101001111001000001000100001001100001111110100" when "1100010100",
"11100000101111000010010001011000010111011101001100010010101101110011001100" when "1100010101",
"11100000101111000010010001011000010111011101001100010010101101110011001100" when "1100010110",
"11100000111101001100111100111011111011101001110101011001100111101000001101" when "1100010111",
"11100001001011011000011010101101011111001000011111110100010100001101110101" when "1100011000",
"11100001001011011000011010101101011111001000011111110100010100001101110101" when "1100011001",
"11100001011001100100101010110010100110001110101110011000100010110111011001" when "1100011010",
"11100001100111110001101101010000110110001101010111111010111010011111011101" when "1100011011",
"11100001100111110001101101010000110110001101010111111010111010011111011101" when "1100011100",
"11100001110101111111100010001101110101010000110100011010000101100001010110" when "1100011101",
"11100001110101111111100010001101110101010000110100011010000101100001010110" when "1100011110",
"11100010000100001110001001101111001010100001001010001101101000000111001010" when "1100011111",
"11100010010010011101100011111010011110000010011011011000100001111010100101" when "1100100000",
"11100010010010011101100011111010011110000010011011011000100001111010100101" when "1100100001",
"11100010100000101101110000110101011000110100110010111111011100100110111010" when "1100100010",
"11100010101110111110110000100101100100110100110010100010101000011011110010" when "1100100011",
"11100010101110111110110000100101100100110100110010100010101000011011110010" when "1100100100",
"11100010111101010000100011010000101100111011011111011011101000000000000000" when "1100100101",
"11100011001011100011001000111100011100111110110000011110101100100100101100" when "1100100110",
"11100011001011100011001000111100011100111110110000011110101100100100101100" when "1100100111",
"11100011011001110110100001101110100001110001011011100000000100001001011110" when "1100101000",
"11100011011001110110100001101110100001110001011011100000000100001001011110" when "1100101001",
"11100011101000001010101101101100101001000011100010111100111010100010101000" when "1100101010",
"11100011110110011111101100111100100001100010100011101000001110110010111100" when "1100101011",
"11100011110110011111101100111100100001100010100011101000001110110010111100" when "1100101100",
"11100100000100110101011111100011111010111001100010011011011110001011011100" when "1100101101",
"11100100010011001100000101101000100101110001011010001011000110000011010101" when "1100101110",
"11100100010011001100000101101000100101110001011010001011000110000011010101" when "1100101111",
"11100100100001100011011111010000010011110001001001011110111101111011110001" when "1100110000",
"11100100100001100011011111010000010011110001001001011110111101111011110001" when "1100110001",
"11100100101111111011101100100000110111011110000000101110101011000010011100" when "1100110010",
"11100100111110010100101101100000000100011011110000000001101110100111110100" when "1100110011",
"11100100111110010100101101100000000100011011110000000001101110100111110100" when "1100110100",
"11100101001100101110100010010011101111001100110101010011110000011101000001" when "1100110101",
"11100101001100101110100010010011101111001100110101010011110000011101000001" when "1100110110",
"11100101011011001001001011000001101101010010101010011100100110101111010001" when "1100110111",
"11100101101001100100100111101111110101001101110011011100011100110101110010" when "1100111000",
"11100101101001100100100111101111110101001101110011011100011100110101110010" when "1100111001",
"11100101111000000000111000100011111110011110001100101011111010001001001000" when "1100111010",
"11100110000110011101111101100100000001100011011001010000001010011010010110" when "1100111011",
"11100110000110011101111101100100000001100011011001010000001010011010010110" when "1100111100",
"11100110010100111011110110110101110111111100110001010011001001000001001101" when "1100111101",
"11100110010100111011110110110101110111111100110001010011001001000001001101" when "1100111110",
"11100110100011011010100100011111011100001001110000011111110000011001101100" when "1100111111",
"11100110110001111010000110100110101001101010000100100010001111001000110010" when "1101000000",
"11100110110001111010000110100110101001101010000100100010001111001000110010" when "1101000001",
"11100111000000011010011101010001011100111101111011101100100100000001101111" when "1101000010",
"11100111000000011010011101010001011100111101111011101100100100000001101111" when "1101000011",
"11100111001110111011101000100101110011100110010011011111000010100101001101" when "1101000100",
"11100111011101011101101000101001101100000101000111010101000001010100010100" when "1101000101",
"11100111011101011101101000101001101100000101000111010101000001010100010100" when "1101000110",
"11100111101100000000011101100011000101111101011111010101110011010010010010" when "1101000111",
"11100111101100000000011101100011000101111101011111010101110011010010010010" when "1101001000",
"11100111111010100100000111011000000001110011111111001001101110001111110001" when "1101001001",
"11101000001001001000100110001110100001001110110100110011011110111011101110" when "1101001010",
"11101000001001001000100110001110100001001110110100110011011110111011101110" when "1101001011",
"11101000010111101101111010001100100110110110000111101101101100110101111010" when "1101001100",
"11101000010111101101111010001100100110110110000111101101101100110101111010" when "1101001101",
"11101000100110010100000011011000010110010100000111101100101111000000001110" when "1101001110",
"11101000110100111011000001110111110100010101011100000100110011001100000000" when "1101001111",
"11101000110100111011000001110111110100010101011100000100110011001100000000" when "1101010000",
"11101001000011100010110101110001000110101001010010110100011001000001101110" when "1101010001",
"11101001000011100010110101110001000110101001010010110100011001000001101110" when "1101010010",
"11101001010010001011011111001010010100000001101111110011000010100001001110" when "1101010011",
"11101001100000110100111110001001100100010011111100000100011011011010010011" when "1101010100",
"11101001100000110100111110001001100100010011111100000100011011011010010011" when "1101010101",
"11101001101111011111010010110101000000011000010101001111111000111100111101" when "1101010110",
"11101001101111011111010010110101000000011000010101001111111000111100111101" when "1101010111",
"11101001111110001010011101010010110010001010111100111100010011100010000100" when "1101011000",
"11101010001100110110011101101001000100101011101000010000011011101101011010" when "1101011001",
"11101010001100110110011101101001000100101011101000010000011011101101011010" when "1101011010",
"11101010011011100011010011111110000011111110001111010111101100001010100100" when "1101011011",
"11101010011011100011010011111110000011111110001111010111101100001010100100" when "1101011100",
"11101010101010010001000000010111111101001010111101001011011010000111001110" when "1101011101",
"11101010111000111111100010111100111110011110011111000000100101101101100010" when "1101011110",
"11101010111000111111100010111100111110011110011111000000100101101101100010" when "1101011111",
"11101011000111101110111011110011010111001010010100011010001100000010000011" when "1101100000",
"11101011000111101110111011110011010111001010010100011010001100000010000011" when "1101100001",
"11101011010110011111001011000001010111100100111110111111111100001001100001" when "1101100010",
"11101011010110011111001011000001010111100100111110111111111100001001100001" when "1101100011",
"11101011100101010000010000101101010001001010010010011001110000111011000011" when "1101100100",
"11101011110100000010001100111101010110011011100100001111110001000100010110" when "1101100101",
"11101011110100000010001100111101010110011011100100001111110001000100010110" when "1101100110",
"11101100000010110100111111110111111010111111111100001110110111000101101010" when "1101100111",
"11101100000010110100111111110111111010111111111100001110110111000101101010" when "1101101000",
"11101100010001101000101001100011010011100100100100010010000010101100101001" when "1101101001",
"11101100100000011101001010000101110101111100111000110000010101010100110111" when "1101101010",
"11101100100000011101001010000101110101111100111000110000010101010100110111" when "1101101011",
"11101100101111010010100001100101111001000010111000101111011011010110011010" when "1101101100",
"11101100101111010010100001100101111001000010111000101111011011010110011010" when "1101101101",
"11101100111110001000110000001001110100110111010110011011000011101011000100" when "1101101110",
"11101100111110001000110000001001110100110111010110011011000011101011000100" when "1101101111",
"11101101001100111111110101111000000010100010000111100001000111010011010110" when "1101110000",
"11101101011011110111110010110110111100010010010101110010100010100101011000" when "1101110001",
"11101101011011110111110010110110111100010010010101110010100010100101011000" when "1101110010",
"11101101101010110000100111001100111101011110101111101001000001110000010010" when "1101110011",
"11101101101010110000100111001100111101011110101111101001000001110000010010" when "1101110100",
"11101101111001101010010011000000100010100101111000110001100010011111100100" when "1101110101",
"11101110001000100100110110011000001001001110011010111011101100001010000110" when "1101110110",
"11101110001000100100110110011000001001001110011010111011101100001010000110" when "1101110111",
"11101110010111100000010001011010010000000111010110101110000000011001111010" when "1101111000",
"11101110010111100000010001011010010000000111010110101110000000011001111010" when "1101111001",
"11101110100110011100100100001101010111001000010100011111000101111001110110" when "1101111010",
"11101110100110011100100100001101010111001000010100011111000101111001110110" when "1101111011",
"11101110110101011001101110110111111111010001110101010011101110110111010100" when "1101111100",
"11101111000100010111110001100000101010101101100100000001111101000110110101" when "1101111101",
"11101111000100010111110001100000101010101101100100000001111101000110110101" when "1101111110",
"11101111010011010110101100001101111100101110100110011001000101011011000010" when "1101111111",
"11101111010011010110101100001101111100101110100110011001000101011011000010" when "1110000000",
"11101111100010010110011111000110011001110001101110001110110011111110010011" when "1110000001",
"11101111100010010110011111000110011001110001101110001110110011111110010011" when "1110000010",
"11101111110001010111001010010000100111011101101010110001010011011111110011" when "1110000011",
"11110000000000011000101101110011001100100011011001111110011001000101111011" when "1110000100",
"11110000000000011000101101110011001100100011011001111110011001000101111011" when "1110000101",
"11110000001111011011001001110100110000111110011001111111110110011000001110" when "1110000110",
"11110000001111011011001001110100110000111110011001111111110110011000001110" when "1110000111",
"11110000011110011110011110011011111101110100111010101100110011110100000110" when "1110001000",
"11110000011110011110011110011011111101110100111010101100110011110100000110" when "1110001001",
"11110000101101100010101011101111011101011000001111010000010101000000001111" when "1110001010",
"11110000101101100010101011101111011101011000001111010000010101000000001111" when "1110001011",
"11110000111100100111110001110101111011000100111111110101001000110011001001" when "1110001100",
"11110001001011101101110000110110000011100011011011010110100111000010011100" when "1110001101",
"11110001001011101101110000110110000011100011011011010110100111000010011100" when "1110001110",
"11110001011010110100101000110110100100100111101001010110111101110000111000" when "1110001111",
"11110001011010110100101000110110100100100111101001010110111101110000111000" when "1110010000",
"11110001101001111100011001111110001101010001111011111010101111110010000001" when "1110010001",
"11110001101001111100011001111110001101010001111011111010101111110010000001" when "1110010010",
"11110001111001000101000100010011101101101111000001101001100110011011001010" when "1110010011",
"11110001111001000101000100010011101101101111000001101001100110011011001010" when "1110010100",
"11110010001000001110100111111101110111011000010111110100011000011010010001" when "1110010101",
"11110010010111011001000101000011011100110100011100100000100111101011100110" when "1110010110",
"11110010010111011001000101000011011100110100011100100000100111101011100110" when "1110010111",
"11110010100110100100011011101011010001110111000000111001011000001000100000" when "1110011000",
"11110010100110100100011011101011010001110111000000111001011000001000100000" when "1110011001",
"11110010110101110000101011111100001011100001011011100101100001001010000001" when "1110011010",
"11110010110101110000101011111100001011100001011011100101100001001010000001" when "1110011011",
"11110011000100111101110101111101000000000010111011000011011011111010110010" when "1110011100",
"11110011000100111101110101111101000000000010111011000011011011111010110010" when "1110011101",
"11110011010100001011111001110100100110111000111000001010010000010100110000" when "1110011110",
"11110011100011011010110111101001111000101111001000110000100010100111111110" when "1110011111",
"11110011100011011010110111101001111000101111001000110000100010100111111110" when "1110100000",
"11110011110010101010101111100011101111100000010010011000100011101000010011" when "1110100001",
"11110011110010101010101111100011101111100000010010011000100011101000010011" when "1110100010",
"11110100000001111011100001101001000110010101111101000010000101100001000111" when "1110100011",
"11110100000001111011100001101001000110010101111101000010000101100001000111" when "1110100100",
"11110100010001001101001110000000111001101001000110000001110111001110010110" when "1110100101",
"11110100010001001101001110000000111001101001000110000001110111001110010110" when "1110100110",
"11110100100000011111110100110010000111000010010010111110101000011011111001" when "1110100111",
"11110100101111110011010110000011101101011010000100110011111000001100000110" when "1110101000",
"11110100101111110011010110000011101101011010000100110011111000001100000110" when "1110101001",
"11110100111111000111110001111100101100111001001010111010010000001000000110" when "1110101010",
"11110100111111000111110001111100101100111001001010111010010000001000000110" when "1110101011",
"11110101001110011101001000100100000110111000110110010101101110011100101011" when "1110101100",
"11110101001110011101001000100100000110111000110110010101101110011100101011" when "1110101101",
"11110101011101110011011010000000111110000011001101001001100000100111101011" when "1110101110",
"11110101011101110011011010000000111110000011001101001001100000100111101011" when "1110101111",
"11110101101101001010100110011010010110010011011101110001110000111010110101" when "1110110000",
"11110101101101001010100110011010010110010011011101110001110000111010110101" when "1110110001",
"11110101111100100010101101110111010100110110010010100011001000111001100001" when "1110110010",
"11110101111100100010101101110111010100110110010010100011001000111001100001" when "1110110011",
"11110110001011111011110000011111000000001010000101010000001010110111111101" when "1110110100",
"11110110011011010101101110011000011111111111010010110100100100100011011111" when "1110110101",
"11110110011011010101101110011000011111111111010010110100100100100011011111" when "1110110110",
"11110110101010110000100111101010111101011000101111000110011100111011110101" when "1110110111",
"11110110101010110000100111101010111101011000101111000110011100111011110101" when "1110111000",
"11110110111010001100011100011101100010101011111000101101011111100111000010" when "1110111001",
"11110110111010001100011100011101100010101011111000101101011111100111000010" when "1110111010",
"11110111001001101001001100110111011011100001001101000000000111101001101100" when "1110111011",
"11110111001001101001001100110111011011100001001101000000000111101001101100" when "1110111100",
"11110111011001000110111000111111110100110100011100000110101100001110110111" when "1110111101",
"11110111011001000110111000111111110100110100011100000110101100001110110111" when "1110111110",
"11110111101000100101100000111101111100110100111101000100110001001011011110" when "1110111111",
"11110111101000100101100000111101111100110100111101000100110001001011011110" when "1111000000",
"11110111111000000101000100111001000011000110000010001000011101101001111100" when "1111000001",
"11111000000111100101100100111000011000011111001100111111111011001100000111" when "1111000010",
"11111000000111100101100100111000011000011111001100111111111011001100000111" when "1111000011",
"11111000010111000111000001000011001111001100100011010100111111010001111100" when "1111000100",
"11111000010111000111000001000011001111001100100011010100111111010001111100" when "1111000101",
"11111000100110101001011001100000111010101111000011001111000001110100110101" when "1111000110",
"11111000100110101001011001100000111010101111000011001111000001110100110101" when "1111000111",
"11111000110110001100101110011000101111111100110111111011000010101000001011" when "1111001000",
"11111000110110001100101110011000101111111100110111111011000010101000001011" when "1111001001",
"11111001000101110000111111110010000101000001101110011010000000010000101100" when "1111001010",
"11111001000101110000111111110010000101000001101110011010000000010000101100" when "1111001011",
"11111001010101010110001101110100010001011111001010010101100010100101000111" when "1111001100",
"11111001010101010110001101110100010001011111001010010101100010100101000111" when "1111001101",
"11111001100100111100011000100110101110001100111010111010111011001011111110" when "1111001110",
"11111001100100111100011000100110101110001100111010111010111011001011111110" when "1111001111",
"11111001110100100011100000010000110101011001001111111100011110001010100110" when "1111010000",
"11111001110100100011100000010000110101011001001111111100011110001010100110" when "1111010001",
"11111010000100001011100100111010000010101001001110111001010101011011011000" when "1111010010",
"11111010000100001011100100111010000010101001001110111001010101011011011000" when "1111010011",
"11111010010011110100100110101001110010111001001000001011110001000001011000" when "1111010100",
"11111010100011011110100101100111100100011100101100011101110110110001000011" when "1111010101",
"11111010100011011110100101100111100100011100101100011101110110110001000011" when "1111010110",
"11111010110011001001100001111010110110111111100010000100110011100110100010" when "1111010111",
"11111010110011001001100001111010110110111111100010000100110011100110100010" when "1111011000",
"11111011000010110101011011101011001011100101011010100010110001000011001011" when "1111011001",
"11111011000010110101011011101011001011100101011010100010110001000011001011" when "1111011010",
"11111011010010100010010011000000000100101010101000001111010001001100110000" when "1111011011",
"11111011010010100010010011000000000100101010101000001111010001001100110000" when "1111011100",
"11111011100010010000001000000001000110000100010100000110010011101010000100" when "1111011101",
"11111011100010010000001000000001000110000100010100000110010011101010000100" when "1111011110",
"11111011110001111110111010110101110101000000110011011110000101111001110000" when "1111011111",
"11111011110001111110111010110101110101000000110011011110000101111001110000" when "1111100000",
"11111100000001101110101011100101111000000111111110000011100001100000110001" when "1111100001",
"11111100000001101110101011100101111000000111111110000011100001100000110001" when "1111100010",
"11111100010001011111011010011000110111011011100011111101011010101111100010" when "1111100011",
"11111100010001011111011010011000110111011011100011111101011010101111100010" when "1111100100",
"11111100100001010001000111010110011100010111100011110110100001111101101000" when "1111100101",
"11111100100001010001000111010110011100010111100011110110100001111101101000" when "1111100110",
"11111100110001000011110010100110010001110010100001001110011010011100110110" when "1111100111",
"11111100110001000011110010100110010001110010100001001110011010011100110110" when "1111101000",
"11111101000000110111011100010000000011111101111010110001001001000101101101" when "1111101001",
"11111101000000110111011100010000000011111101111010110001001001000101101101" when "1111101010",
"11111101010000101100000100011011100000100110100000110101111101100000101010" when "1111101011",
"11111101010000101100000100011011100000100110100000110101111101100000101010" when "1111101100",
"11111101100000100001101011010000010110110100101100000100111000001111111110" when "1111101101",
"11111101100000100001101011010000010110110100101100000100111000001111111110" when "1111101110",
"11111101110000011000010000110110010111001100110100000011010000011111111111" when "1111101111",
"11111101110000011000010000110110010111001100110100000011010000011111111111" when "1111110000",
"11111110000000001111110101010101010011101111100110000111011100000011110010" when "1111110001",
"11111110000000001111110101010101010011101111100110000111011100000011110010" when "1111110010",
"11111110010000001000011000110100111111111010011100010011011100000110010110" when "1111110011",
"11111110010000001000011000110100111111111010011100010011011100000110010110" when "1111110100",
"11111110100000000001111011011101010000100111110100010110110001011000011111" when "1111110101",
"11111110100000000001111011011101010000100111110100010110110001011000011111" when "1111110110",
"11111110101111111100011101010101111100001111100110110111011010100101101100" when "1111110111",
"11111110101111111100011101010101111100001111100110110111011010100101101100" when "1111111000",
"11111110111111110111111110100110111010100111011110100001111111011010111111" when "1111111001",
"11111110111111110111111110100110111010100111011110100001111111011010111111" when "1111111010",
"11111111001111110100011111011000000101000011001111100001001011001011101100" when "1111111011",
"11111111001111110100011111011000000101000011001111100001001011001011101100" when "1111111100",
"11111111011111110001111111110001010110010101001110111100011001100001110110" when "1111111101",
"11111111011111110001111111110001010110010101001110111100011001100001110110" when "1111111110",
"11111111101111110000011111111010101010101110101010011101111000001000100000" when "1111111111",
"--------------------------------------------------------------------------" when others;
Y <= TableOut_d1;
end architecture;
-------------------------------------------------------------------------------
entity bigcase is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of bigcase is
signal clk, rst : std_logic;
signal X : std_logic_vector(9 downto 0);
signal Y : std_logic_vector(73 downto 0);
begin
LogTable_0_10_74_F400_uid60_1: entity work.LogTable_0_10_74_F400_uid60
port map (
clk => clk,
rst => rst,
X => X,
Y => Y );
p1: process is
variable ctr : unsigned(9 downto 0);
begin
for rep in 1 to 10000 loop
for i in 1 to 2**9 - 1 loop
X <= std_logic_vector(ctr);
ctr := ctr + 1;
wait for 1 ns;
end loop;
end loop;
wait;
end process;
end architecture;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/utt.fr/dohist_v1_0/hdl/vhdl/doHist_CTRL_BUS_s_axi.vhd | 5 | 11600 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity doHist_CTRL_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC
);
end entity doHist_CTRL_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x0 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x4 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x8 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0xc : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of doHist_CTRL_BUS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0#;
constant ADDR_GIE : INTEGER := 16#4#;
constant ADDR_IER : INTEGER := 16#8#;
constant ADDR_ISR : INTEGER := 16#c#;
constant ADDR_BITS : INTEGER := 4;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| gpl-3.0 |
nickg/nvc | test/sem/linkage.vhd | 1 | 254 | entity e is
port ( x : linkage integer );
end entity;
architecture a of e is
begin
x <= 1; -- Error
assert x = 1; -- Error
sub: entity work.e port map ( x ); -- OK
end architecture;
| gpl-3.0 |
nickg/nvc | test/regress/vests34.vhd | 1 | 6479 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2439.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests34 IS
END vests34;
ARCHITECTURE c07s03b02x02p01n01i02439arch OF vests34 IS
BEGIN
TESTING: PROCESS
subtype char128 is character range NUL to DEL;
-- Range types are all predefined enumerated types.
type CHAR_ARR is ARRAY( char128 ) of BIT;
type BIT_ARR is ARRAY( BIT ) of BIT;
type BOOL_ARR is ARRAY( BOOLEAN ) of BIT;
type SEV_ARR is ARRAY( SEVERITY_LEVEL ) of BIT;
-- Declare variables of these types.
variable CHARV : CHAR_ARR;
variable BITV : BIT_ARR;
variable BOOLV : BOOL_ARR;
variable SEVV : SEV_ARR;
variable OKtest: integer := 0;
BEGIN
-- Assign each of these arrays using aggregates.
-- 1. Individual aggregates.
CHARV := CHAR_ARR'( 'a' => '1', 'b' => '0', NUL to '`' => '1',
'c' to DEL => '1' );
for C in char128 loop
if (C = 'a') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '1' ) report "CHARV( " & character'image(c)
& " ) = " & bit'image(CHARV( C ));
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( '0' => '0', '1' => '1' );
assert( BITV( '0' ) = '0' );
if NOT( BITV( '0' ) = '0' ) then
OKtest := 1;
end if;
assert( BITV( '1' ) = '1' );
if NOT( BITV( '1' ) = '1' ) then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE => '0', TRUE => '1' );
assert( BOOLV( FALSE ) = '0' );
if NOT( BOOLV( FALSE ) = '0' ) then
OKtest := 1;
end if;
assert( BOOLV( TRUE ) = '1' );
if NOT( BOOLV( TRUE ) = '1' ) then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE => '0', WARNING => '1', ERROR => '0',
FAILURE => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
-- 2. Groups of aggregates.
CHARV := CHAR_ARR'( 'a' | 'b' => '1', NUL to '`' => '0',
'c' to DEL => '0' );
for C in char128 loop
if (C = 'a') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( '0' | '1' => '0' );
assert( BITV( '0' ) = '0' );
assert( BITV( '1' ) = '0' );
if NOT((BITV('0')='0') and (BITV('1')='0')) then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE | TRUE => '1' );
assert( BOOLV( FALSE ) = '1' );
assert( BOOLV( TRUE ) = '1' );
if NOT((BOOLV(FALSE)='1') and (BOOLV(TRUE)='1')) then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE | ERROR => '0', WARNING | FAILURE => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
-- 3. Use of 'others' in these aggregates.
CHARV := CHAR_ARR'( 'a' | 'b' => '0', others => '1' );
for C in char128 loop
if (C = 'a') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( others => '1' );
assert( BITV( '0' ) = '1' );
assert( BITV( '1' ) = '1' );
if NOT(( BITV( '0' ) = '1' )and( BITV( '1' ) = '1' ))then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE => '1', others => '0' );
assert( BOOLV( FALSE ) = '1' );
assert( BOOLV( TRUE ) = '0' );
if NOT(( BOOLV( FALSE ) = '1' )and( BOOLV( TRUE ) = '0' ))then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE | ERROR => '0', others => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
wait for 5 ns;
assert NOT(OKtest = 0)
report "***PASSED TEST: c07s03b02x02p01n01i02439"
severity NOTE;
assert (OKtest = 0)
report "***FAILED TEST: c07s03b02x02p01n01i02439 - Aggregates with different range types test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02439arch;
| gpl-3.0 |
nickg/nvc | test/regress/genpack5.vhd | 1 | 1456 | package poly is
generic (a, b, def : integer);
function apply (x : integer := def) return integer;
end package;
package body poly is
function apply (x : integer := def) return integer is
begin
return x * a + b;
end function;
end package body;
-------------------------------------------------------------------------------
package wrapper is
generic ( package p is new work.poly generic map ( <> ) );
function wrapped_apply (n : integer) return integer;
end package;
package body wrapper is
use p.all;
function wrapped_apply (n : integer) return integer is
begin
return apply(n);
end function;
end package body;
-------------------------------------------------------------------------------
entity genpack5 is
end entity;
architecture test of genpack5 is
package my_poly1 is new work.poly generic map (a => 2, b => 3, def => 10);
package my_wrap1 is new work.wrapper generic map (p => my_poly1);
package my_poly2 is new work.poly generic map (a => 5, b => 1, def => 1);
package my_wrap2 is new work.wrapper generic map (p => my_poly2);
begin
main: process is
variable v : integer := 5;
begin
assert my_wrap1.wrapped_apply(2) = 7;
wait for 1 ns;
assert my_wrap1.wrapped_apply(v) = 13;
assert my_wrap2.wrapped_apply(2) = 11;
assert my_wrap2.wrapped_apply(v) = 26;
wait;
end process;
end architecture;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_bram_ctrl_v4_0/hdl/vhdl/correct_one_bit.vhd | 7 | 8861 | -------------------------------------------------------------------------------
-- correct_one_bit.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: correct_one_bit.vhd
--
-- Description: Identifies single bit to correct in 32-bit word of
-- data read from memory as indicated by the syndrome input
-- vector.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity Correct_One_Bit is
generic (
C_USE_LUT6 : boolean := true;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end entity Correct_One_Bit;
architecture IMP of Correct_One_Bit is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-----------------------------------------------------------------------------
-- Find which bit that has a '1'
-- There is always one bit which has a '1'
-----------------------------------------------------------------------------
function find_one (Syn : std_logic_vector(0 to 6)) return natural is
begin -- function find_one
for I in 0 to 6 loop
if (Syn(I) = '1') then
return I;
end if;
end loop; -- I
return 0; -- Should never reach this statement
end function find_one;
constant di_index : natural := find_one(Correct_Value);
signal corr_sel : std_logic;
signal corr_c : std_logic;
signal lut_compare : std_logic_vector(0 to 5);
signal lut_corr_val : std_logic_vector(0 to 5);
begin -- architecture IMP
Remove_DI_Index : process (Syndrome) is
begin -- process Remove_DI_Index
if (di_index = 0) then
lut_compare <= Syndrome(1 to 6);
lut_corr_val <= Correct_Value(1 to 6);
elsif (di_index = 6) then
lut_compare <= Syndrome(0 to 5);
lut_corr_val <= Correct_Value(0 to 5);
else
lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 6);
lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 6);
end if;
end process Remove_DI_Index;
-- Corr_LUT : LUT6
-- generic map(
-- INIT => X"6996966996696996"
-- )
-- port map(
-- O => corr_sel, -- [out]
-- I0 => InA(5), -- [in]
-- I1 => InA(4), -- [in]
-- I2 => InA(3), -- [in]
-- I3 => InA(2), -- [in]
-- I4 => InA(1), -- [in]
-- I5 => InA(0) -- [in]
-- );
corr_sel <= '0' when lut_compare = lut_corr_val else '1';
Corr_MUXCY : MUXCY_L
port map (
DI => Syndrome(di_index),
CI => '0',
S => corr_sel,
LO => corr_c);
Corr_XORCY : XORCY
port map (
LI => DIn,
CI => corr_c,
O => DCorr);
end architecture IMP;
| gpl-3.0 |
nickg/nvc | test/regress/elab21.vhd | 1 | 1007 | package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
y <= x + r.a + r.b;
end architecture;
-------------------------------------------------------------------------------
entity elab21 is
end entity;
use work.pack.all;
architecture test of elab21 is
signal r1, r2 : rec := (0, 0);
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
process is
begin
r1.a <= 0;
r2 <= (0, 0);
wait for 1 ns;
assert r1.b = 0;
r1.a <= 5;
wait for 1 ns;
assert r1.b = 5;
r2 <= (2, 3);
wait for 1 ns;
assert r1.b = 10;
wait;
end process;
end architecture;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_q_mngr.vhd | 7 | 49985 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
ch2_sg_idle : in std_logic ;
--
-- Channel 1 Control --
ch1_desc_flush : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_ftch_active : in std_logic ; --
ch1_nxtdesc_wren : out std_logic ; --
ch1_ftch_queue_empty : out std_logic ; --
ch1_ftch_queue_full : out std_logic ; --
ch1_ftch_pause : out std_logic ; --
--
-- Channel 2 Control --
ch2_desc_flush : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_ftch_active : in std_logic ; --
ch2_nxtdesc_wren : out std_logic ; --
ch2_ftch_queue_empty : out std_logic ; --
ch2_ftch_queue_full : out std_logic ; --
ch2_ftch_pause : out std_logic ; --
nxtdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : out std_logic ; --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tkeep : in std_logic_vector --
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
--
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ;
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic ;
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Determine the maximum word count for use in setting the word counter width
-- Set bit width on max num words to fetch
constant FETCH_COUNT : integer := max2(C_SG_CH1_WORDS_TO_FETCH
,C_SG_CH2_WORDS_TO_FETCH);
-- LOG2 to get width of counter
constant WORDS2FETCH_BITWIDTH : integer := clog2(FETCH_COUNT);
-- Zero value for counter
constant WORD_ZERO : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= (others => '0');
-- One value for counter
constant WORD_ONE : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,WORDS2FETCH_BITWIDTH));
-- Seven value for counter
constant WORD_SEVEN : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(7,WORDS2FETCH_BITWIDTH));
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_mm2s_tready_i : std_logic := '0';
signal ch1_ftch_tready : std_logic := '0';
signal ch2_ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal fetch_word_count : std_logic_vector
(WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0');
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal lsbnxtdesc_tready : std_logic := '0';
signal msbnxtdesc_tready : std_logic := '0';
signal nxtdesc_tready : std_logic := '0';
signal ch1_writing_curdesc : std_logic := '0';
signal ch2_writing_curdesc : std_logic := '0';
signal m_axis_ch2_ftch_tvalid_1 : std_logic := '0';
-- KAPIL
signal ch_desc_flush : std_logic := '0';
signal m_axis_ch_ftch_tready : std_logic := '0';
signal ch_ftch_queue_empty : std_logic := '0';
signal ch_ftch_queue_full : std_logic := '0';
signal ch_ftch_pause : std_logic := '0';
signal ch_writing_curdesc : std_logic := '0';
signal ch_ftch_tready : std_logic := '0';
signal m_axis_ch_ftch_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch_ftch_tvalid : std_logic := '0';
signal m_axis_ch_ftch_tlast : std_logic := '0';
signal data_concat : std_logic_vector (95 downto 0) := (others => '0');
signal data_concat_64 : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_64_cdma : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_mcdma : std_logic_vector (63 downto 0) := (others => '0');
signal next_bd : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_valid, tvalid_new : std_logic;
signal data_concat_tlast, tlast_new : std_logic;
signal counter : std_logic_vector (C_SG_CH1_WORDS_TO_FETCH-1 downto 0);
signal sof_ftch_desc : std_logic;
signal nxtdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal cyclic_enable : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
cyclic_enable <= ch1_cyclic when ch1_ftch_active = '1' else
ch2_cyclic;
nxtdesc <= nxtdesc_int;
TLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH = 13) generate
-- TLAST is generated when 8th beat is received
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
SOF_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tlast = '1'))then
sof_ftch_desc <= '0';
elsif(counter (6) = '1'
and m_axis_mm2s_tready_i = '1' and m_axis_mm2s_tvalid = '1'
and m_axis_mm2s_tdata(27) = '1' )then
sof_ftch_desc <= '1';
end if;
end if;
end process SOF_CHECK;
end generate TLAST_GEN;
NOTLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH /= 13) generate
sof_ftch_desc <= '0';
CDMA : if C_ENABLE_CDMA = 1 generate
-- For CDMA TLAST is generated when 7th beat is received
-- because last one is not needed
tlast_new <= counter (6) and m_axis_mm2s_tvalid;
tvalid_new <=counter (6) and m_axis_mm2s_tvalid;
end generate CDMA;
NOCDMA : if C_ENABLE_CDMA = 0 generate
-- For DMA tlast is generated with 8th beat
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
end generate NOCDMA;
end generate NOTLAST_GEN;
-- Following shift register keeps track of number of data beats
-- of BD that is being read
DATA_BEAT_REG : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1')) then
counter (0) <= '1';
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= (others => '0');
Elsif (m_axis_mm2s_tvalid = '1') then
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= counter (C_SG_CH1_WORDS_TO_FETCH-2 downto 0);
counter (0) <= '0';
end if;
end if;
end process DATA_BEAT_REG;
-- Registering the Buffer address from BD, 3rd beat
-- Common for DMA, CDMA
DATA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (31 downto 0) <= (others => '0');
Elsif (counter (2) = '1') then
data_concat (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1;
ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (31 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1_64;
end generate ADDR_64BIT;
ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG1_64;
data_concat_64 (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate ADDR_64BIT2;
DMA_REG2 : if C_ENABLE_CDMA = 0 generate
begin
-- For DMA, the 7th beat has the control information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (6) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
end generate DMA_REG2;
CDMA_REG2 : if C_ENABLE_CDMA = 1 generate
begin
-- For CDMA, the 5th beat has the DA information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
CDMA_ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (31 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2_64;
end generate CDMA_ADDR_64BIT;
CDMA_ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG2_64;
data_concat_64_cdma (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate CDMA_ADDR_64BIT2;
end generate CDMA_REG2;
NOFLOP_FOR_QUEUE : if C_SG_CH1_WORDS_TO_FETCH = 8 generate
begin
-- Last beat is directly concatenated and passed to FIFO
-- Masking the CMPLT bit with cyclic_enable
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end generate NOFLOP_FOR_QUEUE;
-- In absence of queuing option the last beat needs to be floped
FLOP_FOR_NOQUEUE : if C_SG_CH1_WORDS_TO_FETCH = 13 generate
begin
NO_FETCH_Q : if C_SG_FTCH_DESC2QUEUE = 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95 downto 64) <= (others => '0');
Elsif (counter (7) = '1') then
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
end if;
end if;
end process DATA_REG3;
end generate NO_FETCH_Q;
FETCH_Q : if C_SG_FTCH_DESC2QUEUE /= 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95) <= '0';
Elsif (counter (7) = '1') then
data_concat (95) <= m_axis_mm2s_tdata (31) and (not cyclic_enable);
end if;
end if;
end process DATA_REG3;
data_concat (94 downto 64) <= (others => '0');
end generate FETCH_Q;
DATA_CNTRL : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_valid <= '0';
data_concat_tlast <= '0';
Else
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end if;
end if;
end process DATA_CNTRL;
end generate FLOP_FOR_NOQUEUE;
-- Since the McDMA BD has two more fields to be captured
-- following procedures are needed
NOMCDMA_FTECH : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
data_concat_mcdma <= (others => '0');
end generate NOMCDMA_FTECH;
MCDMA_BD_FETCH : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
DATA_MCDMA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (31 downto 0) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat_mcdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG1;
DATA_MCDMA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (63 downto 32) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_mcdma (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG2;
end generate MCDMA_BD_FETCH;
---------------------------------------------------------------------------
-- For 32-bit SG addresses then drive zero on msb
---------------------------------------------------------------------------
GEN_CURDESC_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
msb_curdesc <= (others => '0');
end generate GEN_CURDESC_32;
---------------------------------------------------------------------------
-- For 64-bit SG addresses then capture upper order adder to msb
---------------------------------------------------------------------------
GEN_CURDESC_64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CAPTURE_CURADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
msb_curdesc <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
msb_curdesc <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ C_M_AXI_SG_ADDR_WIDTH
downto DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT + 1);
end if;
end if;
end process CAPTURE_CURADDR;
end generate GEN_CURDESC_64;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(31 downto 0) <= (others => '0');
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (0) = '1')then
nxtdesc_int(31 downto 6) <= m_axis_mm2s_tdata (31 downto 6);
-- BD addresses are always 16 word 32-bit aligned
nxtdesc_int(5 downto 0) <= (others => '0');
end if;
end if;
end process REG_LSB_NXTPNTR;
lsbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (0) = '1' --etch_word_count = WORD_ZERO
else '0';
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_NXTDESC : if C_ACTUAL_ADDR = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(63 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(63 downto 32) <= m_axis_mm2s_tdata;
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC;
GEN_UPPER_MSB_NXTDESC2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
nxtdesc_int (63 downto C_ACTUAL_ADDR) <= (others => '0');
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC2;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Throw away second word but drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then --fetch_word_count = WORD_ONE)then
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_NO_UPR_MSB_NXTDESC;
-- Drive ready to DataMover for ether lsb or msb capture
nxtdesc_tready <= msbnxtdesc_tready or lsbnxtdesc_tready;
-- Generate logic for checking stale descriptor
GEN_STALE_DESC_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 or C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
---------------------------------------------------------------------------
-- Examine Completed BIT to determine if stale descriptor fetched
---------------------------------------------------------------------------
CMPLTD_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ftch_stale_desc <= '0';
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (7) = '1' --fetch_word_count = WORD_SEVEN
and m_axis_mm2s_tready_i = '1'
and m_axis_mm2s_tdata(DESC_STS_CMPLTD_BIT) = '1' )then
ftch_stale_desc <= '1' and (not cyclic_enable);
else
ftch_stale_desc <= '0';
end if;
end if;
end process CMPLTD_CHECK;
end generate GEN_STALE_DESC_CHECK;
-- No needed logic for checking stale descriptor
GEN_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 and C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ftch_stale_desc <= '0';
end generate GEN_NO_STALE_CHECK;
---------------------------------------------------------------------------
-- SG Queueing therefore pass stream signals to
-- FIFO
---------------------------------------------------------------------------
GEN_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
begin
-- Instantiate the queue version
FTCH_QUEUE_I : entity axi_sg_v4_1_2.axi_sg_ftch_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_INCLUDE_MM2S => C_INCLUDE_CH1,
C_INCLUDE_S2MM => C_INCLUDE_CH2,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => '0' ,
-- Channel Control
desc1_flush => ch1_desc_flush ,
desc2_flush => ch2_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch1_active => ch1_ftch_active ,
ftch2_active => ch2_ftch_active ,
ftch1_queue_empty => ch1_ftch_queue_empty ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch1_queue_full => ch1_ftch_queue_full ,
ftch2_queue_full => ch2_ftch_queue_full ,
ftch1_pause => ch1_ftch_pause ,
ftch2_pause => ch2_ftch_pause ,
writing_nxtdesc_in => nxtdesc_tready ,
writing1_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat_64_cdma => data_concat_64_cdma,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
m_axis1_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_aclk => m_axi_sg_aclk, --m_axis_ch_ftch_aclk ,
m_axis_ftch1_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch1_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch1_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch1_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch1_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch1_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch1_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
m_axis_ftch2_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ftch2_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ftch2_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
m_axis_ftch2_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ftch2_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ftch2_tready => m_axis_ch2_ftch_tready ,
m_axis_ftch2_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
m_axis_ch2_ftch_tdata_mcdma_nxt <= (others => '0');
end generate GEN_QUEUE;
-- No SG Queueing therefore pass stream signals straight
-- out channel port
-- No SG Queueing therefore pass stream signals straight
-- out channel port
GEN_NO_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
-- Instantiate the No queue version
NO_FTCH_QUEUE_I : entity axi_sg_v4_1_2.axi_sg_ftch_noqueue
generic map (
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_CH1 => C_INCLUDE_CH1
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
-- Channel Control
desc_flush => ch1_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch_active => ch1_ftch_active ,
ftch_queue_empty => ch1_ftch_queue_empty ,
ftch_queue_full => ch1_ftch_queue_full ,
desc2_flush => ch2_desc_flush ,
ftch2_active => ch2_ftch_active ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch2_queue_full => ch2_ftch_queue_full ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch_desc_available => m_axis_ftch1_desc_available ,
m_axis2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis2_ftch_desc_available => m_axis_ftch2_desc_available ,
m_axis2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
ch1_ftch_pause <= '0';
ch2_ftch_pause <= '0';
end generate GEN_NO_QUEUE;
-------------------------------------------------------------------------------
-- DataMover TREADY MUX
-------------------------------------------------------------------------------
writing_curdesc <= ch1_writing_curdesc or ch2_writing_curdesc or ftch_cmnd_wr;
TREADY_MUX : process(writing_curdesc,
fetch_word_count,
nxtdesc_tready,
-- channel 1 signals
ch1_ftch_active,
ch1_desc_flush,
ch1_ftch_tready,
-- channel 2 signals
ch2_ftch_active,
ch2_desc_flush,
counter(0),
counter(1),
ch2_ftch_tready)
begin
-- If commmanded to flush descriptor then assert ready
-- to datamover until active de-asserts. this allows
-- any commanded fetches to complete.
if( (ch1_desc_flush = '1' and ch1_ftch_active = '1')
or(ch2_desc_flush = '1' and ch2_ftch_active = '1'))then
m_axis_mm2s_tready_i <= '1';
-- NOT ready if cmnd being written because
-- curdesc gets written to queue
elsif(writing_curdesc = '1')then
m_axis_mm2s_tready_i <= '0';
-- First two words drive ready from internal logic
elsif(counter(0) = '1' or counter(1)='1')then
m_axis_mm2s_tready_i <= nxtdesc_tready;
-- Remainder stream words drive ready from channel input
else
m_axis_mm2s_tready_i <= (ch1_ftch_active and ch1_ftch_tready)
or (ch2_ftch_active and ch2_ftch_tready);
end if;
end process TREADY_MUX;
m_axis_mm2s_tready <= m_axis_mm2s_tready_i;
end implementation;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/xbip_dsp48_multadd_v3_0/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd | 9 | 73491 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
RRooMx8aKXOKuw0jba9AAvNqcv1aOAWx0dmOeAMZtfEA8NEQBycfD1he5bNQ520rjDcafpEIYoFH
8wShwJiQKg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RgXfz+8mp1qbBTyetHH5ngynBLMwZxu0rxkXLh6QHG9XAy4+BbRKOjz1+c6cH6NYhRRfM4vT5Wl9
ixg8Rc8Yc/S242b09BUNorP5ATo1wne5IxcZ3jC1T4BUzl0tgUScvpD0uFueK3/IMnEjC4aKr60w
VKR6qyW4sq2X954pF24=
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oSpqzFUI/f1Ucw6UHNSsuY41hVH/I8MTwUZaCMUrE6zrelZVctDl9yufZENXxn0WT1Yem6/W+w1g
j5QeVJm+5hjC0WIxLupVJMkqfzQw8dGHJPDGoEaTB2RcDqLTnI9CrpQ+iJb7hrQn6dDmxZImAuMq
3pJVs+aaFHAeNuzZZhE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
X4Fi+a1OzUk68cyxZUSzfNpLCwkSC0wmt8tY0kB574VuReti34LgiOkcPXhGDj4gSUKkUF4A/Yda
WDzaAnabrJ3zv3CWcxwC2pPrD1rNotHPICUvwJpTTNzK8oCLdrgMtygrsL5CwXaOVNz1a++BWa6C
QlArFRdlccowSRhXDf5tSyKNSLiV9tJxHNvWPzIowxyUtoVMdFV+wv3UhZXGP74OmYsEJ9ESIEXz
q0P+Tc5gairxuvjskvUVpqbsNEBOq90+NKAEaLtPOQ6vY8kzp+eWm8uf5f3kgAZZsAiQGswk7vU2
f5LaUSeubviPjfs+8uQjBW2DPBwJbScjsXNcQA==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ro6yqNSieyMPHHxOuV5fgYIFX1ue1fCOQaUrsWRJcJVYR01otjGNBK1LpULF9osLOrFWk4AtTJqV
rWcIGuQTGE8iRA3XlZBfUPo5Auyp6hG2JT2LLT/s9g6oUGrueNakH+McXpdG6aUJkgH9/eoBjrLX
DrPrHqq40IlnSppHpDAOq11fRkZk9TkYdWeakR7Tqj5fMix/Hves5J2MNw7M+0/bs9k7crMC3AB4
hiMav0upztwGMWPFQOTJLcPJQ9Jmlip35nCdHQRH+L1Pz5yPl599XvkZh7InTkLreIaRmIpZaIPJ
dSX841g9ZA3G2q8OiDyHBCZOsKYNN4/R2I8Cjw==
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
K8DR1xFh8LdLJFzLYbjbQJHVBapMV/A5ef8aS1igRTqWTzaxTp8rcNFvJmLeb2FVSABbW9ENq0z2
4PAQuZAFntoQZCy0B96/GhJqiwWNdo9SkQAXHie4qn1yl5LCT837iglxkr5T9u9hdW/y32580N70
9mwvaao2qtKVUj2WO7a8JbZTzIZj2kxqfrfxG+wf2zMcUTQ1XZCsGULlRMnDM7exK4fGQxqbrLsN
3z3GB/1h4CYvFQCvVlD3CURFCtPUP/5toS0Ja6ccVb6/3q73spZWxAHrzIuZDq1YEczGdzSMR+k6
s98cQiYspIArx3y1cvwLR27cpPujPAWuCP8Wyw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52272)
`protect data_block
qSsiLyvJuChi2E0XpHgqvvzL6KzlxNxmE/rnpbeMhxrcw4+YwQJf9PGnnrX4tEF0CY29CW0IjJey
bTv8crMTak6uftHEV7pAuVQqN1qoRfnDfIvU/hzMFvc9tUkx09OtZVb+rRtldxhe/aZS96in+sHB
hTqshw27b8IcBbT8EktIyfwc65qh1xE/ZgulXR9Kcx1Jx3rEjUMwWiD6TB5hlErIg6H2BuygbR/z
IJFQmZVFcQw1H6HyC2DOC4Oj312yg2csbrv5Fz4fRw94DBfNqZf7WhZndcEbGi9oc0JyNlDiyXfp
uxBrEPLYdHAVsWsuHLRyiblPimflRcpi9/LZmqvr6FoY5X17yBHcR+lyAd2iwU+tABC2Z3kvAKPU
A+aJ592s+KfmV0teZoU5XNQysu1h0js1kC6Wn/2qlKufjLQ3OkkwSvreMLyQYXsdiBqb78ISE4Uw
UImzT5LkG7n0RjvhZBUx8U5sZQw9lxMB8gM8JWFuKkkCFerzx7nBeQJ/05ztfnXvcqZ4bf2FKiDL
wxEa8EkkVSUDI5pgxSkWCsURrwxN/e+CU/ajY3aA9LDKl/FOqWj80o40f6ru9PUlZCWuV0wAJSJo
4Uyc4I9Y9+o4JK1cgU6Si7VBlqsDI1yOCHgQpc6hZ6MZ5ghBi1wfReAgcvcoKNsM5w5yZdQBiso+
CY6P0B96TK+IDlGroXJc0AGv7nzWG4KUsiUQKC4E/iqn5XzwXnYrRAZd0nLDCzm/A1+b/u/+vERQ
cDwJzhVgKvFvIvrvyGV03rCdtrxETckrpHjiHdP4eJrm7Oe3i6Drqg/uoEm1kYnpn0zx3QQ26drA
r0x/8Ke0a/e3+HN+3oCKQk351kSjXS++a6wu0iw8OMWM4HOfHoBWHJR13RzchJv0fqy/mJyPlIcU
07kkB5SJJFb/L8cFiEnU9jplyJMA0daXLEFyvoFKEPEtFYpW7eTLMa4znfFv90rALh5EbrNyR8no
Z7o/aBvPDjmx/stKnPwRb8j0bJ7f9l+MfR9enwoNOhGAC8j/Z6j1xNw+53ZtO1GXpQV4Ej4ioSfx
OpOyfc5sCLV278oJuUXxU2Dvw1Rc69cA/oDDbQ3rPQWK+B3p9AVJRcPX/1/bSqGrdSciXZDQgidz
e7Wom4XRKNoQq/HTowIEXTiv+Hh158V6Lj7yxYnYwuGJsyiPQZCCI33W0T+y7lpo1rl1me2uyfhA
TJ2ReQSRSlq4ZpdxYqMq7l2FIrK8KHOjeGDDQ4Ttp5cNpC1Va6EcC+6jm+Y5iQ6iqtB+09A+3RQq
gpWIU0owrNoD9CJQ2QBR/7LDZKHxghYKTkLeX9QiH9JNo1/ipF9d86N6U2qOVW1UMvRGwcIA5Y30
tEVpI0Bq7Y4PL3CGPc0Jt2INtp1aXlH6eezE36hG8KSuQAm1kOjxWoIKkAkIUR2sHUzq+L5T3BG1
w7AMwJpMXqQi9kCIUWT5s1vAJuS5fs7mmeTcqVmF28ZaR4jxXlDtmAohp45hw+6B0zkF9VeLiIAA
CSzIToC0HRRcKoQWE4VjKLkhMXIogE9v/uSpcoc3/wDBirds/0mYTssntTimjBKZdgXZ1xWds5Xa
eXyzP0hmdephl37doXhNbEqfGbGh/SFnulTsiUg9Ivh+t4wCQzMnHhbJKxyW1VDEznt6sxNJnQ5c
YfQNfXkpQ3ZzuxIWkof531RIExR7EG6iVF6NNuqUn869t+BI1yk5NLpaKFGBeSPJsAlbbGFmY1W4
ggfaQZodxVA1aI43AoggG0iCJjARNlb8SN2RmBNmC36eN3HSp3rIZI+5Apd7vf1NoG7qcJmceslj
1JLiPNhKhC1HCDeWioceHB8vRRB8HM92WWHYrrRytojpKoOlLOb93iZxCJ/9H4vkXoXs7Yjw0/pS
qEz/0T0PjDsd1bKZJsz8T1/RshFP+9tuOJmghqv7WD8VXPKC1MA04hhV6XV8rNvImcWMT9Ffm89c
MwYvbPslMDELFE4hDA4PbDH37dwxrIYNYn9ajYlF5zvhsQ84KbwdkSSY1l0v1gFBodPZQ+w5Jr72
9hnX/v7V+QTJIWAmno7uUK7Sjoykfk5HGjrG9HctBH2zRHMZ4F8M/ZgrJ4LisYGzOzimGDOG+q/W
Ni8K866T4S8Zvzl3UHdy8GGM1+TAgcV7Nk6HPcvhOEg5UHt4udE9pDrQVVl8sPSzO+mhqFz/3Ae1
+Wvb5okOmcSOdT5XdTzuDRda17C+qe9OZkP03FVZ3P9wOsgYTSN62FnVkGDuXu3vTXJF80Rr2V23
M9ftZalEIQxzvMe5/SAfYzOXxcYxBH2hEI7ix61A4qgNOwm8PaYszIo5ws0zhbsLmuZweskH9Ufi
bu2S9artLAfkxYdwqanhjIwxLtO53fUoNii43jJgpI/iYTPUWGpbWqB5yK+XGTXGcfZjNDTGMYns
m2XEhjYjobQQsM8vjCelpYtjGqoFaw40UfEVzBdMMgLnsKI3HLozMigEoCpsdDgsnsEldX6rlMaR
LyrOtg0C69QOknJTIwCY3eUR59MWhoysPD9zrQdCFy2o8K9uIfX5xsos69KJeuSdTt46Hn8Vlq/O
LCjannJ3bXpj4nz7BHbNf1yqiG5w9JpFAj3eSPhtWoorw4D+vRNrstKr/mi9nBsuERsP6EegRLDw
RVdVlSdkcyAy4xj838Gzmo3Y0tLJFWjTELHwXIpfHENe8GLhjXlBh9xDTpXj+4EWbK7nKkaogLEk
SpRcgbmnmITAnB8hUTfQHimKyc5TUyokvvdZ9+7ohDEnITf1TE1vBwRuqw82aP0V9HPwC0j8/J90
UmJdxrn8LGmgMLVN8NPHBb5i/8Syx2W70nVa2HK62LO5pOhlfeKqqUOuxUPXA3xqGBu97M0d8R1b
y2HzBrXYTcJSC8PLWAlOJ30cr0fWcYzwg+ZifPRgmNJgf7AL7Xk4UIeyiR306vczhrdyXGmB57fN
qxWvdBBzjybfFVT1F50hYXgRQ0NY4dZT47ZR1tMZSULYE70kueQtRbWd9uEKBk9U+5vk1t54/7BZ
fZ0w8ruVqQExm/opoXdmgcnLwP5OqNkgTNn/GjZ/cGnU1iGwMQrKM5q8zgqexqPZivXSzbPcTzKd
I6OZD0Lxy1n+TaWO63nHhEZ06xvCoTsYFuPxpfXLQIcKO5JCFLFkZpRwwuILdv/clszUIT2ApWG8
u3PV7Q2P8llHIRg6zBYLA4fPHJUxVlUIxcfwy6yFSfKK8fOiBcWQcV80lw/aezwdcUe8AHUVNM+s
dw3jFDaKFpDJfQReEyXhV0E+1ozgBtdLWPenpKBVTt+a8b3dYv4MxNTMulJkqfou4CqyQ+sKQaNL
YFG0Sgy+6qH9N+2AOloEdk7CnImO8JbFxJy8mwmtDxFd/EKc2IW9CJ2D+HXKD9gaOtxRYLeiHP1U
8g0PhjW0uRgmR21PeKLxr5zdhSp9qmxmxD7S0uiJlpe6kBE6e5Qw1++CVDP8N6E6cAp7zWsV2WN1
NXMFhA78ZORcixbi52d1O1Y7lHRNi4IB4lArnxzCWS0ZoQMQC4FsgF2uBi2FBrfP5lfNpVGYlU2i
vJbTIvPRZT3wAwVRo8u7PTCk+5N8gIHsM9rXamRk7LCLQ5sxZJu4EvPrbF4U4UE5Q+6g8HqBpCM6
AasSMob8Cy6VUgT9a2eJ+zto0STCfZob9cHgIIPtkTIWzaru2yz2yXnhgUAao25QSGIfgVs5ra1i
dTCs6h7m0hURg2vFyyayHev1G4b97yhOifm1HHpkqWBx5g6MZ6/dN38bXmzsr873GwpfNi3z4tc2
aXuDlmFwp1aGGutrGSxH4hFZzV5g5lrq36+SGZ59nrrhhJEs27gzN9y95/66tKLeaHeEUQg74BmR
Xyn7S4SBDO7722x4U36btonaiKwD/VRbyyQuyHgjbyCTgYCqvwjqTCwO+w+MGSZUYYUieI8p0VxZ
hGuMrmER7HQ5zeh2qbTeR/i5lm6PQKXv2lABoEgM1O6+8HzQY9/I50lKJP7JSbqt2y7bjTWkgYee
csgOfzhveFpU8QQyTR6iV6rmUSZC6iq9Xo+QewCA4+P0JDtS0mlEWEcUydx4rN/znE0fKWxjn0Or
BuziU0tom9Lf/+KSVwi1G6WesnNmfZ0tL/PbtnA8hkCUsPhYbC5HuDKC58zPscc8WsKMzHKFD50E
oFiJjez3US885jDFqRxi1G4KhYz3o6tqvYVHee3lNBYkHWrX/MIfRsXTSx1093m1DaBHjk1nssKx
DWR7C+XgnalZxIlQD6VTP1Ij/Vpb8rAuQTU2SPTt27OZlXyW6P4UzvxFLtt6sqzkqZreeNGq4r3C
e33i/p/JmHh3Wn2REp3XZiFHmW5iMFZJoXr6D6l9XLAyNpu5WJjo6L0ERcpAYgkOUl97+uDbnXTR
RKij95+o9svEUCZKK1QOf/uYCeWkcz2lNwkJcWHf+vgo7VZcq7aUxydft0AmzUQ53hjbB3tQtQv3
mJi9TknT8tgfrN5uUEOaDKFrActkgx0lhPJWUJ2uOeIdYoSX+XeBt6MNWfrzNizyiaqK/cKX5K5N
5TVrmIbn7FLnub2EnQgzAbrKXfjWOLtWskxsBuYQp5RpEDUnJBtEqVGThESp4FQNGYUqtF/46mTf
1QBsVgn+l3nxhpIDfzBD5ngeAxAt1AYtMScrIa7Y52z+4MGpGOaDsU8askX5kZK5pqE+YD/UxoC1
ugWV7YpPuSzq4ny/MnSBlrptwBVI/k17bDPijw5V2Dm6D527jMovidRMSG4CQBL6LBOYM/R0mJlm
/cPR5e8HSjMlycQZDGI1WrKzSLdgvfm8+ZtppXfGgxe0B2IE2OYPBiUpTAw4GdNVIWQ6rV5A3UPo
NpNz2YaCnLmWGlxoQMPTYCSuwwzD2X1su0eTvwATZM7ph54THL7j+rTXWhY2TZ1ZLOUiHJCkhCIr
bHKqO+sTriRxNA01bHlyFb6lFmgoZGZWLfTGzjQZowXT/dlpiYiw+w6HedDVFv4FtCloCwl594YM
sZ7xWcleAKxTD2ABp8weofH8LKibghYdu5gsn7xcvHAhAZa4LFpeFUtUpyk1/BsRg69px88C4fel
IIYU9tcXD8E2SwVUCXq0aLG3PnHqQEiqu3kdRkvwR3ZU/dmRa5lMiRmiQW31J5tqtGq3oKUP9DMU
nenxhETh5oUtccEWcRM0rnQBMgI2nnhBAza9yAXdIexsNlpqKvfNrBwXOW+7nmKewWSZgCPp6MEG
m1KS2S5yk8To80LHCT4vTy2LXpl8OPFsLN3p2sgTZJbJb5vR/ANS/QWaaeWFyMdSbGdC8ke7rkJI
iswMGTjnQVMFCFfSCJT3hpGjLSBcZ6KGvmsnAf9gY1z+mFe/7h1Vtk17KtnkLJLEDKC3Zvyu65Di
nXD8BGfNjAzLWoMN7rIMduB57beQ9PUbRV4nRWJLtuoito1ZK4vGw2Beq/vXq9lwBtceH+a55Jmt
INsxJsbXcJcFYmWBA6KJyXdy1b7Zviwwmc6iOqdvu42lrk4ckDgzUDJ3bzoUqG90arqe3CxNx8ry
bF1GanDOsXegZ2XX1u49x5cEN1PYSqfgodpZlY7LjqnT9lQZ+RU4C9qSKJBztSiw1ajdS23yas5O
v07RiNr02fW52TfLGWssbm/QJBfXdtLqIOPaMM4iB2/RikPhjtNuyUPr+Cm6GVzyUgg5v+FSIDqD
17rFGeD3a59RDwvciTho3sRlnWFLgEQR/l260vlEPorHqXVEGxejv17UDXeO9dMVtpEfjLTWqpQV
5XdFY7BhM8jXSs0udTqbnnVlTB2ZyAmYAJjVN7AQZtr0VB2ZQm1i32IW0FBnTFEV8aRmG/YGmp0I
yX8goYRCWBcPbsKNLpPv5D8UhBehpTtb+qFaPahWCqtwVYPWIkqE1iRUALfphDKxF/OAZuDPyEGc
9VsAgpTg4naeRXYCAxEHqUGgPXC5jZLgK+FcVGRaq9307OrSWTv1ehswZxurDuWZ/70R/EplQJqT
C5HW3wGVl5yCDP0mGIxGz+aHqw55NgNVJRco8yWffzuW2jvM6JapkO3W/XuW0/639IrPfGn4CNTX
H5N+F13C/qklF17X721fHC0dscmuSgerSlE/Wo00DU4NsO5pnpAHFScqnd3ZGNgPdJrLDWJ1P0We
fINrQMcbIRR9w4fYk5d39QPfKB7mUfim0ESLoJT6ISd+MTgIUptpA8tfWceaEppwvKotALZWLZQP
I7SrED0jKQFIaEfmPldH//Z3ArmliQf9sc+A0JKFbKBEFAHvCgisW0Y2EUZXtC3bIfkbTBiqJ8TX
hVinNW49ucZhIWBnCts6DRqBMZ+Ghd92UilUpmnVbT9Cnw8B1JoOvG92XfFl/yXNqEeQSgAh2X0e
llHSobTmQv4ExRv/FcbZlnKj6qJP7cuOGXjU4ZC7wJzaRmx83UYHTE5S6XunxduKimjw82lFleOf
sBctCD0LFYK0q0D/7BgkFf2mGi/VAOMB2hyl1XGMdB57d1qcZZEc60JiFsDkMqadm6Sp2DY3LUBQ
pPyKeISk5qq/hI7rnyWx4rucaIcSp+SGDX2hck6ApVhAKZcNhWrifu2Unx5lgGiNeGO3yeks6Obc
AXJ9FGPFhu2GQ0pBetpQ7oV1cxQLn1BT1FFshYfHukQO1uhSYsyifBp6t5YQMrLXkxB5sjlkm8PX
pvpEP1KVkMWRPgMF5cSP83m2e3Qv2XZKb2VZUjDbbjl0gkuVKlX+JDtm6TtTSDTLZgpcOWVhD0ib
JCOz/j3b66XyDzpqJkcpJYQjkT8icssuLjVOlUpsj5oEIrtstRo8zdv5nnvYSfA+RTBdBbBpp8TR
4F9+TV0rLnSZDJK25PTkI/c94dz8Vfi4m9jfRR4g6lN/nwlhbUbLipMj5gY361x4p2FBLH8Uei/F
Zwp5Ttgt+khLUHeT3gOvhnTTN8Lpf+EcZw/k0Jumcv7habh5vtSaYjteM0eGx4o0FlxlQRCwVfZv
f/1dtBLIinD/q1xs/PfJVvmfHriV/ug4HcZfN7RYvNN6a7pv3yEcOAlN6H7+EXofkVFI34hYl/Fh
aVoI+Z3QN4tQ8DdFsmSEx8LYRH+n3BhI0wk84a7EHVlN8GhtmGqSWuqt/+QgG3p0gyisgXx2BIGk
I2uPxKwXgB+e2aDj3efgQgeeW7vJS7KrXCviwt1deKM6cISzlnUPn3FYai9PbGZzQozvJtItdbEO
mI7J1Mwq/pfboJ+RRYRepiRvGeKGHU8CrM9rNEjv2v6nCF+gGXGEDJ97hn4B1veZJBtMtfMfN+2z
znTnDdCaMz5IW+lI6lKbHFHVbav70SYN4uDwuVpeL0e3N2MgxJCg0kh70apSP1a7/6BuKRpX15Yw
ZRtbXbNXKDgwS2oFHmOiJgC5ViwvLwhZhcr4KYEbX7XtnV0+/selYWWl86ajenbhJSmIem3DN3f4
MAmpgjF95KRXXOPmsbKGZX0OXSL9N+diAh+tNKtCEj4uQ1B3HILDNNPVGHyv8w/rY0hF3KAmpvuE
ggesTlgy8APycg2FIwv3pyD2L9Pw11GohcXFdAwPJT3U9xBBuYUFkEtiYSc3v+RHR/O9GOOtG0xI
oHGFZXfI4hPKPyAqxztIVkr3cpCXoWSg0M8i/YCeAgRjY2MHAC4qb/XKLDoKTv1QTO68rxV3yYlH
CbP+vqMWP+oAm/8oHmjkawa/QKPLJlf2ruQTkhrTsNBM6THZYIQ6q7jsyoQo3iEyqB+7kGeupxRQ
zulnbOPA3If0oTT8R69hv5ASYG4G/6/mtDst4FYNLcsy0/WtxjpQgM6bXb7e+pW9ERxYaCz5UEOk
HKkyOAd0ysn/DT1opy/c1We1jYPICs2a0aLxNwymdzXqQ3oVoedFMn1tOndaK5T3uTcikyOVzFvI
yf/QL295f4gQDMaQvKPD1V+QnFyjfHZV9w3/6KOlxVCNIYG6gkkT6/hK9vE5proVX2gRVioQkK9C
+U2ASrp9e1mNRrneiahJxwIHWn/3k2g4uZzIuqHDf7S24GuW57+nndWUvRwMaQgbEY40uCDQBaSn
jlI5yp+kYdChMz8s9nupihJPCyfBDq4aiEIG//x04YxoFTkdhUdB0aPAm1Oeg375NtRIwfzwtZ/g
12gutYxAcQ6jdkE5EWc+DgVSVVzuHlPo8wEj1KSi/wYrYx9lLu/9xoviO8q9SfCAXkud0lCfq0e+
nmrQ42roHQMnQmsCwr4SHVmrKw00vb9uyCRc7kYnfTB+aAkn+agCMDQWVZVuxgsRsvBp72nXUAGb
mm9hF9i5q8FS5D/SZLWTCVsI5WI5PYGQNPfuZCoF/J9CNhoUf0p8Dn2SmG48qibc12LKSEGjUA9U
+OkAoCZjFVB8kGRc8EdY/NKRM/b0LBGLUCEncFfd5z+URNqBO671KfUG9cX23mqVzKzz4qUPXaoQ
2V8gRsnxp2AolWmDHBuS+XhZW9tfGh6hZ+wPKYqLewuBWy1zDARJ8PWHqd1AmjJ7+yaItSIQZJW4
OeTpyHRgbqUcpc+5XAWylfD45G9rO9NxBNeHoRwD9KtvnxZEQrVDDRbrvajXmSg4Z//igckDZRYj
HJvn9004k1FbkJsFRzMiDSDorV93vHQmtfehNukP4EXVcr4us96DGyORR2lt9wkIR3mbE+MofDv6
Gd13gLLPE9IJxKCkl1GpqrevGwhPz6FgDt3E3/eEC9YFfNGR3k2Wms2FdEtvLqjxfhKEXAnSJBlq
FFn+5Gm+7Kp7rgY/IAAmnHoVp/1MXakDzBTgGa/WzwkT22Okv9HTLqmNS6LDrvpr5DHLOdZykwGl
DyrfM6vns1+b3RW3r6MASe/iKImSlZA8IRajbuz6KhSkDsRLOtrfbI08idRNY5adGiV2zrkwTyWd
/VJZrd8LOBKv1VIdeieIMjEYY9/WuzJcmYSEt5bpatY3rRjm+2oNAQmHu/ovnyTyikRP1YjQgpdL
bqBTTdW/gMSeg8QM2UctiyVq09zXawUu44c3BM7awxKRv3oU2NUb3l7o7JqQsTyG+FfJ7DRWkhvk
vF4wD/0ZxYj3LgM185rmZofiJ4oMW2mmYeWgtC/LDOnJQiTpw0HplkF8LApOKbAiDHCCtElOp4Jv
hTnstPMHyX2ZpuBZn0jMq1rMQg4+RsMeRbJ4z012N/SClTh0Q2Rd2RH2bZWEC7rhETKCDDGma0YT
T1lOfCJI92egXVwQWH1owS7HwVU5MrXksHC9Osm88UL6KhckFO2Hy0bjaPEs22fGqXalezWWwZTA
dhiNc/HdkvDhvn061mjSuvPZ6CAgmSImIvWfgbolviqCjc+KVdtIyfYsKEAiBQplo7QoKRqdDVBn
W+S+yQ+T/CnWlrZTkDLRsPeKp449YMTtZado1Nw5l3nQXxiybQ4+SqV4ZE3xB3t6QAy04Du1GC4M
TZfsD+wQ7ydwbWnCbHzZ82ONIAaLCilSaum5gcT9AW5BTWGmsSjVwZgd6nPFMzPVFMTklgWHO5k8
Zoiiu9An0FQJ6QAT4bUKByAAv77lPk1+cMHJ5zEyxhG7ozuQisSkj7L0QtjkWozKWEb3CNuZCDJ1
97doQm3rLn8fyAiRm3jAEGMcj2mvEkC90UNZg9vJ2HI2pGAasFwp93reeSvuWkJLjgCfNrLX0YYX
0zi9uvzIzRl8LEl4HMSkEPKADsqNF978V2bNGfAFYCDpqZ/PQkQ0ideLI3JoxheuqG1bRI2lUv7s
Rhuuah4x/skIlUxXMM/Dy5TRqfEKKnO7YCBtRTrDU9vz08VRMZdSZSAa00RJRfbvnAZlDI0gJx9+
Wfq3ze6THskWuM/ThRw7bhi+TXpzdFIcHYoiYBIJydheXf8V/YsaInJshZwBRb6p0w/r8seuGrL4
1sdwT6CiRZtBruWtd9lgcJNtOD0PxSQwQqWSJWVtGkI/DJD3Dstt9yYpvm+y0lfVWAf7W3eTkmnP
zCVVdVML+60Uh9gyoWAB0IAyZr5SjDNytJkMRkowMiErV7Ft+u4xhHQYkv64uJUoQ2iaiP5XTI0w
rAwE45s2XciriEt5T0dSSoWRZSGqIVkNFX8/pmm7E5h8qwYtU2Dd8INkS951AfmH5qHkqjRM5OZy
B2EGyXXcGK1leCH1jq4ZxLkIP+jdCqadSXTc5sEFGVgDuy6xE0XlvV74yWeV4v67Ufw6sQS4BwYR
j2cjT5P83GO4O2P4d+fR9sojq3AwTrvUxYshxYy1chPRObDjHNPoSmMHG5m5MdNFXWWRpsobwZ/D
dJcD7N5hyflQM1nIfuhRSQ80OhGCCZ5LBW8Q2qkE7Oq7U8ECnIPI5rbeBKa1Bo9sMGrkBjAFUNer
QT4DXje4KH+rjderi0tJKmu6DB2l/6cATRIIgM8dD7Ub470g1tjb6TabBRN/DjDE3/z0p62dhXo4
F5a6QrUEq2W4RaW2LRi8bTcPCIgdDI6PQYLfB6+lDYgPE1hDQNdmFj0GJTN5kpOz55xzKE3JvzPL
mZIgdvg5GpgnLYoToDDWpkrDiwVy5Ib2su3hN+ZQpHyS0pS5nM9L/idhvOGTUUqOJDWmFyWFcJK2
P0rJSlSSw4mp7KO1RXXpt3taNjsHOWjGuP0QB9gWfVI+pXHXxyIgdTSoxFA+WXa3j7+UuPClyJoW
vnf/ulsshGV+1QE/Hrl9kC5t57qTbglNWmTvVB2Snt9s9jJb8TAhwJ7YOe87zEUULEj3w9nSV6na
WS5QoQKkhaBW7Yw4qbZbQXh20fbirkOL2OnOeaAGhmIzWMXzpB89mLwfYjbK7qt6quJzzA05WblJ
ti+EeOehTyzg9fATtuiiFRBeoPMEHFVe/cEOienXLFu3ZFpF0wUMOQ825S/6TeFnZzePuba8lxeT
LyGCgZUxsJ/UNK44PmiRurffXjWYYU7Cic1fSWZymX/D/tjDC/tOL4zLuRECMj4dRYvLzYclEbRb
2WNpXTpDgPkciKe3fJphAnenRiBSdOkFyGI4aWeCQbcIZ/edIHpUZayQn9qu0ZJTnOaOQ7mtv8Bj
8VtFoNnr79ua+zAEbHBNKfxf+rddVv0wz956gZBFvVXQeE+KIFW9mHGO7HR5l594cPo5HaMEz7FS
jBLHTMHCp8LjMxjbC8AQfLDoA/hPATI9NWn9sDQMPAsv0CWLjbMHC2VSorcR0JrofIBHJqyEMd/2
juAO1pv1Zs+6HjaRaTRybdzBSeBj4sa1Ej0y+mvYPuDP4yjWuPYOoERk+7zBXnKnm/iyQJOj2p6e
x/ftBvTQgRbMmvvElcbwAXrITyk4Sl2CrZ1umrmHJiQGoSbKmV6XMUdIfGUGj2FbaLimHn/1RH34
3KW41Z48lgdJThfbDwXaGea93Wuj5L/CMWegLwT2KLOTEHJgKSQMr/qDlbeHPjBsriQB+Om3S4HY
fa928I8ql2kJAEqcHRnupU0FdzA8R4Cle94EazHbdWe/38ft0rLtvoKYaQ7mXq1Q3G4ipTGw3zof
LW36uLNa5CQKyxCQOpZ9DqeH7qkqFBr4pi3W5dNo0/kJzEf7DS2p5h+0exwSXVqQvJLvR7cRFGSe
iWljJeaBDbFCEWGWzMSZrBfai6EUoJaiJ+vd3WalQKkb3orbA7ScP7cupmj7cEn6YTmFOncqNlVb
wTM79SmD17Rpfz4cpzbodaC6zdr0JvWmXp0E6ndRBsxwqp5JpIoP3dYJAdpnc5gPQ6UPDVgd4+eJ
sa9Ot96aXZ1tXXcN7ItU37rYutgBGCxAqj45OdMv/FvIRLZC6kzXPyWcPtTCwZ4V7Vt6+VdSSH7c
C+Izak0a5+yFuXIHU6592Fq/BtwMh8VS5/vVjUCJTysFuM8cjXhcmkRc20lcuyAcVB1xZanC+lQK
EwweU3E5yuyy7wFOBQnt5VMGDDbI5yoCW0MmmuMS/muZ+kclgDRvBsmL56DSkee3eUVAQx/NQ/Cl
YBzBDEQqncWDrGdv9HPjvnHE3JA7Xp5ZBkWEOuenw19BBncQjheQADnxL6YGIw9rjkZbeS/3VygV
z9uvNNgQe0O5c7rDQB/V7e36bJH1XHSUryNOg/hun9VtiNcf4he4CGXGX1283klpCBPsQHQ8UOuk
ONUX15ETSJ32GKJaPwpHAsqIj+qvM2f86ymB03Pm5OW0kJYbT94pMDfBHcS3azZllyrQ0Hk1/fna
N7RScOAXmQ1mMagLTMQV4btKcBe+LW24mi74aVO6dx7f+u7+20ELXyQPOTxN3DLGdur3h0F3O+QV
S31YF1kJJXk8ZAW8yprMpZo+Qt/cX4vi5wjCouA7BHo8MPbr0vipFanwxWixKwmaypkifjQQJsXz
95aVGKBPTCre2G3+PL2CJRzhzV6VGoEvmYYgVn2Gr/esJqqYt0VEudzo6I+IA9awRSEd0uXRYJXc
l7slUUtA3DGQUPI26Dy/A2PHxARZwzee5uCLsbz85/0jTHZo8geK6WCU4OaO4JzsNc83szDUgdUb
QTBmB93ID976yZWDrFvJJjID3U0fZct92eRGlanly/kVnPOuAKM0dpjyuSKDDKgeBAV7sZ/0fY1J
xJWzoVCcluxVpDjVPGl3mUycrXO3IYwTJdTEcNCfCFv5KJa5sd+BzSS69R6r3Rkv8mXO6Zv3gUAl
G/Ut+Ub39EwfrDfNMThpGVsjMBkkLDL8LyjSJKcVPIeHOhlO4ZijWe/T61Pr5ggflzn2yRQ4xAwu
AZ1zabgXCFCY2gLbjIqVK6UNG5gaefX840t653PXNmqUh4CyDDaLGkz7WoH3T4RplFOW4yqOpTmk
fKXfmtLKDN21r724UyzN7tYrR0+kRhylBRnMP5xZ2ndXG1PFBmvOJ6nyjePJ8PrPvxzcPDtU/j0I
lCS6BSr11jyXuRgd56UJe52KgImQe+dEL4uaOQ8WENom2Qmg8dNWgxVaPMUOjoKH1S1qNc4Do68Y
jo7Yg1fH8ZCbArr99jygnl7o57sXez5E3TJfRts7QS9MhvqTuqtdlFft+crX6S9tyft3vW64Xvsh
CEJlw+zME9iNazQyXKR9P1OhwLVZ+5CkA8AaXQFEiGHZdBHi7IlfrY/69T1RTYtMvFZVWoSNTpNC
q37c/eQLk1DHJqfbUqYfqbKitCvO5QtHm0BF7V1CpbZpgt1Qb4AZWmDw97Q8R5Kjso82B4HjHV/U
tfdXcfP2hxsijoxGc+cNahpYBK1vPmMIVz00H0qubbMA0Qa+ySURcoCD4QAc3QedUbmIWZXSF4pF
y0OUKxdDQ8oS+720C+pJWc/GpWUAddsrE1jQrvjzP1/ThQnuEDqW5rpn8lqY2QH1g0M5G8IvSOHl
BrDHccmdBGiUT7fkoyxIRNrHwXQEFRuuyf7NyNGFEtlLiciFslgpWvVsgDgt1bIw+7WKL77b8k7g
dNMve7dIslnS2EYbouNGuIsO6r3med+ByF/PbkfQ6UmyU3PW76vj5LU+JCf51QlANl4fTDzYk8/d
NqSLzMbDxxp3OfAyw0VC/U0hQPnZrgfGbnQqSMJikz+1CQ2FxgdyDXCtNVnGJud0VQL42p09Gms4
rMe9/Z6itsjFXqThCUhC6J5ss3N8m0RkRyn5KFx047T5Oj+yURIG1LxXNWsR3KErzllpAPYoXGSN
T4z/xih2+OWlVdP4Aqt2eXtMaBgv+eGrP+D83g620AMh0hb+c2oOH8w+NZr11qPORbOxYiaOpGns
tcSaDrqczGajPx5GEVPJrYBr9VRQc4Tn4Xv3Pg6s20LNQE6Mit48xpZM3zcVwj1nM2azUDxhOQKO
xZuFvX40Pm1LkCIGSw7rFcQX73O388pY2jTVCV/pml2r+nXKuF6FHdlWS+WdvpzIOPP7VRXjHgyR
DJYZx1oFNDjULSRmqvaQ0fFE2EiI5OBl7TyOakucEL88Ge5BTq6W1MxUxz4au8jIj+9yl9O4k1H4
yuF7GzlDUMld2M+czP9mxA+X07C5tWV6PaDswMOxZduKWrC3WPV13WuoMNnCT9GK+VYJet06cygD
jAuobc55/usBihR2w99ddTpALURUXVrl2VcL/mv2EBzGUihiH5qN2cy5cIOdLLaELHy/F9SJ9dIK
ZqLcYcGSyKvUO2IS1KJ2idpoeKy+y3kfG1imJLF/808PxnciEbH7f0txtnCI2m7dVlKHY8yd7Oil
R2uarMBbCOOVJhT1yT+yWrOEBmKUEHcdjPn0loesffvpSZj4r14qm+LS5cSVE9ReNwkLBEVgLLZB
7WtLicnubuukoOsYXGQdcX1L31HtdtR2bJ0SZtUICqeP4OTX5vjjEDLgoyvGbjEsNiSAE3cRZoJ2
Yy8WfTyA1V2iCp3BIqSvnNYbkHg7Ww5bMvMU9fpdWmusO8Cq+IhG/7PvlWf8tt+lYH0oHY2GnJcM
iH2nV9+d1kn9aw1HVw2+/xCF2RBu8lB5/HJ5pSuqZT0Sy8ksVkqy6lF525f1BeuzB14Jdm4GTci5
cQpDvXAE2Nnotfkyz03SinAdCaV7TFe/Iw36f5nHH5D0KYOfK+GDMTAyhENRPd9GpDe8kcdZWZPN
3/iOCpOC7pnOYRcME8rptxfRp2oJAZASKgrlxIRkwXSiP6GFwQ280V813sSNTb5NWt13YBg7nqxi
dYdS3107dl1yCbkjcpOBpC1f8tmDtFI4iWckU7T7gkWsEkMAOwCiKsD0vl3hpw1HnjVHJrf0mn0/
ayuccPBPAecUs2e3wJtPwoFNkvAYYZmmvNbzYw+xrGRAkvtS3lmRiG+OoDeFwF4my9Zx0lLBi+g5
H1uKgo5Ff8zUKEzaRft34hacRKQ1gkhlodl1V1x1dNGJ9JPcC2Td0sTLIlX2i7fQWZFsN4Sunyuy
NpvR51MG7f/1yPLV2UBfZdcUHCSRXionVZTNKzodiNgmHXECbviVIal36XRtlhd/AD3BmX54f/Jm
gZtYUzlfecXXEKF25D+ibMY5Jy2mh2RzYHa7JZzcIUGhhGQU2pKSO4/dGelu4lRtUBLssfTww3l6
ddalc+vbMK7cbY0Oz1o++A6GxHsHQ3jUI5xw2+RC0W4F3WVgzBHKdkvAX9bnk23o+oUyyvTEBKgy
PuO/AOjF6LM6Tj5Idj9EF86z+VvWpArBNaHl1gs8BCpY/uPWKUIyOQoQtST0v/5sFOLF79hijOq6
AmSa9/45Ex6MI2TMv4MJDD5oC6bUa3229Q4yvpRFfMdpfE/2H81P09+C9BAgsf0haOY6+xFq5vt3
xqAZxdyifuWGtMPnfq1ZK5R6B2NmauI8aqPReK6NTMgDnMTL/wy9chLRtRrOG9wMNh1A51IC76v2
jWYjF7Vz+nitnhR8Ui+dEeZPzf4A7MHwX92BRCNlxJAqmKUM2e7RFnNzZb+xoEYszyicR5z9P9B3
SFxyTMSUtRbwnUAvvNPsMnFw71lrE99KUJvvj46OrU5My1939fBU8E3bOe/u9tEA+GhG+X0vQIaU
mqZK+82lnh78eEbRLnC8idFWcfOKqFbnp5uarBnEYazUsAjJuXdJVP9mCrbaPAa52ZK4OFOTx/if
ZE6ZYxSe+z6R60VyN4V2sCq159CpPo7OClR7//6E0Nnoq4qbIeIYPOr+ueE4VvZub8VyBZzjbiQM
6HbkhDei/e3buGPWurZlbi6COBfQ7BJG/6V/DcDZxjN4NSxhPu16di3WV08v1JX7891oNBC7uxsX
FcvKts4/uOHqHJFm8lFLIA+215xGZDfCQ0ZQdNWO8q374qHbXDZuEkkU5ec1P+G3drNhqOWx1QXM
WUmU3TWvyoghCcOeC9AOauXzwGWtC4VdadNaik2M1TKdh9/EVYhblOxDM4qRzs+x/YCHnYi4ofHe
Mm6E4Gq6/7W7HnEMu1tzO1pW+/4dXSoSdSo28YBZekySiwCAR1/cvUReQT/ZxFGThD154i7KBZ6O
iQT9X44hZBupj1RQZCGy7BJOk1DVYdufPxHWKU5z1IH3DvqeUClWNokZVOTSgB2Ho2/n4iezE80J
ak98BnQBOM1fmAMiV856sq7mOEb1zu8k4UJUPx+TwHKQREtVT17vHpFVjpp70PAaC+RBMcAgzbcv
Mg8ijLjsX/IZ9HoPRiUSFuU4YBh74gm6IOS27j/NPTCKT71RG+Si2rxh2W1X6zBphyE4Fy/TKggZ
E0aNaYTKkJFj506pjOC1aWkwgAgHfICzg/4q8Aat35E6oSw2RgG2stOCy52Vni38/AGf2TZMSOR0
MbSVzHVNZ8bBUXNqguSmHl/3t0FLQ1e7RmzewRkJPecFRApIiemLq2H8nw9iOzP7YBummjlYQIIK
rbmNSkGmXHVIUJjylYHrxx4PM6q6Bpn9PdKyV3H7OrTtChE2YaC7t2xZyOkgi0ANSIO7mAusMY+1
6s38aHgPqJyvYkWcA/H26oi+F/W8B7O92Qc324Pvf+JIySGiDueCK5ppPtpndgFJISrODfi6RpKd
q0a7OqVOJvp/0lqjZLRU/oqBE82SmZqe8AEvx/hOonNqotGwTpr5pA+Mu6tmSCuqMv/ueh7qvOFp
wi7jfplvt04kwvB14U5vV1+Z+79NQZr6KIgO5FpPecJTLGYDLvTbwALqLWz51oaRcrHRSgb8Su0S
O1KPqgHOjETX/3/u4H2CHfjQSRUNk+hLZziiBCSEoTS7/zrzuDwpuLaVAqJPrBrxyqKM6z/EbNqu
B7MMaaC+fihnPPorTUCUEVZuPKKdQXMIg3gEb6+2b7mrSBGDH/OszX5aF3zsWv3by4SRdZQmKhIy
5Aur+6O0O2009ikHWjFbMA1MdxGHbdbli6DT0xYkMjiJ/sAIIblXL+72zQgcSJAfOABtnG14Xztx
ACJQOZfAhw9pmGvYCIPq56gwWPmyMl3s4UrqrD6UOhCc5ajHQKLkyoERS1aq+SqNZfUCgVyOI0NX
AEJNq9g3hQ4Az6aTLdt/zwTmWIzg4balCIUk6xrUJx8eVpgOMlare/dtTnj0nKz+Tgrxe74oQ9gI
PApLoXJAiO02C+AoxXGjOx9asv0ZJzIfcA4weKRB+ceAxl5o83uTGczs/EgR7JK8k/ZKZ00GgJNz
ijpduwv69nTOUBmScvIhfD5QM08ILJea0+IKsk+9rxqE/fklmFqczcFu8VQy4LEfN0NQCbu1of4P
E9/YmIc2R2oeJSzrbx2mMtNqN/w8kO72sat9TsJz1hTpXYPMHLyEDr1YZCcjZeZGL0wNrqVhFi4K
UQKzR7Io41i49Mj+0MX0MkgmMp8gwAT+i2tglfwiOkgX0k2s9o8Elu0U5+Hi3wT28UXPtrmNBcXZ
6ln8XCOCHsa9kUTFrP1Kh2634clJUuPjKuw1dWmvvmKvAa6aGO7v9qucAqAIHAgg5xBCdUVeCmOV
sqgfpUmn18cTIgHo+hr/AXC1rTcAzysR0+5XUrCcTGxRtuVc9cnTYqvZnQd56nWV0mZjynxGFEEA
uS+vMTAmVtVKiYtcOJNyrS9D4R39ZPwODirqKKJoWqf7Ol+rzS7EWC5MdilHVp+Jtu2x72XWiCn4
E899TZA2eYCnfdgJLH5dOyFhw2XeJPLYHB0GoFRiN3V0xKuP+7ytvfnrXgxFEs9XLHq5pMO7lT/o
UsiAft3nEH0PTsMd1T/RUUclFuWCecrYw7vJPo0uq5F3h3/WysDMx+ys6cGmq7IAa8OUuaL1B7a9
n5cC0TN5uyKYHEtmnnZxXLFMkrV4OetYzVNUrF5UwyCECPH9vUSvEr7dtz+dPPAJ1pHevMNjXhaO
G1uvMWlLkogEbF/v1Z6JQlVhEC+dSbxxjqzxT84EjjT1CuMJj+0WNDmvgxdLZkQxz4WsEQS9qJ3f
gtXZdjhnfwUpvJapVuCbpBqn4TR1WAiVEesrEbaksqf57f3RpRUZFZRCdCDJRu2LtQygytOLhJIz
EeApluf5ZqvN+KRLAqSBF+vtMkPEAlDSJwwRz7ycC07HISlTmarHLBfrg0DyGNdhaCqTs+5nM55q
5Jrh3iWKqZk8bqWH/y3fng5ggPxNz/D0zgLwLQHLrmSsN0shsmonj6oSJniEw3PVEyXgESq2Lb4i
Z6r5kay38x+1ufws+uJhPOml7vHMBtIKPh2aCaVZGE8yPExsvyKSaCdMXCQ1uycyAH3PSkmBIbcb
85lK23gc5ZUkKuAZvB4pNAgdX+aci3PcqCzPw+Uh5kg64Qhb9uJ7Gd7CkfUUAdm1T6ufPva3qEa6
sJBwtasNt7KzgO1V13fhEWLpwkD91Yj0D+/p0YoCE6IrIo+MLomTeI4uAT7lbaH8WGo2Huiesp/s
kMsqaQELKSjBYTTXWZzF0ioZOn76Qe9YNnkgpFe2wZMQJYWs7kZtcCo7ZM3RblU6IzzdFeJ0ouAe
lhNOI50gQEHoLQB+S9mywS2GQGMOvNtvxaKsp5yHee8B3PL9r9dOqprj++BI5Dj8gQimubl9ypiE
ePg2RyJrCXajaf6Ea1CI+VZq6POikQ1EiMtAgkciKTaDIOpJ+7S7oJhL2XALkHNvdiSfV7eEsFon
G0WhjbIOZl7RehhVMZr3A8m89iHwy6mfZ6VgVwhl3pNLWikAyQQ0PDJC5f/N//rzRB3IxnEI/oNH
ax1DIx1uR5RdcDrTEgI21eovCTcJl2NH+5O1aIq6LLDZ5JXqyQTDze+ceFKu5aHlMatpvZ6z97M8
1J17raoMVrmJqaWmHVHrgdystfnZ01DsV1eLf4UXCewCl7m9coBLzJ6RId66JK8vmwM8n2z2k7ri
SlmdznLNgYBcdBIPX98VO3QYKaGWTMrooQCKItiNgPK5AUyrv79lWHpu5WOXhbGL1alSxTtFtezw
EW0lMPPlBb2vUCtJQK7tUqFsCez0kwwvw6vnAjvWxOIeVmh5JnU1w8t6HHDnL+N9VHiV2BGoMvJh
ZPVzCZAdSnaKZ2r4uVR0kn8MAJ9ezdKkkSXHFg9lZ0X2G+Xj+mXaWNIkaCYy/R2Z35YAUNR2BRS+
o6du5tCA7Ee7pWuxNYaztRLatg9o6oSQ9T1AMBzVWaztXSD/NyNYGZU0zicyHWGzPJeudvOY+dsP
YaWLzh9+PwSa54HAy8Ac1koYOiNcHqk73igVxL0p9HtxqJVCkEX3hwuVHWkmI5fFXhx8bgeBawEw
UAJr+kTM+n9w1I4tIJ8TroxAonRdD6+6YLpBuozRzPuVPizqdEGyjVNiluGqamv0NRUMTBYVmuLC
pJXG0+jS+WQFAq+7C7NHYue91MFLa50NBz0O4L1PgZJGQElPDZGwY+KBPn5xsxQKB4AF+Fc2UER1
0Zz1sTL5XgKy84yPirvMMjxiAm8jUmOt1Bf37jPwnqzIaijanoV8Uxn9Ljo0PKnuy7lHm5evt039
z++dqlq6PdgP7lsqiz5Z6Ja5uSgpl+iruNdmo+eFl3B8pujS+rBS0uxnmXq86BSy9e7NmJj64YrG
msZBMp3KGVMhAWWvfbm0TLVV4/V4JIZWNkP2rShM3NtXlgDLWJCTuqNPR1v0wDnfqVnn3v/kkSwn
6RWMKAadnbExuekbhSjGT1OcKy2tWjDS8XdJxWkXEoefU7qbuUmCH7s2MS5VQ8iPdINPJPGUEztb
HNBlfKuuP/fgGxfdIN2du+JFwnc5Rczbgh32Rf9V5/UYrLhZJV0YNalijt7QA9NFRg3mTG0DfheI
ZLhRps+XKTUStTbxZeFA/gt4cCE/acr9XvGdFbQEyl3F5G1ERCSaB+i0RVKIUU1/CTs2Ps+lWk6q
0kef8Bk8N7KGVNi8CYfC3+1Upfc8HoL3JBo0ozcpiarDvxm16fdb3sFdVrwRbbe8UtltOTRFTOln
VSz/kDU8/vMXpNm8pOTEbHZJl/qOH25LWkwBNzI7PsSFGvzQADU5UKg7cnFhevWJ4bxCbdxAhXFv
X3u8QLNF+kRYOZnbcpQ6p/6Matc2yk6KVcuT6L8/Wbb9+/ggYLnCbrDwNoLWOogsyaEMVQ/GMStb
Jm/hpMsbtHEXGK+ctonNW23pbocIwaI8h08Knz97s/iApx3nuT/x5gintD0BpqxdEDW4H8LJZ5id
V7TFZvkXQf7pQR9B0Hp5U7MPHxzWoKaQf3lGVnkiKGP+QWO0R6GSKQWahphHQjLQyNAPjBCBomFu
PB0WVD0MLapKXxTWs+sSnWuFoXUWOEGb0eiPeFujn/9qcFgeJWVmvQAhUxB+/zKe9ZAgFAwQ2Fws
qONy8YxG215vO0uvljV9Jkx06LXK2D/5ZoLPWArFrqoA6z1oXK3AcYsxyMvtzpbuAgUieQOxvkM0
xy0ZlW96mtG1Il9x8YFEcaLSwcYYx8KVBETVi3dCsXDxaWdzJ1BFVP6JnLLprh+OHWUcavyG/Gk6
RwaXZsq/mI8u5D2Rci9OQ/ih50e3qt3YRA7XRCKq+XfLjeZcl+jBcUigGzEcV4wc1crd7y/qCKVe
+KKZqndHPpODmBrSmWPsQzoED9BfFY4PvEHp0CD9dRim57379KhjOX6adRKvVP04cvXxB2z+6ArU
ojChyxZQTEVu2m1azw4aU4X7WodAbyd081jqO+wF1OE0yrwPOdA0CaFoHIfWm0g5Jr4qDRkxDOq4
nV8iRL5lU8RA0Dwx2kkXtFyynoJPxhnTo2btdLRdNMB338kqldmvx0ZD6MJ/F71MyKmmLJWWXE2n
EWvnrhLNiIP1KG6vrvjEdmok8xJgTvG5rD5DNU+Mu0lyBs0JDQ1SwbwnNFd74sHLLeWpcKlBzqgG
0KdNP5sgwqOE8GDQ3r4VYiCRNMC1+h6rMhtwONTddJo8cMCHsb8TGP/nptU4SH+SpPfp/JjeIbpr
BlSR9Eqh0b3hOQdYRgKaESmH80eQgjhZ7h53G2QgKS31Jw80805kPX8UxH0AXltID91NAY9z6t9r
Og8g0RMRlq59chd8UbqDncJcL3ASFLL341LKzmMxRo54JwC0/C3Q+JNWZVWYhEecUtitThze1Nkc
aDB99cbPJJcSOF9pmlkclOWJA5b8rBr0giZfxdgLONPF7Q76rRkrXndNY9PikWYsyXcG5JjnlRSK
bfTc9SjMtFUUwNXun/zDDrwuCF/UAdub5gfrr3D9nIpnDu4bZcb1c7a4unXuriWQlS3LtHZOPz0d
svksIpBJq89p1q+Yc4wsVGwtzV2TqDoBlP4msCqgF3wP3xBBV1APDHNEfj85VC3/39RIMtFKidpN
AMcqJsoJuWXELDlApinaPcla2HZkEc13zMEl+glITjqRKxC4cihPiZweP0TxpsH1+Bv86iDsFPIw
WwwyAiVaucemzsGPjbzKZmXUctf9AuTzl7JX8Vb0G18Ko0PyLVgN4XU61TSXqvZhZqRRtihwtVkV
MlzZSAzFOw1S/bUurzbdLbOY/hDimFiPmZWeGML0+3hAdUl/OzowSD5qARzKKtM+AvwLnUYa2ryD
vTDUHvsCXQy5sCYUxO4TA0uT2Qs4eP/yqqGTl8OUB4P2+igKjVxYoy5Ejn6pt2u5Ut7cDfr5N31u
SbnsGX/WM5eGZh2/alELM1AgtD4+ACOxtdztrTk8iwhEqjSAnhz1WfZJNbHI6/9tHyPI470eOgJ3
3bw8NZ9C04o0K2RRNZ3zxqEZlp9u19ALCfktLkQfZKACyp7Upm/b/zruer4rKbA+jSMMl9mqeQ0v
zDoggJeKCroFPQ37o9w02sd3jJTo0hQuEpdNfXjO6vDvI2mA9QCoTbeksPzopo5B0sQncuAatiuu
e0N9IRtH9TC534pORf+6VrmUThaz8Fq7LGUP13DKgnGPD+KhumSYR7+Va1b8MGWqKrOh0j/OIhrR
5gLLlWyk+J4c64JJUvN6ul55GjTlvlRT7lsy9KFGlb3ynJmM+TcetXdU7iIzXH/LWc4wJM1c9jjS
58JZ8LnUnX8ZoxSk0nORPdO+5ALSMw2/J4Ish1irSyvUjhdBu5ma5xAL0JS0pf2lsiJuaL9yoDkv
Y7kpfxNXUiD3M7guWF6YrDguHpz5R4AZdCc+sOvHj8z3YFbYSWhslPzQAdwGHAEtNSyb0zFSItWT
YrSvDOlt78M0WVu1QFt5AAsztl7zHXR7OaCnogtIGdYa7qIvnr25MBsoVHgoiBFWT++3F2OYoPJ2
djASBxUxvsRX8warntffUMhknlJyoGPLr64BPawW1FzVhppiyMtc9Ued3m6OFOIUVosMDuWcdy8F
daI2fhdCbbu76QrKqfwjXGIud9pbKBle4sR8uoe7/smQgSXgdxm9M3ENw83SsK/xn7Munxl4U+1o
nKdrp8bPF2BDw8RMWmZ+9cbtmKYQjYcx+syPRIaMOn06ojHpvMQKgaRiI12QX1hJLp6TtA4O4xqy
3qn3/Vtu/XMdYIjgaLhi+JX/UnWolI6X+AsMbB9rrzRvzS6VMqvidGmuygfsDhZRs1cc+OgbqGcH
xFdnhZRDJg37pR553y3bPiDgudPi6FaY1MMKdAeMMEwerxg3z+ywcbzP2RV+UtNDGHbbpjP7utvO
aZyG8Prilw/vFS1/PiX0zNQh16M9PF8gywDbE4WOIfXQi1VBLEdiBo/+4gVXMP5PjR/x4LPmfoZg
Hb6sr5X8lIiXRj4PH5A4JU6XMHbExfITxIcgHzQvBwMHTJa8ckEC50oeoeo9iKNVZhQ+Cba1F5ya
BohHpC8NBxJHtvfoN3LEa7e+nn6OjcZ/ecScbZIpExv3WEcHZhNxjr2oOv6U6jWJwgvmFTSCp+Le
KL2ldcCivuQFxtA5M2dvScGoNLc21C2XeHCZmtFD8AQqDDuuKIc68Ce/F+0cAUyG8wdhGaVb0FpL
WRNH8I8Vwdg9qjyZvS3uNwajjm56gTu3dUT58V3XNIvIhb0OEOIyoBiYShYbdr/0CIhZYLB3bs8A
W9Vx43aS8/ONi0AOvG/iNOHsoYolfA0zZ2BX3kRM0GEHYEJql7cZ4LYn8FQeOH7az1JyUw0H+3un
Dx//7CVP5LBPvDfO1WUNLm9qaq5867AYESSeTWe6rw2Z9Hw8cM6h1lOSNgXPEBUKOdJvpKQtjShO
Sed+gCPZBLwfJwlX5KlhqZYbXwn7+JF2Pu7tzoaspjt6ykYXFFHnPNl+5ranb0Yfdmi6DH2po7d6
0V48uP+f7434cyUAQLbRT646oYQoOwkZAHSR0YgiIip80Z5UKDT/hXA0ezvspKEI7KPuS/2QalNE
sqNW/qpcJdTSa9qq27HZAt8xVz8uOTfxGqejfVocui1oOa7Z1brb9rC2z/X+hDh16GgKYm8jZtGc
ST0T5TFTf2Q1oi/yEZRjc/TwXqbd7Z50HVjJHD9tUBlwYsNJ9ZvVKkjjBiREM+OsjnOxqGWnPseY
EQiJoWr7q+Mgc5WVBf71tXRKyWHE2tC57VGerCycH67wMu55dI36edj9SP63HmnvdZ/A9LapCFOj
iQ08bKt8xDL3nl7M+tcx5DW+43SFy6UYWZ3jmXz1F3mSjHeRgpqRhTkJ0xwAFnB10ZYVIXTp2XSE
eJnICpJf1UJzNapuQyKznG/zMA0WibAEgP3Ee6/3NjSM27vvUhf4ySLS30HFzu3o3IJQVfEI5dbn
a9C4UsvOKYps2PaLbqtNO9cVrsXHAAzNhsvxg6qYrWDQodXzuK9IYzt2Agup90WVtRgzE8ZWlI8A
PCJ8q7HR1tXoD8M1VteYPLPA1hzMALRqxoBv358hP/H+HCXC//9fAKSyskqMHgLJMylJ+ZjWX8/3
XfUVVUuCGpjmYdzXf1Tastyo/bhSX70UXR+5GHY4JJwFtFgipXdo87iYYXq9gzAXtZ9aG9IWOfmy
XHyhzvLGeSL3jgS0KaNwluvx7vLvjBphRt6hHXD9sDewM+UrQvmKPVoUG93dVBERtdRp/1hK5DED
qobJJ7BjvUyebPNRyLkPL8YXsXlmyEZRmH1RovO66mBMXDAd0LrLMhzZhwSntoB942QHVCbaYMku
OiyFqsGKpqKTrKT1ISWqPUgYgWKBIfzu1fxUmRfLuk4s49h2AHf3o5XmFiugrGTsvPqdJ2S0+HaA
WUssTWUp0Kv+1drxxLETWYb9HwGh0lMUBBxXhd6wrtGUBOiJvc125bj6pSlNH4+xOWFED+ngSeNY
lJ3L1jnwZaEt2hWSWzR7P6LlFNxe0H5Uyo0+wlDDL9SahhtsXQ8v8q0LsrbCTQB/ZQmgLT04P0LB
Dwfpf0kONzyhDaiEnq9ECM8WbbYht9jV6Tf9LY2mi3Ak0GAOjDTMdmhsyvidB824aIxn5LRdpcdZ
UAgXstBtd3cTX/6L4yHTxu/poWbZsyj5xeDFJEiISDfPh1uNjSmAoSZo0hwPuY0vifGcNklYOvmR
kxCkC5GKCf2CE4afDdTKiZp6Cd4jxaZpjfo9HzXF9Xd0QdlVopaX2s2LV6l6IVtqXOm4/KhfQJj/
mLoOXAU4RVZErKu+2w21J3fapwU6uWJWHWk6Dr4NXfbFcTvESJxseXzYTvLXnl8W/Y8yV+nz1vju
2A3Xq57Gc8kwBhIKCS8dvy+7gd17C9KyuNgdfPGU9rcvDhzW80PIbmS9wl7n5PfGN57eDNWfhRH9
FhHSK1PV1GyZTAeeT4AGr6dY8N/wq1qoowl23c3SWTbVaLIvyqNViWs4MDq3Z2dfOWXx2rX7D7WR
S5A1hSH4ZeAPLPPA2D1W7mCtLqM2Opg6/23gEUQgajXmrzkexbvj6a+zj3bvkZJ5SYNvA2zy/QOw
F5ZJcl2LlZjxhTyiZceDmKON6gegjpJJCOFOGZSk/dN4rMuC7HnxCxl5kel+chb4rkvohkKkxkpm
GS4j3cZbU7me0KVjwm5Ba70efKeaG6xTow2jPG3mZc4C+Xb4GQP2OgYJ6p8YCCbcDSz+KM6Nqt2T
w3xKWDOcNIQC4Tfz0wv7EGdag2TCzp8DTry0nUXFbvdzo3nXHrpq997goKPl2kD8VHsb2/B4ybS1
KxgZhHpZi3KuxK+OVzcYhxFbL4RlSBSVCYif5sxg6ClBW8bN51osb6+ZIpgga2hqExgPDRnAN6DL
O4s5h4VLdBmi6sCHPgedjRvxcghvb1+kfwqmGE1xU2ZVJxSYylmYbXj2vTfaGOo3X+qEWcSFEd5M
kYr7iAmLzd1lTCSTOvRZtAFwFPiFVZW76pUz77J/LkxSBPy6jbB7mvEfi5G3NMvzLIyEcRxApM1p
aEOhqnLbVQvCq3/TxQb9RSRa9RJ0AkO4U0JCShOADTTF+jTAj0KvegbRzF7BO3TN+M4Eq5KbtyCq
Mn7h86xJNBFbWeott2ydjmOuU/oiFQwnU3EmgKzCvJbe5HeAQZuJ4pWMrrSW3MBiShohVShQ28Fl
ZxC5IcJj7fwrgnEz387pfPBk6cJ1fP6EFR1zT2LtuZc0jN2WrJiLq5TAkzj9SFQLB7geS+3uJD+G
rAkn4CFfx+wXtqvYLCio3J1MAT9IwCbPZTCBt+SW5K9KlkmfaBqBFuglMAnQ1LpCubqTkU9nOY+8
oyogKRDCY0t2SJRH6QeDKLnffCo5y4QWdn3PG9sb1xROYb4Xm5MIS/QNBXAdKJX1KMy0TXutpqkl
PTz+eqMj0DN8pPaueRJUp4PQc3L56iQS3+MLucI7EX2DyqR0pCsB6LsNDqHZenFzvy+SL/k4MHXZ
/cVfuhWmy69lD98/5b54QFSkJP0temxpeXjxh09qCRJeOB04AG03IElLcElYTQ/CSX3tn08w7XOw
mdoEf1JpRf2/WRn5O7GVACceze3d5wRjMAMyfzZqKBa8T2pRmsMKq2lUFP3Fq/rKOkvj57Z9PKEK
q7G62+6Kv3jkSUaXDsvVZQflwKCUbL8jmnH0/byuif0qOTo1wlRvfn4zTqwr31YWPW+74/zly/YR
47IytcqQA59p63RAshhXliJXb6M/kWSqQ3Bf/INnoio0os4WSpIwQyqA1Q4NlcrXXhNf4+0p+me7
86xyPL3Ip5vL4vkOpe/mV2h3vzrQO/VKx5bvEA8rS1d7NiVdvHkfKWGBka8tfHkhsgBbHgAA1GRC
dLKb4YVJeEm9JaV3enAdq1ouEWRSEEM9cW08JdvbkI3ZCNACQob896x2rujOuTaDL99CYDFYebdb
mBzK9blpj367hcANn6Vt8/yfcGw3LryU05bEKfi2BPEjeFi5n6pTWuu88egRLW1w0xt/2KgDm/2G
C+x1PhHLKNDQoMl+Xodsu9jdEa4uXwniN1XhkgrUXpQZORaMGdv769xKkLMnYtZVjNwJ1GBvhLlY
mSosFO/F1JM9Z9A2/wkAIzuI3a4PJHZhH2X8keJK7V5WzzOATkaXKMlOH45z/4WMoiXVMew80MML
7TT5y6XyU1YjdtqKpgZEipJrpk0EXFHpCuPw/Z+BUwRJD3tnpPDBwXYXViGnd9Yo6EcJNvKssxVq
CNd00cVvYkk9ZpPcGEQcn/HeT6srNR9iTcoYSa06ScY8/Fi94U0RmtCojjCxYNDHiiRadu/8sXi3
8dB8DGlOEQLcjWOl5jlS6DGamCQkNm9y66t2Gg5Rj63GL/ZCWWoow3wYtZ5+8LgvKLC3BEtp1ne5
nGxNUVS6UgzLU2wE7pgh5D1qIZWy6cz+6aZmGndWijKy3RJaDYFEHAVBFS37onk0lUK1M1iHv0sS
q2Vl8iGm0HD2B2EdfQvVvsHMaB6uqMrj7MOr5ggSkiORYKadnnD+iltfv4sBVu4hpAzIkhuSGp9D
HzPP8EWzSEjZ7YFkO1YxrygccABAYHKvgbrys9leJbJdUesvX+PwGbvIrs20w2b4SRMp/wjFJvUw
eixeY5xQsnyYYFA2pFHtbUM111txwlk/92Gg0yAnMSCQiXsNPuF9E0+xfTzwucPVqV8txEluj+03
JEn+R7eZiskPTKwOhUTC25hA1SxRBWOdjM1LY5AWlnGPSrFzWSGi/T14EIVwubLks4JA+4oJOzlL
L3CeRl9Tx1+XeMtuiN9qqmmZqN9Y2NIGKBCO1Kz/WhFDTO6WWzYI6fgYNAVDF9GR6bWmQuaaj3BN
06f+3l/g0U71tsEXqhWEbZz9it9Xwj7gKauh3STYsnK3bCfcOCksrup6XhNMoCjnWFXQIvemSVgX
xU6byo22bn1p/Df6E61upuiceFUe2mvPm/9lsHhYj278bPMSs3RaYLiAxsZYZaS2O5EwvfBjvCil
Vv2XyRDnGOoYSpSOwkrNOHmHINtjz/l9Ywh3UAfEqsVEBs/FJG9VnQBIpaIU9OfKNxThAOKVW3qz
fr0APDwR12cg3m2t9COcdpK33d25NzTZHOJdLijWus860CP1/ch0SzA/7lKGcHDQImGVF7kxlXZ7
wIa7h/GHbAZqqMbKTCH6o2nXjokOzQVtdKK3NAzA2P+UuQkgZICtUdHES1WjRjaVplzZaOoR8X9L
llSart4BmWX45jyO/LsNQcVU6feRmgiQiRSzI2Pp2mkvBU9ep9XV0np2IyWMA2quEQkmnOApvnVr
0RtTIBMgamByHsftmuocNMHEwSzd//TGLtJ/Dr+f27ysZZ1w06KkWIuwPidfFimpL0nwNRTQGqWQ
PrXMOHQgrXKv1YN9Lk5kSXF3OsCG6jygTlgik5TfvZLbjXcioA7aYlBSeXRKayppIJAeqI/WJ8Xj
sP8TerpxyFv8Iw/W5j/Ly5LLpzLnIjX7m6EyWmhXH4z9Pk+pqP1+wTyWpml5dvkB4muEeLnLjAyn
iFRRoPpw9kwxYwRU9WlpX1Ws9XLO1Bjtnjh+3PvFczgVHeFx2d2w8gKUJhYB7Xpo5HZIJcIMBUet
TppVExoMrKpjVtv/D5i6z70ERKlc3iEI7zcsz1Rbdgd/mLhD3B4qdOl3OjINjqbf3BqcGwaPSBt5
OgszIO14e/v18zy2cHbUDXJ0nJ9QyLSK8dMGwD+fQCOzQUAJm6+DA5JKRUzdM3ctnNBUCCdq6pDD
38tubCCYCaWA+fM4wRmbnDUB0xTTx0jQFtWX7wdxYdZBi06TkfYQU4P+tq+cLW6sgWOML/4u7ZdO
nMnWi35AcH0j5tu8on51oPeEZ2psi1cMUs0yhN92Lk0a8zbkS6CYl1hpuel4Bn+lEQJMMGHQKSff
hxfG8wr134dP1Pmb+MZ3LIvfiLVH2nLwsunrHVXx0yNcmvzUwc3S4vvrLN55NHtda7456zxUB1vk
wLBCX1qPfaoW/EVUoKqgJvpHmxZ4AD8iM+sZA/Lz1j7IezJcfKgwN7qLt0xH+BRUcScR6zj3n7JX
C8htwRF7o/aVwP9WiB1TKew1ALun+eSvhKBZwrXZNrdnbiiqxLyV/3Lm/PEMrbes+jDZ4E2O82la
WbyGum6XnDXsOaY610txBG6OB/GdEv7Nh86rM74DJTnrm5JkotkT/1KhMhzLBiW775sb1FScQ4M/
8WDDW/D8VPrAnxdNzbxHuLG00zUGM+F8HeKUAbpDThH8pJenfjetDCrHjyaye+kJj3Hf+Bm4Gq9p
K0TTWJImZiFSyO8QkLN+VJsdCxnjkC+j5RXKUOdrNbNimi01fztuI7z2o57SzBfwxbKqVcSNSyeS
Z+fAgDCZEgv4MJeDNthnrtFweUUKDc0l5pXy1WHdOpE9QWmxqLv8jY7otObLkTYIRDYY3RLwmu0Q
7Wtpghhotp6kvz+NyRQ/MxXZghobodNHXJfTcvbGDZnaDiRxc5RhTu9kU/3wBxJPuxW95WGjEdOS
7v3WiiJOTEPEK91OKcJcSQ9GnTg6dzm+T1xi3zYA7YtuBx70o2P7HifaKPqbFGLAcqiQ/7uFRJyj
IBa3YppzKky8r2gAP6R1LJzLoBx+XGU+fnZcRynH0QSSfz7nXs9CsLFP5VECPmQWtOtcTZGUbheX
P5QHNyAgJE0crMAQnzDAsVt7BczUWTPykvHbsIp8MQHac8xe1JBlgGNteakKuWAcSi+WdfX5xhno
rYwobTMCIemESoSPjgOkbHBF/80VCTz5OlgrMvceAqSxzQufFdurEeL+o8WGWBJuph83OTm5kh83
W/5jWKn+VofFV5uggf/fiFHUuLzE6x/Ul+hnQjuc+xP15Q6PzoMkMuZO55b0yQG7ZfOwh3gDogyR
RYNcC+O9i7kEYR+/r9ewRfYuVFFC3gv5NH4aLNLLaMHBTAbhQGK8BvQz+XfPP6b8UkBZH+QYsFNK
gioKjnsy44WPYfhIZBO+4y3sjAoOO482r33u6WB01ye4i1GmasUkY+1ihFXYzieXwHbmQ+a4YQVn
GgabA3ZvYchghbIzKGUkR26zSEJffMBglfOkb/rf1b9ggF51QI+jAqzHLQC4eOj+3KSNe9zWUzuV
YuFn7zI7J/v1YGdk+xCT1LsewGFQ10rcZdjTpM/sBCTOM92DrcOAVbYQi/d3LvgNaOIVsxEgGPfh
OvQY652thXkGA4QofywxLVLi8kHnNsNjtYh5HLljpu6sJVHA73effqfU8z4hmFBQQj1ngfcej7ld
J1EVC+Ad4D+TpMP7irNmXRkh4Y9wXaEjXkst+qqipWAlUGx9Yp2pMAPuB2KqPXs1FxEUBoPq1QVC
liFUC3hhYue8YiLRY99eAinuipULn5kHpPiFljX6UFd81bZxNUkySJVv10eCMl5ERl9cI2XcSLro
zt85eAjBIxlwZADT6tQ/I7ZWNWz0G9i3WxxJZ5qc0UioN0i+75Q0r4gxYYWkVWkqFSBn8JP0js8y
t4bXbGFhn2YE3tE9AnYT5JpsWRyrqpBpeWDBL3XwvjsP2eBzAqF/I3eol2+b+qH670qLCBv2313K
ACoKka4WyLeqZM/BsNqA9aXTH4sY8/L7TM+7knjoK5aEXv09HNThiBZqjLuQ1I+a9gZKj/BVZGqG
4q3KnbfInjHSW/SAkyDfqpHF1sHVX8EiCa+R8zGcdj7379Lh/rc64A0gi7vbTAijjl/K7Hlj7sZy
I/shEYzIKODxWa5SGGaWjLh0yujkZ6jabtLTvnRIJ50EuKfKgBIX96zWVb+EOKeF55kPklv7Gg9u
66UTuM/rHAPrBxWDMUmiuw1z5g0VG+3O2DeuVjlCCWbR7EAWqR0ukZBlKWobLRsUaFJxSL/AKdz3
N0rWF2p7a4Zbs0ML3Al0cwxF3sFFE2TjALyDxy/uJCaJyoDXSu8pv+QUv+AF3xfIpcCe+w/Trlza
kjD3EdSh0Yf4zJs47mGE4+WmRdPLWJqnBw522vwa9sLddLjio2i3IUdxgP5/ZIkKCM88B7auXO4m
CO9H9+w+0yvT3XxRIzH+36ikdBIC2kPMF4dkMP1IEQPOJZk9Y34hyteSJLA6wkPKs5rUQU0Jmlop
kAdVFLo2PLn/zTy2gu2f45ZTdQomVL+Wrve21a1meO8BSSE2TDHJnqVUw5cK/TOrSB/56CGFbYhX
yfGPF2gkqVX54wNs1LRs+S31lpdM3pxBcr4Dge1gwhsAwJ14Yw1ubI3DutiAZixujaRAHjyQkld+
WAQaSzsYq+CUF/SV7Nf7xuxeANNn/ujJsHtZYa7859i3uQimxpKCLKFgfxB5BJ2H4qh1InFE5TEY
v+fIFT9wFtZVoQ280xOX6Q0/3U+jmQKWEUEftLx+dBmzRul9lZcTO2RlbkZ7LoCPAoeVufZxUiPX
dM+RW9hcS/yrdCz13RLWsYIMTbggn4VJfOH2bUvMIjawolYBSQ/YWTg23lBrW0qDIMZGf71loTRF
zobFh9/bsDc7IYMlg+RmEM/MhufkUxdbH5c5xaFf8b7G5Wd1xo9ZUmiYdjR5SmY5Gu+yMvRpMXhG
cSa4dxzdrWcqCZ8iNN6eWMFqd1xv+upGE3urGWu4oTLNBZi1ZSrqxRtgPGS3djGkWDmqJtNvaGKl
wg7nTFQCNpiQ9irUnltaMggrLN7HsmHpcUL62h6nMUUey3tPrsiDLwdjQaLdBoQr8pvsFMttBo/x
TNsucPZZuV1Qgl7WeWPXw4ri9WNuruTyjjSAA38rfHkd/0Mm0gJxmE9J3wvFPsJhl8aRdLADuvY8
lgx12V/uMH0NVIT+PyBg37rIzfFcRMv08qLxI3UvAIxUmCCjL5Jb8rhNZwCQE1+22UpJ5CR6Jy2W
WPFFgiAdzD4VOF/AeegkSoim4PyAo7PBkzhGWwy51k0OVvQvNO3c9gmVRRDJvU/53LuEjmSznAX8
9leGIvKB2/GYdIDmCPt5Ks6kz/tJuWoWAXgHf3us66wmetTttx1oI9akiwqXk1ETBaCsLExN7Hrq
9Sq+jCYCvsDWsdFmqNwLR1zjN+E3S7fwDmr6KUrRE3pfebe3Yf9yVB1RbolRPvavMCHtn7HL9sA9
7Wvu5/FAjucfRJvp2LQ0P3Ni292xtxzsLHOkBUXZvWe3bpchlKadst8tLVLGpu2brkYMx1MPSr38
NsCyy978d1EjISeHDfQ4NgvXWamP9j9ol6NpKN27BhJ8ql2CROghHqVfgGH8dZjJ/CckQk/DiZJE
9Uqp2dJfFWY98RXm6zkOs75YfJp7xRWRmYVuUZXHDF5eMocX1JhOqettqwl+j7Pzp7tPYohZmkGV
Iw/CplVdgwNBrmNMWl8alxW6lpLItUy0VC+9IoCvC7w31/OjKaVhdHmE2Ejpf0GEcb7zzDmjMihD
tGVlwOTkuxYLfwH2fxqsJlR+jDQYetnc9ldETnXxmuAWIeZ47z5YZmnCa2qF0CWSiNayQhAVyj1B
xVdw1yyK02kIWgP2tEtFLfNzPhdDeHO7EST1Ucr2JSc7ksSJ5MhtuLeCnL3d/Xm6XR7iGYwzpzLe
gT6BmUPuc5xZkc5cLNxXd9pogd989jCPEzrAeTBecOsQnInQvJvJdBbIYqWUSHNp22O1ABb70wmC
CvwmMIl65zeNfjFyaf4HFamy1MJnpJKWmvcg1NxBfA+15f0x+UuvvL7icxY4d38kfztYg36PRhSo
w42AiT7rBwE4OgOTLFZcFT2+LgZ3smS/VC7Djmd8Ek8nIr3T5gs1w+UTgTnAiA2xaEnyQZuOyjmb
ZtSdGKmlFldEFAdIIa1I+pYyAE5mTUynSwBryRlenmtXKSS7sdVylIbosNc5GLumX2NeXsTzBxay
uieByePucCewefxIralg1af7nczjKUHvaARd5HiWzLz7YOjP1wyifTq722Z6gCNped6A/yf/8i2D
zsXdtTRkVRYHx/Q7MYa+zd9JZWGmX6QJc/IfJDKmwkR5Jn87mVWI4RvR11bWYxV3vqn2qljFdt4v
BUQR7Q9og9QHGMcrCvNNgZOdLr9KWq5Zn45Mai36wGQihXLhecVlzdRQxsb64XHizWhPzRCWVz5y
/rRkvQGaauJ8ZxDgj52kyZ+oQjpx1mZFTqvikHTkDHEukks2iLAygYPiMOGpfShFstgb+jEzsr38
ymPA5q8D1BQQMUW/vecFmUwyVmyU4FxoPDSJqTdsuAmdXvbFo0Ry0MXy/IGvYAGyZch5uSeIC1pQ
fEei1YrS6le2HlNL+6mtjsgaf4losOkwcibmNfdr2fR4yXL+wljpkPM9WKFRYj0PoaS4thzbMatR
HDpUJj2NddxEqCdXOJpNEn6RnKIZA4wRd3zflCVynb4BoNqk/krqRwZ8thyKFXjO40IH7xpgjmMh
uWUlffIPylySZzOwJ472Q6D+VlJuuOP6FFFVNO+lvkFklvaSgJbXQ+GZHMRcFD+zvBagtbDyXNpE
XSjDd8rg0rXul/m/Up9RBXRIahyS/7uahfVhMVis0mDDm8amJoSuAdmFcHYiS0F3m4PvbBNXJ9ns
AjuHjLFPYlM4l7Rkk/hT5TpOd/gJFEWw4RzW/qmnDi8HV3atV5Cf+q/DU/SA99EubXiuxrr0Tc+n
aHohc3/KBctlQQbXbnTSKtnahfmlcFWv5Juet8/cMgsR8UJcnia2it5vmTpD5OWdHQFV0g4G/FfC
gdIKaNBTEFDUSoIsc3te5EcX/0Hd3UStDm5AOLj2baBgISJC4rCXWaJDqpclr3+Tm2Kw/F3nedD/
Lq3hDdius2KJigWs7f5Uj8TKz/i14iy0QaJNjCi2bFuXWsvhyVDzgI2W6s420BA3e3dTKGV5ZDt8
jL3P4JwIVbMGd7TW7gdWMzAjDby8L4okQVqc9yI1kwbPEGrTj/RRjoVPcEcuZHqueSb0FZReG5pe
WikvXppl/7Aki9npdJPjwHGCU2Cpi7hn8hzo2lYJh2hP27N72z0Qr5R+/k7bljtSpYCz8e/xM03/
TJlNpRR5mNWNN7QZKoC866KCX65zYP5LxJD+pY6lhZBABOuvwHYibpya6galn8XekEGVt5VxnbzY
tzIlL3tn9utdbclayt/k0Kb0GYGYd/cEzgVO4EIdZ/SwhUl0kCSphOZV3grYQ5zYb0KcByPxBlRE
bZwE+zg1eqCHUWM9n14a+4/oa4+Fo+j1V1zf3VeU+hgI37s63YotXbOry5pBAN+rOIdjBm+ElgD6
cWZhU/OvkNik/Of10CnwMxGHHBusIiX4Xr12fVtI9YKtyZ84fezF1dmXYTqV3zvqzSw8XuoQwG+P
L0KExOO+TG+6Rd2CXSbERbEOLDMM3ZOp390bEg12UBVsflTyQOQelXhqHNkbqZIC4EaH+PkRxPHo
4Jno6ouRgMidykHvoEqZ8mWLACYXUTI65iXWdVf3dTIMe2RgQK9f+n9ce3Ec19/6h+MBJ2xcoObV
N+GtSyEHxFdFjWOMmKllfJkzScAXvKZCy8I3RlNV5zaK68u6/s7G43wFsA/E4DzlypdudSaDrdGf
kn3JtAz+OiuVItxuzOKNZXSBvNbHerFj2ReU/IMYQI9zJwhjNlgtFDtLBUxWE67COYJ54txkYAMj
WDgAX7gWHdEq+b1C58af0QEa1fI5WBaZ/2mt+f8iQbjwZswNdH2zZvd2H81ZkuxoZZ7EKP4dt9wy
hMv5uywwTHqNp1/73OAwk1fROm3Wsza9iEzKnDsJILXvCQfPt9HvthuQShLqPHa3YSA/LWSYlDKM
g32VZwqe0rW5kLHnmH09vmKvw9qgso9/zmYFPhVpVSqr4qK33sTclshzzddeEWXS9T+WLENV17JH
FClj5uYcgWWR0q9iGb6GOy5Ir/+y1FKWGu52x7fEjkd419W9/akKOpBD3qAVaXIkWcJNPaxR5yXE
X0td79GK1A1m9m78/mTpu6cXJO1bjg8btMjmjXvkNTVe5hqbH1q1bARy1AE1f81RkxDQei8C0l2B
DQOo4iPukW3RIT5rVvhEWde8tWnlYg0psJX1NZEJGsdI5NAHhkaNktGre+zOfMuvP2Iu9ttT7cTw
H5vApXryrcPxCa78V8v+odJgSumzNkjDpwYUPBkReZp8KQqoHc0xiuRman7vcFlq6T6EKPKY0gWR
8SzXawoTOXxa7Mi7PH94gf7lgr0mVIMdWKgGQP34He4qVt8e1+5PIpJdrJw7of2UbkUcBr7xrfod
LpnPlDwzxBoTydXAF3rZdOYU439id034RG23fWc2O4brQxj6PnaHegBz8abZFw5HdVDvlrptOanx
3/DXjK1Jnc3z0h648bj5iO45AiVoB1Erj1uKsTthRBdWymNNPe3vpotMN6SOUM1rVbLsVINeQqYF
k+Ouj28ep5OPXFltLOI+MH48l2VBVXAbsrxuPoK2dltCeKcOHEm2UB6F7VOWPh41bTthSrmRn9Nb
glhh5D6CGUCQxAzuEvq34qawBN4Wv6rlCm77APZNJfGcHFDTLXi2EutC/5LrhqYLIpXFBr9uJGWT
Zq0eH51+883Ipmq8lraI2/sn6fniH0S+mWcbyaAgC96LI2by1qlfNrDUcvL5N4qX5Rdtq/WTzd65
UHQov5TO/UeHA0+EGgyQA/6zvCd6sDJyS5oqiLeWpbnpeCFsHZKmrCINKiJwFom/dGsNg4tR7Lnr
f2okPFwFQ1zhMiBL1GqqBf8IJlFMzoKAIlpAmDxNLevIf6AgmRyyxQFaWfF9VSG/aBmrMHufCXBm
8IQqwLCPsad+kLRQ7CIEQjyXoQBwkNZlyJSYmvJvUy4CdwvYk9md7jsHjuo9rjfp4LfLqxMG7C1X
p+2Mh6q7FpNm4yUQxmv7y4JWeXtdROV+BTNMcIAof17t2W8hpFu2hbqIqpS6mWt3VkxOg9cQN0aA
nCiEewsCJMVHsESvLGPd7qRKLuETkHhZAIMtdt/IktQXwKy3bGkp+KMO1iIaZu3i3TunsbsSrnuL
j+WWsEWmH6wO5Zb2WGUZaTmGakglrCALkFSWgIZZbf4guJEQKIt+tLOsWig59ZkxMkMs/DF5DtEN
8z5IpGpVzrq9mYlKG6c27SCJceYVWbF21JVTxQfyygGPQ2QYejBJ0CD2mG6Pb5J5wbEvZ36Ui4fG
0mLbU+fJFB+DD8AryfneTmscZBS80CdrGNqTRg7RV2RfdpwZ8aiAUEiLqEjiyIx5iSVdbuQfUq9P
5Wl/Aw4uoGpgp4Dsxz039+iASa8NbE6ZQALNko9zdBQ/KPbq+Q7i1AfJtwUfihWYJId1EzYSTSHZ
Z2r/Y8xvlSpcwSElybm4XiKj1FodroGtsoxlzWZBE8YZKMC41vhpIVNrDI84HEUJyDKiq2YP9V3B
E3TDasR71+XX0euQUWvetlHpYR9jvFwOUHYXuSADqEgkM/moqndp8vOxZDsKjwj9pT28AzZNdasq
A21/9/e0GiBY/j+zVauNc9baqI2rHlXRYhqka1uW/YNo6KVfco3LpK+ZpMxHucdi/U8SRJ7Ozdup
7yV2aOd/8G1z4V5Vvf+sNNcxkkkHo5v0WXD2wEXp+6diKpnogPKtnM3ABObKhRtk+Dbz4TChTfQR
YsYEZXxZ80fcwVSy43O4StTkVALjxXSS3zc7kCiGpg51ABdTINZ2RyDo+2SmR4r9+VAG062GfjLQ
dFpYXU+cAdTwOfVHKLEsdbVCChyX2od9/Bnx9uh610l7Tb69purDVnlmqUwe1Otv79hfhrLCEKcR
jOqBAbVJCDR3/RLwYJrww+PVL6LhnOtUivR0C2hTEPl4OWATl+e5vrtoCcW4cI7nVW+TYkNMbyzC
ABd32XGJ9CEZpkH2WWlsE63RU6XJeJ74kzzXzsjRpElD+Lu9HixcflQy9jWZ+8bvXsNeyMvy/d/H
wQGUgyDLxRZiabXdNOO72G2HO+tlBVK0ohYaDxkn5Mkco6VGOcI9g9DcYf6m235ptsxTj7me8eca
SFEcK3uhPqEpuH0jsvqUSHsJNVgdAip1qgy+eQwWrU5G+K/MI+4AX7CeHPTWxvPADTuVxdekccSs
tJbnt6jcPr9rCuGHBvxaL1P4c9SPYoQ9z+ICon4AJXbF7L3/XYGSuavBPq9PrmMcB29215BmqTz4
GoJ1eSIljRz2H8lDMr6W9o8eyXJpudtER3jLwiO5mdOo2AVEwJT/liNgs1BGt07l4oue8hhk4ljm
wMI0V49QCX3r2V+c2C6V7i6RNOK4uHi4LdSumoZxaelUAsW/x0U4hOqGedCda2ucq2zlcHNLsNTb
fSYSaH1ntAU7czVNjq5dkxb62hX/UTv8oEr1/UPvGoGcrW+h25mxURNMskeY4GV6oh2yfmMFALqr
hvo82J+9MydF7ZLLdxYf2tGlP5sR6mzxj7Z8b6QAe0a5V9qVBB4WTnb5W9VYnPtkiGJRgGzLk295
Q3OUivkIm0KSkicisUWUXAWU8UHYtYcvac/F1U756dK9ElglEV/76pD/Xd/Mz7l5PEuP1/nNFUq0
BgAhXwDz8FqR67JT6zRdQjeR+Een7+HkxbV/N0P/h7Qyikuxmy47zPxT3h+1YtUJ9GtyWLVZCAym
b8pKAAOvs1x6SbqJr631NZC1LnpVDBkWSBySnNuOnorFDrMDf9X8jWvnualqsEVnvBuoab8SyGbf
dYTPH6q+j9ErDPRNU2wL144yf6vLR1J+6OQEH9E2K/AntY2l+7O46dlJmNm3Hr2zu6kP+u8t1xa3
1LQQ6YZbjKP3FvLKzMpqsQ5qeJvnUMe8EfhZcq9oQ9PjThgvwCDxq0s0F6BGDbkPVC7NXAL55/UC
Hlxp1QEeF0lq4TsF6BwSsokSukGszIiRXbZT8CJNPgkAD2QenC3q3herK7+KorJ9ltD1EmOQ9m6k
ysEyBN1a1WlYnqNNK9NRw3EHAt7Af7WJ9J+JJYcj5JCHco2M4UFzRiIp4NuitK+MiZcPSBUbsykZ
53iO2ZMB+atwRIpzZA6sCtVxuuW3551Rq5VeBNrG9eMEW94DtSzvapfXmc4iRf/dqKs19ZepGaKv
RpJ8mrdDpOCoOio0Lt/isEy8xCoCTyZLui6cm/uqgpkv5Lv5VuMjGQnropYV5iSQ1bwlyv6rNjja
Jn2nFAa3Fb4zqHthAdlLHzhqtLOlELFAeCHq04TwZDobbgkasSPsgj3G79bo8yxG/2fm6rRQtUr+
OrQnzSsej9Dg6LziNYbc9V4H9So3Nx968NY+EI7W4p12kLUcjvYqlAwDtmiiJMzVMVyIgELIzdkk
IhAHPO6ovNQKHH/dMYFRKZ7BJFTyvcbeSBXLIFSZejEP381wlKuDlBCgTuTWzKAFuvWsIRGgOe0O
T9zTJJvK95/GfA72ahpLdIrkRmTvLB4neUQEet4TURTp4TxxvRnZvGlo8yOOVPwdYe3ltnuKddA5
IAqIAWCNj81dB2u1fUIvBsH7PcdWHYUsbEhyhd8mmYS7tGw3c4aN/eLuLz3YVNimJow/MdyA7U4g
mgesaTJ20PZu6fPc+WCk9FouBdn7R4+vbogb1F1IsKRI5W7i8L2iJdXLicudxekl90IlYtKz+Sg+
624mZwrZVxBmYn5EcMtUxB3f2VjK4xUiGDh57UDXIZOYlLrUJ1kfZ091ehnY+4dqM/zfrSNcFrMv
SknpQCB9v80b3ly/NJh5LBNwaCn2Tb2cR0zMTyPCAWdEW5YghOgG6L1ppdH6zUgo6oAfRK2sdY56
m+imkbSbUGLXZlFsFExf9tTM8Vf/0BuFfshNvFCuE+MBFeU0J5rjvUhF85uKCrufJ54evObPVPHK
uwCBozkpOQodRcHWSPDBDq2XeVS/foVK7bfGy1MzcXmp2Y70HR084jrBbvCT2mhlg4bhileiqjPz
qlAQbG05dpCXQtDYAw1GuCBw6iLS9Ju16gnc3RN1SvGLsmxvFdVQj32HcSSIVeIutXF4CgpaGmci
C6wR5iG0HhpLwE2/Pml+/H7vbO7bTWW2bqh18BQpXGVvoh3IYbnuPY7P/9GsAMjDzw7kbc4halio
Nb+dTTKP6tucR1kfzzs/rqKe3HMgEkeDEyUh4Dqqper+b4k06y/ibp2tZv6fCeLkncJlsbVgvNSr
rRYqU/OQ6YHnhFCOIQznTCH30VfBueBEzqNLSQjkUDTHBFNQ5kQXiqbm/2/4tCDnPhZTf7NKQpHL
pvdXsHb6K++I8CWW/nW/Mn3tsPQAZtZ7rV85T6C1ZUSHjvvCRQezhUBUuHkUs/Z87sj/WZet9I2p
6Ya6fN/2qPGy9nHwX44h82nchjlpWDBGnkgUoxnYgWqwLf6gmxOMqFObnv3zP/GwAlJJrM40IrXI
CqQrpASh6MAus8HJ8XRIMeCV8ohS6mZKxHmW89qBMhgr0yoJOYdJFy0z4k8A3n5abbTbON7zS/AS
9WuofXwuladburj6nTdozEn3cMfE6c/bE86lm1DMYjtCgiFVL/L8qENPOaaP/RfCTkBwBfD/vwQ/
EqG2D3oCxWPoWloYl9LSL9qlpRSTFGMWdSNt22rMgdZgC/FQonHYEVyjniVYL7uFXURXE0THotsK
VHWknfYZhcrxJZ0HnjH4fcHU4Acz3Q9hcbLHuTGlvyPqt8lD5tlKXsnYTShGvZaI6AAeGLEkrXdV
Dt5cWjn33aj+uM97e/MZ/9/jZlMeHyLA3eqXr5EOBBqm2UVe2rDIHKcX7UtAXUkbaucgWG8H78wV
v3JEUF58+jWLPrOkiaNuuQVf80qlimybwa6d78M/qIHPUXgWWBGia4I/Xlyg1R0Uwt5XAwSo1rPz
mG6EG1tEPcFyuoUjSweF6nUMHS1sgg4CWtmoIkBBAnxAhP3ugY8iJ68T+IIuDpa2CDjr9tQZpckL
NgxfFiIqafuCtUh6+uuMdXYhPkjio3OQwNuyacEMZp1fbDTjr9HvU4N4WUHTwiBVUoh5c2vLKAmo
lS2EoKBHyLR88ybkkY2a3GP+y9TTcVW0LhMih5630gFbNVHMRZKG5Qq6dGuh3ktrSveu/WN/qKsT
fMbAxeN38w0h+dj4CWZFW6hHo+zTOtpsD8rlawq+JXWCwqVbZl9lYlmzrY/iINmGNmofRLkl1BmE
rndX+hRqxC2PEITtIkIlUJ3NnxaKBxmFZKkoFJdVQ5rKBzSKwzeF2nCvqKLn+aEDF2L7RvK0DWQ6
NvG2F6KsoYCvz66vU8TKcaNBFEyW7OC03ZLQULDbYMBQ6C/Nl8IdszfO+i5JdAJylERzQCd8jkn3
d18kic/htb9SGdkmUd01HuxCkjtp+NcULooUCLBFEpvBMgObHSCbyIG7ABOkNG1yRVW8Mohs8rIn
q6ABtnHStwi5ykapp7ufJ/KSFduldpvMpUgdTUOFGTinvIRU5cQK7x5sPoG4WEsQG4JhaTSExVJZ
9z73yxYGLFVythNUcBlPTbxNTfdN23m/DwiDvmfwuYIVtnMhHLsego9d/LXQUfLvO7n1+FUYSU2Q
iZUnXinfTA3sSw7iRaNpt9b+lDGPNV2XfNdMWOPTKHE1KiFyTQ+gSznPQlsrGeBT6AN+sfQA15Cb
B4J4EuNgSrx1RC9rinqxnA01tL3/IuCWKTcQl7jl+4/5Nz+7ZRy7FSOTkeluu6dOXNCGzllVfgW9
3JopCUbJ5ypwtSSEm00VB25apaH8oJM0nQNd7VuLEQVavilJqLnGdwDoZDTS35s4a9je5tyniqdt
BdJhE1Gy/qMbxeMdC8iN8OBAv5+WastPHc67HuS6MjK77WvTj8tci7+0UUIXWm51tqbxcJds61zL
kWkqCqr9Rg3//IYwNVQfAZPYtAfKP3iRyOemM/M0kVWBE6J6Zs3+OrBBM5tzMQKr4kk8/q3XucXA
8cywHmBY2PPG58szQ3f6xx7IZ/QvCZ2yY3f3eUgP2Df0zWtNKhWksvYINdp8OTKpt79g49U50Vo+
Pzf6MFoSkhCNhzsrmu4a07ShwFuaoo6PtnMZoHwmFSyygUGPCvHgoqrrOHnDx4DdmHfum09yxwIQ
GMlTA4ZrNHK9he6UtIjzRmrYZvxCrHgNKyBG7jnHBAwnQ+0rjZm5MxTl2yBYWWt6aFCbJIWjsfQY
HtyfUlmVG+wZtW6nOqPh2OmYb52m6vQNriOBPG1TcQzPRAMBI6D6Cl77arsVV8seev4Sj7MceHfq
Mr4WH7Rx54EPCuMgIpuUwOYs3YjU/zEF4Tc0mx+wJSxZT9AMuU4OkGWz+6jCPtP3kA4PyeiPTVz9
R1CnE/IgmZiiTgDvfNcYv1ZFHzkvByJc8gFYAzrn19BcYvWEEnytSMv19ShVumPiyIvuGAcd013n
IGPsd2g639or1LZEjMtHvoXHsoOgu1BZAWjOzxe+QPG9hmPW5g3M191wmrN5KqSCq3F6gAt/QvGz
AfCMYzflsZmHRrTOa3AACdXS0KqbvGbdHbLkPJ78aN65NHUDAxIrUoEfi8xMYvUa/8c/FLh8q2vS
XV4Ajxyp10uFpOymtIeD80GOH0bRYbq5Hf4G2LCDK33bwQVflvk0droHUjbCvRDYxnp85uivgX0z
BpixseQ9tyLA4Cx5nWQNjlch2j0ykrsgAwpaexg1oc4wJAQU3MtMUOUFob5Flk7yUHlSnZl+rlDJ
cqLZIgq2ekK8ikHQA8vbSAeH1S+9yVSA+Osh7r/cFS4gnmDd8h4WTm6FCocRnhVtc76AqW8+vdky
99Pbvf6mbWaE5BNUnczVBA/k3zXqJ1DJTcXQ0EHCShTcfmzwog85eUs0Rv93h+9HcmIShc9lchXN
AU+TDdLW32mtqKrzWf+w+hTEQ+ksOj0mPRIkc2vPRpjckbLXM8L+U6Qxtu0MzE28y2PWmiOE2Lu+
X67m+As+bg4ELXML/i0pWdDEb2yJ+ay+MMLtq6Wvk5QaY4PooXjVUmUco+2PIhh5QibdtKWc5jX3
z3/KTVfPNfKSTGYYCEt/3J41c6YIfYGVIxn3ww2zOHDXNpOiMCfgNNoYrXI3ok/hoao1dqfRgXHM
HJFfZuTtthQH8JkrGUJza57ZqXWWUsncqscGLNE6iHeTj5aiuKkohopaAQB0EdHwqFWYCbBwtHiy
TI5CujgqBpGiDBWSQ39GFThQHDeLmLKlRVORFw+Jsp0nAuWQaqtpWJPq5/uYsstDw2iFxtHvlvw5
ZrwDnI6jxyVH+fYbkluYd/oeynsPnywpi38DmRDBr5CZDXJSdZIR9+ES6Ayifjin3JCEYwfxrThq
9t54j6uPb/GYny0MMOjETwHRyfCKecr9llLf4GBFxnNTr9ZX/iJEY6wgDbP0ts8Xe+AP0k5R3EtA
MKiOOVj1wJpncAqXSBCw6R69kkJYxrnnhJUgzDYo/F7HIfAmH1TWLUNjWCwTYD9Ht2KmJ5qwFjVx
DvmHSqsgC1Vr6rM1HTvPxfB4Uim/CsvUX0ki/d83VIfjG1RgUAdDmuuG00NO1dF1s8IOcVhKGaHp
qG5gcJ0bvzj7FSaxoSE1kTzLJI5aKEbT+AGCR8LV94/ppxv8bBCfPm0fh39TMG9q+rGlttaYITmL
33dhOgEFjfuqu0Qxw88arH2/i8PD56dqCZ4hCfSUGwTyJ8vMtaVWgK6lrCyDO60ExVqpyzcogiBW
jVJkoz8TmtBXsnxMVXkjnQ0SZRKzfaUeOZbv1YOTB00gwl45SiVfIDm/mP66jB2SQ6M9hhgdgAmq
8oUCY9VzrRx4ixayL7qNIzqaGm2VdRUp3hF/S+JlzfHPR2h7P+afMVcZk8k7WWglS5M+um+DAdG6
CBfvyNDMY5J57tJRy5Zy9CZd+6+vFfz9N3thZPoUsnBY4MOFicRpJZFVckbdIvlyoOI1xLSmUhRr
rFl+isdShlCdRK3rsz75aM6mMNAoqAqaxCMPArX4t+yypkzCnTETVlUvTDFSZvCglp5ROWuz4iSZ
jIyaIgJZkpcFXHsaFnPuL8JrFxoFk3HfXLzdWZtj5GNQ90xzJ3LBY7knRGgn9IW//ZyiajpM1LQY
qdMG9O+ms1zJM0/+hWF2NGsf8O4hp7TXQX0gHHZpx+RwcGgMiuIlWANLHwhO5eArVLcs7RgFJ/sb
6tFbYB+Ao8E6sEMIUVtOE4zTeto6WHN2fNaD/5DyJMuSE46L12SKbOF0uY61oXi2KCQeWUkt3C6r
pIsxzBmQUEGKRhHsq3G4uFkynfhVHZshtB13rDMK6e2diMaiInlIZQOZ5moiC9Hw0b4kLBjCJr2Y
YPFgJaWbV2qX5W+uVxfMc70ezykbpKxZmCNJCfceo9uiDYzQrTefTBe6Bw8a/Q5M5v5j88HqF3c4
SBOAlHAajcrqAkWMIJxflraceEd8qMY50h3mJlqeQCTiaWh/8qUF/BlRwDy2JKw3QUtl+QpACyf5
vcvITe9cG2BzuvB7fQQR1Hr20ysGqYdJBMT2r1HeiAyXPtfDO7+jg4MDmwfWYT+h14inD5030MDd
TVCXBcRSLzTTtc7OPWJaRCM6DwYuVJ7hItHGPJaPfbbqUSY/lxePJWU6GnFJoLBdCJsP1cX9AVbo
NNrV/pviB/14/R4v6BFqHQoFjks6V1zF3q6wzOwSbQmfNRyvWsW6gYO81dX9/LMRuvOHPj1L+hS/
M7WcErYG0eeCpIPUHr5E9PcU58+P4gxAoXq7OuBg1Sr94wAqGEWriId922N9WECmavQpgG4fCyuZ
w6xiZ9EVyajpwBoze4QH5Rzkee6Yh9brO3Wiq5Jku5IWZDOJurhplP+tilH7X+pFCz+hO1mjwTlM
7T4zxnVKChJYK0ThXvTeLquSk/RRdOpfcCk59BVPZUQd+Vua+YtYhgR3A5b/DdfjTAeu7aIHifd0
BssOSGuwR0pG1VFFPMW1hFVYGhw6Q1lcE5nqlDONyHwCcOIFay9xIn4MZ/TBpIiIm7gwrOah7qJB
N8Ygkbfi144EKKGKStW9FBvca0z1/JRB+yk+NmOUzywf5rGPJI/6Mvm1sxMJWAQO5Vo2jKXRectB
djIMVGauENpQG8zZU5L3Op+WkdScTdohM+AYAYrtNrqiwKn4q17dNC3egbciELomX8j6NdawPPmn
ByDpG+1bfd4wDc2/zC3SN9MqJfHIsBW524a2vfTwBrRISqOVggcxN/fvQJvV0FjPNfFi5F3pcRfZ
5wuAQJF5AwgBVE4OaKW1j2xRJFtm871T+Yt7tXklPC5/F9y59SvbgwNWZS6Xp7cBvCpZA/tC3M83
dpKRLMZDaCrL6y7xkAybi3ot3kDgWADBi6Qolxh5hLSaBC7i1AqfdHFgsr9j3BRXsEe2sGF56tri
DXl8xfGEZx9LlmFYw+4pib748fZSMyNZ0xgzmV1KWcdpF8fpuHH20D3+x4x6Or6S1bH6Bc3RXaBj
cNve5es6G+r3KcVvmAxRhLoBanXbdUIHrt3lzB9UZ37woSjiCmlotVUqB7w5CeXM10KU1NmuxR3n
8wADFUuOzeGwDCj5RDt15+jJ6okMr1YtUUN72nrKwam2gxmKL3FutWk9P5G12eM/IlDckGkXJveX
eWR7evy6Pi/UXvccE6acBtwztw34psdnUKCoKR9fESTUhs/YBGSK8q8QkOzGex8lSSgKb4OlwvXc
9DNwmQsSj7OLDb8nAxRozy0uwKg2TdnWuiIuhqGTxDD4F6rtajjDjlpi0bB82lZ3ql1iCvfhAwBm
jn0TK3kdao9VEaH1VM57t03VVdReB+a+DcFDHPZtgXQQ0yUsOrfsAKrvydnclQsFWp9yr8bFh6q9
HQ4A25vcAwhEBrBUnoeWLmxapiEQRxQ7uazMpcmuacgD6czd0yupwsAX2Orq476SGQJp5NOH9BQM
aHNhWoVOrc2thYL671PhGu5jDSs5AGDwO7Iz2XNREGjf0+n93W3NP+7q5g+q90H6qzUHZr5dQtfi
UL5Jj7O9wmngF6VgwtUQHv284rL5+lMmZPyzbInn+V6JfRPTk6ioDxqbOXBr5uFAHj3xIrHWrCdM
bN7r4pB9EESGwOwmZsoWcxIrfzwXxs5n8Fvch9dxi8kCaBzXia/gL030X1L54Qt4eg2O2LopDsUs
YpY0p1cNiiH3LCBWvT0RTu5JyEmDHxG67DiYuMVj4Zd4NtCyx9b0bxWo1pJL9p0/MvvIaOa+2AqB
w9xy0ikMwEE00gDpLkIwaqJ0/mnhlALatcsSqiR8pdPDTOmLdn2deIqVFFZZQNKRj3Z3CRlnPLO7
auDFJUAT5SKrnjnFbU41D/RZanDjF454NhKxlWJZlmtjmdysPDAI3gv3AFOcEYFbkNkG1/XLjzsb
1IYB9u6JWTMWBDHulszmxzrFADVQC3911rmvKXTwQVksqm1Aa7RHmCC9nxHdHljALFBlD6HUUYbZ
frZzz0Nw3ieKSFcn0YLGMGN1vqDIROzy41a1KwBnbNke7yhIs0A8Fle4GvjB/HAb//70DfNubAQc
PvBK1DEwYvfIlsP+J7rMuIi00Aa5enXXkG2QzH+EKD4Qdx83brR49YBnqAeWLGH1iD8izkM1y+we
7aa7CXsKd6yVb18rRA/kmswhst5zcR8RhRrEscGncQWxPo5x/N/uWqA73O00kSa7aDMw32DrElwy
OHGVBKas8qHnrlrtGdMUR5wqHbjT1BYXrwZn3QU6iHwJshUxdLouP2KfitW9+3UfxytmlbsrmtX2
JYIBW8T3XpSMhBPrCsFGKq/7RLA1sAdctbiFeN3PlFQ3TQbKmY4TifIW0QhoqgaKqgQ8WOLknIDF
Pm7gl8xjQttjB2+r7G280j//F6il3xl37CSiQfBSa3+63rayZNFYE4HhytifZesbP07ahwaOIQMp
o7wJVCsaihCHe/tgLuk2YYG24xMgcdDorD/9dXAuiUFCHCza/TKVpm8+DJBYKlh+fOd1X3uno1ND
RqvTyxH2DHeIX1f6lnLcYH2xf0uzZDUM749aNhLS5ABGk0v3enE9j9eW4lo0RwBsA6KNhmf+RfN0
YVigfKomTC3QrNODopXhqEYPbHIamEFOFwen66gNf9r4lYNJVPl0OKw3tslj+8WN41MCzISouDpq
rOokqjBX5SspuUMLeN1CUjuP+0buor/+BjvwMfwYUsyFT7R+uHt3SdDBAxUl6ww0Nqp0K3hW6mc6
q09Xsd/bOGZA34zdcucECdLo3H7sPc7j8cndAFg1mZAQHEAmxGawOLlEQhmsyDNjh5ubSaWvQ/6h
wQKrD0Nf9GmCL4xTG6mcA3RzXCcTy/kpoiM2ewKHYRt9dEVUdV4PRZMEG5fS/j2R5Gc8iXIfkUxN
mRgv8EQXW5asZuidtbaaBentWRM9XzXFqY30EJqkX/287zcvEhHtwSbzGY/NOhIodPVvH08XXGh7
dVM/aNH8uTDzFq3JXcF9PYuUKi59e1EjcnipfgKswm5hwMnOhoXw6zGeow/LnoNnwUHmsaRnGBb9
PswqJgpwwwf3hYcrv7Of6/bH40pjVrPODiH52JJS/el5JarNNe1eWovJTQqKhOCA7Myk85ITGdCB
zIX7Ubqmc5uIrXBtk2rFv+EsRjHahFhkb89iWKUuJYoOUGzoHwmho2wYsGQ7uW07XcSOQ1/ZUHX0
nyP4LvL0C2CUREyzf5/lSJslqH5S0C33TC/UZREOQCZFC5vyA9POxhDFtXjCXlhZbhu/4hSaYDJB
sDXPl4Ie5vlKlOkBxlt7hGmf/Ew02bh2+YuZgMkuiKYM54apv2zK+BpG30Cy3o/CQeARVoKRCj/F
St6gRVDqFve4MAsBcKr0JiCsXPhFh9459amAcnoFtvWZ58gNo3NI7kD48U1r0i+5I9nwuTckvywZ
7WRtM+GVeeO9I4rLdzxA+S79TLBzOatV4VxZkYmZm1ea4AE2zkw7C01vzWzaPu8ogv5Gj/OzF24j
Cc6B99ZI6H6tDvrFkeSy7tP6vufhgI8zPlHMms+ah3DWbZoE5FrYVt2GnUt3PLNumB26Y+YUDW7i
Dm0CuJyfhgTSiFwmJzZArEcuzas3elmsS1b0iVOmR4n5xl7xN1Dk80OoobYHy+hwbnm1ObdbVe8+
KQteDxMSDt2zbsgTbkAKxSKYocEqM3ZxMOWjUU+E1mTNw698sJFRvJBzJvstfZOxusCerXtsSSRh
zVL8NaVW6+YL5Gong2XrXboCYuMnUHSJHIZ01A5qznqIp3uXnCIdXJALg/A5eZSUyOs/ZalPyDc4
wwd26MTSyofvoLEimjEKMM9HZranD0T8STnKAOkK9CPqvkF1XplucLvErxMqWZkCrT0S11VzLMD0
sg9SwwtgIs8AWakqQOo00DCNcE0SMhZ0CdGzp67l9iST8vbmtUHNG9W/8ThbabZ4y19Cc2VrTNcM
RglkOewj4bfbSBzfLCOqFq02Z/1itoNK5r3BkEPNB6Wv4ajWJ1rlIi/iPZ/NY3blgs6xSv3DEonH
UtImFLbYrQoB99vnbtwOh6BBKDbLVRWG1MMqT6awrvom2tvIhZg/B3Z74Eo+LDcPWJE4BsDYzpB/
W196BZKnCDQebsfljlK03p8CQ2BOOLYCgjBuOhR+eFsC0fdqzHPv71+xt5t7RFHHzy+xdAxOcI6V
cxqitwfjl/sS1VVaWNwKCpFGtKJc4rp8ZYbvy1UrxCWGLZyv50ppcKIycNkTHRUdSUEx7HHmQ38/
m6xrMYtk9RJ8igX52EsSzcs4wuuhhARbHOX+++uBYVMHkLX3bVPe4vHiR6u0JN88l2r+Krc2vjY7
v5yNee+TdpHGDDOHh4aaqMgSvMUGP664gvIoQ9M6WLHqPtEGCShFx52KPfqRu3u//PBk6s2eb/zX
q0vhGGZrMe/JQBPJbqjrRewL3rBhA6/7L9MP5Igt03NvqtlVUTWBeVYe3JiFJv8e6DmTLgmir796
blUMaeVNxF7icBAQv3CNWMrJv3jcUSGkcGaFLNi+9c79Xt73aAvuyioEsrg/QyPi/Ds2pVdjra3+
rwrhlaKNoJcSDh2oAHCDhpuAyIHlPG9ZeNUKuDczPDFZJHxK4MsikNDttXl2jWCRlxWeK2lc+7ic
g0YhNlRa7WanBsmBzIdkoBt17zCa2jNEDHPA8NeyYK6V8XmrTpFyt4oFpLHeA+E9qw4rWRXPualV
ZiXXa4hAdvWl8NHx3DQNILkf53j8xtbQnOCpYsKYO1qkK+2bIk/SjnsqdwkPRUVSCJD5AVGyFelW
AxHsH0wZstBUSpffPGdrCBt/ap1jdjwWlPUVlr2nBhj1kazNUH46tCnIb/uwly73ZJ9Le0xS5jop
TeoZ+5UKcX0/dsBQhtkAfRnpMV6aDebTXVPBUnI8q2126JhQeJP+elNghcgijEyvC90ux70eZIP7
PsglHIS3eWxPp7eAiPxo/iZqNQgF8iLV6lNLwy4Z7dKCEbnjbjSsRaNSBFLUqJ43w68Z3FEFPtOc
CtecsF7rDazRfYIfS0VAekcLBNoC7iiHyNmxUJGdSrfwtndtLpXn37VG6d7Q33tUVCm1h+z2LtxC
cmfOphx9Vfyc1+92E37+/dlwMmDMpzsvMIazwuPt8Lfhpl7qLz/UnpIaa/wgnw2eweRtCmhiYmED
vxRZbhVqFRPRG6K/bapdqR3/OXb3SImF3DQH9B7pfJbtx784qhsLyLnEhjUaaF4QYgnj+Evxnj+a
YNtMTtCzdOvS8M1fnvn/LzvHZ1sgdnTZpaFBZPTQ6aR0fh1gX7D63+4iip8nSun7ZPIQhaMI3qbh
sM8qEQpH2/ohplsS0zu3Or1Y55MQQoEHnF1Cix/oAA1xToildyD+Ue5U6CUxPhITgW90cTlLjvwc
t+zB/Q5UZW+ULjQNAwmt2++QUU8eP9cY1Rg2SzjNEVKVTAT39VsoG1OU3e+wB/fKWYHm/sE2D885
stTmqt+Eji4tjwjStTtWrcfS7cl+PR31wRZ0GkpEWXqzAIdyrtHHS9cGik0RwobquUP47FaZcM9g
l5Spr4GKN3A6f5rPFX2kTbK87P/5SdEn7Psx3QmQ+Ukt/RrA+f3e9X0Ki7c7VqzwuwtX6lQaV8mU
/pUE5/WGKuD3L2XxrfCTa+MVXO57LPVIoDecV/ns7bnlANvr4CRDN3zaTqDV3b3FoQVwu2rIr/Lc
BsdZ6inciCaDc/TfQPACJIGKHdSja+ENsclbTZPdxKUhBk7mZcYt3Nldd5IJeUdKAxV1qLkMJ5S4
8anmRGUnOlFuxQwBg180aibZ0AKtJ3CCbgP1uugoSyK4uWwSc91x0oj1kloaxiPDDAInFNKnRyD1
7S1UzkGfxuanyVUaoY4K7jeTt3fn7Dl1rNDDfr25UKcRAOK1ykvpXVDWA6ZZjOsPR9lS23coSm00
HtuyaTNNMZcR/L/+lFyS9alraZIsO1vhHh/kQl1YjHJUn7bIs5be71oix5uUPyjLWgLki8R5LOlE
u12xDXg0AxEIFVoRfaGJCuFZ8IOoolG6uyIOl6gKEkxVBHHv+w993rNAKllmXEh2R/jpGjSJivAZ
oHBSAshdIjN1i/WdXpt9tipirvMIWXSJO7mF+annBUIOLmVmO2x3LoI2GpHwdCL28nX05M6CA1Nb
tZ7ic05EbyFEc8tb+nQ8spiQtywkEx/tkXJxsFf6o34luN00kDYAcgRdJmBaEhvb1GqF7Aqt5/Zi
2/ImPGa1bGzdL9X1UNuiHD+Y31Z58lsfJ3vWV75Ns+Cwc+b6G2NtEBFd5aRVqoXFcaDsJufh6+OH
VqQOmblvkPHNtUQaaPutgDTerMoFCBISa9MJFgMX0zzq5ZW3fRi+q9tZOSHr9sVioi3HEEfcJktr
Jft6HUMFiIXB9KJCwHY1w6beBzwvYkKv+7bXur6eEQvO/nXjtrNr0DOAt2lovhbkOxSayf4V1MSX
6OoZiMYRT3Aj+vRMLZzNvTCSmVHMOg73nTIMiHNhIXM1svGl9slzy5gn/68C4gOdIUAJnb34Q3kD
jAz6kIlSb/8Y8cKlDG0uJnKW6EEJREDVxyWNhEnxhlRqpf8MMKr6pmYMkal0ytLrJY00P7TEKFhz
MY+VXh2UZfUPNc8nMa5HAojF9n44JZemS2wpCavRkN4Hqg3y5uTU6OGO2lkL8ux0zYRdXMep9Voj
+wTWR2rmoaCdWggXfinW7Ca3dKUH/TNlJCLEITQnCQfDsEWm5GOZjkknEhmfqaSe3LW/UDpOUTMI
L14lWtkEkWQf05BNkwX3a8py0wGUYHhYwU96hb10CPKO0OeHlwL8okJNGKa/Op7YID5gPYSrvKoQ
EF7lGrQ9bec3/ukaZs1yN4IU8623BFFe1U3WDYyTw+PuUJTeMIv4GWT5FM+PKRohoRXwuRo4/uud
3E/iwhqO0jUKeJtEdJb+Ax6/cF44W5cF68Dk1QdKzd/GI3aUNLvJCwRUr03TDSkg1SaANwMIV9da
DM6yXoXaY499V7tz53LmFXCjYjHOvGjbY6N5b8b2bis4etWdsQs3WNGoNB43oukATbLCdI5THB+h
ypJeXWRMBtBnRbDHUBaagQE/DWpUWdPxaRXxM5zGeszWFFu5Wyg5dyZkEPlM1G8x5xNYX2XVp0wn
hw+xt0rVGgkiy2cNVtJgZ2V8k5Jc64rDXjjM83+HpMZEC5dtxw9mGnwCNRemL3dFbPJall1BVPOv
gPRtmCWowkTy2AFjTFApwL9LK7xYiiwbvzncjyRSRpIhwoUtJMFbqsJQR8SprDI2jj1a1w3aeY9t
bEWZhwcmGSVBNEukIu/HqC9MPIVtPK23yj5dMvWfqWxbiihJ06N7yCr4ud34OeYQjQYyxHG26D/N
AgXa8OllQPLesRcU/a1/05Mh+0KxmSj/olZ9VMO6GmOdWZql9NUyq2XMyaaVQuWRwlmFs53zw+8C
VsC+qG+1k1P7KjvkqRw8m/mnnIPI+UiUiWrtyKASZCWN9uHpJMH2G08EcAPST7infVMR2CmTSWC1
GQ8+qpSdU8XOYh15FVCX2xc58exatHMZ64CgKTjMWP5dDGvSEwXWbh/08uKZ+43+pPfBJCb2qkaF
B58DbCRq6GfJnEemxFNaEl70nbpiFaAq1AFBwDL5Rihm/0HJlhxBx+LqOCrNEuxUXUgydGSlZy3w
0EXMoWBS9wrt4mALmDKnTGyNujyvQwVnyAQQ5moXiNoHD+QQ8l6xi+KNwCtyqTtRqaCj9MY5XGVS
bChmt1lr43oqQ8qJaEadSkU1i6C5oE152DRO7zwoiohwv0bZyqQr4X2XOYtu3gTb2IFwipsNeXrN
MZfOVUuIf2if4rVKIspozjFaZ4HURhHfgxs4Q3yqV+ubNplI1OVsE99G76wnx/sJ/xHuBftvZOWN
swnKzLPv16/Xu4C+Hj4ZNJkJM2FAsTkUpGupvC8YtpVYzGuxrEb/6yaGL/l2jOYlPo5DGesEH83m
h+U1Vyqu0RRBRnHvrZYiuJuYNuypRNJtnRHd6R1ftX/YDj5XX2KqtYU8TXMyKAE4o8TNtXqgr5Ik
nBEjX1YSAV/evmqrLjzV5OAbtR+UmWJeTcw1IZTfeiPw/buO+IXmB5kVJGYGUblfIjA1qzclaSrL
mtVETgbyacDs4QqlvgaQO5bumHXBjUWL12o5EygM+hrP6ebyJDo9pxtol5wOU2hCUD3UeRP0ysKa
laBGFiVmiJ4gGOShqGxBM67XirXtAsi/bQkOR6OXlRcN7uPbMOWFjpbBamNlNUU0VbldVGeCg3AD
0pU8NVrVsHAv60Ll0UzwWg5DvjGM4xFsm87oU2YoZrKXbjVWGKeUQKKUxxw7JaRqczUBjGOA7DXN
ZC5CJ9nIRgM9N7ZE/sc1TqBEQ2s2PeuWpTwKvSW59GwkMnPaE4tLMEF/5YTFtKH1R/8QfqoZBtfN
9JIW2yhx3a7xBYSE9omLh9Xi9EqLWBMFCCOPmeeBrE0I3OJwM9TZVIStQ0YqeYNIFL59OOfdSevB
5F+AMOLMoLwdgxJspEp00tzQFomUl4RqiOC/q09CwuDXFXvZL0/jdpSouZHXokKteB2PJA6H5AJc
jL1bjIKy5Evy8xxn3U7moCVr5U1F+t6s0DRGnCi2qr5RjeS1OdmIC6IyjBLkJTamvY71HuqtZ6bH
5hP+Pp+w2lHol54jB6AApU9NpeHuaHTHvdIre+eiicve4RaG0vMt9AICCAO50IRfhUsJh+vsnlIS
D2fPARuha8L5TzwNKRQmJAWeLIMWPTSIaepRC3LfzvzaoffnAWQNtv/9tLaVgCwII4GFMFQsQJK/
+pYem8s2GXaB1qBOfL+/e/EpuANmhLdDbnQGvFhCDEufu4wNCkkR7yiDf9g9EHWJZvXWfPLSaqVU
kpCdAJraVWStYulM/7RnQGAtUZBbYHyyp0Huwfy3ITx54f7lm9+JnyfDxFvC+YuVQ0N/Y/zbJHjJ
zcSd8RLi5EaOqm9G5XLXXDwsQA0lFFSsa7sui2dCvGMPi0VavNFsfZo5W6ogYy/6ezbGiQ1zHBZg
WIfJP7YsVb7B29gs1HqF1OOyl4EDkGO+Y5nmpD8EhTnbMHp1pZWmDTIcYh20IaKDjCYCiJb2MZoM
Vs8z7vl+PeAF6b5lGl65kI2gE/AkvQJ1tX30HqXVtNjy3iSvTgeX4BpPn/DmV9PM/ApmGnAe27IT
H7K//72WVa56/k0CoFRHJHdgqwy0jLF1Vl7UeQtfpJN3WOax5Z0na5XOjtAQe1UsS+t0YXgnqCx0
gt3GfUIQ5a0md2UdGMHUG5Se5pF23RMX+Lm9Jbk7l3OoHt7M6veeytVfCmzc3XBbPtbCBI5+Vszw
mL6kiFPxdg7WJ3ZElC6lbrahXQoV83i7RZftgd3Q/Ae2Fc24qdFvLXjHS/1CnLdfm9UYhi9HQ2kP
ardF0vIAYmRB258nBxgo66OKoANjTn/etAe20DoehCCc2zqHa7KEz7xeE2xU3nexMpL5mMJu3eFm
V7Du3sa34voxJ9vrOMLdbxn4witHsmf5Wg/UbrZyHesuz0QP8aIOUQYwtvpc45x6EdhMK9h7IcjC
8oW/2d/UImKmf6whqTm5M+hbgxpQwxmkSC8SYbck3MmGl3Sef6XNyaNxdoPxeAjOinAkEWsHvIcy
d3iggZBmvwj9gsigezFr6c+58wcuf1yrAIZeoz6KtMGlxy06+2Ayb/4Z7ytIBbv2kc5X7NzdSP20
pvU6IX5xaQDVoxaLXzHVG5LHex9LRJg1nqYqg5EnXIruWQgfNko4EBxq4ZmCAMr3Vip8O1hkjuoC
frW/woVDXM5rVH5BP0tsK3/t9D4r5RP0vDvcTF0xwasDhyOpz07aTS786D3qVN5h1HHeQXBX5NDw
6yVDXiID2B9xTJxdTmoxSPhDBLDDM6aehnbCCyMrLrGfIPtZ2kYPVw6ejM0YT0yrCNQoe1riookj
bKlP0fi+nxl5Vr5xdYwdGkKu/8PrZS/PRyZw18mqAwf7TaWRqBfc4izAOdLc+oS8ZP343huU4R/C
+NXB3lMeJd3Zz+IXL1TqIJdx7cTnIwWPIObgq8+ln2PiJKAsxGY+6Uwtz7hu+GRBHiqWjMwdeWxn
gV3oztoS5tEmIGfBvPreY9YjZaQqtrDuNeZyZhHN7EiJpwKtD1/pwwR2Pf+P+yY5B2ol5GBB764u
2vVSj15Grs3o2kGkKF7+AgNkZI+jESu6mWiSgOdinqF8DIi0I53oDCjrKEpjt9ntue2Vm/pY8Bch
lsJXm5ETTXYYYPA+I29mQk//bahe9mMQYpDOhpMCRv4CvPSUQiA/zKXB5/SabFDXYfL+zI7dwpei
GUAamavZUFw0snqaa6Vo4jMl4dnnv5fKv6uIacuHdndJwUBcMRK2hewgJWphyCdAkGEw5inYnUR9
9r/kCjVvI8o0WPzMX+2fLJnZRmQX7N/uc7sdvJ+Ccex9fRYRwM8xQH6b8a+JjyR7baQz+SY2o6yZ
tUzt2xMyCQhmFFttmzH/nSo8D1Hs8JrgbeFHOcMug/J3FYo7JPZU/cZhlvgVAr1XHQC2EzXn3JD6
9/y5SML+l0C2OcEf7IlfTci9YB9uCkCGo60IEgR6EPiGKiuNZ1o/5s0BcWdCvuvatEKQ+aZdzbCi
BMTO63tCl81yN3QWJhIxLByyxumrm21ifnjDNGo5NFcSRDO2mg8NOn9I2Zsy0Q+vPwTQWNiUsEcX
WDM7vzSW5tAb0yan9r//icEvObbLNskY250aKtU4jFYg5rtBrWjXUSroJj93jIDAXB/TwqBcqRu1
LAADBMDzAxH0/x6DewalVYuZacYBPrGLuN6RAQLz+NsRaB40jnh3i9WnoJgicrZSCqtlvD5Ut8Zm
AIgd8+tewt7+9C2ZJtwlZigAUhZu0DYypAUjrvPCXzU6qErBgXiAV9FXxnwJeEbQuMC6r1rJU8lW
8CIfUX1N/HpiTDVMr3L2P+l38VW9MnyUWWJ0Tqhq0+9lyGbEfAp40FvhrHmRGpdXaNdT7rTLzI28
fZycd6CKQq5FJGnuZgBn9fHxyeUZIJDsytCA2FOnHfLexu0Ri2NJ5oZbisLfZBIDRREY2DWwJyza
AkBTnLQY3+wUdDVi9VuVTZFVs7yLciSNKutKi8th/zkdhQO89obpjfEJzU8NGTIwvvurM3R50Mmm
i7/q2c23cQ/+EO5Bm8XkFQCbdBN0XB5C85cONktYS5N4pr9AuQa7j1mBbhDULcwj1NgWshvAtq0K
AxQqZBAIOAZeIM8yAyaj9ab8eOa1dcWAOLxu1e9icwdMKjPifxXqMqaj4b5937VUl6pRdDbjH2eE
hu6NlT7Mv3EKAvgXvW5jlb2wixOYNpn3vmVJ+XXK0HjsZ19YAsj4v24faYkOJ7kFILQvAcI3PHr4
oqGKBM7pGPXoie7eQ/9/tzNCgNr7LplPmseSZpqPE9a9vo6xYFGF7xmoN6GLxbIG4zvmlRcB31Xp
tuJLhX9ho2wW8olmNLys1sBFTt3qlegYrQEeBllUqaFeN1tlxQAxyrP7cgIvw0OzoHFM2lAkaTL2
h0gxic8iIqFUMPuuY3zBMmnOKpoieGDO9EoONpDJ3D6I4zV1jOun0l40vz+KRa9ToJTNrMtTG+ZU
eEhoaXs9DLdCZ9G6RX0Zh/0pwxyt5J5ZxuaA6Hn8Nq/T7pJwR3n+Pl/bVpnPXypsCDs/0k4uhXKr
DMndxLh7P+7lXpM4M0S3nw4ULO2Cli7mUnAUIW53PiBKV3dMfH7hKEAO9YeLWRIgTUZFj0NjF8hl
wCE+f31AnyuPqlK3XtU9ubeiBmHyhZper0Mba1+nW3QS3b1P1+Kqqvc1lirBwOihtc3GntRzIpYA
KPY4dYjiw4/uartFluJEnDWra/uPxCUFcdv4ShxLRhcJ3Ngm3XwtJeMtaVDcxfbP8+CNDQhFMJmg
iZWxBOj0ZfcvtW3HfTEOJLkX8Oeo+4rQ9bGwEkF6XFiR9v3oWNFUNJB3VXX03yQpyH78w3SMZWQt
Sa1c1gvQegX0zez0lBeoZUh7gUpiAnY4bEVYhcTJQjlG9gNZ/uLoWEMF0vvOdcT9zGUdq9Vn07/W
P9Fo/NELr4LyKYZTuUE/0gWmP4Ms02CIK8cLgaOq9pp1E+/qw0XKsVtun8BMdwLlTAfqlSHDQde+
TBqy5IAwuhadMupH2qu2WsJM8lLZgGNT5euZcg2W3ywr8buQyIh1HwJ5BSx54wec3ruKJQxpxUST
+IVoLHG3YObfHXKHDpcMXvLlZeJCg9/wCoA07/0vfgW/wxzIXwMfXOMS04C7QfOAfuzE31FiWsLt
JvhZT4JAt8pAO259icZ5++NNYRbzuGtMPzyzly7GhpvGYSWpsICMgu4VllernqBiUhXjxnSlybal
yUCzviSsPA6l2Bi/dldmUBH+kXtQo2WFXDelHdBSvIh6n5RvvFnHgxmMipdSw9rPIXXxZGDSGEUh
RtsM00ccVLhlNRCbKaY0ayRzlbQT44TxRJP/7VH18ke203vo1Pt2TO+niztLCrYpQDVGUpmO9M+/
wRLjqqGmQd2enEdP8z4XW2FnDABM4USF5tMA1LaapAK83eKzjdqat++YgQSkFwXfkv+Pz29K2b/q
oNI3DuTJWG8YYizzUwy3qLOX3XTNCyVGJ/61co4n2bo1wTnsmbF2WvA2ExqOWbTfopmLAp2vZSFe
QjPDL7F6NBdCr/44qzp35SGX4eoDPKj93d8TFzTanpKlBlFst1DzYB7RBo67ls1g0pr3IGPiVKzm
eZEUaYvfJ6CqhBWSMqRcNukkqOuqCR2HerK7IrKs75gJaVESkiJDWgkt56yyK/Ci+WRJF2YaOIOb
T9ndL6noyH7ukrcvck8zWssTUCjRYQA1hVhN1LWeiYzfyhGCJ/1NZLSxf8p0u6kxU0YlSYWa2SxJ
WwTLqk6vXIT0R5h2mKpAg0WaSFqbiqoaIPAQhLc2bIG7QYwkYN78f5sR/IFpGtH/qFHQiJ+ltRSI
xZZYAANQa421eFLJz8p3OnW/TsHD/iIUiw1wDDa3QrzJ7nCqf/krB0A3W+DAIRHG71Fci6B0kIN0
z+HSuRaAjnwENwO4jfqTeqIJ6zxZhUbxOlTAIN4K1fHDe155Z3USs5SKQOgDDeBp0eJU6EQZfe7u
kLbHaxYK2bv6macl8GadXpHSSpU/nuZSnfwtF7iG3+kzHzZ+bPzBoZm9rGI2pvt6q7292Vsh4hmZ
G6LFvk+9EwpfJrAbN+h8KuTt3umo8n3H5bMr+/PMXWovsp7f315fZVzNTuBKm1BKBf0hxZAD7wLh
hOuZPBE7DqV2tIwcmzl4tthFxXh1D2hVTx10f+p6uJ7MRg2yxvdDoSqfX3sId6GvJSZIvXJEnZYv
werM2cWp2RZqL6zrnWSqXqn1QptdiT/an1+tNm9Yg3t/jzZVaXuWDbIeysFcwQ9aWU1Mqd5Dx1Sy
QSNGOO7RV2j5rKSiSSbYdoG8lHVcKnynN+8itnoGdYSY3TU92uTo2FDXbENGuLYAKuKbqw5nR2eU
xp5ZfICGXzBhjSal7Veh++RYG4RugmMmJUgxxGx5PIpvFYsL+M1/E8ARQaKGUqsfCVkrqYd2UnZe
l58c8CvQ5MerFINcCbH3dYqR9sPwnnfJFXABEXyPJ88LHxhYNHnCgepfiSRgKixlTpZ+pptOhyLc
8mCKm0jWYp+ZUdMI2UZs7+t0n3E9nLI/XuoDX9LAy1IpPyBGVrPFpxyseXdE2WZsLVGXQF9vRCNy
OFabwdQ2KHZBe49BuAagxKqJoca91MfQmXuYfJE6oq+4sTg8mTyblBh2d4LSUz74mLd3RDOQcKJN
0OwHN+McixAzAkl9OU7KLtIBjRxSleyeSDF4kkzwFdrVDpZJJMep0I1/lnRX2evHDLTfuQq+N59+
T7vr0bklkIhd69WPPdMBh3srthVzoHGnv/JpHAs1rd5wURF7gxIl4jbcEcLO9+GZzp9ZLkup24wS
q35+RR6hvBCIwh4qOhDTgGODN3xZS/+s3LI6BekioF7N/8IwD7Ng9FqdC0WTO2krctsmeO0WQe/w
4kfW+ZM7MEfgOQop2OyNr2l+PO1AltUAFB93eCY4jpUJYKZ0DsH+41C1rmN6j5DktFaNbaOMYUTL
oWoqCUVDwgpx/y+npCru+lYXCUP3xOap0E+EuaqCip4V0s5y9QRefTALfgHocFR0dCamVOcQP7Y5
JRxWPVpZQrvrkiDMrwLGI9IMYgGO++6FdiKsX8wAjpDZXZfl61xyXppHp/N9bqJ5fFnv9uncviOY
iSbINOfK7lj4EqHeePlKEDPoCJKvQQwX4MdAkbl6awcyr6UtagBwovcjtBOmcb+GRxc+ulICbExq
MWcAQG2EFP8smJL6+wUH15vaWD+YC38XrVr/6RghLlHJSUFFBor8HxHR9a3/8gQAN6xsLUpYJVuU
zxRNkeGJWyYyfRpNu4nEpvtXTOf32DjroRbzSjnDAhZiipDm+Kv9JV71u5iuS9IrTUR0Cq2OIjIq
oTxNbp4fujvS15NwQyU1h1KX4hv88KHdxF1x/WaGYbYR0Qzxc1mnzAZRRv48Q0rj/t1QZF19FxSq
8w5KOQUl3xw2nkq5GxLwARi079Opc1JN8pCJ0Xk8v13vziuxsWSHERh1x9Fmp5ec57HBZcGFvNOI
UkM1ZAT3quGMiZcI5XYzzyBvoXfWRMzagsvHP1aNk5ZXBhWfyR1XCIXOXjxnqD+udYwiwG00Xuc/
8Un3trLyAoZftXU4Ww1LAFr1dSxKRHg01WWNlPVznJP+miywCQ7kMeYa2meNKKEtcpZ4ki7Vqxw7
Rm8W59rHTqAZGSrRh/OQVgJ5VPB+mwHQxXO+R4mO+tq5BLYl7m26edcdrBdY+szjklNB9uzlEKzZ
I96ihCaOZ5EjMqbXU2Z5dbovfTwQYkFxtfUBAOt82ep5F/3pgAFMSenplriItoVHIy5qSlo+O5Gf
oh7tbrf8vdudBpika7i5aC/L8WhX1+LNH5zDPB5DnrjfdVvYDauhXciz30w6wQmuJopIjkVc0YHa
mzfbfp+pR2drnsN82t9ieKmk8FsXNxA4niGlevyh/NNWl1d3Te3AEPP3uSFYstGBcxB7CMYjc3fP
+XY5BnpLtiFnjVkvso9QBVB+KQtWrE9+BSckE26ncXWgXVw2ALIFoLOdtl14xRB+88MmDzlcxVJi
eX1rgyavNwzwIsUM+uy+PjBXHPeYx0DyHtgYyPGxCwH0BunZCgSfOeRM7OAYpkXmmCfMATAbexBb
tq86c4ipzorq06X9fLafBGDnB5OGYmezF0Yq6qM2UQt1n0QU/kTWlX1+PBMOGabS9mkLphIguw0B
KkHbF39vXNEG5nh3RN/8e5PGCXPOoEGRTjDrwWFt3NMg7pZPjRhZYAL6KdB2A+oUUmnHJVvTYr0M
PnDE8SjHTdZalV1WBLZ8En9LzDVTxI47IS3FvrtSmZQi1HPTRDPWLwG/fzrHNi9s41gLzvAnBkgg
d/i3blY8dUc2kEmYVwsjcc+WyUL+zSZYTDpjJkvo9Dm+QmbxDg6rtR+Ke+67LlxAeSMZdC1JjIJR
7vQtJg+n344VEshn3a4zxNc+/erX8QcwBfaIFWCjioL1S2qiZM73GsesZFsHJDjFbftWkq9dedDc
jVeOice8dOJuj3UIV3ee1el1/hHxhdKyD8A26m0Pz+DOI46aamgc68rmY3jpgm3oFjWE7cYBp7mR
Twin5Z8qPswY76cJ2cwBxP9OMa+yGamNAnUbBEEfAyXx4tTWSTaF51ATEHHomzLs9beexeoLS6Uh
qgEwvqqPzr4ZBd4dOmcZAOFHJP9ttsomENWV28Z5bmaV4TzHf/O3snapl6wgX6UU/U3QiyWkiIBT
Allu8HHe1XS2jB7DDMADdMdqVtwsK1mOa4JvV7Be/wY+eQpCKfssHykkrMtBJwq76JW0QP84XHHw
prc9capZS/6fLab8TveTB0WyXQTJfrfkuVJP1WvlB2+aBvB2pBggnYs1ExsviuRs/YpBauXiK9hH
4wvDN4kCehFeyre2L+nw60lleFK4MHRp3Gl6QBZvrvknFjSEPQNf0CKXI6F/bqjijnS8Nz9+wBnS
nyndcvLBlFLDOIPZuibU9PYMjVGPqrVl/Yc+08aDWZGoo1UdfaXyAb/+O5UZG/vZgHXkTkn/LXak
f2yYcAprDlpd0tobtVEhggia6c0pQqZnnwwc+nawVEmFKMkDa9n4Z9iSgjtRVMsgq2ICz7QDPZxz
0X6C9s8xyi30DW31Euc/UqOVixEIsg+JpKxK42XYfgQ3TrBJPJyErnZIe7x0zaKpHczJIqs45/w1
qHV2as3EPDARze+c1NG2k43qW6vqsQ4NmeebGquhp48EfQMmtlsh6nAOubSHqbszXUc4YpUOLvVZ
PONyO5ASuzfgUFzHe3lWyMPrlCAJOn7fkJ4YQDnnTutpmOg5wNI5FJbAJGl6PXX6XSfvpmogJAxz
LRA/bv00fhzbxUL8Le0WaiOSdY3kDiB4AlYWyeueSJgFOPDKErgeObhco1nrGapgoQXm06bFx0Fr
UyWmGEXubBrsTb7ZqZVsVVpAXp7UH5bJa4+oZkDvNomp7KiYPWHPgfUeA+BTOZETwddkVM2JcqHH
o/PjT/m89D2K799ToOM/1RyJU4fUR96Vg2DWsRhiP8KZXmRitCarrTug7iiwA6lGe7l9zZCCX768
DdjY1IuxVKt3vAj3qHFOECM35BO4lVkls9TVhfz5W0FzBy/mUVFFtpWkfEV1FlBDGPcFX1YFj94E
B/cUYqx0OV7Fe8NBBPzRcsXkXA1SmKQNNNBCXoMPqjF/8Wv1E1XxbtQAqpUVUnIfACJm71yxPHZp
DctI3D6/QbW9R+S47OfX+SruIi9IM7IwjKB96YufnnE6w0tfyG6HHXAw142gYxs8cuw5g9478mFW
9qfHnZGWZ0CvTxm78FkcmGwEBLYkVbGG4awmA1fTu2H8RUPpyiGt1Yk1mG6Pfi85VNaqhWrfKd1r
66TptnpFtD4bFIKoGJ5SPDFLVeMUsc8z9E8+sopnMn4DrWLgMrP7dfBBFnSuihjQwvK9iy2hFIX+
M+tByNvmWi4g40+S1vQE4CNHekS439GL+VQfJxbGiaZpdhfpHxk5V03PTLt1TmD/LQQwgF7bt1Tq
sFUQhg4wvM8hsgUdmgjVDaQS9qIudMfUOP06ifDXoY5IeaV0nPe0+eXhCLmN9axaEtJE1un2OtPt
X9y0tybuJJL53gHVNkHQZlphhdVpLBmejjF1y52v8XY4UXGht5CG3KZdH7iL2ctp2SVWbyv/SgEb
AOawCIWd0SL2+G2jB6UeZ9pTSKMGi54tLuYPDe2C3EC79VfUy4iDhHv6TCiJk8OcHhODcOYoRZPP
4pN866A/5gglArea1iM9eignGwa0S7LYvHMhRw17/jVAs0WiBQ+67ZRLR53dhJXZo8z+3bJpgHrb
BOBfYA/1kc6GmjuRWP2AiRdnWtWtfOcIu62GiftKbIMcNy3/lxX+zoD+GCX+E0wO/ousDuQoGAeZ
Ax3Te5z/vXn7kg+64ivSlL70i+3Mm/gDDohiBjinZQH1DLJDMjMO2E+VaP19JRyYp6No5+opMoit
5p0DuqV/vWHFGoGMSSsogYHQyVdz8EBnY4c4RwIDgZ8/b82PzVID1Qmu/cwXmjJeJTuJNWenRC/g
ossPBfjPvaNyB/EwK5kHPCk1cxhC//XSsv/5M7C1San5iFBIkePfM7QhSDhyXdFzJG/9LB4huAbM
rb6MNIjFJ4qdl4usbMRJOv+QttDfInuy1vVFCcdZkmW343g/NC2u3LosqYbYFZGR6S1qWQXiokzA
bYYod7SfbqcTX3f7jwfCYTJuq2euZSkKJQEo8MdyM22Bz1uGQQVSDHmkBzS/+WkYA3ZQvlAwp+ve
lna+ujOa0LI0gB27e6CAPZXAU155118ZPchyx/0+qcVxLLYrBZPJhtv4w86wRCCM7irAOXsRUaDf
K+TgdbV6MJfOVbbUE3Diaj/BC5wVIeBKrY3idpNTRbPH9pzdGP5rMK4UYvBStYna41zV+GK6NYfH
8KB5erOFfZeVPBXVTh4cy3PxmzZhV17zPY3ydzFu6u/c/yG7vrieA7sAxmuPkErryJrZBn4iJ3im
bv3c05r9aYhW9t9D9GCNE3LpO/h6JrGraMVuWMvQHlmCynp4BfN5YEHLWdDM1RRdajnnYKUUDzYW
SvAFDwVd5+bo3Ua1cg01hw7bMpERz7mc2cAvUYpLIBrxH69te3xTTxUUecHETOog1u441qRSM7ST
X0TicfZfhpjIQw20LLSMWWvzlyATd+KXuXCBA8BE1foupstSHzcBVjOsZs26CgSid+MmON9BI2MH
j4fAxpuSYkTtG2YtDUtbZsLEeRm2GSMAFsGRMtCB2//35T/eqOZg2WCXkJ8JsOhPb9WdSQWQvuV9
cBinZaWZAAJEo72yJOZC494bmT6989IXInB1hv6tKKLjP6r9h0ePSXbJ8NwRBCNZqW7N+w4x51zn
EJVdIms2OwzqEoASLjrWpuVOh/f2AzQS36W1jWTBpbImUkA7iiUdvWrXVVPdOkXj4uYXI1m/nG6Z
/EkTs+4Mb5joMFW5+xsMsh1FShnA2/8Ec5y72PPwsher/rE1ArRpe95rsasor21bplFipI+jZeyh
ecnEyBOrShdL0K7OMrIIR515eCkD62JADDMEHPuRfBn626czMXiCcvTRfG95oUxkhWehEeK7u2q/
gUrmYck8nLqAFlYMZa7E+fPesLAww13yzUo6d/G7Y4c526szNa7nf/d3XyYhPEegIbK3X1t52NIK
/k0cLVobqp3PMrXWmHDVcDV0Pj6Umdp/IjHUHLfX/62NGqspWBgA8gsMWVkeWvbE7O9PjSCuYFDK
Xr4xiGbQQltQZlXFQJoQc657LG3MyLb450QIBkk1fWYg7e2BoyoN3EBV2HDALVlD5iw5l5N8JF3u
6pN+NKNlzZJurSrMZsWTFWNadVDRY54phgva1JVv1AKxCDpb1G+AA8JBW5exzM638NsKfrgEc7ql
zr1ImWuCPvwrELbxQrdjIKnXIDX0p2gcahmsiOp5T1hPkcD5haLLgKB7neSttcZnyM/Y5qliJ1J1
ZJ4R1Z+jUpZiwKrWCc+loO6BmBaFiTppMHZPT0qbbNbME0t8TIEZObxUMoqBpaJM9zyzmKMfo36R
qhQxpEM9fJ6egtX09GAlI9H+Ns+b6frAxd+cXuT208D7mmFecIQNWG0HQT2z826ekkt56sYw2SkY
BkPPq7d4aPWQkm/q48qMSU+N4ytU1pRaUrQk7VzamkSTGPtYDFnQuAAfVOMV40bWv6fsuas2zqor
HgqB5ZJnRpfSXsysNQmgSHThkcq6li51sciqcg3m7N3pdx9BWG9uiE2aclQi9aJXctEZtATJmpxl
PkRn6xwa536R6vLbEJspiIXA0mNGNEXlTlwwjgzQAp5VP5lXdxpMhY0rMQRLoQgBgDdzLWl799Mc
PvLT/cLz+yYuNZNV+jPzDQZ9cYUZzHNgbScK897t35WzZwVJpER4CGDvpPlIxVwpNFVyh1JVRqMK
g0JXO/eBrnHXNyOT/JBho88u4D+uilC4XWdBB9m9vpmaSyvX/bVIpDbsGuKQdwAyq8J4oSY9tz8s
3Zw8fmXRMjVTq4qjF/VggtYogT9vHuzZ7+T8w2VruX3DL9nDl83GEJ1a7mF7+SwdEsR+rjUEQLsD
iAEiIVyO0CK7PpI+XdMmG4ZTnVl4iwoG44MIsPbuvijELXnWiZH/KPjztWwrGLWh6r8a+e/S1aDL
0vNxUCZwB4DCnkfSaEZNXRvprueM6vLOXt8O7j1KxHzNaif9mwRYn8M+dehfqRhodsP2vpVi7pL/
+/HpYlWrXzuQBp06x1zB9SxKDkAmLO3vLb6Gsyd6yeRKUlF6rQ7fKSJDazjwZylBg2l5/jyI0C4A
NfGWe8r7/PaGkrgqle4vYTWiibjTGoDg7093yD6318wXbv5q17ust240KyLzQIn6bvjMXsdj6e9p
afcTc/PsbF3Ic6uOtYP7Kq25ZR2uJRGOuGpJBCMm4T1/s/C7qdj4LHj/O7z7IvUyLMxc9b0f+xF/
Y2YTOkvyZ510NrMzXIbmV+lS47le2n+ym0+TPlkRC9E6YL9gOoqGnW4paVc01l672hjdDdPr7XbW
sRLVHaCAaCosgZNfuLdyJI4QAvuVFhYwRkaG10wCxUqOH7SUvihrtd4CGN67tk1tn5tih+Syr3C2
C3kWRwU0pTm3hNTJ/TVPkEMQ5YvH7Mfo/+KtiSCAXydlXDU7DDeaIyIHkoEP8e8efF61IDGFUyyB
EpTXXWdIpgqr1kjpGoeBJcfqTa/QxueqnPKkWvTnd2K7I+W6cwHhd4Fs7ztIPCdK00h6HSQz7kWn
t9DuL/MFq+4HfGCktfGJUDQfhY3Ov99QcoBFaERVtkzKi2xmnnCksj5Pj9bW7Og9x1vffQfY9Bc2
7f+gYtmFDiLpsxKkttdyGXTOMa/+Raq6Hr2MnGSwwgjtqxyICKQznZIKLcxQqf3nb9CzlFc4OSTT
SrpMNJb8qbcPjbAA8jNuDpZrRjBmDONyk2tNvCBN2Frlyuj9wSGf5ypJfSHPKYD4TeF5lXGYxgtB
MnNOBVELLreJZEZ1HlIdKDsf4ySzZdawaxAR/z8CuxGmvlLWfpEZnQh0XQiFhBRHXNYfLtnhL23Y
8aQ5fCjLjjmrLsZNnvspGj4qyD6b9ikMvIqG/popqBFcaGu0wLTVVjAR2fBSOG7JO+3oq2nMqx/Q
yQgz9fQuYh3VmoR5mD0pkBqHuG+l+prbgh87Q25Ldzm+0IfRORJDGCJoGWGXdKETuuB1alTdkczg
Wb4T+bvsPhMXhErHhPUwUcmjcjY4QeX+6wNbHa90POHyFmy4F7QgBl+bx9vnjbhpvO5DKzI21DSd
IQ1e+5ko+dFNAy5RlD9kQ8gB7yylj8V4Q9YsBxRb3AjaL37i4V2HPRd/LTK6XFpSLDFtADk4exZB
cR75iHHtpgpOxCWu3gqJkDUCcuhy/tLwtI8HvkeuLi3mGAmKmOs7irmqfGfkLbupKod0kfP0fu3c
1yu4u51IYCf92yD+PnfLuL6O4m8VR2vOLodVUhWCCrDytAjxXGejBNy+qa+bb216nXq9lY2x0YtU
w3a3DkC8G2Q9UxS+R7nGrTCs5bc7yLdjnDxnRfOHorRTp8yvrrZ+GatupKtDiFyn9wbFpFO90eJW
evwl2jvCVkT7jEZPBVzZDNKqC38IXR9e1VDJOfVzjqjXY0slULEFegINbXr/fAHSfZ2nEODXAk1i
u1L1KSXppwy9HzhOFAOVoHi2tdyuq2MYd7D40t0HNYeGydcS6oL8/puePTp8ZhIwNlPX8U4lKubm
x9w3sdOtzvBxr7HlFr7w3Uh5Y8OsMDZla/9KjjDWVWuEtjGyoGiErpuN8S55LgD/ixV1cRB1Bcf+
H8S4jgj4bXLXXcZSuMoPskaCB3nTINHEd27pSZ1GYHqeD37PE6TOQtakf6eOfFR0xZz8X65tQfB+
46+9RNU19JRwxiTnJ6ZJv573/zQh9Lq1fxFggMqpHy7M+d9RQeYQsDDODtjEMqi5DM5ffvTbHvyf
ZJO8Em1dG3hnhXeb1Xu3DrNAJKhlzepKyju84pQ/pjdB5x9+PYFyxeIpIzOBHcM0wAQlxFTdiGal
Wn/JycXw6XITgYHmjK/uJX3/AvJ1wjTwM6lgzYQjFoBWl8/Xih9ox8mz8+7hpvxuMHHm2Qs+Homy
fu3hzmndM90lntQtcYrTvUTRRyfa7mjBhHYyU+05fmOk8eMyQQoMEr/OOCmpsdPQjTFUGnOsHODK
dA6Ucxh0cnDK2+kCU2FvjiIS1PfpjNa29ZI5eeCbwVnXSjAHyawox2mtLyDS/wuSF6eNBgYHYeje
MhZq5+y/4b1W1eHU8kNt19jFSmr3vUTCjDLkv6fS/w7yMnh1ehaeuRg7f+AdNPpN6DXbJ1z0StZn
6K63J7vMOphx0rSZjmE8ssloLRQr5xrdYBoih4vSqCtkiKm7ZJgqer1vx9Zw5ZSqtoYrwBr/b4Lo
jkBGrAKmAWAYBchwvmfERHamw3+7VHNc3pwmuzvaB87xjRwOupom8uQrr9EJSTtoMfFUIaP3lbb8
NHA0Vxcnbr1UiX1oeLbLnVN4xTwi2spp/TgZqAhinpOZtptOxdPZdycIQUiFRAn5aSDEk+yS/IHF
oVF6twx/bZrQi0/7HUOyqn2ddxv0g1nKbVyDqAAewpuUzuTDDmcsL1iPRN2E+vbnqL/aRt82G+d0
or30Bh8ndnyA1peV4D/i01SAG39DVjPNwFMVVzSnZo8aqZQVmP+2du3c3kbCvTAB5vSZZyWlEfTw
G1QebxoWswb8eWromZH4TdtoQMNCEJeLVJWT3wZR6zMh8f/D6VhP9OVbapQPJejONBtMXb9GJPxc
Z6Iw8087573xFdMWDM3xOoKeuQlhKU5D7SNQgcMigUCysi5fGGBgwi+18PBn4CoAhhN1+dXhQAsa
W5cPHML3mzh6WUVcsGiE/w8M2JL9ig8fOQ4rcepv85o2fFcQyYco2D+7Df/0Aw1Fc9N/qkcqIx5Y
zKLkGFW504mayDAyclruU1wlFPiI4/L741yo/w1N+gJ4KK3qDlk7+V1Kv9G6i2fe9eDIjZs3DPfJ
Kwm7hLyRnQhpZYaHefkk/nCTbbmkhq8uhKhEAm1UF1EC+UAdQijqcwY7tfSLGG2AoexM6W0s1Qu6
pLFT3QMqt+X1IWRIdmsl7alPsMy+eF/3DSGu8axiBgymT0JyzFgAevnyMrJA+IX6iaIRon/3gzpN
7AN3OBwvU++N5H98OuDYfAvp4q2Kyz4u0Hhy0F/c11XgXLYW3lYzxLZyIciKj+MXnh87fOvKpdAq
X5VMm6qSW+uqq/fJc0rFWeNCCPhBbb2QSdHRBEimN83cv5eM6C90L19SGAyAitygMQXrnwI6HuIa
2jgt+bUNzEjps1wnwAwhtvIyC0nc7kuQOpxrs4q/OdtBcAQ+ew68p4K0RkqVBjlRduGPfjX6fFJB
UZT7etEr6+mwJxL9rjTt8sxUgvDP4CV7z7Qb/NBZYZUhnquIPt3eabOtx+Fmlz01Cj2VoLuXb3XJ
m+dJQu4f9ncLZShf0gnA3LizfNd9KwuMKbAWQ24kzvwdbDWp5Rtmv2MvSTBfJCpERq7mkhN+d7eV
sA98C8ORDlQkODNyest9Lsd0UoEvP3bU6d4Uy7vTbqAPt6tTbgjKIcDLzB6QwYkQRYsE24sV2Hlm
Tyz+LG4bXc2ssf/xCSd09I9N8Bv3s3C+wy3Oz4eShlx4n1m5VavyocwBzwbhSUN89t2e4GTW5WTV
/+UvTslRCzNSgE1J7dTmd8kGGszND+5Xmgr2YIpA33ffU6QA5G7gLqgOtIJ1xJp3M9F6JV3E8Pr3
1BIhTVC0ZVYq4AR+WSXUYMbM4bCLTTIKaT9xjRql5opiIyZkIAke8YvW/mTnOznBldu8wY3/66iE
vQsePnfYYwpAnhZnRC/o+ozZgy17q79MEVxaifqRxMQdKOsF3YfdNQykHrxRt5PKfDb2d1zS8H+b
XYUTYGRFOmbvzjsdkNfkikVoeMeKzS7a/RMxwd7/4a68NblsncfeFEWLfFiPx4SBLv0Oe8oZZgFf
eUVtFFaA0Au2dOKtklGFoRUsTpO38TRn3yDPT9bk5z4le6Had20Kkqy1U5kXVbAhsbaNT0PDTpCP
0S54vqaNXEzlG3jbGxU+Nk0aXamvL3oNf+8m1Sscwzw9Xmr86Gyv1DK/6taDDB7eqfxAFDXZotQS
b0zdbl1/ELBwW0tExPMmm79hLXuGTQt6Bx4SSYCvK148umhzwByQsPyICc0SVtrzagr4HB+t942p
Ll3dvLJaQ52t0b1iVK9JQC3O54ZP42gcYi+REF4uI2pxvGrQ/R27eWs4L65RA1vqKrr362AV8RbE
D40k6f8Z/dFVrnUB71nezXgxCFpczPhI8dp9qeHbV4sr1+XBtta1HYdERu1U2vmFwToB6kmrwNkq
oLFauXt/VGgvz4ejAUTVdMgeovbrLd2wECI31KUZxzCB84y4KUEk1voITwmeFM98800ovfQ3JkCQ
R7GmJALpfkMU4mHzK/tAZofVNg9wKNScTjMm79xj0TILrJ7h4VK7ukN+Z0egSVif8UcX4BZRqJ1o
Olr6sU0LTe8GD8ccIFhyG+KF2ajoB5bW825fhdSCwdC/7XENGc2PsftUFvCmBK8NIThyMRYYKUuS
gRbvcX6CNUaxxOhRvMt//u0we5b+2X5lx0g1y9FjdRJ7cBuAjDj+AkZaLe7IMP3+MnH14WVAD4eV
BLHDELxhfZEkM9sJ6S9m2ZtwuGMpn4zRgj3UN3JfLP349bxWNCIjnZknSM1QMFeRSwuGXa+oH9Ue
umkjnrR2S4y2Cvtl6O7xqWorv8UKsNfGMw8e2GMcCBk5DiG28wz9sdHFA6UeHEYLy2fiB8aXU1hY
NO24KPK74bE5I+TKCfI9dfPcWOrQI3AiSaqZzwYcEj046tzdkTHKy0HPapZESNWk4C44ahdHSop2
H7zL9niGTVoDEj52vVhw7AKuBRMvrozuqTpe6cuduvpYk9H3UYOfQ42iFKmFTgSStjDcAXghu+RX
av/tJInAIUWwwl1mn3P9BaElnFEP7oykvRbxA9kIsFNnYeO9WyAmakb7zoL2zwUh+5tmEti3dFsu
/N95iwN46h5qPkvr5uLvsh42GvseDNTCI0EYu0+pbrkADzqgyPzjwhPYOE4AVklrZ3lyGO4Obuj6
AZItFbq98o8vJ0MX8LytQt9kSoQWoXh7dNeJ6mcnebYYwmdbsi7CWEZYwSTq5zk9cxnzXo4fjC1v
l+vMkMeI5gUsBzx38kga4GWD+S+e5cgdWDjsp0SXEzEe4YBL/ADK1SZKRVSzGUcwlVTlqEhtUdW0
DW+dC572YjD6bGkLVpBUdKlYH9LlUfNCslkW3Yx7oTnwfqslcGRHHnn2xZCMFzIVI71gN4xgR7GM
vKcf7+Kd6RpJ0s7YJHMHnFT2w1ijwJYcuUi3b6+QRgI5LhqfNscK0b8dWvy1OjPCFNpEfBCKsRzc
JXGrpAPErfI6SQbhl7N3acz2mIhd9wla8G54PltU/HpGdnYocNoscn7qhztVgC4XxAwOMkpOdncI
Cl7WsGxALaIHp2CLIdTufQNMUs4iUZnu66kC4CWZNIxFHSo9JDGcNZBYBECknhZceb7sB1TIObU8
FNIivWsuafBvSu8YhPKSPeOrotiITQXdtGWzrC6rrlza6/RbAuCRiXaxU99acW5ufpByyXat3eP1
fCVbN3aq6LaNwmvrPxuvdMO2e2Xl/R0ssraKLHCA7/4cD+OtBS7YGwtrRIjA7a3XFKm7PyxiQfQS
sYGwh2g6qWLDq6lZBqqARjwLMU+yO2XjWXMyqHFR3HJHMCFeV+b4etS2JBIVLn216ONlWnA717Hz
/6byWt1TB0s7pm+sy6hNJyh3yCRM/nRVlf0Q42G8qvxP74DCIQR3cAIYQ8V4HZKUJWrggA6LaGU+
zPz8jxI77nRqk3zo9bnauQIPeAVwHmopsnEyVnUAO8pK+yjSkwv5D4OAG6bOtBmx1qNWtBfpUR+r
ZUXt9O6Pu2U05U+ohZdQ/p9kKnWk6a+5fVrBDCfBAhDqG7Z5ftkHKl75x6L2I5ZRyuswsjW5peo+
5Xs+mz9Ftk3nZb0YPbTwSnh0w/bxJmKbCZuAbTvG0gfaZ2G5cf9XxfTpPPN2WeniWyR0b1zRMOc8
89tVckrLZUNH89qxFK3VDucWwjMKE84Lxy8YXUn+tpFvNVDoM+jhHXZmYsetKOv3v9FF1W/tyh2v
ofnr/n+fJ9gObQh9yiVqxu57aYo1MfkD8x1/ZTs0uXzaSiuc7vq7lcBt8xsbYGA9FcCJCjklm+o8
pATLIDJawyWkSQBWx4VtuUyJcoo6idilU69+14qREege1w0zTOhw2p+wCmNTpA8ujsq9Fp9QIGEl
044N5PCawtpZWl657rEJ6lTz2xGXxTsbRg1rRhp8T53BpaeJL1QCH/B1mdY2zDByFGxL3+8lyp4J
6chJh9V+RnAKCLU0Aph09lwO2rhIKrz8m1MupX9gHyE00Bpix1Ph0ZyroiZOymuJRN9aP+a8gJy7
JqCQph8wxCMOCOI6kJ0PCC54J3MtJ4wrV15rQoT7RnsMyiLX6QHvSZeddqx+7z/a0MFmpz+FSLXO
fA2AehwFW7izBV+ijhMqYKJoi6ajg+o050E6wluW3ZdNHzqqLvftNDFDcZLVB08/BMRo7EDD9OeF
81lB71qbFN6tKCglGThCHPqBRaxIkAng0hmNr8q7WvkhpEm56RUM8XH9xjyjCgCwNpj6AywjehlK
I95FMVBgE8TSeH7PKWI9jXbs1+v6I/X/g2eMIBa7BD0ta811ASmpV6Pkgd2Axqb0T3bX1Khf4xKf
35qS8xgIG471RX54J/u1BfP3k9cvpjReki2ldol6rC+jLoNxT3A3MgSaygs1wPrFRZbG2Ayp2UM0
x6SMW8Gev9b1jPFd/+WntfagQ/Z/5WLG7py3PaaEwEjIUr8Fa4KRqasq4JvNY2FZUPFYXFmz4npO
Dsnjiv4Rks1aZeUEbGeDPTPY7j1wzluWVU2kMScc3HdBym1AAP3n7qez8SJa6/AppJEjsRNrrtq7
6YA/sGeJeFIm2k9O8Glol2b2xQDJFCT99Jf5kkE/albadDV6xgiMgo+ubCr9qQ82yr9dO94y8n8Q
Bm6hoWSngJiZUuL5hRvol5JT80XGdf+knT/N++gavR4a4SAqfvbxKvUw8QiYYvERzHINo38nm+hq
BBxr8daoQYukNu8YsbsDsPJt7/DxSO/tVXubDC7cHd1SPzubfNb+HVoKOsoo7gPzWi287k7FcKqt
LqofI4Bku7FKNA7SeTduhi9kc1SuIKnasCesLpcT//GgdFxgjspc+mQgIAtdDt4JF3TzRtWbbjL1
LXjpv5A9emDdBOyAJLOW0tZTn3qUA+OWk+e5E3rwccJoLLm6P4tV92RdAE1N6g+GZdcWypcBrktb
CH3CrcebfnH7yo82P1Q690bG79jD48SdrhqmaChrbUo8dlOu/PUZnF8oNa54f3jh/EpRkmWyyjdC
wm15YjUsHEHPyGfh+NJZcKbvpEkp6zTsK34hzDNfHbZrYzza1AU5sSC4YgyLpi5nRpjSU7Rj7kK4
BUEV
`protect end_protected
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_sg_v4_1/hdl/src/vhdl/axi_sg_scc.vhd | 13 | 42217 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
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-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc;
architecture implementation of axi_sg_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_cmd2addr_valid1 : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= "0000"; --sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= "0000"; --sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
RD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00001100" when sig_cmd_tag_reg (0) = '1'
else "00000111"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate RD_EXTRA_FIELDS;
NORD_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000111";
end generate NORD_EXTRA_FIELDS;
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
sig_cmd2addr_valid1 <= '1';
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
--
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
--
elsif (sig_btt_is_zero_reg = '1') then
--
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= '1' ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
--
end if;
end if;
end process SCC_SM_REG;
end implementation;
| gpl-3.0 |
nickg/nvc | test/sem/afunc.vhd | 1 | 1339 | entity afunc is
end entity;
architecture test of afunc is
function get return bit_vector is
begin
return X"10";
end function;
function get2(x : integer := 0) return bit_vector is
begin
return "01";
end function;
begin
process is
begin
assert get(0) = '0'; -- OK
assert '0' = get(0); -- OK
assert get2(0) = "01"; -- OK
assert "01" = get2(0); -- OK
assert get2(0) = '0'; -- OK
assert '0' = get2(0); -- OK
wait;
end process;
-- Reduced from VESTS case tc1072.vhd
b1: block is
TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
SUBTYPE A6 IS A (1 TO 6);
SUBTYPE A8 IS A (1 TO 8);
FUNCTION func1 (a,b : INTEGER := 3) RETURN A6 IS
BEGIN
IF (a=3) AND (b=3) THEN
RETURN (1,2,3,4,5,6);
ELSE
IF (a=3) THEN
RETURN (11,22,33,44,55,66);
ELSE
RETURN (111,222,333,444,555,666);
END IF;
END IF;
END;
begin
TESTING: PROCESS
VARIABLE q : A8;
BEGIN
q(1) := func1(3)(1); -- OK
end process;
end block;
end architecture;
| gpl-3.0 |
nickg/nvc | test/regress/vecorder2.vhd | 1 | 1506 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity vecorder2 is
end vecorder2;
architecture rtl of vecorder2 is
signal c_a : std_logic_vector(11 downto 0) := x"FAE";
signal c_b : std_logic_vector(11 downto 0) := x"182";
signal s_expected_vector : std_logic_vector(31 downto 0);
signal s_resulting_vector : std_logic_vector(31 downto 0);
begin
-- Compute expected value using intermediate variables for padding
expected_value : process
variable v_a_padded : std_logic_vector(15 downto 0);
variable v_b_padded : std_logic_vector(15 downto 0);
begin
v_a_padded := (15 downto 12 => c_a(11), 11 downto 0 => c_a);
v_b_padded := (15 downto 12 => c_b(11), 11 downto 0 => c_b);
s_expected_vector <= v_a_padded & v_b_padded;
wait for 1 ns;
report "Expected result " & to_hstring(s_expected_vector) severity note;
wait;
end process;
-- Perform the concatenation and the padding in 1 line
resulting_value : process
begin
s_resulting_vector <=
(15 downto 12 => c_a(11), 11 downto 0 => c_a) &
(15 downto 12 => c_b(11), 11 downto 0 => c_b);
wait for 2 ns;
report "Actual result " & to_hstring(s_resulting_vector) severity note;
wait;
end process;
checker : process
begin
wait for 3 ns;
assert s_resulting_vector = s_expected_vector severity failure;
wait;
end process;
end rtl;
| gpl-3.0 |
nickg/nvc | test/regress/vests6.vhd | 1 | 2341 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc167.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests6 IS
END vests6;
ARCHITECTURE c04s03b03x00p01n01i00167arch OF vests6 IS
BEGIN
TESTING: PROCESS
constant C1 : INTEGER := 1;
alias a1 : INTEGER is C1;
constant C2 : STRING := "Hello";
alias a2 : STRING(4 downto 1) is C2(1 to 4);
alias a3 : STRING(1 to 5) is C2;
alias a4 : CHARACTER is C2(2);
BEGIN
assert C1 = 1;
assert A1 = 1;
assert C2 = "Hello";
assert A2 = "Hell";
assert A3 = "Hello";
assert A4 = 'e';
assert NOT( C1 = 1 and
A1 = 1 and
C2 = "Hello" and
A2 = "Hell" and
A3 = "Hello" and
A4 = 'e' )
report "***PASSED TEST: c04s03b03x00p01n01i00167"
severity NOTE;
assert ( C1 = 1 and
A1 = 1 and
C2 = "Hello" and
A2 = "Hell" and
A3 = "Hello" and
A4 = 'e' )
report "***FAILED TEST: c04s03b03x00p01n01i00167 - Alias for constant object test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x00p01n01i00167arch;
| gpl-3.0 |
nickg/nvc | test/simp/issue331.vhd | 1 | 2148 | -- issue331.vhd
entity ISSUE331 is
generic (
INFO_BITS : integer := 1;
INFO_1_VAL : integer := 0
);
port (
I_INFO_0 : in bit_vector(INFO_BITS-1 downto 0);
I_INFO_1 : in bit_vector(INFO_BITS-1 downto 0);
O_INFO_0 : out bit_vector(INFO_BITS-1 downto 0);
O_INFO_1 : out bit_vector(INFO_BITS-1 downto 0)
);
end ISSUE331;
architecture MODEL of ISSUE331 is
type INFO_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
end record;
type VEC_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
INFO_0 : INFO_RANGE_TYPE;
INFO_1 : INFO_RANGE_TYPE;
end record;
function SET_VEC_RANGE return VEC_RANGE_TYPE is
variable d_pos : integer;
variable v : VEC_RANGE_TYPE;
procedure SET_INFO_RANGE(INFO_RANGE: inout INFO_RANGE_TYPE; BITS: in integer) is
begin
INFO_RANGE.DATA_LO := d_pos;
INFO_RANGE.DATA_HI := d_pos + BITS-1;
d_pos := d_pos + BITS;
end procedure;
begin
d_pos := 0;
v.DATA_LO := d_pos;
SET_INFO_RANGE(v.INFO_0, INFO_BITS);
if (INFO_1_VAL /= 0) then
SET_INFO_RANGE(v.INFO_1, INFO_BITS);
end if;
v.DATA_HI := d_pos - 1;
if (INFO_1_VAL = 0) then
SET_INFO_RANGE(v.INFO_1, INFO_BITS);
end if;
return v;
end function;
constant VEC_RANGE : VEC_RANGE_TYPE := SET_VEC_RANGE;
signal i_data : bit_vector(VEC_RANGE.DATA_HI downto VEC_RANGE.DATA_LO);
begin
i_data(VEC_RANGE.INFO_0.DATA_HI downto VEC_RANGE.INFO_0.DATA_LO) <= I_INFO_0;
O_INFO_0 <= i_data(VEC_RANGE.INFO_0.DATA_HI downto VEC_RANGE.INFO_0.DATA_LO);
INFO_1: if (INFO_1_VAL /= 0) generate
i_data(VEC_RANGE.INFO_1.DATA_HI downto VEC_RANGE.INFO_1.DATA_LO) <= I_INFO_1;
O_INFO_1 <= i_data(VEC_RANGE.INFO_1.DATA_HI downto VEC_RANGE.INFO_1.DATA_LO);
end generate;
end MODEL;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_axi_dma_0_0/synth/design_1_axi_dma_0_0.vhd | 1 | 26131 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
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-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_9;
USE axi_dma_v7_1_9.axi_dma;
ENTITY design_1_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_dma_0_0;
ARCHITECTURE design_1_axi_dma_0_0_arch OF design_1_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_dma_0_0_arch : ARCHITECTURE IS "design_1_axi_dma_0_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "design_1_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=23,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_A" &
"XIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=8,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=8,C_INCLUDE_S2MM_DRE=1,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 23,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 8,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 8,
C_INCLUDE_S2MM_DRE => 1,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_1_axi_dma_0_0_arch;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_timer_v2_0/hdl/src/vhdl/tc_core.vhd | 3 | 18217 | -------------------------------------------------------------------------------
-- TC_Core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_core.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Dual Timer/Counter for PLB bus
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- --tc_core.vhd
-- --mux_onehot_f.vhd
-- --family_support.vhd
-- --timer_control.vhd
-- --count_module.vhd
-- --counter_f.vhd
-- --family_support.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_FAMILY -- Default family
-- C_AWIDTH -- PLB address bus width
-- C_DWIDTH -- PLB data bus width
-- C_COUNT_WIDTH -- Width in the bits of the counter
-- C_ONE_TIMER_ONLY -- Number of the Timer
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- PLB Clock
-- Rst -- PLB Reset
-- Bus2ip_addr -- bus to ip address bus
-- Bus2ip_be -- byte enables
-- Bus2ip_data -- bus to ip data bus
--
-- TC_DBus -- ip to bus data bus
-- bus2ip_rdce -- read select
-- bus2ip_wrce -- write select
-- ip2bus_rdack -- read acknowledge
-- ip2bus_wrack -- write acknowledge
-- TC_errAck -- error acknowledge
-------------------------------------------------------------------------------
-- Timer/Counter signals
-------------------------------------------------------------------------------
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- PWM0 -- Pulse Width Modulation Ouput 0
-- Interrupt -- Interrupt
-- Freeze -- Freeze count value
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_timer_v2_0_10;
use axi_timer_v2_0_10.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0_10.TC_Types.PWMA0_POS;
use axi_timer_v2_0_10.TC_Types.PWMB0_POS;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_3.ipif_pkg.INTEGER_ARRAY_TYPE;
library unisim;
use unisim.vcomponents.FDRS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity tc_core is
generic (
C_FAMILY : string := "virtex5";
C_COUNT_WIDTH : integer := 32;
C_ONE_TIMER_ONLY : integer := 0;
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 5;
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Rst : in std_logic;
-- PLB signals
Bus2ip_addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2ip_be : in std_logic_vector(0 to 3);
Bus2ip_data : in std_logic_vector(0 to 31);
TC_DBus : out std_logic_vector(0 to 31);
bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
TC_errAck : out std_logic;
-- PTC signals
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic
);
end entity tc_core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of tc_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Attribute declaration
attribute syn_keep : boolean;
--Signal declaration
signal load_Counter_Reg : std_logic_vector(0 to 1);
signal load_Load_Reg : std_logic_vector(0 to 1);
signal write_Load_Reg : std_logic_vector(0 to 1);
signal captGen_Mux_Sel : std_logic_vector(0 to 1);
signal loadReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal counterReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal tCSR0_Reg : QUADLET_TYPE;
signal tCSR1_Reg : QUADLET_TYPE;
signal counter_TC : std_logic_vector(0 to 1);
signal counter_En : std_logic_vector(0 to 1);
signal count_Down : std_logic_vector(0 to 1);
attribute syn_keep of count_Down : signal is true;
signal iPWM0 : std_logic;
signal iGenerateOut0 : std_logic;
signal iGenerateOut1 : std_logic;
signal pwm_Reset : std_logic;
signal Read_Reg_In : QUADLET_TYPE;
signal read_Mux_In : std_logic_vector(0 to 6*32-1);
signal read_Mux_S : std_logic_vector(0 to 5);
begin -- architecture imp
-----------------------------------------------------------------------------
-- Generating the acknowledgement/error signals
-----------------------------------------------------------------------------
ip2bus_rdack <= (Bus2ip_rdce(0) or Bus2ip_rdce(1) or Bus2ip_rdce(2) or
Bus2ip_rdce(4) or Bus2ip_rdce(5) or
Bus2ip_rdce(6) or Bus2ip_rdce(7));
ip2bus_wrack <= (Bus2ip_wrce(0) or Bus2ip_wrce(1) or Bus2ip_wrce(2) or
Bus2ip_wrce(4) or Bus2ip_wrce(5) or
Bus2ip_wrce(6) or Bus2ip_wrce(7));
--TCR0 AND TCR1 is read only register, hence writing to these register
--will not generate error ack.
--Modify TC_errAck <= (Bus2ip_wrce(2)or Bus2ip_wrce(6)) on 11/11/08 to;
TC_errAck <= '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--Process :READ_MUX_INPUT
-----------------------------------------------------------------------------
READ_MUX_INPUT: process (TCSR0_Reg,TCSR1_Reg,LoadReg_DBus,CounterReg_DBus) is
begin
read_Mux_In(0 to 19) <= (others => '0');
read_Mux_In(20 to 31) <= TCSR0_Reg(20 to 31);
read_Mux_In(32 to 52) <= (others => '0');
read_Mux_In(53 to 63) <= TCSR1_Reg(21 to 31);
if C_COUNT_WIDTH < C_DWIDTH then
for i in 1 to C_DWIDTH-C_COUNT_WIDTH loop
read_Mux_In(63 +i) <= '0';
read_Mux_In(95 +i) <= '0';
read_Mux_In(127+i) <= '0';
read_Mux_In(159+i) <= '0';
end loop;
end if;
read_Mux_In(64 +C_DWIDTH-C_COUNT_WIDTH to 95) <=
LoadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(96 +C_DWIDTH-C_COUNT_WIDTH to 127) <=
LoadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
read_Mux_In(128+C_DWIDTH-C_COUNT_WIDTH to 159) <=
CounterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(160+C_DWIDTH-C_COUNT_WIDTH to 191) <=
CounterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
end process READ_MUX_INPUT;
---------------------------------------------------------
-- Create read mux select input
-- Bus2ip_rdce(0) -->TCSR0 REG READ ENABLE
-- Bus2ip_rdce(4) -->TCSR1 REG READ ENABLE
-- Bus2ip_rdce(1) -->TLR0 REG READ ENABLE
-- Bus2ip_rdce(5) -->TLR1 REG READ ENABLE
-- Bus2ip_rdce(2) -->TCR0 REG READ ENABLE
-- Bus2ip_rdce(6) -->TCR1 REG READ ENABLE
---------------------------------------------------------
read_Mux_S <= Bus2ip_rdce(0) & Bus2ip_rdce(4)& Bus2ip_rdce(1)
& Bus2ip_rdce(5) & Bus2ip_rdce(2) & Bus2ip_rdce(6);
-- mux_onehot_f
READ_MUX_I: entity axi_timer_v2_0_10.mux_onehot_f
generic map(
C_DW => 32,
C_NB => 6,
C_FAMILY => C_FAMILY)
port map(
D => read_Mux_In, --[in]
S => read_Mux_S, --[in]
Y => Read_Reg_In --[out]
);
--slave to bus data bus assignment
TC_DBus <= Read_Reg_In ;
------------------------------------------------------------------
------------------------------------------------------------------
-- COUNTER MODULE
------------------------------------------------------------------
COUNTER_0_I: entity axi_timer_v2_0_10.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(0), --[in]
Load_Load_Reg => load_Load_Reg(0), --[in]
Write_Load_Reg => write_Load_Reg(0), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(0), --[in]
Counter_En => counter_En(0), --[in]
Count_Down => count_Down(0), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
Counter_TC => counter_TC(0) --[out]
);
----------------------------------------------------------------------
--GEN_SECOND_TIMER:SECOND COUNTER MODULE IS ADDED TO DESIGN
--WHEN C_ONE_TIMER_ONLY /= 1
----------------------------------------------------------------------
GEN_SECOND_TIMER: if C_ONE_TIMER_ONLY /= 1 generate
COUNTER_1_I: entity axi_timer_v2_0_10.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(1), --[in]
Load_Load_Reg => load_Load_Reg(1), --[in]
Write_Load_Reg => write_Load_Reg(1), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(1), --[in]
Counter_En => counter_En(1), --[in]
Count_Down => count_Down(1), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
Counter_TC => counter_TC(1) --[out]
);
end generate GEN_SECOND_TIMER;
----------------------------------------------------------------------
--GEN_NO_SECOND_TIMER: GENERATE WHEN C_ONE_TIMER_ONLY = 1
----------------------------------------------------------------------
GEN_NO_SECOND_TIMER: if C_ONE_TIMER_ONLY = 1 generate
loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counter_TC(1) <= '0';
end generate GEN_NO_SECOND_TIMER;
----------------------------------------------------------------------
--TIMER_CONTROL_I: TIMER_CONTROL MODULE
----------------------------------------------------------------------
TIMER_CONTROL_I: entity axi_timer_v2_0_10.timer_control
generic map (
C_TRIG0_ASSERT => C_TRIG0_ASSERT,
C_TRIG1_ASSERT => C_TRIG1_ASSERT,
C_GEN0_ASSERT => C_GEN0_ASSERT,
C_GEN1_ASSERT => C_GEN1_ASSERT,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map (
Clk => Clk, -- [in]
Reset => Rst, -- [in]
CaptureTrig0 => CaptureTrig0, -- [in]
CaptureTrig1 => CaptureTrig1, -- [in]
GenerateOut0 => iGenerateOut0, -- [out]
GenerateOut1 => iGenerateOut1, -- [out]
Interrupt => Interrupt, -- [out]
Counter_TC => counter_TC, -- [in]
Bus2ip_data => Bus2ip_data, -- [in]
BE => Bus2ip_be, -- [in]
Load_Counter_Reg => load_Counter_Reg, -- [out]
Load_Load_Reg => load_Load_Reg, -- [out]
Write_Load_Reg => write_Load_Reg, -- [out]
CaptGen_Mux_Sel => captGen_Mux_Sel, -- [out]
Counter_En => counter_En, -- [out]
Count_Down => count_Down, -- [out]
Bus2ip_rdce => Bus2ip_rdce, -- [in]
Bus2ip_wrce => Bus2ip_wrce, -- [in]
Freeze => Freeze, -- [in]
TCSR0_Reg => tCSR0_Reg(20 to 31), -- [out]
TCSR1_Reg => tCSR1_Reg(21 to 31) -- [out]
);
tCSR0_Reg (0 to 19) <= (others => '0');
tCSR1_Reg (0 to 20) <= (others => '0');
pwm_Reset <= iGenerateOut1 or
(not tCSR0_Reg(PWMA0_POS) and not tCSR1_Reg(PWMB0_POS));
PWM_FF_I: component FDRS
port map (
Q => iPWM0, -- [out]
C => Clk, -- [in]
D => iPWM0, -- [in]
R => pwm_Reset, -- [in]
S => iGenerateOut0 -- [in]
);
PWM0 <= iPWM0;
GenerateOut0 <= iGenerateOut0;
GenerateOut1 <= iGenerateOut1;
end architecture IMP;
| gpl-3.0 |
nickg/nvc | test/parse/comp.vhd | 1 | 211 | package p is
component c is
generic ( X : integer );
port ( o : out integer );
end component;
component foo
port ( x : inout integer );
end component foo;
end package;
| gpl-3.0 |
mistryalok/FPGA | Xilinx/ISE/Basics/dEMUX8x1/demux1x8.vhd | 1 | 1252 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:29:23 04/04/2013
-- Design Name:
-- Module Name: demux1x8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity demux1x8 is
Port ( i : in STD_LOGIC;
o : out std_logic_VECTOR (7 downto 0);
s : in bit_VECTOR (2 downto 0));
end demux1x8;
architecture Behavioral of demux1x8 is
begin
process(S)
begin
case s is
when "000" => o(0) <= i;
when "001" => o(1) <= i;
when "010" => o(2) <= i;
when "011" => o(3) <= i;
when "100" => o(4) <= i;
when "101" => o(5) <= i;
when "110" => o(6) <= i;
when "111" => o(7) <= i;
end case;
end process;
end Behavioral;
| gpl-3.0 |
nickg/nvc | test/regress/assign6.vhd | 1 | 577 | entity assign6 is
end entity;
architecture test of assign6 is
signal x : bit := '1';
begin
main: process is
type int_ptr is access integer;
type int_ptr_vec is array (natural range <>) of int_ptr;
variable a, b : bit;
variable p, q : int_ptr;
begin
wait for 1 ns;
(a, b) := bit_vector'(x, not x);
assert a = '1';
assert b = '0';
p := new integer'(5);
(p, q) := int_ptr_vec'(q, p);
assert q.all = 5;
assert p = null;
wait;
end process;
end architecture;
| gpl-3.0 |
nickg/nvc | test/lower/directmap3.vhd | 1 | 561 | entity sub is
generic ( W : natural );
port ( o : out bit_vector(1 to 2);
p : in bit_vector(1 to W) );
end entity;
architecture test of sub is
begin
end architecture;
-------------------------------------------------------------------------------
entity directmap3 is
end entity;
architecture test of directmap3 is
constant K : natural := 4;
signal o1, o2 : bit;
signal p : bit_vector(1 to 3);
begin
u: entity work.sub
generic map ( K - 1 )
port map ( o(1) => o1, o(2) => o2, p => p );
end architecture;
| gpl-3.0 |
nickg/nvc | test/sem/generics.vhd | 1 | 2837 | entity bot is
generic ( N : integer );
port ( o : out integer );
end entity;
architecture a of bot is
begin
process is
begin
o <= N;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
architecture test of top is
signal x : integer;
begin
bot0: entity work.bot -- OK
generic map ( N => 5 )
port map ( o => x );
bot1: entity work.bot -- OK
generic map ( 5 )
port map ( o => x );
bot3: entity work.bot
port map ( o => x ); -- Missing N
bot4: entity work.bot
generic map ( 1, 2 ) -- Too many generics
port map ( o => x );
end architecture;
-------------------------------------------------------------------------------
entity bad is
generic (
X : integer;
Y : integer := X + 1 ); -- X not visible
port (
p : in integer := X );
end entity;
-------------------------------------------------------------------------------
entity class is
generic (
constant X : integer; -- OK
signal Y : integer ); -- Error
end entity;
-------------------------------------------------------------------------------
package p is
component c is
generic ( X : integer ); -- OK
port ( p : in integer range 1 to X; -- OK
q : in integer range 1 to Y ); -- Error
end component;
end package;
-------------------------------------------------------------------------------
entity static is
generic ( X : integer );
end entity;
architecture a of static is
constant k : integer := X + 1;
signal s : bit_vector(1 to 3);
alias sx : bit is s(X);
alias sx1 : bit is s(X + 1);
alias sx2 : bit_vector is s(k to 3);
function f(x : bit_vector) return integer;
component c is
generic (
x : bit_vector(2 downto 0) );
end component;
component d is
generic (
t : time );
end component;
begin
i1: entity work.bot
generic map (
N => f("100") )
port map (
o => open );
i2: component c
generic map ( x => "00" & '1' ); -- OK
i3: component c
generic map ( x => "00" & sx ); -- Error
i4: component d
generic map ( t => 100 ns ); -- OK
i5: component c
generic map ( 6 => 1 ); -- Error
i6: component c
generic map ( "not"(x) => "101" ); -- Error
i7: component c
generic map ( i6 ); -- Error
i8: component c
generic map ( a ); -- Error
i9: component c
generic map ( std.standard ); -- Error
end architecture;
| gpl-3.0 |
nickg/nvc | test/regress/attr1.vhd | 1 | 869 | entity attr1 is
end entity;
architecture test of attr1 is
type my_int is range 10 downto 0;
begin
process is
variable x : integer;
variable y : my_int;
begin
assert integer'left = -2147483648;
x := integer'right;
wait for 1 ns;
assert x = 2147483647;
assert positive'left = 1;
assert natural'high = integer'high;
assert integer'ascending;
assert not my_int'ascending;
x := 0;
wait for 1 ns;
assert integer'succ(x) = 1;
assert integer'pred(x) = -1;
x := 1;
y := 1;
wait for 1 ns;
assert integer'leftof(x) = 0;
assert integer'rightof(x) = 2;
assert my_int'leftof(y) = 2;
assert my_int'rightof(y) = 0;
assert my_int'base'left = 10;
wait;
end process;
end architecture;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_bram_ctrl_v4_0/hdl/vhdl/checkbit_handler.vhd | 7 | 25695 | -------------------------------------------------------------------------------
-- checkbit_handler.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: checkbit_handler.vhd
--
-- Description: Generates the ECC checkbits for the input vector of data bits.
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity checkbit_handler is
generic (
C_ENCODE : boolean := true;
C_USE_LUT6 : boolean := true
);
port (
DataIn : in std_logic_vector(0 to 31); --- changed from 31 downto 0 to 0 to 31 to make it compatabile with LMB Controller's hamming code.
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Syndrome_4 : out std_logic_vector (0 to 1);
Syndrome_6 : out std_logic_vector (0 to 5);
Syndrome_Chk : in std_logic_vector (0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler;
library unisim;
use unisim.vcomponents.all;
architecture IMP of checkbit_handler is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
component XOR18 is
generic (
C_USE_LUT6 : boolean);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_USE_LUT6 : boolean;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
signal data_chk0 : std_logic_vector(0 to 17);
signal data_chk1 : std_logic_vector(0 to 17);
signal data_chk2 : std_logic_vector(0 to 17);
signal data_chk3 : std_logic_vector(0 to 14);
signal data_chk4 : std_logic_vector(0 to 14);
signal data_chk5 : std_logic_vector(0 to 5);
begin -- architecture IMP
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30);
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31);
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31);
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31);
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
signal data_chk3_i : std_logic_vector(0 to 17);
signal data_chk4_i : std_logic_vector(0 to 17);
signal data_chk6 : std_logic_vector(0 to 17);
begin
------------------------------------------------------------------------------------------------
-- Checkbit 0 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I0 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk0, -- [in std_logic_vector(0 to 17)]
res => CheckOut(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 1 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I1 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk1, -- [in std_logic_vector(0 to 17)]
res => CheckOut(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 2 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I2 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk2, -- [in std_logic_vector(0 to 17)]
res => CheckOut(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 3 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & "000";
XOR18_I3 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk3_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 4 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & "000";
XOR18_I4 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk4_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 5 built up from 1 LUT6
------------------------------------------------------------------------------------------------
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => CheckOut(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
XOR18_I6 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk6, -- [in std_logic_vector(0 to 17)]
res => CheckOut(6)); -- [out std_logic]
end generate Encode_Bits;
--------------------------------------------------------------------------------------------------
-- Decode bits to get syndrome and UE/CE signals
--------------------------------------------------------------------------------------------------
Decode_Bits : if (not C_ENCODE) generate
signal syndrome_i : std_logic_vector(0 to 6) := (others => '0');
signal chk0_1 : std_logic_vector(0 to 3);
signal chk1_1 : std_logic_vector(0 to 3);
signal chk2_1 : std_logic_vector(0 to 3);
signal data_chk3_i : std_logic_vector(0 to 15);
signal chk3_1 : std_logic_vector(0 to 1);
signal data_chk4_i : std_logic_vector(0 to 15);
signal chk4_1 : std_logic_vector(0 to 1);
signal data_chk5_i : std_logic_vector(0 to 6);
signal data_chk6 : std_logic_vector(0 to 38);
signal chk6_1 : std_logic_vector(0 to 5);
signal syndrome_0_to_2 : std_logic_vector (0 to 2);
signal syndrome_3_to_5 : std_logic_vector (3 to 5);
signal syndrome_3_to_5_multi : std_logic;
signal syndrome_3_to_5_zero : std_logic;
signal ue_i_0 : std_logic;
signal ue_i_1 : std_logic;
begin
------------------------------------------------------------------------------------------------
-- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk0_1(3) <= CheckIn(0);
Parity_chk0_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(0)); -- [out std_logic]
Parity_chk0_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(1)); -- [out std_logic]
Parity_chk0_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(2)); -- [out std_logic]
Parity_chk0_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk1_1(3) <= CheckIn(1);
Parity_chk1_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(0)); -- [out std_logic]
Parity_chk1_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(1)); -- [out std_logic]
Parity_chk1_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(2)); -- [out std_logic]
Parity_chk1_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk2_1(3) <= CheckIn(2);
Parity_chk2_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(0)); -- [out std_logic]
Parity_chk2_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(1)); -- [out std_logic]
Parity_chk2_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(2)); -- [out std_logic]
Parity_chk2_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & CheckIn(3);
Parity_chk3_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(0)); -- [out std_logic]
Parity_chk3_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(1)); -- [out std_logic]
-- For improved timing, remove Enable_ECC signal in this LUT level
Parity_chk3_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & CheckIn(4);
Parity_chk4_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(0)); -- [out std_logic]
Parity_chk4_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(1)); -- [out std_logic]
-- Set bit 4 output with default. Real ECC XOR value will be determined post register
-- stage.
syndrome_i (4) <= '0';
-- For improved timing, move last LUT level XOR to next side of pipeline
-- stage in read path.
Syndrome_4 <= chk4_1;
------------------------------------------------------------------------------------------------
-- Syndrome bit 5 built up from 1 LUT7
------------------------------------------------------------------------------------------------
data_chk5_i <= data_chk5 & CheckIn(5);
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
CheckIn(1) & CheckIn(0) & CheckIn(6);
Parity_chk6_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(0)); -- [out std_logic]
Parity_chk6_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(1)); -- [out std_logic]
Parity_chk6_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(2)); -- [out std_logic]
Parity_chk6_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(3)); -- [out std_logic]
Parity_chk6_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(4)); -- [out std_logic]
Parity_chk6_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(5)); -- [out std_logic]
-- No internal use for MSB of syndrome (it is created after the
-- register stage, outside of this block)
syndrome_i(6) <= '0';
Syndrome <= syndrome_i;
-- (N:0) <= (0:N)
-- Bring out seperate output to do final XOR stage on Syndrome (6) after
-- the pipeline stage.
Syndrome_6 <= chk6_1 (0 to 5);
---------------------------------------------------------------------------
-- With final syndrome registered outside this module for pipeline balancing
-- Use registered syndrome to generate any error flags.
-- Use input signal, Syndrome_Chk which is the registered Syndrome used to
-- correct any single bit errors.
syndrome_0_to_2 <= Syndrome_Chk(0) & Syndrome_Chk(1) & Syndrome_Chk(2);
syndrome_3_to_5 <= Syndrome_Chk(3) & Syndrome_Chk(4) & Syndrome_Chk(5);
syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0';
syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or
syndrome_3_to_5 = "011" or
syndrome_3_to_5 = "101")
else '0';
-- Ensure that CE flag is only asserted for a single clock cycle (and does not keep
-- registered output value)
CE <= (Enable_ECC and Syndrome_Chk(6)) when (syndrome_3_to_5_multi = '0') else '0';
-- Similar edit from CE flag. Ensure that UE flags are only asserted for a single
-- clock cycle. The flags are registered outside this module for detection in
-- register module.
ue_i_0 <= Enable_ECC when (syndrome_3_to_5_zero = '0') or (syndrome_0_to_2 /= "000") else '0';
ue_i_1 <= Enable_ECC and (syndrome_3_to_5_multi);
Use_LUT6: if (C_USE_LUT6) generate
begin
UE_MUXF7 : MUXF7
port map (
I0 => ue_i_0,
I1 => ue_i_1,
S => Syndrome_Chk(6),
O => UE);
end generate Use_LUT6;
Use_RTL: if (not C_USE_LUT6) generate
begin
UE <= ue_i_1 when Syndrome_Chk(6) = '1' else ue_i_0;
end generate Use_RTL;
end generate Decode_Bits;
end architecture IMP;
| gpl-3.0 |
nickg/nvc | test/sem/issue359a.vhd | 2 | 258 | -- this test program aborts during analysis
entity nvc_bug is
end nvc_bug;
architecture behav of nvc_bug is
signal host_write : bit;
begin
process
procedure host_write is
begin
end host_write;
begin
host_write <= '1';
end process;
end behav;
| gpl-3.0 |
nickg/nvc | test/regress/concat4.vhd | 5 | 411 | entity concat4 is
end entity;
architecture test of concat4 is
type mem_type is array (2 downto 0) of bit_vector(7 downto 0);
begin
process is
variable m : mem_type := ( X"03", X"02", X"01" );
variable b : bit_vector(7 downto 0);
begin
b := X"ff";
m := m(1 downto 0) & b;
assert m = ( X"02", X"01", X"ff" );
wait;
end process;
end architecture;
| gpl-3.0 |
nickg/nvc | test/regress/conv5.vhd | 1 | 1681 | package pack is
type int_vector is array (natural range <>) of natural;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
generic ( size : natural );
port ( o1 : out int_vector(1 to size);
o2 : out int_vector(1 to 3);
i1 : in integer );
end entity;
architecture test of sub is
begin
p1: process is
variable tmp : int_vector(1 to size);
begin
assert i1 = 0;
for i in 1 to size loop
tmp(i) := i;
end loop;
o1 <= tmp;
o2 <= (5, 6, 7);
wait for 1 ns;
assert i1 = 150;
o1(1) <= 10;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity conv5 is
end entity;
use work.pack.all;
architecture test of conv5 is
signal x1 : integer;
signal x2 : integer;
signal y : int_vector(1 to 5);
function sum_ints(v : in int_vector) return integer is
variable result : integer := 0;
begin
for i in v'range loop
result := result + v(i);
end loop;
return result;
end function;
begin
uut1: entity work.sub
generic map ( size => 5)
port map ( sum_ints(o1) => x1,
sum_ints(o2) => x2,
i1 => sum_ints(y) );
p2: process is
begin
assert x1 = 0;
assert x2 = 0;
y <= (10, 20, 30, 40, 50);
wait for 1 ns;
assert x1 = 15;
assert x2 = 18;
wait for 1 ns;
assert x1 = 24;
wait;
end process;
end architecture;
| gpl-3.0 |
nickg/nvc | test/lower/bounds1.vhd | 1 | 417 | entity bounds1 is
end entity;
architecture test of bounds1 is
type int_vec is array (natural range <>) of integer;
begin
p1: process is
variable v : int_vec(0 to 9) := (others => 0);
variable k : integer range 0 to 9;
begin
assert v(k) = 1; -- Should elide
assert v(k + 1) = 1; -- Cannot elide
wait;
end process;
end architecture;
| gpl-3.0 |
nickg/nvc | test/regress/protected4.vhd | 2 | 590 | entity protected4 is
end entity;
architecture test of protected4 is
type p is protected
procedure init(path : string);
end protected;
type p is protected body
type ft is file of integer;
file f : ft;
procedure init(path : string) is
begin
file_open(f, path, WRITE_MODE);
end procedure;
end protected body;
procedure run_test is
variable x : p;
begin
x.init("data");
end procedure;
begin
process is
begin
run_test;
wait;
end process;
end architecture;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ip/design_1_axi_timer_0_0/synth/design_1_axi_timer_0_0.vhd | 1 | 9209 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_axi_timer_0_0 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END design_1_axi_timer_0_0;
ARCHITECTURE design_1_axi_timer_0_0_arch OF design_1_axi_timer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "axi_timer,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_timer_0_0_arch : ARCHITECTURE IS "design_1_axi_timer_0_0,axi_timer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "design_1_axi_timer_0_0,axi_timer,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_timer,x_ipVersion=2.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_COUNT_WIDTH=32,C_ONE_TIMER_ONLY=0,C_TRIG0_ASSERT=1,C_TRIG1_ASSERT=1,C_GEN0_ASSERT=1,C_GEN1_ASSERT=1,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "zynq",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END design_1_axi_timer_0_0_arch;
| gpl-3.0 |
nickg/nvc | test/misc/kcuart.vhd | 5 | 724 | entity kcuart is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of kcuart is
signal clk : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0);
signal tx_full : std_logic;
signal tx_wr : std_logic := '0';
signal uart_tx : std_logic;
signal en_16_x_baud : std_logic;
begin
clk <= not clk after 5 ns;
tx_i: entity work.uart_tx6
port map (
data_in => tx_data,
en_16_x_baud => en_16_x_baud,
serial_out => uart_tx,
buffer_write => tx_wr,
buffer_full => tx_full,
buffer_reset => '0',
clk => clk );
end architecture;
| gpl-3.0 |
nickg/nvc | test/regress/protected5.vhd | 1 | 1524 | -- The order of design units in the file is significant
package pack1 is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
end package;
-------------------------------------------------------------------------------
use work.pack1.all;
package pack2 is
shared variable sv : SharedCounter;
end package;
-------------------------------------------------------------------------------
entity protected5 is
end entity;
use work.pack2.all;
architecture test of protected5 is
begin
p1: process is
begin
sv.increment;
sv.increment;
wait for 0 ns;
assert sv.value = 3;
wait;
end process;
p2: process is
begin
sv.increment;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
package body pack1 is
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
end package body;
| gpl-3.0 |
nickg/nvc | test/regress/record30.vhd | 1 | 722 | entity record30 is
end entity;
architecture test of record30 is
type int_ptr is access integer;
type pair is record
x, y : natural;
end record;
type rec is record
x : bit_vector;
y : int_ptr;
z : pair;
end record;
begin
main: process is
variable s : rec(x(1 to 3));
begin
assert s.x = "000";
assert s = (x => "000", y => null, z => (0, 0));
s.x := "101";
assert s.x = "101";
assert s = (x => "101", y => null, z => (0, 0));
s := (x => "111", y => null, z => (0, 0));
assert s.x = "111";
assert s = (x => "111", y => null, z => (0, 0));
wait;
end process;
end architecture;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_sg_v4_1/hdl/src/vhdl/axi_sg_skid2mm_buf.vhd | 7 | 17071 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_wr_demux;
-------------------------------------------------------------------------------
entity axi_sg_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_sg_skid2mm_buf;
architecture implementation of axi_sg_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_sg_v4_1_2.axi_sg_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
| gpl-3.0 |
nickg/nvc | test/elab/comp3.vhd | 1 | 756 | entity sub1 is
generic ( x : integer );
end entity;
architecture test of sub1 is
constant y : integer := x;
begin
end architecture;
-------------------------------------------------------------------------------
entity sub2 is
generic ( x : integer := 5 ;
y : boolean := true );
end entity;
architecture test of sub2 is
begin
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
architecture test of top is
component sub1 is
end component;
component sub2 is
generic ( x : boolean := false ;
y : integer := 7 );
end component;
begin
sub1_i: component sub1;
sub2_i: component sub2;
end architecture;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_strb_gen2.vhd | 18 | 101757 | -------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
| gpl-3.0 |
nickg/nvc | test/parse/vhdl2008.vhd | 1 | 6830 | --
-- Grab bag of miscellaneous VHDL-2008 syntax
--
entity vhdl2008 is
end entity;
package genpack is
generic ( x : integer := 5; y : boolean ); -- OK
generic map ( x => 5, y => false ); -- OK
constant c : bit_vector(1 to x) := (1 to x => '1');
end package;
package genpack2 is
generic ( x : integer := 5; y : boolean ); -- OK
function add_x_if_y ( arg : integer ) return integer;
end package;
package body genpack2 is
function add_x_if_y ( arg : integer ) return integer is
begin
if y then
return arg + x;
else
return arg;
end if;
end function;
end package body;
package primary_genpack2 is new work.genpack2 generic map (4, false); -- OK
architecture test of vhdl2008 is
type my_utype is (a, b, c);
type my_utype_vector is array (natural range <>) of my_utype;
function resolved (s : my_utype_vector) return my_utype;
subtype my_type is resolved my_utype;
subtype my_type_vector is (resolved) my_utype_vector; -- OK
type my_logical_vec is array (natural range <>) of bit;
type my_bool is (true, false);
package my_genpack2 is new work.genpack2 generic map (1, true); -- OK
begin
process is
variable b : bit;
variable v : my_logical_vec(1 to 3);
begin
b := or v; -- OK
if or v = '1' then end if; -- OK
b := and v; -- OK
b := xor v; -- OK
b := xnor v; -- OK
b := nand v; -- OK
b := nor v; -- OK
end process;
process is
variable b : bit;
variable v : my_logical_vec(1 to 3);
begin
b := b ?= '1'; -- OK
b := b ?/= '1'; -- OK
b := b ?< '0'; -- OK
b := b ?> '0'; -- OK
b := b ?<= '1'; -- OK
b := b ?>= '1'; -- OK
b := v ?= "101"; -- OK
b := v ?/= "111"; -- OK
end process;
process is
variable b : bit;
variable i : integer;
function "??"(x : integer) return boolean;
begin
if b then end if; -- OK
if b xor '1' then end if; -- OK
while b and '1' loop end loop; -- OK
if i + 1 then end if; -- OK
if now + 1 ns then end if; -- Error
while true loop
exit when b or '1'; -- OK
next when b or '1'; -- OK
end loop;
wait until b xor '0'; -- OK
assert b nor '1'; -- OK
assert ?? 1; -- OK
end process;
/* This is a comment */
/* Comments /* do not nest */
process is
variable x, y : integer;
begin
x := 1 when y > 2 else 5; -- OK
end process;
process is
variable x : string(7 downto 0);
begin
x := 8x"0"; -- OK
x := 6x"a"; -- OK
x := 4x"4"; -- OK
x := 2x"4"; -- Error
x := 0x"5"; -- Error
x := 18x"383fe"; -- OK
x := 0b"0000"; -- OK
x := d"5"; -- OK
x := 5d"25"; -- OK
x := 120d"83298148949012041209428481024019511"; -- Error
x := uo"5"; -- OK
x := 5sb"11"; -- OK
x := 2sb"1111110"; -- OK
x := 2sb"10110101"; -- Error
x := 4x"0f"; -- OK
x := Uo"2C"; -- OK
x := d"C4"; -- Error
x := 8x"-"; -- OK
x := 12d"13"; -- OK
end process;
b2: block is
signal s : integer;
begin
process is
begin
s <= 1 when s < 0 else 5; -- OK
end process;
end block;
process is
type int_vec2 is array (natural range <>) of integer_vector; -- OK
constant a : int_vec2(1 to 3)(1 to 2) := ( -- OK
(1, 2), (3, 4), (5, 6) );
begin
assert a(1)(1) = 1; -- OK
end process;
b3: block is
signal s : integer;
begin
process is
begin
s <= force 1; -- OK
s <= force out 1; -- OK
s <= force in 2; -- OK
s <= release; -- OK
s <= release out; -- OK
end process;
end block;
process is
variable x : bit_vector(1 to 3);
begin
case? x is -- OK
when "010" => null;
when others => null;
end case?;
case? x is
when others => null;
end case; -- Error
case x is
when others => null;
end case ?; -- Error
end process;
b4: block is
procedure foo (x : integer_vector; y : integer) is
variable a : x'subtype; -- OK
variable b : integer'subtype; -- OK
variable c : b4'subtype; -- Error
variable d : x'element; -- OK
variable e : y'element; -- Error
variable f : b4'element; -- Error
begin
end procedure;
begin
end block;
b5: block is
function gen1 generic (n : integer) (x : integer) return integer is
begin -- OK
return 1;
end function;
function gen2 generic (n : integer) -- OK
parameter (x : integer) return integer;
function gen3 generic (type t; p : t) (x : t) return integer; -- Ok
function my_gen1 is new gen1 generic map (5); -- OK
begin
end block;
b6: block is
constant c1 : string := to_string(100); -- OK
begin
end block;
b7: block is
signal s : integer;
signal b : bit;
begin
s <= 1 when b else 2; -- OK
s <= 2 when '1' else 6; -- OK
process is
variable v : integer;
begin
v := 1 when b else 5; -- OK
s <= 5 when b else 7; -- OK
end process;
end block;
g1: if g1a: true generate -- OK
elsif g2: false generate
begin
end g2;
else generate
end generate;
g1: if true generate
end g1; -- Error
else foo: generate
end bar; -- Error
end generate;
end architecture;
| gpl-3.0 |
nickg/nvc | test/sem/osvvm3.vhd | 1 | 1684 | package my_logic is
type unsigned is array (natural range <>) of bit;
type signed is array (natural range <>) of bit;
function to_integer(x : unsigned) return integer;
function to_integer(x : signed) return integer;
end package;
use work.my_logic.all;
package codec_builder_pkg is
function from_byte_array (
constant byte_array : string)
return bit_vector;
constant integer_code_length : positive := 4;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out work.my_logic.unsigned);
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out work.my_logic.signed);
end package codec_builder_pkg;
package body codec_builder_pkg is
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out integer) is
begin
result := to_integer(work.my_logic.signed(from_byte_array(code(index to index + integer_code_length - 1))));
index := index + integer_code_length;
end procedure decode;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out work.my_logic.unsigned) is
variable result_bv : bit_vector(result'range);
begin
result := work.my_logic.unsigned(result_bv);
end;
procedure decode (
constant code : string;
variable index : inout positive;
variable result : out work.my_logic.signed) is
variable result_bv : bit_vector(result'range);
begin
result := work.my_logic.signed(result_bv);
end;
end package body codec_builder_pkg;
| gpl-3.0 |
nickg/nvc | test/regress/default2.vhd | 1 | 1192 | entity default2 is
end entity;
architecture test of default2 is
procedure proc1 (x : integer) is
type real_vec is array (integer range <>) of real;
variable v : real_vec(1 to x);
begin
assert v(1) = real'left;
assert v(x) = real'left;
end procedure;
procedure proc2 (x : integer) is
type rec is record
x : real;
y : bit_vector(1 to x);
end record;
type rec_vec is array (natural range <>) of rec;
variable v : rec_vec(1 to x);
begin
assert v(1).x = real'left;
assert v(1).y = (1 to x => '0');
assert v(x).x = real'left;
assert v(x).y = (1 to x => '0');
end procedure;
procedure proc3 (x : integer) is
type int_ptr is access integer;
type rec is record
x : int_ptr;
end record;
type rec_vec is array (natural range <>) of rec;
variable v : rec_vec(1 to x);
begin
assert v(1).x = null;
assert v(x).x = null;
end procedure;
begin
main: process is
begin
proc1(5);
proc2(6);
proc3(2);
wait;
end process;
end architecture;
| gpl-3.0 |
nickg/nvc | test/regress/issue94.vhd | 5 | 761 | package pkg is
function func (dataw : integer; shiftw : integer)return bit_vector;
end pkg;
package body pkg is
function func (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_array (0 to max_shift);
begin
y_temp(0):=(others=>'1'); -- Error with LLVM asserts build
y_temp(1):=(others => '0');
return y_temp(0);
end func;
end pkg;
entity issue94 is
end entity;
use work.pkg.all;
architecture test of issue94 is
begin
process is
begin
assert func(4, 4) = "1111";
wait;
end process;
end architecture;
| gpl-3.0 |
nickg/nvc | test/regress/logical2.vhd | 1 | 2510 | entity logical2 is
end entity;
architecture test of logical2 is
signal x : bit;
signal one : bit := '1';
signal zero : bit := '0';
signal vec : bit_vector(0 to 1) := ('0', '1');
begin
process is
variable v : boolean := true;
begin
x <= '0';
wait for 1 ns;
assert (x and zero) = zero;
assert (x and one) = zero;
assert (x or zero) = zero;
assert (x or one) = one;
assert (x xor zero) = zero;
assert (x xor one) = one;
assert (x xnor zero) = one;
assert (x xnor one) = zero;
assert (x nand zero) = one;
assert (x nand one) = one;
assert (x nor zero) = one;
assert (x nor one) = zero;
x <= '1';
wait for 1 ns;
assert (x and zero) = zero;
assert (x and one) = one;
assert (x or zero) = one;
assert (x or one) = one;
assert (x xor zero) = one;
assert (x xor one) = zero;
assert (x xnor zero) = zero;
assert (x xnor one) = one;
assert (x nand zero) = one;
assert (x nand one) = zero;
assert (x nor zero) = zero;
assert (x nor one) = zero;
v := v and v; assert v;
v := v or v; assert v;
v := v nand v; assert not v;
v := v nor v; assert v;
v := v xor v; assert not v;
v := v xnor v; assert v;
v := v xnor v; assert v;
-- This tests short circuiting
x <= '0';
wait for 1 ns;
assert (x and vec(0)) = zero;
assert (x and vec(1)) = zero;
assert (x or vec(0)) = zero;
assert (x or vec(1)) = one;
assert (x xor vec(0)) = zero;
assert (x xor vec(1)) = one;
assert (x xnor vec(0)) = one;
assert (x xnor vec(1)) = zero;
assert (x nand vec(0)) = one;
assert (x nand vec(1)) = one;
assert (x nor vec(0)) = one;
assert (x nor vec(1)) = zero;
x <= '1';
wait for 1 ns;
assert (x and vec(0)) = zero;
assert (x and vec(1)) = one;
assert (x or vec(0)) = one;
assert (x or vec(1)) = one;
assert (x xor vec(0)) = one;
assert (x xor vec(1)) = zero;
assert (x xnor vec(0)) = zero;
assert (x xnor vec(1)) = one;
assert (x nand vec(0)) = one;
assert (x nand vec(1)) = zero;
assert (x nor vec(0)) = zero;
assert (x nor vec(1)) = zero;
wait;
end process;
end architecture;
| gpl-3.0 |
nickg/nvc | test/regress/bounds12.vhd | 5 | 190 | entity bounds12 is
end entity;
architecture test of bounds12 is
begin
process is
begin
assert integer'value("hello") = 5;
wait;
end process;
end architecture;
| gpl-3.0 |
nickg/nvc | test/regress/bounds36.vhd | 1 | 464 | entity bounds36 is
end entity;
architecture test of bounds36 is
begin
main: process is
variable x : integer_vector(4 downto 0);
variable y : integer_vector(1 downto 0);
variable z : integer_vector(2 downto 0);
variable i0, i1 : integer;
begin
x := (1, 2, 3, 4, 5);
i1 := 1;
wait for 1 ns;
(i1, y) := x(4 downto i1); -- Error
wait;
end process;
end architecture;
| gpl-3.0 |
nickg/nvc | test/sem/issue509.vhd | 1 | 389 | entity test is
end entity test;
architecture beh of test is
type t_vvc_config is
record
clock_name : string(1 to 30);
end record;
signal vvc_config : t_vvc_config;
alias clock_name : string is vvc_config.clock_name;
begin
process
begin
vvc_config.clock_name <= (others => NUL);
clock_name <= (others => NUL);
wait;
end process;
end architecture beh;
| gpl-3.0 |
nickg/nvc | test/regress/func8.vhd | 2 | 627 | entity func8 is
end entity;
architecture test of func8 is
type real_vector is array (natural range <>) of real;
function lookup(index : integer) return real is
constant table : real_vector := (
0.62, 61.62, 71.7, 17.25, 26.15, 651.6, 0.45, 5.761 );
begin
return table(index);
end function;
begin
process is
variable x : integer;
begin
x := 0;
wait for 0 ns;
assert lookup(x) = 0.62; -- Avoid constant folding
x := 2;
wait for 0 ns;
assert lookup(x) = 71.7;
wait;
end process;
end architecture;
| gpl-3.0 |
nickg/nvc | test/lower/nullarray.vhd | 1 | 407 | entity nullarray is
end entity;
architecture test of nullarray is
subtype null_range_type is integer range 1 to -1;
type rec is record
x, y : integer;
z : bit_vector(1 to 3);
end record;
type rec_array is array (natural range <>) of rec;
constant A : bit_vector := "010";
constant B : rec_array(null_range_type) := (others => (0, 1, A));
begin
end architecture;
| gpl-3.0 |
nickg/nvc | test/eopt/array3.vhd | 3 | 532 | entity array3 is
end entity;
architecture test of array3 is
type matrix2x4 is array (1 to 2, 1 to 4) of integer;
signal m : matrix2x4;
begin
process is
begin
assert m(2, 2) = integer'left;
m(2, 2) <= 5;
wait for 1 ns;
assert m(2, 2) = 5;
m(2, 3) <= m(2, 2);
wait for 1 ns;
assert m(2, 3) = 5;
m <= ( (1, 2, 3, 4),
(5, 6, 7, 8) );
wait for 1 ns;
assert m(2, 4) = 8;
wait;
end process;
end architecture;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_full_wrap.vhd | 3 | 70871 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Full Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_reset;
use axi_datamover_v5_1_10.axi_datamover_cmd_status;
use axi_datamover_v5_1_10.axi_datamover_pcc;
use axi_datamover_v5_1_10.axi_datamover_addr_cntl;
use axi_datamover_v5_1_10.axi_datamover_rddata_cntl;
use axi_datamover_v5_1_10.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1_10.axi_datamover_mm2s_dre;
Use axi_datamover_v5_1_10.axi_datamover_rd_sf;
use axi_datamover_v5_1_10.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_full_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 1;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Lite MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the incllusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit Store and Forward
-- 1 = Include Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ---------------------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- MM2S Halt request input control --------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Error discrete output ------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ---------
-- Used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
-------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ----------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
-------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -------------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
---------------------------------------------------------------
-- Address Posting contols ------------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
---------------------------------------------------------------
-- MM2S AXI Address Channel I/O ---------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals ------------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
------------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O -----------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
---------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
----------------------------------------------------------------------------------------
-- Testing Support I/O -------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------
);
end entity axi_datamover_mm2s_full_wrap;
architecture implementation of axi_datamover_mm2s_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
If (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else -- no DRE
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others => -- 128 ratio
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for MM2S
-- modules upstream from the downsizing Store and Forward. If
-- Store and Forward is present, then the effective native width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Native Data width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled = 1) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-- Constant Declarations ----------------------------------------
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH,
C_MM2S_SDATA_WIDTH,
C_INCLUDE_MM2S_GP_SF);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S;
Constant IS_MM2S : integer range 0 to 1 := 1;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH;
Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE;
Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED;
Constant NO_INDET_BTT : integer range 0 to 1 := 0;
Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE,
C_MM2S_SDATA_WIDTH);
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE,
C_MM2S_SDATA_WIDTH);
-- Calculates the minimum needed depth of the Store and Forward FIFO
-- based on the MM2S pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * MM2S_BURST_SIZE;
-- Assigns the depth of the optional Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH,
MM2S_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2rdc_wready : std_logic := '0';
signal sig_rdc2sf_wvalid : std_logic := '0';
signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_rdc2sf_wlast : std_logic := '0';
signal sig_skid2dre_wready : std_logic := '0';
signal sig_dre2skid_wvalid : std_logic := '0';
signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2skid_wlast : std_logic := '0';
signal sig_dre2sf_wready : std_logic := '0';
signal sig_sf2dre_wvalid : std_logic := '0';
signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2dre_wlast : std_logic := '0';
signal sig_rdc2dre_new_align : std_logic := '0';
signal sig_rdc2dre_use_autodest : std_logic := '0';
signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_flush : std_logic := '0';
signal sig_sf2dre_new_align : std_logic := '0';
signal sig_sf2dre_use_autodest : std_logic := '0';
signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_flush : std_logic := '0';
signal sig_dre_new_align : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_sf_allow_addr_req : std_logic := '0';
signal sig_mm2s_allow_addr_req : std_logic := '0';
signal sig_addr_req_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_sf2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2sf_cmd_valid : std_logic := '0';
signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2sf_drr : std_logic := '0';
signal sig_mstr2sf_eof : std_logic := '0';
signal sig_mstr2sf_calc_error : std_logic := '0';
signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_data2sf_cmd_cmplt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
signal mm2s_aruser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug vector output
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc
mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc
-- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
sig_cache_data <= mm2s_cmd_wdata(79+(C_MM2S_ADDR_WIDTH-32) downto 72+(C_MM2S_ADDR_WIDTH-32)); -- This is the xUser and xCache values
end generate GEN_CACHE2;
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_10.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_10.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1_10.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1_10.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_MM2S ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_BTT_USED => MM2S_BTT_USED ,
C_SUPPORT_INDET_BTT => NO_INDET_BTT ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_btt => sig_mstr2sf_btt ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_cmd_cmplt => open ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_10.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => mm2s_arcache_int ,
addr2axi_auser => mm2s_aruser_int ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_mm2s_allow_addr_req ,
addr_req_posted => sig_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1_10.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => sig_rdc2dre_new_align ,
mm2s_dre_use_autodest => sig_rdc2dre_use_autodest ,
mm2s_dre_src_align => sig_rdc2dre_src_align ,
mm2s_dre_dest_align => sig_rdc2dre_dest_align ,
mm2s_dre_flush => sig_rdc2dre_flush ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_rdc2sf_wvalid ,
mm2s_strm_wready => sig_sf2rdc_wready ,
mm2s_strm_wdata => sig_rdc2sf_wdata ,
mm2s_strm_wstrb => sig_rdc2sf_wstrb ,
mm2s_strm_wlast => sig_rdc2sf_wlast ,
-- MM2S Store and Forward Supplimental Control ----------
mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_SF
--
-- If Generate Description:
-- Include the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate
begin
-- Merge external address posting control with the
-- Store and Forward address posting control
sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and
mm2s_allow_addr_req;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
sig_dre_new_align <= sig_sf2dre_new_align ;
sig_dre_use_autodest <= sig_sf2dre_use_autodest ;
sig_dre_src_align <= sig_sf2dre_src_align ;
sig_dre_dest_align <= sig_sf2dre_dest_align ;
sig_dre_flush <= sig_sf2dre_flush ;
------------------------------------------------------------
-- Instance: I_RD_SF
--
-- Description:
-- Instance for the MM2S Store and Forward module with
-- downsizer support.
--
------------------------------------------------------------
I_RD_SF : entity axi_datamover_v5_1_10.axi_datamover_rd_sf
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_DRE_IS_USED => INCLUDE_DRE ,
C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -------------------------------
aclk => mm2s_aclk ,
reset => sig_mmap_rst ,
-- DataMover Read Side Address Pipelining Control Interface
ok_to_post_rd_addr => sig_sf_allow_addr_req ,
rd_addr_posted => sig_addr_req_posted ,
rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- Read Side Stream In from DataMover MM2S Read Data Controller -----
sf2sin_tready => sig_sf2rdc_wready ,
sin2sf_tvalid => sig_rdc2sf_wvalid ,
sin2sf_tdata => sig_rdc2sf_wdata ,
sin2sf_tkeep => sig_rdc2sf_wstrb ,
sin2sf_tlast => sig_rdc2sf_wlast ,
-- RDC Store and Forward Supplimental Controls ----------
data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
data2sf_dre_flush => sig_rdc2dre_flush ,
-- DRE Control Interface from the Command Calculator -----------------------------
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset ,
-- MM2S DRE Control -------------------------------------------------------------
sf2dre_new_align => sig_sf2dre_new_align ,
sf2dre_use_autodest => sig_sf2dre_use_autodest ,
sf2dre_src_align => sig_sf2dre_src_align ,
sf2dre_dest_align => sig_sf2dre_dest_align ,
sf2dre_flush => sig_sf2dre_flush ,
-- Stream Out ----------------------------------
sout2sf_tready => sig_dre2sf_wready ,
sf2sout_tvalid => sig_sf2dre_wvalid ,
sf2sout_tdata => sig_sf2dre_wdata ,
sf2sout_tkeep => sig_sf2dre_wstrb ,
sf2sout_tlast => sig_sf2dre_wlast
);
-- ------------------------------------------------------------
-- -- Instance: I_RD_SF
-- --
-- -- Description:
-- -- Instance for the MM2S Store and Forward module.
-- --
-- ------------------------------------------------------------
-- I_RD_SF : entity axi_datamover_v5_1_10.axi_datamover_rd_sf
-- generic map (
--
-- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
-- C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
-- C_DRE_IS_USED => INCLUDE_DRE ,
-- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
--
-- -- Clock and Reset inputs -------------------------------
-- aclk => mm2s_aclk ,
-- reset => sig_mmap_rst ,
--
--
-- -- DataMover Read Side Address Pipelining Control Interface
-- ok_to_post_rd_addr => sig_sf_allow_addr_req ,
-- rd_addr_posted => sig_addr_req_posted ,
-- rd_xfer_cmplt => sig_rd_xfer_cmplt ,
--
--
--
-- -- Read Side Stream In from DataMover MM2S -----
-- sf2sin_tready => sig_sf2dre_wready ,
-- sin2sf_tvalid => sig_dre2sf_wvalid ,
-- sin2sf_tdata => sig_dre2sf_wdata ,
-- sin2sf_tkeep => sig_dre2sf_wstrb ,
-- sin2sf_tlast => sig_dre2sf_wlast ,
--
--
--
-- -- Stream Out ----------------------------------
-- sout2sf_tready => sig_skid2sf_wready ,
-- sf2sout_tvalid => sig_sf2skid_wvalid ,
-- sf2sout_tdata => sig_sf2skid_wdata ,
-- sf2sout_tkeep => sig_sf2skid_wstrb ,
-- sf2sout_tlast => sig_sf2skid_wlast
--
-- );
end generate GEN_INCLUDE_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_SF
--
-- If Generate Description:
-- Omit the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate
begin
-- Allow external address posting control
-- Ignore Store and Forward Control
sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ;
sig_sf_allow_addr_req <= '0' ;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
-- DRE Control Bus (Connect to the Read data Controller)
sig_dre_new_align <= sig_rdc2dre_new_align ;
sig_dre_use_autodest <= sig_rdc2dre_use_autodest ;
sig_dre_src_align <= sig_rdc2dre_src_align ;
sig_dre_dest_align <= sig_rdc2dre_dest_align ;
sig_dre_flush <= sig_rdc2dre_flush ;
-- Just pass stream signals through
sig_sf2rdc_wready <= sig_dre2sf_wready ;
sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ;
sig_sf2dre_wdata <= sig_rdc2sf_wdata ;
sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ;
sig_sf2dre_wlast <= sig_rdc2sf_wlast ;
-- Always enable the DRE Cmd bus for loading to keep from
-- stalling the PCC module
sig_sf2mstr_cmd_ready <= LOGIC_HIGH;
end generate GEN_NO_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_DRE
--
-- If Generate Description:
-- Include the MM2S DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate
begin
------------------------------------------------------------
-- Instance: I_DRE64
--
-- Description:
-- Instance for the MM2S DRE whach can support widths of
-- 16 bits to 64 bits.
--
------------------------------------------------------------
I_DRE_16_to_64 : entity axi_datamover_v5_1_10.axi_datamover_mm2s_dre
generic map (
C_DWIDTH => MM2S_SDATA_WIDTH ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH
)
port map (
-- Control inputs
dre_clk => mm2s_aclk ,
dre_rst => sig_stream_rst ,
dre_new_align => sig_dre_new_align ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
dre_flush => sig_dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_sf2dre_wstrb ,
dre_in_tdata => sig_sf2dre_wdata ,
dre_in_tlast => sig_sf2dre_wlast ,
dre_in_tvalid => sig_sf2dre_wvalid ,
dre_in_tready => sig_dre2sf_wready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2skid_wstrb ,
dre_out_tdata => sig_dre2skid_wdata ,
dre_out_tlast => sig_dre2skid_wlast ,
dre_out_tvalid => sig_dre2skid_wvalid ,
dre_out_tready => sig_skid2dre_wready
);
end generate GEN_INCLUDE_MM2S_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_DRE
--
-- If Generate Description:
-- Omit the MM2S DRE and housekeep the signals that it
-- needs to output.
--
------------------------------------------------------------
GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate
begin
-- Just pass stream signals through from the Store
-- and Forward module
sig_dre2sf_wready <= sig_skid2dre_wready ;
sig_dre2skid_wvalid <= sig_sf2dre_wvalid ;
sig_dre2skid_wdata <= sig_sf2dre_wdata ;
sig_dre2skid_wstrb <= sig_sf2dre_wstrb ;
sig_dre2skid_wlast <= sig_sf2dre_wlast ;
end generate GEN_NO_MM2S_DRE;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_dre2skid_wvalid ,
s_ready => sig_skid2dre_wready ,
s_data => sig_dre2skid_wdata ,
s_strb => sig_dre2skid_wstrb ,
s_last => sig_dre2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_dre2skid_wvalid;
sig_skid2dre_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_dre2skid_wdata;
mm2s_strm_wstrb <= sig_dre2skid_wstrb;
mm2s_strm_wlast <= sig_dre2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
| gpl-3.0 |
nickg/nvc | test/regress/array1.vhd | 1 | 715 | entity array1 is
end entity;
architecture test of array1 is
type matrix_t is array (integer range <>, integer range <>) of integer;
constant c : matrix_t(0 to 1, 0 to 1) := (
( 1, 2 ),
( 3, 4 ) );
begin
process is
variable m : matrix_t(1 to 3, 1 to 3) := (
( 1, 2, 3 ),
( 4, 5, 6 ),
( 7, 8, 9 ) );
begin
report integer'image(m(1, 3));
report integer'image(m(2, 2));
assert m(2, 2) = 5;
assert m(3, 1) = 7;
report integer'image(c(1, 0));
assert c(1, 0) = 3;
assert c = ( (1, 2), (3, 4) );
assert c /= ( (1, 2), (3, 5) );
wait;
end process;
end architecture;
| gpl-3.0 |
nickg/nvc | test/regress/issue262.vhd | 3 | 2817 | package textio is
type line is access string;
end package;
use work.textio.all;
package PKG is
procedure SCAN(
variable TEXT_LINE : inout LINE;
TEXT_END : in integer;
START_POS : in integer;
FOUND : out boolean;
FOUND_LEN : out integer
);
end package;
use work.textio.all;
package body PKG is
procedure SCAN(
variable TEXT_LINE : inout LINE;
TEXT_END : in integer;
START_POS : in integer;
FOUND : out boolean;
FOUND_LEN : out integer
) is
variable len : integer;
variable char : character;
begin
len := 1;
for pos in START_POS+1 to text_end loop
char := text_line(pos);
case char is
when NUL|SOH|STX|ETX|EOT|ENQ|ACK|BEL|
BS |HT |LF |VT |FF |CR |SO |SI |
DLE|DC1|DC2|DC3|DC4|NAK|SYN|ETB|
CAN|EM |SUB|ESC|FSP|GSP|RSP|USP|DEL =>
exit;
when '['|']'|'{'|'}'|',' =>
for prev_pos in pos-1 downto START_POS loop
exit when (text_line(prev_pos) /= ' ');
len := len - 1;
end loop;
exit;
when ':'=>
for prev_pos in pos-1 downto START_POS loop
exit when (text_line(prev_pos) /= ' ');
len := len - 1;
end loop;
exit;
when '#' =>
for prev_pos in pos-1 downto START_POS loop
exit when (text_line(prev_pos) /= ' ');
len := len - 1;
end loop;
exit;
when others => null;
end case;
len := len + 1;
end loop;
FOUND := TRUE;
FOUND_LEN := len;
end procedure;
end package body;
use work.textio.all;
library WORK;
use WORK.PKG.all;
entity issue262 is
end issue262;
architecture MODEL of issue262 is
begin
process
variable text_line : LINE;
variable text_end : integer;
variable found : boolean;
variable found_len : integer;
begin
--write(text_line, string'("{A:1}"));
text_line := new string'("{A:1}");
text_end := 4;
SCAN(text_line, text_end, 1, found, found_len);
report boolean'image(found);
report integer'image(found_len);
assert found;
assert found_len = 2;
wait;
end process;
end MODEL;
| gpl-3.0 |
nickg/nvc | test/regress/signal19.vhd | 1 | 887 | entity sub is
port (
o : out bit_vector(1 to 3) );
end entity;
architecture test of sub is
procedure write1(signal x : out bit) is
begin
x <= '1';
end procedure;
begin
p1: process is
begin
write1(o(1));
wait for 1 ns;
write1(o(3));
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity signal19 is
end entity;
architecture test of signal19 is
signal x : bit_vector(1 to 3);
begin
uut: entity work.sub port map ( x );
main: process is
begin
wait on x for 100 ns;
assert now = 0 ns;
wait on x for 100 ns;
assert now = 1 ns;
assert x'active;
assert not x(1)'active;
assert x(3)'active;
assert x = "101";
wait;
end process;
end architecture;
| gpl-3.0 |
nickg/nvc | test/parse/seq.vhd | 1 | 3943 | entity bb is
end entity;
architecture aa of bb is
signal x, y, z : integer;
signal w : bit_vector(1 to 3);
begin
-- Wait statements
process is
begin
wait for 1 ns;
block_forever: wait;
wait on x;
wait on x, y, z(1 downto 0);
wait on w(1) for 2 ns;
wait until x = 3;
wait until y = x for 5 ns;
wait on x until x = 2 for 1 ns;
end process;
-- Blocking assignment
process is
variable a : integer;
begin
a := 2;
a := a + (a * 3);
end process;
-- Assert and report
process is
begin
assert true;
assert false severity note;
assert 1 > 2 report "oh no" severity failure;
report "hello";
report "boo" severity error;
end process;
-- Function calls
process is
variable a, b : integer;
function foo (x, y, z : integer) return integer;
begin
x := foo(1, 2, 3);
a := "abs"(b);
end process;
-- If
process is
variable x, y : integer;
begin
if true then
x := 1;
end if;
test: if true then
x := y;
end if test;
if x > 2 then
x := 5;
else
y := 2;
end if;
if x > 3 then
null;
elsif x > 5 then
null;
elsif true then
null;
else
x := 2;
end if;
end process;
-- Null
process is
begin
null;
end process;
-- Return
process is
begin
return 4 * 4;
end process;
-- While
process is
variable n : integer;
begin
while n > 0 loop
n := n - 1;
end loop;
loop
null;
end loop;
end process;
-- Delayed assignment
process is
begin
x <= 4 after 5 ns;
x <= 5 after 1 ns, 7 after 8 ns;
x <= 5, 7 after 8 ns;
x <= inertial 5;
x <= transport 4 after 2 ns;
x <= reject 4 ns inertial 6 after 10 ns;
end process;
-- For
process is
type foo is (A, B, C);
begin
for i in 0 to 10 loop
null;
end loop;
for i in foo'range loop
null;
end loop;
end process;
-- Exit
process is
begin
exit;
exit when x = 1;
end process;
-- Procedure call
process is
procedure foo (a, b, c : integer);
procedure bar;
begin
foo(x, y, 1);
bar;
foo(a => 1, b => 2, 3);
end process;
-- Case
process is
begin
case x is
when 1 =>
null;
when 2 =>
null;
when 3 | 4 =>
null;
when others =>
null;
end case;
end process;
-- Next
process is
begin
next;
next when x = 5;
end process;
-- Signal assignment to aggregate
process is
type int_vec is array (natural range <>) of integer;
constant foo : int_vec := (1, 2, 3);
begin
( x, y, z ) <= foo;
end process;
-- Case statement range bug
process is
begin
case y is
when 1 =>
for i in integer'range loop
end loop;
end case;
end process;
-- 2008: all-sensitive process
process (all) is
begin
x <= y;
end process;
-- Variable assignment with aggregate target
process is
type int_vec is array (natural range <>) of integer;
variable v : int_vec(1 to 2);
variable a, b : integer;
begin
(a, b) := v; -- OK
end process;
-- Signal assignment with null transaction
process is
begin
x <= 1, null after 2 ns; -- OK
end process;
end architecture;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd | 15 | 22296 | -------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
use proc_sys_reset_v5_0_9.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_9.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_9.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_9.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_9.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
| gpl-3.0 |
nickg/nvc | test/regress/issue228.vhd | 1 | 261 | entity issue228 is
generic (G : integer range 0 to 3);
end entity issue228;
use std.textio.all;
architecture test of issue228 is
begin
process
begin
write(OUTPUT, integer'image(G) & LF);
wait;
end process;
end architecture test;
| gpl-3.0 |
nickg/nvc | test/sem/issue140.vhd | 5 | 991 | package protected_type_pkg is
type protected_t is protected
procedure proc;
end protected;
end package;
package body protected_type_pkg is
type protected_t is protected body
procedure proc is
begin
end;
end protected body;
end package body;
-------------------------------------------------------------------------------
use work.protected_type_pkg.protected_t;
entity e is
end entity;
architecture a of e is
procedure proc(variable prot : inout protected_t) is
begin
prot.proc; -- Was undefined
end;
begin
end architecture;
-------------------------------------------------------------------------------
use work.protected_type_pkg.protected_t;
package protected_user_pkg is
procedure proc(variable prot : inout protected_t);
end package;
package body protected_user_pkg is
procedure proc(variable prot : inout protected_t) is
begin
prot.proc; -- Was undefined
end;
end package body;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_slice.vhd | 19 | 4781 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity axi_datamover_slice is
generic (
C_DATA_WIDTH : Integer range 1 to 200 := 64
);
port (
ACLK : in std_logic;
ARESET : in std_logic;
-- Slave side
S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0);
S_VALID : in std_logic;
S_READY : out std_logic;
-- Master side
M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0);
M_VALID : out std_logic;
M_READY : in std_logic
);
end entity axi_datamover_slice;
architecture working of axi_datamover_slice is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes";
signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0);
signal s_ready_i : std_logic;
signal m_valid_i : std_logic;
signal areset_d : std_logic_vector (1 downto 0);
begin
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
areset_d(0) <= ARESET;
areset_d(1) <= areset_d(0);
end if;
end process;
-- Save payload data whenever we have a transaction on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (S_VALID = '1' and s_ready_i = '1') then
storage_data <= S_PAYLOAD_DATA;
else
storage_data <= storage_data;
end if;
end if;
end process;
M_PAYLOAD_DATA <= storage_data;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
process (ACLK) begin
if (ACLK'event and ACLK = '1') then
if (areset_d (1) = '1') then
m_valid_i <= '0';
elsif (S_VALID = '1') then
m_valid_i <= '1';
elsif (M_READY = '1') then
m_valid_i <= '0';
else
m_valid_i <= m_valid_i;
end if;
end if;
end process;
-- Slave Ready is either when Master side drives M_Ready or we have space in our storage data
s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0));
end working;
| gpl-3.0 |
nickg/nvc | test/regress/arith3.vhd | 5 | 304 | entity arith3 is
end entity;
architecture test of arith3 is
begin
process is
variable t : time;
variable i : integer;
begin
t := 120 ns;
i := sec / t;
report integer'image(i);
assert i = 8333333;
wait;
end process;
end architecture;
| gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/address_decoder.vhd | 8 | 22452 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0_3.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0_3.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
| gpl-3.0 |
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