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mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_dmask_data_stream_0_V.vhd | 2 | 4629 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_dmask_data_stream_0_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_dmask_data_stream_0_V_shiftReg;
architecture rtl of FIFO_image_filter_dmask_data_stream_0_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_dmask_data_stream_0_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_dmask_data_stream_0_V is
component FIFO_image_filter_dmask_data_stream_0_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_dmask_data_stream_0_V_shiftReg : FIFO_image_filter_dmask_data_stream_0_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_pkg.vhd | 13 | 6615 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI SG Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package axi_sg_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-- Convert boolean to a std_logic
function bo2int (value : boolean)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- AXI Response Values
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
-- Misc Constants
constant CMD_BASE_WIDTH : integer := 40;
constant SG_BTT_WIDTH : integer := 7;
constant SG_ADDR_LSB : integer := 6;
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST : integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
-- Descriptor field bits
constant DESC_STS_INTERR_BIT : integer := 28;
constant DESC_STS_SLVERR_BIT : integer := 29;
constant DESC_STS_DECERR_BIT : integer := 30;
constant DESC_STS_CMPLTD_BIT : integer := 31;
-- IOC Bit on descriptor update
-- Stored in LSB of TAG field then catinated on status word from primary
-- datamover (i.e. DESCTYPE & IOC & STATUS & Bytes Transferred).
constant DESC_IOC_TAG_BIT : integer := 32;
end axi_sg_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_sg_pkg is
-------------------------------------------------------------------------------
-- Boolean to Integer
-------------------------------------------------------------------------------
function bo2int ( value : boolean)
return integer is
variable value_int : integer;
begin
if(value)then
value_int := 1;
else
value_int := 0;
end if;
return value_int;
end function bo2int;
end package body axi_sg_pkg;
| gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_Block_proc.vhd | 2 | 17400 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Block_proc is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_4 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_5 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_6 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_7 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_8 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_9 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_10 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_11 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end;
architecture behav of image_filter_Block_proc is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_20 : BOOLEAN;
signal ap_sig_bdd_46 : BOOLEAN;
signal p_src_rows_V_fu_31_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_cols_V_fu_35_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_return_0_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_1_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_2_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_3_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_4_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_5_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_6_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_7_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_8_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_9_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_10_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_11_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_return_0_preg assign process. --
ap_return_0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_0_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_0_preg <= p_src_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_10_preg assign process. --
ap_return_10_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_10_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_10_preg <= p_src_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_11_preg assign process. --
ap_return_11_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_11_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_11_preg <= p_src_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_1_preg assign process. --
ap_return_1_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_1_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_1_preg <= p_src_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_2_preg assign process. --
ap_return_2_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_2_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_2_preg <= p_src_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_3_preg assign process. --
ap_return_3_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_3_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_3_preg <= p_src_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_4_preg assign process. --
ap_return_4_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_4_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_4_preg <= p_src_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_5_preg assign process. --
ap_return_5_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_5_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_5_preg <= p_src_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_6_preg assign process. --
ap_return_6_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_6_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_6_preg <= p_src_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_7_preg assign process. --
ap_return_7_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_7_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_7_preg <= p_src_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_8_preg assign process. --
ap_return_8_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_8_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_8_preg <= p_src_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_9_preg assign process. --
ap_return_9_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_9_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_9_preg <= p_src_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_46)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_return_0 assign process. --
ap_return_0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_rows_V_fu_31_p1, ap_return_0_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_0 <= p_src_rows_V_fu_31_p1;
else
ap_return_0 <= ap_return_0_preg;
end if;
end process;
-- ap_return_1 assign process. --
ap_return_1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_cols_V_fu_35_p1, ap_return_1_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_1 <= p_src_cols_V_fu_35_p1;
else
ap_return_1 <= ap_return_1_preg;
end if;
end process;
-- ap_return_10 assign process. --
ap_return_10_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_rows_V_fu_31_p1, ap_return_10_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_10 <= p_src_rows_V_fu_31_p1;
else
ap_return_10 <= ap_return_10_preg;
end if;
end process;
-- ap_return_11 assign process. --
ap_return_11_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_cols_V_fu_35_p1, ap_return_11_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_11 <= p_src_cols_V_fu_35_p1;
else
ap_return_11 <= ap_return_11_preg;
end if;
end process;
-- ap_return_2 assign process. --
ap_return_2_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_rows_V_fu_31_p1, ap_return_2_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_2 <= p_src_rows_V_fu_31_p1;
else
ap_return_2 <= ap_return_2_preg;
end if;
end process;
-- ap_return_3 assign process. --
ap_return_3_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_rows_V_fu_31_p1, ap_return_3_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_3 <= p_src_rows_V_fu_31_p1;
else
ap_return_3 <= ap_return_3_preg;
end if;
end process;
-- ap_return_4 assign process. --
ap_return_4_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_cols_V_fu_35_p1, ap_return_4_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_4 <= p_src_cols_V_fu_35_p1;
else
ap_return_4 <= ap_return_4_preg;
end if;
end process;
-- ap_return_5 assign process. --
ap_return_5_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_cols_V_fu_35_p1, ap_return_5_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_5 <= p_src_cols_V_fu_35_p1;
else
ap_return_5 <= ap_return_5_preg;
end if;
end process;
-- ap_return_6 assign process. --
ap_return_6_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_rows_V_fu_31_p1, ap_return_6_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_6 <= p_src_rows_V_fu_31_p1;
else
ap_return_6 <= ap_return_6_preg;
end if;
end process;
-- ap_return_7 assign process. --
ap_return_7_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_rows_V_fu_31_p1, ap_return_7_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_7 <= p_src_rows_V_fu_31_p1;
else
ap_return_7 <= ap_return_7_preg;
end if;
end process;
-- ap_return_8 assign process. --
ap_return_8_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_cols_V_fu_35_p1, ap_return_8_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_8 <= p_src_cols_V_fu_35_p1;
else
ap_return_8 <= ap_return_8_preg;
end if;
end process;
-- ap_return_9 assign process. --
ap_return_9_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_cols_V_fu_35_p1, ap_return_9_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_9 <= p_src_cols_V_fu_35_p1;
else
ap_return_9 <= ap_return_9_preg;
end if;
end process;
-- ap_sig_bdd_20 assign process. --
ap_sig_bdd_20_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_20 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_46 assign process. --
ap_sig_bdd_46_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_46 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
p_src_cols_V_fu_35_p1 <= cols(12 - 1 downto 0);
p_src_rows_V_fu_31_p1 <= rows(12 - 1 downto 0);
end behav;
| gpl-3.0 |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_wrdata_cntl.vhd | 6 | 90830 | -------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_fifo;
use axi_datamover_v5_1.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_datamover_wrdata_cntl;
architecture implementation of axi_datamover_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local constants
Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
Constant NUM_ZEROS_WIDTH : integer := 8;
Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- local signals
signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_byte_cntr : std_logic := '0';
signal lsig_incr_byte_cntr : std_logic := '0';
signal lsig_clr_byte_cntr : std_logic := '0';
signal lsig_end_of_cmd_reg : std_logic := '0';
signal lsig_eop_s_h_reg : std_logic := '0';
signal lsig_eop_reg : std_logic := '0';
signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
begin
-- Assign the outputs to the Write Status Controller
data2wsc_eop <= lsig_eop_reg and
not(sig_next_calc_error_reg);
data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
-- WRSTRB logic ------------------------------
--sig_strbgen_bytes <= (others => '1'); -- set to the max value
-- set the length to the max number of bytes per databeat
sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
STRBGEN_ADDR_SLICE_WIDTH)) ;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator used to generate the starting databeat
-- strobe value for soft shutdown case where the S2MM has to
-- flush out all of the transfers that have been committed
-- to the AXI Write address channel. Starting Strobes must
-- match the committed address offest for each transfer.
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes ,
strb_out => sig_sfhalt_next_strt_strb
);
-- Generate the WSTRB to use during soft shutdown
sig_halt_strb <= sig_strt_strb_reg
When (sig_first_dbeat = '1' or
sig_single_dbeat = '1')
Else (others => '1');
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the Indeterminate BTT case. Strobes come from the Stream
-- input from the Indeterminate BTT module during normal operation.
-- However, during soft shutdown, those strobes become unpredictable
-- so generated strobes have to be used.
data2skid_wstrb <= sig_halt_strb
When (sig_halt_reg = '1')
Else s2mm_strm_wstrb;
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and -- MMap is accepting the xfers
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- TLAST Error housekeeping for Indeterminate BTT Mode
-- There is no Underrun/overrun in Stroe and Forward mode
sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG_FLOP
--
-- Process Description:
-- Register the End of Packet marker.
--
-------------------------------------------------------------
IMP_EOP_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_end_of_cmd_reg <= '0';
lsig_eop_reg <= '0';
Elsif (sig_good_strm_dbeat = '1') Then
lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
s2mm_strm_wlast;
lsig_eop_reg <= s2mm_strm_eop;
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_REG_FLOP;
----- Byte Counter Logic -----------------------------------------------
-- The Byte counter reflects the actual byte count received on the
-- Stream input for each parent command loaded into the S2MM command
-- FIFO. Thus it counts input bytes until the command complete qualifier
-- is set and the TLAST input from the Stream input.
lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
not(sig_good_strm_dbeat); -- immediately after the previous one finished.
lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
sig_good_strm_dbeat; -- immediately after the previous one finished.
lsig_incr_byte_cntr <= sig_good_strm_dbeat;
lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_byte_cntr = '1') then
lsig_byte_cntr <= (others => '0');
elsif (lsig_ld_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr_incr_value;
elsif (lsig_incr_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
end generate GEN_INDET_BTT;
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| gpl-3.0 |
davidhorrocks/1541UltimateII | fpga/1541/vhdl_source/c1541_drive.vhd | 4 | 10338 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity c1541_drive is
generic (
g_audio_tag : std_logic_vector(7 downto 0) := X"01";
g_floppy_tag : std_logic_vector(7 downto 0) := X"02";
g_cpu_tag : std_logic_vector(7 downto 0) := X"04";
g_audio : boolean := true;
g_audio_div : integer := 2222; -- 22500 Hz (from 50 MHz)
g_audio_base : unsigned(27 downto 0) := X"0030000";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
reset : in std_logic;
drive_stop : in std_logic;
-- slave port on io bus
io_req : in t_io_req;
io_resp : out t_io_resp;
-- master port on memory bus
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- serial bus pins
atn_o : out std_logic; -- open drain
atn_i : in std_logic;
clk_o : out std_logic; -- open drain
clk_i : in std_logic;
data_o : out std_logic; -- open drain
data_i : in std_logic;
iec_reset_n : in std_logic;
c64_reset_n : in std_logic;
-- LED
act_led_n : out std_logic;
motor_led_n : out std_logic;
dirty_led_n : out std_logic;
-- audio out
audio_sample : out signed(12 downto 0) );
end c1541_drive;
architecture structural of c1541_drive is
signal cpu_clock_en : std_logic;
signal drv_clock_en : std_logic;
signal iec_reset_o : std_logic;
signal param_write : std_logic;
signal param_ram_en : std_logic;
signal param_addr : std_logic_vector(10 downto 0);
signal param_wdata : std_logic_vector(7 downto 0);
signal param_rdata : std_logic_vector(7 downto 0);
signal do_track_out : std_logic;
signal do_track_in : std_logic;
signal do_head_bang : std_logic;
signal en_hum : std_logic;
signal en_slip : std_logic;
signal use_c64_reset : std_logic;
signal floppy_inserted : std_logic := '0';
signal bank_is_ram : std_logic_vector(7 downto 0);
signal power : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal track : std_logic_vector(6 downto 0);
signal track_is_0 : std_logic;
signal drive_address : std_logic_vector(1 downto 0) := "00";
signal write_prot_n : std_logic := '1';
signal drv_reset : std_logic := '1';
signal disk_rdata : std_logic_vector(7 downto 0);
signal disk_wdata : std_logic_vector(7 downto 0);
signal drive_stop_i : std_logic;
signal stop_on_freeze : std_logic;
signal mem_req_cpu : t_mem_req;
signal mem_resp_cpu : t_mem_resp;
signal mem_req_flop : t_mem_req;
signal mem_resp_flop : t_mem_resp;
signal mem_req_snd : t_mem_req := c_mem_req_init;
signal mem_resp_snd : t_mem_resp;
signal count : unsigned(7 downto 0) := X"00";
signal led_intensity : unsigned(1 downto 0);
begin
drive_stop_i <= drive_stop and stop_on_freeze;
i_timing: entity work.c1541_timing
port map (
clock => clock,
reset => reset,
use_c64_reset=> use_c64_reset,
c64_reset_n => c64_reset_n,
iec_reset_n => iec_reset_n,
iec_reset_o => iec_reset_o,
drive_stop => drive_stop_i,
drv_clock_en => drv_clock_en, -- 1/12.5 (4 MHz)
cpu_clock_en => cpu_clock_en ); -- 1/50 (1 MHz)
i_cpu: entity work.cpu_part_1541
generic map (
g_tag => g_cpu_tag,
g_ram_base => g_ram_base )
port map (
clock => clock,
clock_en => cpu_clock_en,
reset => drv_reset,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
-- trace data
cpu_pc => open, --cpu_pc_1541,
-- configuration
bank_is_ram => bank_is_ram,
-- memory interface
mem_req => mem_req_cpu,
mem_resp => mem_resp_cpu,
-- drive pins
power => power,
drive_address => drive_address,
write_prot_n => write_prot_n,
motor_on => motor_on,
mode => mode,
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
track_is_0 => track_is_0,
drv_rdata => disk_rdata,
drv_wdata => disk_wdata,
-- other
act_led => act_led_n );
i_flop: entity work.floppy
generic map (
g_tag => g_floppy_tag )
port map (
sys_clock => clock,
drv_clock_en => drv_clock_en, -- resulting in 4 MHz
drv_reset => drv_reset,
-- signals from MOS 6522 VIA
motor_on => motor_on,
mode => mode,
write_prot_n => write_prot_n,
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
read_data => disk_rdata,
write_data => disk_wdata,
track => track,
track_is_0 => track_is_0,
---
cpu_write => param_write,
cpu_ram_en => param_ram_en,
cpu_addr => param_addr,
cpu_wdata => param_wdata,
cpu_rdata => param_rdata,
---
floppy_inserted => floppy_inserted,
do_track_out => do_track_out,
do_track_in => do_track_in,
do_head_bang => do_head_bang,
en_hum => en_hum,
en_slip => en_slip,
---
mem_req => mem_req_flop,
mem_resp => mem_resp_flop );
r_snd: if g_audio generate
i_snd: entity work.floppy_sound
generic map (
g_tag => g_audio_tag,
rate_div => g_audio_div, -- 22050 Hz
sound_base => g_audio_base(27 downto 16),
motor_hum_addr => X"0000",
flop_slip_addr => X"1200",
track_in_addr => X"2400",
track_out_addr => X"2C00",
head_bang_addr => X"3480",
motor_len => 4410,
track_in_len => X"0800", -- ~100 ms;
track_out_len => X"0880", -- ~100 ms;
head_bang_len => X"0880" ) -- ~100 ms;
port map (
clock => clock, -- 50 MHz
reset => drv_reset,
do_trk_out => do_track_out,
do_trk_in => do_track_in,
do_head_bang => do_head_bang,
en_hum => en_hum,
en_slip => en_slip,
-- memory interface
mem_req => mem_req_snd,
mem_resp => mem_resp_snd,
-- audio
sample_out => audio_sample );
end generate;
i_regs: entity work.drive_registers
generic map (
g_audio_base => g_audio_base,
g_ram_base => g_ram_base )
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
param_write => param_write,
param_ram_en => param_ram_en,
param_addr => param_addr,
param_wdata => param_wdata,
param_rdata => param_rdata,
iec_reset_o => iec_reset_o,
use_c64_reset => use_c64_reset,
power => power,
drv_reset => drv_reset,
drive_address => drive_address,
floppy_inserted => floppy_inserted,
write_prot_n => write_prot_n,
bank_is_ram => bank_is_ram,
dirty_led_n => dirty_led_n,
stop_on_freeze => stop_on_freeze,
track => track,
mode => mode,
motor_on => motor_on );
-- memory arbitration
i_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 3,
g_registered => false )
port map (
clock => clock,
reset => reset,
reqs(0) => mem_req_flop,
reqs(1) => mem_req_cpu,
reqs(2) => mem_req_snd,
resps(0) => mem_resp_flop,
resps(1) => mem_resp_cpu,
resps(2) => mem_resp_snd,
req => mem_req,
resp => mem_resp );
process(clock)
variable led_int : unsigned(7 downto 0);
begin
if rising_edge(clock) then
count <= count + 1;
if count=X"00" then
motor_led_n <= '0'; -- on
end if;
led_int := led_intensity & led_intensity & led_intensity & led_intensity;
if count=led_int then
motor_led_n <= '1'; -- off
end if;
end if;
end process;
led_intensity <= "00" when power='0' else
"01" when floppy_inserted='0' else
"10" when motor_on='0' else
"11";
end architecture;
| gpl-3.0 |
davidhorrocks/1541UltimateII | fpga/ip/video/vhdl_source/phase_detector.vhd | 5 | 2122 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity phase_detector is
port (
n : in unsigned(11 downto 0);
pll_clock : in std_logic;
h_sync : in std_logic;
mute : in std_logic;
reference : out std_logic;
pulse_level : out std_logic;
pulse_enable: out std_logic;
up : out std_logic;
down : out std_logic;
analog : out std_logic );
end phase_detector;
architecture gideon of phase_detector is
signal div_count : unsigned(n'range) := (others => '0');
signal divided : std_logic;
signal h_latch : std_logic;
signal ref_latch : std_logic;
signal release : std_logic;
signal up_i : std_logic;
signal down_i : std_logic;
begin
reference <= divided;
process(pll_clock)
begin
if rising_edge(pll_clock) then
if div_count = 0 then
div_count <= n;
divided <= '1';
else
div_count <= div_count - 1;
if div_count = ('0' & n(11 downto 1)) then
divided <= '0';
end if;
end if;
end if;
end process;
process(h_sync, release)
begin
if release='1' then
h_latch <= '0';
elsif rising_edge(h_sync) then
h_latch <= '1';
end if;
end process;
process(divided, release)
begin
if release='1' then
ref_latch <= '0';
elsif rising_edge(divided) then
ref_latch <= '1';
end if;
end process;
up_i <= h_latch and not ref_latch;
down_i <= ref_latch and not h_latch;
release <= h_latch and ref_latch;
pulse_enable <= (up_i or down_i) and not mute;
pulse_level <= up_i;
analog <= '0' when (down_i='1' and up_i='0' and mute='0') else
'1' when (up_i='1' and down_i='0' and mute='0') else
'Z';
up <= up_i;
down <= down_i;
end gideon;
| gpl-3.0 |
freecores/gpib_controller | vhdl/src/gpib/SecAddrSaver.vhd | 1 | 1875 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: SecAddrSaver
-- Date:2011-11-11
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SecAddrSaver is
port (
reset : in std_logic;
------------------- gpib ----------------------
TADS : in std_logic;
TPAS : in std_logic;
LADS : in std_logic;
LPAS : in std_logic;
MSA_Dec : in std_logic;
DI : in std_logic_vector(4 downto 0);
currentSecAddr : out std_logic_vector(4 downto 0)
);
end SecAddrSaver;
architecture arch of SecAddrSaver is
signal goToSecAddressed : std_logic;
begin
goToSecAddressed <= MSA_Dec and ((TADS and TPAS) or (LADS and LPAS));
-- save secondary address
process (reset, goToSecAddressed) begin
if(reset = '1') then
currentSecAddr <= (others => '0');
elsif rising_edge(goToSecAddressed) then
currentSecAddr <= DI(4 downto 0);
end if;
end process;
end arch;
| gpl-3.0 |
dhmeves/ece-485 | ece-485-project-2/two_to_one_mux_1_bit.vhd | 1 | 344 | library IEEE;
use ieee.std_logic_1164.all;
entity two_to_one_mux_1_bit is
port(
a, b : in std_logic;
sel : in std_logic;
output : out std_logic
);
end entity two_to_one_mux_1_bit;
architecture behav of two_to_one_mux_1_bit is
begin
--output <= (a and (not sel)) or (b and sel);
output <= a when (sel = '0') else b;
end behav; | gpl-3.0 |
freecores/gpib_controller | vhdl/src/common/gpibComponents.vhd | 1 | 18572 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: components
-- Date: 23:15 10/12/2011
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package gpibComponents is
component if_func_AH is
port(
-- device inputs
clk : in std_logic; -- clock
pon : in std_logic; -- power on
rdy : in std_logic; -- ready for next message
tcs : in std_logic; -- take control synchronously
-- state inputs
LACS : in std_logic; -- listener active state
LADS : in std_logic; -- listener addressed state
-- interface inputs
ATN : in std_logic; -- attention
DAV : in std_logic; -- data accepted
-- interface outputs
RFD : out std_logic; -- ready for data
DAC : out std_logic; -- data accepted
-- reported state
ANRS : out std_logic; -- acceptor not ready state
ACDS : out std_logic -- accept data state
);
end component;
component if_func_SH is
port(
-- device inputs
clk : in std_logic; -- clock
-- settingd
T1 : in std_logic_vector (7 downto 0);
-- local commands
pon : in std_logic; -- power on
nba : in std_logic; -- new byte available
-- state inputs
TACS : in std_logic; -- talker active state
SPAS : in std_logic; -- seriall poll active state
CACS : in std_logic; -- controller active state
CTRS : in std_logic; -- controller transfer state
-- interface inputs
ATN : in std_logic; -- attention
DAC : in std_logic; -- data accepted
RFD : in std_logic; -- ready for data
-- remote instructions
DAV : out std_logic; -- data address valid
-- device outputs
wnc : out std_logic; -- wait for new cycle
-- reported states
STRS : out std_logic; -- source transfer state
SDYS : out std_logic -- source delay state
);
end component;
component if_func_L_LE is
port(
-- clock
clk : in std_logic; -- clock
-- function settings
isLE : in std_logic;
-- local commands
pon : in std_logic; -- power on
ltn : in std_logic; -- listen
lun : in std_logic; -- local unlisten
lon : in std_logic; -- listen only
-- state inputs
ACDS : in std_logic; -- accept data state (AH)
CACS : in std_logic; -- controller active state (C)
TPAS : in std_logic; -- talker primary address state (T)
-- remote commands
ATN : in std_logic; -- attention
IFC : in std_logic; -- interface clear
MLA : in std_logic; -- my listen address
MTA : in std_logic; -- my talk address
UNL : in std_logic; -- unlisten
PCG : in std_logic; -- primary command group
MSA : in std_logic; -- my secondary address
-- reported states
LACS : out std_logic; -- listener active state
LADS : out std_logic; -- listener addressed state
LPAS : out std_logic -- listener primary addressed state
;debug1 : out std_logic
);
end component;
component if_func_T_TE is
port(
-- clock
clk : in std_logic; -- clock
-- function settings
isTE : in std_logic;
-- local instruction inputs
pon : in std_logic; -- power on
ton : in std_logic; -- talk only
endOf : in std_logic; -- end of byte string
-- state inputs
ACDS : in std_logic; -- accept data state (AH)
APRS : in std_logic; -- affirmative poll response
LPAS : in std_logic; -- listener primary state (LE)
-- remote instruction inputs
ATN : in std_logic; -- attention
IFC : in std_logic; -- interface clear
SPE : in std_logic; -- serial poll enable
SPD : in std_logic; -- serial poll disable
MTA : in std_logic; -- my talk address
OTA : in std_logic; -- other talk address
MLA : in std_logic; -- my listen address
OSA : in std_logic; -- other secondary address
MSA : in std_logic; -- my secondary address
PCG : in std_logic; -- primary command group
-- remote instruction outputs
END_OF : out std_logic; -- end of data
RQS : out std_logic; -- data accepted
DAB : out std_logic; -- data byte
EOS : out std_logic; -- end of string
STB : out std_logic; -- status byte
-- local instruction outputs
tac : out std_logic; -- talker active
-- reported states
SPAS : out std_logic; -- serial poll active state
TPAS : out std_logic; -- transmitter active state
TADS : out std_logic; -- talker addressed state
TACS : out std_logic -- talker active state
);
end component;
component if_func_C is
port(
-- device inputs
clk : in std_logic; -- clock
pon : in std_logic; -- power on
gts : in std_logic; -- go to standby
rpp : in std_logic; -- request parallel poll
tcs : in std_logic; -- take control synchronously
tca : in std_logic; -- take control asynchronously
sic : in std_logic; -- send interface clear
rsc : in std_logic; -- request system control
sre : in std_logic; -- send remote enable
-- state inputs
TADS : in std_logic; -- talker addressed state (T or TE)
ACDS : in std_logic; -- accept data state (AH)
ANRS : in std_logic; -- acceptor not ready state (AH)
STRS : in std_logic; -- source transfer state (SH)
SDYS : in std_logic; -- source delay state (SH)
-- command inputs
ATN_in : in std_logic; -- attention
IFC_in : in std_logic; -- interface clear
TCT_in : in std_logic; -- take control
SRQ_in : in std_logic; -- service request
-- command outputs
ATN_out : out std_logic; -- attention
IFC_out : out std_logic; -- interface clear
TCT_out : out std_logic; -- take control
IDY_out : out std_logic; -- identify
REN_out : out std_logic; -- remote enable
-- reported states
CACS : out std_logic; -- controller active state
CTRS : out std_logic; -- controller transfer state
CSBS : out std_logic; -- controller standby state
CPPS : out std_logic; -- controller parallel poll state
CSRS : out std_logic; -- controller service requested state
SACS : out std_logic -- system control active state
);
end component;
component if_func_DC is
port(
-- device inputs
clk : in std_logic; -- clock
-- state inputs
LADS : in std_logic; -- listener addressed state (L or LE)
ACDS : in std_logic; -- accept data state (AH)
-- instructions
DCL : in std_logic; -- my listen address
SDC : in std_logic; -- unlisten
-- local instructions
clr : out std_logic -- clear device
);
end component;
component if_func_DT is
port(
-- device inputs
clk : in std_logic; -- clock
-- state inputs
LADS : in std_logic; -- listener addressed state (L or LE)
ACDS : in std_logic; -- accept data state (AH)
-- instructions
GET : in std_logic; -- group execute trigger
-- local instructions
trg : out std_logic -- trigger
);
end component;
component if_func_PP is
port(
-- device inputs
clk : in std_logic; -- clock
-- settings
lpeUsed : std_logic;
fixedPpLine : in std_logic_vector (2 downto 0);
-- local commands
pon : in std_logic; -- power on
lpe : in std_logic; -- local poll enable
ist : in std_logic; -- individual status
-- state inputs
ACDS : in std_logic; -- accept data state
LADS : in std_logic; -- listener address state (L or LE)
-- data input
dio_data : in std_logic_vector(3 downto 0); -- byte from data lines
-- remote command inputs
IDY : in std_logic; -- identify
PPE : in std_logic; -- parallel poll enable
PPD : in std_logic; -- parallel poll disable
PPC : in std_logic; -- parallel poll configure
PPU : in std_logic; -- parallel poll unconfigure
PCG : in std_logic; -- primary command group
-- remote command outputs
PPR : out std_logic; -- paralel poll response
-- PPR command data
ppBitValue : out std_logic; -- bit value
ppLineNumber : out std_logic_vector (2 downto 0);
-- reported states
PPAS : out std_logic -- parallel poll active state
);
end component;
component if_func_RL is
port(
-- device inputs
clk : in std_logic; -- clock
pon : in std_logic; -- power on
rtl : in std_logic; -- return to local
-- state inputs
ACDS : in std_logic; -- listener active state (AH)
LADS : in std_logic; -- listener addressed state (L or LE)
-- instructions
REN : in std_logic; -- remote enable
LLO : in std_logic; -- local lockout
MLA : in std_logic; -- my listen address
GTL : in std_logic; -- go to local
-- reported state
LOCS : out std_logic; -- local state
LWLS : out std_logic -- local with lockout state
);
end component;
component if_func_SR is
port(
-- device inputs
clk : in std_logic; -- clock
pon : in std_logic; -- power on
rsv : in std_logic; -- service request
-- state inputs
SPAS : in std_logic; -- serial poll active state (T or TE)
-- output instructions
SRQ : out std_logic; -- service request
-- reported states
APRS : out std_logic -- affirmative poll response state
);
end component;
component commandEcoder is
port (
-- data
data : in std_logic_vector (7 downto 0);
-- status byte
status_byte : in std_logic_vector (7 downto 0);
-- PPR command data
ppBitValue : in std_logic;
ppLineNumber : in std_logic_vector (2 downto 0);
-- func states
APRS : in std_logic; -- affirmative poll response state
CACS : in std_logic; -- controller active state (C)
-- commands
ATN : in std_logic;
END_OF : in std_logic;
IDY : in std_logic;
DAC : in std_logic;
RFD : in std_logic;
DAV : in std_logic;
IFC : in std_logic;
REN : in std_logic;
SRQ : in std_logic; -- request for service
DAB : in std_logic;
EOS : in std_logic;
RQS : in std_logic; -- part of STB
STB : in std_logic;
TCT : in std_logic;
PPR : in std_logic;
-------------------------------------------
-- data lines -----------------------------
-------------------------------------------
DO : out std_logic_vector (7 downto 0);
output_valid : out std_logic;
-------------------------------------------
-- control lines --------------------------
-------------------------------------------
-- DAV line
DAV_line : out std_logic;
-- NRFD line
NRFD_line : out std_logic;
-- NDAC line
NDAC_line : out std_logic;
-- ATN line
ATN_line : out std_logic;
-- EOI line
EOI_line : out std_logic;
-- SRQ line
SRQ_line : out std_logic;
-- IFC line
IFC_line : out std_logic;
-- REN line
REN_line : out std_logic
);
end component;
component commandDecoder is
port (
-------------------------------------------
-- data lines -----------------------------
-------------------------------------------
DI : in std_logic_vector (7 downto 0);
-------------------------------------------
-- control lines --------------------------
-------------------------------------------
-- DAV line
DAV_line : in std_logic;
-- NRFD line
NRFD_line : in std_logic;
-- NDAC line
NDAC_line : in std_logic;
-- ATN line
ATN_line : in std_logic;
-- EOI line
EOI_line : in std_logic;
-- SRQ line
SRQ_line : in std_logic;
-- IFC line
IFC_line : in std_logic;
-- REN line
REN_line : in std_logic;
-------------------------------------------
-- internal settiongs ---------------------
-------------------------------------------
-- eos mark
eosMark : in std_logic_vector (7 downto 0);
-- eos used
eosUsed : in std_logic;
-- my listen address
myListAddr : in std_logic_vector (4 downto 0);
-- my talk address
myTalkAddr : in std_logic_vector (4 downto 0);
-- secondary address detected
secAddrDetected : in std_logic;
-------------------------------------------
-- internal states ------------------------
-------------------------------------------
-- serial poll active state (T or TE)
SPAS : in std_logic;
-------------------------------------------
-- single line commands -------------------
-------------------------------------------
-- attention
ATN : out std_logic;
-- data accepted
DAC : out std_logic;
-- data valid
DAV : out std_logic;
-- end
END_c : out std_logic;
-- identify
IDY : out std_logic;
-- interface clear
IFC : out std_logic;
-- remote enable
REN : out std_logic;
-- ready for data
RFD : out std_logic;
-- service request
SRQ : out std_logic;
-------------------------------------------
-- multi line commands --------------------
-------------------------------------------
-- addressed command group
ACG : out std_logic;
-- data byte
DAB : out std_logic;
-- device clear
DCL : out std_logic;
-- end of string
EOS : out std_logic;
-- group execute trigger
GET : out std_logic;
-- go to local
GTL : out std_logic;
-- listen address group
LAG : out std_logic;
-- local lockout
LLO : out std_logic;
-- my listen address
MLA : out std_logic;
-- my talk address
MTA : out std_logic;
-- my secondary address
MSA : out std_logic;
-- null byte
NUL : out std_logic;
-- other secondary address
OSA : out std_logic;
-- other talk address
OTA : out std_logic;
-- primary command group
PCG : out std_logic;
-- parallel poll configure
PPC : out std_logic;
-- parallel poll enable
PPE : out std_logic;
-- parallel poll disable
PPD : out std_logic;
-- parallel poll response
PPR : out std_logic;
-- parallel poll unconfigure
PPU : out std_logic;
-- request service
RQS : out std_logic;
-- secondary command group
SCG : out std_logic;
-- selected device clear
SDC : out std_logic;
-- serial poll disable
SPD : out std_logic;
-- serial poll enable
SPE : out std_logic;
-- status byte
STB : out std_logic;
-- talk address group
TAG : out std_logic;
-- take control
TCT : out std_logic;
-- universal command group
UCG : out std_logic;
-- unlisten
UNL : out std_logic;
-- untalk
UNT : out std_logic
);
end component;
component SecondaryAddressDecoder is
port (
-- secondary address mask
secAddrMask : in std_logic_vector (31 downto 0);
-- data input
DI : in std_logic_vector (4 downto 0);
-- secondary address detected
secAddrDetected : out std_logic
);
end component;
component SecAddrSaver is
port (
reset : in std_logic;
------------------- gpib ----------------------
TADS : in std_logic;
TPAS : in std_logic;
LADS : in std_logic;
LPAS : in std_logic;
MSA_Dec : in std_logic;
DI : in std_logic_vector(4 downto 0);
currentSecAddr : out std_logic_vector(4 downto 0)
);
end component;
component gpibInterface is port (
clk : in std_logic;
reset : std_logic;
-- application interface
isLE : in std_logic;
isTE : in std_logic;
lpeUsed : in std_logic;
fixedPpLine : in std_logic_vector (2 downto 0);
eosUsed : in std_logic;
eosMark : in std_logic_vector (7 downto 0);
myListAddr : in std_logic_vector (4 downto 0);
myTalkAddr : in std_logic_vector (4 downto 0);
secAddrMask : in std_logic_vector (31 downto 0);
data : in std_logic_vector (7 downto 0);
status_byte : in std_logic_vector (7 downto 0);
T1 : in std_logic_vector (7 downto 0);
-- local commands to interface
rdy : in std_logic; -- ready for next message (AH)
nba : in std_logic; -- new byte available (SH)
ltn : in std_logic; -- listen (L, LE)
lun : in std_logic; -- local unlisten (L, LE)
lon : in std_logic; -- listen only (L, LE)
ton : in std_logic; -- talk only (T, TE)
endOf : in std_logic; -- end of byte string (T, TE)
gts : in std_logic; -- go to standby (C)
rpp : in std_logic; -- request parallel poll (C)
tcs : in std_logic; -- take control synchronously (C, AH)
tca : in std_logic; -- take control asynchronously (C)
sic : in std_logic; -- send interface clear (C)
rsc : in std_logic; -- request system control (C)
sre : in std_logic; -- send remote enable (C)
rtl : in std_logic; -- return to local (RL)
rsv : in std_logic; -- request service (SR)
ist : in std_logic; -- individual status (PP)
lpe : in std_logic; -- local poll enable (PP)
-- local commands from interface
dvd : out std_logic; -- data valid (AH)
wnc : out std_logic; -- wait for new cycle (SH)
tac : out std_logic; -- talker active (T, TE)
lac : out std_logic; -- listener active (L, LE)
cwrc : out std_logic; -- controller write commands
cwrd : out std_logic; -- controller write data
clr : out std_logic; -- clear device (DC)
trg : out std_logic; -- trigger device (DT)
atl : out std_logic; -- addressed to listen (T or TE)
att : out std_logic; -- addressed to talk(L or LE)
mla : out std_logic; -- my listen addres decoded (L or LE)
lsb : out std_logic; -- last byte
spa : out std_logic; -- seriall poll active
ppr : out std_logic; -- parallel poll ready
sreq : out std_logic; -- service requested
isLocal : out std_logic; -- device is local controlled
currentSecAddr : out std_logic_vector (4 downto 0); -- current sec addr
-- interface signals
DI : in std_logic_vector (7 downto 0);
DO : out std_logic_vector (7 downto 0);
output_valid : out std_logic;
-- attention
ATN_in : in std_logic;
ATN_out : out std_logic;
-- data valid
DAV_in : in std_logic;
DAV_out : out std_logic;
-- not ready for data
NRFD_in : in std_logic;
NRFD_out : out std_logic;
-- no data accepted
NDAC_in : in std_logic;
NDAC_out : out std_logic;
-- end or identify
EOI_in : in std_logic;
EOI_out : out std_logic;
-- service request
SRQ_in : in std_logic;
SRQ_out : out std_logic;
-- interface clear
IFC_in : in std_logic;
IFC_out : out std_logic;
-- remote enable
REN_in : in std_logic;
REN_out : out std_logic
;debug1 : out std_logic
);
end component;
end gpibComponents; | gpl-3.0 |
freecores/gpib_controller | vhdl/src/gpib_helper/SinglePulseGenerator.vhd | 1 | 1909 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: SinglePulseGenerator
-- Date:2011-11-10
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.utilPkg.all;
entity SinglePulseGenerator is
generic (
WIDTH : integer := 3
);
port (
reset : in std_logic;
clk : in std_logic;
t_in: in std_logic;
t_out : out std_logic;
pulse : out std_logic
);
end SinglePulseGenerator;
architecture arch of SinglePulseGenerator is
signal rcount : integer range 0 to WIDTH;
signal i_t_out : std_logic;
begin
pulse <= to_stdl(t_in /= i_t_out);
t_out <= i_t_out;
-- buffer reset generator
process (reset, clk, t_in) begin
if reset = '1' then
i_t_out <= t_in;
rcount <= 0;
elsif rising_edge(clk) then
if t_in /= i_t_out then
rcount <= rcount + 1;
if rcount = WIDTH then
rcount <= 0;
i_t_out <= t_in;
end if;
end if;
end if;
end process;
end arch;
| gpl-3.0 |
pavsa/hackrf-spectrum-analyzer | src/hackrf-sweep/lib/hackrf/firmware/cpld/sgpio_if/top_tb.vhd | 19 | 3604 | --
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top_tb IS
END top_tb;
ARCHITECTURE behavior OF top_tb IS
COMPONENT top
PORT(
HOST_DATA : INOUT std_logic_vector(7 downto 0);
HOST_CAPTURE : OUT std_logic;
HOST_DISABLE : IN std_logic;
HOST_DIRECTION : IN std_logic;
HOST_DECIM_SEL : IN std_logic_vector(2 downto 0);
DA : IN std_logic_vector(7 downto 0);
DD : OUT std_logic_vector(9 downto 0);
CODEC_CLK : IN std_logic;
CODEC_X2_CLK : IN std_logic
);
END COMPONENT;
--Inputs
signal DA : std_logic_vector(7 downto 0) := (others => '0');
signal CODEC_CLK : std_logic := '0';
signal CODEC_X2_CLK : std_logic := '0';
signal HOST_DISABLE : std_logic := '1';
signal HOST_DIRECTION : std_logic := '0';
signal HOST_DECIM_SEL : std_logic_vector(2 downto 0) := "010";
--BiDirs
signal HOST_DATA : std_logic_vector(7 downto 0);
--Outputs
signal DD : std_logic_vector(9 downto 0);
signal HOST_CAPTURE : std_logic;
begin
uut: top PORT MAP (
HOST_DATA => HOST_DATA,
HOST_CAPTURE => HOST_CAPTURE,
HOST_DISABLE => HOST_DISABLE,
HOST_DIRECTION => HOST_DIRECTION,
HOST_DECIM_SEL => HOST_DECIM_SEL,
DA => DA,
DD => DD,
CODEC_CLK => CODEC_CLK,
CODEC_X2_CLK => CODEC_X2_CLK
);
clk_process :process
begin
CODEC_CLK <= '1';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
CODEC_CLK <= '0';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
end process;
adc_proc: process
begin
wait until rising_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000000";
wait until falling_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000001";
end process;
sgpio_proc: process
begin
HOST_DATA <= (others => 'Z');
HOST_DIRECTION <= '0';
HOST_DISABLE <= '1';
wait for 135 ns;
HOST_DISABLE <= '0';
wait for 1000 ns;
HOST_DISABLE <= '1';
wait for 100 ns;
HOST_DIRECTION <= '1';
wait for 100 ns;
HOST_DISABLE <= '0';
for i in 0 to 10 loop
HOST_DATA <= (others => '0');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
HOST_DATA <= (others => '1');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
end loop;
wait;
end process;
end;
| gpl-3.0 |
freecores/gpib_controller | vhdl/src/gpib/commandDecoder.vhd | 1 | 8375 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: commandDecoder
-- Date:2011-10-07
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.utilPkg.all;
entity commandDecoder is
port (
-------------------------------------------
-- data lines -----------------------------
-------------------------------------------
DI : in std_logic_vector (7 downto 0);
-------------------------------------------
-- control lines --------------------------
-------------------------------------------
-- DAV line
DAV_line : in std_logic;
-- NRFD line
NRFD_line : in std_logic;
-- NDAC line
NDAC_line : in std_logic;
-- ATN line
ATN_line : in std_logic;
-- EOI line
EOI_line : in std_logic;
-- SRQ line
SRQ_line : in std_logic;
-- IFC line
IFC_line : in std_logic;
-- REN line
REN_line : in std_logic;
-------------------------------------------
-- internal settiongs ---------------------
-------------------------------------------
-- eos mark
eosMark : in std_logic_vector (7 downto 0);
-- eos used
eosUsed : in std_logic;
-- my listen address
myListAddr : in std_logic_vector (4 downto 0);
-- my talk address
myTalkAddr : in std_logic_vector (4 downto 0);
-- secondary address detected
secAddrDetected : in std_logic;
-------------------------------------------
-- internal states ------------------------
-------------------------------------------
-- serial poll active state (T or TE)
SPAS : in std_logic;
-------------------------------------------
-- single line commands -------------------
-------------------------------------------
-- attention
ATN : out std_logic;
-- data accepted
DAC : out std_logic;
-- data valid
DAV : out std_logic;
-- end
END_c : out std_logic;
-- identify
IDY : out std_logic;
-- interface clear
IFC : out std_logic;
-- remote enable
REN : out std_logic;
-- ready for data
RFD : out std_logic;
-- service request
SRQ : out std_logic;
-------------------------------------------
-- multi line commands --------------------
-------------------------------------------
-- addressed command group
ACG : out std_logic;
-- data byte
DAB : out std_logic;
-- device clear
DCL : out std_logic;
-- end of string
EOS : out std_logic;
-- group execute trigger
GET : out std_logic;
-- go to local
GTL : out std_logic;
-- listen address group
LAG : out std_logic;
-- local lockout
LLO : out std_logic;
-- my listen address
MLA : out std_logic;
-- my talk address
MTA : out std_logic;
-- my secondary address
MSA : out std_logic;
-- null byte
NUL : out std_logic;
-- other secondary address
OSA : out std_logic;
-- other talk address
OTA : out std_logic;
-- primary command group
PCG : out std_logic;
-- parallel poll configure
PPC : out std_logic;
-- parallel poll enable
PPE : out std_logic;
-- parallel poll disable
PPD : out std_logic;
-- parallel poll response
PPR : out std_logic;
-- parallel poll unconfigure
PPU : out std_logic;
-- request service
RQS : out std_logic;
-- secondary command group
SCG : out std_logic;
-- selected device clear
SDC : out std_logic;
-- serial poll disable
SPD : out std_logic;
-- serial poll enable
SPE : out std_logic;
-- status byte
STB : out std_logic;
-- talk address group
TAG : out std_logic;
-- take control
TCT : out std_logic;
-- universal command group
UCG : out std_logic;
-- unlisten
UNL : out std_logic;
-- untalk
UNT : out std_logic
);
end commandDecoder;
architecture arch of commandDecoder is
signal ATN_int, IDY_int : std_logic;
signal SCG_int, MSA_int, TAG_int, MTA_int, ACG_int, UCG_int,
LAG_int, STB_int : std_logic;
begin
--------------------------------------
-- single line
--------------------------------------
ATN_int <= ATN_line;
ATN <= ATN_int;
----------------------
DAC <= not NDAC_line;
----------------------
DAV <= DAV_line;
----------------------
END_c <= not ATN_line and EOI_line;
----------------------
IDY_int <= ATN_line and EOI_line;
IDY <= IDY_int;
----------------------
IFC <= IFC_line;
----------------------
REN <= REN_line;
----------------------
RFD <= not NRFD_line;
----------------------
SRQ <= SRQ_line;
---------------------------------------
-- multiple line
---------------------------------------
ACG_int <= ATN_int and to_stdl(DI(6 downto 4) = "000");
ACG <= ACG_int;
---------------------------------------
DAB <= not ATN_int and ((eosUsed and to_stdl(DI /= eosMark)) or not eosUsed);
---------------------------------------
DCL <= ATN_int and to_stdl(DI(6 downto 0) = "0010100");
---------------------------------------
EOS <= not ATN_int and eosUsed and to_stdl(DI = eosMark);
---------------------------------------
GET <= ATN_int and to_stdl(DI(6 downto 0) = "0001000");
---------------------------------------
GTL <= ATN_int and to_stdl(DI(6 downto 0) = "0000001");
---------------------------------------
LAG_int <= ATN_int and to_stdl(DI(6 downto 5) = "01");
LAG <= LAG_int;
---------------------------------------
LLO <= ATN_int and to_stdl(DI(6 downto 0) = "0010001");
---------------------------------------
MLA <= LAG_int and to_stdl(DI(4 downto 0) = myListAddr);
---------------------------------------
MTA_int <= TAG_int and to_stdl(DI(4 downto 0) = myTalkAddr);
MTA <= MTA_int;
---------------------------------------
MSA_int <= SCG_int and secAddrDetected;
MSA <= MSA_int;
---------------------------------------
NUL <= ATN_int and to_stdl(DI = "00000000");
---------------------------------------
OSA <= SCG_int and not MSA_int;
---------------------------------------
OTA <= TAG_int and not MTA_int;
---------------------------------------
PCG <= ACG_int or UCG_int or LAG_int or TAG_int;
---------------------------------------
PPC <= ATN_int and to_stdl(DI(6 downto 0) = "0000101");
---------------------------------------
PPE <= ATN_int and to_stdl(DI(6 downto 4) = "110");
---------------------------------------
PPD <= ATN_int and to_stdl(DI(6 downto 4) = "111"); -- "-1110000" ?
---------------------------------------
PPR <= ATN_int and IDY_int;
---------------------------------------
PPU <= ATN_int and to_stdl(DI(6 downto 0) = "0010101");
---------------------------------------
RQS <= STB_int and to_stdl(DI(6) = '1');
---------------------------------------
SCG_int <= ATN_int and to_stdl(DI(6 downto 5) = "11");
SCG <= SCG_int;
---------------------------------------
SDC <= ATN_int and to_stdl(DI(6 downto 0) = "0000100");
---------------------------------------
SPD <= ATN_int and to_stdl(DI(6 downto 0) = "0011001");
---------------------------------------
SPE <= ATN_int and to_stdl(DI(6 downto 0) = "0011000");
---------------------------------------
STB_int <= not ATN_int and SPAS;
STB <= STB_int;
---------------------------------------
TAG_int <= ATN_int and to_stdl(DI(6 downto 5) = "10");
TAG <= TAG_int;
---------------------------------------
TCT <= ATN_int and to_stdl(DI(6 downto 0) = "0001001");
---------------------------------------
UCG_int <= ATN_int and to_stdl(DI(6 downto 4) = "001");
UCG <= UCG_int;
---------------------------------------
UNL <= ATN_int and to_stdl(DI(6 downto 0) = "0111111");
---------------------------------------
UNT <= ATN_int and to_stdl(DI(6 downto 0) = "1011111");
end arch;
| gpl-3.0 |
freecores/gpib_controller | vhdl/src/wrapper/gpibControlReg.vhd | 1 | 2822 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: gpibControlReg
-- Date:2011-11-12
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gpibControlReg is
port (
reset : in std_logic;
strobe : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
------------------ gpib ------------------------
ltn : out std_logic; -- listen (L, LE)
lun : out std_logic; -- local unlisten (L, LE)
rtl : out std_logic; -- return to local (RL)
rsv : out std_logic; -- request service (SR)
ist : out std_logic; -- individual status (PP)
lpe : out std_logic; -- local poll enable (PP)
------------------------------------------------
rsc : out std_logic; -- request system control (C)
sic : out std_logic; -- send interface clear (C)
sre : out std_logic; -- send remote enable (C)
gts : out std_logic; -- go to standby (C)
tcs : out std_logic; -- take control synchronously (C, AH)
tca : out std_logic; -- take control asynchronously (C)
rpp : out std_logic; -- request parallel poll (C)
rec_stb : out std_logic -- receives status byte (C)
);
end gpibControlReg;
architecture arch of gpibControlReg is
signal inner_buf : std_logic_vector (15 downto 0);
begin
ltn <= inner_buf(0);
lun <= inner_buf(1);
rtl <= inner_buf(2);
rsv <= inner_buf(3);
ist <= inner_buf(4);
lpe <= inner_buf(5);
------------------------------------------------
rsc <= inner_buf(6);
sic <= inner_buf(7);
sre <= inner_buf(8);
gts <= inner_buf(9);
tcs <= inner_buf(10);
tca <= inner_buf(11);
rpp <= inner_buf(12);
rec_stb <= inner_buf(13);
data_out <= inner_buf;
process (reset, strobe) begin
if reset = '1' then
inner_buf <= "0000000000000000";
elsif rising_edge(strobe) then
inner_buf <= data_in;
end if;
end process;
end arch;
| gpl-3.0 |
dhmeves/ece-485 | ece-485-project-2/ALUOut.vhd | 1 | 360 | library IEEE;
use ieee.std_logic_1164.all;
entity ALUOut is
port(
input : in std_logic_vector(31 downto 0);
clk, rst, pre, ce : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end ALUOut;
architecture behav of ALUOut is
begin
ALUOutput : entity work.thirty_two_bit_register(behav) port map(input, clk, rst, pre, ce, output);
end behav; | gpl-3.0 |
dhmeves/ece-485 | ece-485-project-2/thirty_two_to_one_mux.vhd | 1 | 1634 | library IEEE;
use ieee.std_logic_1164.all;
entity thirty_two_to_one_mux is
port(
in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, in16, in17, in18, in19, in20, in21, in22, in23, in24, in25, in26, in27, in28, in29, in30, in31 : in std_logic_vector(31 downto 0);
sel : in std_logic_vector(4 downto 0);
output : out std_logic_vector(31 downto 0)
);
end entity thirty_two_to_one_mux;
architecture behav of thirty_two_to_one_mux is
begin
--output <= (a and (not sel(0)) and (not sel(1))) or (b and sel(0) and (not sel(1))) or (c and (not sel(0)) and sel(1)) or (d and sel(0) and sel(1));
output <= in0 when (sel = "00000") else in1 when (sel = "00001") else in2 when (sel = "00010") else in3 when (sel = "00011") else in4 when (sel = "00100") else in5 when (sel = "00101") else in6 when (sel = "00110") else in7 when (sel = "00111") else in8 when (sel = "01000") else in9 when (sel = "01001") else in10 when (sel = "01010") else in11 when (sel = "01011") else in12 when (sel = "01100") else in13 when (sel = "01101") else in14 when (sel = "01110") else in15 when (sel = "01111") else in16 when (sel = "10000") else in17 when (sel = "10001") else in18 when (sel = "10010") else in19 when (sel = "10011") else in20 when (sel = "10100") else in21 when (sel = "10101") else in22 when (sel = "10110") else in23 when (sel = "10111") else in24 when (sel = "11000") else in25 when (sel = "11001") else in26 when (sel = "11010") else in27 when (sel = "11011") else in28 when (sel = "11100") else in29 when (sel = "11101") else in30 when (sel = "11110") else in31 when (sel = "11111");
end behav; | gpl-3.0 |
MonsieurOenologue/Paprotto | Paprotto.vhd | 1 | 2441 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Paprotto IS
PORT(
clk : IN STD_LOGIC;
reset : IN std_logic;
run : IN std_logic;
code : IN std_logic_vector(15 DOWNTO 0);
done : OUT std_logic;
overflow : OUT std_logic
);
END ENTITY Paprotto;
ARCHITECTURE behavior OF Paprotto IS
--Component controler
COMPONENT fsm IS
PORT(
run : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
IR : IN std_logic_vector(9 DOWNTO 0);
done : OUT std_logic;
multSel : OUT std_logic_vector(3 DOWNTO 0);
R0 : OUT std_logic;
R1 : OUT std_logic;
R2 : OUT std_logic;
R3 : OUT std_logic;
R4 : OUT std_logic;
R5 : OUT std_logic;
R6 : OUT std_logic;
R7 : OUT std_logic;
Aset : OUT std_logic_vector(15 DOWNTO 0);
Gset : OUT std_logic_vector(15 DOWNTO 0);
ALU : OUT std_logic_vector(3 DOWNTO 0);
IRSet : OUT std_logic
);
END COMPONENT;
COMPONENT alu IS
GENERIC(N:POSITIVE := 8);
PORT(
clk : IN std_logic;
sel : IN std_logic_vector(3 DOWNTO 0);
A, B : IN std_logic_vector(N-1 DOWNTO 0);
Q : OUT std_logic_vector(N-1 DOWNTO 0);
Cout : OUT std_logic
);
END COMPONENT;
--Memory generic
COMPONENT shiftregG IS
GENERIC(N : POSITIVE := 8);
PORT(
clk,rst,set : IN STD_LOGIC;
d : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
END COMPONENT;
-- Selectors for memorys
SIGNAL Rs : std_logic_vector(7 DOWNTO 0);
SIGNAL Routs : std_logic_vector(15 DOWNTO 0);
SIGNAL ALUs : std_logic_vector(3 DOWNTO 0);
SIGNAL Gs : std_logic_vector(15 DOWNTO 0);
SIGNAL goToGs : std_logic_vector(15 DOWNTO 0);
--SIGNAL StorageDatas : std_logic_vector(15 DOWNTO 0);
SIGNAL IRSets : std_logic;
--multSel : select which value will be take
SIGNAL multSel : STD_LOGIC_VECTOR(3 DOWNTO 0);
-- mults is the exit of the multiplexer
SIGNAL mults : STD_LOGIC_VECTOR(15 DOWNTO 0);
--As is the exit of A register
SIGNAL As : std_logic_vector(15 DOWNTO 0);
BEGIN
fsme : fsm PORT MAP(run, reset, clk, code(9 DOWNTO 0), done, multSel, Rs(0),Rs(1),Rs(2),Rs(3),Rs(4),Rs(5),Rs(6),Rs(7), As, Gs, ALUs, IRSets); -- Problem : Duplicate declaration
alue : alu PORT MAP(clk, ALUs, As , multSel, goToGs, overflow); -- Problem : Duplicate declaration
memory : for i in 0 to 7 GENERATE
shiftregG : shiftregG (Generic : 15) PORT MAP(clk, rst, Rs(i), multSel, Routs(i));
END GENERATE memory;
END ARCHITECTURE behavior;
| gpl-3.0 |
MonsieurOenologue/Paprotto | composants_fonctionnels/faGTest.vhd | 1 | 694 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY testfaG IS
END ENTITY testfaG;
Architecture Test OF testfaG IS
COMPONENT faG IS
GENERIC(N : POSITIVE := 8);
PORT(
A,B : IN std_logic_vector(N-1 DOWNTO 0);
Cin : IN std_logic;
S : OUT std_logic_vector(N-1 DOWNTO 0);
Cout : OUT std_logic
);
END COMPONENT;
SIGNAL s_A, s_B, s_S : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_Cin, s_Cout : STD_LOGIC;
BEGIN
testfaG : faG GENERIC MAP(16) PORT MAP(s_A, s_B, '0', s_S, s_Cout);
ProcessSimulation : PROCESS
BEGIN
s_A <= "1000000000000001";
s_B <= "1000000000000010";
WAIT FOR 40 ns;
WAIT;
END PROCESS ProcessSimulation;
END Test;
| gpl-3.0 |
MonsieurOenologue/Paprotto | IRegister.vhd | 1 | 540 | --Libraries imports
library ieee;
use ieee.std_logic_1164.all;
--Entity declaration
ENTITY IRegister IS
generic (N:integer := 16); --16 for a 16bits processor
PORT (
clk : IN std_logic;
IRSet : IN std_logic;
D : IN std_logic_vector(9 downto 0);
Q : OUT std_logic_vector(9 downto 0)
);
END IRegister;
--Architecture behavior
ARCHITECTURE behavior OF IRegister IS
BEGIN
-- Just a register without the clock part
PROCESS(IRset, Q)
BEGIN
if IRset = '1' then Q <= D;
end if;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 |
iamllama/EE2020 | ee2020.ip_user_files/ipstatic/hdl/c_mux_bit_v12_0_vh_rfs.vhd | 1 | 239688 | `protect begin_protected
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`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| gpl-3.0 |
iamllama/EE2020 | ee2020.cache/ip/b67405368c510ef2/dds_compiler_0_stub.vhdl | 1 | 1617 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Mar 28 05:22:49 2017
-- Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_compiler_0_stub.vhdl
-- Design : dds_compiler_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_phase_tvalid,s_axis_phase_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "dds_compiler_v6_0_13,Vivado 2016.4";
begin
end;
| gpl-3.0 |
suoto/hdlcc | .ci/test_support/test_builders/no_messages.vhd | 1 | 324 | library ieee;
use ieee.std_logic_1164.all;
entity no_messages is
generic (
DIVIDER : integer := 10
);
port (
reset : in std_logic;
clk_input : in std_logic;
clk_output : out std_logic
);
end no_messages;
architecture no_messages of no_messages is
begin
end no_messages;
| gpl-3.0 |
albayaty/Video-Game-Engine | EDK/VGA/40x30/vgatimehelper.vhd | 1 | 4696 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: VGA 40x30 Resolution, Timer Helper VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vgatimehelper is
port(
clk, reset: in std_logic; --send in 50mhz clock
hsync, vsync: out std_logic;
video_on, p_tick: out std_logic; --p_tick is the 25mhz clock you will
--not need to use, video_on is when you
--can display a pixel
pixel_x, pixel_y: out std_logic_vector (9 downto 0)
);
end vgatimehelper;
architecture arch of vgatimehelper is
-- VGA 640-by-480 sync parameters
constant HD: integer:=640; --horizontal display area
constant HF: integer:=16 ; --h. front porch
constant HB: integer:=48 ; --h. back porch
constant HR: integer:=96 ; --h. retrace
constant VD: integer:=480; --vertical display area
constant VF: integer:=10; --v. front porch
constant VB: integer:=33; --v. back porch
constant VR: integer:=2; --v. retrace
-- mod-2 counter
signal mod2_reg, mod2_next: std_logic;
-- sync counters
signal v_count_reg, v_count_next: unsigned(9 downto 0);
signal h_count_reg, h_count_next: unsigned(9 downto 0);
-- output buffer
signal v_sync_reg, h_sync_reg: std_logic;
signal v_sync_next, h_sync_next: std_logic;
-- status signal
signal h_end, v_end, pixel_tick: std_logic;
begin
-- registers
process (clk,reset)
begin
if reset='1' then
mod2_reg <= '0';
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
v_sync_reg <= '0';
h_sync_reg <= '0';
elsif (clk'event and clk='1') then
mod2_reg <= mod2_next;
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next;
h_sync_reg <= h_sync_next;
end if;
end process;
-- mod-2 circuit to generate 25 MHz enable tick
mod2_next <= not mod2_reg;
-- 25 MHz pixel tick
pixel_tick <= '1' when mod2_reg='1' else '0';
-- status
h_end <= -- end of horizontal counter
'1' when h_count_reg=(HD+HF+HB+HR-1) else --799
'0';
v_end <= -- end of vertical counter
'1' when v_count_reg=(VD+VF+VB+VR-1) else --524
'0';
-- mod-800 horizontal sync counter
process (h_count_reg,h_end,pixel_tick)
begin
if pixel_tick='1' then -- 25 MHz tick
if h_end='1' then
h_count_next <= (others=>'0');
else
h_count_next <= h_count_reg + 1;
end if;
else
h_count_next <= h_count_reg;
end if;
end process;
-- mod-525 vertical sync counter
process (v_count_reg,h_end,v_end,pixel_tick)
begin
if pixel_tick='1' and h_end='1' then
if (v_end='1') then
v_count_next <= (others=>'0');
else
v_count_next <= v_count_reg + 1;
end if;
else
v_count_next <= v_count_reg;
end if;
end process;
-- horizontal and vertical sync, buffered to avoid glitch
h_sync_next <=
'1' when (h_count_reg>=(HD+HF)) --656
and (h_count_reg<=(HD+HF+HR-1)) else --751
'0';
v_sync_next <=
'1' when (v_count_reg>=(VD+VF)) --490
and (v_count_reg<=(VD+VF+VR-1)) else --491
'0';
-- video on/off
video_on <=
'1' when (h_count_reg<HD) and (v_count_reg<VD) else
'0';
-- output signal
hsync <= h_sync_reg;
vsync <= v_sync_reg;
pixel_x <= std_logic_vector(h_count_reg);
pixel_y <= std_logic_vector(v_count_reg);
p_tick <= pixel_tick;
end arch;
| gpl-3.0 |
suoto/hdlcc | .ci/test_support/test_project/basic_library/package_with_constants.vhd | 1 | 400 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library basic_library;
package package_with_constants is
constant SOME_INTEGER_CONSTANT : integer := 10;
constant SOME_STRING_CONSTANT : string := "Hello";
constant SOME_STRING : string := basic_library.very_common_pkg.VIM_HDL_VERSION;
end;
-- package body package_with_constants is
-- end package body;
| gpl-3.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/pwm.vhd | 1 | 5515 | --------------------------------------------------------------------------------
--
-- FileName: pwm.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 8/1/2013 Scott Larson
-- Initial Public Release
-- Version 2.0 1/9/2015 Scott Larson
-- Transistion between duty cycles always starts at center of pulse to avoid
-- anomalies in pulse shapes
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY pwm IS
GENERIC(
sys_clk : INTEGER := 50_000_000; --system clock frequency in Hz
pwm_freq : INTEGER := 100_000; --PWM switching frequency in Hz
bits_resolution : INTEGER := 8; --bits of resolution setting the duty cycle
phases : INTEGER := 1); --number of output pwms and phases
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
ena : IN STD_LOGIC; --latches in new duty cycle
duty : IN STD_LOGIC_VECTOR(bits_resolution-1 DOWNTO 0); --duty cycle
pwm_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0); --pwm outputs
pwm_n_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0)); --pwm inverse outputs
END pwm;
ARCHITECTURE logic OF pwm IS
CONSTANT period : INTEGER := sys_clk/pwm_freq; --number of clocks in one pwm period
TYPE counters IS ARRAY (0 TO phases-1) OF INTEGER RANGE 0 TO period - 1; --data type for array of period counters
SIGNAL count : counters := (OTHERS => 0); --array of period counters
SIGNAL half_duty_new : INTEGER RANGE 0 TO period/2 := 0; --number of clocks in 1/2 duty cycle
TYPE half_duties IS ARRAY (0 TO phases-1) OF INTEGER RANGE 0 TO period/2; --data type for array of half duty values
SIGNAL half_duty : half_duties := (OTHERS => 0); --array of half duty values (for each phase)
BEGIN
PROCESS(clk, reset_n)
variable v_compute : unsigned(bits_resolution+24-1 downto 0);
BEGIN
IF(reset_n = '0') THEN --asynchronous reset
count <= (OTHERS => 0); --clear counter
pwm_out <= (OTHERS => '0'); --clear pwm outputs
pwm_n_out <= (OTHERS => '0'); --clear pwm inverse outputs
ELSIF(clk'EVENT AND clk = '1') THEN --rising system clock edge
IF(ena = '1') THEN --latch in new duty cycle
v_compute := unsigned(duty)*to_unsigned(period,24)/(2**(bits_resolution+1));
half_duty_new <= to_integer(v_compute(31-1 downto 0));--(unsigned(duty)*period/(2**(bits_resolution))/2));--conv_integer(duty)*period/(2**bits_resolution)/2; --determine clocks in 1/2 duty cycle
END IF;
FOR i IN 0 to phases-1 LOOP --create a counter for each phase
IF(count(0) = period - 1 - i*period/phases) THEN --end of period reached
count(i) <= 0; --reset counter
half_duty(i) <= half_duty_new; --set most recent duty cycle value
ELSE --end of period not reached
count(i) <= count(i) + 1; --increment counter
END IF;
END LOOP;
FOR i IN 0 to phases-1 LOOP --control outputs for each phase
IF(count(i) = half_duty(i)) THEN --phase's falling edge reached
pwm_out(i) <= '0'; --deassert the pwm output
pwm_n_out(i) <= '1'; --assert the pwm inverse output
ELSIF(count(i) = period - half_duty(i)) THEN --phase's rising edge reached
pwm_out(i) <= '1'; --assert the pwm output
pwm_n_out(i) <= '0'; --deassert the pwm inverse output
END IF;
END LOOP;
END IF;
END PROCESS;
END logic;
| gpl-3.0 |
iamllama/EE2020 | ee2020.srcs/sources_1/imports/hdl/Ps2Interface.vhd | 3 | 32097 | ------------------------------------------------------------------------
-- ps2interface.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- This file contains the implementation of a generic bidirectional
-- ps/2 interface.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web for understanding how
-- the ps/2 protocol works.
-- http://www.computer-engineering.org/ps2protocol/
-- This module implements a generic bidirectional ps/2 interface. It can
-- be used with any ps/2 compatible device. It offers its clients a
-- convenient way to exchange data with the device. The interface
-- transparently wraps the byte to be sent into a ps/2 frame, generates
-- parity for byte and sends the frame one bit at a time to the device.
-- Similarly, when receiving data from the ps2 device, the interface
-- receives the frame, checks for parity, and extract the usefull data
-- and forwards it to the client. If an error occurs during receiving
-- or sending a byte, the client is informed by settings the err output
-- line high. This way, the client can resend the data or can issue
-- a resend command to the device.
-- The physical ps/2 interface uses 4 lines
-- For the 6-pin connector pins are assigned as follows:
-- 1 - Data
-- 2 - Not Implemented
-- 3 - Ground
-- 4 - Vcc (+5V)
-- 5 - Clock
-- 6 - Not Implemented
-- The clock line carries the device generated clock which has a
-- frequency in range 10 - 16.7 kHz (30 to 50us). When line is idle
-- it is placed in high impedance. The clock is only generated when
-- device is sending or receiving data.
-- The Data and Clock lines are both open-collector with pullup
-- resistors to Vcc. An "open-collector" interface has two possible
-- states: low('0') or high impedance('Z').
-- When device wants to send a byte, it pulls the clock line low and the
-- host(i.e. this interfaces) recognizes that the device is sending data
-- When the host wants to send data, it maeks a request to send. This
-- is done by holding the clock line low for at least 100us, then with
-- the clock line low, the data line is brought low. Next the clock line
-- is released (placed in high impedance). The devices begins generating
-- clock signal on clock line.
-- When receiving data, bits are read from the data line (ps2_data) on
-- the falling edge of the clock (ps2_clk). When sending data, the
-- device reads the bits from the data line on the rising edge of the
-- clock.
-- A frame for sending a byte is comprised of 11 bits as shown bellow:
-- bits 10 9 8 7 6 5 4 3 2 1 0
-- -------------------------------------------------------------
-- | STOP| PAR | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | START |
-- -------------------------------------------------------------
-- STOP - stop bit, always '1'
-- PAR - parity bit, odd parity for the 8 data bits.
-- - select in such way that the number of bits of '1' in the data
-- - bits together with parity bit is odd.
-- D0-7 - data bits.
-- START - start bit, always '0'
--
-- Frame is sent bit by bit starting with the least significant bit
-- (starting bit) and is received the same way. This is done, when
-- receiving, by shifting the frame register to the left when a bit
-- is available and placing the bit on data line on the most significant
-- bit. This way the first bit sent will reach the least significant bit
-- of the frame when all the bits have been received. When sending data
-- the least significant bit of the frame is placed on the data line
-- and the frame is shifted to the right when another bit needs to be
-- sent. During the request to send, when releasing the clock line,
-- the device reads the data line and interprets the data on it as the
-- first bit of the frame. Data line is low at that time, at this is the
-- way the start bit('0') is sent. Because of this, when sending, only
-- 10 shifts of the frame will be made.
-- While the interface is sending or receiving data, the busy output
-- signal goes high. When interface is idle, busy is low.
-- After sending all the bits in the frame, the device must acknowledge
-- the data sent. This is done by the host releasing and data line
-- (clock line is already released) after the last bit is sent. The
-- devices brings the data line and the clock line low, in this order,
-- to acknowledge the data. If data line is high when clock line goes
-- low after last bit, the device did not acknowledge the data and
-- err output is set.
-- A FSM is used to manage the transitions the set all the command
-- signals. States that begin with "rx_" are used to receive data
-- from device and states begining with "tx_" are used to send data
-- to the device.
-- For the parity bit, a ROM holds the parity bit for all possible
-- data (256 possible values, since 8 bits of data). The ROM has
-- dimensions 256x1bit. For obtaining the parity bit of a value,
-- the bit at the data value address is read. Ex: to find the parity
-- bit of 174, the bit at address 174 is read.
-- For generating the necessary delay, counters are used. For example,
-- to generate the 100us delay a 14 bit counter is used that has the
-- upper limit for counting 10000. The interface is designed to run
-- at 100MHz. Thus, 10000x10ns = 100us.
-----------------------------------------------------------------------
-- If using the interface at different frequency than 100MHz, adjusting
-- the delay counters is necessary!!!
-----------------------------------------------------------------------
-- Clock line(ps2_clk) and data line(ps2_data) are passed through a
-- debouncer for the transitions of the clock and data to be clean.
-- Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized
-- value of the clock and data line to the system clock(clk).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- ps2_clk - inout pin, clock line of the ps/2 interface
-- ps2_data - inout pin, data line of the ps/2 interface
-- clk - input pin, system clock signal
-- rst - input pin, system reset signal
-- tx_data - input pin, 8 bits, from client
-- - data to be sent to the device
-- write_data - input pin, from client
-- - should be active for one clock period when then
-- - client wants to send data to the device and
-- - data to be sent is valid on tx_data
-- rx_data - output pin, 8 bits, to client
-- - data received from device
-- read - output pin, to client
-- - active for one clock period when new data is
-- - available from device
-- busy - output pin, to client
-- - active while sending or receiving data.
-- err - output pin, to client
-- - active for one clock period when an error occurred
-- - during sending or receiving.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the ps2interface entity declaration
-- read above for behavioral description and port definitions.
entity Ps2Interface is
port(
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
clk : in std_logic;
rst : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
write_data : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
read_data : out std_logic;
busy : out std_logic;
err : out std_logic
);
-- forces the extraction of distributed ram for
-- the parity rom memory.
-- please remove if block ram is preffered.
attribute rom_extract : string;
attribute rom_extract of Ps2Interface: entity is "yes";
attribute rom_style : string;
attribute rom_style of Ps2Interface: entity is "distributed";
end Ps2Interface;
architecture Behavioral of Ps2Interface is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- Values are valid for a 100MHz clk. Please adjust for other
-- frequencies if necessary!
-- upper limit for 100us delay counter.
-- 10000 * 10ns = 100us
constant DELAY_100US : std_logic_vector(13 downto 0):= "10011100010000";
-- 10000 clock periods
-- upper limit for 20us delay counter.
-- 2000 * 10ns = 20us
constant DELAY_20US : std_logic_vector(10 downto 0) := "11111010000";
-- 2000 clock periods
-- upper limit for 63clk delay counter.
constant DELAY_63CLK : std_logic_vector(6 downto 0) := "1111111";
-- 63 clock periods
-- delay from debouncing ps2_clk and ps2_data signals
constant DEBOUNCE_DELAY : std_logic_vector(3 downto 0) := "1111";
-- number of bits in a frame
constant NUMBITS: std_logic_vector(3 downto 0) := "1011"; -- 11
-- parity bit position in frame
constant PARITY_BIT: positive := 9;
-- (odd) parity bit ROM
-- Used instead of logic because this way speed is far greater
-- 256x1bit rom
-- If the odd parity bit for a 8 bits number, x, is needed
-- the bit at address x is the parity bit.
type ROM is array(0 to 255) of std_logic;
constant parityrom : ROM := (
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1',
'1','0','0','1','0','1','1','0',
'1','0','0','1','0','1','1','0',
'0','1','1','0','1','0','0','1'
);
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- 14 bits counter
-- max value DELAY_100US
-- used to wait 100us
signal delay_100us_count: std_logic_vector(13 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_20US
-- used to wait 20us
signal delay_20us_count: std_logic_vector(10 downto 0) :=
(others => '0');
-- 11 bits counter
-- max value DELAY_63CLK
-- used to wait 63 clock periods
signal delay_63clk_count: std_logic_vector(6 downto 0) :=
(others => '0');
-- done signal for the couters above
-- when a counter reaches max value,the corresponding done signal is set
signal delay_100us_done, delay_20us_done, delay_63clk_done: std_logic;
-- enable signal for 100us delay counter
signal delay_100us_counter_enable: std_logic := '0';
-- enable signal for 20us delay counter
signal delay_20us_counter_enable : std_logic := '0';
-- enable signal for 63clk delay counter
signal delay_63clk_counter_enable: std_logic := '0';
-- synchronzed input for ps2_clk and ps2_data
signal ps2_clk_s,ps2_data_s: std_logic := '1';
-- control the output of ps2_clk and ps2_data
-- if 1 then corresponding signal (ps2_clk or ps2_data) is
-- put in high impedance ('Z').
signal ps2_clk_h,ps2_data_h: std_logic := '1';
-- states of the FSM for controlling the communcation with the device
-- states that begin with "rx_" are used when receiving data
-- states that begin with "tx_" are used when transmiting data
type fsm_state is
(
idle,rx_clk_h,rx_clk_l,rx_down_edge,rx_error_parity,rx_data_ready,
tx_force_clk_l,tx_bring_data_down,tx_release_clk,
tx_first_wait_down_edge,tx_clk_l,tx_wait_up_edge,tx_clk_h,
tx_wait_up_edge_before_ack,tx_wait_ack,tx_received_ack,
tx_error_no_ack
);
-- the signal that holds the current state of the FSM
-- implicitly state is idle.
signal state: fsm_state := idle;
-- register that holds the frame received or the one to be sent.
-- Its contents are shifted in from the bus one bit at a time
-- from left to right when receiving data and are shifted on the
-- bus (ps2_data) one bit at a time to the right when sending data
signal frame: std_logic_vector(10 downto 0) := (others => '0');
-- how many bits have been sent or received.
signal bit_count: std_logic_vector(3 downto 0) := (others => '0');
-- when active the bit counter is reset.
signal reset_bit_count: std_logic := '0';
-- when active the contents of the frame is shifted to the right
-- and the most significant bit of frame is loaded with ps2_data.
signal shift_frame: std_logic := '0';
-- parity of the byte that was received from the device.
-- must match the parity bit received, else error occurred.
signal rx_parity: std_logic := '0';
-- parity bit that is sent with the frame, representing the
-- odd parity of the byte currently being sent
signal tx_parity: std_logic := '0';
-- when active, frame is loaded with the start bit, data on
-- tx_data, parity bit (tx_parity) and stop bit
-- this frame will be sent to the device.
signal load_tx_data: std_logic := '0';
-- when active bits 8 downto 1 from frame are loaded into
-- rx_data register. This is the byte received from the device.
signal load_rx_data: std_logic := '0';
-- intermediary signals used to debounce the inputs ps2_clk and ps2_data
signal ps2_clk_clean,ps2_data_clean: std_logic := '1';
-- debounce counter for the ps2_clk input and the ps2_data input.
signal clk_count,data_count: std_logic_vector(3 downto 0);
-- last value on ps2_clk and ps2_data.
signal clk_inter,data_inter: std_logic := '1';
begin
---------------------------------------------------------------------
-- FLAGS and PS2 CLOCK AND DATA LINES
---------------------------------------------------------------------
-- clean ps2_clk signal (debounce)
-- note that this introduces a delay in ps2_clk of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_clk is different
-- from the last value, then reset counter
-- and retain value
if(ps2_clk /= clk_inter) then
clk_inter <= ps2_clk;
clk_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(clk_count = DEBOUNCE_DELAY) then
ps2_clk_clean <= clk_inter;
-- ps2_clk did not change, but counter did not
-- reach limit. Increment counter
else
clk_count <= clk_count + 1;
end if;
end if;
end process;
-- clean ps2_data signal (debounce)
-- note that this introduces a delay in ps2_data of
-- DEBOUNCE_DELAY clocks
process(clk)
begin
if(rising_edge(clk)) then
-- if the current bit on ps2_data is different
-- from the last value, then reset counter
-- and retain value
if(ps2_data /= data_inter) then
data_inter <= ps2_data;
data_count <= (others => '0');
-- if counter reached upper limit, then
-- the signal is clean
elsif(data_count = DEBOUNCE_DELAY) then
ps2_data_clean <= data_inter;
-- ps2_data did not change, but counter did not
-- reach limit. Increment counter
else
data_count <= data_count + 1;
end if;
end if;
end process;
-- Synchronize ps2 entries
ps2_clk_s <= ps2_clk_clean when rising_edge(clk);
ps2_data_s <= ps2_data_clean when rising_edge(clk);
-- Assign parity from frame bits 8 downto 1, this is the parity
-- that should be received inside the frame on PARITY_BIT position
rx_parity <= parityrom(conv_integer(frame(8 downto 1)))
when rising_edge(clk);
-- The parity for the data to be sent
tx_parity <= parityrom(conv_integer(tx_data)) when rising_edge(clk);
-- Force ps2_clk to '0' if ps2_clk_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_clk <= 'Z' when ps2_clk_h = '1' else '0';
-- Force ps2_data to '0' if ps2_data_h = '0', else release the line
-- ('Z' = +5Vcc because of pull-ups)
ps2_data <= 'Z' when ps2_data_h = '1' else '0';
-- Control busy flag. Interface is not busy while in idle state.
busy <= '0' when state = idle else '1';
-- reset the bit counter when in idle state.
reset_bit_count <= '1' when state = idle else '0';
-- Control shifting of the frame
-- When receiving from device, data is read
-- on the falling edge of ps2_clk
-- When sending to device, data is read by device
-- on the rising edge of ps2_clk
shift_frame <= '1' when state = rx_down_edge or
state = tx_clk_l else
'0';
---------------------------------------------------------------------
-- FINITE STATE MACHINE
---------------------------------------------------------------------
-- For the current state establish next state
-- and give necessary commands
manage_fsm: process(clk,rst,state,ps2_clk_s,ps2_data_s,write_data,tx_data,
bit_count,rx_parity,frame,delay_100us_done,
delay_20us_done,delay_63clk_done)
begin
-- if reset occurs, go to idle state.
if(rst = '1') then
state <= idle;
elsif(rising_edge(clk)) then
-- default values for these signals
-- ensures signals are reset to default value
-- when coditions for their activation are no
-- longer applied (transition to other state,
-- where signal should not be active)
-- Idle value for ps2_clk and ps2_data is 'Z'
ps2_clk_h <= '1';
ps2_data_h <= '1';
load_tx_data <= '0';
load_rx_data <= '0';
read_data <= '0';
err <= '0';
case state is
-- wait for the device to begin a transmission
-- by pulling the clock line low and go to state
-- rx_down_edge or, if write is high, the
-- client of this interface wants to send a byte
-- to the device and a transition is made to state
-- tx_force_clk_l
when idle =>
if(ps2_clk_s = '0') then
state <= rx_down_edge;
elsif(write_data = '1') then
state <= tx_force_clk_l;
else
state <= idle;
end if;
-- ps2_clk is high, check if all the bits have been read
-- if, last bit read, check parity, and if parity ok
-- load received data into rx_data.
-- else if more bits left, then wait for the ps2_clk to
-- go low
when rx_clk_h =>
if(bit_count = NUMBITS) then
if(not (rx_parity = frame(PARITY_BIT))) then
state <= rx_error_parity;
else
load_rx_data <= '1';
state <= rx_data_ready;
end if;
elsif(ps2_clk_s = '0') then
state <= rx_down_edge;
else
state <= rx_clk_h;
end if;
-- data must be read into frame in this state
-- the ps2_clk just transitioned from high to low
when rx_down_edge =>
state <= rx_clk_l;
-- ps2_clk line is low, wait for it to go high
when rx_clk_l =>
if(ps2_clk_s = '1') then
state <= rx_clk_h;
else
state <= rx_clk_l;
end if;
-- parity bit received is invalid
-- signal error and go back to idle.
when rx_error_parity =>
err <= '1';
state <= idle;
-- parity bit received was good
-- set read signal for the client to know
-- a new byte was received and is available on rx_data
when rx_data_ready =>
read_data <= '1';
state <= idle;
-- the client wishes to transmit a byte to the device
-- this is done by holding ps2_clk down for at least 100us
-- bringing down ps2_data, wait 20us and then releasing
-- the ps2_clk.
-- This constitutes a request to send command.
-- In this state, the ps2_clk line is held down and
-- the counter for waiting 100us is eanbled.
-- when the counter reached upper limit, transition
-- to tx_bring_data_down
when tx_force_clk_l =>
load_tx_data <= '1';
ps2_clk_h <= '0';
if(delay_100us_done = '1') then
state <= tx_bring_data_down;
else
state <= tx_force_clk_l;
end if;
-- with the ps2_clk line low bring ps2_data low
-- wait for 20us and then go to tx_release_clk
when tx_bring_data_down =>
-- keep clock line low
ps2_clk_h <= '0';
-- set data line low
-- when clock is released in the next state
-- the device will read bit 0 on data line
-- and this bit represents the start bit.
ps2_data_h <= '0'; -- start bit = '0'
if(delay_20us_done = '1') then
state <= tx_release_clk;
else
state <= tx_bring_data_down;
end if;
-- release the ps2_clk line
-- keep holding data line low
when tx_release_clk =>
ps2_clk_h <= '1';
-- must maintain data low,
-- otherwise will be released by default value
ps2_data_h <= '0';
state <= tx_first_wait_down_edge;
-- state is necessary because the clock signal
-- is not released instantaneously and, because of debounce,
-- delay is even greater.
-- Wait 63 clock periods for the clock line to release
-- then if clock is low then go to tx_clk_l
-- else wait until ps2_clk goes low.
when tx_first_wait_down_edge =>
ps2_data_h <= '0';
if(delay_63clk_done = '1') then
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_first_wait_down_edge;
end if;
else
state <= tx_first_wait_down_edge;
end if;
-- place the least significant bit from frame
-- on the data line
-- During this state the frame is shifted one
-- bit to the right
when tx_clk_l =>
ps2_data_h <= frame(0);
state <= tx_wait_up_edge;
-- wait for the clock to go high
-- this is the edge on which the device reads the data
-- on ps2_data.
-- keep holding ps2_data on frame(0) because else
-- will be released by default value.
-- Check if sent the last bit and if so, release data line
-- and go to state that wait for acknowledge
when tx_wait_up_edge =>
ps2_data_h <= frame(0);
-- NUMBITS - 1 because first (start bit = 0) bit was read
-- when the clock line was released in the request to
-- send command (see tx_bring_data_down state).
if(bit_count = NUMBITS-1) then
ps2_data_h <= '1';
state <= tx_wait_up_edge_before_ack;
-- if more bits to send, wait for the up edge
-- of ps2_clk
elsif(ps2_clk_s = '1') then
state <= tx_clk_h;
else
state <= tx_wait_up_edge;
end if;
-- ps2_clk is released, wait for down edge
-- and go to tx_clk_l when arrived
when tx_clk_h =>
ps2_data_h <= frame(0);
if(ps2_clk_s = '0') then
state <= tx_clk_l;
else
state <= tx_clk_h;
end if;
-- release ps2_data and wait for rising edge of ps2_clk
-- once this occurs, transition to tx_wait_ack
when tx_wait_up_edge_before_ack =>
ps2_data_h <= '1';
if(ps2_clk_s = '1') then
state <= tx_wait_ack;
else
state <= tx_wait_up_edge_before_ack;
end if;
-- wait for the falling edge of the clock line
-- if data line is low when this occurs, the
-- ack is received
-- else if data line is high, the device did not
-- acknowledge the transimission
when tx_wait_ack =>
if(ps2_clk_s = '0') then
if(ps2_data_s = '0') then
-- acknowledge received
state <= tx_received_ack;
else
-- acknowledge not received
state <= tx_error_no_ack;
end if;
else
state <= tx_wait_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
when tx_received_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
state <= idle;
else
state <= tx_received_ack;
end if;
-- wait for ps2_clk to be released together with ps2_data
-- (bus to be idle) and go back to idle state
-- signal error for not receiving ack
when tx_error_no_ack =>
if(ps2_clk_s = '1' and ps2_data_s = '1') then
err <= '1';
state <= idle;
else
state <= tx_error_no_ack;
end if;
-- if invalid transition occurred, signal error and
-- go back to idle state
when others =>
err <= '1';
state <= idle;
end case;
end if;
end process manage_fsm;
---------------------------------------------------------------------
-- DELAY COUNTERS
---------------------------------------------------------------------
-- Enable the 100us counter only when state is tx_force_clk_l
delay_100us_counter_enable <= '1' when state = tx_force_clk_l else '0';
-- Counter for a 100us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_100us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_100us_counter_enable = '1') then
if(delay_100us_count = (DELAY_100US)) then
delay_100us_count <= delay_100us_count;
delay_100us_done <= '1';
else
delay_100us_count <= delay_100us_count + 1;
delay_100us_done <= '0';
end if;
else
delay_100us_count <= (others => '0');
delay_100us_done <= '0';
end if;
end if;
end process delay_100us_counter;
-- Enable the 20us counter only when state is tx_bring_data_down
delay_20us_counter_enable <= '1' when state = tx_bring_data_down else '0';
-- Counter for a 20us delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_20us_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_20us_counter_enable = '1') then
if(delay_20us_count = (DELAY_20US)) then
delay_20us_count <= delay_20us_count;
delay_20us_done <= '1';
else
delay_20us_count <= delay_20us_count + 1;
delay_20us_done <= '0';
end if;
else
delay_20us_count <= (others => '0');
delay_20us_done <= '0';
end if;
end if;
end process delay_20us_counter;
-- Enable the 63clk counter only when state is tx_first_wait_down_edge
delay_63clk_counter_enable <= '1' when state = tx_first_wait_down_edge else '0';
-- Counter for a 63 clock periods delay
-- after done counting, done signal remains active until
-- enable counter is reset.
delay_63clk_counter: process(clk)
begin
if(rising_edge(clk)) then
if(delay_63clk_counter_enable = '1') then
if(delay_63clk_count = (DELAY_63CLK)) then
delay_63clk_count <= delay_63clk_count;
delay_63clk_done <= '1';
else
delay_63clk_count <= delay_63clk_count + 1;
delay_63clk_done <= '0';
end if;
else
delay_63clk_count <= (others => '0');
delay_63clk_done <= '0';
end if;
end if;
end process delay_63clk_counter;
---------------------------------------------------------------------
-- BIT COUNTER AND FRAME SHIFTING LOGIC
---------------------------------------------------------------------
-- counts the number of bits shifted into the frame
-- or out of the frame.
bit_counter: process(clk)
begin
if(rising_edge(clk)) then
if(reset_bit_count = '1') then
bit_count <= (others => '0');
elsif(shift_frame = '1') then
bit_count <= bit_count + 1;
end if;
end if;
end process bit_counter;
-- shifts frame with one bit to right when shift_frame is acitve
-- and loads data into frame from tx_data then load_tx_data is high
load_tx_data_into_frame: process(clk)
begin
if(rising_edge(clk)) then
if(load_tx_data = '1') then
frame(8 downto 1) <= tx_data; -- byte to send
frame(0) <= '0'; -- start bit
frame(10) <= '1'; -- stop bit
frame(9) <= tx_parity; -- parity bit
elsif(shift_frame = '1') then
-- shift right 1 bit
frame(9 downto 0) <= frame(10 downto 1);
-- shift in from the ps2_data line
frame(10) <= ps2_data_s;
end if;
end if;
end process load_tx_data_into_frame;
-- Loads data from frame into rx_data output when data is ready
do_load_rx_data: process(clk)
begin
if(rising_edge(clk)) then
if(load_rx_data = '1') then
rx_data <= frame(8 downto 1);
end if;
end if;
end process do_load_rx_data;
end Behavioral;
| gpl-3.0 |
albayaty/Video-Game-Engine | EDK/NES-Controller/user_logic.vhd | 1 | 11238 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: NES User Logic VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Sun Oct 16 17:16:09 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 1
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset : in STD_LOGIC;
led : out STD_LOGIC_VECTOR(0 to 7);
nes_latch : out STD_LOGIC;
nes_clk : out STD_LOGIC;
nes_data : in STD_LOGIC;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component nes_controller
Port ( reset : in STD_LOGIC;
clk_50 : in STD_LOGIC;
led : out STD_LOGIC_VECTOR(0 to 7);
nes_latch : out STD_LOGIC;
nes_clk : out STD_LOGIC;
nes_data : in STD_LOGIC );
end component;
signal led_buf: STD_LOGIC_VECTOR(0 to 31);
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 0);
signal slv_reg_read_sel : std_logic_vector(0 to 0);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
nesmodule: nes_controller port map (
reset => reset,
clk_50 => Bus2IP_Clk,
led => led_buf(24 to 31),
nes_latch => nes_latch,
nes_clk => nes_clk,
nes_data => nes_data );
led <= led_buf(24 to 31);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 0);
slv_write_ack <= Bus2IP_WrCE(0);
slv_read_ack <= Bus2IP_RdCE(0);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
else
case slv_reg_write_sel is
when "1" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
begin
case slv_reg_read_sel is
when "1" => slv_ip2bus_data <= led_buf; --slv_reg0;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| gpl-3.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/types_pkg.vhd | 1 | 791 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package types_pkg is
type int8_t is array (natural range<>) of std_logic_vector(8 -1 downto 0);
type int16_t is array (natural range<>) of std_logic_vector(16-1 downto 0);
type int24_t is array (natural range<>) of std_logic_vector(24-1 downto 0);
type int32_t is array (natural range<>) of std_logic_vector(32-1 downto 0);
function std_norm_range(v: in std_logic_vector) return std_logic_vector;
end package;
package body types_pkg is
function std_norm_range(v: in std_logic_vector) return std_logic_vector is
variable v_result: std_logic_vector(v'length-1 downto 0);
begin
v_result := v;
return v_result;
end function;
end package body;
| gpl-3.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/pwm_pkg.vhd | 1 | 1062 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package pwm_pkg is
component pwm is
generic(
sys_clk : INTEGER := 50_000_000; --system clock frequency in Hz
pwm_freq : INTEGER := 100_000; --PWM switching frequency in Hz
bits_resolution : INTEGER := 8; --bits of resolution setting the duty cycle
phases : INTEGER := 1); --number of output pwms and phases
port(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
ena : IN STD_LOGIC; --latches in new duty cycle
duty : IN STD_LOGIC_VECTOR(bits_resolution-1 DOWNTO 0); --duty cycle
pwm_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0); --pwm outputs
pwm_n_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0) --pwm inverse outputs
);
end component;
end package;
| gpl-3.0 |
aylons/concordic | hdl/modules/unc_mult/unc_mult.vhd | 1 | 2634 | -------------------------------------------------------------------------------
-- Title : Unconstrained multiplier
-- Project :
-------------------------------------------------------------------------------
-- File : unc_mult.vhd
-- Author : Aylons <[email protected]>
-- Company :
-- Created : 2014-05-03
-- Last update: 2014-05-04
-- Platform :
-- Standard : VHDL'93/02/08
-------------------------------------------------------------------------------
-- Description: Generic multiplier which accepts signed vectors of any size
-- for both inputs and the resulting output. The output width must be smaller
-- than the summed width of the inputs. For outputs smaller than a_width +
-- b_width - 1, there will be one sign bit followed by as results MSBs.
--
-- This multiplier expects the synthesizer to infer multiplier logic from the * operator.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-03 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity unc_mult is
port(
a_i : in signed;
b_i : in signed;
result_o : out signed;
clk_i : in std_logic);
end unc_mult;
architecture behavioural of unc_mult is
begin
assert result_o'length < a_i'length + b_i'length
report "result_o width bigger than summed widths of a_i and b_i"
severity error;
process(clk_i) is
variable full_res : signed(a_i'length + b_i'length - 1 downto 0);
begin
if(rising_edge(clk_i)) then
full_res := a_i * b_i;
result_o <= full_res(full_res'left-1 downto full_res'left-1-result_o'length);
end if;
end process;
end architecture behavioural;
| gpl-3.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/spi_master_pkg.vhd | 1 | 1594 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package spi_master_pkg is
component spi_master is
GENERIC(
slaves : INTEGER := 4; --number of spi slaves
d_width : INTEGER := 2 --data bus width
);
PORT(
clock : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
enable : IN STD_LOGIC; --initiate transaction
cpol : IN STD_LOGIC; --spi clock polarity
cpha : IN STD_LOGIC; --spi clock phase
cont : IN STD_LOGIC; --continuous mode command
clk_div : IN INTEGER; --system clock cycles per 1/2 period of sclk
addr : IN INTEGER; --address of slave
tx_data : IN STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data to transmit
miso : IN STD_LOGIC; --master in, slave out
sclk : BUFFER STD_LOGIC; --spi clock
ss_n : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0); --slave select
mosi : OUT STD_LOGIC; --master out, slave in
busy : OUT STD_LOGIC; --busy / data ready signal
rx_data : OUT STD_LOGIC_VECTOR(d_width-1 DOWNTO 0) --data received
);
end component;
end package;
| gpl-3.0 |
suoto/hdlcc | .ci/test_support/test_project/basic_library/clock_divider.vhd | 1 | 1392 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library basic_library;
use basic_library.very_common_pkg.all;
use work.package_with_constants;
entity clock_divider is
generic (
DIVIDER : integer := 10
);
port (
reset : in std_logic;
clk_input : in std_logic;
clk_output : out std_logic
);
end clock_divider;
architecture clock_divider of clock_divider is
signal counter : integer range 0 to DIVIDER - 1 := 0;
signal clk_internal : std_logic := '0';
signal clk_enable_unused : std_logic := '0';
begin
clk_output <= clk_internal;
useless_u : clk_en_generator
generic map (
DIVIDER => DIVIDER)
port map (
reset => reset,
clk_input => clk_input,
clk_en => open);
-- We read 'reset' signal asynchronously inside the process to force
-- msim issuing a synthesis warning
process(clk_input)
begin
if reset = '1' then
counter <= 0;
elsif clk_input'event and clk_input = '1' then
if counter < DIVIDER then
counter <= counter + 1;
else
counter <= 0;
clk_internal <= not clk_internal;
end if;
end if;
end process;
end clock_divider;
| gpl-3.0 |
albayaty/Video-Game-Engine | EDK/VGA/20x15/vga_ip_core.vhd | 1 | 22878 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: VGA 20x15 Resolution, IP Core VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
------------------------------------------------------------------------------
-- vga_ip_core.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: vga_ip_core.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Sat Oct 15 15:40:57 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library vga_ip_core_v1_00_a;
use vga_ip_core_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity vga_ip_core is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex6"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
hsync: out std_logic;
vsync: out std_logic;
rgb: out std_logic_vector(0 to 2);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity vga_ip_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of vga_ip_core is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 7;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity vga_ip_core_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
hsync => hsync,
vsync => vsync,
rgb => rgb,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| gpl-3.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/uart.vhd | 1 | 25117 | --------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- MODULE: UART PARITY BIT GENERATOR
-- AUTHORS: Jakub Cabal <[email protected]>
-- lICENSE: The MIT License (MIT)
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_PARITY is
Generic (
DATA_WIDTH : integer := 8;
PARITY_TYPE : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
PARITY_OUT : out std_logic
);
end UART_PARITY;
architecture FULL of UART_PARITY is
begin
-- -------------------------------------------------------------------------
-- PARITY BIT GENERATOR
-- -------------------------------------------------------------------------
even_parity_g : if (PARITY_TYPE = "even") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '0';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
odd_parity_g : if (PARITY_TYPE = "odd") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '1';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
mark_parity_g : if (PARITY_TYPE = "mark") generate
PARITY_OUT <= '1';
end generate;
space_parity_g : if (PARITY_TYPE = "space") generate
PARITY_OUT <= '0';
end generate;
end FULL;
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- MODULE: UART RECEIVER
-- AUTHORS: Jakub Cabal <[email protected]>
-- lICENSE: The MIT License (MIT)
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_RX is
Generic (
PARITY_BIT : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
UART_RXD : in std_logic;
-- USER DATA OUTPUT INTERFACE
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_VLD : out std_logic; -- when DATA_VLD = 1, data on DATA_OUT are valid
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid, current and next data may be invalid
);
end UART_RX;
architecture FULL of UART_RX is
signal rx_clk_en : std_logic;
signal rx_ticks : unsigned(3 downto 0);
signal rx_clk_divider_en : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_bit_count : unsigned(2 downto 0);
signal rx_bit_count_en : std_logic;
signal rx_data_shreg_en : std_logic;
signal rx_parity_bit : std_logic;
signal rx_parity_error : std_logic;
signal rx_parity_check_en : std_logic;
signal rx_output_reg_en : std_logic;
type state is (idle, startbit, databits, paritybit, stopbit);
signal rx_pstate : state;
signal rx_nstate : state;
begin
-- -------------------------------------------------------------------------
-- UART RECEIVER CLOCK DIVIDER
-- -------------------------------------------------------------------------
uart_rx_clk_divider : process (CLK)
begin
if (rising_edge(CLK)) then
if (rx_clk_divider_en = '1') then
if (uart_clk_en = '1') then
if (rx_ticks = "1111") then
rx_ticks <= (others => '0');
rx_clk_en <= '0';
elsif (rx_ticks = "0111") then
rx_ticks <= rx_ticks + 1;
rx_clk_en <= '1';
else
rx_ticks <= rx_ticks + 1;
rx_clk_en <= '0';
end if;
else
rx_ticks <= rx_ticks;
rx_clk_en <= '0';
end if;
else
rx_ticks <= (others => '0');
rx_clk_en <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RECEIVER BIT COUNTER
-- -------------------------------------------------------------------------
uart_rx_bit_counter : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_bit_count <= (others => '0');
elsif (rx_bit_count_en = '1' AND rx_clk_en = '1') then
if (rx_bit_count = "111") then
rx_bit_count <= (others => '0');
else
rx_bit_count <= rx_bit_count + 1;
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RECEIVER DATA SHIFT REGISTER
-- -------------------------------------------------------------------------
uart_rx_data_shift_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_data <= (others => '0');
elsif (rx_clk_en = '1' AND rx_data_shreg_en = '1') then
rx_data <= UART_RXD & rx_data(7 downto 1);
end if;
end if;
end process;
DATA_OUT <= rx_data;
-- -------------------------------------------------------------------------
-- UART RECEIVER PARITY GENERATOR AND CHECK
-- -------------------------------------------------------------------------
uart_rx_parity_g : if (PARITY_BIT /= "none") generate
uart_rx_parity_gen_i: entity work.UART_PARITY
generic map (
DATA_WIDTH => 8,
PARITY_TYPE => PARITY_BIT
)
port map (
DATA_IN => rx_data,
PARITY_OUT => rx_parity_bit
);
uart_rx_parity_check_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_parity_error <= '0';
elsif (rx_parity_check_en = '1') then
rx_parity_error <= rx_parity_bit XOR UART_RXD;
end if;
end if;
end process;
end generate;
uart_rx_noparity_g : if (PARITY_BIT = "none") generate
rx_parity_error <= '0';
end generate;
-- -------------------------------------------------------------------------
-- UART RECEIVER OUTPUT REGISTER
-- -------------------------------------------------------------------------
uart_rx_output_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
DATA_VLD <= '0';
FRAME_ERROR <= '0';
else
if (rx_output_reg_en = '1') then
DATA_VLD <= NOT rx_parity_error AND UART_RXD;
FRAME_ERROR <= NOT UART_RXD;
else
DATA_VLD <= '0';
FRAME_ERROR <= '0';
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RECEIVER FSM
-- -------------------------------------------------------------------------
-- PRESENT STATE REGISTER
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_pstate <= idle;
else
rx_pstate <= rx_nstate;
end if;
end if;
end process;
-- NEXT STATE AND OUTPUTS LOGIC
process (rx_pstate, UART_RXD, rx_clk_en, rx_bit_count)
begin
case rx_pstate is
when idle =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '0';
rx_parity_check_en <= '0';
if (UART_RXD = '0') then
rx_nstate <= startbit;
else
rx_nstate <= idle;
end if;
when startbit =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '0';
if (rx_clk_en = '1') then
rx_nstate <= databits;
else
rx_nstate <= startbit;
end if;
when databits =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '1';
rx_data_shreg_en <= '1';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '0';
if ((rx_clk_en = '1') AND (rx_bit_count = "111")) then
if (PARITY_BIT = "none") then
rx_nstate <= stopbit;
else
rx_nstate <= paritybit;
end if ;
else
rx_nstate <= databits;
end if;
when paritybit =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '1';
if (rx_clk_en = '1') then
rx_nstate <= stopbit;
else
rx_nstate <= paritybit;
end if;
when stopbit =>
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '0';
if (rx_clk_en = '1') then
rx_nstate <= idle;
rx_output_reg_en <= '1';
else
rx_nstate <= stopbit;
rx_output_reg_en <= '0';
end if;
when others =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '0';
rx_parity_check_en <= '0';
rx_nstate <= idle;
end case;
end process;
end FULL;
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- MODULE: UART TRANSMITTER
-- AUTHORS: Jakub Cabal <[email protected]>
-- lICENSE: The MIT License (MIT)
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_TX is
Generic (
PARITY_BIT : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
UART_TXD : out std_logic;
-- USER DATA INPUT INTERFACE
DATA_IN : in std_logic_vector(7 downto 0);
DATA_SEND : in std_logic; -- when DATA_SEND = 1, data on DATA_IN will be transmit, DATA_SEND can set to 1 only when BUSY = 0
BUSY : out std_logic -- when BUSY = 1 transiever is busy, you must not set DATA_SEND to 1
);
end UART_TX;
architecture FULL of UART_TX is
signal tx_clk_en : std_logic;
signal tx_clk_divider_en : std_logic;
signal tx_ticks : unsigned(3 downto 0);
signal tx_data : std_logic_vector(7 downto 0);
signal tx_bit_count : unsigned(2 downto 0);
signal tx_bit_count_en : std_logic;
signal tx_busy : std_logic;
signal tx_parity_bit : std_logic;
signal tx_data_out_sel : std_logic_vector(1 downto 0);
type state is (idle, txsync, startbit, databits, paritybit, stopbit);
signal tx_pstate : state;
signal tx_nstate : state;
begin
BUSY <= tx_busy;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER CLOCK DIVIDER
-- -------------------------------------------------------------------------
uart_tx_clk_divider : process (CLK)
begin
if (rising_edge(CLK)) then
if (tx_clk_divider_en = '1') then
if (uart_clk_en = '1') then
if (tx_ticks = "1111") then
tx_ticks <= (others => '0');
tx_clk_en <= '0';
elsif (tx_ticks = "0001") then
tx_ticks <= tx_ticks + 1;
tx_clk_en <= '1';
else
tx_ticks <= tx_ticks + 1;
tx_clk_en <= '0';
end if;
else
tx_ticks <= tx_ticks;
tx_clk_en <= '0';
end if;
else
tx_ticks <= (others => '0');
tx_clk_en <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER INPUT DATA REGISTER
-- -------------------------------------------------------------------------
uart_tx_input_data_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_data <= (others => '0');
elsif (DATA_SEND = '1' AND tx_busy = '0') then
tx_data <= DATA_IN;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER BIT COUNTER
-- -------------------------------------------------------------------------
uart_tx_bit_counter : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_bit_count <= (others => '0');
elsif (tx_bit_count_en = '1' AND tx_clk_en = '1') then
if (tx_bit_count = "111") then
tx_bit_count <= (others => '0');
else
tx_bit_count <= tx_bit_count + 1;
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER PARITY GENERATOR
-- -------------------------------------------------------------------------
uart_tx_parity_g : if (PARITY_BIT /= "none") generate
uart_tx_parity_gen_i: entity work.UART_PARITY
generic map (
DATA_WIDTH => 8,
PARITY_TYPE => PARITY_BIT
)
port map (
DATA_IN => tx_data,
PARITY_OUT => tx_parity_bit
);
end generate;
uart_tx_noparity_g : if (PARITY_BIT = "none") generate
tx_parity_bit <= 'Z';
end generate;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER OUTPUT DATA REGISTER
-- -------------------------------------------------------------------------
uart_tx_output_data_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
UART_TXD <= '1';
else
case tx_data_out_sel is
when "01" => -- START BIT
UART_TXD <= '0';
when "10" => -- DATA BITS
UART_TXD <= tx_data(to_integer(tx_bit_count));
when "11" => -- PARITY BIT
UART_TXD <= tx_parity_bit;
when others => -- STOP BIT OR IDLE
UART_TXD <= '1';
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER FSM
-- -------------------------------------------------------------------------
-- PRESENT STATE REGISTER
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_pstate <= idle;
else
tx_pstate <= tx_nstate;
end if;
end if;
end process;
-- NEXT STATE AND OUTPUTS LOGIC
process (tx_pstate, DATA_SEND, tx_clk_en, tx_bit_count)
begin
case tx_pstate is
when idle =>
tx_busy <= '0';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '0';
if (DATA_SEND = '1') then
tx_nstate <= txsync;
else
tx_nstate <= idle;
end if;
when txsync =>
tx_busy <= '1';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '1';
if (tx_clk_en = '1') then
tx_nstate <= startbit;
else
tx_nstate <= txsync;
end if;
when startbit =>
tx_busy <= '1';
tx_data_out_sel <= "01";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '1';
if (tx_clk_en = '1') then
tx_nstate <= databits;
else
tx_nstate <= startbit;
end if;
when databits =>
tx_busy <= '1';
tx_data_out_sel <= "10";
tx_bit_count_en <= '1';
tx_clk_divider_en <= '1';
if ((tx_clk_en = '1') AND (tx_bit_count = "111")) then
if (PARITY_BIT = "none") then
tx_nstate <= stopbit;
else
tx_nstate <= paritybit;
end if ;
else
tx_nstate <= databits;
end if;
when paritybit =>
tx_busy <= '1';
tx_data_out_sel <= "11";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '1';
if (tx_clk_en = '1') then
tx_nstate <= stopbit;
else
tx_nstate <= paritybit;
end if;
when stopbit =>
tx_busy <= '0';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '1';
if (DATA_SEND = '1') then
tx_nstate <= txsync;
elsif (tx_clk_en = '1') then
tx_nstate <= idle;
else
tx_nstate <= stopbit;
end if;
when others =>
tx_busy <= '1';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '0';
tx_nstate <= idle;
end case;
end process;
end FULL;
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- MODULE: UART TOP MODULE
-- AUTHORS: Jakub Cabal <[email protected]>
-- lICENSE: The MIT License (MIT)
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- UART FOR FPGA REQUIRES: 1 START BIT, 8 DATA BITS, 1 STOP BIT!!!
-- OTHER PARAMETERS CAN BE SET USING GENERICS.
entity UART is
Generic (
CLK_FREQ : integer := 50e6; -- set system clock frequency in Hz
BAUD_RATE : integer := 115200; -- baud rate value
PARITY_BIT : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- USER DATA INPUT INTERFACE
DATA_IN : in std_logic_vector(7 downto 0);
DATA_SEND : in std_logic; -- when DATA_SEND = 1, data on DATA_IN will be transmit, DATA_SEND can set to 1 only when BUSY = 0
BUSY : out std_logic; -- when BUSY = 1 transiever is busy, you must not set DATA_SEND to 1
-- USER DATA OUTPUT INTERFACE
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_VLD : out std_logic; -- when DATA_VLD = 1, data on DATA_OUT are valid
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid, current and next data may be invalid
);
end UART;
architecture FULL of UART is
constant divider_value : integer := CLK_FREQ/(16*BAUD_RATE);
signal uart_ticks : integer range 0 to divider_value-1;
signal uart_clk_en : std_logic;
signal uart_rxd_shreg : std_logic_vector(3 downto 0);
signal uart_rxd_debounced : std_logic;
begin
-- -------------------------------------------------------------------------
-- UART OVERSAMPLING CLOCK DIVIDER
-- -------------------------------------------------------------------------
uart_oversampling_clk_divider : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
uart_ticks <= 0;
uart_clk_en <= '0';
elsif (uart_ticks = divider_value-1) then
uart_ticks <= 0;
uart_clk_en <= '1';
else
uart_ticks <= uart_ticks + 1;
uart_clk_en <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RXD DEBAUNCER
-- -------------------------------------------------------------------------
uart_rxd_debouncer : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
uart_rxd_shreg <= (others => '1');
uart_rxd_debounced <= '1';
else
uart_rxd_shreg <= UART_RXD & uart_rxd_shreg(3 downto 1);
uart_rxd_debounced <= uart_rxd_shreg(0) OR
uart_rxd_shreg(1) OR
uart_rxd_shreg(2) OR
uart_rxd_shreg(3);
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER
-- -------------------------------------------------------------------------
uart_tx_i: entity work.UART_TX
generic map (
PARITY_BIT => PARITY_BIT
)
port map (
CLK => CLK,
RST => RST,
-- UART INTERFACE
UART_CLK_EN => uart_clk_en,
UART_TXD => UART_TXD,
-- USER DATA INPUT INTERFACE
DATA_IN => DATA_IN,
DATA_SEND => DATA_SEND,
BUSY => BUSY
);
-- -------------------------------------------------------------------------
-- UART RECEIVER
-- -------------------------------------------------------------------------
uart_rx_i: entity work.UART_RX
generic map (
PARITY_BIT => PARITY_BIT
)
port map (
CLK => CLK,
RST => RST,
-- UART INTERFACE
UART_CLK_EN => uart_clk_en,
UART_RXD => uart_rxd_debounced,
-- USER DATA OUTPUT INTERFACE
DATA_OUT => DATA_OUT,
DATA_VLD => DATA_VLD,
FRAME_ERROR => FRAME_ERROR
);
end FULL;
| gpl-3.0 |
hiyuh/nvc | test/regress/issue111.vhd | 5 | 1265 | entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test is
port(
A,B,C : in bit_vector(7 downto 0);
D : out bit_vector(7 downto 0)
);
end test;
architecture rtl of test is
begin
ADD_GEN: for I in 0 to 7 generate
L: if I=0 generate--failure is here
U0: entity work.t1
port map(A(I),B(I),'0',D(I));
end generate L;
U: if I>0 generate
UX: entity work.t1
port map(A(I),B(I),C(I-1),D(I));
end generate U;
end generate ADD_GEN;
end rtl;
entity issue111 is
end entity;
architecture test of issue111 is
signal A, B, C : bit_vector(7 downto 0);
signal D : bit_vector(7 downto 0);
begin
uut: entity work.test
port map (
A => A,
B => B,
C => C,
D => D );
process is
begin
wait for 1 ns;
assert D = X"00";
A <= X"ff";
wait for 1 ns;
assert D = X"00";
B <= X"0f";
C <= X"0c";
wait for 1 ns;
assert D = X"08";
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/driver3.vhd | 5 | 444 | entity driver3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver3 is
signal x : std_logic_vector(0 to 0);
begin
x <= "H";
p1: process is
begin
x <= "Z";
wait for 1 ns;
assert x = "H";
x <= "0";
wait for 1 ns;
assert x = "0";
x <= "Z";
wait for 1 ns;
assert x = "H";
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/elab/genagg.vhd | 5 | 1071 | entity genagg_sub_sub is
generic (
DEVA : bit_vector(6 downto 0) );
port (
clk : in bit;
reset : in bit );
end entity;
architecture rtl of genagg_sub_sub is
begin
end architecture;
-------------------------------------------------------------------------------
entity genagg_sub is
generic (
DEVA : bit_vector(6 downto 0) );
port (
clk : in bit;
reset : in bit );
end entity;
architecture rtl of genagg_sub is
begin
slave_i: entity work.genagg_sub_sub
generic map (
DEVA => DEVA )
port map (
clk => clk,
reset => reset );
end architecture;
-------------------------------------------------------------------------------
entity genagg is
end entity;
architecture test of genagg is
signal clk : bit := '0';
signal reset : bit := '1';
begin
uut: entity work.genagg_sub
generic map (
DEVA => "0000101" )
port map (
clk => clk,
reset => reset );
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/lower/issue116.vhd | 4 | 341 | entity issue116 is
end issue116;
architecture behav of issue116 is
signal intstat : BIT_VECTOR (7 DOWNTO 0);
ALIAS INT_int : BIT is intstat(7);
begin
INT_int <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
--intstat(7) <= '1' when (intstat(6 downto 0) and "1111111") /= "0000000";
end behav;
| gpl-3.0 |
hiyuh/nvc | test/group/issue95.vhd | 5 | 289 | entity issue95 is
end entity;
architecture behav of issue95 is
type point is record
x : integer;
z : boolean;
end record point;
type point_array is array(0 to 2) of point;
signal points : point_array := (others => (x => 1, z => true));
begin
end behav;
| gpl-3.0 |
hiyuh/nvc | test/regress/toplevel1.vhd | 5 | 414 | entity toplevel1 is
generic (
WIDTH : integer := 6 );
port (
x : in bit_vector(WIDTH - 1 downto 0);
y : out bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of toplevel1 is
begin
y <= x after 1 ns;
process is
begin
assert x'length = 6;
assert y'length = 6;
assert x = "000000";
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/parse/block.vhd | 4 | 205 | architecture a of e is
begin
b: block is
begin
end block;
c: block is
signal x : integer;
signal y : real;
begin
x <= y;
end block;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/sem/issue105.vhd | 5 | 696 | entity sub is
generic ( GEN : in bit_vector(1 to 3) );
port ( x : in bit_vector(1 to 3) );
end entity;
architecture test of sub is
begin
process (x) is
begin
case x is
when GEN => -- OK in 2008
report "x = GEN";
when others =>
report "x /= GEN";
end case;
end process;
end architecture;
-------------------------------------------------------------------------------
entity issue105 is
end entity;
architecture test of issue105 is
signal s : bit_vector(1 to 3) := "101";
begin
sub_i: entity work.sub
generic map ( "101" )
port map ( s );
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/sem/issue165.vhd | 4 | 236 | package assert_after_missing_type is
end package;
package body assert_after_missing_type is
procedure proc(var : type_t) is
begin
end;
procedure calling_proc is
begin
proc(1); -- Causes SIGABRT
end;
end package body;
| gpl-3.0 |
hiyuh/nvc | test/regress/const5.vhd | 5 | 804 | entity const5 is
end entity;
architecture test of const5 is
subtype byte_t is bit_vector(7 downto 0);
type byte_array_t is array (natural range <>) of byte_t;
procedure popcount_assert
( value : in byte_t;
pop : in integer )
is
variable cnt : natural := 0;
begin
for i in value'range loop
if value(i) = '1' then
cnt := cnt + 1;
end if;
end loop;
report integer'image(cnt);
assert cnt = pop;
end procedure;
begin
stim_p: process is
constant COME_ADDRS : byte_array_t := ( X"08", X"10", X"20" );
begin
for i in 0 to 2 loop
popcount_assert(value => COME_ADDRS(i), pop => 1);
end loop;
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/elab/open.vhd | 5 | 542 | entity open_bot is
port (
i : in integer;
o : out integer;
v : out bit_vector(3 downto 0) := X"f" );
end entity;
architecture test of open_bot is
begin
v(1) <= '0';
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity open_top is
end entity;
architecture test of open_top is
signal x : integer;
begin
uut: entity work.open_bot
port map ( x, open );
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/elab2.vhd | 5 | 764 | entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2 is
end entity;
architecture test of elab2 is
signal a, b, c : integer;
begin
bot1: entity work.elab2_bot
port map ( a, b );
bot2: entity work.elab2_bot
port map ( b, c );
process is
begin
a <= 0;
wait for 1 ns;
assert b = 1;
assert c = 2;
a <= 2;
wait for 1 ns;
assert b = 3;
assert c = 4;
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/case3.vhd | 5 | 1231 | entity case3 is
end entity;
architecture test of case3 is
signal x : bit_vector(3 downto 0);
signal y, z, q : integer;
begin
decode_y: with x select y <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
decode_z: with x(3 downto 0) select z <=
0 when X"0",
1 when X"1",
2 when X"2",
3 when X"3",
4 when X"4",
5 when X"5",
6 when X"6",
7 when X"7",
8 when X"8",
9 when X"9",
10 when X"a",
11 when X"b",
12 when X"c",
13 when X"d",
14 when X"e",
15 when X"f";
stim: process is
begin
wait for 0 ns;
assert y = 0;
assert z = 0;
x <= X"4";
wait for 1 ns;
assert y = 4;
assert y = 4;
x <= X"f";
wait for 1 ns;
assert y = 15;
assert z = 15;
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/case6.vhd | 5 | 619 | entity case6 is
end entity;
architecture test of case6 is
signal x, y : integer;
begin
process (x) is
begin
case x is
when 1 to 5 =>
y <= 1;
when 6 =>
y <= 2;
when 7 to 10 =>
y <= 3;
when others =>
y <= 4;
end case;
end process;
process is
begin
wait for 1 ns;
assert y = 4;
x <= 2;
wait for 1 ns;
assert y = 1;
x <= 10;
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/real3.vhd | 4 | 370 | entity real3 is
end real3;
architecture Behavioral of real3 is
signal value_real : real := -523467.0;
signal value_integer : integer;
begin
process
begin
report "real: " & real'image(value_real);
value_integer <= integer(value_real);
wait for 0 ns;
report "integer: " & integer'image(value_integer);
wait;
end process;
end Behavioral;
| gpl-3.0 |
hiyuh/nvc | test/regress/access1.vhd | 5 | 1592 | entity access1 is
end entity;
architecture test of access1 is
type int_ptr is access integer;
type list;
type list_ptr is access list;
type list is record
link : list_ptr;
value : integer;
end record;
procedure list_add(l : inout list_ptr; v : integer) is
variable n : list_ptr;
begin
n := new list;
n.link := l;
n.value := v;
l := n;
end procedure;
procedure list_print(variable l : in list_ptr) is
begin
if l /= null then
report integer'image(l.all.value);
list_print(l.all.link);
end if;
end procedure;
procedure list_free(l : inout list_ptr) is
variable tmp : list_ptr;
begin
while l /= null loop
tmp := l.all.link;
deallocate(l);
l := tmp;
end loop;
end procedure;
signal p1_done : boolean := false;
type str_ptr is access string;
begin
p1: process is
variable p, q : int_ptr;
begin
assert p = null;
p := new integer;
p.all := 5;
assert p.all = 5;
q := p;
assert q.all = 5;
q.all := 6;
assert p.all = 6;
deallocate(p);
assert p = null;
p1_done <= true;
wait;
end process;
p2: process is
variable l, p : list_ptr;
begin
wait until p1_done;
for i in 1 to 10 loop
list_add(l, i);
end loop;
list_print(l);
list_free(l);
wait;
end process;
end architecture;
| gpl-3.0 |
dobairoland/ZyEHW | hw/hdl/lut_pkg.vhd | 1 | 10601 | -- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use work.zyehw_pkg.all;
package lut_pkg is
subtype lut_t is bit_vector(63 downto 0);
type pe_lut_t is array (cgp_t'reverse_range) of lut_t;
type pe_lut_arr_t is array (0 to (rows-1), 0 to (columns-1)) of pe_lut_t;
-- these are random numbers because otherwise the synthesizer would
-- remove some of the PE items
constant dummy_pe_lut_arr: pe_lut_arr_t:= (
(
(
X"000000005851F42D",
X"40B18CCF4BB5F646",
X"4703312930705B04",
X"20FD5DB41A8B7F78",
X"502959D82B894868",
X"6C0356A708CDB7FF",
X"3477D43F70A3A52B",
X"28E4BAF17D8341FC"
),
(
X"0AE16FD9742D2F7A",
X"0D1F079676035E09",
X"40F7702C6FA72CA5",
X"2AA8415758A0DF74",
X"474A03642E533CC4",
X"04185FAF6DE3B115",
X"0CAB86287043BFA4",
X"398150E937521657"
),
(
X"4D9A2FDB76C3625E",
X"55075020329B54FB",
X"381FC0385378D5A8",
X"76E5004E797D87A6",
X"2756C7144C598D93",
X"643BD7252B449456",
X"671286247899E644",
X"088232DF6DB50559"
),
(
X"7D157D8D71DFED43",
X"45CB977B6EA3BBBE",
X"3A984B90666D9716",
X"6FD595896931589D",
X"17C5E07E0B0ABB77",
X"51AF16C61DEE132F",
X"3B3A772600F32298",
X"5148068835EB8DF5"
),
(
X"7A1179B41AE53A30",
X"7C418DD42170B934",
X"6DB4489D4A691C3A",
X"5A89680D249AD60F",
X"28BAE6BD526D022F",
X"6DE3EDA1559E2FF7",
X"38B9210F072790D9",
X"638391684C1EE2F4"
),
(
X"0D1102D92657C93C",
X"79B12BA855365135",
X"794F06E57091758F",
X"59B5FE2A302059CD",
X"4E8694C26E7B6440",
X"116E0FC138479ACF",
X"23252C5217E96171",
X"40C9FE6A49067A72"
),
(
X"561F3B294FD30023",
X"07D89DB046755A5B",
X"482FA51B44AEB1A3",
X"0D57872A4CBD7E82",
X"235E94882BD25B44",
X"5EC1CC197B5F2B0E",
X"27DE5630302D71F2",
X"47A3556B3C7F6AA3"
),
(
X"7C55D8AE512B300F",
X"2D5E8A842FBE7DCD",
X"2B847F490057B6D6",
X"5DF6E2834B941D42",
X"4CC54C177044FFE7",
X"274A1FA301B18039",
X"7FDF0C93446D8073",
X"6A50ABC676E04EE6"
)
),
(
(
X"00611EF139B7048A",
X"5CFAA8FE26FAAC21",
X"77E1241B0E63C119",
X"29AE8B7E0F90F8E4",
X"755B6B7570C23C8E",
X"72F7FCC6205C9587",
X"43AF20857ABEBC58",
X"1F1B54DD340C3024"
),
(
X"7B7620E675214E9D",
X"5AEC5E5D0CAD3244",
X"587F60406E6AA68B",
X"1FD3905A22C4F223",
X"7C06BA5E0CF05DA9",
X"36745DEF7325D2EC",
X"775CFE3F0E223791",
X"7502199C312FAB7A"
),
(
X"6559AA410BBADF17",
X"2A16DB1800985972",
X"75C9AEEB4EA0C606",
X"1A637BF20DD45F91",
X"227B64EE121412B8",
X"42967A6C4BB1E6BE",
X"1C2099D9500F7B34",
X"7E0D3DF744AC5234"
),
(
X"142FEF23690AE306",
X"6849ED7A25D23D33",
X"426B1E70040E4297",
X"2E03D8D7274EE452",
X"0346C6125E36B2F5",
X"74A7347E742072D2",
X"20F8FF943D044295",
X"0C75DB6622FEFE06"
),
(
X"63D6E1236C52F559",
X"13DE80F246AC426F",
X"6A4677FA1203EEE7",
X"767BB4EC22E2E0A9",
X"467C6EE63E0E58AB",
X"665297AA003A5839",
X"773336BF05DF1FBA",
X"0D20D75F5F6694A5"
),
(
X"2C86C8B15DE2D8AE",
X"7FDD81242AD45A81",
X"14CC39617DC30B8A",
X"521B4C7811305745",
X"4817E9E417E9263C",
X"09EFFE474CBE2C78",
X"7756E63935F58C47",
X"14B17CC737B9759D"
),
(
X"455E81D9476E8C4A",
X"7B6797AF3BCBFD61",
X"0C2CB017268FBB3B",
X"4681C3BD0C7FE26A",
X"080778F52FCBC7D0",
X"000135441E63235B",
X"4272E9912930A9CD",
X"78AB7F5F24308D75"
),
(
X"1B5A7B5F49202F41",
X"2103FBB8713585D5",
X"00D9443830D8D007",
X"289C95FE48D313D8",
X"25A5CD5A391204B1",
X"4170B52F1DE77846",
X"7F31C5BC4206B48E",
X"07BFF03541F7C92A"
)
),
(
(
X"43FF573804D5E4CC",
X"1EDC4A2A7B8D5AAF",
X"28ADC2AF30C25462",
X"5498210F72A45A86",
X"332A78752C2EF355",
X"332EC7743FEC221C",
X"557BAC7028E1EBA3",
X"1F746A094E0C64E3"
),
(
X"40BACB5F48E2ACBE",
X"4DBB1DB34CA91014",
X"7EF0357A1132F327",
X"44C47458033D4927",
X"354A946B1FA92310",
X"17552ED80A7C5CB1",
X"7AB97D104170719A",
X"75D77CAE515A5105"
),
(
X"40A722086FBFE338",
X"55E2DD847DCB6BD6",
X"0A1B990A24872187",
X"242D4A553FCAD87A",
X"03E4E3A35E1DCE75",
X"51F0AA352AEC52BF",
X"1809F23E5A736871",
X"6FE91E6C2322A884"
),
(
X"6DF778271E63DA77",
X"2A81F9C13740F7D1",
X"621F7DC2473FADE0",
X"0ECFD39645480065",
X"562666204BF4E964",
X"57F7686D7936F374",
X"6EE7EB0755EE4C0B",
X"44C1AA5D4F7DF387"
),
(
X"16DC99605368C1DE",
X"0AA98CB7314D8D5D",
X"5964648B6F641684",
X"09F4BA361AF7C2E0",
X"6B1623BB127E9DBF",
X"19CB4497662FBE85",
X"7BDE7EA20E124E0A",
X"7655B2C10945B15A"
),
(
X"232C184841D5CD1C",
X"353B17C935B804C5",
X"407A658958E3CB69",
X"574084D2137883AA",
X"52E8AA321F7189CF",
X"0BEE617173BA11C8",
X"0DF549D77AEC3614",
X"4EF8AE5164D964A2"
),
(
X"247D020667334E8D",
X"5041D31D4075F3CD",
X"5BDD6FED24043DC9",
X"18883FFA157B47C9",
X"39DD7E18032FD357",
X"54487B0545C44367",
X"787D24FD01B60989",
X"12744794780C1CEA"
),
(
X"41C74C53599937BD",
X"679BC6FF08DE2644",
X"68B031DC1ADC60A5",
X"4564152004DA37D5",
X"16BA7DA341D7E24C",
X"5483058E24019394",
X"47D331934CB87DA1",
X"66ADD5246F103874"
)
),
(
(
X"25DCDCCD1B9E331A",
X"16B6A604675D3BA3",
X"14B4777F5A00FD41",
X"31D535FF3F2A8012",
X"213AF44F6EF45642",
X"0699F098734AC0CB",
X"548DEE737DE2F6F6",
X"1E6741F97A6FD954"
),
(
X"4D4CC8B3057449D4",
X"29741EEC41EC94B5",
X"331D901E32D7FE82",
X"5320437F3FF66956",
X"53F9DE63159D897B",
X"23C6A5604E29C9A7",
X"4F55C1AA6AAB997F",
X"04AC6CAC7B0948E1"
),
(
X"706B2BF03016C8E4",
X"7D091D3877807C4D",
X"571F0866378B963A",
X"0939171E548D45B7",
X"55809B502B0DB4AA",
X"1362976702622738",
X"066826E04163ABEE",
X"04F1C4B64A9F4466"
),
(
X"2D51B68C7533D847",
X"66DB2F8334473607",
X"724FC8C36548DF64",
X"73C895C319C78C0C",
X"51350DEA44078660",
X"63467E4861438AEE",
X"507271666AF75183",
X"0ECCACAB3DD5EE27"
),
(
X"5FB6CF733072F75C",
X"20FF0A9439E75E18",
X"3C1F66D73D586049",
X"3DF0F31F1B3E3D30",
X"66E3E98129FDC121",
X"49830FCD0E41EB0D",
X"530ED0D91C0A5D46",
X"5881E8714B6DDDB1"
),
(
X"1D72EB9A28E05172",
X"6E0AE02A03F0C525",
X"1CB139113CB18F8C",
X"4F808C811F456E1A",
X"4295AAD467A9332D",
X"2417D13456AA68AA",
X"61BC0768418EC1AC",
X"256A1E7670378A72"
),
(
X"727578810F9B9D87",
X"0C6F008B5567B32B",
X"34767B5A6FED3F2F",
X"713F4226417A91BE",
X"023E7BDE21A91AEC",
X"528456BF2A595A38",
X"10A600AD334BDFB0",
X"706032DF3B920BA3"
),
(
X"11C4790D7F6FFC29",
X"6876FDC834B73C6F",
X"7ED693DF4AED9078",
X"286DF60642E7DDB8",
X"27AB01843AE8CB0A",
X"5AB80872141285A2",
X"6903382A4658B84C",
X"4B1103AE3950E877"
)
)
);
end;
package body lut_pkg is
end package body;
| gpl-3.0 |
hiyuh/nvc | test/elab/bounds10.vhd | 5 | 642 | entity UC is
port(
an_input: in bit_vector;
an_output: out bit_vector
);
end entity;
architecture test of UC is
begin
an_output <= an_input;
end architecture;
-------------------------------------------------------------------------------
entity bounds10 is
end entity;
architecture test of bounds10 is
signal an_input: bit_vector( 0 downto 0);
signal an_output: bit_vector(100 downto 0);
begin
UC:
entity work.UC
port map
(
an_input => an_input,
an_output => an_output
);
TEST:
an_input <= "0", "1" after 1 ns;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/issue79.vhd | 5 | 976 | package access_bug is
type integer_access is access integer;
type integer_access_array is array (natural range <>) of integer_access;
end package;
package body access_bug is
function bug_function return integer_access_array is
variable bug_here : integer_access_array(0 to 0);
begin
return bug_here;
end function;
end package body;
entity issue79 is
end entity;
use work.access_bug.all;
architecture test of issue79 is
function make_ptrs(init : integer) return integer_access_array is
variable r : integer_access_array(1 to 5);
begin
for i in r'range loop
r(i) := new integer'(init);
end loop;
return r;
end function;
begin
process is
variable p : integer_access_array(1 to 5);
begin
assert p = (1 to 5 => null);
p := make_ptrs(2);
for i in p'range loop
assert p(i).all = 2;
end loop;
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/implicit1.vhd | 5 | 548 | entity implicit1 is
end entity;
architecture test of implicit1 is
signal x : natural;
begin
x <= 1 after 1 ns,
2 after 2 ns,
3 after 3 ns;
process is
begin
assert x = 0;
assert x'delayed = 0;
wait for 1 ns;
assert x = 1;
assert x'delayed = 0;
wait for 0 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 0;
wait for 1 ns;
assert x'delayed = 1;
assert x'delayed(1 ns) = 1;
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/parse/based.vhd | 3 | 326 | package p is
constant a : integer := 2#1101#;
constant b : integer := 3#20#;
constant c : integer := 8#7#;
constant d : integer := 10#1234#;
constant e : integer := 16#beef01#;
constant f : integer := 2#1_0#;
constant g : integer := 2:1_0:;
constant h : integer := 16#abababab#;
end package;
| gpl-3.0 |
hiyuh/nvc | test/sem/spec.vhd | 4 | 1248 | entity c1_ent1 is
end entity;
-------------------------------------------------------------------------------
package p is
end package;
-------------------------------------------------------------------------------
entity e is
end entity;
architecture a of e is
component c1 is
end component;
component c2 is
end component;
for i1: c2 use entity work.c1_ent1; -- Error
for i1: e use entity work.c1_ent1; -- Error
for i1: c1 use entity work.c1_ent1; -- OK
for bad: c1 use entity work.c1_ent1; -- Error
for i2: c1 use entity work.c1_ent1; -- Error
for i1: c1 use entity work.c1_ent1; -- Error
for i3: c1 use entity work.not_here; -- Error
for i3: c1 use entity work.p; -- Error
for all: c2 use entity work.c1_ent1; -- OK
for i5: c1 use entity work.c1_ent1; -- Error
for all: c2 use entity work.c1_ent1; -- Error
for others: c1 use entity work.c1_ent1; -- OK
for i7: c1 use open; -- OK
begin
i1: component c1;
i2: entity work.e;
i3: component c1;
i4: component c2;
b1: block is
begin
i5: component c1;
end block;
i6: component c1;
i7: component c1;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/parse/concat.vhd | 4 | 213 | architecture a of b is
signal x : bit_vector(1 to 3);
signal y : bit_vector(1 to 2);
begin
x <= y & '0';
process is
begin
p := q & g & ('1', '1');
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/func17.vhd | 5 | 477 | entity func17 is
end entity;
architecture test of func17 is
function func(x : bit_vector) return bit_vector is
variable y : bit_vector(1 to x'length) := x;
begin
y(1 + x'length / 2) := '1'; -- Would corrupt X
return y;
end function;
begin
process is
variable b : bit_vector(1 to 3);
begin
b := "101";
assert func(b) = "111";
assert b = "101";
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/issue104.vhd | 5 | 590 | ENTITY dummy IS PORT(
i : IN bit;
o : OUT bit );
END ENTITY dummy;
ARCHITECTURE arch OF dummy IS
BEGIN
o <= i;
END ARCHITECTURE arch;
ENTITY issue104 IS
END ENTITY issue104;
ARCHITECTURE arch OF issue104 IS
SIGNAL v : bit_vector(4 DOWNTO 0);
BEGIN
fold : FOR i IN 0 TO 3 GENERATE
BEGIN
dummy : ENTITY work.dummy PORT MAP(
i => v(i+1),
o => v(i)
);
END GENERATE fold;
process is
begin
v(4) <= '1';
wait for 1 ns;
assert v(0) = '1';
wait;
end process;
END ARCHITECTURE arch;
| gpl-3.0 |
dobairoland/ZyEHW | hw/hdl/image_window.vhd | 1 | 2988 | -- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use work.zyehw_pkg.all;
entity image_window is
port (
clk: in std_logic;
en: in std_logic;
input: in cgp_t;
redundant_kernel_pixels: out cgp_input_redundant_t
);
end image_window;
architecture behav_image_window of image_window is
signal serial_img: serial_img_t;
signal tmp_pixels: cgp_input_redundant_t;
-- The don_touch attribute should be on the signal which is duplicated
-- into redundant registers. However cannot be placed on the inner
-- registers because the synthesizer would add weird proxy LUTs.
-- Therefore, an individual registered temporary signal should be used.
attribute dont_touch: string;
attribute dont_touch of tmp_pixels: signal is "true";
begin
process (clk)
begin
if clk'event and clk = '1' then
if en = '1' then
serial_img(0) <= input;
for i in 1 to (serial_img_t'length-1) loop
serial_img(i) <= serial_img(i-1);
end loop;
-- This will generate the actual redundant registers
redundant_kernel_pixels <= tmp_pixels;
end if;
end if;
end process;
-- We generate a temporary signal which is a predecessor of the output
-- register.
kernel_row: for i in 0 to (img_kernel-1) generate
kernel_column: for j in 0 to (img_kernel-1) generate
constant src_ind: integer:= serial_img_t'length-1-j-i*img_size;
constant dst_ind: integer:= j+i*img_kernel;
begin
kernel_redundant: for k in tmp_pixels'range generate
redund_from_input: if src_ind = 0 generate
tmp_pixels(k)(dst_ind) <= input;
-- because previously this was used:
-- serial_img(0) <= input;
end generate;
other_redundats: if src_ind > 0 generate
tmp_pixels(k)(dst_ind) <= serial_img(src_ind - 1);
-- minus one because serial_image is generated
-- like this: serial_img(i) <= serial_img(i-1)
end generate;
end generate;
end generate;
end generate;
end behav_image_window;
| gpl-3.0 |
hiyuh/nvc | test/elab/comp.vhd | 5 | 1733 | entity e1 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e2 is
generic ( g : integer );
port (
x : in integer );
end entity;
architecture test of e2 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e3 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e3 is
begin
end architecture;
-------------------------------------------------------------------------------
entity foo is
end entity;
architecture test of foo is
component e1 is
generic (
g : integer);
port (
x : in integer;
y : out integer);
end component;
component e2 is
generic (
g : integer);
port (
y : out integer);
end component;
component e3 is
generic (
g : integer);
port (
x : in bit;
y : out integer);
end component;
signal x : integer;
signal y : integer;
begin
e1_1: e1 -- OK
generic map (
g => 5 )
port map (
x => x,
y => y);
e2_1: e2 -- Error
generic map (
g => 5 )
port map (
y => y);
e3_1: e3 -- Error
generic map (
g => 5 )
port map (
x => '1',
y => y);
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/proc6.vhd | 5 | 573 | entity proc6 is
end entity;
architecture test of proc6 is
procedure delay(signal x : out integer;
signal y : in integer;
constant d : in delay_length) is
begin
x <= y after d;
end procedure;
signal a, b : integer;
begin
foo: delay(a, b, 10 ns);
check: process is
begin
b <= 6;
wait for 11 ns;
assert a = 6;
b <= 7;
wait for 5 ns;
assert a = 6;
wait for 5 ns;
assert a = 7;
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/sem/issue128.vhd | 5 | 400 | package A_NG is
procedure PROC(SEL: in integer);
end package;
package body A_NG is
procedure PROC(SEL: in integer) is
begin
case SEL is
when 0 | 1 => -- Used to crash in sem_hoist_for_loop_var
for i in 0 to 3 loop
end loop;
when others =>
null;
end case;
end procedure;
end package body;
| gpl-3.0 |
hiyuh/nvc | test/regress/signal4.vhd | 5 | 728 | entity signal4 is
end entity;
architecture test of signal4 is
signal s : bit_vector(3 downto 0) := (1 => '1', others => '0');
begin
process is
variable v : bit_vector(3 downto 0) := (others => '1');
begin
assert s(0) = '0';
assert s(1) = '1';
assert v(1) = '1';
v(2) := s(3);
assert v(2) = '0';
s(0) <= v(3);
assert s(0) = '0';
wait for 1 ns;
assert v(3) = '1';
assert s(0) = v(3);
assert v = ( '1', '0', '1', '1' );
s <= v;
assert s = ( '0', '0', '1', '1' ) report "one";
wait for 1 ns;
assert s = ( '1', '0', '1', '1' ) report "two";
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/lower/signal1.vhd | 4 | 212 | entity signal1 is
end entity;
architecture test of signal1 is
signal x : integer := 5;
begin
process is
begin
assert x = 5;
x <= 6;
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/elab/ifgen.vhd | 5 | 472 | entity sub is
generic (
foo : boolean := true );
port (
x : out integer );
end entity;
architecture test of sub is
begin
g: if foo = true generate
x <= 5;
end generate;
end architecture;
-------------------------------------------------------------------------------
entity ifgen is
end entity;
architecture test of ifgen is
signal x : integer;
begin
sub_i: entity work.sub
port map ( x );
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/parse/access.vhd | 4 | 206 | architecture a of e is
begin
process is
begin
x.all := 1;
v := x.all + 5;
p := new t;
p := a.all(1 to 3);
q := a.all(3);
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/sem/interfaces.vhd | 3 | 1255 | use std.textio.all;
package interfaces is
component comp1 is
port (
signal p1 : integer; -- OK
p2 : integer -- OK
);
end component;
component comp2 is
port (variable p : integer); -- Error
end component;
component comp3 is
port (constant p : integer); -- Error
end component;
component comp4 is
port (file p : text); -- Error
end component;
component comp5 is
generic (constant p1 : integer; -- OK
p2 : integer);-- OK
end component;
component comp5 is
generic (signal p : integer); -- Error
end component;
component comp5 is
generic (variable p : integer); -- Error
end component;
component comp5 is
generic (file p : text); -- Error
end component;
procedure proc1(c : buffer integer); -- Error
procedure proc2(c : linkage integer); -- Error
procedure proc3(constant c : inout integer); -- Error
procedure proc3(constant c : out integer); -- Error
procedure proc4(file c : integer); -- Error
procedure proc5(constant c : text); -- Error
end package interfaces;
| gpl-3.0 |
hiyuh/nvc | test/regress/issue53.vhd | 5 | 441 | entity c is
generic (e : bit);
port (i : in bit);
begin
assert i = e;
end entity c;
architecture a of c is
begin
end architecture a;
entity issue53 is
begin
end entity issue53;
architecture a of issue53 is
component c is
generic (e : bit);
port (i : in bit);
end component c;
begin
u0 : c generic map ('0') port map (i => '0');
u1 : c generic map ('1') port map (i => '1');
end architecture a;
| gpl-3.0 |
hiyuh/nvc | test/elab/elab3.vhd | 5 | 1328 | package p is
function log2(x : in integer) return integer;
end package;
package body p is
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
end package body;
-------------------------------------------------------------------------------
entity sub is
generic ( W : integer );
end entity;
use work.p.all;
architecture test of sub is
constant B : integer := log2(W);
signal s : bit_vector(B - 1 downto 0);
constant C : bit_vector(log2(B) to 1) := (others => '0');
begin
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
architecture test of top is
begin
s : entity work.sub
generic map ( 10 );
end architecture;
-------------------------------------------------------------------------------
use work.p.all;
entity top2 is
end entity;
architecture test of top2 is
constant W : integer := 10;
constant B : integer := log2(W);
signal s : bit_vector(B - 1 downto 0);
begin
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/attr2.vhd | 5 | 617 | entity attr2 is
end entity;
architecture test of attr2 is
type int3d is array (natural range <>,
natural range <>,
natural range <>) of integer;
procedure foo(x : in int3d) is
begin
assert x'length(1) = 2;
assert x'length(2) = 2;
assert x'length(3) = 10;
end procedure;
begin
process is
variable v : int3d(1 to 2, 1 downto 0, 10 to 19);
begin
assert v'length(1) = 2;
assert v'length(2) = 2;
assert v'length(3) = 10;
foo(v);
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/parse/bitstring.vhd | 3 | 307 | package bitstring is
constant x : t := X"1234";
constant y : t := O"1234";
constant z : t := X"ab";
constant b : t := B"101";
constant c : t := x"f";
constant d : t := X"a_b";
end package;
package bitstring_error is
constant e1 : t := O"9"; -- Error
end package;
| gpl-3.0 |
hiyuh/nvc | test/regress/cover1.vhd | 5 | 527 | entity cover1 is
end entity;
architecture test of cover1 is
signal s : integer;
begin
process is
variable v : integer;
begin
v := 1;
s <= 2;
wait for 1 ns;
if s = 2 or s > 10 then
v := 3;
else
v := 2;
end if;
while v > 0 loop
if v mod 2 = 0 then
v := v - 1;
else
v := (v / 2) * 2;
end if;
end loop;
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/bounds16.vhd | 5 | 504 | entity bounds16 is
end entity;
architecture test of bounds16 is
function add_nat(x : in integer) return natural is
variable r : natural := x;
begin
return r + 1;
end function;
begin
process is
variable x : integer;
begin
x := 5;
report integer'image(add_nat(x));
x := 0;
report integer'image(add_nat(x));
x := -1;
report integer'image(add_nat(x)); -- Error
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/bounds3.vhd | 5 | 220 | entity bounds3 is
end entity;
architecture test of bounds3 is
type int_vec is array (natural range <>) of integer;
signal s : int_vec(5 to 7);
signal k : integer;
begin
s(k) <= 61;
end architecture;
| gpl-3.0 |
dobairoland/ZyEHW | hw/hdl/gray2binary.vhd | 1 | 1582 | -- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
entity gray2binary is
generic (
WIDTH: integer
);
port (
clk: in std_logic;
input: in std_logic_vector(WIDTH-1 downto 0);
output: out std_logic_vector(WIDTH-1 downto 0)
);
end gray2binary;
architecture behav_gray2binary of gray2binary is
signal output_reg: std_logic_vector(output'range):= (others => '0');
begin
output <= output_reg;
process (clk)
variable tmp_out: std_logic_vector(output'range);
begin
if clk'event and clk = '1' then
tmp_out:= (others => '0');
for i in output'range loop
for j in i to output'high loop
tmp_out(i):= tmp_out(i) xor input(j);
end loop;
end loop;
output_reg <= tmp_out;
end if;
end process;
end behav_gray2binary;
| gpl-3.0 |
hiyuh/nvc | test/parse/generate.vhd | 4 | 842 | architecture a of g is
begin
g1: if foo generate
signal x : integer;
begin
x <= 5;
end generate;
g2: if bar generate
g2a: if x < 5 generate
g <= 7;
end generate;
end generate;
g3: for i in 1 to 40 generate
signal x : integer;
begin
f <= h;
end generate;
g4: for i in x'range generate
end generate;
g5: for i in x'range generate
begin
end generate;
g6: for i in 1 to 3 generate
component sub_ent is
port (val: out natural);
end component sub_ent; -- OK
begin
end generate;
g7: if true generate
procedure doit is -- OK
begin
write(OUTPUT, "OK." & LF);
end procedure doit;
begin
end generate g7;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/issue57.vhd | 4 | 634 | package issueH is
constant c : bit_vector;
end package issueH;
package body issueH is
pure function f (
i : bit_vector;
l : integer range 1 to integer'high
) return bit_vector is
variable v : bit_vector(i'length-1 downto 0);
begin
v := i;
return v(l-1 downto 0);
end function f;
constant c : bit_vector := f(X"1F", 5);
end package body issueH;
entity issue57 is
end entity;
use work.issueH.all;
architecture test of issue57 is
begin
process is
begin
assert c'length = 5;
assert c = "11111";
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/access7.vhd | 4 | 905 | entity access7 is
end entity;
architecture test of access7 is
type int_ptr is access integer;
type int_ptr_ptr is access int_ptr;
type int_ptr_array is array (integer range <>) of int_ptr;
type int_ptr_array_ptr is access int_ptr_array;
procedure alloc_ptr(x : out int_ptr_ptr) is
begin
x := new int_ptr;
end procedure;
procedure alloc_ptr_array(x : out int_ptr_array_ptr) is
begin
x := new int_ptr_array(1 to 3);
end procedure;
begin
process is
variable pp : int_ptr_ptr;
variable pa : int_ptr_array_ptr;
begin
alloc_ptr(pp);
assert pp.all = null;
pp.all := new integer'(4);
assert pp.all.all = 4;
alloc_ptr_array(pa);
assert pa.all = (null, null, null);
pa(1) := new integer'(6);
assert pa(1).all = 6;
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/bounds10.vhd | 5 | 334 | entity bounds10 is
end entity;
architecture test of bounds10 is
begin
process is
variable n : integer;
variable a : bit_vector(3 downto 0);
variable b : bit_vector(7 downto 0);
begin
n := 7;
wait for 1 ns;
a := b(n downto 0);
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/alias5.vhd | 5 | 1222 | entity alias5 is
end entity;
architecture test of alias5 is
subtype bit_vector4 is bit_vector(3 downto 0);
type footype is ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0x, trx1, tr1x, trx0, trxz, trzx);
type bartype01 is array (footype range tr01 to tr10)
of time;
type yahtype01 is array (natural range <>) of bartype01;
procedure bufpath (
constant tpd : in yahtype01
) is
begin
report "tpd'left=" & integer'image(tpd'left);
report "tpd'right=" & integer'image(tpd'right);
end;
procedure vitalmux4 (
variable data : in bit_vector4;
constant tpd_data_q : in yahtype01
) is
alias atpd_data_q : yahtype01(data'range) is tpd_data_q;
begin
bufpath ( atpd_data_q );
assert atpd_data_q(data'left)(tr01) = 1 ns;
assert atpd_data_q(3 downto 3)(3)(tr01) = 1 ns;
end;
begin
process is
variable data : bit_vector4;
variable yah : yahtype01(5 downto 2);
begin
data := X"1";
yah := (others => (others => 1 ns ) );
vitalmux4(data, yah);
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/record11.vhd | 5 | 696 | entity record11 is
end entity;
architecture test of record11 is
type rec is record
x, y : bit;
end record;
signal r : rec;
signal a, b : bit;
begin
process is
begin
r <= ( '1', '0' );
wait for 0 ns;
assert r.x'event;
assert not r.y'event;
assert r.y'active;
assert r'event;
wait for 1 ns;
assert a'event;
assert not b'event;
assert b'active;
assert a = '1';
assert b = '0';
r.y <= '1';
wait for 1 ns;
assert b = '1';
wait;
end process;
update_a: a <= r.x after 1 ns;
update_b: b <= r.y after 1 ns;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/wait4.vhd | 5 | 649 | entity wait4 is
end entity;
architecture test of wait4 is
signal x, y, z : bit;
begin
proc_a: process is
begin
wait for 1 ns;
y <= '1';
wait for 1 ns;
z <= '1';
wait for 1 ns;
assert x = '1';
wait;
end process;
proc_b: process is
begin
wait on x, y;
assert y = '1';
assert now = 1 ns;
assert y'event report "not y'event";
assert not x'event report "x'event";
wait on z;
assert not x'event;
assert z'event;
assert z = '1';
x <= '1';
wait;
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/counter.vhd | 5 | 920 | entity counter_bot is
port (
clk : in bit;
count : out integer );
end entity;
architecture behav of counter_bot is
begin
process (clk) is
variable count_var : integer := 0;
begin
if clk'event and clk = '1' then
count_var := count_var + 1;
count <= count_var;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
entity counter is
end entity;
architecture test of counter is
signal clk : bit := '0';
signal count : integer := 0;
begin
clkgen: process is
begin
wait for 5 ns;
clk <= not clk;
end process;
uut: entity work.counter_bot
port map (
clk => clk,
count => count );
process (count) is
begin
report integer'image(count);
end process;
end architecture;
| gpl-3.0 |
hiyuh/nvc | test/regress/wait5.vhd | 5 | 474 | entity wait5 is
end entity;
architecture test of wait5 is
signal x, y : integer := 0;
begin
a: process (x) is
begin
y <= y + 1;
end process;
b: process is
begin
wait for 1 ns;
assert y = 1;
x <= 1;
wait for 1 ns;
x <= 0;
wait for 1 ns;
assert y = 3;
x <= 0;
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
| gpl-3.0 |
freecores/usb_fpga_2_16 | examples/usb-fpga-1.15/1.15b/lightshow/fpga/lightshow.vhd | 36 | 2235 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led : out std_logic_vector(11 downto 0);
CLK : in std_logic -- 32 MHz
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern is array(11 downto 0) of integer range 0 to 15;
signal pattern1 : tPattern := (0, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2, 1);
signal pattern2 : tPattern := (6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5);
signal pattern3 : tPattern := (0, 1, 4, 9, 4, 1, 0, 0, 0, 0, 0, 0);
type tXlatTable1 is array(0 to 12) of integer range 0 to 1023;
constant xt1 : tXlatTable1 := (0, 0, 1, 4, 13, 31, 64, 118, 202, 324, 493, 722, 1023);
type tXlatTable2 is array(0 to 9) of integer range 0 to 255;
--constant xt2 : tXlatTable2 := (0, 1, 11, 38, 90, 175, 303, 481, 718, 1023);
constant xt2 : tXlatTable2 := (0, 0, 3, 9, 22, 44, 76, 120, 179, 255);
signal cp1 : std_logic_vector(22 downto 0);
signal cp2 : std_logic_vector(22 downto 0);
signal cp3 : std_logic_vector(22 downto 0);
signal d : std_logic_vector(16 downto 0);
begin
dpCLK: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( cp1 = conv_std_logic_vector(3000000,23) )
then
pattern1(10 downto 0) <= pattern1(11 downto 1);
pattern1(11) <= pattern1(0);
cp1 <= (others => '0');
else
cp1 <= cp1 + 1;
end if;
if ( cp2 = conv_std_logic_vector(2200000,23) )
then
pattern2(10 downto 0) <= pattern2(11 downto 1);
pattern2(11) <= pattern2(0);
cp2 <= (others => '0');
else
cp2 <= cp2 + 1;
end if;
if ( cp3 = conv_std_logic_vector(1500000,23) )
then
pattern3(11 downto 1) <= pattern3(10 downto 0);
pattern3(0) <= pattern3(11);
cp3 <= (others => '0');
else
cp3 <= cp3 + 1;
end if;
if ( d = conv_std_logic_vector(1278*64-1,17) )
then
d <= (others => '0');
else
d <= d + 1;
end if;
for i in 0 to 11 loop
if ( d(16 downto 6) < conv_std_logic_vector( xt1(pattern1(i) + pattern2(i)) + xt2(pattern3(i)) ,11) )
then
led(i) <= '1';
else
led(i) <= '0';
end if;
end loop;
end if;
end process dpCLK;
end RTL;
| gpl-3.0 |
freecores/usb_fpga_2_16 | examples/usb-fpga-1.15/1.15d/lightshow/fpga/lightshow.vhd | 36 | 2235 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led : out std_logic_vector(11 downto 0);
CLK : in std_logic -- 32 MHz
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern is array(11 downto 0) of integer range 0 to 15;
signal pattern1 : tPattern := (0, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2, 1);
signal pattern2 : tPattern := (6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5);
signal pattern3 : tPattern := (0, 1, 4, 9, 4, 1, 0, 0, 0, 0, 0, 0);
type tXlatTable1 is array(0 to 12) of integer range 0 to 1023;
constant xt1 : tXlatTable1 := (0, 0, 1, 4, 13, 31, 64, 118, 202, 324, 493, 722, 1023);
type tXlatTable2 is array(0 to 9) of integer range 0 to 255;
--constant xt2 : tXlatTable2 := (0, 1, 11, 38, 90, 175, 303, 481, 718, 1023);
constant xt2 : tXlatTable2 := (0, 0, 3, 9, 22, 44, 76, 120, 179, 255);
signal cp1 : std_logic_vector(22 downto 0);
signal cp2 : std_logic_vector(22 downto 0);
signal cp3 : std_logic_vector(22 downto 0);
signal d : std_logic_vector(16 downto 0);
begin
dpCLK: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( cp1 = conv_std_logic_vector(3000000,23) )
then
pattern1(10 downto 0) <= pattern1(11 downto 1);
pattern1(11) <= pattern1(0);
cp1 <= (others => '0');
else
cp1 <= cp1 + 1;
end if;
if ( cp2 = conv_std_logic_vector(2200000,23) )
then
pattern2(10 downto 0) <= pattern2(11 downto 1);
pattern2(11) <= pattern2(0);
cp2 <= (others => '0');
else
cp2 <= cp2 + 1;
end if;
if ( cp3 = conv_std_logic_vector(1500000,23) )
then
pattern3(11 downto 1) <= pattern3(10 downto 0);
pattern3(0) <= pattern3(11);
cp3 <= (others => '0');
else
cp3 <= cp3 + 1;
end if;
if ( d = conv_std_logic_vector(1278*64-1,17) )
then
d <= (others => '0');
else
d <= d + 1;
end if;
for i in 0 to 11 loop
if ( d(16 downto 6) < conv_std_logic_vector( xt1(pattern1(i) + pattern2(i)) + xt2(pattern3(i)) ,11) )
then
led(i) <= '1';
else
led(i) <= '0';
end if;
end loop;
end if;
end process dpCLK;
end RTL;
| gpl-3.0 |
peladex/RHD2132_FPGA | src/params_reg_bank/params_reg_bank.vhd | 1 | 6323 | -----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 13/11/2016 -- dd/mm/yyyy
-- Module Name: params_reg_bank
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Banco de registros para almacenar los parametros de configuracion de los chips.
-- Las entradas input_* son de 8 bits y permiten modificar el parametro a configurar
-- Las saludas output_* son de 16 bits y representan el comando que se debe enviar al
-- chip para cargar el parametro de confiuracion.
-- El comando a enviar es:
-- WRITE(R,D) Write data D to register R
--
-- MSB LSB
-- | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
-- | 1 | 0 | R[5]| R[4]| R[3]| R[2]| R[1]| R[0]| D[7]| D[6]| D[5]| D[4]| D[3]| D[2]| D[1]| D[0] |
--
--
-----------------------------------------------------------------------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY params_reg_bank IS
PORT(
clk : in std_logic;
rst : in std_logic;
-- chip 1 --
input_chip_1 : in std_logic_vector(7 downto 0);
select_chip_1 : in std_logic_vector(6 downto 0);
output_chip_1 : out std_logic_vector(15 downto 0);
wren_chip_1 : in std_logic;
-- chip 2 --
input_chip_2 : in std_logic_vector(7 downto 0);
select_chip_2 : in std_logic_vector(6 downto 0);
output_chip_2 : out std_logic_vector(15 downto 0);
wren_chip_1 : in std_logic
);
END test_maquina_control;
ARCHITECTURE behav of params_reg_bank IS
-- signals
signal chip_1_reg_00 : std_logic_vector(7 downto 0); --adr: 00
signal chip_1_reg_01 : std_logic_vector(7 downto 0); --adr: 01
signal chip_1_reg_02 : std_logic_vector(7 downto 0); --adr: 02
signal chip_1_reg_03 : std_logic_vector(7 downto 0); --adr: 03
signal chip_1_reg_04 : std_logic_vector(7 downto 0); --adr: 04
signal chip_1_reg_05 : std_logic_vector(7 downto 0); --adr: 05
signal chip_1_reg_06 : std_logic_vector(7 downto 0); --adr: 06
signal chip_1_reg_07 : std_logic_vector(7 downto 0); --adr: 07
signal chip_1_reg_08 : std_logic_vector(7 downto 0); --adr: 08
signal chip_1_reg_09 : std_logic_vector(7 downto 0); --adr: 09
signal chip_1_reg_10 : std_logic_vector(7 downto 0); --adr: 10
signal chip_1_reg_11 : std_logic_vector(7 downto 0); --adr: 11
signal chip_1_reg_12 : std_logic_vector(7 downto 0); --adr: 12
signal chip_1_reg_13 : std_logic_vector(7 downto 0); --adr: 13
signal chip_1_reg_14 : std_logic_vector(7 downto 0); --adr: 14
signal chip_1_reg_15 : std_logic_vector(7 downto 0); --adr: 15
signal chip_1_reg_16 : std_logic_vector(7 downto 0); --adr: 16
signal chip_1_reg_17 : std_logic_vector(7 downto 0); --adr: 17
signal chip_2_reg_00 : std_logic_vector(7 downto 0); --adr: 20
signal chip_2_reg_01 : std_logic_vector(7 downto 0); --adr: 21
signal chip_2_reg_02 : std_logic_vector(7 downto 0); --adr: 22
signal chip_2_reg_03 : std_logic_vector(7 downto 0); --adr: 23
signal chip_2_reg_04 : std_logic_vector(7 downto 0); --adr: 24
signal chip_2_reg_05 : std_logic_vector(7 downto 0); --adr: 25
signal chip_2_reg_06 : std_logic_vector(7 downto 0); --adr: 26
signal chip_2_reg_07 : std_logic_vector(7 downto 0); --adr: 27
signal chip_2_reg_08 : std_logic_vector(7 downto 0); --adr: 28
signal chip_2_reg_09 : std_logic_vector(7 downto 0); --adr: 29
signal chip_2_reg_10 : std_logic_vector(7 downto 0); --adr: 30
signal chip_2_reg_11 : std_logic_vector(7 downto 0); --adr: 31
signal chip_2_reg_12 : std_logic_vector(7 downto 0); --adr: 32
signal chip_2_reg_13 : std_logic_vector(7 downto 0); --adr: 33
signal chip_2_reg_14 : std_logic_vector(7 downto 0); --adr: 34
signal chip_2_reg_15 : std_logic_vector(7 downto 0); --adr: 35
signal chip_2_reg_16 : std_logic_vector(7 downto 0); --adr: 36
signal chip_2_reg_17 : std_logic_vector(7 downto 0); --adr: 37
BEGIN
read_write_reg_bank_1 : process()
begin
if rst = '1' then
-- default value --
chip_1_reg_00 => X"DE";
chip_1_reg_01 => X"60";
chip_1_reg_02 => X"28";
chip_1_reg_03 => X"00";
chip_1_reg_04 => X"00";
chip_1_reg_05 => X"00";
chip_1_reg_06 => X"00";
chip_1_reg_07 => X"00";
chip_1_reg_08 => X"26";
chip_1_reg_09 => X"1A";
chip_1_reg_10 => X"05";
chip_1_reg_11 => X"1F";
chip_1_reg_12 => X"16";
chip_1_reg_13 => X"7C";
chip_1_reg_14 => X"FF";
chip_1_reg_15 => X"FF";
chip_1_reg_16 => X"FF";
chip_1_reg_17 => X"FF";
elsif m_clk'event and m_clk = '1' then
if wren_chip_1 = '1' then
case select_chip_1
else
end if;
end if;
end process;
read_write_reg_bank_2 : process()
begin
if rst = '1' then
-- default value --
chip_2_reg_00 => X"DE";
chip_2_reg_01 => X"60";
chip_2_reg_02 => X"28";
chip_2_reg_03 => X"00";
chip_2_reg_04 => X"00";
chip_2_reg_05 => X"00";
chip_2_reg_06 => X"00";
chip_2_reg_07 => X"00";
chip_2_reg_08 => X"26";
chip_2_reg_09 => X"1A";
chip_2_reg_10 => X"05";
chip_2_reg_11 => X"1F";
chip_2_reg_12 => X"16";
chip_2_reg_13 => X"7C";
chip_2_reg_14 => X"FF";
chip_2_reg_15 => X"FF";
chip_2_reg_16 => X"FF";
chip_2_reg_17 => X"FF";
elsif m_clk'event and m_clk = '1' then
if wren_chip_1 = '1' then
case select_chip_1
else
end if;
end if;
end process;
END behav;
| gpl-3.0 |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia_save/rs232in.vhd | 1 | 7432 | -- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: rs232in.vhd 325 2015-06-03 12:47:32Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/rs232in.vhd $
-- $Author : Ivan Auge (Email: [email protected])
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
-------------------------------------------------------------------------------
-- Ce module désérialise l'entrée RX dans la sortie DATA de 8 bits.
--
-- le format lu est:
-- - 1 start bit
-- - 8 bit de données
-- - 1 ou plusieurs stop bits
--
-- Ce module met NDATA à 1 pendant un cycle quand une nouvelle
-- valeur est présente sur DATA d'où le chronogramme suivant
-- avec A, B et C des valeurs stables de NDATA.
-- La valeur reste stable pendant un BAUD.
--
-- NDATA 0000100000000000000000001000000000000000100000000000
-- DATA ????AAAAA???????????????BBBBB???????????CCCCC???????
--
-- Pour fixer le BAUD du composant utilisez les paramètres génériques
-- BAUD et FREQ ci dessous.
-------------------------------------------------------------------------------
library IEEE ;
use IEEE.std_logic_1164.all ;
entity rs232in is
generic(
FREQ : integer := 50000000; -- Frequence de clk
BAUD : integer := 9600); -- Baud de Rx
port(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
rx : IN STD_LOGIC;
Ndata : OUT STD_LOGIC;
Data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-- debug
debug : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end rs232in;
architecture montage of rs232in is
signal CMD_sh: STD_LOGIC; -- 0:noop, 1:shift
signal R_sh: STD_LOGIC_VECTOR(7 DOWNTO 0);
type T_CMD_baud is (COUNT, INIT1P5B, INIT1B) ;
signal CMD_baud: T_CMD_baud;
signal VT_baud: STD_LOGIC;
signal R_baud: INTEGER RANGE 0 TO (2*FREQ)/BAUD;
type T_CMD_i is (NOOP, COUNT, INIT);
signal CMD_i: T_CMD_i;
signal R_i: INTEGER RANGE 0 TO 10;
signal VT_i: STD_LOGIC;
-- rx input avoid glitch
signal rx_R : std_logic;
signal rx_fifo_R : std_logic_vector(2 downto 0);
--Description des états
type STATE_TYPE is ( WAIT_StartBit, WAIT_1P5B, MainLoop, ECRIRE,
WAIT_1B, GEN_PULSE, WAIT_FIN);
signal state : STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
VT_baud <= '1' when R_baud=0 else '0';
VT_i <= '1' when R_i=0 else '0';
Data <= R_sh;
process (clk)
begin if clk'event and clk='1' then
if CMD_baud=INIT1P5B then
R_baud <= (FREQ+FREQ/2)/BAUD; -- init à 1.5 * F/B
elsif CMD_baud=INIT1B then
R_baud <= FREQ/BAUD; -- init à F/B
else
R_baud <= R_baud - 1;
end if;
-- R_i
if CMD_i=NOOP then
R_i <= R_i ; -- on ne fait rien (noop)
elsif CMD_i=INIT then
R_i <= 8; -- init à 8
else
R_i <= R_i - 1; -- on compte
end if;
-- R_sh
if CMD_sh='1' then
R_sh(6 downto 0) <= R_sh(7 downto 1);
R_sh(7) <= rx_R;
end if;
-- rx input avoid glitch
rx_fifo_R(2 downto 1) <= rx_fifo_R(1 downto 0);
rx_fifo_R(0) <= rx;
if rx_fifo_R = "000" or rx_fifo_R = "111" then
rx_R <= rx_fifo_R(2);
end if;
end if; end process;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- fonction de transitition
process (reset,clk)
begin
if reset = '1' then
state <= WAIT_StartBit;
elsif clk'event and clk = '1' then case state is
when WAIT_StartBit =>
if rx_R = '0' then
state <= WAIT_1P5B;
else
state <= WAIT_StartBit;
end if;
when WAIT_1P5B =>
if VT_baud='1' then
state <= MainLoop;
else
state <= WAIT_1P5B;
end if;
when MainLoop=>
if VT_i='1' then
state <= GEN_PULSE;
else
state <= ECRIRE;
end if;
when ECRIRE=>
state <= WAIT_1B;
when WAIT_1B=>
if VT_baud='1' then
state <= MainLoop;
else
state <= WAIT_1B;
end if;
when GEN_PULSE =>
state <= WAIT_FIN;
when WAIT_FIN=>
if VT_baud='1' then
state <= WAIT_StartBit;
else
state <= WAIT_FIN;
end if;
when others =>
state <= WAIT_StartBit;
end case; end if; end process;
-- fonction de sortie
with state select nData <=
'1' when GEN_PULSE,
'0' when others;
with state select CMD_sh <=
'1' when ECRIRE,
'0' when others;
with state select CMD_baud <=
INIT1B when MainLoop,
INIT1B when ECRIRE,
INIT1P5B when WAIT_StartBit,
COUNT when others;
with state select CMD_i <=
INIT when WAIT_StartBit,
INIT when WAIT_1P5B,
COUNT when MainLoop,
NOOP when others;
debug(7) <= rx_R;
with state select debug(6 downto 0) <=
"1000000" when WAIT_StartBit,
"0100000" when WAIT_1P5B,
"0010000" when MainLoop,
"0001000" when ECRIRE,
"0000100" when WAIT_1B,
"0000010" when GEN_PULSE,
"0000001" when WAIT_FIN,
"1111111" when others;
end montage;
| gpl-3.0 |
peladex/RHD2132_FPGA | src/spi_master_slave/spi_slave.vhd | 1 | 34143 | ----------------------------------------------------------------------------------
-- Author: Jonny Doin, [email protected]
--
-- Create Date: 15:36:20 05/15/2011
-- Module Name: SPI_SLAVE - RTL
-- Project Name: SPI INTERFACE
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Description:
--
-- This block is the SPI slave interface, implemented in one single entity.
-- All internal core operations are synchronous to the external SPI clock, and follows the general SPI de-facto standard.
-- The parallel read/write interface is synchronous to a supplied system master clock, 'clk_i'.
-- Synchronization for the parallel ports is provided by input data request and write enable lines, and output data valid line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
--
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), and lookahead prefetch
-- signaling ('PREFETCH').
--
-- PARALLEL WRITE INTERFACE
-- The parallel interface has a input port 'di_i' and an output port 'do_o'.
-- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'.
-- When the core needs input data, a look ahead data request strobe , 'di_req_o' is pulsed 'PREFETCH' 'spi_sck_i'
-- cycles in advance to synchronize a user pipelined memory or fifo to present the next input data at 'di_i'
-- in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
-- The data request strobe on 'di_req_o' is 2 'clk_i' clock cycles long.
-- The write to 'di_i' must occur at most one 'spi_sck_i' cycle before actual load to the core shift register, to avoid
-- race conditions at the register transfer.
-- The user circuit places data at the 'di_i' port and strobes the 'wren_i' line for one rising edge of 'clk_i'.
-- For a pipelined sync RAM, a PREFETCH of 3 cycles allows an address generator to present the new adress to the RAM in one
-- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the interface one clock before transfer.
-- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
-- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last clock cycle,
-- if continuous transmission is intended.
-- When the interface is idle ('spi_ssel_i' is HIGH), the top bit of the latched 'di_i' port is presented at port 'spi_miso_o'.
--
-- PARALLEL WRITE PIPELINED SEQUENCE
-- =================================
-- __ __ __ __ __ __ __
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock
-- ___________
-- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'clk_i'
-- ______________ ___________________________...
-- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'clk_i' rising edge
-- ________
-- wren_i __________________________/ \______... -- 'wren_i' enables latch on rising edge of 'clk_i'
--
--
-- PARALLEL READ INTERFACE
-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete
-- word is received, the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_sck_i'.
-- The signal 'do_valid_o' is strobed 3 'clk_i' clocks after, to directly drive a synchronous memory or fifo write enable.
-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'clk_i'.
-- When the interface is idle, data at the 'do_o' port holds the last word received.
--
-- PARALLEL READ PIPELINED SEQUENCE
-- ================================
-- ______ ______ ______ ______
-- clk_spi_i ___/ bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- spi base clock
-- __ __ __ __ __ __ __ __ __
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock
-- _________________ _____________________________________... -- 1) received data is transferred to 'do_buffer_reg'
-- do_o __old_data_______X__________new_data___________________... -- after last bit received, at next shift clock.
-- ____________
-- do_valid_o ________________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'clk_i' cycles
-- -- on the 3rd 'clk_i' rising edge.
--
--
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
--
-- Author(s): Jonny Doin, [email protected], [email protected]
--
-- Copyright (C) 2011 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/05/15 v0.10.0050 [JD] created the slave logic, with 2 clock domains, from SPI_MASTER module.
-- 2011/05/15 v0.15.0055 [JD] fixed logic for starting state when CPHA='1'.
-- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries.
-- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core.
-- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets.
-- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches.
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
-- synthesis LUT overhead in Spartan-6 architecture.
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
-- 2011/06/12 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
-- 2011/06/17 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
-- 2011/07/29 v2.00.0110 [JD] FIX: CPHA bugs:
-- - redesigned core clocking to address all CPOL and CPHA configurations.
-- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite
-- clock phases from SHIFT_EDGE.
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core.
-- Simulated in iSim with the master core for continuous transmission mode.
-- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
-- 2011/08/04 v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic.
-- 2011/08/08 v2.02.0122 [JD] FIX: continuous transfer mode bug. When wren_i is not strobed prior to state 1 (last bit), the
-- sequencer goes to state 0, and then to state 'N' again. This produces a wrong bit-shift for received
-- data. The fix consists in engaging continuous transfer regardless of the user strobing write enable, and
-- sequencing from state 1 to N as long as the master clock is present. If the user does not write new
-- data, the last data word is repeated.
-- 2011/08/08 v2.02.0123 [JD] ISSUE: continuous transfer mode bug, for ignored 'di_req' cycles. Instead of repeating the last data word,
-- the slave will send (others => '0') instead.
-- 2011/08/28 v2.02.0126 [JD] ISSUE: the miso_o MUX that preloads tx_bit when slave is desselected will glitch for CPHA='1'.
-- FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity spi_slave is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 3); -- prefetch lookahead cycles
Port (
clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers)
spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line
spi_sck_i : in std_logic := 'X'; -- spi bus sck clock (clocks the shift register core)
spi_mosi_i : in std_logic := 'X'; -- spi bus mosi input
spi_miso_o : out std_logic := 'X'; -- spi bus spi_miso_o output
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i)
wren_i : in std_logic := 'X'; -- user data write enable
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge.
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i)
--- debug ports: can be removed for the application circuit ---
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_next_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_slave;
--================================================================================================================
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
-- Alternatively, you can remove these ports and related circuitry once the core is verified and
-- integrated to your circuit.
--================================================================================================================
architecture rtl of spi_slave is
-- constants to control FlipFlop synthesis
constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge
constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); -- MISO data is updated at this SCK edge
------------------------------------------------------------------------------------------
-- GLOBAL RESET:
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and
-- especially for the Spartan-6 and newer CLB architectures, where a local reset can
-- reduce the usability of the slice registers, due to the need to share the control
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
-- By using GSR for the initialization, and reducing RESET local init to the really
-- essential, the model achieves better LUT/FF packing and CLB usability.
------------------------------------------------------------------------------------------
-- internal state signals for register and combinatorial stages
signal state_next : natural range N downto 0 := 0; -- state 0 is idle state
signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
-- mosi and miso connections
signal rx_bit_next : std_logic; -- sample of MOSI input
signal tx_bit_next : std_logic;
signal tx_bit_reg : std_logic; -- drives MISO during sequential logic
signal preload_miso : std_logic; -- controls the MISO MUX
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector (N-1 downto 0);
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
-- internal input data request signal
signal di_req_next : std_logic := '0';
signal di_req_reg : std_logic := '0';
-- cross-clock do_valid_o logic
signal do_valid_next : std_logic := '0';
signal do_valid_A : std_logic := '0';
signal do_valid_B : std_logic := '0';
signal do_valid_C : std_logic := '0';
signal do_valid_D : std_logic := '0';
signal do_valid_o_reg : std_logic := '0';
-- cross-clock di_req_o logic
signal di_req_o_next : std_logic := '0';
signal di_req_o_A : std_logic := '0';
signal di_req_o_B : std_logic := '0';
signal di_req_o_C : std_logic := '0';
signal di_req_o_D : std_logic := '0';
signal di_req_o_reg : std_logic := '0';
begin
--=============================================================================================
-- GENERICS CONSTRAINTS CHECKING
--=============================================================================================
-- minimum word width is 8 bits
assert N >= 8
report "Generic parameter 'N' error: SPI shift register size needs to be 8 bits minimum"
severity FAILURE;
-- maximum prefetch lookahead check
assert PREFETCH <= N-5
report "Generic parameter 'PREFETCH' error: lookahead count out of range, needs to be N-5 maximum"
severity FAILURE;
--=============================================================================================
-- GENERATE BLOCKS
--=============================================================================================
--=============================================================================================
-- DATA INPUTS
--=============================================================================================
-- connect rx bit input
rx_bit_proc : rx_bit_next <= spi_mosi_i;
--=============================================================================================
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC
--=============================================================================================
-- do_valid_o and di_req_o strobe output logic
-- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a
-- fixed-length delayed pulse for the output flags, at the parallel clock domain
out_transfer_proc : process ( clk_i, do_transfer_reg, di_req_reg,
do_valid_A, do_valid_B, do_valid_D,
di_req_o_A, di_req_o_B, di_req_o_D) is
begin
if clk_i'event and clk_i = '1' then -- clock at parallel port clock
-- do_transfer_reg -> do_valid_o_reg
do_valid_A <= do_transfer_reg; -- the input signal must be at least 2 clocks long
do_valid_B <= do_valid_A; -- feed it to a ripple chain of FFDs
do_valid_C <= do_valid_B;
do_valid_D <= do_valid_C;
do_valid_o_reg <= do_valid_next; -- registered output pulse
--------------------------------
-- di_req_reg -> di_req_o_reg
di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long
di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs
di_req_o_C <= di_req_o_B;
di_req_o_D <= di_req_o_C;
di_req_o_reg <= di_req_o_next; -- registered output pulse
end if;
-- generate a 2-clocks pulse at the 3rd clock cycle
do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
end process out_transfer_proc;
-- parallel load input registers: data register and write enable
in_transfer_proc: process (clk_i, wren_i, wr_ack_reg) is
begin
-- registered data input, input register with clock enable
if clk_i'event and clk_i = '1' then
if wren_i = '1' then
di_reg <= di_i; -- parallel data input buffer register
end if;
end if;
-- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
if clk_i'event and clk_i = '1' then
if wren_i = '1' then -- wren_i is the sync preset for wren
wren <= '1';
elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren
wren <= '0';
end if;
end if;
end process in_transfer_proc;
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers change on spi SHIFT_EDGE
core_reg_proc : process (spi_sck_i, spi_ssel_i) is
begin
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1)
-- state fsm register (fdr)
if spi_ssel_i = '1' then -- async clr
state_reg <= 0; -- state falls back to idle when slave not selected
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update state register
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock
end if;
-- FFD registers clocked on SHIFT edge
-- rtl core registers (fd)
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers
sh_reg <= sh_next; -- core shift register
do_buffer_reg <= do_buffer_next; -- registered data output
do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag
di_req_reg <= di_req_next; -- input data request
wr_ack_reg <= wr_ack_next; -- wren ack for data load synchronization
end if;
-- FFD registers clocked on CHANGE edge and cleared on idle (spi_ssel_i = 1)
-- miso MUX preload control register (fdp)
if spi_ssel_i = '1' then -- async preset
preload_miso <= '1'; -- miso MUX sees top bit of parallel input when slave not selected
elsif spi_sck_i'event and spi_sck_i = CHANGE_EDGE then -- on CHANGE edge, change to tx_reg output
preload_miso <= spi_ssel_i; -- miso MUX sees tx_bit_reg when it is driven by SCK
end if;
-- FFD registers clocked on CHANGE edge
-- tx_bit register (fd)
if spi_sck_i'event and spi_sck_i = CHANGE_EDGE then
tx_bit_reg <= tx_bit_next; -- update MISO driver from the MSb
end if;
end process core_reg_proc;
--=============================================================================================
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg,
do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is
begin
-- all output signals are assigned to (avoid latches)
sh_next <= sh_reg; -- shift register
tx_bit_next <= tx_bit_reg; -- MISO driver
do_buffer_next <= do_buffer_reg; -- output data buffer
do_transfer_next <= do_transfer_reg; -- output data flag
wr_ack_next <= wr_ack_reg; -- write enable acknowledge
di_req_next <= di_req_reg; -- data input request
state_next <= state_reg; -- fsm control state
case state_reg is
when (N) => -- deassert 'di_rdy' and stretch do_valid
wr_ack_next <= '0'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) => -- remove 'do_transfer' and shift bits
do_transfer_next <= '0'; -- reset 'do_valid' transfer signal
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
wr_ack_next <= '0'; -- remove data load ack for all but the load stages
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 3 => -- raise prefetch 'di_req_o' signal
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
wr_ack_next <= '0'; -- remove data load ack for all but the load stages
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when 2 => -- transfer received data to do_buffer_reg on next cycle
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
wr_ack_next <= '0'; -- remove data load ack for all but the load stages
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle
do_buffer_next <= sh_next; -- get next data directly into rx buffer
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 => -- transfer rx data to do_buffer and restart if new data is written
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
state_next <= N; -- next state is top bit of new data
if wren = '1' then -- load tx register if valid data present at di_reg
wr_ack_next <= '1'; -- acknowledge data in transfer
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
else
wr_ack_next <= '0'; -- no data reload for continuous transfer mode
sh_next(N-1 downto 1) <= (others => '0'); -- clear transmit shift register
tx_bit_next <= '0'; -- send ZERO
end if;
when 0 => -- idle state: start and end of transmission
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- clear signal transfer to do_buffer
state_next <= N; -- next state is top bit of new data
when others =>
state_next <= 0; -- safe state
end case;
end process core_combi_proc;
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
do_o_proc : do_o <= do_buffer_reg; -- do_o always available
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output
-----------------------------------------------------------------------------------------------
-- MISO driver process: preload top bit of parallel data to MOSI at reset
-----------------------------------------------------------------------------------------------
-- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit
-- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic.
spi_miso_o_proc: process (preload_miso, tx_bit_reg, di_reg) is
begin
if preload_miso = '1' then
spi_miso_o <= di_reg(N-1); -- copy top bit of parallel data at reset
else
spi_miso_o <= tx_bit_reg; -- copy top bit of shifter at sequential operation
end if;
end process spi_miso_o_proc;
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4)); -- export internal state to debug
rx_bit_next_proc: rx_bit_next_o <= rx_bit_next;
wren_o_proc: wren_o <= wren;
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug
end architecture rtl;
| gpl-3.0 |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/plus12.vhd | 1 | 7342 | -- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: plus12.vhd 325 2015-06-03 12:47:32Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/plus12.vhd $
-- $Author : Ivan Auge (Email: [email protected])
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
-------------------------------------------------------------------------------
-- Ce module additionne 2 nombres de 12 bits signés.
-- Ses E/S sont les bus busin et busout.
--
-- Input:
-- busin_ctl (43 DOWNTO 40) : not used
-- busin_asrc(39 DOWNTO 32) : adresse emetteur (E_ADR)
-- busin_ades(31 DOWNTO 24) : adresse destination (MYADR)
-- busin_data(23 DOWNTO 12) : operande B en complement a 2
-- busin_data(11 DOWNTO 0) : operande A en complement a 2
--
-- Output:
-- busout_ctl (43 DOWNTO 40) : "0000"
-- busout_asrc(39 DOWNTO 32) : MYADR
-- busout_ades(31 DOWNTO 24) : E_ADR
-- busout_data(23) : V (overflow)
-- busout_data(22) : C (retenue sortante)
-- busout_data(21) : N (résultat négatif)
-- busout_data(20) : Z (résultat nul)
-- busout_data(19 DOWNTO 12) : "00000000"
-- busout_data(11 DOWNTO 0) : résultat en complément a 2 (A+B)
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
ENTITY plus12 IS
GENERIC(
MYADR : STD_LOGIC_VECTOR(7 downto 0) := x"C0" ); -- 192
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 DOWNTO 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface busout
busout : OUT STD_LOGIC_VECTOR(43 DOWNTO 0);
busout_valid : OUT STD_LOGIC;
busout_eated : IN STD_LOGIC;
-- debug
debug : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END plus12;
ARCHITECTURE Montage OF plus12 IS
TYPE T_CMD_LoadNoop IS (LOAD, NOOP);
-- partie operative
-- le registre de transfert de busin vers busout
SIGNAL CMD_tft : T_CMD_LoadNoop;
SIGNAL R_tft : STD_LOGIC_VECTOR(43 DOWNTO 0);
-- le registre resultat de A+B, ov
-- on etend R sur 13 bits pour avoir la retenue
SIGNAL CMD_res : T_CMD_LoadNoop;
SIGNAL R_res : STD_LOGIC_VECTOR(12 DOWNTO 0);
-- les operandes A et B (1 bit de plus pour la retenue)
SIGNAL A,B : STD_LOGIC_VECTOR (12 DOWNTO 0); -- V1
-- bits de retenue et de somme de A+B -- V1
SIGNAL r,s : STD_LOGIC_VECTOR (12 DOWNTO 0); -- V1
-- SIGNAL A,B : SIGNED (12 DOWNTO 0); -- V2
-- l' adresse destination
SIGNAL busin_ades : STD_LOGIC_VECTOR ( 7 DOWNTO 0);
-- message résulat
SIGNAL mess_resultat : STD_LOGIC_VECTOR (43 DOWNTO 0);
-- partie controle
TYPE STATE_TYPE IS (ST_READ, ST_WRITE_TFT, ST_COMPUTE, ST_WRITE_SUM);
SIGNAL state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
busin_ades <= busin(31 DOWNTO 24) ;
a <= "0" & R_tft(23 DOWNTO 12) ; -- V1
b <= "0" & R_tft(11 DOWNTO 0) ; -- V1
-- a <= SIGNED (R_tft(23 DOWNTO 12)) ; -- V2
-- b <= SIGNED (R_tft(11 DOWNTO 0)) ; -- V2
mess_resultat(43 DOWNTO 40) <= "0000";
mess_resultat(39 DOWNTO 32) <= MYADR;
mess_resultat(31 DOWNTO 24) <= R_tft(39 DOWNTO 32);
mess_resultat(23) <= -- overflow
'1' WHEN a(11)='1' AND b(11)='1' AND R_res(11)='0' ELSE -- N+N=P
'1' WHEN a(11)='0' AND b(11)='0' AND R_res(11)='1' ELSE -- P+P=N
'0' ;
mess_resultat(22) <= R_res(12); -- cout
mess_resultat(21) <= R_res(11); -- signe
mess_resultat(20) <= -- null
'1' WHEN R_res(11 downto 0) = x"000" ELSE '0';
mess_resultat(19 DOWNTO 12) <= "00000000" ;
mess_resultat(11 DOWNTO 0) <= R_res(11 DOWNTO 0);
-- s,r <-- a + b; -- V1
s <= a XOR b XOR r; -- V1
r(0) <= '0'; -- V1
r(12 DOWNTO 1) <= -- V1
( a(11 DOWNTO 0) AND b(11 DOWNTO 0) ) OR -- V1
( a(11 DOWNTO 0) AND r(11 DOWNTO 0) ) OR -- V1
( r(11 DOWNTO 0) AND b(11 DOWNTO 0) ); -- V1
PROCESS (clk)
BEGIN IF clk'EVENT AND clk = '1' THEN
-- R_tft
if ( CMD_tft = LOAD ) then
R_tft <= busin;
end if;
-- R_res
if ( CMD_res = LOAD ) then
R_res(12 DOWNTO 0) <= s ; -- V1
-- R_res(12 DOWNTO 0) <= STD_LOGIC_VECTOR(a + b) ; -- V2
end if;
END IF; END PROCESS;
-------------------------------------------------------------------------------
-- Partie Controle
-------------------------------------------------------------------------------
-- Inputs: busin_valid busout_eated
-- Outputs: busin_eated busout_valid, CMD_res, CMD_tft, busout
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
IF reset = '1' THEN
state <= ST_READ;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN ST_READ =>
IF busin_valid = '1' and busin_ades = MYADR THEN
state <= ST_COMPUTE;
ELSIF busin_valid = '1' and busin_ades /= MYADR THEN
state <= ST_WRITE_TFT;
END IF;
WHEN ST_COMPUTE =>
state <= ST_WRITE_SUM;
WHEN ST_WRITE_SUM =>
IF busout_eated = '1' THEN
state <= ST_READ;
END IF;
WHEN ST_WRITE_TFT =>
IF busout_eated = '1' THEN
state <= ST_READ;
END IF;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
WITH state SELECT busin_eated <=
'1' WHEN ST_READ,
'0' WHEN OTHERS;
WITH state SELECT busout_valid <=
'1' WHEN ST_WRITE_TFT,
'1' WHEN ST_WRITE_SUM,
'0' WHEN OTHERS;
WITH state SELECT CMD_res <=
LOAD WHEN ST_Compute,
NOOP WHEN OTHERS;
WITH state SELECT CMD_tft <=
LOAD WHEN ST_READ,
NOOP WHEN OTHERS;
WITH state SELECT busout <=
mess_resultat WHEN ST_WRITE_SUM,
R_tft WHEN OTHERS;
END Montage;
| gpl-3.0 |
DaveyPocket/btrace448 | btrace/vector_reg.vhd | 1 | 555 | -- Btrace 448
-- Vector Register
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use work.btrace_pack.all;
entity vector_reg is
port(clk, rst, en: in std_logic;
Din: in vector;
Dout: out vector);
end vector_reg;
architecture arch of vector_reg is
constant zero_vector: vector := ((others => '0'), (others => '0'), (others => '0'));
begin
process(clk, rst)
begin
if rst = '1' then
Dout <= zero_vector;
elsif rising_edge(clk) then
if en = '1' then
Dout <= Din;
end if;
end if;
end process;
end arch;
| gpl-3.0 |
freecores/usb_fpga_2_16 | examples/usb-fpga-1.15/1.15a/intraffic/fpga/intraffic.vhd | 42 | 1939 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity intraffic is
port(
RESET : in std_logic;
CONT : in std_logic;
IFCLK : in std_logic;
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic
);
end intraffic;
architecture RTL of intraffic is
----------------------------
-- test pattern generator --
----------------------------
-- 30 bit counter
signal GEN_CNT : std_logic_vector(29 downto 0);
signal INT_CNT : std_logic_vector(6 downto 0);
signal FIFO_WORD : std_logic;
begin
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1'; -- no data alignment
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
INT_CNT <= ( others => '0' );
FIFO_WORD <= '0';
SLWR <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
if CONT = '1' or FLAGB = '1'
then
if FIFO_WORD = '0'
then
FD(14 downto 0) <= GEN_CNT(14 downto 0);
else
FD(14 downto 0) <= GEN_CNT(29 downto 15);
end if;
FD(15) <= FIFO_WORD;
if FIFO_WORD = '1'
then
GEN_CNT <= GEN_CNT + '1';
if INT_CNT = conv_std_logic_vector(99,7)
then
INT_CNT <= ( others => '0' );
else
INT_CNT <= INT_CNT + '1';
end if;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
if ( INT_CNT >= conv_std_logic_vector(90,7) ) and ( CONT = '0' )
then
SLWR <= '1';
else
SLWR <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
| gpl-3.0 |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia_save/plus12.vhd | 1 | 7829 | -- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: plus12.vhd 325 2015-06-03 12:47:32Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/plus12.vhd $
-- $Author : Ivan Auge (Email: [email protected])
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
-------------------------------------------------------------------------------
-- Ce module additionne 2 nombres de 12 bits signés.
-- Ses E/S sont les bus busin et busout.
--
-- Input:
-- busin_ctl (43 DOWNTO 40) : not used
-- busin_asrc(39 DOWNTO 32) : adresse emetteur (E_ADR)
-- busin_ades(31 DOWNTO 24) : adresse destination (MYADR)
-- busin_data(23 DOWNTO 12) : operande B en complement a 2
-- busin_data(11 DOWNTO 0) : operande A en complement a 2
--
-- Output:
-- busout_ctl (43 DOWNTO 40) : "0000"
-- busout_asrc(39 DOWNTO 32) : MYADR
-- busout_ades(31 DOWNTO 24) : E_ADR
-- busout_data(23) : V (overflow)
-- busout_data(22) : C (retenue sortante)
-- busout_data(21) : N (résultat négatif)
-- busout_data(20) : Z (résultat nul)
-- busout_data(19 DOWNTO 12) : "00000000"
-- busout_data(11 DOWNTO 0) : résultat en complément a 2 (A+B)
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
ENTITY plus12 IS
GENERIC(
MYADR : STD_LOGIC_VECTOR(7 downto 0) := x"C0" ); -- 192
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 DOWNTO 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface busout
busout : OUT STD_LOGIC_VECTOR(43 DOWNTO 0);
busout_valid : OUT STD_LOGIC;
busout_eated : IN STD_LOGIC;
-- debug
debug : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END plus12;
ARCHITECTURE Montage OF plus12 IS
TYPE T_CMD_LoadNoop IS (LOAD, NOOP);
-- partie operative
-- le registre de transfert de busin vers busout
SIGNAL CMD_tft : T_CMD_LoadNoop;
SIGNAL R_tft : STD_LOGIC_VECTOR(43 DOWNTO 0);
-- le registre resultat de A+B, ov
-- on etend R sur 13 bits pour avoir la retenue
SIGNAL CMD_res : T_CMD_LoadNoop;
SIGNAL R_res : STD_LOGIC_VECTOR(12 DOWNTO 0);
-- les operandes A et B (1 bit de plus pour la retenue)
SIGNAL A,B : STD_LOGIC_VECTOR (12 DOWNTO 0); -- V1
-- bits de retenue et de somme de A+B -- V1
SIGNAL r,s : STD_LOGIC_VECTOR (12 DOWNTO 0); -- V1
-- SIGNAL A,B : SIGNED (12 DOWNTO 0); -- V2
-- l' adresse destination
SIGNAL busin_ades : STD_LOGIC_VECTOR ( 7 DOWNTO 0);
-- message résulat
SIGNAL mess_resultat : STD_LOGIC_VECTOR (43 DOWNTO 0);
-- partie controle
TYPE STATE_TYPE IS (ST_READ, ST_WRITE_TFT, ST_COMPUTE, ST_WRITE_SUM);
SIGNAL state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
busin_ades <= busin(31 DOWNTO 24) ;
a <= "0" & R_tft(23 DOWNTO 12) ; -- V1
b <= "0" & R_tft(11 DOWNTO 0) ; -- V1
-- a <= SIGNED (R_tft(23 DOWNTO 12)) ; -- V2
-- b <= SIGNED (R_tft(11 DOWNTO 0)) ; -- V2
mess_resultat(43 DOWNTO 40) <= "0000";
mess_resultat(39 DOWNTO 32) <= MYADR;
mess_resultat(31 DOWNTO 24) <= R_tft(39 DOWNTO 32);
mess_resultat(23) <= -- overflow
'1' WHEN a(11)='1' AND b(11)='1' AND R_res(11)='0' ELSE -- N+N=P
'1' WHEN a(11)='0' AND b(11)='0' AND R_res(11)='1' ELSE -- P+P=N
'0' ;
mess_resultat(22) <= R_res(12); -- cout
mess_resultat(21) <= R_res(11); -- signe
mess_resultat(20) <= -- null
'1' WHEN R_res(11 downto 0) = x"000" ELSE '0';
mess_resultat(19 DOWNTO 12) <= "00000000" ;
mess_resultat(11 DOWNTO 0) <= R_res(11 DOWNTO 0);
-- s,r <-- a + b; -- V1
s <= a XOR b XOR r; -- V1
r(0) <= '0'; -- V1
r(12 DOWNTO 1) <= -- V1
( a(11 DOWNTO 0) AND b(11 DOWNTO 0) ) OR -- V1
( a(11 DOWNTO 0) AND r(11 DOWNTO 0) ) OR -- V1
( r(11 DOWNTO 0) AND b(11 DOWNTO 0) ); -- V1
PROCESS (clk)
BEGIN IF clk'EVENT AND clk = '1' THEN
-- R_tft
if ( CMD_tft = LOAD ) then
R_tft <= busin;
end if;
-- R_res
if ( CMD_res = LOAD ) then
R_res(12 DOWNTO 0) <= s ; -- V1
-- R_res(12 DOWNTO 0) <= STD_LOGIC_VECTOR(a + b) ; -- V2
end if;
END IF; END PROCESS;
-------------------------------------------------------------------------------
-- Partie Controle
-------------------------------------------------------------------------------
-- Inputs: busin_valid busout_eated
-- Outputs: busin_eated busout_valid, CMD_res, CMD_tft, busout
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
IF reset = '1' THEN
state <= ST_READ;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN ST_READ =>
IF busin_valid = '1' and busin_ades = MYADR THEN
state <= ST_COMPUTE;
ELSIF busin_valid = '1' and busin_ades /= MYADR THEN
state <= ST_WRITE_TFT;
END IF;
WHEN ST_COMPUTE =>
state <= ST_WRITE_SUM;
WHEN ST_WRITE_SUM =>
IF busout_eated = '1' THEN
state <= ST_READ;
END IF;
WHEN ST_WRITE_TFT =>
IF busout_eated = '1' THEN
state <= ST_READ;
END IF;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
WITH state SELECT busin_eated <=
'1' WHEN ST_READ,
'0' WHEN OTHERS;
WITH state SELECT busout_valid <=
'1' WHEN ST_WRITE_TFT,
'1' WHEN ST_WRITE_SUM,
'0' WHEN OTHERS;
WITH state SELECT CMD_res <=
LOAD WHEN ST_Compute,
NOOP WHEN OTHERS;
WITH state SELECT CMD_tft <=
LOAD WHEN ST_READ,
NOOP WHEN OTHERS;
WITH state SELECT busout <=
mess_resultat WHEN ST_WRITE_SUM,
R_tft WHEN OTHERS;
END Montage;
| gpl-3.0 |
DaveyPocket/btrace448 | btrace/controller.vhd | 1 | 2655 | -- Btrace 448
-- Controller
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.btrace_pack.all;
entity controller is
port(clk, rst: in std_logic;
-- Control outputs
init_x, init_y, inc_x, inc_y: out std_logic;
set_vector, set_org: out std_logic;
next_obj, start_search: out std_logic;
clr_z_reg, clr_hit: out std_logic;
store: out std_logic;
paint: out std_logic;
done: out std_logic;
-- Status inputs
last_x, last_y, last_obj, obj_valid, start: in std_logic);
end controller;
architecture arch of controller is
-- Controller states
type states_t is (s_idle, s_start, s_set, s_wait, s_next, s_done);
signal controller_state: states_t := s_idle;
begin
process(clk, rst)
begin
if rst = '1' then
controller_state <= s_idle;
elsif rising_edge(clk) then
case controller_state is
when s_idle =>
if start = '1' then
controller_state <= s_start;
end if;
when s_start =>
controller_state <= s_set;
when s_set =>
controller_state <= s_wait;
when s_wait =>
controller_state <= s_next;
when s_next =>
if last_obj = '0' then
controller_state <= s_wait;
else
if last_x = '0' then
controller_state <= s_start;
else
if last_y = '0' then
controller_state <= s_start;
else
controller_state <= s_done;
end if;
end if;
end if;
when others =>
if start = '1' then
controller_state <= s_done;
else
controller_state <= s_idle;
end if;
end case;
end if;
end process;
clr_hit <= '1' when controller_state = s_start else '0';
clr_z_reg <= '1' when controller_state = s_start else '0';
init_x <= '1' when (controller_state = s_idle) or ((controller_state = s_next) and ((last_obj and last_x) = '1') and (last_y = '0')) else '0';
inc_y <= '1' when ((controller_state = s_next) and ((last_obj and last_x) = '1') and (last_y = '0')) else '0';
inc_x <= '1' when ((controller_state = s_next) and (last_obj = '1') and (last_x = '0')) else '0';
init_y <= '1' when (controller_state = s_idle) else '0';
set_vector <= '1' when controller_state = s_set else '0';
set_org <= '1' when controller_state = s_set else '0';
store <= '1' when (controller_state = s_wait) and (obj_valid = '1') else '0';
paint <= '1' when (controller_state = s_next) and (last_obj = '1') else '0';
next_obj <= '1' when (controller_state = s_next) else '0';
start_search <= '1' when (controller_state = s_start) else '0';
done <= '1' when (controller_state = s_done) else '0';
end arch;
| gpl-3.0 |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/initiateur.vhd | 1 | 7667 | -- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: initiateur.vhd 327 2015-06-03 19:18:19Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/initiateur.vhd $
-- $Author : Ivan Auge (Email: [email protected])
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
-------------------------------------------------------------------------------
-- Ce module transfert tous les messages venant de busin sur busout.
-- De plus, ce module récupère 4 octets B3,B2,B1,B0 1 par 1 sur RS232in et
-- les regroupe pour réaliser un message (0000,addrsrc,addrdest,data)
-- (voir bus.txt) qu'il transfert sur busout.
-- B0 est le premier octet reçu, B3 est le dernier octet reçu.
--
-- addrsrc = 11111111 (255)
-- addrdest = B3
-- data = B2<<16 | B1<<8 | B0
--
-- Du coté busin, il suit le protocole "poignée de main" (signaux: busin,
-- busin_valid, busin_eated).
-- Du coté busout, il suit le protocole "poignée de main" (signaux: busout,
-- busout_valid, busout_eated).
-- Du coté RS232in, il suit le protocole du module RS232in (signaux: Data, Ndata).
--
-- Attention:
-- - il n'y a pas de contrôle de flux du cote RS232in, donc si des données
-- arrive sur Data et que le bus est bloqué, elles seront perdues.
-- - ce module assume que Data reste stable au moins 3 cycles après la pulse Ndata
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY initiateur IS
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 DOWNTO 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface busout
busout : OUT STD_LOGIC_VECTOR(43 DOWNTO 0);
busout_valid : OUT STD_LOGIC;
busout_eated : IN STD_LOGIC;
-- interface vers rs232out
Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Ndata : IN STD_LOGIC);
END initiateur;
ARCHITECTURE Montage OF initiateur IS
-- compteur donnant le nombre d'octets a mettre dans R_32
TYPE T_CMD_i IS (NOOP, COUNT, INIT);
SIGNAL CMD_i : T_CMD_i ;
SIGNAL R_i : INTEGER RANGE 0 TO 4;
SIGNAL VT_endLoop: STD_LOGIC;
-- accumule les octets venant de Data.
TYPE T_CMD_32 IS (NOOP, SHIFT);
SIGNAL CMD_32 : T_CMD_32 ;
SIGNAL R_32 : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- Registre de transfert entre busin et busout
TYPE T_CMD_tft IS (INIT, NOOP);
SIGNAL CMD_tft : T_CMD_tft ;
SIGNAL R_tft : STD_LOGIC_VECTOR (43 DOWNTO 0);
-- Sauve une pulse de Ndata qd on est dans les etats de la FSM
-- qui ne teste pas Ndata
TYPE T_CMD_pulse IS (CLEAR, LOAD);
SIGNAL CMD_pulse : T_CMD_pulse ;
SIGNAL R_pulse : STD_LOGIC;
SIGNAL R_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- les sources d'ecriture sur busout
SIGNAL busout_rs232 : STD_LOGIC_VECTOR(43 DOWNTO 0);
SIGNAL busout_tft : STD_LOGIC_VECTOR(43 DOWNTO 0);
--Description des �tats
TYPE STATE_TYPE IS (
ST_INIT,ST_WAIT_BUSIN_OR_NDATA,
ST_BUSIN_AND_NDATA_LOADED,
ST_NDATA_LOADED, ST_BUSIN_LOADED,
ST_EndLoop, ST_NDATA_WRITE);
SIGNAL state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Op�rative
-------------------------------------------------------------------------------
PROCESS (clk)
BEGIN IF clk'EVENT AND clk = '1' THEN
-- R_i
if ( CMD_i = INIT ) then
R_i <= 4 ;
elsif ( CMD_i = COUNT ) then
R_i <= R_i - 1;
else
R_i <= R_i;
end if;
-- R_32
if ( CMD_32 = SHIFT ) then
R_32(31 DOWNTO 24) <= R_data;
R_32(23 DOWNTO 16) <= R_32(31 DOWNTO 24);
R_32(15 DOWNTO 8) <= R_32(23 DOWNTO 16);
R_32( 7 DOWNTO 0) <= R_32(15 DOWNTO 8);
else
R_32 <= R_32 ;
end if;
-- R_tft
if ( CMD_tft = INIT ) then
R_tft <= busin ;
else
R_tft <= R_tft ;
end if;
-- R_pulse
if ( CMD_pulse = LOAD ) then
R_pulse <= R_pulse OR Ndata ;
else -- CLEAR
R_pulse <= '0' ;
end if;
-- R_data
if (Ndata = '1') then
R_data <= data;
else
R_data <= R_data;
end if;
END IF; END PROCESS;
VT_endLoop <= '1' when R_i=0 else '0' ;
busout_rs232(43 DOWNTO 40) <= "0000";
busout_rs232(39 DOWNTO 32) <= "11111111";
busout_rs232(31 DOWNTO 0) <= R_32;
busout_tft <= R_tft;
-------------------------------------------------------------------------------
-- Partie Contr�le
-------------------------------------------------------------------------------
-- Inputs: busout_eated Ndata R_pulse VT_endLoop busin_valid
-- Outputs: busout_valid CMD_i CMD_32 busin_eated CMD_tft CMD_pulse busout
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
if reset = '1' then
state <= ST_INIT;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN ST_INIT =>
state <= ST_WAIT_BUSIN_OR_NDATA;
WHEN ST_WAIT_BUSIN_OR_NDATA =>
IF busin_valid = '1' AND R_pulse = '1' THEN
state <= ST_BUSIN_AND_NDATA_LOADED;
ELSIF R_pulse = '1' THEN
state <= ST_NDATA_LOADED;
ELSIF busin_valid = '1' THEN
state <= ST_BUSIN_LOADED;
END IF;
WHEN ST_BUSIN_LOADED =>
if busout_eated = '1' then
state <= ST_WAIT_BUSIN_OR_NDATA;
END IF;
WHEN ST_BUSIN_AND_NDATA_LOADED =>
if busout_eated = '1' then
state <= ST_NDATA_LOADED;
END IF;
WHEN ST_NDATA_LOADED =>
state <= ST_EndLoop;
WHEN ST_EndLoop =>
IF VT_EndLoop = '1' THEN
state <= ST_NDATA_WRITE;
else
state <= ST_WAIT_BUSIN_OR_NDATA;
END IF;
WHEN ST_NDATA_WRITE =>
if busout_eated = '1' then
state <= ST_WAIT_BUSIN_OR_NDATA;
END IF;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
WITH state SELECT busout_valid <=
'1' WHEN ST_BUSIN_LOADED,
'1' WHEN ST_NDATA_WRITE,
'0' WHEN OTHERS;
WITH state SELECT CMD_i <=
INIT WHEN ST_INIT,
INIT WHEN ST_NDATA_WRITE,
COUNT WHEN ST_NDATA_LOADED,
NOOP WHEN OTHERS;
WITH state SELECT CMD_32 <=
SHIFT WHEN ST_NDATA_LOADED,
NOOP WHEN OTHERS;
WITH state SELECT busin_eated <=
'1' WHEN ST_WAIT_BUSIN_OR_NDATA,
'0' WHEN OTHERS;
WITH state SELECT CMD_tft <=
INIT WHEN ST_WAIT_BUSIN_OR_NDATA,
NOOP WHEN OTHERS;
WITH state SELECT CMD_pulse <=
CLEAR WHEN ST_NDATA_LOADED,
LOAD WHEN OTHERS;
WITH state SELECT busout <=
busout_rs232 WHEN ST_NDATA_WRITE,
busout_tft WHEN OTHERS;
END Montage;
| gpl-3.0 |
freecores/usb_fpga_2_16 | examples/usb-fpga-1.15/1.15d/ucecho/fpga/ucecho.vhd | 42 | 580 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
| gpl-3.0 |
rpereira-dev/ENSIIE | UE/S3/microarchi/terminateur/terminateur.vhd | 3 | 6218 | -- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: terminateur.vhd 322 2015-05-29 06:43:59Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/terminateur.vhd $
-- $Author : Ivan Auge (Email: [email protected])
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
-------------------------------------------------------------------------------
-- ATTENTION:
-- Ceci un template, les trous marqués "..." doivent être comblés pour
-- pouvoir être compilé, puis fonctionné.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Ce module transfert tous les messages (????,addrsrc,addrdest,data) venant de
-- busin.
-- Si ????=???1, il transmet le messages sur busdump.
-- Si ????=???0 et addrdest!=MYADDR, il transmet sur busout le message
-- (???1,addrsrc,addrdest,data).
-- Si addrdest==MYADDR, il transmet le message sur busdump.
--
-- Du coté busin, il suit le protocole "poignée de main" (signaux: busin,
-- busin_valid, busin_eated).
-- Du coté busout, il suit le protocole "poignée de main" (signaux: busout,
-- busout_valid, busout_eated).
-- Du coté busdump, il suit le protocole "poignée de main" (signaux: busdump,
-- busdump_valid, busdump_eated).
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity terminateur is
generic(
MYADDR : STD_LOGIC_VECTOR(7 downto 0) := "11111111" -- 255
);
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 downto 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface busout
busout : out STD_LOGIC_VECTOR(43 downto 0);
busout_valid : out STD_LOGIC;
busout_eated : in STD_LOGIC;
-- interface busdump
busdump : out STD_LOGIC_VECTOR(43 downto 0);
busdump_valid: out STD_LOGIC;
busdump_eated: in STD_LOGIC);
end terminateur;
architecture montage of terminateur is
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
-- Registre de transfert entre busin et busout
type T_CMD_tft is (INIT, NOOP);
signal CMD_tft : T_CMD_tft ;
signal R_tft : STD_LOGIC_VECTOR (43 downto 0);
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- adresse destination & bit de boucle du message lu
alias busin_addrdest : STD_LOGIC_VECTOR(7 downto 0) is busin(31 downto 24);
alias busin_loop : STD_LOGIC is busin(40);
type STATE_TYPE is (
ST_READ_BUSIN, ST_WRITE_OUT, ST_WRITE_DUMP
);
signal state : STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
process (clk)
begin if clk'event and clk = '1' then
IF CMD_tft = INIT THEN
R_tft <= busin ;
END IF;
end if; end process;
busout(43 downto 41) <= R_tft(43 downto 41);
busout(40) <= '1';
busout(39 downto 0) <= R_tft(39 downto 0);
busdump <= R_tft;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: busin_valid, busout_eated, busdump_eated, busin_addrdest, busin_loop
-- Outputs: busin_eated, busout_valid, busdump_valid, CMD_tft
-------------------------------------------------------------------------------
-- fonction de transitition
process (reset,clk)
begin
if reset = '1' then
state <= ST_READ_BUSIN;
elsif clk'event and clk = '1' then
case state is
when ST_READ_BUSIN =>
IF busin_valid='1' THEN
IF busin_loop = '1' OR busin_addrdest = MYADDR THEN
state <= ST_WRITE_DUMP ;
ELSE
state <= ST_WRITE_OUT ;
END IF ;
END IF ;
when ST_WRITE_OUT =>
IF busout_eated = '1' THEN
state <= ST_READ_BUSIN;
END IF ;
when ST_WRITE_DUMP =>
IF busdump_eated = '1' THEN
state <= ST_READ_BUSIN;
END IF ;
end case;
end if;
end process;
-- fonction de sortie
with state select busin_eated <=
'1' when ST_READ_BUSIN,
'0' when others;
with state select busout_valid <=
'1' when ST_WRITE_OUT,
'0' when others;
with state select busdump_valid <=
'1' when ST_WRITE_DUMP,
'0' when others;
with state select CMD_tft <=
INIT when ST_READ_BUSIN,
NOOP when others;
end montage;
| gpl-3.0 |
peladex/RHD2132_FPGA | quartus/test_maquina_control/test_maquina_control.vhd | 1 | 931 | -----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 13/11/2016 -- dd/mm/yyyy
-- Module Name: test_maquina_control
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- ...
--
-----------------------------------------------------------------------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY test_maquina_control IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
-- registros param chips --
-- registros control --
);
END test_maquina_control;
ARCHITECTURE synth of test_maquina_control IS
BEGIN
END synth;
| gpl-3.0 |
peladex/RHD2132_FPGA | quartus/test_spi_comm/test_spi_slaves.vhd | 1 | 5242 | -----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 09/11/2016 -- dd/mm/yyyy
-- Module Name: test_spi_slaves
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Este bloque instancia dos bloques spi escalvos tal que la salida de datos de uno esta conectada a la entrada
-- de datos del otro. Lo mismo sucede con la salida que indica un dato valido y la entrada write enable. Por lo tanto,
-- si un bloque recibe un dato, en el proximo ciclo spi ese dato sera enviado por el otro bloque spi.
--
-----------------------------------------------------------------------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY test_spi_slaves IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
---- serial interface 1 ----
slave1_ssel_i : in std_logic := 'X'; -- spi bus slave select line
slave1_sck_i : in std_logic := 'X'; -- spi bus sck
slave1_mosi_i : in std_logic := 'X'; -- spi bus mosi output
slave1_miso_o : out std_logic := 'X'; -- spi bus spi_miso_i input
---- serial interface 2 ----
slave2_ssel_i : in std_logic := 'X'; -- spi bus slave select line
slave2_sck_i : in std_logic := 'X'; -- spi bus sck
slave2_mosi_i : in std_logic := 'X'; -- spi bus mosi output
slave2_miso_o : out std_logic := 'X' -- spi bus spi_miso_i input
);
END test_spi_slaves;
ARCHITECTURE synth OF test_spi_slaves IS
---- COMPONENTS
COMPONENT spi_slave IS
Generic (
N : positive := 16; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2); -- prefetch lookahead cycles
Port (
clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers)
spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line
spi_sck_i : in std_logic := 'X'; -- spi bus sck clock (clocks the shift register core)
spi_mosi_i : in std_logic := 'X'; -- spi bus mosi input
spi_miso_o : out std_logic := 'X'; -- spi bus spi_miso_o output
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i)
wren_i : in std_logic := 'X'; -- user data write enable
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge.
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i)
--- debug ports: can be removed for the application circuit ---
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_next_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
END COMPONENT;
---- SIGNALS
SIGNAL sg_slave1_di, sg_slave2_di : std_logic_vector(15 downto 0);
SIGNAL sg_slave1_wren, sg_slave2_wren : std_logic;
BEGIN
---- INSTANCES
SLAVE_1: spi_slave PORT MAP (
clk_i => m_clk,
spi_ssel_i => slave1_ssel_i,
spi_sck_i => slave1_sck_i,
spi_mosi_i => slave1_mosi_i,
spi_miso_o => slave1_miso_o,
di_i => sg_slave1_di,
wren_i => sg_slave1_wren,
do_valid_o => sg_slave2_wren,
do_o => sg_slave2_di
);
SLAVE_2: spi_slave PORT MAP (
clk_i => m_clk,
spi_ssel_i => slave2_ssel_i,
spi_sck_i => slave2_sck_i,
spi_mosi_i => slave2_mosi_i,
spi_miso_o => slave2_miso_o,
di_i => sg_slave2_di,
wren_i => sg_slave2_wren,
do_valid_o => sg_slave1_wren,
do_o => sg_slave1_di
);
END synth; | gpl-3.0 |
DaveyPocket/btrace448 | core/vga/frame_buf.vhd | 1 | 933 | -- Btrace 448
-- Frame Buffer
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity frame_buf is
generic(inputWidth: integer := 9;
inputHeight: integer := 8);
port(clk: in std_logic;
en: in std_logic;
Din: in std_logic_vector(11 downto 0);
Dout: out std_logic_vector(11 downto 0);
iaddr_x: in std_logic_vector(inputWidth-1 downto 0);
iaddr_y: in std_logic_vector(inputHeight-1 downto 0);
vga_addr_x: in std_logic_vector(inputWidth-1 downto 0);
vga_addr_y: in std_logic_vector(inputHeight-1 downto 0));
end frame_buf;
architecture arch of frame_buf is
signal t_addr, vga_addr: std_logic_vector((inputWidth + inputHeight) - 1 downto 0);
begin
t_addr <= iaddr_y & iaddr_x;
vga_addr <= vga_addr_y & vga_addr_x;
b: entity work.buf generic map(inputWidth + inputHeight) port map(clk, en, Din, Dout, t_addr, vga_addr);
end arch;
| gpl-3.0 |
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