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Separius/DigitalLogicDesign-FixedPoint-LnComputation | work/my_top/_primary.vhd | 1 | 384 | library verilog;
use verilog.vl_types.all;
entity my_top is
port(
ready : in vl_logic;
start : in vl_logic;
clk : in vl_logic;
reset : in vl_logic;
outBus : out vl_logic_vector(7 downto 0);
xBus : in vl_logic_vector(7 downto 0)
);
end my_top;
| gpl-3.0 |
Separius/DigitalLogicDesign-FixedPoint-LnComputation | work/ln_x_controller/_primary.vhd | 1 | 1172 | library verilog;
use verilog.vl_types.all;
entity ln_x_controller is
generic(
RAEDY : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
\INIT\ : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi1);
CALC_POW : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi0);
CALC_SUM : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi1)
);
port(
start : in vl_logic;
clk : in vl_logic;
reset : in vl_logic;
init : out vl_logic;
ldPow : out vl_logic;
ldRes : out vl_logic;
mul_mux : out vl_logic;
add_or_sub : out vl_logic;
ready : out vl_logic;
rom_addr : out vl_logic_vector(3 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of RAEDY : constant is 2;
attribute mti_svvh_generic_type of \INIT\ : constant is 2;
attribute mti_svvh_generic_type of CALC_POW : constant is 2;
attribute mti_svvh_generic_type of CALC_SUM : constant is 2;
end ln_x_controller;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_timer_v2_0/de85f913/hdl/src/vhdl/mux_onehot_f.vhd | 7 | 12551 | -- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
-- family_support
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
--library proc_common_v4_0;
--use proc_common_v4_0.family_support.all; -- 'supported' function, etc.
--
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
--constant NLS : natural := native_lut_size(fam_as_string => C_FAMILY,
constant NLS : natural := 6; --native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_timer_v2_0/de85f913/hdl/src/vhdl/mux_onehot_f.vhd | 7 | 12551 | -- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
-- family_support
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
--library proc_common_v4_0;
--use proc_common_v4_0.family_support.all; -- 'supported' function, etc.
--
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
--constant NLS : natural := native_lut_size(fam_as_string => C_FAMILY,
constant NLS : natural := 6; --native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/bocntr.vhd | 4 | 18015 | -------------------------------------------------------------------------------
-- bocntr - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : bocntr.vhd
-- Version : v2.0
-- Description : This is the transmit collision back off counter
-- the back off delay for retry n (1 <= n <= 16) is defined as
-- delay where delay is a uniformly distributed integer number
-- of slot times (512 bit times) defined as
-- 0 <= delay <= 2^k where k is min(n, 10) i.e., k is equal
-- to the retry attempt up to 10 and then remains at 10 for
-- retry attempts 11 through 16. So the delay for retry 1
-- would be 0, 1, or 2 slot times. The delay for retry 2
-- would be 0, 1, 2, 3, or 4 slot times.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Clken -- Clock enable
-- InitBackoff -- Backoff initialized
-- RetryCnt -- Retry count
-- BackingOff -- Backing off from transmit
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity bocntr is
port (
Clk : in std_logic; -- tx Clk based (2.5 or 25 MHz)
Clken : in std_logic;
Rst : in std_logic;
InitBackoff : in std_logic;
RetryCnt : in std_logic_vector(0 to 4);
BackingOff : out std_logic);
end bocntr;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of bocntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type StateName is (idle, shifting, inBackoff);
signal thisState : StateName;
signal nextState : StateName;
signal initBackoffLtch : std_logic;
signal initBackoffLtchRst : std_logic;
signal backingOff_i : std_logic;
signal lfsrOut : std_logic;
signal slotCntRst : std_logic;
signal slotCntEnbl : std_logic;
signal slotCnt : std_logic_vector(0 to 6);
signal backOffCntLd : std_logic;
signal backOffCntEnbl : std_logic;
signal backOffCnt : std_logic_vector(0 to 9);
signal shftCntLd : std_logic;
signal shftCntEnbl : std_logic;
signal shftCnt : std_logic_vector(0 to 3);
signal shftRst : std_logic;
signal shftEnbl : std_logic;
signal shftData : std_logic_vector(0 to 9);
signal slotDone : std_logic;
signal numRetries : std_logic_vector(0 to 3);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
LFSRP : entity axi_ethernetlite_v3_0.lfsr16
port map(
Rst => Rst,
Clk => Clk,
Clken => Clken,
Enbl => shftEnbl,
Shftout => lfsrOut);
numRetries <= "1010" when (((RetryCnt(1) = '1') and -- 8 or larger and
((RetryCnt(3) = '1') or -- 10, 11, 14, 15 or
(RetryCnt(2) = '1'))) or -- 12 thru 15
(RetryCnt(0) = '1')) else -- 12 thru 15
RetryCnt(1 to 4); -- 9 or less
-------------------------------------------------------------------------------
-- INT_SHFT_PROCESS
-------------------------------------------------------------------------------
INT_SHFT_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Clken = '1') then
if shftRst = '1' then
shftData <= (others => '0');
elsif (shftEnbl = '1') then
shftData(9) <= lfsrOut;
shftData(8) <= shftData(9);
shftData(7) <= shftData(8);
shftData(6) <= shftData(7);
shftData(5) <= shftData(6);
shftData(4) <= shftData(5);
shftData(3) <= shftData(4);
shftData(2) <= shftData(3);
shftData(1) <= shftData(2);
shftData(0) <= shftData(1);
-- coverage off
else
null;
-- coverage on
end if;
end if;
end if;
end process INT_SHFT_PROCESS;
-------------------------------------------------------------------------------
-- INT_SLOT_COUNT_PROCESS
-------------------------------------------------------------------------------
INT_SLOT_COUNT_PROCESS: process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Clken = '1') then
if ((slotCntRst = '1') or (slotDone = '1')) then
slotCnt <= "1111111";
elsif (slotCntEnbl = '1' and not(slotCnt = "0000000")) then
slotCnt <= slotCnt - 1;
-- coverage off
else
null;
-- coverage on
end if;
end if;
end if;
end process INT_SLOT_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- INT_BACKOFF_COUNT_PROCESS
-------------------------------------------------------------------------------
INT_BACKOFF_COUNT_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Clken = '1') then
if (backOffCntLd = '1') then
backOffCnt <= shftData;
elsif (backOffCntEnbl = '1' and not(backOffCnt = "0000000000") and
(slotDone = '1')) then
backOffCnt <= backOffCnt - 1;
-- coverage off
else
null;
-- coverage on
end if;
end if;
end if;
end process INT_BACKOFF_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- INT_SHIFT_COUNT_PROCESS
-------------------------------------------------------------------------------
INT_SHIFT_COUNT_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Clken = '1') then
if (shftCntLd = '1') then
shftCnt <= numRetries;
elsif (shftCntEnbl = '1' and not(shftCnt = "0000")) then
shftCnt <= shftCnt - 1;
-- coverage off
else
null;
-- coverage on
end if;
end if;
end if;
end process INT_SHIFT_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- INT_BACKOFFDONE_PROCESS
-------------------------------------------------------------------------------
INT_BACKOFFDONE_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = '1') then
backingOff_i <= '0';
elsif (InitBackoff = '1') then
backingOff_i <= '1';
elsif ((backOffCntEnbl = '1') and (backOffCnt = "000000000")) then
backingOff_i <= '0';
-- coverage off
else
null;
-- coverage on
end if;
end if;
end process INT_BACKOFFDONE_PROCESS;
BackingOff <= backingOff_i;
-------------------------------------------------------------------------------
-- INT_SLOT_TIME_DONE_PROCESS
-------------------------------------------------------------------------------
INT_SLOT_TIME_DONE_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = '1') then
slotDone <= '0';
elsif (slotCntEnbl = '0') then
slotDone <= '0';
elsif ((slotDone = '1') and (Clken = '1')) then
slotDone <= '0';
elsif ((slotCntEnbl = '1') and (slotCnt = "0000000")) then
slotDone <= '1';
else
null;
end if;
end if;
end process INT_SLOT_TIME_DONE_PROCESS;
-------------------------------------------------------------------------------
-- INT_LATCH_PROCESS
-------------------------------------------------------------------------------
INT_LATCH_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = '1') then
initBackoffLtch <= '0';
elsif (InitBackoff = '1') then
initBackoffLtch <= '1';
elsif (initBackoffLtchRst = '1') then
initBackoffLtch <= '0';
-- coverage off
else
null;
-- coverage on
-- coverage on
end if;
end if;
end process INT_LATCH_PROCESS;
-------------------------------------------------------------------------------
-- An FSM that deals with backing off
-------------------------------------------------------------------------------
FSMR : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
thisState <= idle;
elsif (Clken = '1') then
thisState <= nextState;
end if;
end if;
end process FSMR;
-------------------------------------------------------------------------------
-- State Machine
-------------------------------------------------------------------------------
FSMC : process (thisState,initBackoffLtch,shftCnt,backOffCnt)
begin --
case thisState is
when idle =>
if (initBackoffLtch = '1') then
nextState <= shifting;
else
nextState <= idle;
end if;
when shifting =>
if (shftCnt = "0000") then
nextState <= inBackoff;
else
nextState <= shifting;
end if;
when inBackoff =>
if (backOffCnt = "000000000") then
nextState <= idle;
else
nextState <= inBackoff;
end if;
-- coverage off
when others => null;
nextState <= idle;
-- coverage on
end case;
end process FSMC;
-------------------------------------------------------------------------------
-- State Machine Control signals generation
-------------------------------------------------------------------------------
FSMD : process(thisState)
begin
if (thisState = idle) then
shftRst <= '1';
shftCntLd <= '1';
else
shftRst <= '0';
shftCntLd <= '0';
end if;
if ((thisState = idle) or (thisState = shifting)) then
slotCntRst <= '1';
backOffCntLd <= '1';
else
slotCntRst <= '0';
backOffCntLd <= '0';
end if;
if (thisState = shifting) then
shftCntEnbl <= '1';
shftEnbl <= '1';
initBackoffLtchRst <= '1';
else
shftCntEnbl <= '0';
shftEnbl <= '0';
initBackoffLtchRst <= '0';
end if;
if (thisState = inBackoff) then
slotCntEnbl <= '1';
backOffCntEnbl <= '1';
else
slotCntEnbl <= '0';
backOffCntEnbl <= '0';
end if;
end process FSMD;
end implementation;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/synth/design_1_dlmb_bram_if_cntlr_0.vhd | 2 | 13330 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_bram_if_cntlr_v4_0;
USE lmb_bram_if_cntlr_v4_0.lmb_bram_if_cntlr;
ENTITY design_1_dlmb_bram_if_cntlr_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
);
END design_1_dlmb_bram_if_cntlr_0;
ARCHITECTURE design_1_dlmb_bram_if_cntlr_0_arch OF design_1_dlmb_bram_if_cntlr_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_bram_if_cntlr IS
GENERIC (
C_FAMILY : STRING;
C_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_NUM_LMB : INTEGER;
C_MASK : STD_LOGIC_VECTOR(0 TO 31);
C_MASK1 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK2 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK3 : STD_LOGIC_VECTOR(0 TO 31);
C_LMB_AWIDTH : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_ECC : INTEGER;
C_INTERCONNECT : INTEGER;
C_FAULT_INJECT : INTEGER;
C_CE_FAILING_REGISTERS : INTEGER;
C_UE_FAILING_REGISTERS : INTEGER;
C_ECC_STATUS_REGISTERS : INTEGER;
C_ECC_ONOFF_REGISTER : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER;
C_CE_COUNTER_WIDTH : INTEGER;
C_WRITE_ACCESS : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_AddrStrobe : IN STD_LOGIC;
LMB1_ReadStrobe : IN STD_LOGIC;
LMB1_WriteStrobe : IN STD_LOGIC;
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl1_Ready : OUT STD_LOGIC;
Sl1_Wait : OUT STD_LOGIC;
Sl1_UE : OUT STD_LOGIC;
Sl1_CE : OUT STD_LOGIC;
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_AddrStrobe : IN STD_LOGIC;
LMB2_ReadStrobe : IN STD_LOGIC;
LMB2_WriteStrobe : IN STD_LOGIC;
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl2_Ready : OUT STD_LOGIC;
Sl2_Wait : OUT STD_LOGIC;
Sl2_UE : OUT STD_LOGIC;
Sl2_CE : OUT STD_LOGIC;
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_AddrStrobe : IN STD_LOGIC;
LMB3_ReadStrobe : IN STD_LOGIC;
LMB3_WriteStrobe : IN STD_LOGIC;
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl3_Ready : OUT STD_LOGIC;
Sl3_Wait : OUT STD_LOGIC;
Sl3_UE : OUT STD_LOGIC;
Sl3_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
S_AXI_CTRL_ACLK : IN STD_LOGIC;
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_CTRL_WVALID : IN STD_LOGIC;
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
S_AXI_CTRL_BREADY : IN STD_LOGIC;
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
S_AXI_CTRL_RREADY : IN STD_LOGIC;
UE : OUT STD_LOGIC;
CE : OUT STD_LOGIC;
Interrupt : OUT STD_LOGIC
);
END COMPONENT lmb_bram_if_cntlr;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_dlmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "design_1_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "design_1_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x00007FFF,C_BASEADDR=0x00000000,C_NUM_LMB=1,C_MASK=0x40000000,C_MASK1=0x00800000,C_MASK2=0x00800000,C_MASK3=0x00800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAILING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
BEGIN
U0 : lmb_bram_if_cntlr
GENERIC MAP (
C_FAMILY => "artix7",
C_HIGHADDR => X"00007FFF",
C_BASEADDR => X"00000000",
C_NUM_LMB => 1,
C_MASK => X"40000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
PORT MAP (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_AddrStrobe => '0',
LMB1_ReadStrobe => '0',
LMB1_WriteStrobe => '0',
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_AddrStrobe => '0',
LMB2_ReadStrobe => '0',
LMB2_WriteStrobe => '0',
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_AddrStrobe => '0',
LMB3_ReadStrobe => '0',
LMB3_WriteStrobe => '0',
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Din_A => BRAM_Din_A,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_CTRL_WVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_RREADY => '0'
);
END design_1_dlmb_bram_if_cntlr_0_arch;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/876b8fe4/hdl/src/vhdl/address_decoder.vhd | 16 | 22444 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/axi_emc.vhd | 4 | 163491 | -------------------------------------------------------------------------------
-- $Id: axi_emc.vhd
-------------------------------------------------------------------------------
-- axi_emc.vhd - Entity and architecture
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_emc.vhd
-- Version: v2.0
-- Description: This is the top-level design file for the AXI External
-- Memory Controller.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_emc.vhd
-- -- axi_emc_native_interface.vhd
-- -- axi_emc_addr_gen.vhd
-- -- axi_emc_address_decode.vhd
-- -- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 10/02/10 -- created v1.01.a version
-- ^^^^^^
-- 1. Replaced the AXI Lite IPIF interface with AXI4 lite native interface
-- 2. Replaced the AXI Slave Burst interface with AXI4 full native interface
-- 3. Reduced the core utilization to resolve CR 573074
-- ~~~~~~
-- SK 12/02/10
-- ^^^^^^
-- 1. Added NO_REG_EN_GEN section to drive all the output signals in the register
-- interface to '0' when not selected.
-- ~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-- SK 04/14/13
-- ^^^^^^
-- -- Fixed CR 723506 - Fixed issues with the signal driven X when parity is enabled.
-- -- Fixed CR 721840 - Fixed issues in linear sync flash memory mode, parameter ordering is updated
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library emc_common_v3_0;
use emc_common_v3_0.all;
library axi_emc_v3_0;
use axi_emc_v3_0.all;
use axi_emc_v3_0.emc_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- C_NUM_BANKS_MEM -- Number of memory banks
-- C_MEM0_TYPE -- Type of Memory
-- 0-> Sync SRAM
-- 1-> Async SRAM
-- 2-> Nor Flash
-- 3-> Page Mode Nor Flash
-- 4-> Cellar RAM/PSRAM
-- C_PARITY_TYPE_MEM_0 -- Type of Parity
-- 0-> No Parity
-- 1-> Odd Parity
-- 2-> Even Parity
-- C_INCLUDE_NEGEDGE_IOREGS -- Include negative edge IO registers
-- C_NUM_MASTERS -- Number of axi masters
-- C_MEM(0:3)_BASEADDR -- Memory bank (0:3) base address
-- C_MEM(0:3)_HIGHADDR -- Memory bank (0:3) high address
-- C_MEM(0:3)_WIDTH -- Memory bank (0:3) data width
-- C_MAX_MEM_WIDTH -- Maximum data width of all memory banks
--
-- C_INCLUDE_DATAWIDTH_MATCHING_(0:3) -- Support data width matching for
-- memory bank (0:3)
-- C_SYNCH_MEM_(0:3) -- Memory bank (0:3) type
-- C_SYNCH_PIPEDELAY_(0:3) -- Memory bank (0:3) synchronous pipedelay
-- C_TCEDV_PS_MEM_(0:3) -- Chip Enable to Data Valid Time
-- -- (Maximum of TCEDV and TAVDV applied
-- as read cycle start to first data valid)
-- C_TAVDV_PS_MEM_(0:3) -- Address Valid to Data Valid Time
-- -- (Maximum of TCEDV and TAVDV applied
-- as read cycle start to first data valid)
-- C_THZCE_PS_MEM_(0:3) -- Chip Enable High to Data Bus High
-- Impedance (Maximum of THZCE and THZOE
-- applied as Read Recovery before Write)
-- C_THZOE_PS_MEM_(0:3) -- Output Enable High to Data Bus High
-- Impedance (Maximum of THZCE and THZOE
-- applied as Read Recovery before Write)
-- C_TWC_PS_MEM_(0:3) -- Write Cycle Time
-- (Maximum of TWC and TWP applied as write
-- enable pulse width)
-- C_TWP_PS_MEM_(0:3) -- Write Enable Minimum Pulse Width
-- (Maximum of TWC and TWP applied as write
-- enable pulse width)
-- C_TLZWE_PS_MEM_(0:3) -- Write Enable High to Data Bus Low
-- Impedance (Applied as Write Recovery
-- before Read)
-- C_WR_REC_TIME_MEM_0 -- Write recovery time between the write
-- -- and next consecutive read transaction
-- C_S_AXI_MEM_DWIDTH -- axi Data Bus Width
-- C_S_AXI_MEM_AWIDTH -- axi Address Width
-- C_AXI_CLK_PERIOD_PS -- axi clock period to calculate wait
-- state pulse widths.
--
--
-- Definition of Ports:
-- Memory Signals
-- mem_a -- Memory address inputs
-- mem_dq_i -- Memory Input Data Bus
-- mem_dq_o -- Memory Output Data Bus
-- mem_dq_t -- Memory Data Output Enable
-- mem_dq_parity_i -- Memory Parity Input Data Bus
-- mem_dq_parity_o -- Memory Parity Output Data Bus
-- mem_dq_parity_t -- Memory Parity Output Enable
-- mem_cen -- Memory Chip Select
-- mem_oen -- Memory Output Enable
-- mem_wen -- Memory Write Enable
-- mem_qwen -- Memory Qualified Write Enable
-- mem_ben -- Memory Byte Enables
-- mem_rpn -- Memory Reset/Power Down
-- mem_ce -- Memory chip enable
-- mem_adv_ldn -- Memory counter advance/load (=0)
-- mem_lbon -- Memory linear/interleaved burst order (=0)
-- mem_cken -- Memory clock enable (=0)
-- mem_rnw -- Memory read not write
-------------------------------------------------------------------------------
entity axi_emc is
-- Generics to be set by user
generic (
C_FAMILY : string := "virtex6";
C_INSTANCE : string := "axi_emc_inst";
C_AXI_CLK_PERIOD_PS : integer := 10000;
C_LFLASH_PERIOD_PS : integer := 20000;
C_LINEAR_FLASH_SYNC_BURST : integer range 0 to 1 := 0;
---- AXI REG Parameters
C_S_AXI_REG_ADDR_WIDTH : integer range 5 to 5 := 5;
C_S_AXI_REG_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_EN_REG : integer range 0 to 1 := 0;
----C_S_AXI_REG_BASEADDR : std_logic_vector := x"FFFFFFFF";
----C_S_AXI_REG_HIGHADDR : std_logic_vector := x"00000000";
---- AXI MEM Parameters
C_S_AXI_MEM_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MEM_DATA_WIDTH : integer := 32;--8,16,32,64
C_S_AXI_MEM_ID_WIDTH : integer range 1 to 16 := 4;
C_S_AXI_MEM0_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM0_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM1_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM1_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM2_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM2_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM3_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM3_HIGHADDR : std_logic_vector := x"00000000";
-- EMC generics
C_INCLUDE_NEGEDGE_IOREGS : integer range 0 to 1 := 0;
C_NUM_BANKS_MEM : integer range 1 to 4 := 1;
C_MEM0_TYPE : integer range 0 to 5 := 0;
C_MEM1_TYPE : integer range 0 to 5 := 0;
C_MEM2_TYPE : integer range 0 to 5 := 0;
C_MEM3_TYPE : integer range 0 to 5 := 0;
C_MEM0_WIDTH : integer := 32;--8,16,32,64 allowed
C_MEM1_WIDTH : integer := 32;--8,16,32,64
C_MEM2_WIDTH : integer := 32;--8,16,32,64
C_MEM3_WIDTH : integer := 32;--8,16,32,64
C_MAX_MEM_WIDTH : integer := 32;--8,16,32,64
-- parity type of memory 0-no parity, 1-odd parity, 2-even parity
C_PARITY_TYPE_MEM_0 : integer range 0 to 2 := 0;
C_PARITY_TYPE_MEM_1 : integer range 0 to 2 := 0;
C_PARITY_TYPE_MEM_2 : integer range 0 to 2 := 0;
C_PARITY_TYPE_MEM_3 : integer range 0 to 2 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_0 : integer range 0 to 1 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_1 : integer range 0 to 1 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_2 : integer range 0 to 1 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_3 : integer range 0 to 1 := 0;
-- Memory read and write access times for all memory banks
C_SYNCH_PIPEDELAY_0 : integer range 1 to 2 := 2;
C_TCEDV_PS_MEM_0 : integer := 15000;
C_TAVDV_PS_MEM_0 : integer := 15000;
C_TPACC_PS_FLASH_0 : integer := 25000;
C_THZCE_PS_MEM_0 : integer := 7000;
C_THZOE_PS_MEM_0 : integer := 7000;
C_TWC_PS_MEM_0 : integer := 15000;
C_TWP_PS_MEM_0 : integer := 12000;
C_TWPH_PS_MEM_0 : integer := 12000;
C_TLZWE_PS_MEM_0 : integer := 0;
C_WR_REC_TIME_MEM_0 : integer := 270000000;
C_SYNCH_PIPEDELAY_1 : integer range 1 to 2 := 2;
C_TCEDV_PS_MEM_1 : integer := 15000;
C_TAVDV_PS_MEM_1 : integer := 15000;
C_TPACC_PS_FLASH_1 : integer := 25000;
C_THZCE_PS_MEM_1 : integer := 7000;
C_THZOE_PS_MEM_1 : integer := 7000;
C_TWC_PS_MEM_1 : integer := 15000;
C_TWP_PS_MEM_1 : integer := 12000;
C_TWPH_PS_MEM_1 : integer := 12000;
C_TLZWE_PS_MEM_1 : integer := 0;
C_WR_REC_TIME_MEM_1 : integer := 270000000;
C_SYNCH_PIPEDELAY_2 : integer range 1 to 2 := 2;
C_TCEDV_PS_MEM_2 : integer := 15000;
C_TAVDV_PS_MEM_2 : integer := 15000;
C_TPACC_PS_FLASH_2 : integer := 25000;
C_THZCE_PS_MEM_2 : integer := 7000;
C_THZOE_PS_MEM_2 : integer := 7000;
C_TWC_PS_MEM_2 : integer := 15000;
C_TWP_PS_MEM_2 : integer := 12000;
C_TWPH_PS_MEM_2 : integer := 12000;
C_TLZWE_PS_MEM_2 : integer := 0;
C_WR_REC_TIME_MEM_2 : integer := 270000000;
C_SYNCH_PIPEDELAY_3 : integer range 1 to 2 := 2;
C_TCEDV_PS_MEM_3 : integer := 15000;
C_TAVDV_PS_MEM_3 : integer := 15000;
C_TPACC_PS_FLASH_3 : integer := 25000;
C_THZCE_PS_MEM_3 : integer := 7000;
C_THZOE_PS_MEM_3 : integer := 7000;
C_TWC_PS_MEM_3 : integer := 15000;
C_TWP_PS_MEM_3 : integer := 12000;
C_TWPH_PS_MEM_3 : integer := 12000;
C_TLZWE_PS_MEM_3 : integer := 0 ;
C_WR_REC_TIME_MEM_3 : integer := 270000000
);
port (
-- -- AXI Slave signals ------------------------------------------------------
-- AXI Global System Signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
rdclk : in std_logic;
-- axi lite interface
-- -- axi write address Channel Signals
s_axi_reg_awaddr : in std_logic_vector
(4 downto 0);
s_axi_reg_awvalid : in std_logic;
s_axi_reg_awready : out std_logic;
-- -- axi write channel Signals
s_axi_reg_wdata : in std_logic_vector
(31 downto 0);
s_axi_reg_wstrb : in std_logic_vector
(3 downto 0);
s_axi_reg_wvalid : in std_logic;
s_axi_reg_wready : out std_logic;
-- -- axi write response Channel Signals
s_axi_reg_bresp : out std_logic_vector(1 downto 0);
s_axi_reg_bvalid : out std_logic;
s_axi_reg_bready : in std_logic;
-- -- axi read address Channel Signals
s_axi_reg_araddr : in std_logic_vector
(4 downto 0);
s_axi_reg_arvalid : in std_logic;
s_axi_reg_arready : out std_logic;
-- -- axi read data Channel Signals
s_axi_reg_rdata : out std_logic_vector
(31 downto 0);
s_axi_reg_rresp : out std_logic_vector(1 downto 0);
s_axi_reg_rvalid : out std_logic;
s_axi_reg_rready : in std_logic;
-- -- axi full interface
-- -- axi write address Channel Signals
s_axi_mem_awid : in std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
s_axi_mem_awaddr : in std_logic_vector(31 downto 0);
s_axi_mem_awlen : in std_logic_vector(7 downto 0);
s_axi_mem_awsize : in std_logic_vector(2 downto 0);
s_axi_mem_awburst : in std_logic_vector(1 downto 0);
s_axi_mem_awlock : in std_logic;
s_axi_mem_awcache : in std_logic_vector(3 downto 0);
s_axi_mem_awprot : in std_logic_vector(2 downto 0);
s_axi_mem_awvalid : in std_logic;
s_axi_mem_awready : out std_logic;
-- -- axi write channel Signals
s_axi_mem_wdata : in std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1)
downto 0);
s_axi_mem_wstrb : in std_logic_vector
(((C_S_AXI_MEM_DATA_WIDTH/8)-1) downto 0);
s_axi_mem_wlast : in std_logic;
s_axi_mem_wvalid : in std_logic;
s_axi_mem_wready : out std_logic;
-- -- axi write response Channel Signals
s_axi_mem_bid : out std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
s_axi_mem_bresp : out std_logic_vector(1 downto 0);
s_axi_mem_bvalid : out std_logic;
s_axi_mem_bready : in std_logic;
-- -- axi read address Channel Signals
s_axi_mem_arid : in std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1) downto 0);
s_axi_mem_araddr : in std_logic_vector(31 downto 0);
s_axi_mem_arlen : in std_logic_vector(7 downto 0);
s_axi_mem_arsize : in std_logic_vector(2 downto 0);
s_axi_mem_arburst : in std_logic_vector(1 downto 0);
s_axi_mem_arlock : in std_logic;
s_axi_mem_arcache : in std_logic_vector(3 downto 0);
s_axi_mem_arprot : in std_logic_vector(2 downto 0);
s_axi_mem_arvalid : in std_logic;
s_axi_mem_arready : out std_logic;
-- -- axi read data Channel Signals
s_axi_mem_rid : out std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
s_axi_mem_rdata : out std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1)
downto 0);
s_axi_mem_rresp : out std_logic_vector(1 downto 0);
s_axi_mem_rlast : out std_logic;
s_axi_mem_rvalid : out std_logic;
s_axi_mem_rready : in std_logic;
-- memory signals
mem_dq_i : in std_logic_vector((C_MAX_MEM_WIDTH-1) downto 0);
mem_dq_o : out std_logic_vector((C_MAX_MEM_WIDTH-1) downto 0);
mem_dq_t : out std_logic_vector((C_MAX_MEM_WIDTH-1) downto 0);
mem_dq_parity_i : in std_logic_vector(((C_MAX_MEM_WIDTH/8)-1) downto 0);
mem_dq_parity_o : out std_logic_vector(((C_MAX_MEM_WIDTH/8)-1) downto 0);
mem_dq_parity_t : out std_logic_vector(((C_MAX_MEM_WIDTH/8)-1) downto 0);
mem_a : out std_logic_vector(31 downto 0);
-- chip selects
mem_ce : out std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
mem_cen : out std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
-- read enable
mem_oen : out std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
-- write enable
mem_wen : out std_logic;-- write enable
-- byte enables
mem_ben : out std_logic_vector((C_MAX_MEM_WIDTH/8-1) downto 0);
mem_qwen : out std_logic_vector((C_MAX_MEM_WIDTH/8-1) downto 0);
-- reset or power down
mem_rpn : out std_logic;
-- address valid active low
mem_adv_ldn : out std_logic;
-- interleaved burst order
mem_lbon : out std_logic;
-- clock enable
mem_cken : out std_logic;
-- synch mem read not write signal
mem_rnw : out std_logic;
--
mem_cre : out std_logic;
mem_wait : in std_logic_vector(C_NUM_BANKS_MEM -1 downto 0)
);
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
attribute MAX_FANOUT of rdclk : signal is "10000";
-- Added attribute to FIX CR CR204317. The following attribute prevent
-- the tools from optimizing the tristate control down to a single
-- registered signal and to pack input, output, and tri-state registers
-- into the IOB.
attribute EQUIVALENT_REGISTER_REMOVAL : string;
attribute EQUIVALENT_REGISTER_REMOVAL of Mem_DQ_T: signal is "no";
attribute EQUIVALENT_REGISTER_REMOVAL of MEM_DQ_PARITY_T: signal is "no";
-- SIGIS attribute for specifying clocks,interrrupts,resets for EDK
attribute SIGIS : string;
attribute SIGIS of s_axi_aclk : signal is "Clk" ;
attribute SIGIS of s_axi_aresetn : signal is "Rst" ;
attribute SIGIS of rdclk : signal is "Clk" ;
-- Minimum size attribute for EDK
attribute MIN_SIZE : string;
attribute MIN_SIZE of C_S_AXI_MEM0_BASEADDR : constant is "0x08";
attribute MIN_SIZE of C_S_AXI_MEM1_BASEADDR : constant is "0x08";
attribute MIN_SIZE of C_S_AXI_MEM2_BASEADDR : constant is "0x08";
attribute MIN_SIZE of C_S_AXI_MEM3_BASEADDR : constant is "0x08";
-- Assignment attribute for EDK
attribute ASSIGNMENT : string;
attribute ASSIGNMENT of C_S_AXI_MEM0_BASEADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM0_HIGHADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM1_BASEADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM1_HIGHADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM2_BASEADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM2_HIGHADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM3_BASEADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM3_HIGHADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM_ADDR_WIDTH : constant is "CONSTANT";
-- ADDR_TYPE attribute for EDK
attribute ADDR_TYPE : string;
attribute ADDR_TYPE of C_S_AXI_MEM0_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM0_HIGHADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM1_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM1_HIGHADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM2_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM2_HIGHADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM3_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM3_HIGHADDR : constant is "MEMORY";
------------------------------------------------------------------------------
-- end of PSFUtil MPD attributes
------------------------------------------------------------------------------
end axi_emc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_emc is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
--constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_emc,{"
-- & "c_family=" & C_FAMILY
-- & ",c_instance=" & C_INSTANCE
-- & ",c_axi_clk_period_ps=" & integer'image(C_AXI_CLK_PERIOD_PS)
-- & ",c_lflash_period_ps=" & integer'image(C_LFLASH_PERIOD_PS)
-- & ",c_linear_flash_sync_burst=" & integer'image(C_LINEAR_FLASH_SYNC_BURST)
-- & ",c_s_axireg_addr_width=" & integer'image(C_S_AXI_REG_ADDR_WIDTH)
-- & ",c_s_axi_reg_data_width=" & integer'image(C_S_AXI_REG_DATA_WIDTH)
-- & ",c_s_axi_en_reg=" & integer'image(C_S_AXI_EN_REG)
-- & ",c_s_axi_mem_addr_width=" & integer'image(C_S_AXI_MEM_ADDR_WIDTH)
-- & ",c_s_axi_mem_data_width=" & integer'image(C_S_AXI_MEM_DATA_WIDTH)
-- & ",c_s_axi_mem_id_width=" & integer'image(C_S_AXI_MEM_ID_WIDTH)
-- & ",c_include_negedge_ioregs=" & integer'image(C_INCLUDE_NEGEDGE_IOREGS)
-- & ",c_num_banks_mem=" & integer'image(C_NUM_BANKS_MEM)
-- & ",c_mem0_type=" & integer'image(C_MEM0_TYPE)
-- & ",c_mem1_type=" & integer'image(C_MEM1_TYPE)
-- & ",c_mem2_type=" & integer'image(C_MEM2_TYPE)
-- & ",c_mem3_type=" & integer'image(C_MEM3_TYPE)
-- & ",c_mem0_width=" & integer'image(C_MEM0_WIDTH)
-- & ",c_mem1_width=" & integer'image(C_MEM1_WIDTH)
-- & ",c_mem2_width=" & integer'image(C_MEM2_WIDTH)
-- & ",c_mem3_width=" & integer'image(C_MEM3_WIDTH)
-- & ",c_max_mem_width=" & integer'image(C_MAX_MEM_WIDTH)
-- & ",c_parity_type_mem_0=" & integer'image(C_PARITY_TYPE_MEM_0)
-- & ",c_parity_type_mem_1=" & integer'image(C_PARITY_TYPE_MEM_1)
-- & ",c_parity_type_mem_2=" & integer'image(C_PARITY_TYPE_MEM_2)
-- & ",c_parity_type_mem_3=" & integer'image(C_PARITY_TYPE_MEM_3)
-- & ",c_include_datawidth_matching_0=" & integer'image(C_INCLUDE_DATAWIDTH_MATCHING_0)
-- & ",c_include_datawidth_matching_1=" & integer'image(C_INCLUDE_DATAWIDTH_MATCHING_1)
-- & ",c_include_datawidth_matching_2=" & integer'image(C_INCLUDE_DATAWIDTH_MATCHING_2)
-- & ",c_include_datawidth_matching_3=" & integer'image(C_INCLUDE_DATAWIDTH_MATCHING_3)
-- & ",c_synch_pipedelay_0=" & integer'image(C_SYNCH_PIPEDELAY_0)
-- & ",c_synch_pipedelay_1=" & integer'image(C_SYNCH_PIPEDELAY_1)
-- & ",c_synch_pipedelay_2=" & integer'image(C_SYNCH_PIPEDELAY_2)
-- & ",c_synch_pipedelay_3=" & integer'image(C_SYNCH_PIPEDELAY_3)
-- & ",c_tcedv_ps_mem_0=" & integer'image(C_TCEDV_PS_MEM_0)
-- & ",c_tcedv_ps_mem_1=" & integer'image(C_TCEDV_PS_MEM_1)
-- & ",c_tcedv_ps_mem_2=" & integer'image(C_TCEDV_PS_MEM_2)
-- & ",c_tcedv_ps_mem_=3" & integer'image(C_TCEDV_PS_MEM_3)
-- & ",c_tavdv_ps_mem_0=" & integer'image(C_TAVDV_PS_MEM_0)
-- & ",c_tavdv_ps_mem_1=" & integer'image(C_TAVDV_PS_MEM_1)
-- & ",c_tavdv_ps_mem_2=" & integer'image(C_TAVDV_PS_MEM_2)
-- & ",c_tavdv_ps_mem_3=" & integer'image(C_TAVDV_PS_MEM_3)
-- & ",c_tpacc_ps_flash_0=" & integer'image(C_TPACC_PS_FLASH_0)
-- & ",c_tpacc_ps_flash_1=" & integer'image(C_TPACC_PS_FLASH_1)
-- & ",c_tpacc_ps_flash_2=" & integer'image(C_TPACC_PS_FLASH_2)
-- & ",c_tpacc_ps_flash_3=" & integer'image(C_TPACC_PS_FLASH_3)
-- & ",c_thzce_ps_mem_0=" & integer'image(C_THZCE_PS_MEM_0)
-- & ",c_thzce_ps_mem_1=" & integer'image(C_THZCE_PS_MEM_1)
-- & ",c_thzce_ps_mem_2=" & integer'image(C_THZCE_PS_MEM_2)
-- & ",c_thzce_ps_mem_3=" & integer'image(C_THZCE_PS_MEM_3)
-- & ",c_thzoe_ps_mem_0=" & integer'image(C_THZOE_PS_MEM_0)
-- & ",c_thzoe_ps_mem_1=" & integer'image(C_THZOE_PS_MEM_1)
-- & ",c_thzoe_ps_mem_2=" & integer'image(C_THZOE_PS_MEM_2)
-- & ",c_thzoe_ps_mem_3=" & integer'image(C_THZOE_PS_MEM_3)
-- & ",c_twc_ps_mem_0=" & integer'image(C_TWC_PS_MEM_0)
-- & ",c_twc_ps_mem_1=" & integer'image(C_TWC_PS_MEM_1)
-- & ",c_twc_ps_mem_2=" & integer'image(C_TWC_PS_MEM_2)
-- & ",c_twc_ps_mem_3=" & integer'image(C_TWC_PS_MEM_3)
-- & ",c_twp_ps_mem_0=" & integer'image(C_TWP_PS_MEM_0)
-- & ",c_twp_ps_mem_1=" & integer'image(C_TWP_PS_MEM_1)
-- & ",c_twp_ps_mem_2=" & integer'image(C_TWP_PS_MEM_2)
-- & ",c_twp_ps_mem_3=" & integer'image(C_TWP_PS_MEM_3)
-- & ",c_twph_ps_mem_0=" & integer'image(C_TWPH_PS_MEM_0)
-- & ",c_twph_ps_mem_1=" & integer'image(C_TWPH_PS_MEM_1)
-- & ",c_twph_ps_mem_2=" & integer'image(C_TWPH_PS_MEM_2)
-- & ",c_twph_ps_mem_3=" & integer'image(C_TWPH_PS_MEM_3)
-- & ",c_tlzwe_ps_mem_0=" & integer'image(C_TLZWE_PS_MEM_0)
-- & ",c_tlzwe_ps_mem_1=" & integer'image(C_TLZWE_PS_MEM_1)
-- & ",c_tlzwe_ps_mem_2=" & integer'image(C_TLZWE_PS_MEM_2)
-- & ",c_tlzwe_ps_mem_3=" & integer'image(C_TLZWE_PS_MEM_3)
-- & ",c_wr_rec_time_mem_0=" & integer'image(C_WR_REC_TIME_MEM_0)
-- & ",c_wr_rec_time_mem_1=" & integer'image(C_WR_REC_TIME_MEM_1)
-- & ",c_wr_rec_time_mem_2=" & integer'image(C_WR_REC_TIME_MEM_2)
-- & ",c_wr_rec_time_mem_3=" & integer'image(C_WR_REC_TIME_MEM_3)
-- & "}";
--
-- attribute CORE_GENERATION_INFO : string;
-- attribute CORE_GENERATION_INFO of implementation : architecture is C_CORE_GENERATION_INFO;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- addresses for axi_slave_burst are 64-bits wide - create constants to
-- zero the most significant address bits
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_S_AXI_MEM_ADDR_WIDTH-1)
:= (others => '0');
-- four banks with SRAM, ASYNC SRAM, PSRAM, Cellular RAM, Flash memory
type MEM_TYPE_ARRAY_TYPE is array (0 to 3) of integer range 0 to 5;
type MEM_PARITY_ARRAY_TYPE is array (0 to 3) of integer range 0 to 2;
-----------------------------------------------------------------------------
-- Function: get_AXI_ARD_ADDR_RANGE_ARRAY
-- Purpose: Fill AXI_ARD_ADDR_RANGE_ARRAY based on input parameters
-----------------------------------------------------------------------------
function get_AXI_ARD_ADDR_RANGE_ARRAY return SLV64_ARRAY_TYPE is
variable axi_ard_addr_range_array_v : SLV64_ARRAY_TYPE
(0 to C_NUM_BANKS_MEM*2-1);
begin
if (C_NUM_BANKS_MEM = 1) then
axi_ard_addr_range_array_v(0) := ZERO_ADDR_PAD&C_S_AXI_MEM0_BASEADDR;
axi_ard_addr_range_array_v(1) := ZERO_ADDR_PAD&C_S_AXI_MEM0_HIGHADDR;
elsif (C_NUM_BANKS_MEM = 2) then
axi_ard_addr_range_array_v(0) := ZERO_ADDR_PAD&C_S_AXI_MEM0_BASEADDR;
axi_ard_addr_range_array_v(1) := ZERO_ADDR_PAD&C_S_AXI_MEM0_HIGHADDR;
axi_ard_addr_range_array_v(2) := ZERO_ADDR_PAD&C_S_AXI_MEM1_BASEADDR;
axi_ard_addr_range_array_v(3) := ZERO_ADDR_PAD&C_S_AXI_MEM1_HIGHADDR;
elsif (C_NUM_BANKS_MEM = 3) then
axi_ard_addr_range_array_v(0) := ZERO_ADDR_PAD&C_S_AXI_MEM0_BASEADDR;
axi_ard_addr_range_array_v(1) := ZERO_ADDR_PAD&C_S_AXI_MEM0_HIGHADDR;
axi_ard_addr_range_array_v(2) := ZERO_ADDR_PAD&C_S_AXI_MEM1_BASEADDR;
axi_ard_addr_range_array_v(3) := ZERO_ADDR_PAD&C_S_AXI_MEM1_HIGHADDR;
axi_ard_addr_range_array_v(4) := ZERO_ADDR_PAD&C_S_AXI_MEM2_BASEADDR;
axi_ard_addr_range_array_v(5) := ZERO_ADDR_PAD&C_S_AXI_MEM2_HIGHADDR;
else
axi_ard_addr_range_array_v(0) := ZERO_ADDR_PAD&C_S_AXI_MEM0_BASEADDR;
axi_ard_addr_range_array_v(1) := ZERO_ADDR_PAD&C_S_AXI_MEM0_HIGHADDR;
axi_ard_addr_range_array_v(2) := ZERO_ADDR_PAD&C_S_AXI_MEM1_BASEADDR;
axi_ard_addr_range_array_v(3) := ZERO_ADDR_PAD&C_S_AXI_MEM1_HIGHADDR;
axi_ard_addr_range_array_v(4) := ZERO_ADDR_PAD&C_S_AXI_MEM2_BASEADDR;
axi_ard_addr_range_array_v(5) := ZERO_ADDR_PAD&C_S_AXI_MEM2_HIGHADDR;
axi_ard_addr_range_array_v(6) := ZERO_ADDR_PAD&C_S_AXI_MEM3_BASEADDR;
axi_ard_addr_range_array_v(7) := ZERO_ADDR_PAD&C_S_AXI_MEM3_HIGHADDR;
end if;
return axi_ard_addr_range_array_v;
end function get_AXI_ARD_ADDR_RANGE_ARRAY;
constant AXI_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= get_AXI_ARD_ADDR_RANGE_ARRAY;
-----------------------------------------------------------------------------
-- Function: get_axi_ard_num_ce_array
-- Purpose: Fill AXI_NUM_CE_ARRAY based on input parameters
-----------------------------------------------------------------------------
function get_axi_ard_num_ce_array return INTEGER_ARRAY_TYPE is
variable axi_ard_num_ce_array_v : INTEGER_ARRAY_TYPE(0 to C_NUM_BANKS_MEM-1);
begin
if (C_NUM_BANKS_MEM = 1) then
axi_ard_num_ce_array_v(0) := 1; -- memories have only 1 CE
elsif (C_NUM_BANKS_MEM = 2) then
axi_ard_num_ce_array_v(0) := 1;
axi_ard_num_ce_array_v(1) := 1;
elsif (C_NUM_BANKS_MEM = 3) then
axi_ard_num_ce_array_v(0) := 1;
axi_ard_num_ce_array_v(1) := 1;
axi_ard_num_ce_array_v(2) := 1;
else
axi_ard_num_ce_array_v(0) := 1;
axi_ard_num_ce_array_v(1) := 1;
axi_ard_num_ce_array_v(2) := 1;
axi_ard_num_ce_array_v(3) := 1;
end if;
return axi_ard_num_ce_array_v;
end function get_axi_ard_num_ce_array;
-------------------------------------------------------------------------------
-- constant declaration
-----------------------
constant AXI_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
:= get_axi_ard_num_ce_array;
-- axi full read/write interconnect related parameters
constant C_S_AXI_MEM_SUPPORTS_WRITE : integer := 1;
constant C_S_AXI_MEM_SUPPORTS_READ : integer := 1;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
--IPIC request qualifier signals
signal ip2bus_rdack : std_logic;
signal ip2bus_wrack : std_logic;
signal ip2bus_addrack : std_logic;
signal ip2bus_errack : std_logic;
-- IPIC address, data signals
signal ip2bus_data : std_logic_vector(0 to (C_S_AXI_MEM_DATA_WIDTH-1));
signal bus2ip_addr : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
signal bus2ip_addr_temp : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
-- lower two bits address to generate the byte level address
signal bus2ip_addr_reg : std_logic_vector(0 to 2);
-- Bus2IP_* Signals
signal bus2ip_data : std_logic_vector(0 to (C_S_AXI_MEM_DATA_WIDTH-1));
-- below little endian signals are for data & BE swapping
signal temp_bus2ip_data : std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
signal temp_ip2bus_data : std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
signal temp_bus2ip_be : std_logic_vector(((C_S_AXI_MEM_DATA_WIDTH/8)-1) downto 0);
--
signal bus2ip_rnw : std_logic;
signal bus2ip_rdreq_i : std_logic;
signal bus2ip_wrreq_i : std_logic;
--
signal bus2ip_cs_i : std_logic;
----
signal bus2ip_cs : std_logic_vector
(0 to ((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
-- big endian bus2ip_cs is used for EMC to maintain its big-endian structure
----
signal temp_bus2ip_cs : std_logic_vector
(((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
----
signal bus2ip_rdce : std_logic_vector
(0 to calc_num_ce(AXI_ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector
(0 to calc_num_ce(AXI_ARD_NUM_CE_ARRAY)-1);
--
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_MEM_DATA_WIDTH/8)-1);
signal bus2ip_burst : std_logic;
-- External memory signals
signal mem_dq_o_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
signal mem_dq_i_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
signal mem_dq_t_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
signal mem_dq_parity_o_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
signal mem_dq_parity_t_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
signal mem_dq_parity_i_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
--
signal parity_error_adrss : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
signal parity_error_MEM : std_logic_vector(1 downto 0);
signal err_parity_bits : std_logic_vector(2 downto 0);
--
signal mem_cen_i : std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
signal mem_oen_i : std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
signal mem_wen_i : std_logic;
signal mem_qwen_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
signal mem_ben_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
signal mem_adv_ldn_i : std_logic;
signal mem_cken_i : std_logic;
signal mem_ce_i : std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
signal mem_a_i : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
signal bus2ip_burstlength : std_logic_vector(0 to 7);
signal Type_of_xfer : std_logic;
signal psram_page_mode : std_logic;
signal bus2ip_reset : std_logic;
signal temp_single_0 : std_logic;
signal temp_single_1 : std_logic;
signal temp_single_2 : std_logic;
signal or_reduced_rdce_d1 : std_logic;
signal or_reduced_wrce : std_logic;
signal bus2ip_wrreq_reg : std_logic;
signal original_wrce : std_logic;
signal Bus2IP_RdReq_emc : std_logic;
signal Bus2IP_WrReq_emc : std_logic;
signal synch_mem, last_addr1 : std_logic;
signal axi_trans_size_reg_int : std_logic_vector(1 downto 0); -- 1/3/2013
signal axi_lite_ip2bus_wrack_d1: std_logic;
signal axi_arsize : std_logic_vector(2 downto 0) := (OTHERS => '0');
--*
--**
-------------------------------------------------------------------------------
-- not_all_psram: checks if any of the memory is of PSRAM type. PSRAM is assigned
---------------- with value 4, so check if MEM_TYPE = 4 and return 0 or 1.
function not_all_psram(input_array : MEM_TYPE_ARRAY_TYPE;
num_real_elements : integer)
return integer is
variable sum : integer range 0 to 4 := 0;
begin
for i in 0 to num_real_elements -1 loop
if input_array(i) = 4 then
sum := sum + 1;
end if;
end loop;
if sum = 0 then
return 0;
else
return 1;
end if;
end function not_all_psram;
-------------------------------------------------------------------------------
-- not_all_parity : check if any of the memory is assigned with PARITY bit
------------------ if any of the memory is assigned with parity, return 1.
function not_all_parity(input_array : MEM_PARITY_ARRAY_TYPE;
num_real_elements : integer)
return integer is
variable sum : integer range 0 to 4 := 0;
begin
for i in 0 to num_real_elements -1 loop
if input_array(i) /= 0 then
sum := sum + 1;
end if;
end loop;
if sum = 0 then
return 0;
else
return 1;
end if;
end function not_all_parity;
-------------------------------------------------------------------------------
-- sync_get_val: Check if the memory is SYNC memory type, if yes return 1.
---------------
function sync_get_val(x: integer; y: integer) return integer is
begin
if x = 0 then
return 1;
else
return 0;
end if;
end function sync_get_val;
-------------------------------------------------------------------------------
-- page_get_val: If Page Mode Flash or PSRAM, then return 1.
---------------
function page_get_val(x: integer) return integer is
begin
if x = 3 or x = 4 then
return 1;
else
return 0;
end if;
end function page_get_val;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- psram_or_lflash_sync: If PSRAM or Linear Flash sync burst, then return 1.
---------------
function psram_or_lflash_sync(x: integer; y: integer) return integer is
begin
if ((x = 1) or (y = 1)) then
return 1;
else
return 0;
end if;
end function psram_or_lflash_sync;
-------------------------------------------------------------------------------
constant MEM_TYPE_ARRAY : MEM_TYPE_ARRAY_TYPE :=
(
C_MEM0_TYPE,
C_MEM1_TYPE,
C_MEM2_TYPE,
C_MEM3_TYPE
);
constant MEM_PARITY_ARRAY : MEM_PARITY_ARRAY_TYPE :=
(
C_PARITY_TYPE_MEM_0,
C_PARITY_TYPE_MEM_1,
C_PARITY_TYPE_MEM_2,
C_PARITY_TYPE_MEM_3
);
constant GLOBAL_PSRAM_MEM : integer range 0 to 1
:= not_all_psram(MEM_TYPE_ARRAY,
C_NUM_BANKS_MEM);
constant GLOBAL_PSRAM_FLASH_MEM : integer range 0 to 1
:= psram_or_lflash_sync(C_LINEAR_FLASH_SYNC_BURST,
GLOBAL_PSRAM_MEM);
constant GLOBAL_PARITY_MEM : integer range 0 to 1
:= not_all_parity(MEM_PARITY_ARRAY,
C_NUM_BANKS_MEM);
-- if SYNC memories are configured, then below parameter will be = 1
constant C_SYNCH_MEM_0 : integer :=sync_get_val(C_MEM0_TYPE, C_LINEAR_FLASH_SYNC_BURST);
constant C_SYNCH_MEM_1 : integer :=sync_get_val(C_MEM1_TYPE, C_LINEAR_FLASH_SYNC_BURST);
constant C_SYNCH_MEM_2 : integer :=sync_get_val(C_MEM2_TYPE, C_LINEAR_FLASH_SYNC_BURST);
constant C_SYNCH_MEM_3 : integer :=sync_get_val(C_MEM3_TYPE, C_LINEAR_FLASH_SYNC_BURST);
-- if Page Mode or PSRAM memories are configured,then below parameter will be= 1
constant C_PAGEMODE_FLASH_0 : integer :=page_get_val(C_MEM0_TYPE);
constant C_PAGEMODE_FLASH_1 : integer :=page_get_val(C_MEM1_TYPE);
constant C_PAGEMODE_FLASH_2 : integer :=page_get_val(C_MEM2_TYPE);
constant C_PAGEMODE_FLASH_3 : integer :=page_get_val(C_MEM3_TYPE);
--signal Mem_CRE_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
signal bus2ip_ce_lite_cmb : std_logic_vector(7 downto 0);
signal sync_mode : std_logic_vector(C_NUM_BANKS_MEM-1 downto 0):= (others => '0');
signal Cre_reg_en : std_logic_vector(C_NUM_BANKS_MEM-1 downto 0):= (others => '0');-- := '0';
signal Cre_reg_en_reduced : std_logic:= '0';
signal CTRL_REG : std_logic_vector((C_S_AXI_REG_DATA_WIDTH-1)
downto 0);
signal Linear_flash_brst_rd_flag : std_logic := '0';
signal Linear_flash_rd_data_ack: std_logic := '0';
signal mem_a_io : std_logic_vector(31 downto 0);
signal mem_wait_io : std_logic_vector(C_NUM_BANKS_MEM -1 downto 0);
signal Mem_WAIT_reg : std_logic := '0';
signal Mem_WAIT_reg_d1,
Mem_WAIT_reg_d2,
Mem_WAIT_reg_one_hot : std_logic := '0';
signal CTRL_REG_DATA: std_logic_vector(15 downto 0);
signal CTRL_REG_ADDR: std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0) := (others => '0');
signal sync_burst_data_ack : std_logic;
signal sync_data_select : std_logic;
constant FREQ_FACT_INT : integer range 0 to 15
:= (C_LFLASH_PERIOD_PS/C_AXI_CLK_PERIOD_PS);
constant FLASH_FREQ_FACTOR : std_logic_vector(3 downto 0)
:= conv_std_logic_vector(FREQ_FACT_INT - 1, 4);
signal test_rd : std_logic;
signal ADDR_PROGRAM : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal ADDR_PROGRAM_D : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal ADDR_SYNCH_BURST_RD : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal ADDR_SYNCH_BURST_RD_D : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal Addr_select : std_logic := '0';
signal S_AXI_MEM_BVALID1 : std_logic;
signal S_AXI_MEM_WREADY1 : std_logic;
signal S_AXI_MEM_ARREADY1 : std_logic;
signal temp_strb : std_logic_vector(((C_S_AXI_MEM_DATA_WIDTH/8)-1) downto 0) := (others => '1');
signal temp_prog_cmd_data : std_logic_vector(15 downto 0) := X"0040";
signal Mem_WAIT_temp0 : std_logic := '0';
signal Mem_WAIT_temp1 : std_logic := '0';
signal Mem_WAIT_temp2 : std_logic := '0';
signal Mem_WAIT_temp3 : std_logic := '0';
signal Mem_WAIT_cmb_delay: std_logic := '0';
signal Parity_err_i : std_logic;
signal s_axi_reg_bvalid_i : std_logic;
signal s_axi_reg_awready_i : std_logic;
signal pr_idle, axi_sm_ns_IDLE : std_logic; -- 11-12-2012
signal mem_cre_int : std_logic;
signal mem_a_int : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
attribute IOB : string;
attribute IOB of Mem_WAIT_io : signal is "true";
attribute IOB of Mem_cre_int : signal is "true";
attribute IOB of Mem_a_int : signal is "true";
-----
begin -- architecture IMP
-----
s_axi_mem_bvalid <= S_AXI_MEM_BVALID1;
s_axi_mem_wready <= S_AXI_MEM_WREADY1;
s_axi_mem_arready <= S_AXI_MEM_ARREADY1;
-- EMC memory read/write access times assignments
-- CMD_ADDR_LOGIC_LFLASH : if (C_LINEAR_FLASH_SYNC_BURST = 1) generate
-- Mem_A <= mem_a_i when Cre_reg_en = '0' else CTRL_REG_ADDR ;
-- end generate CMD_ADDR_LOGIC_LFLASH;
-- ADDR_LOGIC_NO_LFLASH : if (C_LINEAR_FLASH_SYNC_BURST = 0) generate
mem_a_io <= ADDR_PROGRAM when Addr_select = '1' else
ADDR_SYNCH_BURST_RD when Linear_flash_brst_rd_flag = '1' else mem_a_i ;
-- end generate ADDR_LOGIC_NO_LFLASH;
mem_wen <= mem_wen_i ;
mem_adv_ldn <= mem_adv_ldn_i;
mem_cken <= mem_cken_i ;
err_parity_bits <= parity_error_MEM & Parity_err_i;
--axi_arsize <= S_AXI_MEM_ARSIZE when (S_AXI_MEM_ARVALID = '1' and S_AXI_MEM_ARREADY1 = '1') else axi_arsize;
mem_a <= mem_a_int;
mem_cre <= mem_cre_int;
INPUT_MEM_A_REG_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
mem_a_int <= mem_a_io;
end if;
end process INPUT_MEM_A_REG_PROCESS;
INPUT_MEM_WAIT_REG_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_io(C_NUM_BANKS_MEM -1 downto 0) <= Mem_WAIT(C_NUM_BANKS_MEM -1 downto 0);
end if;
end process INPUT_MEM_WAIT_REG_PROCESS;
process (s_axi_aclk) begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if S_AXI_MEM_ARVALID = '1' and S_AXI_MEM_ARREADY1 = '1' then
axi_arsize <= S_AXI_MEM_ARSIZE;
else
axi_arsize <= axi_arsize;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- AXI EMC is little endian and EMC COMMON is still big endian, to make
-- this interface work normally, we need to swap the Write and read data
-- bytes comming from and going to external memory interface
---------------------------------------------------------------------------
ENDIAN_CEN_BANKS_1 : if (C_NUM_BANKS_MEM = 1) generate
mem_cen(0) <= mem_cen_i(0);
mem_ce(0) <= mem_ce_i(0);
end generate ENDIAN_CEN_BANKS_1;
ENDIAN_CEN_BANKS_2 : if (C_NUM_BANKS_MEM = 2) generate
mem_cen(0) <= mem_cen_i(0);
mem_cen(1) <= mem_cen_i(1);
mem_ce(0) <= mem_ce_i(0);
mem_ce(1) <= mem_ce_i(1);
end generate ENDIAN_CEN_BANKS_2;
ENDIAN_CEN_BANKS_3 : if (C_NUM_BANKS_MEM = 3) generate
mem_cen(0) <= mem_cen_i(0);
mem_cen(1) <= mem_cen_i(1);
mem_cen(2) <= mem_cen_i(2);
mem_ce(0) <= mem_ce_i(0);
mem_ce(1) <= mem_ce_i(1);
mem_ce(2) <= mem_ce_i(2);
end generate ENDIAN_CEN_BANKS_3;
ENDIAN_CEN_BANKS_4 : if (C_NUM_BANKS_MEM = 4) generate
mem_cen(0) <= mem_cen_i(0);
mem_cen(1) <= mem_cen_i(1);
mem_cen(2) <= mem_cen_i(2);
mem_cen(3) <= mem_cen_i(3);
mem_ce(0) <= mem_ce_i(0);
mem_ce(1) <= mem_ce_i(1);
mem_ce(2) <= mem_ce_i(2);
mem_ce(3) <= mem_ce_i(3);
end generate ENDIAN_CEN_BANKS_4;
-- assign OutPut Enable signals (Read Enable Signals)
ENDIAN_OEN_BANKS_1 : if (C_NUM_BANKS_MEM = 1) generate
mem_oen(0) <= mem_oen_i(0);
end generate ENDIAN_OEN_BANKS_1;
ENDIAN_OEN_BANKS_2 : if (C_NUM_BANKS_MEM = 2) generate
mem_oen(0) <= mem_oen_i(0);
mem_oen(1) <= mem_oen_i(1);
end generate ENDIAN_OEN_BANKS_2;
ENDIAN_OEN_BANKS_3 : if (C_NUM_BANKS_MEM = 3) generate
mem_oen(0) <= mem_oen_i(0);
mem_oen(1) <= mem_oen_i(1);
mem_oen(2) <= mem_oen_i(2);
end generate ENDIAN_OEN_BANKS_3;
ENDIAN_OEN_BANKS_4 : if (C_NUM_BANKS_MEM = 4) generate
mem_oen(0) <= mem_oen_i(0);
mem_oen(1) <= mem_oen_i(1);
mem_oen(2) <= mem_oen_i(2);
mem_oen(3) <= mem_oen_i(3);
end generate ENDIAN_OEN_BANKS_4;
-- data byte swapping for 8 bit memory
ENDIAN_MEM_CONVERSION_8 : if (C_MAX_MEM_WIDTH = 8) generate
-- output from memory core
mem_dq_o(7 downto 0) <= mem_dq_o_i (0 to 7);
mem_dq_t(7 downto 0) <= mem_dq_t_i (0 to 7);
-- input to memory core
mem_dq_i_i (0 to 7) <= Mem_DQ_I (7 downto 0);
mem_qwen <= mem_qwen_i;
mem_ben <= mem_ben_i;
-- o/p from memory
mem_dq_parity_o <= mem_dq_parity_o_i;
mem_dq_parity_t <= mem_dq_parity_t_i;
-- i/p to memory
mem_dq_parity_i_i <= MEM_DQ_PARITY_I;
end generate ENDIAN_MEM_CONVERSION_8;
-- data byte swapping for 16 bit memory
-- ENDIAN_MEM_CONVERSION_16: byte -by -byte swapping for 16 bit memory
---------------------------
ENDIAN_MEM_CONVERSION_16 : if (C_MAX_MEM_WIDTH = 16) generate
-- o/p to memory
mem_dq_o(7 downto 0) <= mem_dq_o_i (0 to 7);
mem_dq_o(15 downto 8) <= mem_dq_o_i (8 to 15);
mem_dq_t(7 downto 0) <= mem_dq_t_i (0 to 7);
mem_dq_t(15 downto 8) <= mem_dq_t_i (8 to 15);
-- i/p from memory
mem_dq_i_i (0 to 7) <= Mem_DQ_I (7 downto 0);
mem_dq_i_i (8 to 15) <= Mem_DQ_I (15 downto 8);
-- qualified write enabls
mem_qwen(0) <= mem_qwen_i(0);
mem_qwen(1) <= mem_qwen_i(1);
-- byte enabls
mem_ben(0) <= mem_ben_i(0);
mem_ben(1) <= mem_ben_i(1);
-- parity bits to memory
mem_dq_parity_o(0) <= mem_dq_parity_o_i(0);
mem_dq_parity_o(1) <= mem_dq_parity_o_i(1);
mem_dq_parity_t(0) <= mem_dq_parity_t_i(0);
mem_dq_parity_t(1) <= mem_dq_parity_t_i(1);
-- parity bits from memory
mem_dq_parity_i_i(0) <= MEM_DQ_PARITY_I(0);
mem_dq_parity_i_i(1) <= MEM_DQ_PARITY_I(1);
end generate ENDIAN_MEM_CONVERSION_16;
-- data byte swapping for 32 bit memory
-- ENDIAN_MEM_CONVERSION_32: byte -by -byte swapping for 32 bit memory
ENDIAN_MEM_CONVERSION_32 : if (C_MAX_MEM_WIDTH = 32) generate
-- o/p to memory
mem_dq_o(7 downto 0) <= mem_dq_o_i (0 to 7);
mem_dq_o(15 downto 8) <= mem_dq_o_i (8 to 15);
mem_dq_o(23 downto 16) <= mem_dq_o_i (16 to 23);
mem_dq_o(31 downto 24) <= mem_dq_o_i (24 to 31);
mem_dq_t(7 downto 0) <= mem_dq_t_i (0 to 7);
mem_dq_t(15 downto 8) <= mem_dq_t_i (8 to 15);
mem_dq_t(23 downto 16) <= mem_dq_t_i (16 to 23);
mem_dq_t(31 downto 24) <= mem_dq_t_i (24 to 31);
-- i/p from memory
mem_dq_i_i (0 to 7) <= Mem_DQ_I (7 downto 0);
mem_dq_i_i (8 to 15) <= Mem_DQ_I (15 downto 8);
mem_dq_i_i (16 to 23) <= Mem_DQ_I (23 downto 16);
mem_dq_i_i (24 to 31) <= Mem_DQ_I (31 downto 24);
-- qualified write enabls
mem_qwen(0) <= mem_qwen_i(0);
mem_qwen(1) <= mem_qwen_i(1);
mem_qwen(2) <= mem_qwen_i(2);
mem_qwen(3) <= mem_qwen_i(3);
-- byte enabls
mem_ben(0) <= mem_ben_i(0);
mem_ben(1) <= mem_ben_i(1);
mem_ben(2) <= mem_ben_i(2);
mem_ben(3) <= mem_ben_i(3);
-- parity bits to memory
mem_dq_parity_o(0) <= mem_dq_parity_o_i(0);
mem_dq_parity_o(1) <= mem_dq_parity_o_i(1);
mem_dq_parity_o(2) <= mem_dq_parity_o_i(2);
mem_dq_parity_o(3) <= mem_dq_parity_o_i(3);
mem_dq_parity_t(0) <= mem_dq_parity_t_i(0);
mem_dq_parity_t(1) <= mem_dq_parity_t_i(1);
mem_dq_parity_t(2) <= mem_dq_parity_t_i(2);
mem_dq_parity_t(3) <= mem_dq_parity_t_i(3);
-- parity bits from memory
mem_dq_parity_i_i(0) <= mem_dq_parity_i(0);
mem_dq_parity_i_i(1) <= mem_dq_parity_i(1);
mem_dq_parity_i_i(2) <= mem_dq_parity_i(2);
mem_dq_parity_i_i(3) <= mem_dq_parity_i(3);
end generate ENDIAN_MEM_CONVERSION_32;
-- data byte swapping for 64 bit memory
-- ENDIAN_MEM_CONVERSION_64: byte -by -byte swapping for 64 bit memory
ENDIAN_MEM_CONVERSION_64 : if (C_MAX_MEM_WIDTH = 64) generate
-- o/p to memory
mem_dq_o(7 downto 0) <= mem_dq_o_i (0 to 7);
mem_dq_o(15 downto 8) <= mem_dq_o_i (8 to 15);
mem_dq_o(23 downto 16) <= mem_dq_o_i (16 to 23);
mem_dq_o(31 downto 24) <= mem_dq_o_i (24 to 31);
mem_dq_o(39 downto 32) <= mem_dq_o_i (32 to 39);
mem_dq_o(47 downto 40) <= mem_dq_o_i (40 to 47);
mem_dq_o(55 downto 48) <= mem_dq_o_i (48 to 55);
mem_dq_o(63 downto 56) <= mem_dq_o_i (56 to 63);
mem_dq_t(7 downto 0) <= mem_dq_t_i (0 to 7);
mem_dq_t(15 downto 8) <= mem_dq_t_i (8 to 15);
mem_dq_t(23 downto 16) <= mem_dq_t_i (16 to 23);
mem_dq_t(31 downto 24) <= mem_dq_t_i (24 to 31);
mem_dq_t(39 downto 32) <= mem_dq_t_i (32 to 39);
mem_dq_t(47 downto 40) <= mem_dq_t_i (40 to 47);
mem_dq_t(55 downto 48) <= mem_dq_t_i (48 to 55);
mem_dq_t(63 downto 56) <= mem_dq_t_i (56 to 63);
-- o/p from memory
mem_dq_i_i (0 to 7) <= mem_dq_i (7 downto 0);
mem_dq_i_i (8 to 15) <= mem_dq_i (15 downto 8);
mem_dq_i_i (16 to 23) <= mem_dq_i (23 downto 16);
mem_dq_i_i (24 to 31) <= mem_dq_i (31 downto 24);
mem_dq_i_i (32 to 39) <= mem_dq_i (39 downto 32);
mem_dq_i_i (40 to 47) <= mem_dq_i (47 downto 40);
mem_dq_i_i (48 to 55) <= mem_dq_i (55 downto 48);
mem_dq_i_i (56 to 63) <= mem_dq_i (63 downto 56);
-- qualified write enabls
mem_qwen(0) <= mem_qwen_i(0);
mem_qwen(1) <= mem_qwen_i(1);
mem_qwen(2) <= mem_qwen_i(2);
mem_qwen(3) <= mem_qwen_i(3);
mem_qwen(4) <= mem_qwen_i(4);
mem_qwen(5) <= mem_qwen_i(5);
mem_qwen(6) <= mem_qwen_i(6);
mem_qwen(7) <= mem_qwen_i(7);
-- byte enabls
mem_ben(0) <= mem_ben_i(0);
mem_ben(1) <= mem_ben_i(1);
mem_ben(2) <= mem_ben_i(2);
mem_ben(3) <= mem_ben_i(3);
mem_ben(4) <= mem_ben_i(4);
mem_ben(5) <= mem_ben_i(5);
mem_ben(6) <= mem_ben_i(6);
mem_ben(7) <= mem_ben_i(7);
-- parity bits to memory
mem_dq_parity_o(0) <= mem_dq_parity_o_i(0);
mem_dq_parity_o(1) <= mem_dq_parity_o_i(1);
mem_dq_parity_o(2) <= mem_dq_parity_o_i(2);
mem_dq_parity_o(3) <= mem_dq_parity_o_i(3);
mem_dq_parity_o(4) <= mem_dq_parity_o_i(4);
mem_dq_parity_o(5) <= mem_dq_parity_o_i(5);
mem_dq_parity_o(6) <= mem_dq_parity_o_i(6);
mem_dq_parity_o(7) <= mem_dq_parity_o_i(7);
mem_dq_parity_t(0) <= mem_dq_parity_t_i(0);
mem_dq_parity_t(1) <= mem_dq_parity_t_i(1);
mem_dq_parity_t(2) <= mem_dq_parity_t_i(2);
mem_dq_parity_t(3) <= mem_dq_parity_t_i(3);
mem_dq_parity_t(4) <= mem_dq_parity_t_i(4);
mem_dq_parity_t(5) <= mem_dq_parity_t_i(5);
mem_dq_parity_t(6) <= mem_dq_parity_t_i(6);
mem_dq_parity_t(7) <= mem_dq_parity_t_i(7);
-- parity bits from memory
mem_dq_parity_i_i(0) <= mem_dq_parity_i(0);
mem_dq_parity_i_i(1) <= mem_dq_parity_i(1);
mem_dq_parity_i_i(2) <= mem_dq_parity_i(2);
mem_dq_parity_i_i(3) <= mem_dq_parity_i(3);
mem_dq_parity_i_i(4) <= mem_dq_parity_i(4);
mem_dq_parity_i_i(5) <= mem_dq_parity_i(5);
mem_dq_parity_i_i(6) <= mem_dq_parity_i(6);
mem_dq_parity_i_i(7) <= mem_dq_parity_i(7);
end generate ENDIAN_MEM_CONVERSION_64;
-------------------------------------------------------------------------------
-- NO_REG_EN_GEN: the below instantion is to make the output signals for
-- register interface driving '0'.
--------------
NO_REG_EN_GEN : if (C_S_AXI_EN_REG = 0) generate
-------------
begin
-------------------------------------
s_axi_reg_awready <= '0';
s_axi_reg_wready <= '0';
s_axi_reg_bresp <= (others => '0');
s_axi_reg_bvalid <= '0';
s_axi_reg_arready <= '0';
s_axi_reg_rdata <= (others => '0');
s_axi_reg_rresp <= (others => '0');
s_axi_reg_rvalid <= '0';
-- PSRAM_CONFIG_REG_DIS: if (GLOBAL_PSRAM_FLASH_MEM = 0) generate
psram_page_mode <= '0';-- Default value is psram in async mode
-- end generate PSRAM_CONFIG_REG_DIS;
-------------------------------------
end generate NO_REG_EN_GEN;
-------------------------------------------------------------------------------
-- EMC REGISTER MODULE Instantiations
-------------------------------------------------------------------------------
-- REG_EN_GEN: Include the AXI Lite IPIF and register module
--------------
REG_EN_GEN : if (C_S_AXI_EN_REG = 1) generate
-------------
-- IPIC Used Sgnals
constant RST_ACTIVE : std_logic := '0';
type MEM_PARITY_REG_ARRAY_TYPE is array(3 downto 0) of
std_logic_vector((C_S_AXI_REG_DATA_WIDTH -1) downto 0);
type MEM_PSRAM_REG_ARRAY_TYPE is array(3 downto 0) of
std_logic_vector((C_S_AXI_REG_DATA_WIDTH -1) downto 0);
signal PEAR_REG : MEM_PARITY_REG_ARRAY_TYPE;-- 4 parity regs of each 32 bit
signal PCR_REG : MEM_PSRAM_REG_ARRAY_TYPE ; -- 4 psram regs of each 32 bit
signal axi_lite_ip2bus_data_i : std_logic_vector((C_S_AXI_REG_DATA_WIDTH-1)
downto 0);
signal axi_lite_ip2bus_data1 : std_logic_vector((C_S_AXI_REG_DATA_WIDTH-1)
downto 0);
signal axi_lite_ip2bus_data2 : std_logic_vector((C_S_AXI_REG_DATA_WIDTH-1)
downto 0);
signal bus2ip_addr_lite_reg : std_logic_vector(4 downto 2);--((3+GLOBAL_PSRAM_FLASH_MEM)
-- downto 2);
signal arready_i : std_logic;
signal awready_i : std_logic;
signal rvalid : std_logic;
signal axi_lite_ip2bus_wrack_i : std_logic;
signal axi_lite_ip2bus_rdack_i : std_logic;
signal axi_lite_ip2bus_rdack1 : std_logic;
signal axi_lite_ip2bus_rdack2 : std_logic;
signal axi_lite_ip2bus_wrack1 : std_logic;
signal axi_lite_ip2bus_wrack2 : std_logic;
signal read_reg_req : std_logic;
signal write_reg_req : std_logic;
signal bus2ip_rdce_lite_cmb : std_logic_vector(7 downto 0);-- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM)) downto 0);
signal bus2ip_wrce_lite_cmb : std_logic_vector(7 downto 0);-- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM)) downto 0);
signal s_axi_reg_rresp_reg: std_logic_vector(1 downto 0);
signal s_axi_reg_bresp_reg: std_logic_vector(1 downto 0);
signal s_axi_reg_bvalid_i : std_logic;
------------------------
-----
begin
-------------------------------------------------------------------------------
-- *
-------------------------------------------------------------------------------
PSRAM_FLASH_PARITY_CE_LOCAL_REG_GEN : if (GLOBAL_PSRAM_FLASH_MEM = 1)generate
-------------------------------
--signal bus2ip_ce_lite_cmb : std_logic_vector(7 downto 0);
-----
begin-- *
-----
--* to generate the WRCE and RDCE for register access.
PSRAM_PARITY_NUM_BANKS_4_GEN: if (C_NUM_BANKS_MEM=4) generate
begin
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)
)is
--------
variable bus2ip_addr_reg_4_2 : std_logic_vector(2 downto 0);
--------
begin
--
bus2ip_addr_reg_4_2 := bus2ip_addr_lite_reg;
--
case bus2ip_addr_reg_4_2 is
when "000" => bus2ip_ce_lite_cmb <= "00000001";
when "001" => bus2ip_ce_lite_cmb <= "00000010";
when "010" => bus2ip_ce_lite_cmb <= "00000100";
when "011" => bus2ip_ce_lite_cmb <= "00001000";
when "100" => bus2ip_ce_lite_cmb <= "00010000";
when "101" => bus2ip_ce_lite_cmb <= "00100000";
when "110" => bus2ip_ce_lite_cmb <= "01000000";
when "111" => bus2ip_ce_lite_cmb <= "10000000";
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
----------------------------------------
end generate PSRAM_PARITY_NUM_BANKS_4_GEN;
------------------------------------------
PSRAM_PARITY_NUM_BANKS_3_GEN: if (C_NUM_BANKS_MEM=3) generate
begin
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)
)is
--------
variable bus2ip_addr_reg_4_2 : std_logic_vector(2 downto 0);
--------
begin
--
bus2ip_addr_reg_4_2 := bus2ip_addr_lite_reg;
--
case bus2ip_addr_reg_4_2 is
-- when "000" => bus2ip_ce_lite_cmb <= "00000001";
-- when "001" => bus2ip_ce_lite_cmb <= "00000010";
-- when "010" => bus2ip_ce_lite_cmb <= "00000100";
-- when "011" => bus2ip_ce_lite_cmb <= "00001000"; -- this will complete the transaction without any updates
-- -- psram configuration registers
-- when "100" => bus2ip_ce_lite_cmb <= "00010000";
-- when "101" => bus2ip_ce_lite_cmb <= "00100000";
-- when "110" => bus2ip_ce_lite_cmb <= "01000000";
-- -- coverage off
-- when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- -- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- bank 2 present if SRAM is chosen
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- REGISTER HOLE - provide only ack
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- bank 2 present if PSRAM/Flash is chosen
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- REGISTER HOLE - provide only ack
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
-- end if;
-- end if;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
----------------------------------------
end generate PSRAM_PARITY_NUM_BANKS_3_GEN;
------------------------------------------
PSRAM_PARITY_NUM_BANKS_2_GEN: if (C_NUM_BANKS_MEM=2) generate
begin
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)
)is
--------
variable bus2ip_addr_reg_4_2 : std_logic_vector(2 downto 0);
--------
begin
--
bus2ip_addr_reg_4_2 := bus2ip_addr_lite_reg;
--
case bus2ip_addr_reg_4_2 is
--when "000" => bus2ip_ce_lite_cmb <= "00000001";
--when "001" => bus2ip_ce_lite_cmb <= "00000010";
--when "010" => bus2ip_ce_lite_cmb <= "00000100"; -- this will complete the transaction without any updates
--when "011" => bus2ip_ce_lite_cmb <= "00001000"; -- this will complete the transaction without any updates
---- psram configuration registers
--when "100" => bus2ip_ce_lite_cmb <= "00010000";
--when "101" => bus2ip_ce_lite_cmb <= "00100000";
--when "110" => bus2ip_ce_lite_cmb <= "01000000"; -- this will complete the transaction without any updates
--when "111" => bus2ip_ce_lite_cmb <= "10000000"; -- this will complete the transaction without any updates
---- coverage off
--when others => bus2ip_ce_lite_cmb <= (others=> '0');
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- REGISTER HOLE - provide only ack
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- REGISTER HOLE - provide only ack
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- REGISTER HOLE - provide only ack
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- REGISTER HOLE - provide only ack
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
----------------------------------------
end generate PSRAM_PARITY_NUM_BANKS_2_GEN;
PSRAM_PARITY_NUM_BANKS_1_GEN: if (C_NUM_BANKS_MEM=1) generate
begin
BUS2IP_CE_GEN_P: process--(s_axi_aclk) is
(
bus2ip_addr_lite_reg(4 downto 2)
)is
--------
variable bus2ip_addr_reg_4_2 : std_logic_vector(2 downto 0);
--------
begin
--
bus2ip_addr_reg_4_2 := bus2ip_addr_lite_reg;
--
case bus2ip_addr_reg_4_2 is
--when "000" => bus2ip_ce_lite_cmb <= "00000001";
--when "001" => bus2ip_ce_lite_cmb <= "00000010";-- this will complete the transaction without any updates
--when "010" => bus2ip_ce_lite_cmb <= "00000100";-- this will complete the transaction without any updates
--when "011" => bus2ip_ce_lite_cmb <= "00001000"; -- this will complete the transaction without any updates
-- psram configuration registers
--when "100" => bus2ip_ce_lite_cmb <= "00010000";
--when "101" => bus2ip_ce_lite_cmb <= "00100000"; -- this will complete the transaction without any updates
--when "110" => bus2ip_ce_lite_cmb <= "01000000"; -- this will complete the transaction without any updates
--when "111" => bus2ip_ce_lite_cmb <= "10000000"; -- this will complete the transaction without any updates
-- coverage off
--when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- REGISTER HOLE - provide only ack
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- REGISTER HOLE - provide only ack
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- REGISTER HOLE - provide only ack
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- REGISTER HOLE - provide only ack
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- REGISTER HOLE - provide only ack
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- REGISTER HOLE - provide only ack
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
----------------------------------------
end generate PSRAM_PARITY_NUM_BANKS_1_GEN;
end generate PSRAM_FLASH_PARITY_CE_LOCAL_REG_GEN;
-------------------------------------------------------------------------------
NO_LFLASH_PSRAM_CE_LOCAL_REG_GEN: if (GLOBAL_PSRAM_FLASH_MEM = 0)generate
-----
begin-- *
-----
--* to generate the WRCE and RDCE for register access.
NUM_BANKS_4_GEN: if (C_NUM_BANKS_MEM=4) generate
--signal bus2ip_ce_lite_cmb : std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);--9/14/2013
-----
begin
-----
BUS2IP_CE_GEN_P: process
(
bus2ip_addr_lite_reg(4 downto 2) -- (3 downto 2)
) is
--------
--variable bus2ip_addr_reg_3_2 : std_logic_vector(1 downto 0);
--------
begin
--
case bus2ip_addr_lite_reg(4 downto 2) is -- (3 downto 2) is
--when "00" => bus2ip_ce_lite_cmb <= "0001";
--when "01" => bus2ip_ce_lite_cmb <= "0010";
--when "10" => bus2ip_ce_lite_cmb <= "0100";
--when "11" => bus2ip_ce_lite_cmb <= "1000";
---- coverage off
--when others => bus2ip_ce_lite_cmb <= "0001";--(others => '0');
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen, else hole
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen, else hole
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- bank 2 present if SRAM is chosen, else hole
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- bank 3 present if SRAM is chosen, else hole
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen, else hole
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen, else hole
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- bank 2 present if PSRAM/Flash is chosen, else hole
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- bank 3 present if PSRAM/Flash is chosen, else hole
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and
bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate --C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
--------------------------------------
end generate NUM_BANKS_4_GEN;
------------------------------------------
NUM_BANKS_3_GEN: if (C_NUM_BANKS_MEM=3) generate
--signal bus2ip_ce_lite_cmb : std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
-----
begin
-----
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)-- (3 downto 2)
) is
--------
begin
--
case bus2ip_addr_lite_reg(4 downto 2) is
--when "00" => bus2ip_ce_lite_cmb <= "001";
--when "01" => bus2ip_ce_lite_cmb <= "010";
--when "10" => bus2ip_ce_lite_cmb <= "100";
--when "11" => bus2ip_ce_lite_cmb <= "001"; -- this will complete the transaction without any updates
---- coverage off
--when others => bus2ip_ce_lite_cmb <= "001";--(others=>'0');
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen, else hole
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen, else hole
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- bank 2 present if SRAM is chosen, else hole
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- hole, provide ack in any case
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen, else hole
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen, else hole
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- bank 2 present if PSRAM/Flash is chosen, else hole
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- hole, provide ack in any case
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and
bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
--------------------------------------
end generate NUM_BANKS_3_GEN;
------------------------------------------
NUM_BANKS_2_GEN: if (C_NUM_BANKS_MEM=2) generate
--signal bus2ip_ce_lite_cmb : std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
-----
begin
-----
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)-- (3 downto 2)
) is
--------
begin
--
case bus2ip_addr_lite_reg(4 downto 2) is -- (3 downto 2) is
--when "00" => bus2ip_ce_lite_cmb <= "01";
--when "01" => bus2ip_ce_lite_cmb <= "10";
--when "10" => bus2ip_ce_lite_cmb <= "01"; -- this will complete the transaction without any updates
--when "11" => bus2ip_ce_lite_cmb <= "01"; -- this will complete the transaction without any updates
---- coverage off
--when others => bus2ip_ce_lite_cmb <= "01";-- (others=>'0');
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen, else hole
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen, else hole
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- hole, provide ack in any case
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- hole, provide ack in any case
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen, else hole
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen, else hole
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- hole, provide ack in any case
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- hole, provide ack in any case
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and
bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
--------------------------------------
end generate NUM_BANKS_2_GEN;
------------------------------------------
NUM_BANKS_1_GEN: if (C_NUM_BANKS_MEM=1) generate
--signal bus2ip_ce_lite_cmb : std_logic;
-----
begin
-----
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2) -- (3 downto 2)
) is
--------
begin
--
case bus2ip_addr_lite_reg(4 downto 2) is -- (3 downto 2) is
--when "00" => bus2ip_ce_lite_cmb <= '1';
--when "01" => bus2ip_ce_lite_cmb <= '1'; -- this will complete the transaction without any updates
--when "10" => bus2ip_ce_lite_cmb <= '1'; -- this will complete the transaction without any updates
--when "11" => bus2ip_ce_lite_cmb <= '1'; -- this will complete the transaction without any updates
---- coverage off
--when others => bus2ip_ce_lite_cmb <= '1';-- '0';
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen, else hole
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- hole, provide ack in any case
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- hole, provide ack in any case
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- hole, provide ack in any case
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen, else hole
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- hole, provide ack in any case
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- hole, provide ack in any case
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- hole, provide ack in any case
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and
bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
--------------------------------------
end generate NUM_BANKS_1_GEN;
--------------------------------------
end generate NO_LFLASH_PSRAM_CE_LOCAL_REG_GEN;
--*
s_axi_reg_awready <= axi_lite_ip2bus_wrack_i; -- awready_i;
s_axi_reg_wready <= axi_lite_ip2bus_wrack_i; -- write_reg_req;
s_axi_reg_bresp <= s_axi_reg_bresp_reg;
s_axi_reg_arready <= arready_i;
s_axi_reg_rvalid <= rvalid;
s_axi_reg_rresp <= s_axi_reg_rresp_reg;
-- AWREADY is enabled only if valid write request and no read request
awready_i <= (not write_reg_req) and
not ( s_axi_reg_arvalid or read_reg_req or rvalid ) and
s_axi_aresetn;
-- ARREADY is enabled only if valid read request and no current write request
arready_i <= not(rvalid or read_reg_req) and
not (write_reg_req)
and s_axi_aresetn;
-- WRITE_AWREADY_P: process (s_axi_aclk) is
-- begin
-- if (s_axi_aclk'event and s_axi_aclk = '1') then
-- if (s_axi_aresetn=RST_ACTIVE) then
-- s_axi_reg_awready_i <= '0';
-- --elsif (s_axi_reg_awvalid = '0') and (axi_lite_ip2bus_wrack_i = '1') then
-- -- s_axi_reg_awready_i <= '1';
-- elsif (s_axi_reg_awvalid = '1') and (s_axi_reg_awready_i = '1') then
-- s_axi_reg_awready_i <= '0';
-- else
-- s_axi_reg_awready_i <= axi_lite_ip2bus_wrack_i;
-- end if;
-- end if;
-- end process WRITE_AWREADY_P;
-- ---------------------------------------------------------------------------------
-- s_axi_reg_awready <= s_axi_reg_awready_i;
-------------------------------------------------------------------------------
-- Process READ_REQUEST_P to generate read request
-------------------------------------------------------------------------------
READ_REQUEST_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
read_reg_req <= '0';
elsif (s_axi_reg_arvalid = '1' and arready_i = '1') then
read_reg_req <= '1';
elsif (axi_lite_ip2bus_rdack_i = '1') then
read_reg_req <= '0';
end if;
end if;
end process READ_REQUEST_P;
-------------------------------------------------------------------------------
-- Process WRITE_REQUEST_P to generate Write request on the IPIC
-------------------------------------------------------------------------------
WRITE_REQUEST_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
write_reg_req <= '0';
elsif (s_axi_reg_awvalid = '1' and awready_i = '1') then
write_reg_req <= '1';
elsif (axi_lite_ip2bus_wrack_i = '1') then
write_reg_req <= '0';
end if;
end if;
end process WRITE_REQUEST_P;
-------------------------------------------------------------------------------
-- Process ADDR_GEN_P to generate bus2ip_addr for read/write
-------------------------------------------------------------------------------
PSRAM_PARITY_ADDR_REG_GEN : if (GLOBAL_PSRAM_FLASH_MEM = 1) generate
------------------------
-----
begin-- *
-----
ADDR_GEN_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
bus2ip_addr_lite_reg(4 downto 2) <= (others=>'0');
elsif (s_axi_reg_arvalid = '1' and arready_i = '1') then
bus2ip_addr_lite_reg(4 downto 2) <= s_axi_reg_araddr(4 downto 2);
elsif (s_axi_reg_awvalid = '1' and awready_i = '1') then
bus2ip_addr_lite_reg(4 downto 2) <= s_axi_reg_awaddr(4 downto 2);
end if;
end if;
end process ADDR_GEN_P;
end generate PSRAM_PARITY_ADDR_REG_GEN;
---------------------------------------
NO_PSRAM_PARITY_ADDR_REG_GEN : if (GLOBAL_PSRAM_FLASH_MEM = 0) generate
------------------------
-----
begin-- *
-----
ADDR_GEN_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
bus2ip_addr_lite_reg(4 downto 2) <= (others=>'0');
elsif (s_axi_reg_arvalid = '1' and arready_i = '1') then
bus2ip_addr_lite_reg(4 downto 2) <= s_axi_reg_araddr(4 downto 2);
elsif (s_axi_reg_awvalid = '1' and awready_i = '1') then
bus2ip_addr_lite_reg(4 downto 2) <= s_axi_reg_awaddr(4 downto 2);
end if;
end if;
end process ADDR_GEN_P;
end generate NO_PSRAM_PARITY_ADDR_REG_GEN;
---------------------------------------
-- -----------------------------------------------------------------------
-- Process AXI_READ_OUTPUT_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_READ_OUTPUT_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
s_axi_reg_rdata <= (others =>'0');
elsif (axi_lite_ip2bus_rdack_i = '1') then
s_axi_reg_rdata <= axi_lite_ip2bus_data_i;
elsif(rvalid='0')then
s_axi_reg_rdata <= (others =>'0');
end if;
end if;
end process AXI_READ_OUTPUT_P;
-- -----------------------------------------------------------------------
-- Process READ_RVALID_P to generate Read valid
-- -----------------------------------------------------------------------
READ_RVALID_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
s_axi_reg_rresp_reg <= "00";
if (s_axi_aresetn=RST_ACTIVE) then
rvalid <= '0';
elsif (axi_lite_ip2bus_rdack_i = '1') then
rvalid <= '1';
elsif (s_axi_reg_rready='1') then
rvalid <= '0';
end if;
end if;
end process READ_RVALID_P;
-- -----------------------------------------------------------------------
-- Process WRITE_BVALID_P to generate Write valid
-- -----------------------------------------------------------------------
WRITE_BVALID_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
s_axi_reg_bresp_reg <= "00";
if (s_axi_aresetn=RST_ACTIVE) then
s_axi_reg_bvalid_i <= '0';
--elsif (axi_lite_ip2bus_wrack_i = '1') then
-- s_axi_reg_bvalid <= '1';
--elsif (s_axi_reg_bready='1') then
-- s_axi_reg_bvalid <= '0';
--elsif(s_axi_reg_bready='1')then
--else
--s_axi_reg_bvalid <= axi_lite_ip2bus_wrack_i;
elsif ((axi_lite_ip2bus_wrack_i and (not axi_lite_ip2bus_wrack_d1)) = '1') then
s_axi_reg_bvalid_i <= '1';
elsif (s_axi_reg_bready = '0') and (s_axi_reg_bvalid_i = '1') then
s_axi_reg_bvalid_i <= '1';
elsif (s_axi_reg_bready = '1') and (s_axi_reg_bvalid_i = '1') then
s_axi_reg_bvalid_i <= '0';
end if;
end if;
end process WRITE_BVALID_P;
LOCK_BVALID_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
axi_lite_ip2bus_wrack_d1 <= '0';
else -- if (axi_lite_ip2bus_wrack_i = '1') then
axi_lite_ip2bus_wrack_d1 <= axi_lite_ip2bus_wrack_i;
end if;
end if;
end process LOCK_BVALID_P;
---------------------------------------------------------------------------------
s_axi_reg_bvalid <= s_axi_reg_bvalid_i;
-----------------------------------------------------------------------------
axi_lite_ip2bus_data_i <= axi_lite_ip2bus_data1 or
axi_lite_ip2bus_data2;
axi_lite_ip2bus_rdack_i <= axi_lite_ip2bus_rdack1 or
axi_lite_ip2bus_rdack2;
axi_lite_ip2bus_wrack_i <= axi_lite_ip2bus_wrack1 or
axi_lite_ip2bus_wrack2;
-----------------------------------------------------------------------------
-- PEAR_X_RD, Byte Parity Register Read Process
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
NO_PARITY_ENABLED_REG_GEN : if (MEM_PARITY_ARRAY(0) = 0 and -- if all mentioned meories are not having
MEM_PARITY_ARRAY(1) = 0 and -- parity included, then there wont be any
MEM_PARITY_ARRAY(2) = 0 and -- local registers
MEM_PARITY_ARRAY(3) = 0) generate
-----
begin
------
axi_lite_ip2bus_data1 <= (others => '0');
axi_lite_ip2bus_rdack1 <= '0';
axi_lite_ip2bus_wrack1 <= '0';
end generate NO_PARITY_ENABLED_REG_GEN;
---------------------------------------
-- PEAR_X_RD : If any of the memories are having parity enabled then local register may be
-- needed. 1-odd parity, 2-even parity
--------------
PARITY_ENABLED_REG_GEN : if ( MEM_PARITY_ARRAY(0) /= 0 or -- if any of the memories are of
MEM_PARITY_ARRAY(1) /= 0 or -- having parity enables, then there
MEM_PARITY_ARRAY(2) /= 0 or -- is need of local registers
MEM_PARITY_ARRAY(3) /= 0
) generate
-----
begin
-----
-- PARITY_REG_DUMMY_WR_ACK_P : Parity registers are read only registers. write to these registers is not allowed or should come
-- out safely. Below logic generates ACK and write transactions are come out safely.
PARITY_REG_DUMMY_WR_ACK_P :process(s_axi_aclk)is
begin
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
axi_lite_ip2bus_wrack1 <= '0';
else--if(or_reduce(bus2ip_wrce_lite_cmb) = '1') then
axi_lite_ip2bus_wrack1 <= or_reduce(bus2ip_wrce_lite_cmb); -- '1';
end if;
end if;
end process PARITY_REG_DUMMY_WR_ACK_P;
----------------------------------------------------------------------------
------------------------------------------------------
PERR_NUM_MEM_4_GEN: if C_NUM_BANKS_MEM = 4 generate
------------------
begin
-----
FOUR_BANKS_PARITY_REG_RD_P : process (bus2ip_rdce_lite_cmb,
PEAR_REG(0),
PEAR_REG(1),
PEAR_REG(2),
PEAR_REG(3)
) is
variable internal_bus2ip_rdack : std_logic_vector(7 downto 0); -- 9/14/2013
--(((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0);--(3 downto 0);
-----
begin
-----
internal_bus2ip_rdack := bus2ip_rdce_lite_cmb;
-- defaults
axi_lite_ip2bus_data1 <= (others => '0');
axi_lite_ip2bus_rdack1 <= or_reduce(bus2ip_rdce_lite_cmb);
case internal_bus2ip_rdack(7 downto 0) is -- (3 downto 0) is
--when "0001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
--when "0010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
--when "0100" => axi_lite_ip2bus_data1 <= PEAR_REG(2);
--when "1000" => axi_lite_ip2bus_data1 <= PEAR_REG(3);
when "00000001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
when "00000010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
when "00000100" => axi_lite_ip2bus_data1 <= PEAR_REG(2);
when "00001000" => axi_lite_ip2bus_data1 <= PEAR_REG(3);
-- hole returns data 0
when "00010000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00100000" => axi_lite_ip2bus_data1 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data1 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data1 <= (others => '0');
-- coverage off
when others => axi_lite_ip2bus_data1 <= (others=> '0');
-- coverage on
end case;
end process FOUR_BANKS_PARITY_REG_RD_P;
----------------------------------
PARITY_ERR_REG_STORE_P: process (s_axi_aclk) is
-----------------------
--variable err_parity_bits : std_logic_vector(2 downto 0);
-----
begin
-----
--err_parity_bits := parity_error_MEM & Parity_err_i;
--err_parity_bits := ip2bus_errack & parity_error_MEM;
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PEAR_REG (i) <= (others => '0');
end loop;
else
if (ip2bus_errack = '1') then
case err_parity_bits is -- (parity_error_MEM & Parity_err_i) is
when "001" => PEAR_REG(0) <= parity_error_adrss;
when "011" => PEAR_REG(1) <= parity_error_adrss;
when "101" => PEAR_REG(2) <= parity_error_adrss;
when "111" => PEAR_REG(3) <= parity_error_adrss;
-- coverage off
when others => NULL;
-- coverage on
end case;
else
PEAR_REG(0) <= PEAR_REG(0);
PEAR_REG(1) <= PEAR_REG(1);
PEAR_REG(2) <= PEAR_REG(2);
PEAR_REG(3) <= PEAR_REG(3);
end if;
end if;
end if;
end process PARITY_ERR_REG_STORE_P;
end generate PERR_NUM_MEM_4_GEN;
------------------------------------------------------
------------------------------------------------------
PERR_NUM_MEM_3_GEN: if C_NUM_BANKS_MEM = 3 generate
------------------
begin
-----
THREE_BANKS_PARITY_REG_RD_P : process (bus2ip_rdce_lite_cmb,
PEAR_REG(0),
PEAR_REG(1),
PEAR_REG(2)
) is
variable internal_bus2ip_rdack : std_logic_vector(7 downto 0);--9/14/2013
--(((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0);--(3 downto 0);
-----
begin
-----
internal_bus2ip_rdack := bus2ip_rdce_lite_cmb;
-- defaults
axi_lite_ip2bus_rdack1 <= or_reduce(bus2ip_rdce_lite_cmb);
-- axi_lite_ip2bus_data1 <= (others => '0');
case internal_bus2ip_rdack(7 downto 0) is -- (2 downto 0) is
--when "001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
--when "010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
--when "100" => axi_lite_ip2bus_data1 <= PEAR_REG(2);
---- coverage off
--when others => null;
---- coverage on
when "00000001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
when "00000010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
when "00000100" => axi_lite_ip2bus_data1 <= PEAR_REG(2);
-- hole returns data 0
when "00010000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00100000" => axi_lite_ip2bus_data1 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data1 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage off
when others => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage on
end case;
end process THREE_BANKS_PARITY_REG_RD_P;
----------------------------------------
PARITY_ERR_REG_STORE_P: process (s_axi_aclk) is
-----------------------
--variable err_parity_bits : std_logic_vector(2 downto 0);
-----
begin
-----
--err_parity_bits := parity_error_MEM & Parity_err_i;
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PEAR_REG (i) <= (others => '0');
end loop;
else
if (ip2bus_errack = '1') then
case err_parity_bits is -- (parity_error_MEM & Parity_err_i ) is
when "001" => PEAR_REG(0) <= parity_error_adrss;
when "011" => PEAR_REG(1) <= parity_error_adrss;
when "101" => PEAR_REG(2) <= parity_error_adrss;
-- coverage off
when others => null; -- axi_lite_ip2bus_data1 <= (others => '0');
-- coverage on
end case;
else
PEAR_REG(0) <= PEAR_REG(0);
PEAR_REG(1) <= PEAR_REG(1);
PEAR_REG(2) <= PEAR_REG(2);
end if;
end if;
end if;
end process PARITY_ERR_REG_STORE_P;
end generate PERR_NUM_MEM_3_GEN;
------------------------------------------------------
------------------------------------------------------
PERR_NUM_MEM_2_GEN: if C_NUM_BANKS_MEM = 2 generate
------------------
begin
-----
TWO_BANKS_PARITY_REG_RD_P : process (bus2ip_rdce_lite_cmb,
PEAR_REG(0),
PEAR_REG(1)
) is
variable internal_bus2ip_rdack : std_logic_vector(7 downto 0); -- 9/14/2013
--(((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0);--(3 downto 0);
-----
begin
-----
internal_bus2ip_rdack := bus2ip_rdce_lite_cmb;
-- defaults
axi_lite_ip2bus_data1 <= (others => '0');
axi_lite_ip2bus_rdack1 <= or_reduce(bus2ip_rdce_lite_cmb);
case internal_bus2ip_rdack(7 downto 0) is -- (1 downto 0) is
--when "01" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
--when "10" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
---- coverage off
--when others => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage on
when "00000001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
when "00000010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
-- hole returns data 0
when "00000100" => axi_lite_ip2bus_data1 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00100000" => axi_lite_ip2bus_data1 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data1 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage off
when others => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage on
end case;
end process TWO_BANKS_PARITY_REG_RD_P;
----------------------------------------
PARITY_ERR_REG_STORE_P: process (s_axi_aclk) is
-----------------------
--variable err_parity_bits : std_logic_vector(2 downto 0);
--variable err_parity_bits : std_logic_vector(2 downto 0);
-----
begin
-----
--err_parity_bits := parity_error_MEM & Parity_err_i;
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PEAR_REG (i) <= (others => '0');
end loop;
else
if (ip2bus_errack = '1') then
case err_parity_bits is -- (parity_error_MEM & Parity_err_i) is
when "001" => PEAR_REG(0) <= parity_error_adrss;
when "011" => PEAR_REG(1) <= parity_error_adrss;
-- coverage off
when others => NULL;
-- coverage on
end case;
else
PEAR_REG(0) <= PEAR_REG(0);
PEAR_REG(1) <= PEAR_REG(1);
end if;
end if;
end if;
end process PARITY_ERR_REG_STORE_P;
end generate PERR_NUM_MEM_2_GEN;
------------------------------------------------------
------------------------------------------------------
PERR_NUM_MEM_1_GEN: if C_NUM_BANKS_MEM = 1 generate
------------------
begin
-----
ONE_BANKS_PARITY_REG_RD_P : process (bus2ip_rdce_lite_cmb,
PEAR_REG(0)
) is
variable internal_bus2ip_rdack : std_logic_vector(7 downto 0);
-----
begin
-----
internal_bus2ip_rdack := bus2ip_rdce_lite_cmb;-- or_reduce(bus2ip_rdce_lite_cmb);
-- defaults
axi_lite_ip2bus_data1 <= (others => '0');
axi_lite_ip2bus_rdack1 <= or_reduce(bus2ip_rdce_lite_cmb);
case internal_bus2ip_rdack is
--when '1' => axi_lite_ip2bus_data1 <= PEAR_REG(0);
---- coverage off
--when others => axi_lite_ip2bus_data1 <= (others=> '0'); -- null;
---- coverage on
when "00000001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
-- hole returns data 0
when "00000010" => axi_lite_ip2bus_data1 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data1 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00100000" => axi_lite_ip2bus_data1 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data1 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage off
when others => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage on
end case;
end process ONE_BANKS_PARITY_REG_RD_P;
----------------------------------------
PARITY_ERR_REG_STORE_P: process (s_axi_aclk) is
-----------------------
--variable err_parity_bits : std_logic_vector(2 downto 0);
-----
begin
-----
--err_parity_bits := parity_error_MEM & Parity_err_i;
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PEAR_REG (i) <= (others => '0');
end loop;
else
if (ip2bus_errack = '1') then
case err_parity_bits is -- (parity_error_MEM & Parity_err_i) is
when "001" => PEAR_REG(0) <= parity_error_adrss;
-- coverage off
when others => NULL;
-- coverage on
end case;
else
PEAR_REG(0) <= PEAR_REG(0);
end if;
end if;
end if;
end process PARITY_ERR_REG_STORE_P;
end generate PERR_NUM_MEM_1_GEN;
------------------------------------------------------
end generate PARITY_ENABLED_REG_GEN;
------------------------------------
-----------------------------------------------------------------------------
-- PCR_X_RD, Byte Parity Register Read Process
-----------------------------------------------------------------------------
LINEAR_FLASH_CONFIG_REG_GEN: if (C_LINEAR_FLASH_SYNC_BURST = 1) generate
--------------------
begin
-----
PCR_FOUR_GEN: if C_NUM_BANKS_MEM = 4 generate
LFLASH_CONFIG_REG_RD_PROCESS_4 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= PCR_REG(2);
when "10000000" => axi_lite_ip2bus_data2 <= PCR_REG(3);
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process LFLASH_CONFIG_REG_RD_PROCESS_4;
end generate PCR_FOUR_GEN;
PCR_THREE_GEN: if C_NUM_BANKS_MEM = 3 generate
LFLASH_CONFIG_REG_RD_PROCESS_3 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= PCR_REG(2);
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process LFLASH_CONFIG_REG_RD_PROCESS_3;
end generate PCR_THREE_GEN;
PCR_TWO_GEN: if C_NUM_BANKS_MEM = 2 generate
LFLASH_CONFIG_REG_RD_PROCESS_2 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process LFLASH_CONFIG_REG_RD_PROCESS_2;
end generate PCR_TWO_GEN;
PCR_ONE_GEN: if C_NUM_BANKS_MEM = 1 generate
LFLASH_CONFIG_REG_RD_PROCESS_1 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data2 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process LFLASH_CONFIG_REG_RD_PROCESS_1;
end generate PCR_ONE_GEN;
-----------------------------------------
axi_lite_ip2bus_wrack2 <= or_reduce(bus2ip_wrce_lite_cmb);-- ((C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
-----------------------------------------
LFLASH_CONFIG_REG_WR_PROCESS : process (s_axi_aclk) is
begin
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PCR_REG (i) <= X"0000_0024";
end loop;
else
for i in C_NUM_BANKS_MEM-1 downto 0 loop
if((bus2ip_wrce_lite_cmb(4+i)='1') and
(MEM_TYPE_ARRAY(i) = 2 or MEM_TYPE_ARRAY(i) = 5 )
)then
PCR_REG(i)(31 downto 30) <= s_axi_reg_wdata(31 downto 30);
PCR_REG(i)(6 downto 0) <= s_axi_reg_wdata(6 downto 0);
else
PCR_REG(i) <= PCR_REG(i);
end if;
end loop;
end if;
end if;
end process LFLASH_CONFIG_REG_WR_PROCESS;
----------------------------------------
MEM_WAIT_TEMP_1_GEN: if C_NUM_BANKS_MEM = 1 generate
------------------
begin
-------------------------------------------------------------------------------
-- Registers the input memory wait signal.
-------------------------------------------------------------------------------
INPUT_MEM_WAIT_REGS_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
if(Mem_WAIT_reg_one_hot = '1') then
Mem_WAIT_reg_d1 <= '0';
elsif(Mem_WAIT_io(0) = '1')then
Mem_WAIT_reg_d1 <= '1';
end if;
end if;
end process INPUT_MEM_WAIT_REGS_PROCESS;
----------------------------------------
DUAL_REG_MEM_WAIT_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_reg_d2 <= Mem_WAIT_reg_d1;
end if;
end process DUAL_REG_MEM_WAIT_PROCESS;
----------------------------------------
Mem_WAIT_reg_one_hot <= Mem_WAIT_reg_d1 and (not Mem_WAIT_reg_d2);
Mem_WAIT_reg <= Mem_WAIT_reg_d1;
Linear_flash_brst_rd_flag <= sync_mode(0) and
(not Cre_reg_en(0))and
temp_bus2ip_cs(0); -- 4/2/2013
Cre_reg_en_reduced <= or_reduce(Cre_reg_en);
-----------------------------------------
end generate MEM_WAIT_TEMP_1_GEN;
MEM_WAIT_TEMP_2_GEN: if C_NUM_BANKS_MEM = 2 generate
------------------
begin
INPUT_MEM_WAIT_REGS_PROCESS: process(RdClk)is
begin
if RdClk'event and RdClk = '1' then
if(Mem_WAIT_reg_one_hot = '1') then
Mem_WAIT_reg_d1 <= '0';
elsif(Mem_WAIT_io(0) = '1' or Mem_WAIT_io(1) = '1')then
Mem_WAIT_reg_d1 <= '1';
end if;
end if;
end process INPUT_MEM_WAIT_REGS_PROCESS;
----------------------------------------
DUAL_REG_MEM_WAIT_PROCESS: process(RdClk) is
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_reg_d2 <= Mem_WAIT_reg_d1;
end if;
end process DUAL_REG_MEM_WAIT_PROCESS;
----------------------------------------
Mem_WAIT_reg_one_hot <= Mem_WAIT_reg_d1 and (not Mem_WAIT_reg_d2);
Mem_WAIT_reg <= Mem_WAIT_reg_d1;
Linear_flash_brst_rd_flag <= (sync_mode(0) and (not Cre_reg_en(0)))
when (temp_bus2ip_cs(0) = '1')
else
(sync_mode(1) and (not Cre_reg_en(1)))
when (temp_bus2ip_cs(1) = '1')
else
'0';
Cre_reg_en_reduced <= or_reduce(Cre_reg_en);
----------------------------------------
end generate MEM_WAIT_TEMP_2_GEN;
MEM_WAIT_TEMP_3_GEN: if C_NUM_BANKS_MEM = 3 generate
------------------
begin
INPUT_MEM_WAIT_REGS_PROCESS: process(RdClk)is
begin
if RdClk'event and RdClk = '1' then
if(Mem_WAIT_reg_one_hot = '1') then
Mem_WAIT_reg_d1 <= '0';
elsif(Mem_WAIT_io(0) = '1' or Mem_WAIT_io(1) = '1' or Mem_WAIT_io(2) = '1')then
Mem_WAIT_reg_d1 <= '1';
end if;
end if;
end process INPUT_MEM_WAIT_REGS_PROCESS;
-----------------------------------------
DUAL_REG_MEM_WAIT_PROCESS: process(RdClk)is
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_reg_d2 <= Mem_WAIT_reg_d1;
end if;
end process DUAL_REG_MEM_WAIT_PROCESS;
-----------------------------------------
Mem_WAIT_reg_one_hot <= Mem_WAIT_reg_d1 and (not Mem_WAIT_reg_d2);
Mem_WAIT_reg <= Mem_WAIT_reg_d1;
Linear_flash_brst_rd_flag <= (sync_mode(0) and (not Cre_reg_en(0)))
when (temp_bus2ip_cs(0) = '1')
else
(sync_mode(1) and (not Cre_reg_en(1)))
when (temp_bus2ip_cs(1) = '1')
else
(sync_mode(2) and (not Cre_reg_en(2)))
when (temp_bus2ip_cs(2) = '1')
else
'0';
Cre_reg_en_reduced <= or_reduce(Cre_reg_en);
-----------------------------------------
end generate MEM_WAIT_TEMP_3_GEN;
MEM_WAIT_TEMP_4_GEN: if C_NUM_BANKS_MEM = 4 generate
------------------
begin
INPUT_MEM_WAIT_REGS_PROCESS: process(RdClk)is
begin
if RdClk'event and RdClk = '1' then
if(Mem_WAIT_reg_one_hot = '1') then
Mem_WAIT_reg_d1 <= '0';
elsif(Mem_WAIT_io(0) = '1' or
Mem_WAIT_io(1) = '1' or
Mem_WAIT_io(2) = '1' or
Mem_WAIT_io(3) = '1'
)then
Mem_WAIT_reg_d1 <= '1';
end if;
end if;
end process INPUT_MEM_WAIT_REGS_PROCESS;
----------------------------------------
DUAL_REG_MEM_WAIT_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_reg_d2 <= Mem_WAIT_reg_d1;
end if;
end process DUAL_REG_MEM_WAIT_PROCESS;
----------------------------------------
Mem_WAIT_reg_one_hot <= Mem_WAIT_reg_d1 and (not Mem_WAIT_reg_d2);
Mem_WAIT_reg <= Mem_WAIT_reg_d1;
Linear_flash_brst_rd_flag <= (sync_mode(0) and (not Cre_reg_en(0)))
when (temp_bus2ip_cs(0) = '1')
else
(sync_mode(1) and (not Cre_reg_en(1)))
when (temp_bus2ip_cs(1) = '1')
else
(sync_mode(2) and (not Cre_reg_en(2)))
when (temp_bus2ip_cs(2) = '1')
else
(sync_mode(3) and (not Cre_reg_en(3)))
when (temp_bus2ip_cs(3) = '1')
else
'0';
Cre_reg_en_reduced <= or_reduce(Cre_reg_en);
----------------------------------------
end generate MEM_WAIT_TEMP_4_GEN;
Linear_flash_rd_data_ack <= Mem_WAIT_reg;
WR_PROGRAM_PROCESS : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
ADDR_select <= '0';
--ADDR_PROGRAM <= (others => '0');
elsif(S_AXI_MEM_WREADY1 = '1' and S_AXI_MEM_WVALID = '1') then
if(signed(S_AXI_MEM_WDATA(15 downto 0)) = signed(temp_prog_cmd_data)) then
ADDR_select <= '1';
-- ADDR_PROGRAM <= S_AXI_MEM_AWADDR;
end if;
elsif(S_AXI_MEM_BREADY = '1' and S_AXI_MEM_BVALID1 = '1') then
ADDR_select <= '0';
--ADDR_PROGRAM <= (others => '0');
end if;
end if;
end process WR_PROGRAM_PROCESS;
WR_PROGRAM_PROCESS_N : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
ADDR_PROGRAM_D <= (others => '0');
else
ADDR_PROGRAM_D <= ADDR_PROGRAM;
end if;
end if;
end process WR_PROGRAM_PROCESS_N;
ADDR_PROGRAM <= (others => '0') when (s_axi_aresetn = '0')
else S_AXI_MEM_AWADDR when ((S_AXI_MEM_WREADY1 = '1' and S_AXI_MEM_WVALID = '1') and (signed(S_AXI_MEM_WDATA(15 downto 0)) = signed(temp_prog_cmd_data)))
else (others => '0') when (S_AXI_MEM_BREADY = '1' and S_AXI_MEM_BVALID1 = '1')
else ADDR_PROGRAM_D;
-------------------------------
BURST_RD_ADDR_PROCESS : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
ADDR_SYNCH_BURST_RD_D <= (others => '0');
elsif(S_AXI_MEM_ARREADY1 = '1' and S_AXI_MEM_ARVALID = '1') then
ADDR_SYNCH_BURST_RD_D <= ADDR_SYNCH_BURST_RD;
end if;
--if (s_axi_aresetn = '0') then
-- ADDR_SYNCH_BURST_RD <= (others => '0');
--elsif(S_AXI_MEM_ARREADY1 = '1' and S_AXI_MEM_ARVALID = '1') then
-- ADDR_SYNCH_BURST_RD <= S_AXI_MEM_ARADDR;
--end if;
end if;
end process BURST_RD_ADDR_PROCESS;
ADDR_SYNCH_BURST_RD <= (others => '0') when (s_axi_aresetn = '0')
else S_AXI_MEM_ARADDR when (S_AXI_MEM_ARREADY1 = '1' and S_AXI_MEM_ARVALID = '1')
else ADDR_SYNCH_BURST_RD_D;
--CTRL_REG_ADDR(16 downto 1) <= CTRL_REG_DATA;
-- Linear_flash_rd_data_ack <= sync_data_select;
--Linear_flash_brst_rd_flag <= sync_mode and (not Cre_reg_en);
FLASH_SYNCH_CRE_WR_PROCESS : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
Cre_reg_en <= (others => '0');
sync_mode <= (others => '0');
else
Cre_reg_en <= (others => '0');
sync_mode <= (others => '0');
for i in C_NUM_BANKS_MEM-1 downto 0 loop
if(bus2ip_ce_lite_cmb(4+i) = '1' ) then
sync_mode(i) <= ( PCR_REG(i)(30));
Cre_reg_en(i) <= PCR_REG(i)(31);
end if;
end loop;
end if;
end if;
end process FLASH_SYNCH_CRE_WR_PROCESS;
end generate LINEAR_FLASH_CONFIG_REG_GEN;
--------------------------------------------------------------------------------
NO_LFLASH_PSRAM_CONFIG_REG_GEN: if (GLOBAL_PSRAM_FLASH_MEM = 0) generate
--------------------
begin
-----
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= '0';
axi_lite_ip2bus_wrack2 <= '0'; -- 6/6/2013
psram_page_mode <= '1';-- DONT change this value
CRE_WR_PROCESS_G : process (s_axi_aclk) is
begin
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
Mem_CRE_int <= '0';
end if;
end process CRE_WR_PROCESS_G;
end generate NO_LFLASH_PSRAM_CONFIG_REG_GEN;
-------------------------------------
-- NO_PSRAM_CONFIG_REG_GEN : If any of the memories are defined with PSRAM, then there will
-- local register in the core.
----------------
PSRAM_CONFIG_REG_GEN: if (GLOBAL_PSRAM_MEM = 1) generate
--------------------
begin
-----
--SRAM_CONFIG_REG_RD_PROCESS : process (bus2ip_rdce_lite_cmb,
-- PCR_REG) is
--egin
--- defaults
--xi_lite_ip2bus_data2 <= (others => '0');
--xi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb); -- 9/14/2013 -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0));
--or i in C_NUM_BANKS_MEM-1 downto 0 loop
-- if( (bus2ip_rdce_lite_cmb(4+i)='1') and
-- (MEM_TYPE_ARRAY(i)=4 )
-- )then
-- axi_lite_ip2bus_data2 <= PCR_REG(i);
-- else -- 9/14/2013
-- axi_lite_ip2bus_data2 <= (others => '0');
-- end if;
--nd loop;
--nd process PSRAM_CONFIG_REG_RD_PROCESS;
PSRAM_ONE_GEN: if C_NUM_BANKS_MEM = 1 generate
PSRAM_CONFIG_REG_RD_PROCESS_1 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data2 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process PSRAM_CONFIG_REG_RD_PROCESS_1;
end generate PSRAM_ONE_GEN;
PSRAM_TWO_GEN: if C_NUM_BANKS_MEM = 2 generate
PSRAM_CONFIG_REG_RD_PROCESS_2 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process PSRAM_CONFIG_REG_RD_PROCESS_2;
end generate PSRAM_TWO_GEN;
PSRAM_THREE_GEN: if C_NUM_BANKS_MEM = 3 generate
PSRAM_CONFIG_REG_RD_PROCESS_3 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= PCR_REG(2);
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process PSRAM_CONFIG_REG_RD_PROCESS_3;
end generate PSRAM_THREE_GEN;
PSRAM_FOUR_GEN: if C_NUM_BANKS_MEM = 4 generate
PSRAM_CONFIG_REG_RD_PROCESS_4 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= PCR_REG(2);
when "10000000" => axi_lite_ip2bus_data2 <= PCR_REG(3);
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process PSRAM_CONFIG_REG_RD_PROCESS_4;
end generate PSRAM_FOUR_GEN;
axi_lite_ip2bus_wrack2 <= or_reduce(bus2ip_wrce_lite_cmb); -- 9/14/2013 -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0));
PSRAM_CONFIG_REG_WR_PROCESS : process (s_axi_aclk) is
begin
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PCR_REG (i) <= X"0000_0024";
end loop;
else
for i in C_NUM_BANKS_MEM-1 downto 0 loop
if((bus2ip_wrce_lite_cmb(4+i)='1') and
(MEM_TYPE_ARRAY(i) = 4 )
)then
--PCR_REG(i) <= s_axi_reg_wdata;
PCR_REG(i)(31 downto 30) <= s_axi_reg_wdata(31 downto 30);
PCR_REG(i)(6 downto 0) <= s_axi_reg_wdata(6 downto 0);
else
PCR_REG(i) <= PCR_REG(i);
end if;
end loop;
end if;
end if;
end process PSRAM_CONFIG_REG_WR_PROCESS;
----------------------------------------
CRE_WR_PROCESS : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
Mem_CRE_int <= '0';
psram_page_mode <= '1';
else
-- defaults
Mem_CRE_int <= '0';
psram_page_mode <= '0';
for i in C_NUM_BANKS_MEM-1 downto 0 loop
if (temp_bus2ip_cs(i) = '1' ) then
Mem_CRE_int <= PCR_REG(i)(6);-- (25);
psram_page_mode <= PCR_REG(i)(0); -- (31);
end if;
end loop;
end if;
end if;
end process CRE_WR_PROCESS;
---------------------------
end generate PSRAM_CONFIG_REG_GEN;
-------------------------
end generate REG_EN_GEN;
-------------------------------------------------------------------------------
AXI_EMC_NATIVE_INTERFACE_I: entity axi_emc_v3_0.axi_emc_native_interface
-- Generics to be set by user
generic map(
C_FAMILY => C_FAMILY ,
C_S_AXI_MEM_ADDR_WIDTH => C_S_AXI_MEM_ADDR_WIDTH ,
C_S_AXI_MEM_DATA_WIDTH => C_S_AXI_MEM_DATA_WIDTH ,
C_S_AXI_MEM_ID_WIDTH => C_S_AXI_MEM_ID_WIDTH ,
C_S_AXI_MEM0_BASEADDR => C_S_AXI_MEM0_BASEADDR ,
C_S_AXI_MEM0_HIGHADDR => C_S_AXI_MEM0_HIGHADDR ,
C_S_AXI_MEM1_BASEADDR => C_S_AXI_MEM1_BASEADDR ,
C_S_AXI_MEM1_HIGHADDR => C_S_AXI_MEM1_HIGHADDR ,
C_S_AXI_MEM2_BASEADDR => C_S_AXI_MEM2_BASEADDR ,
C_S_AXI_MEM2_HIGHADDR => C_S_AXI_MEM2_HIGHADDR ,
C_S_AXI_MEM3_BASEADDR => C_S_AXI_MEM3_BASEADDR ,
C_S_AXI_MEM3_HIGHADDR => C_S_AXI_MEM3_HIGHADDR ,
AXI_ARD_ADDR_RANGE_ARRAY => AXI_ARD_ADDR_RANGE_ARRAY,
AXI_ARD_NUM_CE_ARRAY => AXI_ARD_NUM_CE_ARRAY ,
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM
)
port map(
s_axi_aclk => s_axi_aclk ,
s_axi_aresetn => s_axi_aresetn ,
-- -- AXI Write Address Channel Signals
S_AXI_MEM_AWID => s_axi_mem_awid ,
S_AXI_MEM_AWADDR => s_axi_mem_awaddr ,
S_AXI_MEM_AWLEN => s_axi_mem_awlen ,
S_AXI_MEM_AWSIZE => s_axi_mem_awsize ,
S_AXI_MEM_AWBURST => s_axi_mem_awburst ,
S_AXI_MEM_AWLOCK => s_axi_mem_awlock ,
S_AXI_MEM_AWCACHE => s_axi_mem_awcache ,
S_AXI_MEM_AWPROT => s_axi_mem_awprot ,
S_AXI_MEM_AWVALID => s_axi_mem_awvalid ,
S_AXI_MEM_AWREADY => s_axi_mem_awready ,
-- -- AXI Write Channel Signals
S_AXI_MEM_WDATA => s_axi_mem_wdata ,
S_AXI_MEM_WSTRB => s_axi_mem_wstrb ,
S_AXI_MEM_WLAST => s_axi_mem_wlast ,
S_AXI_MEM_WVALID => s_axi_mem_wvalid ,
S_AXI_MEM_WREADY => s_axi_mem_wready1 ,
-- -- AXI Write Response Channel Signals
S_AXI_MEM_BID => s_axi_mem_bid ,
S_AXI_MEM_BRESP => s_axi_mem_bresp ,
S_AXI_MEM_BVALID => s_axi_mem_bvalid1 ,
S_AXI_MEM_BREADY => s_axi_mem_bready ,
-- -- AXI Read Address Channel Signals
S_AXI_MEM_ARID => s_axi_mem_arid ,
S_AXI_MEM_ARADDR => s_axi_mem_araddr ,
S_AXI_MEM_ARLEN => s_axi_mem_arlen ,
S_AXI_MEM_ARSIZE => s_axi_mem_arsize ,
S_AXI_MEM_ARBURST => s_axi_mem_arburst ,
S_AXI_MEM_ARLOCK => s_axi_mem_arlock ,
S_AXI_MEM_ARCACHE => s_axi_mem_arcache ,
S_AXI_MEM_ARPROT => s_axi_mem_arprot ,
S_AXI_MEM_ARVALID => s_axi_mem_arvalid ,
S_AXI_MEM_ARREADY => s_axi_mem_arready1 ,
-- -- AXI Read Data Channel Signals
S_AXI_MEM_RID => s_axi_mem_rid ,
S_AXI_MEM_RDATA => s_axi_mem_rdata ,
S_AXI_MEM_RRESP => s_axi_mem_rresp ,
S_AXI_MEM_RLAST => s_axi_mem_rlast ,
S_AXI_MEM_RVALID => s_axi_mem_rvalid ,
S_AXI_MEM_RREADY => s_axi_mem_rready ,
-- IP Interconnect (IPIC) port signals ------------------------------------
-- Controls to the IP/IPIF modules
-- IP Interconnect (IPIC) port signals
IP2Bus_Data => temp_ip2bus_data ,
IP2Bus_WrAck => IP2Bus_WrAck ,
IP2Bus_RdAck => IP2Bus_RdAck ,
IP2Bus_AddrAck => IP2Bus_AddrAck ,
IP2Bus_Error => ip2bus_errack ,
Bus2IP_Addr => bus2ip_addr_temp ,
Bus2IP_Data => temp_bus2ip_data ,
Bus2IP_RNW => Bus2IP_RNW ,
Bus2IP_BE => temp_bus2ip_be ,
Bus2IP_Burst => Bus2IP_Burst ,
Bus2IP_BurstLength => bus2ip_burstlength ,
Bus2IP_RdReq => Bus2IP_RdReq_emc ,
Bus2IP_WrReq => Bus2IP_WrReq_emc ,
Bus2IP_CS => temp_bus2ip_cs ,
Bus2IP_RdCE => bus2ip_rdce ,
Bus2IP_WrCE => bus2ip_wrce ,
Type_of_xfer => Type_of_xfer ,
Cre_reg_en => Cre_reg_en_reduced , -- newly added
synch_mem => synch_mem ,
last_addr1 => last_addr1 ,
pr_idle => pr_idle ,
axi_trans_size_reg => axi_trans_size_reg_int
);
---------------------------------------------------------------------------
-- Miscellaneous assignments to match EMC controller to IPIC
---------------------------------------------------------------------------
or_reduced_wrce <= or_reduce(bus2ip_wrce);
------------------------------------------
RD_CE_PIPE_PROCESS : process(s_axi_aclk)is
begin
if(s_axi_aclk'EVENT and s_axi_aclk = '1') then
or_reduced_rdce_d1 <= or_reduce(bus2ip_rdce);
bus2ip_wrreq_reg <= or_reduced_wrce;
end if;
end process RD_CE_PIPE_PROCESS;
------------------------------------------
original_wrce <= or_reduced_wrce;
bus2ip_wrreq_i <= Bus2IP_WrReq_emc;--or_reduce(bus2ip_wrce);
--bus2ip_rdreq_i <= or_reduce(bus2ip_rdce); -- Bus2IP_RdReq_emc;--or_reduce(bus2ip_rdce);
bus2ip_rdreq_i <= Bus2IP_RdReq_emc when synch_mem = '1' else or_reduce(bus2ip_rdce);--or_reduce(bus2ip_rdce);
bus2ip_cs_i <= or_reduce(temp_bus2ip_cs);
---------------------------------------------------------------------------
-- AXI EMC is little endian and EMC COMMON is still big endian, to make
-- this interface work normally, we need to swap the Write and read data
-- comming from and going to slave burst interface
---------------------------------------------------------------------------
ENDIAN_BANKS_0 : if (C_NUM_BANKS_MEM = 1) generate
bus2ip_cs(0)<= temp_bus2ip_cs(0);
end generate ENDIAN_BANKS_0;
ENDIAN_BANKS_1 : if (C_NUM_BANKS_MEM = 2) generate
bus2ip_cs(0)<= temp_bus2ip_cs(0);
bus2ip_cs(1)<= temp_bus2ip_cs(1);
end generate ENDIAN_BANKS_1;
ENDIAN_BANKS_2 : if (C_NUM_BANKS_MEM = 3) generate
bus2ip_cs(0)<= temp_bus2ip_cs(0);
bus2ip_cs(1)<= temp_bus2ip_cs(1);
bus2ip_cs(2)<= temp_bus2ip_cs(2);
end generate ENDIAN_BANKS_2;
ENDIAN_BANKS_3 : if (C_NUM_BANKS_MEM = 4) generate
bus2ip_cs(0)<= temp_bus2ip_cs(0);
bus2ip_cs(1)<= temp_bus2ip_cs(1);
bus2ip_cs(2)<= temp_bus2ip_cs(2);
bus2ip_cs(3)<= temp_bus2ip_cs(3);
end generate ENDIAN_BANKS_3;
ENDIAN_CONVERSION_32 : if (C_S_AXI_MEM_DATA_WIDTH = 32) generate
bus2ip_data(0 to 7) <= temp_bus2ip_data(7 downto 0);
bus2ip_data(8 to 15) <= temp_bus2ip_data(15 downto 8);
bus2ip_data(16 to 23) <= temp_bus2ip_data(23 downto 16);
bus2ip_data(24 to 31) <= temp_bus2ip_data(31 downto 24);
temp_ip2bus_data(7 downto 0) <= ip2bus_data(0 to 7) ;
temp_ip2bus_data(15 downto 8) <= ip2bus_data(8 to 15) ;
temp_ip2bus_data(23 downto 16) <= ip2bus_data(16 to 23);
temp_ip2bus_data(31 downto 24) <= ip2bus_data(24 to 31);
bus2ip_be(0) <= temp_bus2ip_be(0);
bus2ip_be(1) <= temp_bus2ip_be(1);
bus2ip_be(2) <= temp_bus2ip_be(2);
bus2ip_be(3) <= temp_bus2ip_be(3);
-- the below logic is to generate the lower 2 bits of address for 32
-- bit data width
temp_single_0 <= or_reduce(temp_bus2ip_be(1 downto 0));
temp_single_1 <= or_reduce(temp_bus2ip_be(3 downto 0));
bus2ip_addr_reg(2) <= ((not temp_bus2ip_be(0)) and
(temp_bus2ip_be(1)
OR
((NOT temp_bus2ip_be(2)) and
temp_bus2ip_be(3) and
(NOT temp_single_0)
)
)
) and Type_of_xfer;
bus2ip_addr_reg(1) <= (((not temp_bus2ip_be(0)) and (not
temp_bus2ip_be(1))) and (temp_bus2ip_be(2) OR
temp_bus2ip_be(3)))and Type_of_xfer;
bus2ip_addr <= (bus2ip_addr_temp (0 to 29) & bus2ip_addr_reg (1 to 2))
when (Cre_reg_en_reduced = '0')
else
bus2ip_addr_temp ;
bus2ip_addr_reg(0) <= '0';
end generate ENDIAN_CONVERSION_32;
ENDIAN_CONVERSION_64 : if (C_S_AXI_MEM_DATA_WIDTH = 64) generate
bus2ip_data(0 to 7) <= temp_bus2ip_data(7 downto 0);
bus2ip_data(8 to 15) <= temp_bus2ip_data(15 downto 8);
bus2ip_data(16 to 23) <= temp_bus2ip_data(23 downto 16);
bus2ip_data(24 to 31) <= temp_bus2ip_data(31 downto 24);
bus2ip_data(32 to 39) <= temp_bus2ip_data(39 downto 32);
bus2ip_data(40 to 47) <= temp_bus2ip_data(47 downto 40);
bus2ip_data(48 to 55) <= temp_bus2ip_data(55 downto 48);
bus2ip_data(56 to 63) <= temp_bus2ip_data(63 downto 56);
temp_ip2bus_data(7 downto 0) <= ip2bus_data(0 to 7) ;
temp_ip2bus_data(15 downto 8) <= ip2bus_data(8 to 15) ;
temp_ip2bus_data(23 downto 16) <= ip2bus_data(16 to 23);
temp_ip2bus_data(31 downto 24) <= ip2bus_data(24 to 31);
temp_ip2bus_data(39 downto 32) <= ip2bus_data(32 to 39);
temp_ip2bus_data(47 downto 40) <= ip2bus_data(40 to 47);
temp_ip2bus_data(55 downto 48) <= ip2bus_data(48 to 55);
temp_ip2bus_data(63 downto 56) <= ip2bus_data(56 to 63);
bus2ip_be(0) <= temp_bus2ip_be(0);
bus2ip_be(1) <= temp_bus2ip_be(1);
bus2ip_be(2) <= temp_bus2ip_be(2);
bus2ip_be(3) <= temp_bus2ip_be(3);
bus2ip_be(4) <= temp_bus2ip_be(4);
bus2ip_be(5) <= temp_bus2ip_be(5);
bus2ip_be(6) <= temp_bus2ip_be(6);
bus2ip_be(7) <= temp_bus2ip_be(7);
-- the below logic is to generate the lower 3 bits of address for 64 bit
-- data width
temp_single_0 <= or_reduce(temp_bus2ip_be(1 downto 0));
temp_single_1 <= or_reduce(temp_bus2ip_be(3 downto 0));
temp_single_2 <= or_reduce(temp_bus2ip_be(5 downto 0));
bus2ip_addr_reg(2) <=((not temp_bus2ip_be(0)) and (temp_bus2ip_be(1)
OR ((NOT temp_bus2ip_be(2)) and
temp_bus2ip_be(3) and
(NOT temp_single_0))
OR ((NOT temp_bus2ip_be(4)) and
temp_bus2ip_be(5) and
(NOT temp_single_1))
OR ((NOT temp_bus2ip_be(6)) and
temp_bus2ip_be(7) and
(NOT temp_single_2)))) and Type_of_xfer;
bus2ip_addr_reg(1) <=((((not temp_bus2ip_be(0)) and
(not temp_bus2ip_be(1))) and (temp_bus2ip_be(2)
OR temp_bus2ip_be(3))) OR
(((not temp_bus2ip_be(4)) and
(not temp_bus2ip_be(5))) and (temp_bus2ip_be(6)
OR temp_bus2ip_be(7)) and (NOT temp_single_0)))
and Type_of_xfer;
bus2ip_addr_reg(0) <= (not (temp_bus2ip_be(0) or temp_bus2ip_be(1) or
temp_bus2ip_be(2) or temp_bus2ip_be(3)))
and Type_of_xfer;
bus2ip_addr <= bus2ip_addr_temp (0 to 28) &
bus2ip_addr_reg (0 to 2)
when bus2ip_cs_i = '1' else
(others => '0');
end generate ENDIAN_CONVERSION_64;
-----------------------------------------------------------------------------
--RESET_TOGGLE: convert active low to active hig reset to rest of the core.
-----------------------------------------------------------------------------
RESET_TOGGLE: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(s_axi_aresetn);
end if;
end process RESET_TOGGLE;
EMC_CTRL_I: entity emc_common_v3_0.emc
generic map(
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM,
C_IPIF_DWIDTH => C_S_AXI_MEM_DATA_WIDTH,
C_IPIF_AWIDTH => C_S_AXI_MEM_ADDR_WIDTH,
C_MEM0_BASEADDR => C_S_AXI_MEM0_BASEADDR,
C_MEM0_HIGHADDR => C_S_AXI_MEM0_HIGHADDR,
C_MEM1_BASEADDR => C_S_AXI_MEM1_BASEADDR,
C_MEM1_HIGHADDR => C_S_AXI_MEM1_HIGHADDR,
C_MEM2_BASEADDR => C_S_AXI_MEM2_BASEADDR,
C_MEM2_HIGHADDR => C_S_AXI_MEM2_HIGHADDR,
C_MEM3_BASEADDR => C_S_AXI_MEM3_BASEADDR,
C_MEM3_HIGHADDR => C_S_AXI_MEM3_HIGHADDR,
C_PAGEMODE_FLASH_0 => C_PAGEMODE_FLASH_0,
C_PAGEMODE_FLASH_1 => C_PAGEMODE_FLASH_1,
C_PAGEMODE_FLASH_2 => C_PAGEMODE_FLASH_2,
C_PAGEMODE_FLASH_3 => C_PAGEMODE_FLASH_3,
C_INCLUDE_NEGEDGE_IOREGS => C_INCLUDE_NEGEDGE_IOREGS,
C_MEM0_WIDTH => C_MEM0_WIDTH,
C_MEM1_WIDTH => C_MEM1_WIDTH,
C_MEM2_WIDTH => C_MEM2_WIDTH,
C_MEM3_WIDTH => C_MEM3_WIDTH,
C_MAX_MEM_WIDTH => C_MAX_MEM_WIDTH,
C_MEM0_TYPE => C_MEM0_TYPE,
C_MEM1_TYPE => C_MEM1_TYPE,
C_MEM2_TYPE => C_MEM2_TYPE,
C_MEM3_TYPE => C_MEM3_TYPE,
C_PARITY_TYPE_0 => C_PARITY_TYPE_MEM_0,
C_PARITY_TYPE_1 => C_PARITY_TYPE_MEM_1,
C_PARITY_TYPE_2 => C_PARITY_TYPE_MEM_2,
C_PARITY_TYPE_3 => C_PARITY_TYPE_MEM_3,
C_INCLUDE_DATAWIDTH_MATCHING_0 => C_INCLUDE_DATAWIDTH_MATCHING_0,
C_INCLUDE_DATAWIDTH_MATCHING_1 => C_INCLUDE_DATAWIDTH_MATCHING_1,
C_INCLUDE_DATAWIDTH_MATCHING_2 => C_INCLUDE_DATAWIDTH_MATCHING_2,
C_INCLUDE_DATAWIDTH_MATCHING_3 => C_INCLUDE_DATAWIDTH_MATCHING_3,
-- Memory read and write access times for all memory banks
C_BUS_CLOCK_PERIOD_PS => C_AXI_CLK_PERIOD_PS,
C_SYNCH_MEM_0 => C_SYNCH_MEM_0,
C_SYNCH_PIPEDELAY_0 => C_SYNCH_PIPEDELAY_0,
C_TCEDV_PS_MEM_0 => C_TCEDV_PS_MEM_0,
C_TAVDV_PS_MEM_0 => C_TAVDV_PS_MEM_0,
C_TPACC_PS_FLASH_0 => C_TPACC_PS_FLASH_0,
C_THZCE_PS_MEM_0 => C_THZCE_PS_MEM_0,
C_THZOE_PS_MEM_0 => C_THZOE_PS_MEM_0,
C_TWC_PS_MEM_0 => C_TWC_PS_MEM_0,
C_TWP_PS_MEM_0 => C_TWP_PS_MEM_0,
C_TWPH_PS_MEM_0 => C_TWPH_PS_MEM_0,
C_TLZWE_PS_MEM_0 => C_TLZWE_PS_MEM_0,
C_WR_REC_TIME_MEM_0 => C_WR_REC_TIME_MEM_0,
C_SYNCH_MEM_1 => C_SYNCH_MEM_1,
C_SYNCH_PIPEDELAY_1 => C_SYNCH_PIPEDELAY_1,
C_TCEDV_PS_MEM_1 => C_TCEDV_PS_MEM_1,
C_TAVDV_PS_MEM_1 => C_TAVDV_PS_MEM_1,
C_TPACC_PS_FLASH_1 => C_TPACC_PS_FLASH_1,
C_THZCE_PS_MEM_1 => C_THZCE_PS_MEM_1,
C_THZOE_PS_MEM_1 => C_THZOE_PS_MEM_1,
C_TWC_PS_MEM_1 => C_TWC_PS_MEM_1,
C_TWP_PS_MEM_1 => C_TWP_PS_MEM_1,
C_TWPH_PS_MEM_1 => C_TWPH_PS_MEM_1,
C_TLZWE_PS_MEM_1 => C_TLZWE_PS_MEM_1,
C_WR_REC_TIME_MEM_1 => C_WR_REC_TIME_MEM_1,
C_SYNCH_MEM_2 => C_SYNCH_MEM_2,
C_SYNCH_PIPEDELAY_2 => C_SYNCH_PIPEDELAY_2,
C_TCEDV_PS_MEM_2 => C_TCEDV_PS_MEM_2,
C_TAVDV_PS_MEM_2 => C_TAVDV_PS_MEM_2,
C_TPACC_PS_FLASH_2 => C_TPACC_PS_FLASH_2,
C_THZCE_PS_MEM_2 => C_THZCE_PS_MEM_2,
C_THZOE_PS_MEM_2 => C_THZOE_PS_MEM_2,
C_TWC_PS_MEM_2 => C_TWC_PS_MEM_2,
C_TWP_PS_MEM_2 => C_TWP_PS_MEM_2,
C_TWPH_PS_MEM_2 => C_TWPH_PS_MEM_2,
C_TLZWE_PS_MEM_2 => C_TLZWE_PS_MEM_2,
C_WR_REC_TIME_MEM_2 => C_WR_REC_TIME_MEM_2,
C_SYNCH_MEM_3 => C_SYNCH_MEM_3,
C_SYNCH_PIPEDELAY_3 => C_SYNCH_PIPEDELAY_3,
C_TCEDV_PS_MEM_3 => C_TCEDV_PS_MEM_3,
C_TAVDV_PS_MEM_3 => C_TAVDV_PS_MEM_3,
C_TPACC_PS_FLASH_3 => C_TPACC_PS_FLASH_3,
C_THZCE_PS_MEM_3 => C_THZCE_PS_MEM_3,
C_THZOE_PS_MEM_3 => C_THZOE_PS_MEM_3,
C_TWC_PS_MEM_3 => C_TWC_PS_MEM_3,
C_TWP_PS_MEM_3 => C_TWP_PS_MEM_3,
C_TWPH_PS_MEM_3 => C_TWPH_PS_MEM_3,
C_TLZWE_PS_MEM_3 => C_TLZWE_PS_MEM_3,
C_WR_REC_TIME_MEM_3 => C_WR_REC_TIME_MEM_3
)
port map (
Bus2IP_Clk => s_axi_aclk ,
RdClk => RdClk ,
Bus2IP_Reset => Bus2IP_Reset ,
-- Bus and IPIC Interface signals
Bus2IP_Addr => bus2ip_addr ,
Bus2IP_BE => bus2ip_be ,
Bus2IP_Data => bus2ip_data ,
Bus2IP_RNW => bus2ip_rnw ,
Bus2IP_Burst => bus2ip_burst ,
Bus2IP_WrReq => bus2ip_wrreq_i ,
Bus2IP_RdReq => bus2ip_rdreq_i ,
Linear_flash_brst_rd_flag => Linear_flash_brst_rd_flag ,
Linear_flash_rd_data_ack => Linear_flash_rd_data_ack ,
Bus2IP_RdReq_emc => Bus2IP_RdReq_emc ,
Bus2IP_WrReq_emc => Bus2IP_WrReq_emc ,
Bus2IP_Mem_CS => bus2ip_cs ,
Bus2IP_BurstLength => bus2ip_burstlength ,
IP2Bus_Data => ip2bus_data ,
IP2Bus_errAck => ip2bus_errack ,
IP2Bus_retry => open ,
IP2Bus_toutSup => open ,
IP2Bus_RdAck => ip2bus_rdack ,
IP2Bus_WrAck => ip2bus_wrack ,
IP2Bus_AddrAck => ip2bus_addrack ,
parity_error_adrss => parity_error_adrss , -- 32 bit
parity_error_mem => parity_error_MEM , -- 2 bit
Type_of_xfer => Type_of_xfer ,
psram_page_mode => psram_page_mode ,
original_wrce => original_wrce ,
-- Memory signals
Mem_A => mem_a_i ,
Mem_DQ_I => mem_dq_i_i ,
Mem_DQ_O => mem_dq_o_i ,
Mem_DQ_T => mem_dq_t_i ,
Mem_DQ_PRTY_I => mem_dq_parity_i_i ,
Mem_DQ_PRTY_O => mem_dq_parity_o_i ,
Mem_DQ_PRTY_T => mem_dq_parity_t_i ,
Mem_CEN => mem_cen_i ,
Mem_OEN => mem_oen_i ,
Mem_WEN => mem_wen_i ,
Mem_QWEN => mem_qwen_i ,
Mem_BEN => mem_ben_i ,
Mem_RPN => Mem_RPN ,
Mem_CE => mem_ce_i ,
Mem_ADV_LDN => mem_adv_ldn_i ,
Mem_LBON => Mem_LBON ,
Mem_CKEN => mem_cken_i ,
Mem_RNW => Mem_RNW ,
Cre_reg_en => Cre_reg_en_reduced ,
MEM_WAIT => Mem_WAIT_reg ,
synch_mem12 => synch_mem ,
last_addr1 => last_addr1 ,
pr_idle => pr_idle ,
axi_trans_size_reg => axi_trans_size_reg_int,
axi_arsize => axi_arsize,
axi_wvalid => S_AXI_MEM_WVALID,
axi_wlast => S_AXI_MEM_WLAST,
Parity_err => Parity_err_i
);
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/synth/design_1_microblaze_0_axi_intc_0.vhd | 2 | 11547 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_intc:4.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_intc_v4_1;
USE axi_intc_v4_1.axi_intc;
ENTITY design_1_microblaze_0_axi_intc_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
intr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
processor_clk : IN STD_LOGIC;
processor_rst : IN STD_LOGIC;
irq : OUT STD_LOGIC;
processor_ack : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
interrupt_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_microblaze_0_axi_intc_0;
ARCHITECTURE design_1_microblaze_0_axi_intc_0_arch OF design_1_microblaze_0_axi_intc_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_intc IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_NUM_INTR_INPUTS : INTEGER;
C_NUM_SW_INTR : INTEGER;
C_KIND_OF_INTR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_KIND_OF_EDGE : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_KIND_OF_LVL : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_ASYNC_INTR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_NUM_SYNC_FF : INTEGER;
C_IVAR_RESET_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_ENABLE_ASYNC : INTEGER;
C_HAS_IPR : INTEGER;
C_HAS_SIE : INTEGER;
C_HAS_CIE : INTEGER;
C_HAS_IVR : INTEGER;
C_HAS_ILR : INTEGER;
C_IRQ_IS_LEVEL : INTEGER;
C_IRQ_ACTIVE : STD_LOGIC;
C_DISABLE_SYNCHRONIZERS : INTEGER;
C_MB_CLK_NOT_CONNECTED : INTEGER;
C_HAS_FAST : INTEGER;
C_EN_CASCADE_MODE : INTEGER;
C_CASCADE_MASTER : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
intr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
processor_clk : IN STD_LOGIC;
processor_rst : IN STD_LOGIC;
irq : OUT STD_LOGIC;
processor_ack : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
interrupt_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
interrupt_address_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
processor_ack_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT axi_intc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "axi_intc,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_microblaze_0_axi_intc_0_arch : ARCHITECTURE IS "design_1_microblaze_0_axi_intc_0,axi_intc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "design_1_microblaze_0_axi_intc_0,axi_intc,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_intc,x_ipVersion=4.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_intc_inst,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_NUM_INTR_INPUTS=2,C_NUM_SW_INTR=0,C_KIND_OF_INTR=0xfffffffe,C_KIND_OF_EDGE=0xffffffff,C_KIND_OF_LVL=0xffffffff,C_ASYNC_INTR=0xFFFFFFFC,C_NUM_SYNC_FF=2,C_IVAR_RESET_VALUE=0x00000010,C_ENABLE_ASYNC=0,C_HAS_IPR=1,C_HAS_SIE=1,C_HAS_CIE=1,C_HAS_IVR=1,C_HAS_ILR=0,C_IRQ_IS_LEVEL=1,C_IRQ_ACTIVE=0x1,C_DISABLE_SYNCHRONIZERS=1,C_MB_CLK_NOT_CONNECTED=1,C_HAS_FAST=1,C_EN_CASCADE_MODE=0,C_CASCADE_MASTER=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_resetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RREADY";
ATTRIBUTE X_INTERFACE_INFO OF intr: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt_input INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF processor_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 proc_clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF processor_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 proc_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF processor_ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt ACK";
ATTRIBUTE X_INTERFACE_INFO OF interrupt_address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt ADDRESS";
BEGIN
U0 : axi_intc
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_intc_inst",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_NUM_INTR_INPUTS => 2,
C_NUM_SW_INTR => 0,
C_KIND_OF_INTR => X"fffffffe",
C_KIND_OF_EDGE => X"ffffffff",
C_KIND_OF_LVL => X"ffffffff",
C_ASYNC_INTR => X"FFFFFFFC",
C_NUM_SYNC_FF => 2,
C_IVAR_RESET_VALUE => X"00000010",
C_ENABLE_ASYNC => 0,
C_HAS_IPR => 1,
C_HAS_SIE => 1,
C_HAS_CIE => 1,
C_HAS_IVR => 1,
C_HAS_ILR => 0,
C_IRQ_IS_LEVEL => 1,
C_IRQ_ACTIVE => '1',
C_DISABLE_SYNCHRONIZERS => 1,
C_MB_CLK_NOT_CONNECTED => 1,
C_HAS_FAST => 1,
C_EN_CASCADE_MODE => 0,
C_CASCADE_MASTER => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
intr => intr,
processor_clk => processor_clk,
processor_rst => processor_rst,
irq => irq,
processor_ack => processor_ack,
interrupt_address => interrupt_address,
interrupt_address_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_microblaze_0_axi_intc_0_arch;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rmii_tx_fixed.vhd | 4 | 17460 | -----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rmii_tx_fixed.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_GEN1 -- description of generic, if description doesn't fit
-- -- align with first part of description
-- C_GEN2 -- description of generic
--
-- Definition of Ports:
-- Port_name1 -- description of port, indicate source or destination
-- Port_name2 -- description of port
--
------------------------------------------------------------------------------
entity rmii_tx_fixed is
generic (
C_RESET_ACTIVE : std_logic := '0'
);
port (
Tx_speed_100 : in std_logic;
------------------ System Signals -------------------------------
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
------------------ MII <--> RMII --------------------------------
Mac2Rmii_tx_en : in std_logic;
Mac2Rmii_txd : in std_logic_vector(3 downto 0);
Mac2Rmii_tx_er : in std_logic;
Rmii2Mac_tx_clk : out std_logic;
------------------ RMII <--> PHY --------------------------------
Rmii2Phy_txd : out std_logic_vector(1 downto 0);
Rmii2Phy_tx_en : out std_logic
);
end rmii_tx_fixed;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of rmii_tx_fixed is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should be
-- collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a register.
-- If no constants are required, simply state this in a comment below the file
-- section separation comments.
------------------------------------------------------------------------------
-- No Constants
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_CLK_L,
IDLE_CLK_H,
TX100_DIBIT_0_CLK_L,
TX100_DIBIT_1_CLK_H,
TX10_DIBIT_0_CLK_L0,
TX10_DIBIT_0_CLK_L1,
TX10_DIBIT_0_CLK_L2,
TX10_DIBIT_0_CLK_L3,
TX10_DIBIT_0_CLK_L4,
TX10_DIBIT_0_CLK_L5,
TX10_DIBIT_0_CLK_L6,
TX10_DIBIT_0_CLK_L7,
TX10_DIBIT_0_CLK_L8,
TX10_DIBIT_0_CLK_L9,
TX10_DIBIT_1_CLK_H0,
TX10_DIBIT_1_CLK_H1,
TX10_DIBIT_1_CLK_H2,
TX10_DIBIT_1_CLK_H3,
TX10_DIBIT_1_CLK_H4,
TX10_DIBIT_1_CLK_H5,
TX10_DIBIT_1_CLK_H6,
TX10_DIBIT_1_CLK_H7,
TX10_DIBIT_1_CLK_H8,
TX10_DIBIT_1_CLK_H9
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
signal mac2Rmii_tx_en_d : std_logic;
signal mac2Rmii_txd_d : std_logic_vector(3 downto 0);
signal mac2Rmii_tx_er_d : std_logic;
signal tx_in_reg_en : std_logic;
signal txd_dibit : std_logic;
signal txd_error : std_logic;
begin
------------------------------------------------------------------------------
-- TX_IN_REG_PROCESS
------------------------------------------------------------------------------
TX_IN_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
mac2Rmii_tx_en_d <= '0';
mac2Rmii_txd_d <= (others => '0');
mac2Rmii_tx_er_d <= '0';
elsif (tx_in_reg_en = '1') then
mac2Rmii_tx_en_d <= Mac2Rmii_tx_en;
mac2Rmii_txd_d <= Mac2Rmii_txd;
mac2Rmii_tx_er_d <= Mac2Rmii_tx_er;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_OUT_REG_PROCESS
------------------------------------------------------------------------------
TX_OUT_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rmii2Phy_txd(0) <= '0';
Rmii2Phy_txd(1) <= '0';
Rmii2Phy_tx_en <= '0';
elsif (txd_dibit = '0') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(0) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(1) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
elsif (txd_dibit = '1') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(2) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(3) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_SYNC_PROCESS
------------------------------------------------------------------------------
TX_CONTROL_SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_CLK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_NEXT_STATE_PROCESS
------------------------------------------------------------------------------
TX_CONTROL_NEXT_STATE_PROCESS : process (
present_state,
mac2Rmii_tx_er_d,
Tx_speed_100
)
begin
case present_state is
when IDLE_CLK_L =>
next_state <= IDLE_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '0';
txd_error <= '0';
when IDLE_CLK_H =>
if (Tx_speed_100 = '1') then
next_state <= TX100_DIBIT_0_CLK_L;
else
next_state <= TX10_DIBIT_0_CLK_L0;
end if;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX100_DIBIT_0_CLK_L =>
next_state <= TX100_DIBIT_1_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= mac2Rmii_tx_er_d;
when TX100_DIBIT_1_CLK_H =>
next_state <= TX100_DIBIT_0_CLK_L;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= mac2Rmii_tx_er_d;
when TX10_DIBIT_0_CLK_L0 =>
next_state <= TX10_DIBIT_0_CLK_L1;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L1 =>
next_state <= TX10_DIBIT_0_CLK_L2;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L2 =>
next_state <= TX10_DIBIT_0_CLK_L3;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L3 =>
next_state <= TX10_DIBIT_0_CLK_L4;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L4 =>
next_state <= TX10_DIBIT_0_CLK_L5;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L5 =>
next_state <= TX10_DIBIT_0_CLK_L6;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L6 =>
next_state <= TX10_DIBIT_0_CLK_L7;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L7 =>
next_state <= TX10_DIBIT_0_CLK_L8;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L8 =>
next_state <= TX10_DIBIT_0_CLK_L9;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L9 =>
next_state <= TX10_DIBIT_1_CLK_H0;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H0 =>
next_state <= TX10_DIBIT_1_CLK_H1;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H1 =>
next_state <= TX10_DIBIT_1_CLK_H2;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H2 =>
next_state <= TX10_DIBIT_1_CLK_H3;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H3 =>
next_state <= TX10_DIBIT_1_CLK_H4;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H4 =>
next_state <= TX10_DIBIT_1_CLK_H5;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H5 =>
next_state <= TX10_DIBIT_1_CLK_H6;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H6 =>
next_state <= TX10_DIBIT_1_CLK_H7;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H7 =>
next_state <= TX10_DIBIT_1_CLK_H8;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H8 =>
next_state <= TX10_DIBIT_1_CLK_H9;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H9 =>
next_state <= TX10_DIBIT_0_CLK_L0;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
end case;
end process;
end simulation;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/mem_steer.vhd | 4 | 121972 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: mem_steer.vhd
-- Description: This file contains the logic for steering the read data,
-- write data and memory controls to the appropriate memory
-- and data byte lane.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is same as in version v3_01_c - no change in the logic of this
-- module. Deleted the history from version v3_01_c.
-- ~~~~~~
-- NSK 02/12/08 Updated
-- ^^^^^^^^
-- Removed the unused part of code (not supporting C_MAX_MEM_WIDTH = 64): -
-- 1. Deleted the generate block lebelled "WRITE_DATABE_MUX_64_GEN".
-- 2. Deleted the generate block lebelled "READ_DATA_64_GEN".
-- Removed the unused part of code (not supporting C_IPIF_DWIDTH = 64): -
-- 1. Deleted the generate block lebelled "READ_DATA_CE_64_GEN".
-- ~~~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
-- KSB 05/08/08 version v4_00_a
-- 1. Modified for Page mdoe read
-- 2. Modified for 64 Bit memory address align
-- ~~~~~~~~
-- KSB 22/05/10 version v5_00_a
-- 1. Modified for AXI EMC, PSRAM, Byte parity Memory Support
-- 2. Modified for AXI Slave burst interface
-- ~~~~~~~~
-- ~~~~~~
-- SK 25/10/10
-- ^^^^^^^^
-- 1. Added "parity_error_mem" in default condition in "MEM_CEN_STEER_PROCESS".
-- 2. In "PARITY_ACK_SYNC",
-- a.added "MEM2BUS_PARITY_ERR_P" by replacing priority logic
-- b.added "MEM2BUS_RD_ACK_P" by replacing priority logic
-- c.added "ADDR_ALIGN_READ_P" by replacing priority logic for addr_align_read
-- ~~~~~~
-- SK 24/11/10
-- ^^^^^^^^
-- 1. Added "ns_idle" signal to reset the address counter in mem_steer.vhd
-- ~~~~~~~~
-- SK 02/11/11 version v5_02_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
-------------------------------------------------------------------------------
-- vcomponents package of the unisim library is used for the FDS, FDR and FDCE
-- component declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BANKS_MEM -- Number of Memory Banks
-- C_MAX_MEM_WIDTH -- Maximum memory width of all memory banks
-- C_MIN_MEM_WIDTH -- Minimum memory width (set to 8 bits)
-- C_IPIF_DWIDTH -- Width of IPIF data bus
-- C_ADDR_CNTR_WIDTH -- Width of address counter
-- C_GLOBAL_DATAWIDTH_MATCH -- Indicates if datawidth matching is
-- implemented in any memory bank
-- C_GLOBAL_SYNC_MEM -- Indicates if any memory bank is
-- synchronous
--
-- Definition of Ports:
-- EMC signals
-- Bus2IP_Data -- Processor Data Bus
-- Bus2IP_BE -- Processor Byte Enable
-- Bus2IP_Mem_CS -- Memory Channel Chip Select
--
-- Memory state machine signals
-- Write_req_ack -- Memory Write Acknowledge
-- Read_req_ack -- Memory Read Address Acknowledge
-- Read_ack -- Memory Read Acknowledge
-- Read_data_en -- Read Data Enable for read registers
-- Data_strobe -- Data Strobe signal
-- MSM_Mem_CEN -- Memory Chip Enable
-- MSM_Mem_OEN -- Memory Output Enable
-- MSM_Mem_WEN -- Memory Write Enable
-- Mem2Bus_WrAddrAck -- Memory Write Address Acknowledge
-- Mem2Bus_WrAck -- Memory Write Data Acknowledge
-- Mem2Bus_RdAddrAck -- Memory Read Address Acknowledge
-- Mem2Bus_RdAck -- Memory Read Data Acknowledge
-- Mem2Bus_Data -- Memory Read Data
-- Select Param signals
-- Mem_width_bytes -- Memory Device Width in Bytes
-- Synch_mem -- Synchronous Memory Control
-- Two_pipe_delay -- Synchronous pipeline stages
-- Addr counter mux signals
-- Addr_cnt -- Address Count
-- IO Register signals
-- MemSteer_Mem_DQ_I -- Memory Device Data In
-- MemSteer_Mem_DQ_O -- Memory Device Data Out
-- MemSteer_Mem_DQ_T -- Memory Device FPGA Impedance Control
-- MemSteer_Mem_DQ_prty_I -- Memory Device Parity Input
-- MemSteer_Mem_DQ_prty_O -- Memory Device Parity Output
-- MemSteer_Mem_DQ_prty_T -- Memory Device Parity Impedance Control
-- MemSteer_Mem_CEN -- Memory Device Chip Enable (Active Low)
-- MemSteer_Mem_OEN -- Memory Device Output Enable
-- MemSteer_Mem_WEN -- Memory Device Write Enable
-- MemSteer_Mem_QWEN -- Memory Device Qualified Write Enabled
-- MemSteer_Mem_BEN -- Memory Device Byte Enable
-- MemSteer_Mem_CE -- Memory Device Chip Enable (Active High)
-- MemSteer_Mem_RNW -- Memory Device Read/Write
--
-- Clock and reset
-- Clk -- System Clock
-- Rst -- System Reset
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity mem_steer is
generic (
C_NUM_BANKS_MEM : integer;
C_MAX_MEM_WIDTH : integer;
C_MIN_MEM_WIDTH : integer;
C_IPIF_DWIDTH : integer;
C_IPIF_AWIDTH : integer;
C_PARITY_TYPE_MEMORY : integer range 0 to 1;
C_ADDR_CNTR_WIDTH : integer range 1 to 5;
C_GLOBAL_DATAWIDTH_MATCH : integer range 0 to 1;
C_GLOBAL_SYNC_MEM : integer range 0 to 1
);
port (
-- Clock and reset
Clk : in std_logic;
Rst : in std_logic;
-- EMC signals
Bus2IP_Data : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Bus2IP_Mem_CS : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_Burst : in std_logic;
-- Memory state machine signals
Write_req_ack : in std_logic;
Read_req_ack : in std_logic;
Read_ack : in std_logic;
Read_data_en : in std_logic;
-- Data_strobe : in std_logic;09-12-2012
MSM_Mem_CEN : in std_logic;
MSM_Mem_OEN : in std_logic;
MSM_Mem_WEN : in std_logic;
Mem2Bus_WrAddrAck : out std_logic;
Mem2Bus_WrAck : out std_logic;
Mem2Bus_RdAddrAck : out std_logic;
Mem2Bus_RdAck : out std_logic;
Mem2Bus_Data : out std_logic_vector(0 to C_IPIF_DWIDTH -1);
-- Select param signals
Mem_width_bytes : in std_logic_vector(0 to 3);
Synch_mem : in std_logic;
Two_pipe_delay : in std_logic;
single_transaction : in std_logic;
-- Parity logic
parity_error_mem : out std_logic_vector(0 to 1);
Parity_enable : in std_logic;
Parity_type : in std_logic;
Parity_err : out std_logic;
-- Addr counter mux signal
Addr_cnt : in std_logic_vector(0 to
C_ADDR_CNTR_WIDTH-1);
Addr_align : in std_logic;
Addr_align_rd : in std_logic;
-- IO register signals
MemSteer_Mem_DQ_I : in std_logic_vector
(0 to C_MAX_MEM_WIDTH-1);
MemSteer_Mem_DQ_O : out std_logic_vector
(0 to C_MAX_MEM_WIDTH-1);
MemSteer_Mem_DQ_T : out std_logic_vector
(0 to C_MAX_MEM_WIDTH-1);
MemSteer_Mem_DQ_prty_I : in std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_DQ_prty_O : out std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_DQ_prty_T : out std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_CEN : out std_logic_vector
(0 to C_NUM_BANKS_MEM-1);
MemSteer_Mem_OEN : out std_logic_vector
(0 to C_NUM_BANKS_MEM-1);
MemSteer_Mem_WEN : out std_logic;
MemSteer_Mem_QWEN : out std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_BEN : out std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_CE : out std_logic_vector
(0 to C_NUM_BANKS_MEM-1);
MemSteer_Mem_RNW : out std_logic;
Bus2IP_RdReq_emc : in std_logic;
Bus2IP_WrReq_emc : in std_logic;
Write_req_data_ack : in std_logic;
Write_req_addr_ack : in std_logic;
address_strobe_c : in std_logic;
be_strobe_c : in std_logic;
data_strobe_c : in std_logic;
ns_idle : in std_logic;
Linear_flash_rd_data_ack : in std_logic;
Linear_flash_brst_rd_flag : in std_logic;
last_addr : in std_logic; -- stop_oen
stop_oen : in std_logic;
cycle_end: in std_logic;
axi_arsize: in std_logic_vector(2 downto 0);
axi_trans_size_reg : in std_logic_vector(1 downto 0)
);
end entity mem_steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of mem_steer is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
signal mem_cen_cmb : std_logic;
signal mem_oen_cmb : std_logic;
signal read_ack_d : std_logic_vector(0 to 5);
signal read_parity_d : std_logic_vector(0 to 5);
signal addr_align_d : std_logic_vector(0 to 5);
signal addr_align_read : std_logic;
signal write_data : std_logic_vector(0 to C_IPIF_DWIDTH-1);
signal write_data_cmb : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal write_data_parity : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal write_data_parity_cmb : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal read_data : std_logic_vector(0 to C_IPIF_DWIDTH-1);
signal read_parity : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
signal write_data_d1 : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal write_data_d2 : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal write_data_parity_d1 : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal write_data_parity_d2 : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_be_i : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_dq_t_cmb : std_logic_vector(0 to 3);
signal mem_dq_parity_t_cmb : std_logic_vector(0 to 3);
signal addr_cnt_d1 : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_cnt_d2 : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_cnt_d3 : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_cnt_d4 : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_cnt_sel : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal mem_dqt_t_d : std_logic;
signal mem_dqt_t_async : std_logic;
signal mem_dqt_parity_t_d : std_logic;
signal mem_dqt_parity_t_async : std_logic;
signal Read_req_ack_reg : std_logic;
signal readreq_th_reset : std_logic;
signal read_data_ce : std_logic_vector(0 to 7);
signal read_data_en_d : std_logic_vector(0 to 4);
signal read_data_en_sel : std_logic;
signal read_data_cmb : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal read_data_parity : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal read_data_parity_cmb : std_logic_vector(0 to C_IPIF_DWIDTH/8-1) := (OTHERS => '0');
signal read_data_parity_int : std_logic_vector(0 to C_IPIF_DWIDTH/8-1) := (OTHERS => '0');
signal Bus2IP_Mem_CS_del : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal single_par_err : std_logic;
signal single_par_err_int : std_logic;
signal Mem2Bus_RdAck_int : std_logic;
signal Parity_err_int : std_logic;
signal cmb_ored,comp_int : std_logic;
signal arsize_int,arsize_int_e,mem_bytes_int: integer range 0 to 64;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
function "and" ( l : std_logic_vector; r : std_logic )
return std_logic_vector is
variable rex : std_logic_vector(l'range);
begin
rex := (others => r);
return( l and rex );
end function "and";
function calc_parity ( data_in : std_logic_vector (0 to 7);
Parity_type : std_logic
)
return std_logic is
variable parity_out_temp: std_logic;
begin
if Parity_type = '0' then
parity_out_temp := '0';
for j in 0 to 7 loop
parity_out_temp := parity_out_temp XOR data_in(j);
end loop;
elsif Parity_type = '1' then
parity_out_temp := '1';
for j in 0 to 7 loop
parity_out_temp := NOT(parity_out_temp XOR data_in(j));
end loop;
else
parity_out_temp := '0';
end if;
return parity_out_temp;
end function calc_parity;
function check_parity ( data_in : std_logic_vector (0 to 7);
parity_bit : std_logic;
Parity_type : std_logic
)
return std_logic is
variable parity_result : std_logic;
variable parity_out_temp : std_logic;
begin
if Parity_type = '0' then
parity_out_temp := '0';
for j in 0 to 7 loop
parity_out_temp := parity_out_temp XOR data_in(j);
end loop;
elsif Parity_type = '1' then
parity_out_temp := '1';
for j in 0 to 7 loop
parity_out_temp := NOT(parity_out_temp XOR data_in(j));
end loop;
else
parity_out_temp := '0';
end if;
if parity_bit= parity_out_temp then
return '0';
else
return '1';
end if;
end function check_parity;
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
signal addr_cnt_numonyx : std_logic;
--attribute IOB : string;
--attribute IOB of mem_dqt_t_d : signal is "true";
begin -- architecture imp
read_ack_d (5) <= '0';
addr_align_d (5) <= '0';
MemSteer_Mem_BEN <= not mem_be_i;
MemSteer_Mem_RNW <= MSM_Mem_WEN;
MemSteer_Mem_QWEN <= not(mem_be_i and (not MSM_Mem_WEN));
MemSteer_Mem_WEN <= MSM_Mem_WEN;
Mem2Bus_RdAck <= Mem2Bus_RdAck_int;
ADDR_CNT_SYNCH_MODE : process(Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
addr_cnt_numonyx <= '0';
elsif(Linear_flash_brst_rd_flag = '1') then
if(Read_ack = '1') then
addr_cnt_numonyx <= not(addr_cnt_numonyx);
end if;
end if;
end if;
end process ADDR_CNT_SYNCH_MODE;
-------------------------------------------------------------------------------
-- Memory chip enable control generation.
-------------------------------------------------------------------------------
mem_cen_cmb <= MSM_Mem_CEN;
MEM_CEN_SINGLE_BANK_GEN: if C_NUM_BANKS_MEM = 1 generate
begin
MemSteer_Mem_CEN(0) <= mem_cen_cmb; -- 10-12-2012
--CEN_P: process (stop_oen, synch_mem,mem_cen_cmb) is -- 10-12-2012
--begin
-- if(synch_mem = '1') then
-- MemSteer_Mem_CEN(0) <= mem_cen_cmb or stop_oen;
-- else
-- MemSteer_Mem_CEN(0) <= mem_cen_cmb;
-- end if;
--end process CEN_P;
MemSteer_Mem_CE(0) <= not mem_cen_cmb;
parity_error_mem <= "00";
end generate MEM_CEN_SINGLE_BANK_GEN;
-------------------------------------------------------------------------------
-- Generate chip enable signals for multiple memory banks.
-------------------------------------------------------------------------------
MEM_CEN_MULTI_BANK_GEN: if C_NUM_BANKS_MEM > 1 generate
begin
-------------------------------------------------------------------------------
-- Chip enable steer process steers the chip enable to the corresponding memory
-- bank.
-------------------------------------------------------------------------------
MEM_CEN_STEER_PROCESS: process(mem_cen_cmb, Bus2IP_Mem_CS)
begin
MemSteer_Mem_CEN <= (others => '1');
MemSteer_Mem_CE <= (others => '0');
parity_error_mem <= (others => '0');
for i in 0 to C_NUM_BANKS_MEM -1 loop
if(Bus2IP_Mem_CS(i) = '1')then
MemSteer_Mem_CEN(i) <= mem_cen_cmb;
MemSteer_Mem_CE(i) <= not mem_cen_cmb;
parity_error_mem <= conv_std_logic_vector
(i,2);
end if;
end loop;
end process MEM_CEN_STEER_PROCESS;
end generate MEM_CEN_MULTI_BANK_GEN;
-------------------------------------------------------------------------------
-- Memory output enable control generation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 1 -------------------------------
-------------------------------------------------------------------------------
SYNC_MEM_OEN : if C_GLOBAL_SYNC_MEM = 1 generate
signal mem_oen_d : std_logic_vector(0 to 2);
signal mem_oen_sync : std_logic;
begin
mem_oen_d(0) <= MSM_Mem_OEN;
-------------------------------------------------------------------------------
-- FDS primitive is used for output enable pipe generation.
-------------------------------------------------------------------------------
OEN_PIPE_GEN : for i in 0 to 1 generate
begin
OEN_PIPE: FDS
port map (
Q => mem_oen_d(i+1), --[out]
C => Clk, --[in]
D => mem_oen_d(i), --[in]
S => Rst --[in]
);
end generate OEN_PIPE_GEN;
mem_oen_sync <= mem_oen_d(2) and mem_oen_d(1) when (Two_pipe_delay = '1') -- 1/3/2013
--mem_oen_d(2) when (Two_pipe_delay = '1') -- 1/3/2013
else
mem_oen_d(1) and mem_oen_d(0);
mem_oen_cmb <= mem_oen_d(0) when (Synch_mem = '0')
else
mem_oen_sync;
end generate SYNC_MEM_OEN;
-------------------------------------------------------------------------------
-- Generate output enable signals when C_GLOBAL_STNC_MEM = 0.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 0 -------------------------------
-------------------------------------------------------------------------------
ASYNC_MEM_OEN : if C_GLOBAL_SYNC_MEM = 0 generate
begin
mem_oen_cmb <= MSM_Mem_OEN;
end generate ASYNC_MEM_OEN;
-------------------------------------------------------------------------------
-- Generate output enable signals for multiple memory banks.
-------------------------------------------------------------------------------
MEM_OEN_SINGLE_BANK_GEN: if C_NUM_BANKS_MEM = 1 generate
begin
--OEN_P: process (stop_oen, synch_mem,mem_oen_cmb) is -- 10-12-2012
--begin
-- if(synch_mem = '1') then
-- MemSteer_Mem_OEN(0) <= mem_oen_cmb or stop_oen;
-- else
-- MemSteer_Mem_OEN(0) <= mem_oen_cmb;
-- end if;
--end process OEN_P;
MemSteer_Mem_OEN(0) <= mem_oen_cmb; -- 10-12-2012
end generate MEM_OEN_SINGLE_BANK_GEN;
-------------------------------------------------------------------------------
-- Generate output enable signals for multiple memory banks.
-------------------------------------------------------------------------------
MEM_OEN_MULTI_BANK_GEN: if C_NUM_BANKS_MEM > 1 generate
begin
-------------------------------------------------------------------------------
-- Output enable steer process is used to steer the output enable to the
-- corresponding memory bank.
-------------------------------------------------------------------------------
MEM_OEN_STEER_PROCESS: process(mem_oen_cmb, Bus2IP_Mem_CS)
begin
MemSteer_Mem_OEN <= (others => '1');
for i in 0 to C_NUM_BANKS_MEM -1 loop
if(Bus2IP_Mem_CS(i) = '1')then
MemSteer_Mem_OEN(i) <= mem_oen_cmb;
end if;
end loop;
end process MEM_OEN_STEER_PROCESS;
end generate MEM_OEN_MULTI_BANK_GEN;
-------------------------------------------------------------------------------
-- Address and Data ack generation.
-------------------------------------------------------------------------------
--Mem2Bus_WrAddrAck <= Write_req_ack and (Bus2IP_WrReq_emc or single_transaction);
--Mem2Bus_WrAck <= Write_req_ack ;
Mem2Bus_WrAddrAck <= Write_req_addr_ack and
(Bus2IP_WrReq_emc or single_transaction or last_addr);
Mem2Bus_WrAck <= Write_req_data_ack;
Mem2Bus_RdAddrAck <= Read_req_ack;-- and Bus2IP_RdReq_emc;
read_ack_d(0) <= Read_ack;
addr_align_d(0) <= Addr_align_rd;
-------------------------------------------------------------------------------
-- Geneartion of Mem2Bus_RdAck signal when external memory bank has at least
-- one synchronous memory
-------------------------------------------------------------------------------
GSYNC_MEM_RDACK_GEN : if C_GLOBAL_SYNC_MEM = 1 generate
begin
---------------------------------------------------------------------------
-- Read ack pipe generation.
---------------------------------------------------------------------------
RDACK_PIPE_GEN_SYNC : for i in 0 to 3 generate
begin
readreq_th_reset <= ((not Bus2IP_RdReq) and ( not single_transaction))
or Rst;
---------------------------------------------------------------------------
-- FDR primitive is used for read data ack pipe generation.
---------------------------------------------------------------------------
RDACK_PIPE_SYNC: FDR
port map (
Q => read_ack_d(i+1), --[out]
C => Clk, --[in]
D => read_ack_d(i), --[in]
R => readreq_th_reset --[in]
);
end generate RDACK_PIPE_GEN_SYNC;
NO_PARITY_ACK_SYNC : if (C_PARITY_TYPE_MEMORY=0) generate
Parity_err <= '0';
end generate NO_PARITY_ACK_SYNC;
PARITY_ACK_SYNC : if (C_PARITY_TYPE_MEMORY/=0) generate
---------------------------------------------------------------------------
-- ERR ack pipe generation.
---------------------------------------------------------------------------
ERRACK_PIPE_GEN_SYNC : for i in 0 to 3 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for read data ack pipe generation.
---------------------------------------------------------------------------
ERRACK_PIPE_SYNC: FDR
port map (
Q => read_parity_d(i+1), --[out]
C => Clk, --[in]
D => read_parity_d(i), --[in]
R => Rst --[in]
);
end generate ERRACK_PIPE_GEN_SYNC;
--Parity_err_int <= read_parity_d(2) when (Synch_mem = '0') else
-- read_parity_d(3) when (Synch_mem = '1' and
-- Two_pipe_delay = '0') else
-- read_parity_d(4) when (Two_pipe_delay = '1')
--
-- else '0'; --10/25/2010
COMP_INT_S:process (clk)
begin
if clk'event and clk = '1' then
if arsize_int >= mem_bytes_int then
comp_int <= '0';
else
comp_int <= '1';
end if;
end if;
end process COMP_INT_S;
MEM2BUS_PARITY_ERR_P: process(read_parity_d(1),
read_parity_d(2),--10/25/2010
read_parity_d(3),
read_parity_d(4),
Synch_mem,
comp_int,
Two_pipe_delay) is
variable parity_sync_mem_pipe_delay: std_logic_vector(2 downto 0);
begin
parity_sync_mem_pipe_delay := comp_int & Synch_mem & Two_pipe_delay;
case parity_sync_mem_pipe_delay is
when "000" => Parity_err_int <= read_parity_d(2); -- async mem
when "001" => Parity_err_int <= read_parity_d(2); -- async mem
when "010" => Parity_err_int <= read_parity_d(2); -- and read_ack_d(3);--(3); -- sync mem + pipe delay
when "011" => Parity_err_int <= read_parity_d(4); -- sync mem + pipe delay 2
when "100" => Parity_err_int <= read_parity_d(1); -- async mem
when "101" => Parity_err_int <= read_parity_d(1); -- async mem
when "110" => Parity_err_int <= read_parity_d(1); -- and read_ack_d(3);--(3); -- sync mem + pipe delay
when "111" => Parity_err_int <= read_parity_d(3); -- sync mem + pipe delay 2
-- coverage off
when others => Parity_err_int <= '0';
-- coverage on
end case;
end process MEM2BUS_PARITY_ERR_P;
arsize_int_e <= conv_integer(axi_arsize);
PARITY_CALC_32 : if (C_IPIF_DWIDTH = 32) generate
SIZE_SYN_32: process(CLK)
begin
if (clk'event and clk = '1') then
case axi_arsize is
when "000" =>
cmb_ored <= read_data_parity_cmb(0);
when "001" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 1));
when "010" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 3));
when OTHERS =>
cmb_ored <= read_data_parity_cmb(0);
end case;
end if;
end process SIZE_SYN_32;
end generate PARITY_CALC_32;
PARITY_CALC_64 : if (C_IPIF_DWIDTH = 64) generate
SIZE_SYN_64: process(CLK)
begin
if (clk'event and clk = '1') then
case axi_arsize is
when "000" =>
cmb_ored <= read_data_parity_cmb(0);
when "001" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 1));
when "010" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 3));
when "011" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 7));
when OTHERS =>
cmb_ored <= read_data_parity_cmb(0);
end case;
end if;
end process SIZE_SYN_64;
end generate PARITY_CALC_64;
--SIZE_CONV: process(arsize_int)
--begin
-- case arsize_int is
-- when 0 =>
-- arsize_bytes <= 1;
-- when 1 =>
-- arsize_bytes <= 2;
-- when 2 =>
-- arsize_bytes <= 4;
-- when 3 =>
-- arsize_bytes <= 8;
-- when 4 =>
-- arsize_bytes <= 16;
-- when 5 =>
-- arsize_bytes <= 32;
-- when 6 =>
-- arsize_bytes <= 64;
-- when OTHERS =>
-- arsize_bytes <= 1;
-- end case;
--end process SIZE_CONV;
INT_CONV_SIZE: process(arsize_int_e)
begin
case arsize_int_e is
when 0 =>
arsize_int <= 1;
when 1 =>
arsize_int <= 2;
when 2 =>
arsize_int <= 4;
when 3 =>
arsize_int <= 8;
when OTHERS =>
arsize_int <= 1;
end case;
end process INT_CONV_SIZE;
INT_CONV: process(Mem_width_bytes)
begin
case Mem_width_bytes is
when "0001" =>
mem_bytes_int <= 1;
when "0010" =>
mem_bytes_int <= 2;
when "0100" =>
mem_bytes_int <= 4;
when "1000" =>
mem_bytes_int <= 8;
when OTHERS =>
mem_bytes_int <= 1;
end case;
end process INT_CONV;
-------------------------
--process (read_data_parity_cmb)
--begin
-- for i in 0 to arsize_int loop
-- read_data_parity_int(i) <= read_data_parity_cmb(i);
-- end loop;
--end process;
process (Clk)
begin
if (clk'event and clk = '1') then
if (Rst = '1') then
single_par_err <= '0';
else
if (arsize_int >= mem_bytes_int) then
single_par_err <= or_reduce(read_data_parity_cmb) and single_transaction;
else
--single_par_err <= or_reduce(read_data_parity_cmb(0 to arsize_int)) and single_transaction;
single_par_err <= cmb_ored;
end if;
end if;
end if;
end process;
process (Clk)
begin
if (clk'event and clk = '1') then
if (Rst = '1') then
single_par_err_int <= '0';
else
single_par_err_int <= Mem2Bus_RdAck_int and single_par_err;
end if;
end if;
end process;
Parity_err <= Parity_err_int or single_par_err_int;
---------------------------
--read_parity_d(0) <= -- or_reduce(read_data_parity_cmb) and Read_ack;
-- (or_reduce(read_data_parity_cmb)) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq) -- read_ack_d(3))
-- when Two_pipe_delay = '0'
-- else
-- (or_reduce(read_data_parity_cmb) and read_ack_d(4));
--read_parity_d(0) <=
-- (or_reduce(read_data_parity_cmb)) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq) when Two_pipe_delay = '0' else (or_reduce(read_data_parity_cmb) and read_ack_d(4))
-- when arsize_int >= mem_bytes_int else
-- ((cmb_ored) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq)) when Two_pipe_delay = '0' else ((cmb_ored) and read_ack_d(4));
read_parity_d(0) <=
(or_reduce(read_data_parity_cmb)) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq) when arsize_int >= mem_bytes_int else ((cmb_ored) and (or_reduce(read_data_ce)) and (Read_ack))
when Two_pipe_delay = '0' else
(or_reduce(read_data_parity_cmb) and read_ack_d(4)) when arsize_int >= mem_bytes_int else ((cmb_ored) and read_ack_d(4));
--process (read_data_ce,
-- read_data_parity_cmb,
-- Bus2IP_RdReq,
-- read_ack_d,
-- Two_pipe_delay,
-- read_data_parity_int
-- )
--begin
-- if (arsize_int >= mem_bytes_int) then
-- if (Two_pipe_delay = '0') then
-- read_parity_d(0) <= (or_reduce(read_data_parity_cmb)) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq); -- read_ack_d(3))
-- else
-- read_parity_d(0) <= (or_reduce(read_data_parity_cmb) and read_ack_d(4));
-- end if;
-- else
-- if (Two_pipe_delay = '0') then
-- read_parity_d(0) <= (cmb_ored) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq); -- read_ack_d(3))
-- else
-- read_parity_d(0) <= (cmb_ored) and read_ack_d(4);
-- end if;
-- end if;
--end process;
end generate PARITY_ACK_SYNC;
--Mem2Bus_RdAck <= -- read_ack_d(2) when (Synch_mem = '0') else
-- read_ack_d(3) when (Synch_mem = '1' and
-- Two_pipe_delay = '0') else
-- read_ack_d(4) when (Two_pipe_delay = '1')
-- else '0'; -- 10/25/2010
MEM2BUS_RD_ACK_P: process(read_ack_d(2), -- 10/25/2010
read_ack_d(3),
read_ack_d(4),
Synch_mem,
addr_cnt_numonyx,
Read_ack,
Linear_flash_brst_rd_flag,
Two_pipe_delay) is
variable sync_mem_pipe_delay: std_logic_vector(1 downto 0);
begin
sync_mem_pipe_delay := Synch_mem & Two_pipe_delay;
case sync_mem_pipe_delay is
when "00" => if (Linear_flash_brst_rd_flag = '0') then
Mem2Bus_RdAck_int <= read_ack_d(2);
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
when "01" => if (Linear_flash_brst_rd_flag = '0') then
Mem2Bus_RdAck_int <= read_ack_d(2);
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
when "10" => if (Linear_flash_brst_rd_flag = '0') then
Mem2Bus_RdAck_int <= read_ack_d(3);
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
when "11" => if (Linear_flash_brst_rd_flag = '0') then
Mem2Bus_RdAck_int <= read_ack_d(4);
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
-- coverage off
when others => Mem2Bus_RdAck_int <= '0';
-- coverage on
end case;
end process MEM2BUS_RD_ACK_P;
ADDR_ALIGN_PIPE_GEN : for i in 0 to 3 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for Address align pipe generation.
---------------------------------------------------------------------------
ALIGN_PIPE: FDR
port map (
Q => addr_align_d(i+1), --[out]
C => Clk, --[in]
D => addr_align_d(i), --[in]
R => Rst --[in]
);
end generate ADDR_ALIGN_PIPE_GEN;
--addr_align_read <= addr_align_d(0)when Synch_mem = '0'
-- else
-- addr_align_d(1) when Synch_mem = '1' and Two_pipe_delay = '0'
-- else
-- addr_align_d(2);--10/25/2010
ADDR_ALIGN_READ_P: process(addr_align_d(0), -- 10/25/2010
addr_align_d(1),
addr_align_d(2),
Synch_mem,
Two_pipe_delay) is
variable addr_align_syn_pipe_dly: std_logic_vector(1 downto 0);
begin
addr_align_syn_pipe_dly := Synch_mem & Two_pipe_delay;
case addr_align_syn_pipe_dly is
when "00" => addr_align_read <= addr_align_d(0);
when "01" => addr_align_read <= addr_align_d(0);
when "10" => addr_align_read <= addr_align_d(1);
when "11" => addr_align_read <= addr_align_d(2);
-- coverage off
when others => addr_align_read <=addr_align_d(2);
-- coverage on
end case;
end process ADDR_ALIGN_READ_P;
------------------------------
end generate GSYNC_MEM_RDACK_GEN;
-------------------------------------------------------------------------------
-- Geneartion of Mem2Bus_RdAck signal when external memory bank has only
-- asynchronous memory
-------------------------------------------------------------------------------
ASYNC_MEM_RDACK_GEN : if (C_GLOBAL_SYNC_MEM = 0) generate
begin
---------------------------------------------------------------------------
-- Read ack pipe generation.
---------------------------------------------------------------------------
RDACK_PIPE_GEN_ASYNC : for i in 0 to 1 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for read data ack pipe generation.
---------------------------------------------------------------------------
readreq_th_reset <= ((not Bus2IP_RdReq) and ( not single_transaction))
or Rst;
RDACK_PIPE_ASYNC: FDR
port map (
Q => read_ack_d(i+1), --[out]
C => Clk, --[in]
D => read_ack_d(i), --[in]
R => readreq_th_reset --[in]
);
end generate RDACK_PIPE_GEN_ASYNC;
NO_ASYN_PARITY_ACK_SYNC : if (C_PARITY_TYPE_MEMORY=0) generate
Parity_err <= '0';
end generate NO_ASYN_PARITY_ACK_SYNC;
PARITY_ACK : if (C_PARITY_TYPE_MEMORY/=0) generate
---------------------------------------------------------------------------
-- ERR ack pipe generation.
---------------------------------------------------------------------------
ERRACK_PIPE_GEN_ASYNC : for i in 0 to 1 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for read data ack pipe generation.
---------------------------------------------------------------------------
ERRACK_PIPE_ASYNC: FDR
port map (
Q => read_parity_d(i+1), --[out]
C => Clk, --[in]
D => read_parity_d(i), --[in]
R => Rst --[in]
);
end generate ERRACK_PIPE_GEN_ASYNC;
Parity_err <= read_parity_d(2);
end generate PARITY_ACK;
-- Mem2Bus_RdAck <= read_ack_d(2) when (Linear_flash_brst_rd_flag = '0') else (addr_cnt_numonyx and Read_ack) ;
ASYNC_MEM_MEM2BUS_RDACK_P: process(read_ack_d(2),
Linear_flash_brst_rd_flag,
cycle_end,
Read_ack,
axi_trans_size_reg,
addr_cnt_numonyx )is
begin
if(Linear_flash_brst_rd_flag = '0')then
Mem2Bus_RdAck_int <= read_ack_d(2);
else
if(axi_trans_size_reg(1) = '0')then -- half word access
Mem2Bus_RdAck_int <= cycle_end and Read_ack;
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
end if;
end process ASYNC_MEM_MEM2BUS_RDACK_P;
---------------------------------------------------------------------------
-- ADDR ALLIGN pipe generation.
---------------------------------------------------------------------------
AALIGN_PIPE_GEN : for i in 0 to 1 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for Address align pipe generation.
---------------------------------------------------------------------------
AALIGN_PIPE: FDR
port map (
Q => addr_align_d(i+1), --[out]
C => Clk, --[in]
D => addr_align_d(i), --[in]
R => Rst --[in]
);
end generate AALIGN_PIPE_GEN;
addr_align_read <= addr_align_d(0);
end generate ASYNC_MEM_RDACK_GEN;
-------------------------------------------------------------------------------
-- Store the data coming from bus, as address ack and data ack is issued early,
-- and to make burst appear as continuous on memory side.
-------------------------------------------------------------------------------
DATA_STORE_GEN: for i in 0 to C_IPIF_DWIDTH - 1 generate
begin
-------------------------------------------------------------------------------
-- FDCE primitive is used for latching Bus2IP_Data when Data_strobe = 1.
-------------------------------------------------------------------------------
WRDATA_REG: FDRE
port map (
Q => write_data(i), --[out]
C => Clk, --[in]
CE => data_strobe_c,--Data_strobe, --[in]
D => Bus2IP_Data(i), --[in]
R => Rst --[in]
);
end generate DATA_STORE_GEN;
-------------------------------------------------------------------------------
-- When one of the memory bank has different data width than OPB/MCH data
-- width, data steering logic is required.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_DATAWIDTH_MATCH = 1 ------------------------
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 1 generate
begin
-------------------------------------------------------------------------------
-- Write data path
-------------------------------------------------------------------------------
-- Write data mux is used to multiplex write_data out to memories. This will
-- vary on whether the max memory data width is 8, 16, 32 or 64. Separate
-- generate statements are used for each of them. If the memory is synchronous,
-- the BEs assert at the same time. However, the write data goes out one or
-- two clocks later (depending on Two_pipe_delay). Therefore, separate
-- processes are used for the write data and byte enables.
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_64_GEN: if (C_MAX_MEM_WIDTH=64 and C_IPIF_DWIDTH=64) generate
begin
-------------------------------------------------------------------------------
-- Write data path for 64 bit maximum memory width. Write data mux process is
-- used to multiplex the write_data depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_DATA_MUX_PROCESS_64: process(Mem_width_bytes, Addr_cnt, write_data)
begin
write_data_cmb <= (others => '0');
write_data_parity_cmb <= (others => '0');
case Mem_width_bytes is
when "0001" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MIN_MEM_WIDTH-1) <=
write_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "0010" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 2*C_MIN_MEM_WIDTH-1) <=
write_data(i*2*C_MIN_MEM_WIDTH to
i*2*C_MIN_MEM_WIDTH + 2*C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "0100" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 4*C_MIN_MEM_WIDTH-1) <=
write_data(i*4*C_MIN_MEM_WIDTH to
i*4*C_MIN_MEM_WIDTH + 4*C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "1000" =>
if Addr_cnt = conv_std_logic_vector(0, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MAX_MEM_WIDTH-1) <=
write_data(0 to C_MAX_MEM_WIDTH-1);
end if;
when others =>
write_data_cmb <= (others => '0');
end case;
end process WRITE_DATA_MUX_PROCESS_64;
-------------------------------------------------------------------------------
-- Write data path for 64 bit maximum memory width. Write byte enable mux
-- process is used to multiplex the byte enable depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_BE_MUX_PROCESS_64: process(Mem_width_bytes, Addr_cnt, Bus2IP_BE)
begin
mem_be_i <= (others => '0');
case Mem_width_bytes is
when "0001" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8 + C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "0010" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 2*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*2*C_MIN_MEM_WIDTH/8 to
i*2*C_MIN_MEM_WIDTH/8 + 2*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "0100" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 4*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*4*C_MIN_MEM_WIDTH/8 to
i*4*C_MIN_MEM_WIDTH/8 + 4*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "1000" =>
if Addr_cnt = conv_std_logic_vector(0, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH-1) <=
Bus2IP_BE(0 to C_MIN_MEM_WIDTH-1);
end if;
when others =>
mem_be_i <= (others => '0');
end case;
end process WRITE_BE_MUX_PROCESS_64;
WRITE_PARITY_EN_64_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
--
-- WRITE_PARITY_MUX_PROCESS_64: process(Parity_type,
-- Addr_cnt,
-- write_data)
-- begin
--
-- write_data_parity_cmb <= (others => '0');
--
-- for i in 0 to 7 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb (i)<=
-- calc_parity(write_data(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
--
--
-- end process WRITE_PARITY_MUX_PROCESS_64;
WRITE_DATA_PARITY_PROCESS_64: process(Mem_width_bytes,
Addr_cnt,
write_data_parity_cmb,
Parity_type,
write_data,
write_data_cmb
) is
begin
write_data_parity_cmb <= (others => '0');
--------------
case Mem_width_bytes is
when "0001" => -- 8 bit memory (need only one Parity Enable bit to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(0) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
--end loop;
write_data_parity_cmb(0) <= calc_parity(write_data_cmb(0 to C_MIN_MEM_WIDTH-1),Parity_type);
when "0010" => -- 16 bit memory (need only two Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
--end loop;
for i in 0 to 1 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
when "0100" => -- 32 bit memory (need four Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
--end loop;
for i in 0 to 3 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
when "1000" => -- 64 bit memory (need eight Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
--end loop;
for i in 0 to 7 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
-- coverage off
when others =>
write_data_parity_cmb <= (others => '0');
-- coverage on
end case;
--------------
end process WRITE_DATA_PARITY_PROCESS_64;
end generate WRITE_PARITY_EN_64_MAX;
end generate WRITE_DATABE_MUX_64_GEN;
-------------------------------------------------------------------------------
-- Write data path
-------------------------------------------------------------------------------
-- Write data mux is used to multiplex write_data out to memories. This will
-- vary on whether the max memory data width is 8, 16, 32 or 64. Separate
-- generate statements are used for each of them. If the memory is synchronous,
-- the BEs assert at the same time. However, the write data goes out one or
-- two clocks later (depending on Two_pipe_delay). Therefore, separate
-- processes are used for the write data and byte enables.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Write data byte enable generation for 32 bit.
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_32_GEN: if (C_MAX_MEM_WIDTH=32) generate
begin
-------------------------------------------------------------------------------
-- Write data path for 32 bit maximum memory width. Write data mux process is
-- used to multiplex the write_data depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_DATA_MUX_PROCESS_32: process(Mem_width_bytes, Addr_cnt, write_data)
begin
write_data_cmb <= (others => '0');
case Mem_width_bytes(1 to 3) is
when "001" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MIN_MEM_WIDTH-1) <=
write_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "010" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 2*C_MIN_MEM_WIDTH-1) <=
write_data(i*2*C_MIN_MEM_WIDTH to
i*2*C_MIN_MEM_WIDTH + 2*C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "100" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 4*C_MIN_MEM_WIDTH-1) <=
write_data(i*4*C_MIN_MEM_WIDTH to
i*4*C_MIN_MEM_WIDTH + 4*C_MIN_MEM_WIDTH-1);
end if;
end loop;
when others =>
write_data_cmb <= (others => '0');
end case;
end process WRITE_DATA_MUX_PROCESS_32;
-------------------------------------------------------------------------------
-- Write data path for 32 Bit maximum memory width. Write byte enable mux
-- process is used to multiplex the byte enable depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_BE_MUX_PROCESS_32: process(Mem_width_bytes, Addr_cnt, Bus2IP_BE)
begin
mem_be_i <= (others => '0');
case Mem_width_bytes(1 to 3) is
when "001" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8 + C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "010" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 2*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*2*C_MIN_MEM_WIDTH/8 to
i*2*C_MIN_MEM_WIDTH/8 + 2*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "100" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 4*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*4*C_MIN_MEM_WIDTH/8 to
i*4*C_MIN_MEM_WIDTH/8 + 4*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when others =>
mem_be_i <= (others => '0');
end case;
end process WRITE_BE_MUX_PROCESS_32;
-----------------------------------**--
WRITE_PARITY_EN_32_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
--
-- WRITE_PARITY_MUX_PROCESS_32: process(Parity_type, Addr_cnt, write_data)
-- begin
--
-- write_data_parity_cmb <= (others => '0');
-- ----------
-- for i in 0 to 3 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb (i)<=
-- calc_parity(write_data(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
-- ----------
-- end process WRITE_PARITY_MUX_PROCESS_32;
-- WRITE_DATA_PARITY_PROCESS_32: process(Mem_width_bytes,
-- Addr_cnt,
-- write_data_parity_cmb,
-- Parity_type
-- ) is
-- begin
-- write_data_parity_cmb <= (others => '0');
-- --------------
-- case Mem_width_bytes(1 to 3) is
-- when "001" => -- 8 bit memory (need only one Parity Enable bit to active)
-- for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(0) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
--
-- when "010" => -- 16 bit memory (need only two Parity Enable bits to active)
-- for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
-- when "100" => -- 32 bit memory (need four Parity Enable bits to active)
-- for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
-- -- coverage off
-- when others =>
-- write_data_parity_cmb <= (others => '0');
-- -- coverage on
-- end case;
-- --------------
-- end process WRITE_DATA_PARITY_PROCESS_32;
WRITE_DATA_PARITY_PROCESS_32: process(Mem_width_bytes,
Addr_cnt,
write_data_cmb,
Parity_type,
write_data
) is
-----
begin
-----
write_data_parity_cmb <= (others => '0');
--------------
case Mem_width_bytes(1 to 3) is
------------
when "001" => -- 8 bit memory (need only one Parity Enable bit to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- for j in 0 to 1 loop
-- write_data_parity_cmb(0) <=
-- calc_parity(write_data((i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
-- end loop;
--end if;
--end loop;
write_data_parity_cmb(0) <= calc_parity(write_data_cmb(0 to C_MIN_MEM_WIDTH-1),Parity_type);
------------
when "010" => -- 16 bit memory (need only two Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- for j in 0 to 1 loop
-- write_data_parity_cmb(j) <=
-- calc_parity(write_data((i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
--
-- end loop;
-- end if;
--end loop;
for i in 0 to 1 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
------------
when "100" => -- 32 bit memory (need four Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- --for j in 0 to 3 loop
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data((i*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
--
-- --end loop;
-- end if;
--end loop;
for i in 0 to 3 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
------------
-- coverage off
when others =>
write_data_parity_cmb <= (others => '0');
-- coverage on
------------
end case;
--------------
end process WRITE_DATA_PARITY_PROCESS_32;
--------------------------------------
end generate WRITE_PARITY_EN_32_MAX;
-----------------------------------**--
end generate WRITE_DATABE_MUX_32_GEN;
-------------------------------------------------------------------------------
-- Write data byte enable generation for 16 bit.
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_16_GEN: if C_MAX_MEM_WIDTH=16 generate
begin
-------------------------------------------------------------------------------
-- Write data path for 16 bit maximum memory width. Write data mux process is
-- used to multiplex the write_data depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_DATA_MUX_PROCESS_16: process(Mem_width_bytes, Addr_cnt, write_data)
begin
write_data_cmb <= (others => '0');
--------------
case Mem_width_bytes(2 to 3) is
when "01" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MIN_MEM_WIDTH-1) <=
write_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "10" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 2*C_MIN_MEM_WIDTH-1) <=
write_data(i*2*C_MIN_MEM_WIDTH to
i*2*C_MIN_MEM_WIDTH + 2*C_MIN_MEM_WIDTH-1);
end if;
end loop;
-- coverage off
when others =>
write_data_cmb <= (others => '0');
-- coverage on
end case;
--------------
end process WRITE_DATA_MUX_PROCESS_16;
-------------------------------------------------------------------------------
-- Write data path for 16 bit maximum memory width. Write byte enable mux
-- process is used to multiplex the byte enable depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_BE_MUX_PROCESS_16: process(Mem_width_bytes, Addr_cnt, Bus2IP_BE)
begin
mem_be_i <= (others => '0');
case Mem_width_bytes(2 to 3) is
when "01" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8 + C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "10" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 2*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*2*C_MIN_MEM_WIDTH/8 to
i*2*C_MIN_MEM_WIDTH/8 + 2*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
-- coverage off
when others =>
mem_be_i <= (others => '0');
-- coverage on
end case;
end process WRITE_BE_MUX_PROCESS_16;
WRITE_PARITY_EN_16_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
-- WRITE_PARITY_MUX_PROCESS_16: process(Parity_type, Addr_cnt, write_data)
-- begin
--
-- write_data_parity_cmb <= (others => '0');
-- --------------------
-- for i in 0 to 1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb (i)<=
-- calc_parity(write_data(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
---- ------------------
-- end process WRITE_PARITY_MUX_PROCESS_16;
WRITE_DATA_PARITY_PROCESS_16: process(Mem_width_bytes,
Addr_cnt,
write_data_cmb,
Parity_type,
write_data
) is
begin
write_data_parity_cmb <= (others => '0');
--------------
case Mem_width_bytes(2 to 3) is
------------
when "01" => -- 8 bit memory (need only one Parity Enable bit to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
--if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
--for j in 0 to 1 loop
write_data_parity_cmb(0) <=
--calc_parity(write_data_cmb((i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
calc_parity(write_data_cmb(0 to C_MIN_MEM_WIDTH-1),Parity_type);
--end loop;
--end if;
--end loop;
------------
when "10" => -- 16 bit memory (need only two Parity Enable bits to active)
for i in 0 to 1 loop
--if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
--for j in 0 to 1 loop
--write_data_parity_cmb(j) <=
--calc_parity(write_data_cmb((i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
--end loop;
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
--end if;
end loop;
------------
-- coverage off
when others =>
write_data_parity_cmb <= (others => '0');
-- coverage on
------------
end case;
--------------
end process WRITE_DATA_PARITY_PROCESS_16;
-- for j in 0 to 1 loop
-- write_data_parity_cmb(j)<=
-- calc_parity(write_data(i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end loop;
end generate WRITE_PARITY_EN_16_MAX;
end generate WRITE_DATABE_MUX_16_GEN;
-------------------------------------------------------------------------------
-- Write data byte enable generation for 8 bit.
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_8_GEN: if C_MAX_MEM_WIDTH=8 generate
begin
-------------------------------------------------------------------------------
-- Write data path for 8 bit maximum memory width. Write data mux process is
-- used to multiplex the write_data depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_DATA_MUX_PROCESS_8: process(Mem_width_bytes, Addr_cnt, write_data)
begin
write_data_cmb <= (others => '0');
--------------
case Mem_width_bytes(3) is
when '1' =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MIN_MEM_WIDTH-1) <=
write_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1);
end if;
end loop;
-- coverage off
when others =>
write_data_cmb <= (others => '0');
-- coverage on
end case;
---------------
end process WRITE_DATA_MUX_PROCESS_8;
-------------------------------------------------------------------------------
-- Write data path for 8 bit maximum memory width. Write byte enable mux
-- process is used to multiplex the byte enable depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_BE_MUX_PROCESS_8: process(Mem_width_bytes, Addr_cnt, Bus2IP_BE)
begin
mem_be_i <= (others => '0');
--------------------------
case Mem_width_bytes(3) is
when '1' =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8 + C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
-- coverage off
when others =>
mem_be_i <= (others => '0');
-- coverage on
end case;
--------------------------
end process WRITE_BE_MUX_PROCESS_8;
WRITE_PARITY_EN_8_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
WRITE_PARITY_MUX_PROCESS_8: process(Parity_type,
Addr_cnt,
write_data_parity_cmb,
write_data_cmb
) is
begin
write_data_parity_cmb <= (others => '0');
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
--if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_parity_cmb (0) <=
calc_parity(write_data_cmb(0 to C_MIN_MEM_WIDTH-1),Parity_type);--(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
--end if;
--end loop;
end process WRITE_PARITY_MUX_PROCESS_8;
end generate WRITE_PARITY_EN_8_MAX;
end generate WRITE_DATABE_MUX_8_GEN;
end generate WRITE_DATABE_MUX_GEN;
-------------------------------------------------------------------------------
-- When all the memory banks has same data width as OPB/MCH data width,
-- data steering logic is not required.
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_DATAWIDTH_MATCH = 0 ------------------------
-------------------------------------------------------------------------------
WRITE_DATABE_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 0 generate
begin
write_data_cmb <= write_data(0 to C_MAX_MEM_WIDTH-1);
mem_be_i <= Bus2IP_BE(0 to C_MAX_MEM_WIDTH/8-1);
---------**--
WRITE_PARITY_EN : if (C_PARITY_TYPE_MEMORY/=0) generate
begin
WRITE_PARITY: process(Parity_type,
write_data_cmb
) is
begin
for i in 0 to C_MAX_MEM_WIDTH/8 -1 loop
write_data_parity_cmb (i)<= calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
end process WRITE_PARITY;
end generate WRITE_PARITY_EN;
---------**--
end generate WRITE_DATABE_GEN;
-------------------------------------------------------------------------------
-- Write data generation for synchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 1 -------------------------------
-------------------------------------------------------------------------------
SYNC_MEM_WRITE_DATA : if C_GLOBAL_SYNC_MEM = 1 generate
begin
-------------------------------------------------------------------------------
-- Write data pipeline process is used to pipeline write_data_cmb.
-------------------------------------------------------------------------------
WRITE_DATA_PIPE_PROCESS : process(Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
write_data_d1 <= (others => '0');
write_data_d2 <= (others => '0');
Read_req_ack_reg <= '0';
else
write_data_d1 <= write_data_cmb;
write_data_d2 <= write_data_d1;
Read_req_ack_reg <= Read_req_ack;
end if;
end if;
end process WRITE_DATA_PIPE_PROCESS;
-- PARITY_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 0 generate
-- begin
---------------------------------------------------------------------------
-- Write Parity pipeline process is used to pipeline write_data_cmb
---------------------------------------------------------------------------
WRITE_PARITY_PIPE_PROCESS : process(Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
write_data_parity_d1 <= (others => '0');
write_data_parity_d2 <= (others => '0');
else
write_data_parity_d1 <= write_data_parity_cmb;
write_data_parity_d2 <= write_data_parity_d1;
end if;
end if;
end process WRITE_PARITY_PIPE_PROCESS;
-- end generate PARITY_GEN;
-------------------------------------------------------------------------------
-- Write data process is used to multiplex the write data on the memory
-- depending on the type of memory.
-------------------------------------------------------------------------------
WRITE_DATA_PROCESS: process(write_data_cmb, Synch_mem, Two_pipe_delay,
write_data_parity_cmb, write_data_parity_d2,
write_data_parity_d1, write_data_d1,
write_data_d2)
begin
if Synch_mem = '1' then
if Two_pipe_delay = '1' then
MemSteer_Mem_DQ_O <= write_data_d2;
MemSteer_Mem_DQ_prty_O <= write_data_parity_d2;
else
MemSteer_Mem_DQ_O <= write_data_d1;
MemSteer_Mem_DQ_prty_O <= write_data_parity_d1;
end if;
else
MemSteer_Mem_DQ_O <= write_data_cmb;
MemSteer_Mem_DQ_prty_O <= write_data_parity_cmb;
end if;
end process WRITE_DATA_PROCESS;
end generate SYNC_MEM_WRITE_DATA;
-------------------------------------------------------------------------------
-- Memory write data generation for asynchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 0 -------------------------------
-------------------------------------------------------------------------------
ASYNC_MEM_WRITE_DATA : if C_GLOBAL_SYNC_MEM = 0 generate
begin
MemSteer_Mem_DQ_O <= write_data_cmb;
MemSteer_Mem_DQ_prty_O <= write_data_parity_cmb;
end generate ASYNC_MEM_WRITE_DATA;
-------------------------------------------------------------------------------
-- Memory data bus high impedance buffer control.
-------------------------------------------------------------------------------
mem_dq_t_cmb(0) <= MSM_Mem_WEN;
mem_dqt_t_async <= MSM_Mem_WEN and mem_dqt_t_d;
ASYNC_PARITY_MEM_WRITE: if C_PARITY_TYPE_MEMORY /= 0 generate
begin
mem_dq_parity_t_cmb(0) <= MSM_Mem_WEN;
mem_dqt_parity_t_async <= MSM_Mem_WEN and mem_dqt_parity_t_d;
end generate ASYNC_PARITY_MEM_WRITE;
-------------------------------------------------------------------------------
-- Asynchronous memory DQT process is used to generate impedance control
-- signal.
-------------------------------------------------------------------------------
MEM_DQT_D_ASYNC_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
mem_dqt_t_d <= '1';
mem_dqt_parity_t_d <= '1';
else
mem_dqt_t_d <= MSM_Mem_WEN;
mem_dqt_parity_t_d <= MSM_Mem_WEN;
end if;
end if;
end process MEM_DQT_D_ASYNC_PROCESS;
-------------------------------------------------------------------------------
-- Impedance generation for synchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 1 -------------------------------
-------------------------------------------------------------------------------
SYNC_MEM_DQT : if C_GLOBAL_SYNC_MEM = 1 generate
begin
REG_DQT_GEN : for i in 0 to 2 generate
begin
-------------------------------------------------------------------------------
-- FDS primitive is used for mem_dq_t_cmb pipe generation.
-------------------------------------------------------------------------------
DQT_REG: FDS
port map (
Q => mem_dq_t_cmb(i+1), --[out]
C => Clk, --[in]
D => mem_dq_t_cmb(i), --[in]
S => Rst --[in]
);
end generate REG_DQT_GEN;
-------------------------------------------------------------------------------
-- Memory dqt process is used to multiplex the impeadance control signal on to
-- the memory depending on the type of memory.
-------------------------------------------------------------------------------
MEM_DQT_PROCESS_SYNC: process(Synch_mem, Two_pipe_delay, mem_dq_t_cmb,
mem_dqt_t_async)
begin
MemSteer_Mem_DQ_T <= (others => '1');
for i in 0 to C_MAX_MEM_WIDTH-1 loop
if(Synch_mem = '1')then
if(Two_pipe_delay = '1')then
MemSteer_Mem_DQ_T(i) <= mem_dq_t_cmb(2);
else
MemSteer_Mem_DQ_T(i) <= mem_dq_t_cmb(1);
end if;
else
MemSteer_Mem_DQ_T(i) <= mem_dqt_t_async;
end if;
end loop;
end process MEM_DQT_PROCESS_SYNC;
SYNC_PARITY_MEM_WRITE_DQT: if C_PARITY_TYPE_MEMORY /= 0 generate
begin
REG_DQT_PARITY_GEN : for i in 0 to 2 generate
begin
-------------------------------------------------------------------------------
-- FDS primitive is used for mem_dq_t_cmb pipe generation.
-------------------------------------------------------------------------------
DQT_REG: FDS
port map (
Q => mem_dq_parity_t_cmb(i+1), --[out]
C => Clk, --[in]
D => mem_dq_parity_t_cmb(i), --[in]
S => Rst --[in]
);
end generate REG_DQT_PARITY_GEN;
-------------------------------------------------------------------------------
-- Memory dqt process is used to multiplex the impeadance control signal on to
-- the memory depending on the type of memory.
-------------------------------------------------------------------------------
MEM_DQT_PARITY_PROCESS_SYNC: process(Synch_mem,
Two_pipe_delay,
mem_dq_parity_t_cmb,
mem_dqt_parity_t_async
) is
begin
MemSteer_Mem_DQ_prty_T <= (others => '1');
for i in 0 to C_MAX_MEM_WIDTH/8-1 loop
if(Synch_mem = '1')then
if(Two_pipe_delay = '1')then
MemSteer_Mem_DQ_prty_T(i) <= mem_dq_parity_t_cmb(2);
else
MemSteer_Mem_DQ_prty_T(i) <= mem_dq_parity_t_cmb(1);
end if;
else
MemSteer_Mem_DQ_prty_T(i) <= mem_dqt_parity_t_async;
end if;
end loop;
end process MEM_DQT_PARITY_PROCESS_SYNC;
end generate SYNC_PARITY_MEM_WRITE_DQT;
end generate SYNC_MEM_DQT;
-------------------------------------------------------------------------------
-- Impedance generation for asynchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 0 -------------------------------
-------------------------------------------------------------------------------
ASYNC_MEM_DQT : if C_GLOBAL_SYNC_MEM = 0 generate
begin
-------------------------------------------------------------------------------
-- Memory dqt process is used to generate impeadance control signal on to
-- the memory.
-------------------------------------------------------------------------------
MEM_DQT_PROCESS_ASYNC: process(mem_dqt_t_async)
begin
for i in 0 to C_MAX_MEM_WIDTH-1 loop
MemSteer_Mem_DQ_T(i) <= mem_dqt_t_async;
end loop;
end process MEM_DQT_PROCESS_ASYNC;
-------------------------------------------------------------------------------
-- Memory PARITY dqt process is used to generate impeadance control signal on
-- to the memory.
-------------------------------------------------------------------------------
ASYNC_PARITY_MEM_WRITE_DQT: if C_PARITY_TYPE_MEMORY /= 0 generate
begin
MEM_PARITY_DQT_PROCESS_ASYNC: process(mem_dqt_parity_t_async)
begin
for i in 0 to C_MAX_MEM_WIDTH/8-1 loop
MemSteer_Mem_DQ_prty_T(i) <= mem_dqt_parity_t_async;
end loop;
end process MEM_PARITY_DQT_PROCESS_ASYNC;
end generate ASYNC_PARITY_MEM_WRITE_DQT;
end generate ASYNC_MEM_DQT;
-------------------------------------------------------------------------------
-- Read data path.
-- Read data and byte enable generation.
-------------------------------------------------------------------------------
RDDATA_GEN: for j in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH - 1 generate
begin
RDDATA_BYTE_GEN:for i in 0 to C_MIN_MEM_WIDTH - 1 generate
begin
-------------------------------------------------------------------------------
-- FDCE primitive is used for latching read_data when read_data_ce = 1.
-------------------------------------------------------------------------------
RDDATA_REG: FDRE
port map (
Q => Mem2Bus_Data(C_MIN_MEM_WIDTH*j+i), --[out]
C => Clk, --[in]
CE => read_data_ce(j), --[in]
D => read_data(C_MIN_MEM_WIDTH*j+i), --[in]
R => RST --[in]
);
end generate RDDATA_BYTE_GEN;
end generate RDDATA_GEN;
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_DATAWIDTH_MATCH = 0 ------------------------
-------------------------------------------------------------------------------
RDDATA_PATH_GEN : if C_GLOBAL_DATAWIDTH_MATCH = 0 generate
begin
read_data <= MemSteer_Mem_DQ_I;
read_data_ce <= (others=>'1');
READ_PARITY_EN : if (C_PARITY_TYPE_MEMORY/=0) generate
begin
READ_PARITY: process(MemSteer_Mem_DQ_I,
Parity_type,
read_ack_d,
MemSteer_Mem_DQ_prty_I
) is
begin
-- default assignment
--read_parity <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to C_MAX_MEM_WIDTH/8 -1 loop
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY;
end generate READ_PARITY_EN;
end generate RDDATA_PATH_GEN;
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_DATAWIDTH_MATCH = 1 ------------------------
-------------------------------------------------------------------------------
RDDATA_PATH_MUX_GEN : if C_GLOBAL_DATAWIDTH_MATCH = 1 generate
begin
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 1 -------------------------------
-------------------------------------------------------------------------------
SYNC_ADDR_CNT_GEN: if C_GLOBAL_SYNC_MEM = 1 generate
begin
-------------------------------------------------------------------------------
-- Address count pipeline process is used to pipeline address count.
-------------------------------------------------------------------------------
ADDR_CNT_PIPE_PROCESS_SYN: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
addr_cnt_d1 <= (others => '0');
addr_cnt_d2 <= (others => '0');
addr_cnt_d3 <= (others => '0');
addr_cnt_d4 <= (others => '0');
else
if Bus2IP_RdReq = '1' or single_transaction = '1' then
addr_cnt_d1 <= Addr_cnt;
addr_cnt_d2 <= addr_cnt_d1;
addr_cnt_d3 <= addr_cnt_d2;
addr_cnt_d4 <= addr_cnt_d3;
else
addr_cnt_d1 <= (others => '0');
addr_cnt_d2 <= (others => '0');
addr_cnt_d3 <= (others => '0');
addr_cnt_d4 <= (others => '0');
end if;
end if;
end if;
end process ADDR_CNT_PIPE_PROCESS_SYN;
-------------------------------------------------------------------------------
-- Synchonous address counter process is used to multiplex the address counter
-- select signal depending on the type of memory.
-------------------------------------------------------------------------------
SYNC_ADDR_CNT_PROCESS: process(ns_idle,
Synch_mem,
Two_pipe_delay,
addr_cnt_d2,
addr_cnt_d3,
addr_cnt_d4)
begin
if (ns_idle='0') then
if Synch_mem = '1' then
if Two_pipe_delay = '1' then
addr_cnt_sel <= addr_cnt_d4;
else
addr_cnt_sel <= addr_cnt_d3;
end if;
else
addr_cnt_sel <= addr_cnt_d2;
end if;
else
addr_cnt_sel <= (others => '0');
end if;
end process SYNC_ADDR_CNT_PROCESS;
---------------------------- Read Data Enable Logic ---------------------------
read_data_en_d(0) <= Read_data_en;
RDDATA_EN_GEN_SYNC: for i in 0 to 3 generate
begin
-------------------------------------------------------------------------------
-- FDR primitive is used for read_data_en_d pipe generation.
-------------------------------------------------------------------------------
RDDATA_EN_REG_SYNC: FDR
port map (
Q => read_data_en_d(i+1), --[out]
C => Clk, --[in]
D => read_data_en_d(i), --[in]
R => Rst --[in]
);
end generate RDDATA_EN_GEN_SYNC;
-------------------------------------------------------------------------------
-- Read data enable select process is used to multiplex the read data enable
-- depending on the type of memory.
-------------------------------------------------------------------------------
READ_DATA_EN_SEL_PROCESS: process(read_data_en_d, Synch_mem,
Two_pipe_delay)
begin
if Synch_mem = '1' then
if Two_pipe_delay = '1' then
read_data_en_sel <= read_data_en_d(3);
else
read_data_en_sel <= read_data_en_d(2);
end if;
else
read_data_en_sel <= read_data_en_d(1);
end if;
end process READ_DATA_EN_SEL_PROCESS;
end generate SYNC_ADDR_CNT_GEN;
-------------------------------------------------------------------------------
-- Address count select generation for asynchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 0 -------------------------------
-------------------------------------------------------------------------------
ASYNC_ADDR_CNT_GEN: if C_GLOBAL_SYNC_MEM = 0 generate
begin
-------------------------------------------------------------------------------
-- Address count pipeline process is used to pipeline address count.
-------------------------------------------------------------------------------
ADDR_CNT_PIPE_PROCESS_ASYNC: process(Clk)
begin
if Clk'event and Clk = '1' then
if ((Rst = '1') or (ns_idle='1')) then
addr_cnt_d1 <= (others => '0');
addr_cnt_d2 <= (others => '0');
else
addr_cnt_d1 <= Addr_cnt;
addr_cnt_d2 <= addr_cnt_d1;
end if;
end if;
end process ADDR_CNT_PIPE_PROCESS_ASYNC;
addr_cnt_sel <= addr_cnt_d2;
---------------------------- Read Data Enable Logic ---------------------------
read_data_en_d(0) <= Read_data_en;
read_data_en_sel <= read_data_en_d(1);
RDDATA_EN_GEN_ASYNC: for i in 0 to 3 generate
begin
-------------------------------------------------------------------------------
-- FDR primitive is used for read_data_en_d pipe generation.
-------------------------------------------------------------------------------
RDDATA_EN_REG_ASYNC: FDR
port map (
Q => read_data_en_d(i+1), --[out]
C => Clk, --[in]
D => read_data_en_d(i), --[in]
R => Rst --[in]
);
end generate RDDATA_EN_GEN_ASYNC;
end generate ASYNC_ADDR_CNT_GEN;
-------------------------------------------------------------------------------
-- Read Data CE generation For 64 Bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_CE_64_GEN: if C_IPIF_DWIDTH = 64 generate
begin
--signal test :std_logic_vector(0 downto 7);
--test <= read_data_ce(conv_integer(addr_cnt_sel)*4+i);
-------------------------------------------------------------------------------
-- Read data CE process is used to generate read data chip enable for 64 Bit
-- DWidth.
-------------------------------------------------------------------------------
READ_DATA_CE_PROCESS_64: process(read_data_en_sel,
addr_cnt_sel,
single_transaction,
Bus2IP_RdReq,
Mem_width_bytes,
Linear_flash_brst_rd_flag,
Linear_flash_rd_data_ack,
addr_cnt_numonyx
) is
begin
read_data_ce <= (others => '0');
if Bus2IP_RdReq = '1' or single_transaction = '1' then
case Mem_width_bytes is
when "0001" =>
read_data_ce(conv_integer(addr_cnt_sel))
<= read_data_en_sel;
when "0010" =>
for i in 0 to 1 loop
--read_data_ce(conv_integer(addr_cnt_sel)*2+i)
-- <= read_data_en_sel;
if(Linear_flash_brst_rd_flag = '0') then
read_data_ce(conv_integer(addr_cnt_sel)*2+i)
<= read_data_en_sel;
else
read_data_ce(conv_integer(addr_cnt_numonyx)*2+i)
<= Linear_flash_rd_data_ack;--read_data_en_sel;
end if;
end loop;
when "0100" =>
for i in 0 to 3 loop
read_data_ce(conv_integer(addr_cnt_sel)*4+i)
<= read_data_en_sel;
end loop;
when "1000" =>
for i in 0 to 7 loop
read_data_ce(i) <= read_data_en_sel;
end loop;
-- coverage off
when others =>
read_data_ce <= (others => '0');
-- coverage on
end case;
end if;
end process READ_DATA_CE_PROCESS_64;
end generate READ_DATA_CE_64_GEN;
-------------------------------------------------------------------------------
-- Read data CE generation For 32 Bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_CE_32_GEN: if C_IPIF_DWIDTH = 32 generate
begin
-------------------------------------------------------------------------------
-- Read data CE process is used to generate read data chip enable for 32 Bit
-- DWidth.
-------------------------------------------------------------------------------
READ_DATA_CE_PROCESS_32: process(Mem_width_bytes,
addr_cnt_sel,
addr_cnt_numonyx,
read_data_en_sel,
Linear_flash_brst_rd_flag,
Linear_flash_rd_data_ack
) is
begin
read_data_ce <= (others => '0');
case Mem_width_bytes is
when "0001" =>
read_data_ce(conv_integer(addr_cnt_sel))
<= read_data_en_sel ; -- and not(Linear_flash_brst_rd_flag)) or (Linear_flash_brst_rd_flag and Linear_flash_rd_data_ack);
when "0010" =>
for i in 0 to 1 loop
if(Linear_flash_brst_rd_flag = '0') then
read_data_ce(conv_integer(addr_cnt_sel)*2+i)
<= read_data_en_sel;
else
read_data_ce(conv_integer(addr_cnt_numonyx)*2+i)
<= Linear_flash_rd_data_ack;--read_data_en_sel;
end if;
end loop;
when "0100" =>
for i in 0 to 3 loop
read_data_ce(i) <= read_data_en_sel ;--and not(Linear_flash_brst_rd_flag)) or (Linear_flash_brst_rd_flag and Linear_flash_rd_data_ack);--read_data_en_sel;
end loop;
-- coverage off
when others =>
read_data_ce <= (others => '0');
-- coverage on
end case;
end process READ_DATA_CE_PROCESS_32;
end generate READ_DATA_CE_32_GEN;
-------------------------------------------------------------------------------
-- Read Data Path For 64 Bit Maximum Memory Width.
-------------------------------------------------------------------------------
READ_DATA_64_GEN: if (C_MAX_MEM_WIDTH=64 and C_IPIF_DWIDTH=64) generate
begin
-------------------------------------------------------------------------------
-- Read data process is used to generate read data for 64 Bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_PROCESS_64_64: process(Mem_width_bytes, MemSteer_Mem_DQ_I )
begin
read_data <= (others => '0');
case Mem_width_bytes is
when "0001" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH+C_MIN_MEM_WIDTH-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH-1);
end loop;
when "0010" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
read_data(i*C_MIN_MEM_WIDTH*2 to
i*C_MIN_MEM_WIDTH*2+C_MIN_MEM_WIDTH*2-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*2-1);
end loop;
when "0100" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
read_data(i*C_MIN_MEM_WIDTH*4 to
i*C_MIN_MEM_WIDTH*4+C_MIN_MEM_WIDTH*4-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*4-1);
end loop;
when "1000" =>
read_data <= MemSteer_Mem_DQ_I;
-- coverage off
when others =>
read_data <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_64_64;
READ_PARITY_EN_64_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
READ_PRTY_PROCESS_64: process(Mem_width_bytes, MemSteer_Mem_DQ_prty_I)
begin
read_parity <= (others => '0');
case Mem_width_bytes is
when "0001" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_parity(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8+C_MIN_MEM_WIDTH/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH/8-1);
end loop;
when "0010" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
read_parity(i*C_MIN_MEM_WIDTH*2/8 to
i*C_MIN_MEM_WIDTH*2/8+C_MIN_MEM_WIDTH*2/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*2/8-1);
end loop;
when "0100" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
read_parity(i*C_MIN_MEM_WIDTH*4/8 to
i*C_MIN_MEM_WIDTH*4/8+C_MIN_MEM_WIDTH*4/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*4/8-1);
end loop;
when "1000" =>
read_parity <= MemSteer_Mem_DQ_prty_I;
when others =>
read_parity <= (others => '0');
end case;
end process READ_PRTY_PROCESS_64;
READ_PARITY_MUX_PROCESS_64: process(MemSteer_Mem_DQ_I,
Parity_type,
Bus2IP_BE,
read_ack_d,
MemSteer_Mem_DQ_prty_I)
begin
read_data_parity_cmb <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to 7 loop
--if Bus2IP_BE(i) = '1' then
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I
(i*C_MIN_MEM_WIDTH to i*C_MIN_MEM_WIDTH
+ C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
--end if;
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY_MUX_PROCESS_64;
end generate READ_PARITY_EN_64_MAX;
end generate READ_DATA_64_GEN;
-------------------------------------------------------------------------------
-- Read data path For 32 bit maximum memory width.
-------------------------------------------------------------------------------
READ_DATA_32_GEN: if (C_MAX_MEM_WIDTH=32) generate
begin
-------------------------------------------------------------------------------
-- Read data process is used to generate read data for 32 bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_PROCESS_32: process(Mem_width_bytes, MemSteer_Mem_DQ_I)
begin
read_data <= (others => '0');
case Mem_width_bytes(1 to 3) is
when "001" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH+C_MIN_MEM_WIDTH-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH-1);
end loop;
when "010" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2)-1 loop
read_data(i*C_MIN_MEM_WIDTH*2 to
i*C_MIN_MEM_WIDTH*2+C_MIN_MEM_WIDTH*2-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*2-1);
end loop;
when "100" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4)-1 loop
read_data(i*C_MIN_MEM_WIDTH*4 to
i*C_MIN_MEM_WIDTH*4+C_MIN_MEM_WIDTH*4-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*4-1);
end loop;
-- coverage off
when others =>
read_data <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_32;
READ_PARITY_EN_32_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
READ_PRTY_PROCESS_32: process(Mem_width_bytes, MemSteer_Mem_DQ_prty_I)
begin
read_parity <= (others => '0');
case Mem_width_bytes(1 to 3) is
when "001" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_parity(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8+C_MIN_MEM_WIDTH/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH/8-1);
end loop;
when "010" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2)-1 loop
read_parity(i*C_MIN_MEM_WIDTH*2/8 to
i*C_MIN_MEM_WIDTH*2/8+C_MIN_MEM_WIDTH*2/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*2/8-1);
end loop;
when "100" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4)-1 loop
read_parity(i*C_MIN_MEM_WIDTH*4/8 to
i*C_MIN_MEM_WIDTH*4/8+C_MIN_MEM_WIDTH*4/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*4/8-1);
end loop;
-- coverage off
when others =>
read_parity <= (others => '0');
-- coverage on
end case;
end process READ_PRTY_PROCESS_32;
READ_PARITY_MUX_PROCESS_32: process(MemSteer_Mem_DQ_I,
Parity_type,
MemSteer_Mem_DQ_prty_I,
read_ack_d,
Bus2IP_BE)
begin
read_data_parity_cmb <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to 3 loop
--if Bus2IP_BE(i) = '1' then
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I
(i*C_MIN_MEM_WIDTH to i*C_MIN_MEM_WIDTH
+ C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
--end if;
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY_MUX_PROCESS_32;
end generate READ_PARITY_EN_32_MAX;
end generate READ_DATA_32_GEN;
-------------------------------------------------------------------------------
-- Read data path for 16 bit maximum memory width.
-------------------------------------------------------------------------------
READ_DATA_16_GEN: if C_MAX_MEM_WIDTH=16 generate
begin
-------------------------------------------------------------------------------
-- Read data process is used to generate read data for 16 bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_PROCESS_16: process(Mem_width_bytes, MemSteer_Mem_DQ_I)
begin
read_data <= (others => '0');
case Mem_width_bytes(2 to 3) is
when "01" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH+C_MIN_MEM_WIDTH-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH-1);
end loop;
when "10" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2)-1 loop
read_data(i*C_MIN_MEM_WIDTH*2 to
i*C_MIN_MEM_WIDTH*2+C_MIN_MEM_WIDTH*2-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*2-1);
end loop;
-- coverage off
when others =>
read_data <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_16;
READ_PARITY_EN_16_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
READ_DATA_PROCESS_16: process(Mem_width_bytes, MemSteer_Mem_DQ_prty_I)
begin
read_parity <= (others => '0');
case Mem_width_bytes(2 to 3) is
when "01" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_parity(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8+C_MIN_MEM_WIDTH/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH/8-1);
end loop;
when "10" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2)-1 loop
read_parity(i*C_MIN_MEM_WIDTH*2/8 to
i*C_MIN_MEM_WIDTH*2/8+C_MIN_MEM_WIDTH*2/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*2/8-1);
end loop;
-- coverage off
when others =>
read_parity <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_16;
READ_PARITY_MUX_PROCESS_16: process(MemSteer_Mem_DQ_I,
Parity_type,
MemSteer_Mem_DQ_prty_I,
read_ack_d,
Bus2IP_BE)
begin
read_data_parity_cmb <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to 1 loop
--if Bus2IP_BE(i) = '1' then
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I(i*C_MIN_MEM_WIDTH to i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
--end if;
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY_MUX_PROCESS_16;
end generate READ_PARITY_EN_16_MAX;
end generate READ_DATA_16_GEN;
-------------------------------------------------------------------------------
-- Read data path for 8 bit maximum memory width.
-------------------------------------------------------------------------------
READ_DATA_8_GEN: if C_MAX_MEM_WIDTH=8 generate
begin
-------------------------------------------------------------------------------
-- Read data process is used to generate read data for 8 bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_PROCESS_8: process(Mem_width_bytes,
MemSteer_Mem_DQ_I)
begin
read_data <= (others => '0');
case Mem_width_bytes(3) is
when '1' =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH+C_MIN_MEM_WIDTH-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH-1);
end loop;
-- coverage off
when others =>
read_data <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_8;
READ_PARITY_EN_8_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
READ_DATA_PROCESS_8: process(Mem_width_bytes, MemSteer_Mem_DQ_prty_I)
begin
read_parity <= (others => '0');
case Mem_width_bytes(3) is
when '1' =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_parity(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8+C_MIN_MEM_WIDTH/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH/8-1);
end loop;
when others =>
read_parity <= (others => '0');
end case;
end process READ_DATA_PROCESS_8;
READ_PARITY_MUX_PROCESS_8: process(MemSteer_Mem_DQ_I,
Parity_type,
Bus2IP_BE,
read_ack_d,
MemSteer_Mem_DQ_prty_I)
begin
read_data_parity_cmb <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to 0 loop
--if Bus2IP_BE(i) = '1' then
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I(i*C_MIN_MEM_WIDTH to i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
--end if;
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY_MUX_PROCESS_8;
end generate READ_PARITY_EN_8_MAX;
end generate READ_DATA_8_GEN;
end generate RDDATA_PATH_MUX_GEN;
end imp;
-------------------------------------------------------------------------------
-- End of file mem_steer.vhd.
-------------------------------------------------------------------------------
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/mdio_if.vhd | 4 | 23285 | -------------------------------------------------------------------------------
-- mdio_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : mdio_if.vhd
-- Version : v2.0
-- Description : This entity provides the interface between the physical layer
-- management control, and the host interface through the MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- MDIO_Clk -- 2.5Mhz clock
-- MDIO_en -- MDIO enable
-- MDIO_OP -- MDIO OP code
-- MDIO_Req -- MDIO transmission request
-- MDIO_PHY_AD -- The physical layer address
-- MDIO_REG_AD -- The individual register address
-- MDIO_WR_DATA -- The data to be written on MDIO
-- MDIO_RD_DATA -- The data read from MDIO
-- PHY_MDIO_I -- MDIO Tri-state input from PHY
-- PHY_MDIO_O -- MDIO Tri-state output to PHY
-- PHY_MDIO_T -- MDIO Tri-state control
-- PHY_MDC -- 2.5Mhz communication clock to PHY
-- MDIO_done -- RX FIFO read ack
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity mdio_if is
port (
Clk : in std_logic; -- System Clock
Rst : in std_logic; -- System Reset
MDIO_Clk : in std_logic; -- 2.5Mhz clock
MDIO_en : in std_logic; -- MDIO enable
MDIO_OP : in std_logic; -- MDIO OP code
MDIO_Req : in std_logic; -- MDIO transmission request
MDIO_PHY_AD : in std_logic_vector(4 downto 0);
-- The physical layer address
MDIO_REG_AD : in std_logic_vector(4 downto 0);
-- The individual register address
MDIO_WR_DATA : in std_logic_vector(15 downto 0);
-- The data to be written on MDIO
MDIO_RD_DATA : out std_logic_vector(15 downto 0);
-- The data read from MDIO
PHY_MDIO_I : in std_logic; -- MDIO Tri-state input from PHY
PHY_MDIO_O : out std_logic; -- MDIO Tri-state output to PHY
PHY_MDIO_T : out std_logic; -- MDIO Tri-state control
PHY_MDC : out std_logic; -- 2.5Mhz communication clock
MDIO_done : out std_logic -- MDIO tranfer done indicator
);
end mdio_if;
architecture imp of mdio_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type mdio_state_type is (IDLE, PREAMBLE, ST1, ST2, OP1, OP2, TA1, TA2,
PHY_ADDR, REG_ADDR, WRITE, READ, DONE);
signal mdio_state, next_state : mdio_state_type;
signal mdio_xfer_done : std_logic; -- pulse to inidcate end of activity
signal mdio_idle : std_logic; -- internal READY signal
signal rd_data_en : std_logic_vector(15 downto 0); -- decoded write
-- MDIO_en for RD_DATA
signal mdio_en_reg : std_logic; -- MDIO_en signal latched at start of
-- transmission
signal mdio_o_cmb : std_logic; -- rising edge version of MDIO_OUT
signal mdio_t_comb : std_logic; -- combinatorial term to produce
-- MDIO_TRISTATE
signal mdio_clk_reg : std_logic; -- registering MDIO_Clk to use it as a
-- clock MDIO_en
signal mdio_in_reg1 : std_logic; -- compensate in pipeline delay caused
-- by using MDC as a clock MDIO_en
signal mdio_in_reg2 : std_logic; -- compensate in pipeline delay caused by
-- using MDC as a clock MDIO_en
signal clk_cnt : integer range 0 to 32; -- Clk counter
signal ld_cnt_data_cmb : integer range 0 to 32; -- Counter load comb
signal ld_cnt_data_reg : integer range 0 to 32; -- Counter load reg
signal ld_cnt_en_cmb : std_logic; -- Counter load enable
signal clk_cnt_en : std_logic; -- Counter enable
signal mdc_falling : std_logic; -- MDC falling edge
signal mdc_rising : std_logic; -- MDC rising edge
signal ld_cnt_en_reg : std_logic; -- Counter load enable reg
begin
----------------------------------------------------------------------------
-- PROCESS : INPUT_REG_CLK
----------------------------------------------------------------------------
-- Registering PHY_MDIO_I and MDC signals w.r.t SAXI clock.
----------------------------------------------------------------------------
INPUT_REG_CLK: process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_clk_reg <= '0';
mdio_in_reg1 <= '0';
mdio_in_reg2 <= '0';
else
mdio_clk_reg <= MDIO_Clk;
mdio_in_reg1 <= PHY_MDIO_I;
mdio_in_reg2 <= mdio_in_reg1;
end if;
end if;
end process INPUT_REG_CLK;
-- Falling edge and rising edge generation of MDC clock
mdc_falling <= not MDIO_Clk and mdio_clk_reg;
mdc_rising <= MDIO_Clk and not mdio_clk_reg;
-- Enable MDC only when MDIO interface is enabled.
PHY_MDC <= MDIO_Clk; -- making the MDC clk contineous
--PHY_MDC <= MDIO_Clk and mdio_en_reg;
-- Informs MDIO interface about the MDIO transfer complete.
MDIO_done <= mdio_xfer_done;
----------------------------------------------------------------------------
-- PROCESS : REG_MDIO_en
----------------------------------------------------------------------------
-- Latch MDIO_en bit on falling edge of MDC and when MDIO master is IDLE.
-- MDIO Master will complete the existing transfer even if MDIO interface
-- is disable in middle of the transaction.
----------------------------------------------------------------------------
REG_MDIO_en : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_reg <= '0';
elsif mdc_falling='1' then
if mdio_idle = '1' then
mdio_en_reg <= MDIO_en;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_T_REG
----------------------------------------------------------------------------
-- The mdio_t_comb signal is driven high only for read operation starting
-- from the Turn arround state.
-- It is driven on falling clock edge to match up with PHY_MDIO_O
----------------------------------------------------------------------------
PHY_MDIO_T_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_T <= '1';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_T <= mdio_t_comb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_O_REG
----------------------------------------------------------------------------
-- Generating PHY_MDIO_O output singnal on falling edge of MDC
----------------------------------------------------------------------------
PHY_MDIO_O_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_O <= '0';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_O <= mdio_o_cmb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_IDLE_REG
----------------------------------------------------------------------------
-- The mdio_idle signal is used to indicate no activity on the MDIO.
-- Set at reset amd at the end of transmission.
-- Rst at start of transmission as long as device is MDIO_end
----------------------------------------------------------------------------
MDIO_IDLE_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_idle <= '1';
elsif (mdc_rising='1') then -- rising edge of MDC
if (mdio_xfer_done = '1') then
mdio_idle <= '1';
elsif (MDIO_Req = '1' and mdio_en_reg = '1') then
mdio_idle <= '0';
end if;
end if;
end if;
end process ;
----------------------------------------------------------------------------
-- PROCESS : MDIO_CAPTURE_DATA
----------------------------------------------------------------------------
-- This process captures registered PHY_MDIO_i input on rising edge of the
-- MDC clock. The rd_data_en signal is generated in MDIO State machine for
-- respective captured bit.
----------------------------------------------------------------------------
MDIO_CAPTURE_DATA : for i in 15 downto 0 generate
MDIO_DATA_IN : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
MDIO_RD_DATA(i) <= '0';
elsif (mdc_rising='1') then -- rising edge of MDC
if(rd_data_en(i) = '1') then
MDIO_RD_DATA(i) <= mdio_in_reg2;
end if;
end if;
end if;
end process MDIO_DATA_IN;
end generate;
----------------------------------------------------------------------------
-- PROCESS : MDIO_DOWN_COUNTER
----------------------------------------------------------------------------
-- This counter is used in Preamble and PHY_ADDR and REG_ADDR state.
-- This counter is loaded for the required values for each above states.
----------------------------------------------------------------------------
MDIO_DOWN_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= 0;
elsif (mdc_rising='1') then -- falling edge of MDC
if (ld_cnt_en_reg = '1') then -- Load counter with load data
clk_cnt <= ld_cnt_data_reg;
elsif (clk_cnt_en='1') then -- Enable Down Counter
clk_cnt <= clk_cnt - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_NEXT_STATE_GEN
----------------------------------------------------------------------------
-- MDIO next state register process
----------------------------------------------------------------------------
MDIO_NEXT_STATE_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
mdio_state <= IDLE;
elsif (mdc_rising='1') then
mdio_state <= next_state;
end if;
end if;
end process MDIO_NEXT_STATE_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_COMB_REG_GEN
----------------------------------------------------------------------------
-- Combinational signal register process
----------------------------------------------------------------------------
MDIO_COMB_REG_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
ld_cnt_data_reg <= 0;
ld_cnt_en_reg <= '0';
else
ld_cnt_data_reg <= ld_cnt_data_cmb;
ld_cnt_en_reg <= ld_cnt_en_cmb;
end if;
end if;
end process MDIO_COMB_REG_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_STATE_COMB
----------------------------------------------------------------------------
-- This process generates mdio_o_cmb signal in command and Write phase as
-- per the required MDIO protocol. This process also generate mdio_t_comb
-- tristate signal and rd_data_en to capture the respective bit in Read
-- operation.
----------------------------------------------------------------------------
MDIO_STATE_COMB : process (mdio_state, mdio_idle, clk_cnt, MDIO_OP,
MDIO_PHY_AD, MDIO_REG_AD, MDIO_WR_DATA)
begin
-- state machine defaults
mdio_o_cmb <= '1';
rd_data_en <= "0000000000000000";
mdio_xfer_done <= '0';
ld_cnt_en_cmb <= '0';
clk_cnt_en <= '0';
mdio_t_comb <= '0';
next_state <= mdio_state;
ld_cnt_data_cmb <= 0;
case mdio_state is
when IDLE =>
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
ld_cnt_en_cmb <= '1';
-- leave IDLE state when new mdio request is received.
if mdio_idle = '0' then
-- Load counter for 32-bit preamble
ld_cnt_data_cmb <= 31;
next_state <= PREAMBLE;
end if;
when PREAMBLE =>
clk_cnt_en <= '1';
-- Move to ST1 after 32-bit preamble.
if clk_cnt = 0 then
next_state <= ST1;
clk_cnt_en <= '0';
end if;
when ST1 => -- Start Code-1
mdio_o_cmb <= '0';
next_state <= ST2;
when ST2 => -- Start Code-2
mdio_o_cmb <= '1';
next_state <= OP1;
when OP1 => -- Opcode-1
next_state <= OP2;
if MDIO_OP='1' then
mdio_o_cmb <= '1';
else
mdio_o_cmb <= '0';
end if;
when OP2 => -- Opcode-2
next_state <= PHY_ADDR;
-- Load counter for 5-bit PHYaddress transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
if MDIO_OP='1' then
mdio_o_cmb <= '0';
else
mdio_o_cmb <= '1';
end if;
when PHY_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_PHY_AD(clk_cnt);
-- Send 5-bit PHY device address
if clk_cnt=0 then
next_state <= REG_ADDR;
-- Load counter for 5-bit REG address transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
end if;
when REG_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_REG_AD(clk_cnt);
-- Send 5-bit PHY Register address
if clk_cnt=0 then
next_state <= TA1;
clk_cnt_en <= '0';
end if;
when TA1 => -- Turn Around Time-1
mdio_o_cmb <= '1';
next_state <= TA2;
-- For Read operation generate high impedence on
-- MDIO bus
if MDIO_OP='1' then
mdio_t_comb <= '1';
else
mdio_t_comb <= '0';
end if;
when TA2 => -- Turn Around Time-2
mdio_o_cmb <= '0';
-- Load the down counter for 16 bit data transfer
ld_cnt_data_cmb <= 15;
ld_cnt_en_cmb <= '1';
-- Move to Write state if opcode is '0'
if MDIO_OP='0' then
next_state <= WRITE;
mdio_t_comb <= '0';
else
next_state <= READ;
mdio_t_comb <= '1';
end if;
when WRITE => -- MDIO DATA Write
clk_cnt_en <= '1';
-- Send 16-bit Write Data on the MDIO data line
mdio_o_cmb <= MDIO_WR_DATA(clk_cnt);
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when READ => -- MDIO DATA Read
clk_cnt_en <= '1';
mdio_t_comb <= '1';
-- Generate read data enable for respective bit
rd_data_en(clk_cnt) <= '1';
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when DONE => -- MDIO Transfer Done
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
next_state <= IDLE;
-- Mdio trasnfer complete
mdio_xfer_done <= '1';
-- coverage off
when others =>
next_state <= IDLE;
-- coverage on
end case;
end process MDIO_STATE_COMB;
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/mdio_if.vhd | 4 | 23285 | -------------------------------------------------------------------------------
-- mdio_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : mdio_if.vhd
-- Version : v2.0
-- Description : This entity provides the interface between the physical layer
-- management control, and the host interface through the MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- MDIO_Clk -- 2.5Mhz clock
-- MDIO_en -- MDIO enable
-- MDIO_OP -- MDIO OP code
-- MDIO_Req -- MDIO transmission request
-- MDIO_PHY_AD -- The physical layer address
-- MDIO_REG_AD -- The individual register address
-- MDIO_WR_DATA -- The data to be written on MDIO
-- MDIO_RD_DATA -- The data read from MDIO
-- PHY_MDIO_I -- MDIO Tri-state input from PHY
-- PHY_MDIO_O -- MDIO Tri-state output to PHY
-- PHY_MDIO_T -- MDIO Tri-state control
-- PHY_MDC -- 2.5Mhz communication clock to PHY
-- MDIO_done -- RX FIFO read ack
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity mdio_if is
port (
Clk : in std_logic; -- System Clock
Rst : in std_logic; -- System Reset
MDIO_Clk : in std_logic; -- 2.5Mhz clock
MDIO_en : in std_logic; -- MDIO enable
MDIO_OP : in std_logic; -- MDIO OP code
MDIO_Req : in std_logic; -- MDIO transmission request
MDIO_PHY_AD : in std_logic_vector(4 downto 0);
-- The physical layer address
MDIO_REG_AD : in std_logic_vector(4 downto 0);
-- The individual register address
MDIO_WR_DATA : in std_logic_vector(15 downto 0);
-- The data to be written on MDIO
MDIO_RD_DATA : out std_logic_vector(15 downto 0);
-- The data read from MDIO
PHY_MDIO_I : in std_logic; -- MDIO Tri-state input from PHY
PHY_MDIO_O : out std_logic; -- MDIO Tri-state output to PHY
PHY_MDIO_T : out std_logic; -- MDIO Tri-state control
PHY_MDC : out std_logic; -- 2.5Mhz communication clock
MDIO_done : out std_logic -- MDIO tranfer done indicator
);
end mdio_if;
architecture imp of mdio_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type mdio_state_type is (IDLE, PREAMBLE, ST1, ST2, OP1, OP2, TA1, TA2,
PHY_ADDR, REG_ADDR, WRITE, READ, DONE);
signal mdio_state, next_state : mdio_state_type;
signal mdio_xfer_done : std_logic; -- pulse to inidcate end of activity
signal mdio_idle : std_logic; -- internal READY signal
signal rd_data_en : std_logic_vector(15 downto 0); -- decoded write
-- MDIO_en for RD_DATA
signal mdio_en_reg : std_logic; -- MDIO_en signal latched at start of
-- transmission
signal mdio_o_cmb : std_logic; -- rising edge version of MDIO_OUT
signal mdio_t_comb : std_logic; -- combinatorial term to produce
-- MDIO_TRISTATE
signal mdio_clk_reg : std_logic; -- registering MDIO_Clk to use it as a
-- clock MDIO_en
signal mdio_in_reg1 : std_logic; -- compensate in pipeline delay caused
-- by using MDC as a clock MDIO_en
signal mdio_in_reg2 : std_logic; -- compensate in pipeline delay caused by
-- using MDC as a clock MDIO_en
signal clk_cnt : integer range 0 to 32; -- Clk counter
signal ld_cnt_data_cmb : integer range 0 to 32; -- Counter load comb
signal ld_cnt_data_reg : integer range 0 to 32; -- Counter load reg
signal ld_cnt_en_cmb : std_logic; -- Counter load enable
signal clk_cnt_en : std_logic; -- Counter enable
signal mdc_falling : std_logic; -- MDC falling edge
signal mdc_rising : std_logic; -- MDC rising edge
signal ld_cnt_en_reg : std_logic; -- Counter load enable reg
begin
----------------------------------------------------------------------------
-- PROCESS : INPUT_REG_CLK
----------------------------------------------------------------------------
-- Registering PHY_MDIO_I and MDC signals w.r.t SAXI clock.
----------------------------------------------------------------------------
INPUT_REG_CLK: process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_clk_reg <= '0';
mdio_in_reg1 <= '0';
mdio_in_reg2 <= '0';
else
mdio_clk_reg <= MDIO_Clk;
mdio_in_reg1 <= PHY_MDIO_I;
mdio_in_reg2 <= mdio_in_reg1;
end if;
end if;
end process INPUT_REG_CLK;
-- Falling edge and rising edge generation of MDC clock
mdc_falling <= not MDIO_Clk and mdio_clk_reg;
mdc_rising <= MDIO_Clk and not mdio_clk_reg;
-- Enable MDC only when MDIO interface is enabled.
PHY_MDC <= MDIO_Clk; -- making the MDC clk contineous
--PHY_MDC <= MDIO_Clk and mdio_en_reg;
-- Informs MDIO interface about the MDIO transfer complete.
MDIO_done <= mdio_xfer_done;
----------------------------------------------------------------------------
-- PROCESS : REG_MDIO_en
----------------------------------------------------------------------------
-- Latch MDIO_en bit on falling edge of MDC and when MDIO master is IDLE.
-- MDIO Master will complete the existing transfer even if MDIO interface
-- is disable in middle of the transaction.
----------------------------------------------------------------------------
REG_MDIO_en : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_reg <= '0';
elsif mdc_falling='1' then
if mdio_idle = '1' then
mdio_en_reg <= MDIO_en;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_T_REG
----------------------------------------------------------------------------
-- The mdio_t_comb signal is driven high only for read operation starting
-- from the Turn arround state.
-- It is driven on falling clock edge to match up with PHY_MDIO_O
----------------------------------------------------------------------------
PHY_MDIO_T_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_T <= '1';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_T <= mdio_t_comb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_O_REG
----------------------------------------------------------------------------
-- Generating PHY_MDIO_O output singnal on falling edge of MDC
----------------------------------------------------------------------------
PHY_MDIO_O_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_O <= '0';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_O <= mdio_o_cmb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_IDLE_REG
----------------------------------------------------------------------------
-- The mdio_idle signal is used to indicate no activity on the MDIO.
-- Set at reset amd at the end of transmission.
-- Rst at start of transmission as long as device is MDIO_end
----------------------------------------------------------------------------
MDIO_IDLE_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_idle <= '1';
elsif (mdc_rising='1') then -- rising edge of MDC
if (mdio_xfer_done = '1') then
mdio_idle <= '1';
elsif (MDIO_Req = '1' and mdio_en_reg = '1') then
mdio_idle <= '0';
end if;
end if;
end if;
end process ;
----------------------------------------------------------------------------
-- PROCESS : MDIO_CAPTURE_DATA
----------------------------------------------------------------------------
-- This process captures registered PHY_MDIO_i input on rising edge of the
-- MDC clock. The rd_data_en signal is generated in MDIO State machine for
-- respective captured bit.
----------------------------------------------------------------------------
MDIO_CAPTURE_DATA : for i in 15 downto 0 generate
MDIO_DATA_IN : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
MDIO_RD_DATA(i) <= '0';
elsif (mdc_rising='1') then -- rising edge of MDC
if(rd_data_en(i) = '1') then
MDIO_RD_DATA(i) <= mdio_in_reg2;
end if;
end if;
end if;
end process MDIO_DATA_IN;
end generate;
----------------------------------------------------------------------------
-- PROCESS : MDIO_DOWN_COUNTER
----------------------------------------------------------------------------
-- This counter is used in Preamble and PHY_ADDR and REG_ADDR state.
-- This counter is loaded for the required values for each above states.
----------------------------------------------------------------------------
MDIO_DOWN_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= 0;
elsif (mdc_rising='1') then -- falling edge of MDC
if (ld_cnt_en_reg = '1') then -- Load counter with load data
clk_cnt <= ld_cnt_data_reg;
elsif (clk_cnt_en='1') then -- Enable Down Counter
clk_cnt <= clk_cnt - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_NEXT_STATE_GEN
----------------------------------------------------------------------------
-- MDIO next state register process
----------------------------------------------------------------------------
MDIO_NEXT_STATE_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
mdio_state <= IDLE;
elsif (mdc_rising='1') then
mdio_state <= next_state;
end if;
end if;
end process MDIO_NEXT_STATE_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_COMB_REG_GEN
----------------------------------------------------------------------------
-- Combinational signal register process
----------------------------------------------------------------------------
MDIO_COMB_REG_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
ld_cnt_data_reg <= 0;
ld_cnt_en_reg <= '0';
else
ld_cnt_data_reg <= ld_cnt_data_cmb;
ld_cnt_en_reg <= ld_cnt_en_cmb;
end if;
end if;
end process MDIO_COMB_REG_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_STATE_COMB
----------------------------------------------------------------------------
-- This process generates mdio_o_cmb signal in command and Write phase as
-- per the required MDIO protocol. This process also generate mdio_t_comb
-- tristate signal and rd_data_en to capture the respective bit in Read
-- operation.
----------------------------------------------------------------------------
MDIO_STATE_COMB : process (mdio_state, mdio_idle, clk_cnt, MDIO_OP,
MDIO_PHY_AD, MDIO_REG_AD, MDIO_WR_DATA)
begin
-- state machine defaults
mdio_o_cmb <= '1';
rd_data_en <= "0000000000000000";
mdio_xfer_done <= '0';
ld_cnt_en_cmb <= '0';
clk_cnt_en <= '0';
mdio_t_comb <= '0';
next_state <= mdio_state;
ld_cnt_data_cmb <= 0;
case mdio_state is
when IDLE =>
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
ld_cnt_en_cmb <= '1';
-- leave IDLE state when new mdio request is received.
if mdio_idle = '0' then
-- Load counter for 32-bit preamble
ld_cnt_data_cmb <= 31;
next_state <= PREAMBLE;
end if;
when PREAMBLE =>
clk_cnt_en <= '1';
-- Move to ST1 after 32-bit preamble.
if clk_cnt = 0 then
next_state <= ST1;
clk_cnt_en <= '0';
end if;
when ST1 => -- Start Code-1
mdio_o_cmb <= '0';
next_state <= ST2;
when ST2 => -- Start Code-2
mdio_o_cmb <= '1';
next_state <= OP1;
when OP1 => -- Opcode-1
next_state <= OP2;
if MDIO_OP='1' then
mdio_o_cmb <= '1';
else
mdio_o_cmb <= '0';
end if;
when OP2 => -- Opcode-2
next_state <= PHY_ADDR;
-- Load counter for 5-bit PHYaddress transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
if MDIO_OP='1' then
mdio_o_cmb <= '0';
else
mdio_o_cmb <= '1';
end if;
when PHY_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_PHY_AD(clk_cnt);
-- Send 5-bit PHY device address
if clk_cnt=0 then
next_state <= REG_ADDR;
-- Load counter for 5-bit REG address transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
end if;
when REG_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_REG_AD(clk_cnt);
-- Send 5-bit PHY Register address
if clk_cnt=0 then
next_state <= TA1;
clk_cnt_en <= '0';
end if;
when TA1 => -- Turn Around Time-1
mdio_o_cmb <= '1';
next_state <= TA2;
-- For Read operation generate high impedence on
-- MDIO bus
if MDIO_OP='1' then
mdio_t_comb <= '1';
else
mdio_t_comb <= '0';
end if;
when TA2 => -- Turn Around Time-2
mdio_o_cmb <= '0';
-- Load the down counter for 16 bit data transfer
ld_cnt_data_cmb <= 15;
ld_cnt_en_cmb <= '1';
-- Move to Write state if opcode is '0'
if MDIO_OP='0' then
next_state <= WRITE;
mdio_t_comb <= '0';
else
next_state <= READ;
mdio_t_comb <= '1';
end if;
when WRITE => -- MDIO DATA Write
clk_cnt_en <= '1';
-- Send 16-bit Write Data on the MDIO data line
mdio_o_cmb <= MDIO_WR_DATA(clk_cnt);
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when READ => -- MDIO DATA Read
clk_cnt_en <= '1';
mdio_t_comb <= '1';
-- Generate read data enable for respective bit
rd_data_en(clk_cnt) <= '1';
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when DONE => -- MDIO Transfer Done
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
next_state <= IDLE;
-- Mdio trasnfer complete
mdio_xfer_done <= '1';
-- coverage off
when others =>
next_state <= IDLE;
-- coverage on
end case;
end process MDIO_STATE_COMB;
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/crcgenrx.vhd | 4 | 14428 | -------------------------------------------------------------------------------
-- crcgenrx - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : crcgenrx.vhd
-- Version : v4.00.a
-- Description : This module does an 4-bit parallel CRC generation.
-- The polynomial is that specified for IEEE 802.3 (ethernet)
-- LANs and other standards.
--
-- I. Functionality:
-- 1. The module does an 4-bit parallel CRC generation.
-- 2. The module provides a synchronous 4-bit per clock load and
-- unload function.
-- 3. The polynomial is that specified for 802.3 LANs and other
-- standards.
-- The polynomial computed is:
-- G(x)=X**32+X**26+X**23+X**22+X**16+X**12+X**11+X**10+X**8
-- +X**7+X**5+X**4+X** >2+X+1
--
-- II. Module I/O
-- Inputs: Clk, CLKEN, Rst, LOAD, COMPUTE, DATA_IN[3:0]
-- outputs: CRC_OK, DATA_OUT[3:0], CRC[31:0]
--
-- III.Truth Table:
--
-- CLKEN Rst COMPUTE LOAD | DATA_OUT
-- ------------------------------------------
-- 0 X X X | No change
-- 1 0 0 0 | No change
-- 1 1 X X | 0xFFFF (all ones)
-- 1 0 X 1 | load and shift 1 nibble of crc
-- 1 0 1 0 | Compute CRC
--
-- 0 0 1 1 | unload 4 byte crc
-- NOT IMPLEMENTED)
--
-- Loading and unloading of the 32-bit CRC register is done one
-- nibble at a time by asserting LOAD and CLKEN. The Data on
-- data_in is shifted into the the LSB of the CRC register. The
-- MSB of the CRC register is available on data_out.
--
-- Signals ending in _n are active low.
--
-- Copyright 1997 VAutomation Inc. Nashua NH USA (603) 882-2282.
-- Modification for 4 Bit done by Ronald Hecht @ Xilinx Inc.
-- This software is provided AS-IS and free of charge with the restriction that
-- this copyright notice remain in all copies of the Source Code at all times.
-- Visit HTTP://www.vautomation.com for more information on our cores.
-------------------------------------------------------------------------------
-- We remove the 32 bits register which restore the crc value in the old code.
-- For receive part we only need to know the crc is ok or not, so remove the
-- register for restoring crc value will save some resources.
--
-- THE INTERFACE REQUIREMENTS OF THIS MODULE
--
-- Rst reset everything to initial value. We must give this reset
-- before we use crc module, otherwise the result will incorrect.
-- Clk For use with mactx module, it will be 2.5 MHZ.
-- Data Input Data from other module in nibbles.
-- DataEn Enable crcgenrx. Make sure your enable and first Data can be
-- captured at the beginning of Data stream.
-- CrcOk At the end of Data stream, this will go high if the crc is
-- correct.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- xemac.vhd
-- \
-- \-- axi_ipif_interface.vhd
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ ethernetlite_v3_0_dmem_v2.edn
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- ethernetlite_v3_0_dmem_v2.edn
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Data -- Data in
-- DataEn -- Data enable
-- CrcOk -- CRC valid
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity crcgenrx is
port
(
Clk : in std_logic;
Rst : in std_logic;
Data : in std_logic_vector(3 downto 0);
DataEn : in std_logic;
CrcOk : out std_logic
);
end crcgenrx;
architecture arch1 of crcgenrx is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of arch1 : architecture is "yes";
constant CRC_REMAINDER : std_logic_vector(31 downto 0) :=
"11000111000001001101110101111011";
-- 0xC704DD7B
signal crc_local : std_logic_vector(31 downto 0); -- local version
signal data_transpose : std_logic_vector(3 downto 0);
function parallel_crc (crc_in : std_logic_vector(31 downto 0);
data_in : std_logic_vector(3 downto 0)
) return std_logic_vector is
variable c, crc_out : std_logic_vector(31 downto 0);
variable x : std_logic_vector (31 downto 28);
variable d : std_logic_vector (3 downto 0);
begin
-- Because the equations are long I am keeping the name of the incoming
-- CRC and the XOR vector short.
c := crc_in;
d := data_in;
-- the first thing that a parallel CRC needs to do is to develop the
-- vector formed by XORing the input vector by the current CRC. This
-- vector is then used during the CRC calculation.
x := (c(31) xor d(3)) & (c(30) xor d(2)) &
(c(29) xor d(1)) & (c(28) xor d(0));
-- The parellel CRC is a function of the X vector and the current CRC.
crc_out :=
(c(27) ) &
(c(26) ) &
(c(25) xor x(31) ) &
(c(24) xor x(30) ) &
(c(23) xor x(29) ) &
(c(22) xor x(31) xor x(28) ) &
(c(21) xor x(31) xor x(30) ) &
(c(20) xor x(30) xor x(29) ) &
(c(19) xor x(29) xor x(28) ) &
(c(18) xor x(28) ) &
(c(17) ) &
(c(16) ) &
(c(15) xor x(31) ) &
(c(14) xor x(30) ) &
(c(13) xor x(29) ) &
(c(12) xor x(28) ) &
(c(11) xor x(31) ) &
(c(10) xor x(31) xor x(30) ) &
(c(9 ) xor x(31) xor x(30) xor x(29) ) &
(c(8 ) xor x(30) xor x(29) xor x(28) ) &
(c(7 ) xor x(31) xor x(29) xor x(28) ) &
(c(6 ) xor x(31) xor x(30) xor x(28) ) &
(c(5 ) xor x(30) xor x(29) ) &
(c(4 ) xor x(31) xor x(29) xor x(28) ) &
(c(3 ) xor x(31) xor x(30) xor x(28) ) &
(c(2 ) xor x(30) xor x(29) ) &
(c(1 ) xor x(31) xor x(29) xor x(28) ) &
(c(0 ) xor x(31) xor x(30) xor x(28) ) &
( x(31) xor x(30) xor x(29) ) &
( x(30) xor x(29) xor x(28) ) &
( x(29) xor x(28) ) &
( x(28) );
return(crc_out);
end parallel_crc;
begin ------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Xilinx modification, use asynchronous clear
-------------------------------------------------------------------------------
data_transpose <= Data(0) & Data(1) & Data(2) & Data(3);
-- Reverse the bit order
-- Create the 32 Flip flops (with clock enable flops)
CRC_REG : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
crc_local <= (others=>'1');
elsif DataEn = '1' then
crc_local <= parallel_crc(crc_local, data_transpose);
end if;
end if;
end process CRC_REG;
-------------------------------------------------------------------------------
-- Xilinx modification, remove reset from mux
-------------------------------------------------------------------------------
CrcOk <= '1' when crc_local = CRC_REMAINDER else '0';
-- This is a 32-bit wide AND
-- function, so proper
-- attention should be paid
-- when synthesizing to
-- achieve good results. If
-- there are cycles available
-- pipeling this gate would be
-- appropriate.
end arch1;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/876b8fe4/hdl/src/vhdl/pselect_f.vhd | 28 | 10116 | -- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/xlconcat_v2_1/21a398c4/xlconcat.vhd | 9 | 11196 | ------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconcat
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of bus concatenater
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconcat is
generic (
NUM_PORTS : integer := 2; -- Number of input ports to concat
IN0_WIDTH : integer := 1; -- Width of a In0 input
IN1_WIDTH : integer := 1; -- Width of a In1 input
IN2_WIDTH : integer := 1; -- Width of a In2 input
IN3_WIDTH : integer := 1; -- Width of a In3 input
IN4_WIDTH : integer := 1; -- Width of a In4 input
IN5_WIDTH : integer := 1; -- Width of a In5 input
IN6_WIDTH : integer := 1; -- Width of a In6 input
IN7_WIDTH : integer := 1; -- Width of a In7 input
IN8_WIDTH : integer := 1; -- Width of a In8 input
IN9_WIDTH : integer := 1; -- Width of a In9 input
IN10_WIDTH : integer := 1; -- Width of a In10 input
IN11_WIDTH : integer := 1; -- Width of a In10 input
IN12_WIDTH : integer := 1; -- Width of a In10 input
IN13_WIDTH : integer := 1; -- Width of a In10 input
IN14_WIDTH : integer := 1; -- Width of a In10 input
IN15_WIDTH : integer := 1; -- Width of a In15 input
IN16_WIDTH : integer := 1; -- Width of a In16 input
IN17_WIDTH : integer := 1; -- Width of a In17 input
IN18_WIDTH : integer := 1; -- Width of a In18 input
IN19_WIDTH : integer := 1; -- Width of a In19 input
IN20_WIDTH : integer := 1; -- Width of a In20 input
IN21_WIDTH : integer := 1; -- Width of a In21 input
IN22_WIDTH : integer := 1; -- Width of a In22 input
IN23_WIDTH : integer := 1; -- Width of a In23 input
IN24_WIDTH : integer := 1; -- Width of a In24 input
IN25_WIDTH : integer := 1; -- Width of a In25 input
IN26_WIDTH : integer := 1; -- Width of a In26 input
IN27_WIDTH : integer := 1; -- Width of a In27 input
IN28_WIDTH : integer := 1; -- Width of a In28 input
IN29_WIDTH : integer := 1; -- Width of a In29 input
IN30_WIDTH : integer := 1; -- Width of a In30 input
IN31_WIDTH : integer := 1; -- Width of a In31 input
dout_width : integer := 2); -- Width of output
port (
In0 : in std_logic_vector (IN0_WIDTH-1 downto 0);
In1 : in std_logic_vector (IN1_WIDTH-1 downto 0);
In2 : in std_logic_vector (IN2_WIDTH-1 downto 0);
In3 : in std_logic_vector (IN3_WIDTH-1 downto 0);
In4 : in std_logic_vector (IN4_WIDTH-1 downto 0);
In5 : in std_logic_vector (IN5_WIDTH-1 downto 0);
In6 : in std_logic_vector (IN6_WIDTH-1 downto 0);
In7 : in std_logic_vector (IN7_WIDTH-1 downto 0);
In8 : in std_logic_vector (IN8_WIDTH-1 downto 0);
In9 : in std_logic_vector (IN9_WIDTH-1 downto 0);
In10 : in std_logic_vector (IN10_WIDTH-1 downto 0);
In11 : in std_logic_vector (IN11_WIDTH-1 downto 0);
In12 : in std_logic_vector (IN12_WIDTH-1 downto 0);
In13 : in std_logic_vector (IN13_WIDTH-1 downto 0);
In14 : in std_logic_vector (IN14_WIDTH-1 downto 0);
In15 : in std_logic_vector (IN15_WIDTH-1 downto 0);
In16 : in std_logic_vector (IN16_WIDTH-1 downto 0);
In17 : in std_logic_vector (IN17_WIDTH-1 downto 0);
In18 : in std_logic_vector (IN18_WIDTH-1 downto 0);
In19 : in std_logic_vector (IN19_WIDTH-1 downto 0);
In20 : in std_logic_vector (IN20_WIDTH-1 downto 0);
In21 : in std_logic_vector (IN21_WIDTH-1 downto 0);
In22 : in std_logic_vector (IN22_WIDTH-1 downto 0);
In23 : in std_logic_vector (IN23_WIDTH-1 downto 0);
In24 : in std_logic_vector (IN24_WIDTH-1 downto 0);
In25 : in std_logic_vector (IN25_WIDTH-1 downto 0);
In26 : in std_logic_vector (IN26_WIDTH-1 downto 0);
In27 : in std_logic_vector (IN27_WIDTH-1 downto 0);
In28 : in std_logic_vector (IN28_WIDTH-1 downto 0);
In29 : in std_logic_vector (IN29_WIDTH-1 downto 0);
In30 : in std_logic_vector (IN30_WIDTH-1 downto 0);
In31 : in std_logic_vector (IN31_WIDTH-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0)
);
end xlconcat;
architecture behavioral of xlconcat is
begin
NUM_1_INST : if NUM_PORTS = 1 generate
begin
dout <= In0;
end generate NUM_1_INST;
NUM_2_INST : if NUM_PORTS = 2 generate
begin
dout <= In1 & In0;
end generate NUM_2_INST;
NUM_3_INST : if NUM_PORTS = 3 generate
begin
dout <= In2 & In1 & In0;
end generate NUM_3_INST;
NUM_4_INST : if NUM_PORTS = 4 generate
begin
dout <= In3 & In2 & In1 & In0;
end generate NUM_4_INST;
NUM_5_INST : if NUM_PORTS = 5 generate
begin
dout <= In4 & In3 & In2 & In1 & In0;
end generate NUM_5_INST;
NUM_6_INST : if NUM_PORTS = 6 generate
begin
dout <= In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_6_INST;
NUM_7_INST : if NUM_PORTS = 7 generate
begin
dout <= In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_7_INST;
NUM_8_INST : if NUM_PORTS = 8 generate
begin
dout <= In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_8_INST;
NUM_9_INST : if NUM_PORTS = 9 generate
begin
dout <= In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_9_INST;
NUM_10_INST : if NUM_PORTS = 10 generate
begin
dout <= In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_10_INST;
NUM_11_INST : if NUM_PORTS = 11 generate
begin
dout <= In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_11_INST;
NUM_12_INST : if NUM_PORTS = 12 generate
begin
dout <= In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_12_INST;
NUM_13_INST : if NUM_PORTS = 13 generate
begin
dout <= In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_13_INST;
NUM_14_INST : if NUM_PORTS = 14 generate
begin
dout <= In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_14_INST;
NUM_15_INST : if NUM_PORTS = 15 generate
begin
dout <= In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_15_INST;
NUM_16_INST : if NUM_PORTS = 16 generate
begin
dout <= In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_16_INST;
NUM_17_INST : if NUM_PORTS = 17 generate
begin
dout <= In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_17_INST;
NUM_18_INST : if NUM_PORTS = 18 generate
begin
dout <= In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_18_INST;
NUM_19_INST : if NUM_PORTS = 19 generate
begin
dout <= In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_19_INST;
NUM_20_INST : if NUM_PORTS = 20 generate
begin
dout <= In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_20_INST;
NUM_21_INST : if NUM_PORTS = 21 generate
begin
dout <= In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_21_INST;
NUM_22_INST : if NUM_PORTS = 22 generate
begin
dout <= In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_22_INST;
NUM_23_INST : if NUM_PORTS = 23 generate
begin
dout <= In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_23_INST;
NUM_24_INST : if NUM_PORTS = 24 generate
begin
dout <= In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_24_INST;
NUM_25_INST : if NUM_PORTS = 25 generate
begin
dout <= In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_25_INST;
NUM_26_INST : if NUM_PORTS = 26 generate
begin
dout <= In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_26_INST;
NUM_27_INST : if NUM_PORTS = 27 generate
begin
dout <= In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_27_INST;
NUM_28_INST : if NUM_PORTS = 28 generate
begin
dout <= In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_28_INST;
NUM_29_INST : if NUM_PORTS = 29 generate
begin
dout <= In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_29_INST;
NUM_30_INST : if NUM_PORTS = 30 generate
begin
dout <= In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_30_INST;
NUM_31_INST : if NUM_PORTS = 31 generate
begin
dout <= In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_31_INST;
NUM_32_INST : if NUM_PORTS = 32 generate
begin
dout <= In31 & In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_32_INST;
end behavioral;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/xlconcat_v2_1/21a398c4/xlconcat.vhd | 9 | 11196 | ------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconcat
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of bus concatenater
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconcat is
generic (
NUM_PORTS : integer := 2; -- Number of input ports to concat
IN0_WIDTH : integer := 1; -- Width of a In0 input
IN1_WIDTH : integer := 1; -- Width of a In1 input
IN2_WIDTH : integer := 1; -- Width of a In2 input
IN3_WIDTH : integer := 1; -- Width of a In3 input
IN4_WIDTH : integer := 1; -- Width of a In4 input
IN5_WIDTH : integer := 1; -- Width of a In5 input
IN6_WIDTH : integer := 1; -- Width of a In6 input
IN7_WIDTH : integer := 1; -- Width of a In7 input
IN8_WIDTH : integer := 1; -- Width of a In8 input
IN9_WIDTH : integer := 1; -- Width of a In9 input
IN10_WIDTH : integer := 1; -- Width of a In10 input
IN11_WIDTH : integer := 1; -- Width of a In10 input
IN12_WIDTH : integer := 1; -- Width of a In10 input
IN13_WIDTH : integer := 1; -- Width of a In10 input
IN14_WIDTH : integer := 1; -- Width of a In10 input
IN15_WIDTH : integer := 1; -- Width of a In15 input
IN16_WIDTH : integer := 1; -- Width of a In16 input
IN17_WIDTH : integer := 1; -- Width of a In17 input
IN18_WIDTH : integer := 1; -- Width of a In18 input
IN19_WIDTH : integer := 1; -- Width of a In19 input
IN20_WIDTH : integer := 1; -- Width of a In20 input
IN21_WIDTH : integer := 1; -- Width of a In21 input
IN22_WIDTH : integer := 1; -- Width of a In22 input
IN23_WIDTH : integer := 1; -- Width of a In23 input
IN24_WIDTH : integer := 1; -- Width of a In24 input
IN25_WIDTH : integer := 1; -- Width of a In25 input
IN26_WIDTH : integer := 1; -- Width of a In26 input
IN27_WIDTH : integer := 1; -- Width of a In27 input
IN28_WIDTH : integer := 1; -- Width of a In28 input
IN29_WIDTH : integer := 1; -- Width of a In29 input
IN30_WIDTH : integer := 1; -- Width of a In30 input
IN31_WIDTH : integer := 1; -- Width of a In31 input
dout_width : integer := 2); -- Width of output
port (
In0 : in std_logic_vector (IN0_WIDTH-1 downto 0);
In1 : in std_logic_vector (IN1_WIDTH-1 downto 0);
In2 : in std_logic_vector (IN2_WIDTH-1 downto 0);
In3 : in std_logic_vector (IN3_WIDTH-1 downto 0);
In4 : in std_logic_vector (IN4_WIDTH-1 downto 0);
In5 : in std_logic_vector (IN5_WIDTH-1 downto 0);
In6 : in std_logic_vector (IN6_WIDTH-1 downto 0);
In7 : in std_logic_vector (IN7_WIDTH-1 downto 0);
In8 : in std_logic_vector (IN8_WIDTH-1 downto 0);
In9 : in std_logic_vector (IN9_WIDTH-1 downto 0);
In10 : in std_logic_vector (IN10_WIDTH-1 downto 0);
In11 : in std_logic_vector (IN11_WIDTH-1 downto 0);
In12 : in std_logic_vector (IN12_WIDTH-1 downto 0);
In13 : in std_logic_vector (IN13_WIDTH-1 downto 0);
In14 : in std_logic_vector (IN14_WIDTH-1 downto 0);
In15 : in std_logic_vector (IN15_WIDTH-1 downto 0);
In16 : in std_logic_vector (IN16_WIDTH-1 downto 0);
In17 : in std_logic_vector (IN17_WIDTH-1 downto 0);
In18 : in std_logic_vector (IN18_WIDTH-1 downto 0);
In19 : in std_logic_vector (IN19_WIDTH-1 downto 0);
In20 : in std_logic_vector (IN20_WIDTH-1 downto 0);
In21 : in std_logic_vector (IN21_WIDTH-1 downto 0);
In22 : in std_logic_vector (IN22_WIDTH-1 downto 0);
In23 : in std_logic_vector (IN23_WIDTH-1 downto 0);
In24 : in std_logic_vector (IN24_WIDTH-1 downto 0);
In25 : in std_logic_vector (IN25_WIDTH-1 downto 0);
In26 : in std_logic_vector (IN26_WIDTH-1 downto 0);
In27 : in std_logic_vector (IN27_WIDTH-1 downto 0);
In28 : in std_logic_vector (IN28_WIDTH-1 downto 0);
In29 : in std_logic_vector (IN29_WIDTH-1 downto 0);
In30 : in std_logic_vector (IN30_WIDTH-1 downto 0);
In31 : in std_logic_vector (IN31_WIDTH-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0)
);
end xlconcat;
architecture behavioral of xlconcat is
begin
NUM_1_INST : if NUM_PORTS = 1 generate
begin
dout <= In0;
end generate NUM_1_INST;
NUM_2_INST : if NUM_PORTS = 2 generate
begin
dout <= In1 & In0;
end generate NUM_2_INST;
NUM_3_INST : if NUM_PORTS = 3 generate
begin
dout <= In2 & In1 & In0;
end generate NUM_3_INST;
NUM_4_INST : if NUM_PORTS = 4 generate
begin
dout <= In3 & In2 & In1 & In0;
end generate NUM_4_INST;
NUM_5_INST : if NUM_PORTS = 5 generate
begin
dout <= In4 & In3 & In2 & In1 & In0;
end generate NUM_5_INST;
NUM_6_INST : if NUM_PORTS = 6 generate
begin
dout <= In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_6_INST;
NUM_7_INST : if NUM_PORTS = 7 generate
begin
dout <= In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_7_INST;
NUM_8_INST : if NUM_PORTS = 8 generate
begin
dout <= In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_8_INST;
NUM_9_INST : if NUM_PORTS = 9 generate
begin
dout <= In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_9_INST;
NUM_10_INST : if NUM_PORTS = 10 generate
begin
dout <= In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_10_INST;
NUM_11_INST : if NUM_PORTS = 11 generate
begin
dout <= In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_11_INST;
NUM_12_INST : if NUM_PORTS = 12 generate
begin
dout <= In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_12_INST;
NUM_13_INST : if NUM_PORTS = 13 generate
begin
dout <= In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_13_INST;
NUM_14_INST : if NUM_PORTS = 14 generate
begin
dout <= In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_14_INST;
NUM_15_INST : if NUM_PORTS = 15 generate
begin
dout <= In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_15_INST;
NUM_16_INST : if NUM_PORTS = 16 generate
begin
dout <= In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_16_INST;
NUM_17_INST : if NUM_PORTS = 17 generate
begin
dout <= In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_17_INST;
NUM_18_INST : if NUM_PORTS = 18 generate
begin
dout <= In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_18_INST;
NUM_19_INST : if NUM_PORTS = 19 generate
begin
dout <= In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_19_INST;
NUM_20_INST : if NUM_PORTS = 20 generate
begin
dout <= In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_20_INST;
NUM_21_INST : if NUM_PORTS = 21 generate
begin
dout <= In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_21_INST;
NUM_22_INST : if NUM_PORTS = 22 generate
begin
dout <= In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_22_INST;
NUM_23_INST : if NUM_PORTS = 23 generate
begin
dout <= In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_23_INST;
NUM_24_INST : if NUM_PORTS = 24 generate
begin
dout <= In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_24_INST;
NUM_25_INST : if NUM_PORTS = 25 generate
begin
dout <= In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_25_INST;
NUM_26_INST : if NUM_PORTS = 26 generate
begin
dout <= In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_26_INST;
NUM_27_INST : if NUM_PORTS = 27 generate
begin
dout <= In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_27_INST;
NUM_28_INST : if NUM_PORTS = 28 generate
begin
dout <= In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_28_INST;
NUM_29_INST : if NUM_PORTS = 29 generate
begin
dout <= In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_29_INST;
NUM_30_INST : if NUM_PORTS = 30 generate
begin
dout <= In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_30_INST;
NUM_31_INST : if NUM_PORTS = 31 generate
begin
dout <= In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_31_INST;
NUM_32_INST : if NUM_PORTS = 32 generate
begin
dout <= In31 & In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_32_INST;
end behavioral;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/mux_onehot_f.vhd | 4 | 12287 | -- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
constant NLS : natural := 6;--native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mdm_v3_2/fbb28dda/hdl/vhdl/arbiter.vhd | 4 | 9525 | -------------------------------------------------------------------------------
-- arbiter.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: arbiter.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- arbiter.vhd
-- mdm_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2014/05/08 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Arbiter is
generic (
Size : natural := 32;
Size_Log2 : natural := 5);
port (
Clk : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
Requests : in std_logic_vector(Size-1 downto 0);
Granted : out std_logic_vector(Size-1 downto 0);
Valid_Sel : out std_logic;
Selected : out std_logic_vector(Size_Log2-1 downto 0));
end entity Arbiter;
architecture IMP of Arbiter is
component select_bit
generic (
sel_value : std_logic_vector(1 downto 0));
port (
Mask : in std_logic_vector(1 downto 0);
Request : in std_logic_vector(1 downto 0);
Carry_In : in std_logic;
Carry_Out : out std_logic);
end component select_bit;
component carry_or_vec
generic (
Size : natural);
port (
Carry_In : in std_logic;
In_Vec : in std_logic_vector(0 to Size-1);
Carry_Out : out std_logic);
end component carry_or_vec;
component carry_and
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end component carry_and;
component carry_or
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end component carry_or;
subtype index_type is std_logic_vector(Size_Log2-1 downto 0);
type int_array_type is array (natural range 2*Size-1 downto 0) of index_type;
function init_index_table return int_array_type is
variable tmp : int_array_type;
begin -- function init_index_table
for I in 0 to Size-1 loop
tmp(I) := std_logic_vector(to_unsigned(I, Size_Log2));
tmp(Size+I) := std_logic_vector(to_unsigned(I, Size_Log2));
end loop; -- I
return tmp;
end function init_index_table;
constant index_table : int_array_type := init_index_table;
signal long_req : std_logic_vector(2*Size-1 downto 0);
signal mask : std_logic_vector(2*Size-1 downto 0);
signal grant_sel : std_logic_vector(Size_Log2-1 downto 0);
signal new_granted : std_logic;
signal reset_loop : std_logic;
signal mask_reset : std_logic;
signal valid_grant : std_logic;
begin -- architecture IMP
long_req <= Requests & Requests;
Request_Or : carry_or_vec
generic map (
Size => Size)
port map (
Carry_In => Enable,
In_Vec => Requests, -- in
Carry_Out => new_granted); -- out
Valid_Sel <= new_granted;
-----------------------------------------------------------------------------
-- Generate Carry-Chain structure
-----------------------------------------------------------------------------
Chain: for I in Size_Log2-1 downto 0 generate
signal carry : std_logic_vector(Size downto 0); -- Assumes 2 bit/muxcy
begin -- generate Bits
carry(Size) <= '0';
Bits: for J in Size-1 downto 0 generate
constant sel1 : std_logic := index_table(2*J+1)(I);
constant sel0 : std_logic := index_table(2*J)(I);
attribute keep_hierarchy : string;
attribute keep_hierarchy of Select_bits : label is "yes";
begin -- generate Bits
Select_bits : select_bit
generic map (
sel_value => sel1 & sel0)
port map (
Mask => mask(2*J+1 downto 2*J), -- in
Request => long_req(2*J+1 downto 2*J), -- in
Carry_In => carry(J+1), -- in
Carry_Out => carry(J)); -- out
end generate Bits;
grant_sel(I) <= carry(0);
end generate Chain;
Selected <= grant_sel;
-----------------------------------------------------------------------------
-- Handling Mask value
-----------------------------------------------------------------------------
-- if (Reset = '1') or ((new_granted and mask(1)) = '1') then
Reset_loop_and : carry_and
port map (
Carry_IN => new_granted, -- in
A => mask(1), -- in
Carry_OUT => reset_loop); -- out
Mask_Reset_carry : carry_or
port map (
Carry_IN => reset_loop, -- in
A => Reset, -- in
Carry_OUT => mask_reset); -- out
Mask_Handler : process (Clk) is
begin -- process Mask_Handler
if Clk'event and Clk = '1' then -- rising clock edge
if (mask_reset = '1') then -- synchronous reset (active high)
mask(2*Size-1 downto Size) <= (others => '1');
mask(Size-1 downto 0) <= (others => '0');
else
if (new_granted = '1') then
mask(2*Size-1 downto 1) <= mask(1) & mask(2*Size-1 downto 2);
end if;
end if;
end if;
end process Mask_Handler;
-----------------------------------------------------------------------------
-- Generate grant signal
-----------------------------------------------------------------------------
Grant_Signals: for K in Size-1 downto 1 generate
signal tmp : std_logic;
attribute keep : string;
attribute keep of tmp : signal is "true";
begin -- generate Grant_Signals
tmp <= '1' when (K = to_integer(unsigned(grant_sel))) else '0';
granted(K) <= tmp;
end generate Grant_Signals;
Granted(0) <= Requests(0) when to_integer(unsigned(grant_sel)) = 0 else '0';
end architecture IMP;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/emc.vhd | 4 | 73849 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: emc.vhd
-- Version: v2.1
-- Description: Common interface for External Memory Controller
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 03/01/08 First Version
-- ^^^^^^^^^^
-- This file is based on version v3_01_c updated to fixed CR #466745: -
-- Added generic C_MEM_DQ_CAPTURE_NEGEDGE. The same generic is mapped to
-- component io_registers from emc_common_v3_03_a.
-- ~~~~~~~~~
-- NSK 03/12/08 Updated
-- ^^^^^^^^
-- Added generic C_MEM_DQ_CAPTURE_NEGEDGE in comment "Definition of Generics"
-- section.
-- ~~~~~~~~
-- NSK 03/03/08 Updated
-- ^^^^^^^^
-- 1. Removed generic C_MEM_DQ_CAPTURE_NEGEDGE.
-- 2. Added the port RdClk used as clock to capture the data from memory.
-- ~~~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_03_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
--
-- KSB 05/08/08 version v4_00_a
-- 1. Modified for Page mdoe read
-- 2. Modified for 64 Bit memory address align
-- ~~~~~~~~
--
-- KSB 22/05/10 version v5_00_a
-- 1. Modified for AXI EMC, PSRAM, Byte parity Memory Support
-- 2. Modified for AXI Slave burst interface
-- ~~~~~~~~
-- SK 03/11/10 version v5_01_a
-- ^^^^^^^^
-- 1. Registered the IP2Bus_RdAck and IP2Bus_Data signals.
-- 2. Reduced utilization
-- ~~~~~~~~
-- SK 03/11/11 version v5_03_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- emc_common_v3_0 library is used for emc_common component declarations
-------------------------------------------------------------------------------
library emc_common_v3_0;
use emc_common_v3_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- C_NUM_BANKS_MEM -- Number of memory banks
-- C_IPIF_DWIDTH -- Width of processor data bus
-- C_IPIF_AWIDTH -- Width of processor address bus
-- C_MEM(0:3)_BASEADDR -- Memory bank (0:3) base address
-- C_MEM(0:3)_HIGHADDR -- Memory bank (0:3) high address
-- C_INCLUDE_NEGEDGE_IOREGS -- Include negative edge IO registers
-- C_PAGEMODE_FLASH_(0:3) -- Whether a PAGE MODE Flash device is used
-- C_MEM(0:3)_WIDTH -- Width of memory bank's data bus
-- C_MAX_MEM_WIDTH -- Maximum width of memory data bus
-- C_INCLUDE_DATAWIDTH_MATCHING_(0:3) -- Include datawidth matching logic for
-- -- memory bank
-- C_BUS_CLOCK_PERIOD_PS -- Bus clock period to calculate wait
-- state pulse widths.
-- C_SYNCH_MEM_(0:3) -- Memory bank is synchronous
-- C_TCEDV_PS_MEM_(0:3) -- Chip Enable to Data Valid Time
-- -- (Maximum of TCEDV and TAVDV applied
-- as read cycle start to first data valid)
-- C_TAVDV_PS_MEM_(0:3) -- Address Valid to Data Valid Time
-- -- (Maximum of TCEDV and TAVDV applied
-- as read cycle start to first data valid)
-- C_TPACC_PS_FLASH_(0:3) -- Address Valid to Data Valid Time
-- -- for a PAGE Read for a PAGE MODE Flash
-- C_THZCE_PS_MEM_(0:3) -- Chip Enable High to Data Bus High
-- Impedance (Maximum of THZCE and THZOE
-- applied as Read Recovery before Write)
-- C_THZOE_PS_MEM_(0:3) -- Output Enable High to Data Bus High
-- Impedance (Maximum of THZCE and THZOE
-- applied as Read Recovery before Write)
-- C_TWC_PS_MEM_(0:3) -- Write Cycle Time
-- (Maximum of TWC and TWP applied as write
-- enable pulse width)
-- C_TWP_PS_MEM_(0:3) -- Write Enable Minimum Pulse Width
-- (Maximum of TWC and TWP applied as write
-- enable pulse width)
-- C_TLZWE_PS_MEM_(0:3) -- Write Enable High to Data Bus Low
-- Impedance (Applied as Write Recovery
-- before Read)
-- C_WR_REC_TIME_MEM_(0:3) -- Write recovery time between the write
-- -- and next consecutive read transaction
-- Definition of Ports:
--
-- Bus2IP_Clk -- System clock
-- RdClk -- Read Clock
-- Bus2IP_Reset -- System Reset
--
-- Bus and IPIC Interface signals
-- Bus2IP_Addr -- Processor bus address
-- Bus2IP_BE -- Processor bus byte enables
-- Bus2IP_Data -- Processor data
-- Bus2IP_RNW -- Processor read not write
-- Bus2IP_Burst -- Processor burst
-- Bus2IP_WrReq -- Processor write request
-- Bus2IP_RdReq -- Processor read request
-- Bus2IP_Mem_CS -- Memory address range is being accessed
--
-- EMC to bus signals
-- IP2Bus_Data -- Data to processor bus
-- IP2Bus_errAck -- Error acknowledge
-- IP2Bus_retry -- Retry indicator
-- IP2Bus_toutSup -- Suppress watch dog timer
-- IP2Bus_RdAck -- Read acknowledge
-- IP2Bus_WrAck -- Write acknowledge
-- IP2Bus_AddrAck -- Read/Write Address acknowledge
--
-- Memory signals
-- Mem_A -- Memory address inputs
-- Mem_DQ_I -- Memory input data bus
-- Mem_DQ_O -- Memory output data bus
-- Mem_DQ_T -- Memory data output enable
-- Mem_CEN -- Memory chip select
-- Mem_OEN -- Memory output enable
-- Mem_WEN -- Memory write enable
-- Mem_QWEN -- Memory qualified write enable
-- Mem_BEN -- Memory byte enables
-- Mem_RPN -- Memory reset/power down
-- Mem_CE -- Memory chip enable
-- Mem_ADV_LDN -- Memory counter advance/load (=0)
-- Mem_LBON -- Memory linear/interleaved burst order (=0)
-- Mem_CKEN -- Memory clock enable (=0)
-- Mem_RNW -- Memory read not write
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity EMC is
generic (
C_NUM_BANKS_MEM : integer range 1 to 4 := 1;
C_IPIF_DWIDTH : integer := 32;
C_IPIF_AWIDTH : integer := 32;
C_MEM0_BASEADDR : std_logic_vector := x"30000000";
C_MEM0_HIGHADDR : std_logic_vector := x"3000ffff";
C_MEM1_BASEADDR : std_logic_vector := x"40000000";
C_MEM1_HIGHADDR : std_logic_vector := x"4000ffff";
C_MEM2_BASEADDR : std_logic_vector := x"50000000";
C_MEM2_HIGHADDR : std_logic_vector := x"5000ffff";
C_MEM3_BASEADDR : std_logic_vector := x"60000000";
C_MEM3_HIGHADDR : std_logic_vector := x"6000ffff";
C_INCLUDE_NEGEDGE_IOREGS : integer := 0;
C_PAGEMODE_FLASH_0 : integer := 0;
C_PAGEMODE_FLASH_1 : integer := 0;
C_PAGEMODE_FLASH_2 : integer := 0;
C_PAGEMODE_FLASH_3 : integer := 0;
C_MEM0_WIDTH : integer range 8 to 64 := 32;
C_MEM1_WIDTH : integer range 8 to 64 := 32;
C_MEM2_WIDTH : integer range 8 to 64 := 32;
C_MEM3_WIDTH : integer range 8 to 64 := 32;
C_MAX_MEM_WIDTH : integer range 8 to 64 := 32;
C_MEM0_TYPE : integer range 0 to 5 := 0;
C_MEM1_TYPE : integer range 0 to 5 := 0;
C_MEM2_TYPE : integer range 0 to 5 := 0;
C_MEM3_TYPE : integer range 0 to 5 := 0;
C_PARITY_TYPE_0 : integer range 0 to 2 := 0;
C_PARITY_TYPE_1 : integer range 0 to 2 := 0;
C_PARITY_TYPE_2 : integer range 0 to 2 := 0;
C_PARITY_TYPE_3 : integer range 0 to 2 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_0 : integer := 0;
C_INCLUDE_DATAWIDTH_MATCHING_1 : integer := 0;
C_INCLUDE_DATAWIDTH_MATCHING_2 : integer := 0;
C_INCLUDE_DATAWIDTH_MATCHING_3 : integer := 0;
C_BUS_CLOCK_PERIOD_PS : integer := 10000;
-- Memory Channel 0 Timing Parameters
C_SYNCH_MEM_0 : integer := 0;
--C_SUPPORT_SYNC_RD_0 : integer := 0;
C_SYNCH_PIPEDELAY_0 : integer := 2;
C_TCEDV_PS_MEM_0 : integer := 15000;
C_TAVDV_PS_MEM_0 : integer := 15000;
C_TPACC_PS_FLASH_0 : integer := 25;
C_THZCE_PS_MEM_0 : integer := 7000;
C_THZOE_PS_MEM_0 : integer := 7000;
C_TWC_PS_MEM_0 : integer := 15000;
C_TWP_PS_MEM_0 : integer := 12000;
C_TWPH_PS_MEM_0 : integer := 12000;
C_TLZWE_PS_MEM_0 : integer := 0;
C_WR_REC_TIME_MEM_0 : integer := 100000;
-- Memory Channel 1 Timing Parameters
C_SYNCH_MEM_1 : integer := 0;
--C_SUPPORT_SYNC_RD_1 : integer := 0;
C_SYNCH_PIPEDELAY_1 : integer := 2;
C_TCEDV_PS_MEM_1 : integer := 15000;
C_TAVDV_PS_MEM_1 : integer := 15000;
C_TPACC_PS_FLASH_1 : integer := 25000;
C_THZCE_PS_MEM_1 : integer := 7000;
C_THZOE_PS_MEM_1 : integer := 7000;
C_TWC_PS_MEM_1 : integer := 15000;
C_TWP_PS_MEM_1 : integer := 12000;
C_TWPH_PS_MEM_1 : integer := 12000;
C_TLZWE_PS_MEM_1 : integer := 0;
C_WR_REC_TIME_MEM_1 : integer := 100000;
-- Memory Channel 2 Timing Parameters
C_SYNCH_MEM_2 : integer := 0;
--C_SUPPORT_SYNC_RD_2 : integer := 0;
C_SYNCH_PIPEDELAY_2 : integer := 2;
C_TCEDV_PS_MEM_2 : integer := 15000;
C_TAVDV_PS_MEM_2 : integer := 15000;
C_TPACC_PS_FLASH_2 : integer := 25000;
C_THZCE_PS_MEM_2 : integer := 7000;
C_THZOE_PS_MEM_2 : integer := 7000;
C_TWC_PS_MEM_2 : integer := 15000;
C_TWP_PS_MEM_2 : integer := 12000;
C_TWPH_PS_MEM_2 : integer := 12000;
C_TLZWE_PS_MEM_2 : integer := 0;
C_WR_REC_TIME_MEM_2 : integer := 100000;
-- Memory Channel 3 Timing Parameters
C_SYNCH_MEM_3 : integer := 0;
--C_SUPPORT_SYNC_RD_3 : integer := 0;
C_SYNCH_PIPEDELAY_3 : integer := 2;
C_TCEDV_PS_MEM_3 : integer := 15000;
C_TAVDV_PS_MEM_3 : integer := 15000;
C_TPACC_PS_FLASH_3 : integer := 25000;
C_THZCE_PS_MEM_3 : integer := 7000;
C_THZOE_PS_MEM_3 : integer := 7000;
C_TWC_PS_MEM_3 : integer := 15000;
C_TWP_PS_MEM_3 : integer := 12000;
C_TWPH_PS_MEM_3 : integer := 12000;
C_TLZWE_PS_MEM_3 : integer := 0 ;
C_WR_REC_TIME_MEM_3 : integer := 100000
);
port (
Bus2IP_Clk : in std_logic;
RdClk : in std_logic;
Bus2IP_Reset : in std_logic;
-- Bus and IPIC Interface signals
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_AWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Bus2IP_Data : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
Bus2IP_RNW : in std_logic;
Bus2IP_Burst : in std_logic;
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_Mem_CS : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Bus2IP_BurstLength : in std_logic_vector (0 to 7);
Linear_flash_brst_rd_flag : in std_logic;
Linear_flash_rd_data_ack : in std_logic;
Bus2IP_RdReq_emc : in std_logic;
Bus2IP_WrReq_emc : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
IP2Bus_errAck : out std_logic;
IP2Bus_retry : out std_logic;
IP2Bus_toutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_AddrAck : out std_logic;
parity_error_adrss : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
parity_error_mem : out std_logic_vector(0 to 1);
Type_of_xfer : in std_logic;
psram_page_mode : in std_logic;
original_wrce : in std_logic;
Mem_DQ_I : in std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_O : out std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_T : out std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_PRTY_I : in std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PRTY_O : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PRTY_T : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_A : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_OEN : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_BEN : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_CE : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic;
Cre_reg_en : in std_logic;
Mem_WAIT : in std_logic;
Synch_mem12 : out std_logic;
last_addr1 : in std_logic;
pr_idle : out std_logic; -- 11-12-2012
axi_trans_size_reg : in std_logic_vector(1 downto 0); -- 1/3/2013
axi_wvalid : in std_logic;
axi_wlast : in std_logic;
axi_arsize : in std_logic_vector(2 downto 0);
Parity_err : out std_logic
);
end entity EMC;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of EMC is
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Data Types
-------------------------------------------------------------------------------
type EMC_ARRAY_TYPE is array (0 to 3) of integer;
-- type EMC_ARRAY_TYPE is array (0 to C_NUM_BANKS_MEM-1) of integer;
type INTEGER_ARRAY is array (natural range <>) of integer;
type MEM_ADDR_ARRAY is array (0 to C_NUM_BANKS_MEM-1) of
std_logic_vector(0 to C_IPIF_AWIDTH-1);
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- not_all_zeros()
-------------------------------------------------------------------------------
function not_all_zeros(input_array : EMC_ARRAY_TYPE;
num_real_elements : integer)
return integer is
variable sum : integer range 0 to 16 := 0;
begin
for i in 0 to num_real_elements -1 loop
sum := sum + input_array(i);
end loop;
if sum = 0 then
return 0;
else
return 1;
end if;
end function not_all_zeros;
--------------------------------------------------------------------------------
function check_flash_mem(input_array : EMC_ARRAY_TYPE; -- 9/7/2011
num_real_elements : integer)
return integer is
variable sum : integer range 0 to 10 := 0;
begin
for i in 0 to num_real_elements -1 loop
if(input_array(i) = 2)or
(input_array(i) = 3)or
(input_array(i) = 5)or
(input_array(i) = 4)then
sum := sum + 1;
end if;
end loop;
if sum = 0 then
return 0;
else
return 1;
end if;
end function check_flash_mem;
-- --------------------------------------------------------------------------------
-- -- flash_supports_sync_rd: below function is used to check if any of the memories in the assigned
-- -- memory location is of Linear Flash which supports Sync Burst Read mode
-- --------------------------------------------------------------------------------
-- function flash_supports_sync_rd (input_flash_array : EMC_ARRAY_TYPE;
-- num_of_mem_banks : integer)
-- return integer is
-- variable flash_sync_rd : integer range 0 to 1 := 0;
-- begin
-- for i in 0 to num_of_mem_banks -1 loop
-- flash_sync_rd := flash_sync_rd + input_flash_array(i);
-- end loop;
--
-- if flash_sync_rd = 0 then
-- return 0;
-- else
-- return 1;
-- end if;
-- end function flash_supports_sync_rd;
-- -------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- minimum memory data width supported is 8 bits
constant MIN_MEM_WIDTH : integer := 8;
-- address offset
constant ADDR_OFFSET : integer range 0 to 4
:= log2(C_IPIF_DWIDTH/8);
constant ADDR_CNTR_WIDTH : integer range 1 to 5
:= max2(1,log2(C_IPIF_DWIDTH/8));
-- create arrays of generics for use in functions
constant SYNCH_MEM_ARRAY : EMC_ARRAY_TYPE :=
(C_SYNCH_MEM_0,
C_SYNCH_MEM_1,
C_SYNCH_MEM_2,
C_SYNCH_MEM_3);
constant DATAWIDTH_MATCH_ARRAY : EMC_ARRAY_TYPE :=
(C_INCLUDE_DATAWIDTH_MATCHING_0,
C_INCLUDE_DATAWIDTH_MATCHING_1,
C_INCLUDE_DATAWIDTH_MATCHING_2,
C_INCLUDE_DATAWIDTH_MATCHING_3);
constant C_PAGEMODE_FLASH : EMC_ARRAY_TYPE :=
(C_PAGEMODE_FLASH_0,
C_PAGEMODE_FLASH_1,
C_PAGEMODE_FLASH_2,
C_PAGEMODE_FLASH_3);
-- constant C_FLASH_SUPPORTS_SYNC_RD : EMC_ARRAY_TYPE :=
-- (
-- C_SUPPORT_SYNC_RD_0,
-- C_SUPPORT_SYNC_RD_1,
-- C_SUPPORT_SYNC_RD_2,
-- C_SUPPORT_SYNC_RD_3
-- );
type MEM_PARITY_ARRAY_TYPE is array (0 to 3) of integer range 0 to 2;
constant MEM_PARITY_TYPE_ARRAY : EMC_ARRAY_TYPE :=
(
C_PARITY_TYPE_0,
C_PARITY_TYPE_1,
C_PARITY_TYPE_2,
C_PARITY_TYPE_3
);
-- constant C_WRITE_RECOVERY_TIME : EMC_ARRAY_TYPE :=
-- (
-- C_WR_REC_TIME_MEM_0,
-- C_WR_REC_TIME_MEM_1,
-- C_WR_REC_TIME_MEM_2,
-- C_WR_REC_TIME_MEM_3
-- );
constant C_FLASH_TYPE_MEM : EMC_ARRAY_TYPE :=
(C_MEM0_TYPE,
C_MEM1_TYPE,
C_MEM2_TYPE,
C_MEM3_TYPE);
-------------------------------------------------------------------------------
-- Create global constants that indicate if any data matching is needed or if
-- any memories are synchronous. These can be used to eliminate un-necessary
-- logic.
-------------------------------------------------------------------------------
-- check for any memory in configuration is SYNC type or not.
constant GLOBAL_SYNC_MEM : integer range 0 to 1
:= not_all_zeros(SYNCH_MEM_ARRAY,
C_NUM_BANKS_MEM);
-- check for any memory in configuration needs Data Width Matching or not.
constant GLOBAL_DATAWIDTH_MATCH : integer range 0 to 1
:= not_all_zeros(DATAWIDTH_MATCH_ARRAY,
C_NUM_BANKS_MEM);
-- check for any memory in configuration is Page Mode Flash type or not.
constant PAGEMODE_FLASH : integer range 0 to 1
:= not_all_zeros(C_PAGEMODE_FLASH,
C_NUM_BANKS_MEM);
--constant C_FLASH_SYNC_RD : integer range 0 to 1
-- := flash_supports_sync_rd(C_FLASH_SUPPORTS_SYNC_RD,
-- C_NUM_BANKS_MEM);
-- check for any memory in configuration is parity enabled or not.
-- 0 - no parity
-- 1 - odd parity
-- 2 - even parity
constant PARITY_TYPE_MEMORY : integer range 0 to 2
:= not_all_zeros(MEM_PARITY_TYPE_ARRAY,
C_NUM_BANKS_MEM);
constant FLASH_TYP_MEM : integer range 0 to 1
:= check_flash_mem(C_FLASH_TYPE_MEM,
C_NUM_BANKS_MEM);
-------------------------------------------------------------------------------
-- Memory Cycle Time Calculations
-------------------------------------------------------------------------------
-- Read Cycle (maximum of CE or Address Change to Valid Data)
-- Note: Minimum 1 extra clock is required to interface from the asynchronous
-- environment to a synchronous environment.
-------------------------------------------------------------------------------
-- C_TCEDV_PS_MEM_x:
-- Read cycle chip enable low to data valid duration of memory bank x
-- C_TAVDV_PS_MEM_x:
-- Read cycle address valid to data valid duration of memory bank x
-- CE ----\
-- \-------------
-- _ _ _ _ _ _
-- Addr __/
-- \_ _ _ _ _ _
--
-- TRD_CLKS_x
-- |<------>|
-- _ _ _ _ _
-- Data _ _ _ _ _ __/
-- \_ _ _ _ _
constant TRD_CLKS_0 : integer range 0 to 31
:= ((max2(1,max2(C_TCEDV_PS_MEM_0,
C_TAVDV_PS_MEM_0))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TRD_CLKS_1 : integer range 0 to 31
:= ((max2(1,max2(C_TCEDV_PS_MEM_1,
C_TAVDV_PS_MEM_1))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TRD_CLKS_2 : integer range 0 to 31
:= ((max2(1,max2(C_TCEDV_PS_MEM_2,
C_TAVDV_PS_MEM_2))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TRD_CLKS_3 : integer range 0 to 31
:= ((max2(1,max2(C_TCEDV_PS_MEM_3,
C_TAVDV_PS_MEM_3))-1)/C_BUS_CLOCK_PERIOD_PS);
-- std logic vector counter for rd_clks_x
constant TRDCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_CLKS_0+1, 5);
constant TRDCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_CLKS_1+1, 5);
constant TRDCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_CLKS_2+1, 5);
constant TRDCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_CLKS_3+1, 5);
-----------------------------------------------------------------------------
-- TRD_TPACC_x: Page access time of memory bank x in page mode flash mode
constant TRD_TPACC_0 :integer range 0 to 31 --:= (0);
:= (C_TPACC_PS_FLASH_0/C_BUS_CLOCK_PERIOD_PS);
constant TRD_TPACC_1 :integer range 0 to 31 --:= (0);
:= (C_TPACC_PS_FLASH_1/C_BUS_CLOCK_PERIOD_PS);
constant TRD_TPACC_2 :integer range 0 to 31 --:= (0);
:= (C_TPACC_PS_FLASH_2/C_BUS_CLOCK_PERIOD_PS);
constant TRD_TPACC_3 :integer range 0 to 31 -- := (0);
:= (C_TPACC_PS_FLASH_3/C_BUS_CLOCK_PERIOD_PS);
-- TRD_TPACC_x: std logic vector counter for Page Access Time
constant TPACC_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_TPACC_0+1, 5);
constant TPACC_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_TPACC_1+1, 5);
constant TPACC_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_TPACC_2+1, 5);
constant TPACC_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_TPACC_3+1, 5);
-------------------------------------------------------------------------------
-- Read Cycle End to Data Bus High Impedance
-------------------------------------------------------------------------------
-- C_THZCE_PS_MEM_x:
-- Read cycle chip enable low to data valid duration of memory bank x
-- C_THZOE_PS_MEM_x:
-- Enable high to data bus high impedance duration of memory bank x
-- CE ----\ /--------
-- \-----------xx-------/
-- OE ----\ /--------
-- \-----------xx-------/
-- THZ_CLKS_x
-- |<------->|
-- _ _ _ _ _ _ _ _ _ _ _
-- Data _ _ _ _ _ __/ \_ _ _ _
-- \_ _ _ _ _ _ _ _ _ _ _/
constant THZ_CLKS_0 : integer range 0 to 31
:= ((max2(1,max2(C_THZCE_PS_MEM_0,
C_THZOE_PS_MEM_0))-1)/C_BUS_CLOCK_PERIOD_PS);
constant THZ_CLKS_1 : integer range 0 to 31
:= ((max2(1,max2(C_THZCE_PS_MEM_1,
C_THZOE_PS_MEM_1))-1)/C_BUS_CLOCK_PERIOD_PS);
constant THZ_CLKS_2 : integer range 0 to 31
:= ((max2(1,max2(C_THZCE_PS_MEM_2,
C_THZOE_PS_MEM_2))-1)/C_BUS_CLOCK_PERIOD_PS);
constant THZ_CLKS_3 : integer range 0 to 31
:= ((max2(1,max2(C_THZCE_PS_MEM_3,
C_THZOE_PS_MEM_3))-1)/C_BUS_CLOCK_PERIOD_PS);
-- HZ counter in std logic vector
constant THZCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(THZ_CLKS_0+1, 5);
constant THZCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(THZ_CLKS_1+1, 5);
constant THZCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(THZ_CLKS_2+1, 5);
constant THZCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(THZ_CLKS_3+1, 5);
-------------------------------------------------------------------------------
-- Write Cycle to Data Store
-------------------------------------------------------------------------------
-- C_TWC_PS_MEM_x:
-- Write cycle time of memory bank x
-- C_TWP_PS_MEM_x:
-- Write enable minimum pulse width duration of memory bank x
constant TWR_CLKS_0 : integer range 0 to 31
:= ((max2(1,max2(C_TWC_PS_MEM_0,
C_TWP_PS_MEM_0))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TWR_CLKS_1 : integer range 0 to 31
:= ((max2(1,max2(C_TWC_PS_MEM_1,
C_TWP_PS_MEM_1))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TWR_CLKS_2 : integer range 0 to 31
:= ((max2(1,max2(C_TWC_PS_MEM_2,
C_TWP_PS_MEM_2))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TWR_CLKS_3 : integer range 0 to 31
:= ((max2(1,max2(C_TWC_PS_MEM_3,
C_TWP_PS_MEM_3))-1)/C_BUS_CLOCK_PERIOD_PS);
-- TWRCNT_x: std logic vector counter for Write cycle Time
constant TWRCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWR_CLKS_0, 5);
constant TWRCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWR_CLKS_1, 5);
constant TWRCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWR_CLKS_2, 5);
constant TWRCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWR_CLKS_3, 5);
-------------------------------------------------------------------------------
-- Write Cycle High Period
-------------------------------------------------------------------------------
constant TWPH_CLKS_0 : integer range 0 to 31
:= (C_TWPH_PS_MEM_0/C_BUS_CLOCK_PERIOD_PS);
constant TWPH_CLKS_1 : integer range 0 to 31
:= (C_TWPH_PS_MEM_1/C_BUS_CLOCK_PERIOD_PS);
constant TWPH_CLKS_2 : integer range 0 to 31
:= (C_TWPH_PS_MEM_2/C_BUS_CLOCK_PERIOD_PS);
constant TWPH_CLKS_3 : integer range 0 to 31
:= (C_TWPH_PS_MEM_3/C_BUS_CLOCK_PERIOD_PS);
-- TWPHCNT_x: std logic vector counter for Write Cycle High Time
constant TWPHCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWPH_CLKS_0+1, 5);
constant TWPHCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWPH_CLKS_1+1, 5);
constant TWPHCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWPH_CLKS_2+1, 5);
constant TWPHCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWPH_CLKS_3+1, 5);
------------------------------------------------------------------------------
-- Write Cycle End Data Hold Time
-------------------------------------------------------------------------------
-- C_TLZWE_PS_MEM_x:
-- Write cycle write enable high to data bus low impedance
-- duration of memory bank x
-- WE ----\ /--------
-- \------------/
-- TLZ_CLKS_x
-- |<----->|
-- _ _ _ _ _ _ _ _ _ _ _
-- Data __/ \_ _ _ _
-- \_ _ _ _ _ _ _ _ _ _ _/
constant TLZ_CLKS_0 : integer range 0 to 31
:= ((max2(1,C_TLZWE_PS_MEM_0)-1)/C_BUS_CLOCK_PERIOD_PS);
constant TLZ_CLKS_1 : integer range 0 to 31
:= ((max2(1,C_TLZWE_PS_MEM_1)-1)/C_BUS_CLOCK_PERIOD_PS);
constant TLZ_CLKS_2 : integer range 0 to 31
:= ((max2(1,C_TLZWE_PS_MEM_2)-1)/C_BUS_CLOCK_PERIOD_PS);
constant TLZ_CLKS_3 : integer range 0 to 31
:= ((max2(1,C_TLZWE_PS_MEM_3)-1)/C_BUS_CLOCK_PERIOD_PS);
-- TLZCNT_x: std logic vector counter for Write Cycle End Data Hold Time
constant TLZCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TLZ_CLKS_0+1, 5);
constant TLZCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TLZ_CLKS_1+1, 5);
constant TLZCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TLZ_CLKS_2+1, 5);
constant TLZCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TLZ_CLKS_3+1, 5);
--------------------------------------------------------------
-- Write recovery time for Flash. some idle time is needed for Flash memories
-- after write and begin of next consecutive read cycle.
-- TWR_REC_TIME_x: Write recovery time of memory bank x in flash mode
constant TWR_REC_TIME_0 :integer range 0 to 65535 -- 7/4/2011
:= (C_WR_REC_TIME_MEM_0/C_BUS_CLOCK_PERIOD_PS);
constant TWR_REC_TIME_1 :integer range 0 to 65535
:= (C_WR_REC_TIME_MEM_1/C_BUS_CLOCK_PERIOD_PS);
constant TWR_REC_TIME_2 :integer range 0 to 65535
:= (C_WR_REC_TIME_MEM_2/C_BUS_CLOCK_PERIOD_PS);
constant TWR_REC_TIME_3 :integer range 0 to 65535
:= (C_WR_REC_TIME_MEM_3/C_BUS_CLOCK_PERIOD_PS);
constant TP_WR_REC_CNT_0 : std_logic_vector(0 to 15)
:= conv_std_logic_vector(TWR_REC_TIME_0+1, 16);
constant TP_WR_REC_CNT_1 : std_logic_vector(0 to 15)
:= conv_std_logic_vector(TWR_REC_TIME_1+1, 16);
constant TP_WR_REC_CNT_2 : std_logic_vector(0 to 15)
:= conv_std_logic_vector(TWR_REC_TIME_2+1, 16);
constant TP_WR_REC_CNT_3 : std_logic_vector(0 to 15)
:= conv_std_logic_vector(TWR_REC_TIME_3+1, 16);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- Write Cycle Time
signal twr_data : std_logic_vector(0 to 4);
signal twr_load : std_logic;
signal twr_cnt_en : std_logic;
signal twr_end : std_logic;
-- Write Cycle High Time
signal twph_data : std_logic_vector(0 to 4);
signal twph_load : std_logic;
signal twph_cnt_en : std_logic;
signal twph_end : std_logic;
-- Write Cycle End To Data Bus Low-Z
signal tlz_data : std_logic_vector(0 to 4);
signal tlz_load : std_logic;
signal Tlz_cnt_en : std_logic;
signal tlz_end : std_logic;
-- Read Cycle End To Data Bus High-Z
signal thz_data : std_logic_vector(0 to 4);
signal thz_load : std_logic;
signal Thz_cnt_en : std_logic;
signal thz_end : std_logic;
-- Read Cycle Address Change to Valid Data
signal trd_data : std_logic_vector(0 to 4);
signal trd_load : std_logic;
signal trd_cnt_en : std_logic;
signal trd_end : std_logic;
-- Read Cycle Address Change to Valid Data
signal tpacc_data : std_logic_vector(0 to 4);
signal tpacc_load : std_logic;
signal tpacc_cnt_en : std_logic;
signal tpacc_end : std_logic;
-- Write recovery time for flash
-- signal twr_rec_data : std_logic_vector(0 to 4);--7/4/2011
-- signal twr_rec_load : std_logic;
-- signal twr_rec_cnt_en : std_logic;
-- signal twr_rec_end : std_logic;
signal twr_rec_data_int : std_logic_vector(0 to 15);--7/4/2011
signal twr_rec_load_int : std_logic;
signal twr_rec_cnt_en_int : std_logic;
signal twr_rec_end_int : std_logic;
-- Memory Access IPIC Signals
signal bus2ip_cs_reg : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal bus2ip_cs_reg_d1 : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal cs_Strobe : std_logic;
signal new_page_access : std_logic;
signal Parity_enable : std_logic;
signal Parity_type : std_logic;
signal Parity_err_i : std_logic;
signal bus2Mem_CS : std_logic;
signal bus2Mem_RdReq : std_logic;
signal bus2Mem_WrReq : std_logic;
signal mem2Bus_RdAck : std_logic;
signal mem2Bus_WrAck : std_logic;
signal mem2Bus_RdAddrAck : std_logic;
signal mem2Bus_WrAddrAck : std_logic;
signal mem2Bus_Data : std_logic_vector(0 to C_IPIF_DWIDTH - 1);
signal write_req_ack : std_logic;
signal read_req_ack : std_logic;
signal read_data_en : std_logic;
signal read_ack : std_logic;
-- Memory Control Internal Signals
signal mem_CEN_cmb : std_logic;
signal mem_OEN_cmb : std_logic;
signal mem_WEN_cmb : std_logic;
signal bus2ip_ben_int : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
signal bus2ip_ben_fixed : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
signal mem_a_int : std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal par_error_addr : std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal mem_dq_i_int : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal mem_dq_o_int : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal mem_dq_t_int : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal mem_dq_parity_i_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_dq_parity_o_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_dq_parity_t_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_cen_int : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_oen_int : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_wen_int : std_logic;
signal mem_qwen_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_ben_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_rpn_int : std_logic;
signal mem_ce_int : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_adv_ldn_int : std_logic;
signal mem_lbon_int : std_logic;
signal mem_cken_int : std_logic;
signal mem_rnw_int : std_logic;
signal mem_be_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
-- Data Width Matching Address Management
signal addr_cnt_ce : std_logic;
signal addr_cnt_rst : std_logic;
signal addr_cnt : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal addr_align : std_logic;
signal addr_align_rd : std_logic;
signal addr_align_write : std_logic;
signal CS_par_addr : std_logic;
signal cycle_cnt_en : std_logic;
signal cycle_cnt_ld : std_logic;
signal cycle_End : std_logic;
signal address_strobe : std_logic;
signal data_strobe : std_logic;
-- Access Parameters
signal mem_width_bytes : std_logic_vector(0 to 3);
signal datawidth_match : std_logic;
signal synch_mem1 : std_logic;
signal two_pipe_delay : std_logic;
signal ip2Bus_RdAck_i : std_logic;
signal IP2Bus_errAck_i : std_logic;
signal Mem_Addr_rst : std_logic;
signal transaction_done_i : std_logic;
signal Bus2IP_Mem_CS_i : std_logic;
signal single_transaction : std_logic;
signal temp_parity_error_adrss: std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal last_burst_cnt : std_logic;
signal Write_req_data_ack : std_logic;
signal Write_req_addr_ack : std_logic;
signal address_strobe_c : std_logic;
signal be_strobe_c : std_logic;
signal data_strobe_c : std_logic;
signal pr_state_wait_temp_cmb : std_logic;
signal ns_idle : std_logic;
signal flash_mem_access_int : std_logic;
signal flash_mem_access_int_1 : std_logic;
signal int_Flash_mem_access_dis : std_logic;
signal Adv_L_N : std_logic;
signal stop_oen : std_logic;
signal bus2ip_ben_all_1 : std_logic;-- 12-12-2012
--signal Linear_flash_brst_rd_flag : std_logic;
--signal Linear_flash_rd_data_ack : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
mem_rpn_int <= not Bus2IP_Reset;
mem_adv_ldn_int <= '0';
mem_lbon_int <= '0';
mem_cken_int <= '0';
IP2Bus_RdAck <= ip2Bus_RdAck_i;
IP2Bus_errAck <= IP2Bus_errAck_i;
Parity_err <= Parity_err_i;
Bus2IP_Mem_CS_i <= or_reduce(Bus2IP_Mem_CS);
---------------------------------------------------------------------------
-- Store the Chip Select Coming from IPIF in case C_NUM_BANKS_MEM > 1
---------------------------------------------------------------------------
CS_STORE_GEN: if (C_NUM_BANKS_MEM > 1) generate
begin
CS_STORE_PROCESS:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if Bus2IP_Reset = '1' then
bus2ip_cs_reg_d1 <= (others=>'0');
else
bus2ip_cs_reg_d1 <= bus2ip_cs_reg;
end if;
end if;
end process CS_STORE_PROCESS;
bus2ip_cs_reg <= Bus2IP_Mem_CS when (cs_Strobe = '1')
else
bus2ip_cs_reg_d1;
end generate CS_STORE_GEN;
---------------------------------------------------------------------------
-- Pass on the Chip Select Coming from IPIF in case C_NUM_BANKS_MEM = 1
---------------------------------------------------------------------------
CS_PASS_GEN: if (C_NUM_BANKS_MEM = 1) generate
-----
function int_to_std (flash_type: integer) return std_logic is
begin
if (flash_type = 1) then
return '1';
else
return '0';
end if;
end function;
------------------------------------------------------------------------------
begin
-----
bus2ip_cs_reg <= Bus2IP_Mem_CS;
flash_mem_access_int_1 <= int_to_std(FLASH_TYP_MEM);
end generate CS_PASS_GEN;
------------------------------------------------------------------------------
-- Generate single transaction signals for multiple memory banks.
------------------------------------------------------------------------------
SINGLE_BURST_GEN_PROCESS: process(Bus2IP_Mem_CS,
bus2ip_burst,
Bus2IP_BurstLength)is
-----
begin
-----
single_transaction <= '0';
for i in 0 to C_NUM_BANKS_MEM -1 loop
if(Bus2IP_Mem_CS(i) = '1' and
--bus2ip_burst= '0' and
or_reduce(Bus2IP_BurstLength) = '0') then -- = "00000000") then
single_transaction <= '1';
end if;
end loop;
end process SINGLE_BURST_GEN_PROCESS;
----------------------------------------------------------------
MULTIPLE_MEM_FLASH_ACCESS_GEN: if (C_NUM_BANKS_MEM > 1) generate
-----
begin
-----
REG_FLASH_ACCESS: process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(flash_mem_access_int = '1') then
flash_mem_access_int_1 <= '1';
elsif(Bus2IP_Reset = '1' or int_Flash_mem_access_dis = '1')then
flash_mem_access_int_1 <= '0';
end if;
end if;
end process REG_FLASH_ACCESS;
FLASH_ACCESS_PROCESS: process (Bus2IP_Mem_CS) is
-----
begin
-----
flash_mem_access_int <= '0';
for i in 0 to C_NUM_BANKS_MEM -1 loop
if((Bus2IP_Mem_CS(i) = '1') and
((C_FLASH_TYPE_MEM(i) = 2)or -- check if the memory is flash,page mode flash
(C_FLASH_TYPE_MEM(i) = 3)or
(C_FLASH_TYPE_MEM(i) = 4)or
(C_FLASH_TYPE_MEM(i) = 5)
)) then
flash_mem_access_int <= '1';
--else
-- flash_mem_access_int <= '0';
end if;
end loop;
end process FLASH_ACCESS_PROCESS;
---------------------------------
end generate MULTIPLE_MEM_FLASH_ACCESS_GEN;
-------------------------------------------
-------------------------------------------------------------------------------
-- IPIC Interface
-------------------------------------------------------------------------------
IPIC_IF_I : entity emc_common_v3_0.ipic_if
generic map (
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM,
C_IPIF_DWIDTH => C_IPIF_DWIDTH
)
port map (
Bus2IP_Clk => Bus2IP_Clk ,
Bus2IP_Reset => Bus2IP_Reset ,
Bus2IP_RNW => Bus2IP_RNW ,-- in std_logic;
Bus2IP_Mem_CS => Bus2IP_Mem_CS ,-- in std_logic_vector
Mem2Bus_RdAddrAck => mem2Bus_RdAddrAck ,-- in std_logic;
Mem2Bus_WrAddrAck => mem2Bus_WrAddrAck ,-- in std_logic;
Mem2Bus_RdAck => mem2Bus_RdAck ,-- in std_logic;
Mem2Bus_WrAck => mem2Bus_WrAck ,-- in std_logic;
Mem2Bus_Data => mem2Bus_Data ,-- in std_logic;
Bus2IP_WrReq => Bus2IP_WrReq ,-- in std_logic;
Bus2IP_RdReq => Bus2IP_RdReq ,-- in std_logic_vector
Bus2IP_Burst => bus2ip_burst ,-- in std_logic;
Bus2IP_RdReq_emc => Bus2IP_RdReq_emc ,-- in std_logic;
Bus2IP_WrReq_emc => Bus2IP_WrReq_emc ,-- in std_logic;
Bus2Mem_CS => bus2Mem_CS ,-- out std_logic;
Bus2Mem_RdReq => bus2Mem_RdReq ,-- out std_logic;
Bus2Mem_WrReq => bus2Mem_WrReq ,-- out std_logic;
Parity_err => Parity_err_i ,-- in std_logic;
IP2Bus_Data => IP2Bus_Data ,-- out std_logic_vector
IP2Bus_errAck => IP2Bus_errAck_i ,-- out std_logic;
IP2Bus_retry => IP2Bus_retry ,-- out std_logic;
IP2Bus_toutSup => IP2Bus_toutSup ,-- out std_logic;
IP2Bus_RdAck => ip2Bus_RdAck_i ,-- out std_logic;
IP2Bus_WrAck => IP2Bus_WrAck ,-- out std_logic;
IP2Bus_AddrAck => IP2Bus_AddrAck ,-- out std_logic;
Type_of_xfer => Type_of_xfer ,-- in std_logic;
Burst_length => Bus2IP_BurstLength ,-- in std_logic_vector(
Transaction_done => transaction_done_i ,-- in std_logic;
single_transaction=> single_transaction ,-- in std_logic;
last_burst_cnt => last_burst_cnt ,-- out std_logic;
pr_state_wait_temp_cmb => pr_state_wait_temp_cmb ,
Synch_mem => synch_mem1 ,
Mem_width_bytes => mem_width_bytes , -- 10-12-2012
stop_oen => stop_oen , -- 10-12-2012
axi_trans_size_reg => axi_trans_size_reg ,-- 1/3/2013
Linear_flash_brst_rd_flag=> Linear_flash_brst_rd_flag -- 1/28/2013
);
-------------------------------------------------------------------------------
-- Memory State Machine
-------------------------------------------------------------------------------
MEM_STATE_MACHINE_I : entity emc_common_v3_0.mem_state_machine
port map (
Clk => Bus2IP_Clk,
Rst => Bus2IP_Reset,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_RdReq => bus2Mem_RdReq,
Bus2IP_WrReq => Bus2Mem_WrReq,
original_wrce => original_wrce,
--flash_mem_access => flash_mem_access_int,
Synch_mem => synch_mem1,
Two_pipe_delay => two_pipe_delay,
Cycle_End => cycle_End,
Bus2IP_Mem_CS => Bus2IP_Mem_CS_i,
Bus2IP_Burst => bus2ip_burst,
Read_data_en => read_data_en,
Read_ack => read_ack,
Address_strobe => address_strobe,
-- Data_strobe => data_strobe,09-12-2012
CS_Strobe => cs_Strobe,
axi_wvalid => axi_wvalid,
axi_wlast => axi_wlast,
Addr_cnt_ce => addr_cnt_ce,
Addr_cnt_rst => addr_cnt_rst,
Cycle_cnt_ld => cycle_cnt_ld,
Cycle_cnt_en => cycle_cnt_en,
single_trans => single_transaction,
Trd_cnt_en => trd_cnt_en,
Twr_cnt_en => twr_cnt_en,
Twph_cnt_en => twph_cnt_en,
Tpacc_cnt_en => tpacc_cnt_en,
Trd_load => trd_load,
Twr_load => twr_load,
Twph_load => twph_load,
Tpacc_load => tpacc_load,
Thz_load => thz_load,
Tlz_load => tlz_load,
Trd_end => trd_end,
Twr_end => twr_end,
Twph_end => twph_end,
Thz_end => thz_end,
Tlz_end => tlz_end,
Tpacc_end => Tpacc_end,
New_page_access => new_page_access,
Linear_flash_brst_rd_flag => Linear_flash_brst_rd_flag,
Linear_flash_rd_data_ack => Linear_flash_rd_data_ack,
MSM_Mem_CEN => mem_CEN_cmb,
MSM_Mem_OEN => mem_OEN_cmb,
MSM_Mem_WEN => mem_WEN_cmb,
CS_Strobe_par_addr => CS_par_addr,
Addr_align => addr_align_write,
Addr_align_rd => addr_align_rd,
Write_req_ack => write_req_ack,
Read_req_ack => read_req_ack,
Transaction_done => transaction_done_i,
Mem_Addr_rst => Mem_Addr_rst,
last_burst_cnt => last_burst_cnt,
Write_req_data_ack => Write_req_data_ack,
Write_req_addr_ack => Write_req_addr_ack,
address_strobe_c => address_strobe_c,
be_strobe_c => be_strobe_c,
data_strobe_c => data_strobe_c,
ns_idle => ns_idle ,
pr_state_wait_temp_cmb => pr_state_wait_temp_cmb,
Twr_rec_load => twr_rec_load_int ,
Twr_rec_cnt_en => twr_rec_cnt_en_int,
Twr_rec_end => twr_rec_end_int,
Flash_mem_access_disable => int_Flash_mem_access_dis, --
Flash_mem_access => flash_mem_access_int_1, --Flash_mem_access_int
Mem_WAIT => Mem_WAIT,
Adv_L_N => Adv_L_N,
Bus2IP_RdReq_emc => Bus2IP_RdReq_emc, -- 17-10-2012
last_addr1 => last_addr1,
stop_oen => stop_oen,
pr_idle => pr_idle, -- 11-12-2012
bus2ip_ben_all_1 => bus2ip_ben_all_1
--Linear_flash_brst_rd_flag => Linear_flash_brst_rd_flag,
--Linear_flash_rd_data_ack => Linear_flash_rd_data_ack
);
bus2ip_ben_fixed <= (others=>'0') when Type_of_xfer = '0'
else
Bus2IP_BE;
bus2ip_ben_all_1 <= and_reduce(Bus2IP_BE);-- 13-12-2012
parity_error_adrss <= temp_parity_error_adrss when (ip2Bus_RdAck_i = '1' and IP2Bus_errAck_i = '1') else (others => '0');
-------------------------------------------------------------------------------
-- Datawidth Matching Address Counter
-------------------------------------------------------------------------------
ADDR_COUNTER_MUX_I : entity emc_common_v3_0.addr_counter_mux
generic map (
C_ADDR_CNTR_WIDTH => ADDR_CNTR_WIDTH,
C_IPIF_DWIDTH => C_IPIF_DWIDTH,
C_IPIF_AWIDTH => C_IPIF_AWIDTH,
C_ADDR_OFFSET => ADDR_OFFSET,
PARITY_TYPE_MEMORY => PARITY_TYPE_MEMORY,
C_GLOBAL_DATAWIDTH_MATCH => GLOBAL_DATAWIDTH_MATCH
)
port map (
Clk => Bus2IP_Clk,
Rst => Bus2IP_Reset,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_BE => bus2ip_ben_fixed,
Address_strobe => address_strobe,
--Data_strobe => data_strobe,09-12-2012
Mem_width_bytes => mem_width_bytes,
Datawidth_match => datawidth_match,
Bus2Mem_CS => bus2Mem_CS,
Addr_cnt_ce => addr_cnt_ce,
Addr_cnt_rst => addr_cnt_rst,
Addr_cnt => addr_cnt,
Addr_align => addr_align_write,
CS_par_addr => CS_par_addr,
par_error_addr => temp_parity_error_adrss,
Cycle_cnt_ld => cycle_cnt_ld,
Cycle_cnt_en => cycle_cnt_en,
Cycle_End => cycle_End,
Mem_addr => Mem_A_int,
Mem_Ben => bus2ip_ben_int,
address_strobe_c => address_strobe_c,
be_strobe_c => be_strobe_c ,
data_strobe_c => data_strobe_c,
Cre_reg_en => Cre_reg_en,
Bus2IP_RdReq => bus2Mem_RdReq, -- 17-10-2012
psram_page_mode => psram_page_mode,
axi_trans_size_reg => axi_trans_size_reg -- 1/17/2013
);
-------------------------------------------------------------------------------
-- Asynchronous Memory Cycle Timers
-------------------------------------------------------------------------------
COUNTERS_I: entity emc_common_v3_0.counters
port map (
Synch_mem => synch_mem1,
Twr_data => twr_data,
Twr_load => twr_load,
Twr_cnt_en => twr_cnt_en,
twph_data => twph_data,
twph_load => twph_load,
twph_cnt_en => twph_cnt_en,
Tlz_data => tlz_data,
Tlz_load => tlz_load,
Trd_data => trd_data,
Trd_load => trd_load,
Trd_cnt_en => trd_cnt_en,
Tpacc_data => tpacc_data,
Tpacc_load => tpacc_load,
Tpacc_cnt_en => tpacc_cnt_en,
Thz_data => thz_data,
Thz_load => thz_load,
Twr_end => twr_end,
Twph_end => twph_end,
Tlz_end => tlz_end,
Trd_end => trd_end,
Thz_end => thz_end,
Tpacc_end => Tpacc_end,
--------------------------
Twr_rec_data => twr_rec_data_int ,
Twr_rec_load => twr_rec_load_int ,
Twr_rec_cnt_en => twr_rec_cnt_en_int,
Twr_rec_end => twr_rec_end_int ,
--------------------------
Clk => Bus2IP_Clk,
Rst => Bus2IP_Reset
);
-------------------------------------------------------------------------------
-- Memory Paramter Selector
-------------------------------------------------------------------------------
SELECT_PARAM_I: entity emc_common_v3_0.select_param
generic map (
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM,
C_GLOBAL_SYNC_MEM => GLOBAL_SYNC_MEM,
C_SYNCH_MEM_0 => C_SYNCH_MEM_0,
C_SYNCH_MEM_1 => C_SYNCH_MEM_1,
C_SYNCH_MEM_2 => C_SYNCH_MEM_2,
C_SYNCH_MEM_3 => C_SYNCH_MEM_3,
C_MEM0_WIDTH => C_MEM0_WIDTH,
C_MEM1_WIDTH => C_MEM1_WIDTH,
C_MEM2_WIDTH => C_MEM2_WIDTH,
C_MEM3_WIDTH => C_MEM3_WIDTH,
C_PAGEMODE_FLASH => PAGEMODE_FLASH,
C_PAGEMODE_FLASH_0 => C_PAGEMODE_FLASH_0,
C_PAGEMODE_FLASH_1 => C_PAGEMODE_FLASH_1,
C_PAGEMODE_FLASH_2 => C_PAGEMODE_FLASH_2,
C_PAGEMODE_FLASH_3 => C_PAGEMODE_FLASH_3,
PARITY_TYPE_MEMORY => PARITY_TYPE_MEMORY,
C_PARITY_TYPE_0 => C_PARITY_TYPE_0,
C_PARITY_TYPE_1 => C_PARITY_TYPE_1,
C_PARITY_TYPE_2 => C_PARITY_TYPE_2,
C_PARITY_TYPE_3 => C_PARITY_TYPE_3,
C_SYNCH_PIPEDELAY_0 => C_SYNCH_PIPEDELAY_0,
C_SYNCH_PIPEDELAY_1 => C_SYNCH_PIPEDELAY_1,
C_SYNCH_PIPEDELAY_2 => C_SYNCH_PIPEDELAY_2,
C_SYNCH_PIPEDELAY_3 => C_SYNCH_PIPEDELAY_3,
C_GLOBAL_DATAWIDTH_MATCH => GLOBAL_DATAWIDTH_MATCH,
C_INCLUDE_DATAWIDTH_MATCHING_0 => C_INCLUDE_DATAWIDTH_MATCHING_0,
C_INCLUDE_DATAWIDTH_MATCHING_1 => C_INCLUDE_DATAWIDTH_MATCHING_1,
C_INCLUDE_DATAWIDTH_MATCHING_2 => C_INCLUDE_DATAWIDTH_MATCHING_2,
C_INCLUDE_DATAWIDTH_MATCHING_3 => C_INCLUDE_DATAWIDTH_MATCHING_3,
TRDCNT_0 => TRDCNT_0,
TRDCNT_1 => TRDCNT_1,
TRDCNT_2 => TRDCNT_2,
TRDCNT_3 => TRDCNT_3,
THZCNT_0 => THZCNT_0,
THZCNT_1 => THZCNT_1,
THZCNT_2 => THZCNT_2,
THZCNT_3 => THZCNT_3,
TWRCNT_0 => TWRCNT_0,
TWRCNT_1 => TWRCNT_1,
TWRCNT_2 => TWRCNT_2,
TWRCNT_3 => TWRCNT_3,
TWPHCNT_0 => TWPHCNT_0,
TWPHCNT_1 => TWPHCNT_1,
TWPHCNT_2 => TWPHCNT_2,
TWPHCNT_3 => TWPHCNT_3,
C_IPIF_AWIDTH => C_IPIF_AWIDTH,
C_IPIF_DWIDTH => C_IPIF_DWIDTH,
TPACC_0 => TPACC_0,
TPACC_1 => TPACC_1,
TPACC_2 => TPACC_2,
TPACC_3 => TPACC_3,
TLZCNT_0 => TLZCNT_0,
TLZCNT_1 => TLZCNT_1,
TLZCNT_2 => TLZCNT_2,
TLZCNT_3 => TLZCNT_3,
TP_WR_REC_CNT_0 => TP_WR_REC_CNT_0,--7/4/2011
TP_WR_REC_CNT_1 => TP_WR_REC_CNT_1,
TP_WR_REC_CNT_2 => TP_WR_REC_CNT_2,
TP_WR_REC_CNT_3 => TP_WR_REC_CNT_3
)
port map (
Bus2IP_Mem_CS => bus2ip_cs_reg,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
Bus2IP_RNW => Bus2IP_RNW,
psram_page_mode => psram_page_mode,
New_page_access => new_page_access,
Parity_enable => Parity_enable,
Parity_type => Parity_type,
Twr_data => twr_data,
Twph_data => twph_data,
Tlz_data => tlz_data,
Trd_data => trd_data,
Thz_data => thz_data,
Tpacc_data => tpacc_data,
Twr_rec_data => twr_rec_data_int,-- 9/6/2011
Synch_mem => synch_mem1,
Mem_width_bytes => mem_width_bytes,
Two_pipe_delay => two_pipe_delay,
Datawidth_match => datawidth_match
);
-------------------------------------------------------------------------------
-- Memory Data/Control Steering Logic
-------------------------------------------------------------------------------
MEM_STEER_I : entity emc_common_v3_0.mem_steer
generic map(
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM,
C_MAX_MEM_WIDTH => C_MAX_MEM_WIDTH,
C_MIN_MEM_WIDTH => MIN_MEM_WIDTH,
C_IPIF_DWIDTH => C_IPIF_DWIDTH,
C_IPIF_AWIDTH => C_IPIF_AWIDTH,
C_ADDR_CNTR_WIDTH => ADDR_CNTR_WIDTH,
C_PARITY_TYPE_MEMORY => PARITY_TYPE_MEMORY,
C_GLOBAL_SYNC_MEM => GLOBAL_SYNC_MEM,
C_GLOBAL_DATAWIDTH_MATCH => GLOBAL_DATAWIDTH_MATCH
)
port map(
--
--Clk => Bus2IP_Clk,
--Rst => Bus2IP_Reset
Clk => Bus2IP_Clk,
Rst => Bus2IP_Reset,
Bus2IP_Data => Bus2IP_Data, -- in std_logic_vector
Bus2IP_BE => bus2ip_ben_int, -- in std_logic_vector
Bus2IP_Mem_CS => bus2ip_cs_reg, -- in std_logic_vector
Bus2IP_RdReq => bus2Mem_RdReq, -- in std_logic;
Bus2IP_Burst => bus2ip_burst, -- in std_logic;
Write_req_ack => write_req_ack, -- in std_logic;
Read_req_ack => read_req_ack, -- in std_logic;
Read_ack => read_ack, -- in std_logic;
Read_data_en => read_data_en, -- in std_logic;
--Data_strobe => data_strobe, -- in std_logic;09-12-2012
MSM_Mem_CEN => mem_CEN_cmb, -- in std_logic;
MSM_Mem_OEN => mem_OEN_cmb, -- in std_logic;
MSM_Mem_WEN => mem_WEN_cmb, -- in std_logic;
Mem2Bus_WrAddrAck => mem2Bus_WrAddrAck,-- out std_logic;
Mem2Bus_WrAck => mem2Bus_WrAck, -- out std_logic;
Mem2Bus_RdAddrAck => mem2Bus_RdAddrAck,-- out std_logic;
Mem2Bus_RdAck => mem2Bus_RdAck, -- out std_logic;
Mem2Bus_Data => mem2Bus_Data, -- out std_logic_vector
Mem_width_bytes => mem_width_bytes, -- in std_logic_vector
Synch_mem => synch_mem1, -- in std_logic;
Two_pipe_delay => two_pipe_delay, -- in std_logic;
single_transaction => single_transaction,-- in std_logic;
Parity_enable => Parity_enable, -- out std_logic_vector
Parity_type => Parity_type, -- in std_logic;
parity_error_mem => parity_error_mem, -- in std_logic;
Parity_err => Parity_err_i, -- out std_logic;
Addr_cnt => addr_cnt, -- in std_logic_vector
Addr_align => addr_align_write, -- in std_logic
Addr_align_rd => addr_align_rd, -- in std_logic
MemSteer_Mem_DQ_I => mem_dq_i_int, -- in std_logic_vector
MemSteer_Mem_DQ_O => mem_dq_o_int, -- out std_logic_vector
MemSteer_Mem_DQ_T => mem_dq_t_int, -- out std_logic_vector
MemSteer_Mem_DQ_prty_I => mem_dq_parity_i_int,-- in std_logic_vector
MemSteer_Mem_DQ_prty_O => mem_dq_parity_o_int,-- out std_logic_vector
MemSteer_Mem_DQ_prty_T => mem_dq_parity_t_int,-- out std_logic_vector
MemSteer_Mem_CEN => mem_cen_int, -- out std_logic_vector
MemSteer_Mem_OEN => mem_oen_int, -- out std_logic_vector
MemSteer_Mem_WEN => mem_wen_int, -- out std_logic
MemSteer_Mem_QWEN => mem_qwen_int, -- out std_logic_vector
MemSteer_Mem_BEN => mem_ben_int, -- out std_logic_vector
MemSteer_Mem_CE => mem_ce_int, -- out std_logic_vector
MemSteer_Mem_RNW => mem_rnw_int, -- out std_logic
Bus2IP_RdReq_emc => Bus2IP_RdReq_emc, -- in std_logic;
Bus2IP_WrReq_emc => Bus2IP_WrReq_emc, -- in std_logic;
Write_req_data_ack => Write_req_data_ack,
Write_req_addr_ack => Write_req_addr_ack,
address_strobe_c => address_strobe_c, --- in
be_strobe_c => be_strobe_c , -- in
data_strobe_c => data_strobe_c, -- in
ns_idle => ns_idle , -- in
Linear_flash_brst_rd_flag => Linear_flash_brst_rd_flag,
Linear_flash_rd_data_ack => Linear_flash_rd_data_ack,
last_addr => last_addr1, -- 10-12-2012
stop_oen => stop_oen ,-- 10-12-2012
cycle_end => cycle_End ,
axi_arsize => axi_arsize,
axi_trans_size_reg => axi_trans_size_reg
);
-------------------------------------------------------------------------------
-- Instantiate the IO register block to memory
-- IO registers will be instantiated based on the parameter settings
-------------------------------------------------------------------------------
IO_REGISTERS_I: entity emc_common_v3_0.io_registers
generic map (
--C_FLASH_SYNC_RD => C_FLASH_SYNC_RD,
C_INCLUDE_NEGEDGE_IOREGS => C_INCLUDE_NEGEDGE_IOREGS,
C_IPIF_AWIDTH => C_IPIF_AWIDTH,
C_MAX_MEM_WIDTH => C_MAX_MEM_WIDTH,
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM
)
port map (
Linear_flash_brst_rd_flag=> Linear_flash_brst_rd_flag, -- 1/28/2013
Clk => Bus2IP_Clk, --in std_logic
RdClk => RdClk, --in std_logic
Rst => Bus2IP_Reset, --in std_logic
Mem_A_int => mem_a_int, --in std_logic_vector
Mem_DQ_I_int => mem_dq_i_int, --out std_logic_vector
Mem_DQ_O_int => mem_dq_o_int, --in std_logic_vector
Mem_DQ_T_int => mem_dq_t_int, --in std_logic_vector
Mem_DQ_PARITY_I_int => mem_dq_parity_i_int, --out std_logic_vector
Mem_DQ_PARITY_O_int => mem_dq_parity_o_int, --in std_logic_vector
Mem_DQ_PARITY_T_int => mem_dq_parity_t_int, --in std_logic_vector
Mem_CEN_int => mem_cen_int, --in std_logic_vector
Mem_OEN_int => mem_oen_int, --in std_logic_vector
Mem_WEN_int => mem_wen_int, --in std_logic;
Mem_QWEN_int => mem_qwen_int, --in std_logic_vector
Mem_BEN_int => mem_ben_int, --in std_logic_vector
Mem_RPN_int => mem_rpn_int, --in std_logic;
Mem_CE_int => mem_ce_int, --in std_logic_vector
Mem_ADV_LDN_int => mem_adv_ldn_int, --in std_logic;
Mem_LBON_int => mem_lbon_int, --in std_logic;
Mem_CKEN_int => mem_cken_int, --in std_logic;
Mem_RNW_int => mem_rnw_int, --in std_logic;
Mem_Addr_rst => Mem_Addr_rst, --in std_logic
--Linear_flash_rd_data_ack => Linear_flash_rd_data_ack, -- out std_logic;
Mem_A => Mem_A, --out std_logic_vector
Mem_DQ_I => Mem_DQ_I, --in std_logic_vector
Mem_DQ_O => Mem_DQ_O, --out std_logic_vector
Mem_DQ_T => Mem_DQ_T, --out std_logic_vector
Mem_DQ_PRTY_I => Mem_DQ_PRTY_I, --in std_logic_vector
Mem_DQ_PRTY_O => Mem_DQ_PRTY_O, --out std_logic_vector
Mem_DQ_PRTY_T => Mem_DQ_PRTY_T, --out std_logic_vector
Mem_CEN => Mem_CEN, --out std_logic_vector
Mem_OEN => Mem_OEN, --out std_logic_vector
Mem_WEN => Mem_WEN, --out std_logic;
Mem_QWEN => Mem_QWEN, --out std_logic_vector
Mem_BEN => Mem_BEN, --out std_logic_vector
Mem_RPN => Mem_RPN, --out std_logic;
Mem_CE => Mem_CE, --out std_logic_vector
Mem_ADV_LDN => Mem_ADV_LDN, --out std_logic;
Mem_LBON => Mem_LBON, --out std_logic;
Mem_CKEN => Mem_CKEN, --out std_logic;
Mem_RNW => Mem_RNW --out std_logic
--Mem_WAIT => Mem_WAIT, --in std_logic
--Mem_Flash_clk => Mem_Flash_clk --in std_logic
);
synch_mem12 <= synch_mem1;
end architecture imp;
-------------------------------------------------------------------------------
-- End of File emc.vhd
-------------------------------------------------------------------------------
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/ld_arith_reg.vhd | 8 | 14864 | -- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 08/01 -- First version
--
-- FO 11/14/01 -- Cosmetic improvements
--
-- FO 02/22/02 -- Switched from MUXCY_L primitive to MUXCY.
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end ld_arith_reg;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP;
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
-- Adder case
------------------------------------------------------------------------
Q_I_GEN_ADD: if C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case
------------------------------------------------------------------------
Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= LOAD or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/a3d1bdff/hdl/src/vhdl/uartlite_rx.vhd | 6 | 24708 | -------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_rx.vhd
-- Version: v2.0
-- Description: UART Lite Receive Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_srl_fifo_v1_0;
library lib_cdc_v1_0;
use lib_cdc_v1_0.cdc_sync;
-- dynshreg_i_f refered from proc_common_v4_0
-- srl_fifo_f refered from proc_common_v4_0
use lib_srl_fifo_v1_0.srl_fifo_f;
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
--
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- RX -- Receive Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Read_RX_FIFO -- Read receive FIFO
-- Reset_RX_FIFO -- Reset receive FIFO
-- RX_Data -- Receive data output
-- RX_Data_Present -- Receive data present
-- RX_Buffer_Full -- Receive buffer full
-- RX_Frame_Error -- Receive frame error
-- RX_Overrun_Error -- Receive overrun error
-- RX_Parity_Error -- Receive parity error
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_rx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
RX : in std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_DATA_BITS-1);
RX_Data_Present : out std_logic;
RX_Buffer_Full : out std_logic;
RX_Frame_Error : out std_logic;
RX_Overrun_Error : out std_logic;
RX_Parity_Error : out std_logic
);
end entity uartlite_rx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_rx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant SERIAL_TO_PAR_LENGTH : integer :=
C_DATA_BITS + C_USE_PARITY;
constant STOP_BIT_POS : integer := SERIAL_TO_PAR_LENGTH;
constant DATA_LSB_POS : integer := SERIAL_TO_PAR_LENGTH;
constant CALC_PAR_POS : integer := SERIAL_TO_PAR_LENGTH;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
signal start_Edge_Detected : boolean;
signal start_Edge_Detected_Bit : std_logic;
signal running : boolean;
signal recycle : std_logic;
signal sample_Point : std_logic;
signal stop_Bit_Position : std_logic;
signal fifo_Write : std_logic;
signal fifo_din : std_logic_vector(0 to SERIAL_TO_PAR_LENGTH);
signal serial_to_Par : std_logic_vector(1 to SERIAL_TO_PAR_LENGTH);
signal calc_parity : std_logic;
signal parity : std_logic;
signal RX_Buffer_Full_I : std_logic;
signal RX_D1 : std_logic;
signal RX_D2 : std_logic;
signal rx_1 : std_logic;
signal rx_2 : std_logic;
signal rx_3 : std_logic;
signal rx_4 : std_logic;
signal rx_5 : std_logic;
signal rx_6 : std_logic;
signal rx_7 : std_logic;
signal rx_8 : std_logic;
signal rx_9 : std_logic;
signal rx_Data_Empty : std_logic := '0';
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal RX_FIFO_Reset : std_logic;
signal valid_rx : std_logic;
signal valid_start : std_logic;
signal frame_err_ocrd : std_logic;
signal frame_err : std_logic;
begin -- architecture RTL
---------------------------------------------------------------------------
-- RX_SAMPLING : Double sample RX to avoid meta-stability
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => RX,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => RX_D2,
scndry_vect_out => open
);
-- RX_SAMPLING: process (Clk) is
-- begin -- process RX_Sampling
-- if Clk'event and Clk = '1' then -- rising clock edge
-- if Reset = '1' then -- synchronous reset (active high)
-- RX_D1 <= '1';
-- RX_D2 <= '1';
-- else
-- RX_D1 <= RX;
-- RX_D2 <= RX_D1;
-- end if;
-- end if;
-- end process RX_SAMPLING;
-------------------------------------------------------------------------------
-- Detect a falling edge on RX and start a new reception if idle
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- detect the start of the frame
---------------------------------------------------------------------------
RX_DFFS : process (Clk) is
begin -- process Prev_RX_DFFS
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
rx_1 <= '0';
rx_2 <= '0';
rx_3 <= '0';
rx_4 <= '0';
rx_5 <= '0';
rx_6 <= '0';
rx_7 <= '0';
rx_8 <= '0';
rx_9 <= '0';
elsif (EN_16x_Baud = '1') then
rx_1 <= RX_D2;
rx_2 <= rx_1;
rx_3 <= rx_2;
rx_4 <= rx_3;
rx_5 <= rx_4;
rx_6 <= rx_5;
rx_7 <= rx_6;
rx_8 <= rx_7;
rx_9 <= rx_8;
end if;
end if;
end process RX_DFFS;
---------------------------------------------------------------------------
-- Start bit valid when RX is continuously low for atleast 8 samples
---------------------------------------------------------------------------
valid_start <= rx_8 or rx_7 or rx_6 or rx_5 or
rx_4 or rx_3 or rx_2 or rx_1;
---------------------------------------------------------------------------
-- START_EDGE_DFF : Start a new reception if idle
---------------------------------------------------------------------------
START_EDGE_DFF : process (Clk) is
begin -- process Start_Edge_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
start_Edge_Detected <= false;
elsif (EN_16x_Baud = '1') then
start_Edge_Detected <= ((not running) and
(frame_err_ocrd = '0') and
(rx_9 = '1') and
(valid_start = '0'));
end if;
end if;
end process START_EDGE_DFF;
---------------------------------------------------------------------------
-- FRAME_ERR_CAPTURE : frame_err_ocrd is '1' when a frame error is occured
-- and deasserted when the next low to high on RX
---------------------------------------------------------------------------
FRAME_ERR_CAPTURE : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
frame_err_ocrd <= '0';
elsif (frame_err = '1') then
frame_err_ocrd <= '1';
elsif (RX_D2 = '1') then
frame_err_ocrd <= '0';
end if;
end if;
end process FRAME_ERR_CAPTURE;
---------------------------------------------------------------------------
-- VALID_XFER : valid_rx is '1' when a valid start edge detected
---------------------------------------------------------------------------
VALID_XFER : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
valid_rx <= '0';
elsif (start_Edge_Detected = true) then
valid_rx <= '1';
elsif (fifo_Write = '1') then
valid_rx <= '0';
end if;
end if;
end process VALID_XFER;
---------------------------------------------------------------------------
-- RUNNING_DFF : Running is '1' during a reception
---------------------------------------------------------------------------
RUNNING_DFF : process (Clk) is
begin -- process Running_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
running <= false;
elsif (EN_16x_Baud = '1') then
if (start_Edge_Detected) then
running <= true;
elsif ((sample_Point = '1') and (stop_Bit_Position = '1')) then
running <= false;
end if;
end if;
end if;
end process RUNNING_DFF;
---------------------------------------------------------------------------
-- Boolean to std logic conversion of start edge
---------------------------------------------------------------------------
start_Edge_Detected_Bit <= '1' when start_Edge_Detected else '0';
---------------------------------------------------------------------------
-- After the start edge is detected, generate recycle to generate sample
-- point
---------------------------------------------------------------------------
recycle <= (valid_rx and (not stop_Bit_Position) and
(start_Edge_Detected_Bit or sample_Point));
-------------------------------------------------------------------------
-- DELAY_16_I : Keep regenerating new values into the 16 clock delay,
-- Starting with the first start_Edge_Detected_Bit and for every new
-- sample_points until stop_Bit_Position is reached
-------------------------------------------------------------------------
DELAY_16_I : entity axi_uartlite_v2_0.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => recycle,
Dout(0) => sample_Point
);
---------------------------------------------------------------------------
-- STOP_BIT_HANDLER : Detect when the stop bit is received
---------------------------------------------------------------------------
STOP_BIT_HANDLER : process (Clk) is
begin -- process Stop_Bit_Handler
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
stop_Bit_Position <= '0';
elsif (EN_16x_Baud = '1') then
if (stop_Bit_Position = '0') then
-- Start bit has reached the end of the shift register
-- (Stop bit position)
stop_Bit_Position <= sample_Point and
fifo_din(STOP_BIT_POS);
elsif (sample_Point = '1') then
-- if stop_Bit_Position is 1 clear it at next sample_Point
stop_Bit_Position <= '0';
end if;
end if;
end if;
end process STOP_BIT_HANDLER;
USING_PARITY_NO : if (C_USE_PARITY = 0) generate
RX_Parity_Error <= '0' ;
end generate USING_PARITY_NO;
---------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
---------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1' or start_Edge_Detected_Bit = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (EN_16x_Baud = '1') then
parity <= calc_parity;
end if;
end if;
end process PARITY_DFF;
calc_parity <= parity when (stop_Bit_Position or
(not sample_Point)) = '1'
else parity xor RX_D2;
RX_Parity_Error <= (EN_16x_Baud and sample_Point) and
(fifo_din(CALC_PAR_POS)) and not stop_Bit_Position
when running and (RX_D2 /= parity) else '0';
end generate USING_PARITY;
fifo_din(0) <= RX_D2 and not Reset;
---------------------------------------------------------------------------
-- SERIAL_TO_PARALLEL : Serial to parrallel conversion data part
---------------------------------------------------------------------------
SERIAL_TO_PARALLEL : for i in 1 to serial_to_Par'length generate
serial_to_Par(i) <= fifo_din(i) when (stop_Bit_Position or
not sample_Point) = '1'
else fifo_din(i-1);
BIT_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
fifo_din(i) <= '0'; -- Bit STOP_BIT_POS resets to '0';
else -- others to '1'
if (start_Edge_Detected_Bit = '1') then
fifo_din(i) <= bo2sl(i=1); -- Bit 1 resets to '1';
-- others to '0'
elsif (EN_16x_Baud = '1') then
fifo_din(i) <= serial_to_Par(i);
end if;
end if;
end if;
end process BIT_I;
end generate SERIAL_TO_PARALLEL;
--------------------------------------------------------------------------
-- FIFO_WRITE_DFF : Write in the received word when the stop_bit has been
-- received and it is a '1'
--------------------------------------------------------------------------
FIFO_WRITE_DFF : process (Clk) is
begin -- process FIFO_Write_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Write <= '0';
else
fifo_Write <= stop_Bit_Position and RX_D2 and sample_Point
and EN_16x_Baud;
end if;
end if;
end process FIFO_WRITE_DFF;
frame_err <= stop_Bit_Position and sample_Point and EN_16x_Baud
and not RX_D2;
RX_Frame_Error <= frame_err;
--------------------------------------------------------------------------
-- Write RX FIFO when FIFO is not full when valid data is reveived
--------------------------------------------------------------------------
fifo_wr <= fifo_Write and (not RX_Buffer_Full_I) and valid_rx;
--------------------------------------------------------------------------
-- Read RX FIFO when FIFO is not empty when AXI reads data from RX FIFO
--------------------------------------------------------------------------
fifo_rd <= Read_RX_FIFO and (not rx_Data_Empty);
--------------------------------------------------------------------------
-- Reset RX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
RX_FIFO_Reset <= Reset_RX_FIFO or Reset;
---------------------------------------------------------------------------
-- SRL_FIFO_I : Receive FIFO Interface
---------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => RX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => fifo_din((DATA_LSB_POS-C_DATA_BITS + 1) to DATA_LSB_POS),
FIFO_Read => fifo_rd,
Data_Out => RX_Data,
FIFO_Full => RX_Buffer_Full_I,
FIFO_Empty => rx_Data_Empty,
Addr => open
);
RX_Data_Present <= not rx_Data_Empty;
RX_Overrun_Error <= RX_Buffer_Full_I and fifo_Write; -- Note that if
-- the RX FIFO is read on the same cycle as it is written while full,
-- there is no loss of data. However this case is not optimized and
-- is also reported as an overrun.
RX_Buffer_Full <= RX_Buffer_Full_I;
end architecture RTL;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/a3d1bdff/hdl/src/vhdl/uartlite_rx.vhd | 6 | 24708 | -------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_rx.vhd
-- Version: v2.0
-- Description: UART Lite Receive Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_srl_fifo_v1_0;
library lib_cdc_v1_0;
use lib_cdc_v1_0.cdc_sync;
-- dynshreg_i_f refered from proc_common_v4_0
-- srl_fifo_f refered from proc_common_v4_0
use lib_srl_fifo_v1_0.srl_fifo_f;
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
--
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- RX -- Receive Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Read_RX_FIFO -- Read receive FIFO
-- Reset_RX_FIFO -- Reset receive FIFO
-- RX_Data -- Receive data output
-- RX_Data_Present -- Receive data present
-- RX_Buffer_Full -- Receive buffer full
-- RX_Frame_Error -- Receive frame error
-- RX_Overrun_Error -- Receive overrun error
-- RX_Parity_Error -- Receive parity error
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_rx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
RX : in std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_DATA_BITS-1);
RX_Data_Present : out std_logic;
RX_Buffer_Full : out std_logic;
RX_Frame_Error : out std_logic;
RX_Overrun_Error : out std_logic;
RX_Parity_Error : out std_logic
);
end entity uartlite_rx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_rx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant SERIAL_TO_PAR_LENGTH : integer :=
C_DATA_BITS + C_USE_PARITY;
constant STOP_BIT_POS : integer := SERIAL_TO_PAR_LENGTH;
constant DATA_LSB_POS : integer := SERIAL_TO_PAR_LENGTH;
constant CALC_PAR_POS : integer := SERIAL_TO_PAR_LENGTH;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
signal start_Edge_Detected : boolean;
signal start_Edge_Detected_Bit : std_logic;
signal running : boolean;
signal recycle : std_logic;
signal sample_Point : std_logic;
signal stop_Bit_Position : std_logic;
signal fifo_Write : std_logic;
signal fifo_din : std_logic_vector(0 to SERIAL_TO_PAR_LENGTH);
signal serial_to_Par : std_logic_vector(1 to SERIAL_TO_PAR_LENGTH);
signal calc_parity : std_logic;
signal parity : std_logic;
signal RX_Buffer_Full_I : std_logic;
signal RX_D1 : std_logic;
signal RX_D2 : std_logic;
signal rx_1 : std_logic;
signal rx_2 : std_logic;
signal rx_3 : std_logic;
signal rx_4 : std_logic;
signal rx_5 : std_logic;
signal rx_6 : std_logic;
signal rx_7 : std_logic;
signal rx_8 : std_logic;
signal rx_9 : std_logic;
signal rx_Data_Empty : std_logic := '0';
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal RX_FIFO_Reset : std_logic;
signal valid_rx : std_logic;
signal valid_start : std_logic;
signal frame_err_ocrd : std_logic;
signal frame_err : std_logic;
begin -- architecture RTL
---------------------------------------------------------------------------
-- RX_SAMPLING : Double sample RX to avoid meta-stability
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => RX,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => RX_D2,
scndry_vect_out => open
);
-- RX_SAMPLING: process (Clk) is
-- begin -- process RX_Sampling
-- if Clk'event and Clk = '1' then -- rising clock edge
-- if Reset = '1' then -- synchronous reset (active high)
-- RX_D1 <= '1';
-- RX_D2 <= '1';
-- else
-- RX_D1 <= RX;
-- RX_D2 <= RX_D1;
-- end if;
-- end if;
-- end process RX_SAMPLING;
-------------------------------------------------------------------------------
-- Detect a falling edge on RX and start a new reception if idle
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- detect the start of the frame
---------------------------------------------------------------------------
RX_DFFS : process (Clk) is
begin -- process Prev_RX_DFFS
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
rx_1 <= '0';
rx_2 <= '0';
rx_3 <= '0';
rx_4 <= '0';
rx_5 <= '0';
rx_6 <= '0';
rx_7 <= '0';
rx_8 <= '0';
rx_9 <= '0';
elsif (EN_16x_Baud = '1') then
rx_1 <= RX_D2;
rx_2 <= rx_1;
rx_3 <= rx_2;
rx_4 <= rx_3;
rx_5 <= rx_4;
rx_6 <= rx_5;
rx_7 <= rx_6;
rx_8 <= rx_7;
rx_9 <= rx_8;
end if;
end if;
end process RX_DFFS;
---------------------------------------------------------------------------
-- Start bit valid when RX is continuously low for atleast 8 samples
---------------------------------------------------------------------------
valid_start <= rx_8 or rx_7 or rx_6 or rx_5 or
rx_4 or rx_3 or rx_2 or rx_1;
---------------------------------------------------------------------------
-- START_EDGE_DFF : Start a new reception if idle
---------------------------------------------------------------------------
START_EDGE_DFF : process (Clk) is
begin -- process Start_Edge_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
start_Edge_Detected <= false;
elsif (EN_16x_Baud = '1') then
start_Edge_Detected <= ((not running) and
(frame_err_ocrd = '0') and
(rx_9 = '1') and
(valid_start = '0'));
end if;
end if;
end process START_EDGE_DFF;
---------------------------------------------------------------------------
-- FRAME_ERR_CAPTURE : frame_err_ocrd is '1' when a frame error is occured
-- and deasserted when the next low to high on RX
---------------------------------------------------------------------------
FRAME_ERR_CAPTURE : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
frame_err_ocrd <= '0';
elsif (frame_err = '1') then
frame_err_ocrd <= '1';
elsif (RX_D2 = '1') then
frame_err_ocrd <= '0';
end if;
end if;
end process FRAME_ERR_CAPTURE;
---------------------------------------------------------------------------
-- VALID_XFER : valid_rx is '1' when a valid start edge detected
---------------------------------------------------------------------------
VALID_XFER : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
valid_rx <= '0';
elsif (start_Edge_Detected = true) then
valid_rx <= '1';
elsif (fifo_Write = '1') then
valid_rx <= '0';
end if;
end if;
end process VALID_XFER;
---------------------------------------------------------------------------
-- RUNNING_DFF : Running is '1' during a reception
---------------------------------------------------------------------------
RUNNING_DFF : process (Clk) is
begin -- process Running_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
running <= false;
elsif (EN_16x_Baud = '1') then
if (start_Edge_Detected) then
running <= true;
elsif ((sample_Point = '1') and (stop_Bit_Position = '1')) then
running <= false;
end if;
end if;
end if;
end process RUNNING_DFF;
---------------------------------------------------------------------------
-- Boolean to std logic conversion of start edge
---------------------------------------------------------------------------
start_Edge_Detected_Bit <= '1' when start_Edge_Detected else '0';
---------------------------------------------------------------------------
-- After the start edge is detected, generate recycle to generate sample
-- point
---------------------------------------------------------------------------
recycle <= (valid_rx and (not stop_Bit_Position) and
(start_Edge_Detected_Bit or sample_Point));
-------------------------------------------------------------------------
-- DELAY_16_I : Keep regenerating new values into the 16 clock delay,
-- Starting with the first start_Edge_Detected_Bit and for every new
-- sample_points until stop_Bit_Position is reached
-------------------------------------------------------------------------
DELAY_16_I : entity axi_uartlite_v2_0.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => recycle,
Dout(0) => sample_Point
);
---------------------------------------------------------------------------
-- STOP_BIT_HANDLER : Detect when the stop bit is received
---------------------------------------------------------------------------
STOP_BIT_HANDLER : process (Clk) is
begin -- process Stop_Bit_Handler
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
stop_Bit_Position <= '0';
elsif (EN_16x_Baud = '1') then
if (stop_Bit_Position = '0') then
-- Start bit has reached the end of the shift register
-- (Stop bit position)
stop_Bit_Position <= sample_Point and
fifo_din(STOP_BIT_POS);
elsif (sample_Point = '1') then
-- if stop_Bit_Position is 1 clear it at next sample_Point
stop_Bit_Position <= '0';
end if;
end if;
end if;
end process STOP_BIT_HANDLER;
USING_PARITY_NO : if (C_USE_PARITY = 0) generate
RX_Parity_Error <= '0' ;
end generate USING_PARITY_NO;
---------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
---------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1' or start_Edge_Detected_Bit = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (EN_16x_Baud = '1') then
parity <= calc_parity;
end if;
end if;
end process PARITY_DFF;
calc_parity <= parity when (stop_Bit_Position or
(not sample_Point)) = '1'
else parity xor RX_D2;
RX_Parity_Error <= (EN_16x_Baud and sample_Point) and
(fifo_din(CALC_PAR_POS)) and not stop_Bit_Position
when running and (RX_D2 /= parity) else '0';
end generate USING_PARITY;
fifo_din(0) <= RX_D2 and not Reset;
---------------------------------------------------------------------------
-- SERIAL_TO_PARALLEL : Serial to parrallel conversion data part
---------------------------------------------------------------------------
SERIAL_TO_PARALLEL : for i in 1 to serial_to_Par'length generate
serial_to_Par(i) <= fifo_din(i) when (stop_Bit_Position or
not sample_Point) = '1'
else fifo_din(i-1);
BIT_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
fifo_din(i) <= '0'; -- Bit STOP_BIT_POS resets to '0';
else -- others to '1'
if (start_Edge_Detected_Bit = '1') then
fifo_din(i) <= bo2sl(i=1); -- Bit 1 resets to '1';
-- others to '0'
elsif (EN_16x_Baud = '1') then
fifo_din(i) <= serial_to_Par(i);
end if;
end if;
end if;
end process BIT_I;
end generate SERIAL_TO_PARALLEL;
--------------------------------------------------------------------------
-- FIFO_WRITE_DFF : Write in the received word when the stop_bit has been
-- received and it is a '1'
--------------------------------------------------------------------------
FIFO_WRITE_DFF : process (Clk) is
begin -- process FIFO_Write_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Write <= '0';
else
fifo_Write <= stop_Bit_Position and RX_D2 and sample_Point
and EN_16x_Baud;
end if;
end if;
end process FIFO_WRITE_DFF;
frame_err <= stop_Bit_Position and sample_Point and EN_16x_Baud
and not RX_D2;
RX_Frame_Error <= frame_err;
--------------------------------------------------------------------------
-- Write RX FIFO when FIFO is not full when valid data is reveived
--------------------------------------------------------------------------
fifo_wr <= fifo_Write and (not RX_Buffer_Full_I) and valid_rx;
--------------------------------------------------------------------------
-- Read RX FIFO when FIFO is not empty when AXI reads data from RX FIFO
--------------------------------------------------------------------------
fifo_rd <= Read_RX_FIFO and (not rx_Data_Empty);
--------------------------------------------------------------------------
-- Reset RX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
RX_FIFO_Reset <= Reset_RX_FIFO or Reset;
---------------------------------------------------------------------------
-- SRL_FIFO_I : Receive FIFO Interface
---------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => RX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => fifo_din((DATA_LSB_POS-C_DATA_BITS + 1) to DATA_LSB_POS),
FIFO_Read => fifo_rd,
Data_Out => RX_Data,
FIFO_Full => RX_Buffer_Full_I,
FIFO_Empty => rx_Data_Empty,
Addr => open
);
RX_Data_Present <= not rx_Data_Empty;
RX_Overrun_Error <= RX_Buffer_Full_I and fifo_Write; -- Note that if
-- the RX FIFO is read on the same cycle as it is written while full,
-- there is no loss of data. However this case is not optimized and
-- is also reported as an overrun.
RX_Buffer_Full <= RX_Buffer_Full_I;
end architecture RTL;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/rx_statemachine.vhd | 4 | 43053 | -------------------------------------------------------------------------------
-- rx_statemachine - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : rx_statemachine.vhd
-- Version : v2.0
-- Description : This file contains the receive control state machine.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."+";
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Emac_rx_rd_data -- RX FIFO read data to controller
-- Rcv_en -- Receive enable
-- RxBusFifoRdAck -- RX FIFO read ack
-- BusFifoEmpty -- RX FIFO empty
-- Collision -- Collision detected
-- DataValid -- Data valid from PHY
-- RxError -- Receive error
-- BusFifoData -- RX FIFO data
-- CrcOk -- CRC correct in the receive data
-- BusFifoRd -- RX FIFO read
-- RxAbortRst -- Receive abort
-- RxCrcRst -- Receive CRC reset
-- RxCrcEn -- RX CRC enable
-- Rx_addr_en -- Receive address enable
-- Rx_start -- Receive start
-- Rx_done -- Receive complete
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write read enable
-- Rx_idle -- RX idle
-- Mac_addr_ram_addr_rd -- MAC Addr RAM read address
-- Mac_addr_ram_data -- MAC Addr RAM read data
-- Rx_buffer_ready -- RX buffer ready to accept new packet
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity rx_statemachine is
generic (
C_DUPLEX : integer := 1
-- 1 = full duplex, 0 = half duplex
);
port (
Clk : in std_logic;
Rst : in std_logic;
Emac_rx_rd_data_d1 : in std_logic_vector(0 to 5); -- 03-26-04
Receive_enable : out std_logic; -- 03-26-04
RxBusFifoRdAck : in std_logic;
BusFifoEmpty : in std_logic;
Collision : in std_logic;
DataValid : in std_logic;
RxError : in std_logic;
BusFifoData : in std_logic_vector(0 to 3);
CrcOk : in std_logic;
BusFifoRd : out std_logic;
RxAbortRst : out std_logic;
RxCrcRst : out std_logic;
RxCrcEn : out std_logic;
Rx_addr_en : out std_logic;
Rx_start : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_idle : out std_logic;
Mac_addr_ram_addr_rd : out std_logic_vector(0 to 3);
Mac_addr_ram_data : in std_logic_vector (0 to 3);
Rx_buffer_ready : in std_logic
);
end rx_statemachine;
architecture imp of rx_statemachine is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
signal idle : std_logic; -- state 0
signal waitForSfd1 : std_logic; -- state 1
signal sfd1CheckBusFifoEmpty : std_logic; -- state 2
signal waitForSfd2 : std_logic; -- state 3
signal startReadDestAdrNib : std_logic; -- state 4
signal rdDestAddrNib_eq_0 : std_logic;
signal rdDestAddrNib_eq_12 : std_logic;
signal startReadDataNib : std_logic; -- state 17
signal crcCheck : std_logic; -- state 18
signal rxDone : std_logic; -- state 20
signal receiveRst : std_logic; -- state 21
signal rxCollision : std_logic; -- state 22
signal idle_D : std_logic; -- state 0
signal waitForSfd1_D : std_logic; -- state 1
signal sfd1CheckBusFifoEmpty_D : std_logic; -- state 2
signal waitForSfd2_D : std_logic; -- state 3
signal startReadDestAdrNib_D : std_logic; -- state 4
signal startReadDataNib_D : std_logic; -- state 17
signal crcCheck_D : std_logic; -- state 18
signal rxDone_D : std_logic; -- state 20
signal receiveRst_D : std_logic; -- state 21
signal rxCollision_D : std_logic; -- state 22
signal goto_idle_1 : std_logic; -- state 0
signal goto_idle_2 : std_logic; -- state 0
signal goto_idle_3 : std_logic; -- state 0
signal goto_idle_4 : std_logic; -- state 0
signal goto_waitForSfd1 : std_logic; -- state 1
signal goto_sfd1CheckBusFifoEmpty_1 : std_logic; -- state 2
signal goto_sfd1CheckBusFifoEmpty_2 : std_logic; -- state 2
signal goto_waitForSfd2 : std_logic; -- state 3
signal goto_startReadDestAdrNib_1 : std_logic; -- state 4
signal goto_readDestAdrNib1 : std_logic; -- state 5
signal goto_startReadDataNib_2 : std_logic; -- state 17
signal goto_crcCheck : std_logic; -- state 18
signal goto_rxDone_3 : std_logic; -- state 20
signal goto_receiveRst_1 : std_logic; -- state 21
signal goto_receiveRst_2 : std_logic; -- state 21
signal goto_receiveRst_3 : std_logic; -- state 21
signal goto_receiveRst_5 : std_logic; -- state 21
signal goto_receiveRst_9 : std_logic; -- state 21
signal goto_receiveRst_10 : std_logic; -- state 21
signal goto_receiveRst_14 : std_logic; -- state 21
signal goto_rxCollision_1 : std_logic; -- state 22
signal goto_rxCollision_2 : std_logic; -- state 22
signal goto_rxCollision_5 : std_logic; -- state 22
signal stay_idle : std_logic; -- state 0
signal stay_sfd1CheckBusFifoEmpty : std_logic; -- state 2
signal stay_startReadDestAdrNib : std_logic; -- state 4
signal stay_startReadDataNib : std_logic; -- state 17
signal state_machine_rst : std_logic;
signal full_half_n : std_logic;
signal checkingBroadcastAdr_i : std_logic;
signal checkingBroadcastAdr_reg : std_logic;
signal busFifoData_is_5 : std_logic;
signal busFifoData_is_13 : std_logic;
signal busFifoData_not_5 : std_logic;
signal busFifoData_not_13 : std_logic;
signal bcastAddrGood : std_logic;
signal ucastAddrGood : std_logic;
signal crcokr1 : std_logic;
signal crcokin : std_logic;
signal rxCrcEn_i : std_logic;
signal mac_addr_ram_addr_rd_D : std_logic_vector(0 to 3);
signal rdDestAddrNib_D_t : std_logic_vector(0 to 3);
signal rdDestAddrNib_D_t_q : std_logic_vector(0 to 3);
signal rxDone_i : std_logic;
signal preamble_valid : std_logic;
signal preamble_error_reg : std_logic;
signal preamble_error : std_logic;
signal busFifoData_is_5_d1 : std_logic;
signal busFifoData_is_5_d2 : std_logic;
signal busFifoData_is_5_d3 : std_logic;
signal pkt_length_cnt : integer range 0 to 127;
signal crc_rst : std_logic;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDS
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------
-- CRC check
----------------------------------------------------------------------------
crcokin <= ((CrcOk -- set
or crcokr1) -- keep
and (not(rxCrcEn_i) or CrcOk)); -- clear when 0
crcokdelay: FDR
port map (
Q => crcokr1, --[out]
C => Clk, --[in]
D => crcokin, --[in]
R => crc_rst --[in]
);
-- Added this to reset CRCokr1 before starting the next packet reception.
crc_rst <= Rst or (not CrcOk and crcokr1);
-- RX Complete indicator
Rx_done <= rxDone_i; -- added Rx_done output for ping pong control
-- Generate rxdone only if received framelength is greater than minimum
-- frame length
rxDone_i <= '1' when rxDone='1' and pkt_length_cnt=0 else
'0';
-- Check start of Frame
-- If receive data=5
busFifoData_is_5 <= not(BusFifoData(0)) and BusFifoData(1) and
not(BusFifoData(2)) and BusFifoData(3);
-- If receive data/=5
busFifoData_not_5 <= not(busFifoData_is_5);
-- If receive data=13
busFifoData_is_13 <= BusFifoData(0) and BusFifoData(1) and
not(BusFifoData(2)) and BusFifoData(3);
-- If receive data/=13
busFifoData_not_13 <= not(busFifoData_is_13);
-- State Machine Reset
state_machine_rst <= Rst;
----------------------------------------------------------------------------
-- idle state
----------------------------------------------------------------------------
goto_idle_1 <= rxDone;
goto_idle_2 <= receiveRst;
goto_idle_3 <= waitForSfd1 and (not(DataValid) or busFifoData_not_5);
goto_idle_4 <= waitForSfd2 and (not(DataValid) or
(busFifoData_not_5 and busFifoData_not_13));
stay_idle <= idle and not(goto_waitForSfd1);
idle_D <= goto_idle_1 or goto_idle_2 or goto_idle_3 or goto_idle_4
or stay_idle;
state0a: FDS
port map (
Q => idle, --[out]
C => Clk, --[in]
D => idle_D, --[in]
S => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- waitForSfd1 state
----------------------------------------------------------------------------
goto_waitForSfd1 <= idle and (RxBusFifoRdAck or not(BusFifoEmpty))
and (Rx_buffer_ready);
waitForSfd1_D <= goto_waitForSfd1;
state1a: FDR
port map (
Q => waitForSfd1, --[out]
C => Clk, --[in]
D => waitForSfd1_D, --[in]
R => state_machine_rst --[in]
);
Rx_idle <= idle or waitForSfd1;
----------------------------------------------------------------------------
-- sfd1CheckBusFifoEmpty state
----------------------------------------------------------------------------
goto_sfd1CheckBusFifoEmpty_1 <= waitForSfd1 and busFifoData_is_5
and DataValid;
goto_sfd1CheckBusFifoEmpty_2 <= waitForSfd2 and busFifoData_is_5
and DataValid;
stay_sfd1CheckBusFifoEmpty <= sfd1CheckBusFifoEmpty and
not(goto_rxCollision_1) and
not(goto_receiveRst_1) and
not(goto_waitForSfd2);
sfd1CheckBusFifoEmpty_D <= goto_sfd1CheckBusFifoEmpty_1 or
goto_sfd1CheckBusFifoEmpty_2 or
stay_sfd1CheckBusFifoEmpty;
state2a: FDR
port map (
Q => sfd1CheckBusFifoEmpty, --[out]
C => Clk, --[in]
D => sfd1CheckBusFifoEmpty_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- waitForSfd2 state
----------------------------------------------------------------------------
goto_waitForSfd2 <= sfd1CheckBusFifoEmpty and not(goto_rxCollision_1) and
not(goto_receiveRst_1) and (RxBusFifoRdAck or
not(BusFifoEmpty)) and
busFifoData_is_5;
waitForSfd2_D <= goto_waitForSfd2;
state3a: FDR
port map (
Q => waitForSfd2, --[out]
C => Clk, --[in]
D => waitForSfd2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--startReadDestAdrNib state
----------------------------------------------------------------------------
goto_startReadDestAdrNib_1 <= waitForSfd2 and busFifoData_is_13
and preamble_valid
and DataValid;
stay_startReadDestAdrNib <= startReadDestAdrNib and
not(goto_rxCollision_2) and
not(goto_receiveRst_2) and
not(goto_readDestAdrNib1);
startReadDestAdrNib_D <= goto_startReadDestAdrNib_1 or
stay_startReadDestAdrNib;
state4a: FDR
port map (
Q => startReadDestAdrNib, --[out]
C => Clk, --[in]
D => startReadDestAdrNib_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--readDestAdrNib1 state
----------------------------------------------------------------------------
goto_readDestAdrNib1 <= startReadDestAdrNib and
not(goto_rxCollision_2) and
not(goto_receiveRst_2) and
RxBusFifoRdAck;
rdDestAddrNib_eq_0 <= bo2sl(rdDestAddrNib_D_t_q = "0000");
rdDestAddrNib_eq_12 <= bo2sl(rdDestAddrNib_D_t_q = "1011");
----------------------------------------------------------------------------
-- STATE_REG_PROCESS
----------------------------------------------------------------------------
-- Registeting the read destination address.
----------------------------------------------------------------------------
STATE_REG_PROCESS : process (Clk)
begin
if (Clk'event and Clk='1') then
if (state_machine_rst = '1' or
goto_startReadDestAdrNib_1 = '1') then
rdDestAddrNib_D_t_q <= "0000";
else
rdDestAddrNib_D_t_q <= rdDestAddrNib_D_t;
end if;
end if;
end process STATE_REG_PROCESS;
----------------------------------------------------------------------------
-- FSM_CMB_PROCESS
----------------------------------------------------------------------------
-- This process generate read destination address for the MAC address RAM
-- for the received frame.
----------------------------------------------------------------------------
FSM_CMB_PROCESS : process (startReadDestAdrNib,goto_rxCollision_2,
goto_receiveRst_2,RxBusFifoRdAck,goto_receiveRst_3,bcastAddrGood,
ucastAddrGood,goto_receiveRst_5,
rdDestAddrNib_D_t_q)
begin
----
rdDestAddrNib_D_t <= rdDestAddrNib_D_t_q;
case (rdDestAddrNib_D_t_q) is
when "0000" =>
if (startReadDestAdrNib and not(goto_rxCollision_2) and
not(goto_receiveRst_2) and RxBusFifoRdAck) = '1' then
rdDestAddrNib_D_t <= "0001";
else
rdDestAddrNib_D_t <= "0000";
end if;
when "0001" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0010";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0001";
end if;
when "0010" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0011";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0010";
end if;
when "0011" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0100";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0011";
end if;
when "0100" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0101";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0100";
end if;
when "0101" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0110";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0101";
end if;
when "0110" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0111";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0110";
end if;
when "0111" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1000";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0111";
end if;
when "1000" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1001";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1000";
end if;
when "1001" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1010";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1001";
end if;
when "1010" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1011";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1010";
end if;
when "1011" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1100";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1011";
end if;
when "1100" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0000";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1100";
end if;
when others => null;
end case;
end process FSM_CMB_PROCESS;
----------------------------------------------------------------------------
--startReadDataNib state
----------------------------------------------------------------------------
goto_startReadDataNib_2 <= rdDestAddrNib_eq_12 and RxBusFifoRdAck and
(bcastAddrGood or ucastAddrGood) and not(goto_receiveRst_5) and
not(goto_receiveRst_3);
stay_startReadDataNib <= startReadDataNib and not(goto_rxCollision_5)
and not(goto_receiveRst_9) and DataValid;
startReadDataNib_D <= goto_startReadDataNib_2
or stay_startReadDataNib;
state17a: FDR
port map (
Q => startReadDataNib, --[out]
C => Clk, --[in]
D => startReadDataNib_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--crcCheck state
----------------------------------------------------------------------------
goto_crcCheck <= startReadDataNib and not(DataValid) ;
goto_receiveRst_1 <= sfd1CheckBusFifoEmpty and not(goto_rxCollision_1)
and RxError;
goto_receiveRst_2 <= startReadDestAdrNib and not(goto_rxCollision_2)
and RxError;
goto_receiveRst_9 <= startReadDataNib and not(goto_rxCollision_5)
and RxError;
crcCheck_D <= goto_crcCheck or goto_receiveRst_1 or
goto_receiveRst_2 or
goto_receiveRst_9;
state18a: FDR
port map (
Q => crcCheck, --[out]
C => Clk, --[in]
D => crcCheck_D, --[in]
R => state_machine_rst --[in]
);
-------------------------------------------------------------------------------
--rxDone state
-------------------------------------------------------------------------------
--goto_rxDone_3 <= writeFinalData ;
goto_rxDone_3 <= crcCheck and crcokr1;
rxDone_D <= goto_rxDone_3 ;
state20a: FDR
port map (
Q => rxDone, --[out]
C => Clk, --[in]
D => rxDone_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--rxCollision state
----------------------------------------------------------------------------
full_half_n <= '1'when C_DUPLEX = 1 else
'0';
goto_rxCollision_1 <= sfd1CheckBusFifoEmpty and Collision
and not(full_half_n);
goto_rxCollision_2 <= startReadDestAdrNib and Collision
and not(full_half_n);
goto_rxCollision_5 <= startReadDataNib and Collision
and not(full_half_n);
rxCollision_D <= goto_rxCollision_1 or goto_rxCollision_2 or
goto_rxCollision_5;
state21a: FDR
port map (
Q => rxCollision, --[out]
C => Clk, --[in]
D => rxCollision_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--receiveRst state
----------------------------------------------------------------------------
goto_receiveRst_3 <= not rdDestAddrNib_eq_0 and not(DataValid);
goto_receiveRst_5 <= not rdDestAddrNib_eq_0 and
not(BusFifoEmpty) and
not(bcastAddrGood or ucastAddrGood);
goto_receiveRst_10<= crcCheck and not(crcokr1);
goto_receiveRst_14<= rxCollision;
receiveRst_D <= goto_receiveRst_3 or
goto_receiveRst_5 or
goto_receiveRst_10 or
goto_receiveRst_14 or
preamble_error_reg;
state22a: FDR
port map (
Q => receiveRst, --[out]
C => Clk, --[in]
D => receiveRst_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- end of states
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- BROADCAST_ADDR_REG
----------------------------------------------------------------------------
-- This process generate control signals for the state machine.
----------------------------------------------------------------------------
BROADCAST_ADDR_REG : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
checkingBroadcastAdr_reg <= '0';
else
checkingBroadcastAdr_reg <= checkingBroadcastAdr_i;
end if;
end if;
end process BROADCAST_ADDR_REG;
----------------------------------------------------------------------------
-- RX_FSMD_PROCESS
----------------------------------------------------------------------------
-- This process generate control signals for the state machine.
----------------------------------------------------------------------------
RX_FSMD_PROCESS : process( DataValid,RxBusFifoRdAck,idle,
startReadDestAdrNib, startReadDataNib,
sfd1CheckBusFifoEmpty, rxDone, receiveRst,
waitForSfd2, Emac_rx_rd_data_d1,
checkingBroadcastAdr_reg, rdDestAddrNib_eq_0,
rdDestAddrNib_D_t_q)
begin
-- Reset RX CRC in idle state
if (idle = '1') then
RxCrcRst <= '1';
else
RxCrcRst <= '0';
end if;
-- RX CRC enable
if ((( startReadDestAdrNib or (not rdDestAddrNib_eq_0) or
(startReadDataNib and DataValid))
and RxBusFifoRdAck) = '1') then
RxCrcEn <= '1';
rxCrcEn_i <= '1';
else
RxCrcEn <= '0';
rxCrcEn_i <= '0';
end if;
-- RX buffer FIFO read enable
if ((idle = '1') or
(sfd1CheckBusFifoEmpty = '1') or
(not rdDestAddrNib_eq_0 = '1') or
(rxDone = '1') or -- 03-26-04
(startReadDestAdrNib = '1') or
(startReadDataNib = '1')) and (RxBusFifoRdAck = '0')then
BusFifoRd <= '1';
else
BusFifoRd <= '0';
end if;
-- RX abort reset
if (receiveRst = '1') then
RxAbortRst <= '1';
else
RxAbortRst <= '0';
end if;
-- RX buffer address enable
if RxBusFifoRdAck = '1' and
(
(startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1')
) then
Rx_addr_en <= '1'; --enable address increment
else
Rx_addr_en <= '0';
end if;
-- Generate RX start after SFD is detected
if (waitForSfd2 = '1')then
Rx_start <= '1'; -- reset address to 0 for start of receive
else
Rx_start <= '0';
end if;
-- RX buffer chip enable
if (idle = '1') or
((
(startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1')
) and (RxBusFifoRdAck = '1')
) then
Rx_DPM_ce <= '1';
else
Rx_DPM_ce <= '0';
end if;
-- RX buffer read/write enable
if (startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1') then
Rx_DPM_wr_rd_n <= '1';
else
Rx_DPM_wr_rd_n <= '0';
end if;
-- RX buffer chip enable
if (idle = '1') then
checkingBroadcastAdr_i <= '0'; -- reset
-- 06-09-04 Use delayed data for compare
elsif (rdDestAddrNib_D_t_q = x"1" and
Emac_rx_rd_data_d1(0 to 3) = x"f") then
checkingBroadcastAdr_i <= '1'; -- set
else
checkingBroadcastAdr_i <= checkingBroadcastAdr_reg; -- stay the same
end if;
end process RX_FSMD_PROCESS;
-- write data to Receive DPRAM
Rx_DPM_wr_data <= BusFifoData;
----------------------------------------------------------------------------
-- MARAR_PROC
----------------------------------------------------------------------------
-- This process generate MAC RAM address to get mac addres to compare with
-- incoming frame destination address
----------------------------------------------------------------------------
MARAR_PROC : process (rdDestAddrNib_D_t, idle_D, startReadDestAdrNib_D)
begin
case rdDestAddrNib_D_t is
when "0001" => mac_addr_ram_addr_rd_D <= x"0";
when "0010" => mac_addr_ram_addr_rd_D <= x"1";
when "0011" => mac_addr_ram_addr_rd_D <= x"2";
when "0100" => mac_addr_ram_addr_rd_D <= x"3";
when "0101" => mac_addr_ram_addr_rd_D <= x"4";
when "0110" => mac_addr_ram_addr_rd_D <= x"5";
when "0111" => mac_addr_ram_addr_rd_D <= x"6";
when "1000" => mac_addr_ram_addr_rd_D <= x"7";
when "1001" => mac_addr_ram_addr_rd_D <= x"8";
when "1010" => mac_addr_ram_addr_rd_D <= x"9";
when "1011" => mac_addr_ram_addr_rd_D <= x"a";
when "1100" => mac_addr_ram_addr_rd_D <= x"b";
when others => mac_addr_ram_addr_rd_D <= x"0";
end case;
-- Reset the address in idle or start of new frame
if (idle_D or startReadDestAdrNib_D) = '1' then
mac_addr_ram_addr_rd_D <= x"0";
end if;
end process MARAR_PROC;
----------------------------------------------------------------------------
-- OUTPUT_REG
----------------------------------------------------------------------------
-- Registerit the mac_addr_ram_addr_rd
----------------------------------------------------------------------------
OUTPUT_REG:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Mac_addr_ram_addr_rd <= (others => '0');
else
Mac_addr_ram_addr_rd <= mac_addr_ram_addr_rd_D;
end if;
end if;
end process OUTPUT_REG;
----------------------------------------------------------------------------
-- Check if the incoming packet is broadcast packet
----------------------------------------------------------------------------
bcastAddrGood <= '1' when checkingBroadcastAdr_i = '1' and
Emac_rx_rd_data_d1(0 to 3) = x"F" else -- 03-26-04
'0';
----------------------------------------------------------------------------
-- Check if the incoming packet is unicast and address matches to core
-- MAC address
----------------------------------------------------------------------------
ucastAddrGood <= '1' when checkingBroadcastAdr_i = '0' and
(Emac_rx_rd_data_d1(0 to 3) = Mac_addr_ram_data)
else -- 03-26-04
'0';
-- Genarate Receive enable
Receive_enable <= not(crcCheck or rxDone or receiveRst);
----------------------------------------------------------------------------
-- PROCESS : PKT_LENGTH_COUNTER
----------------------------------------------------------------------------
-- This counter is used to check if the receive packet length is greater
-- minimum packet length (64 byte - 128 nibble)
----------------------------------------------------------------------------
PKT_LENGTH_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' or preamble_error_reg = '1' ) then
pkt_length_cnt <= 0;
elsif goto_readDestAdrNib1 = '1' then -- load the counter for
pkt_length_cnt <= 127; -- minimum packet length
elsif (rxCrcEn_i='1') then -- Enable Down Counter
if (pkt_length_cnt = 0) then
pkt_length_cnt <= 0;
else
pkt_length_cnt <= pkt_length_cnt - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : SFD_CHECK_REG
----------------------------------------------------------------------------
-- This process registers the preamble nibble to checl if atleast last 2
-- preamble nibbles are valid before the SFD nibble.
----------------------------------------------------------------------------
SFD_CHECK_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
busFifoData_is_5_d1 <= '0';
busFifoData_is_5_d2 <= '0';
busFifoData_is_5_d3 <= '0';
elsif RxBusFifoRdAck = '1' then
busFifoData_is_5_d1 <= busFifoData_is_5;
busFifoData_is_5_d2 <= busFifoData_is_5_d1;
busFifoData_is_5_d3 <= busFifoData_is_5_d2;
end if;
end if;
end process;
preamble: FDR
port map (
Q => preamble_error_reg, --[out]
C => Clk, --[in]
D => preamble_error, --[in]
R => state_machine_rst --[in]
);
-- Premable valid
preamble_valid <= (busFifoData_is_5_d1) and
busFifoData_is_13;
-- Premable Error
preamble_error <= (not busFifoData_is_5 and
busFifoData_is_5_d1 and
not busFifoData_is_13) and waitForSfd2 ;
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/blk_mem_gen_v8_2/7b054ed9/hdl/blk_mem_gen_v8_2.vhd | 41 | 20439 | `protect begin_protected
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`protect end_protected
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_axi_timer_0_0/synth/design_1_axi_timer_0_0.vhd | 2 | 9270 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_timer_v2_0;
USE axi_timer_v2_0.axi_timer;
ENTITY design_1_axi_timer_0_0 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END design_1_axi_timer_0_0;
ARCHITECTURE design_1_axi_timer_0_0_arch OF design_1_axi_timer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "axi_timer,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_timer_0_0_arch : ARCHITECTURE IS "design_1_axi_timer_0_0,axi_timer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "design_1_axi_timer_0_0,axi_timer,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_timer,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_COUNT_WIDTH=32,C_ONE_TIMER_ONLY=0,C_TRIG0_ASSERT=1,C_TRIG1_ASSERT=1,C_GEN0_ASSERT=1,C_GEN1_ASSERT=1,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "artix7",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END design_1_axi_timer_0_0_arch;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd | 1 | 14171 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.2 (win64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
--Date : Thu Nov 19 17:38:29 2015
--Host : ALI-WORKSTATION running 64-bit major release (build 9200)
--Command : generate_target design_1_wrapper.bd
--Design : design_1_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
port (
cellular_ram_addr : out STD_LOGIC_VECTOR ( 22 downto 0 );
cellular_ram_adv_ldn : out STD_LOGIC;
cellular_ram_ben : out STD_LOGIC_VECTOR ( 1 downto 0 );
cellular_ram_ce_n : out STD_LOGIC;
cellular_ram_cre : out STD_LOGIC;
cellular_ram_dq_io : inout STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_oen : out STD_LOGIC;
cellular_ram_wait : in STD_LOGIC;
cellular_ram_wen : out STD_LOGIC;
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_io : inout STD_LOGIC;
eth_ref_clk : out STD_LOGIC;
eth_rmii_crs_dv : in STD_LOGIC;
eth_rmii_rx_er : in STD_LOGIC;
eth_rmii_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
eth_rmii_tx_en : out STD_LOGIC;
eth_rmii_txd : out STD_LOGIC_VECTOR ( 1 downto 0 );
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
end design_1_wrapper;
architecture STRUCTURE of design_1_wrapper is
component design_1 is
port (
cellular_ram_addr : out STD_LOGIC_VECTOR ( 22 downto 0 );
cellular_ram_adv_ldn : out STD_LOGIC;
cellular_ram_ben : out STD_LOGIC_VECTOR ( 1 downto 0 );
cellular_ram_ce_n : out STD_LOGIC;
cellular_ram_cre : out STD_LOGIC;
cellular_ram_dq_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_dq_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_dq_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_oen : out STD_LOGIC;
cellular_ram_wait : in STD_LOGIC;
cellular_ram_wen : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
eth_rmii_crs_dv : in STD_LOGIC;
eth_rmii_rx_er : in STD_LOGIC;
eth_rmii_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
eth_rmii_tx_en : out STD_LOGIC;
eth_rmii_txd : out STD_LOGIC_VECTOR ( 1 downto 0 );
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_i : in STD_LOGIC;
eth_mdio_mdc_mdio_o : out STD_LOGIC;
eth_mdio_mdc_mdio_t : out STD_LOGIC;
reset : in STD_LOGIC;
eth_ref_clk : out STD_LOGIC;
sys_clock : in STD_LOGIC
);
end component design_1;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal cellular_ram_dq_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_i_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_i_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_i_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_i_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_i_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_i_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_i_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_i_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal cellular_ram_dq_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_io_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_io_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_io_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_io_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_io_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_io_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_io_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_io_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal cellular_ram_dq_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_o_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_o_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_o_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_o_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_o_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_o_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_o_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_o_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal cellular_ram_dq_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_t_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_t_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_t_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_t_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_t_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_t_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_t_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_t_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_t_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_t_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal eth_mdio_mdc_mdio_i : STD_LOGIC;
signal eth_mdio_mdc_mdio_o : STD_LOGIC;
signal eth_mdio_mdc_mdio_t : STD_LOGIC;
begin
cellular_ram_dq_iobuf_0: component IOBUF
port map (
I => cellular_ram_dq_o_0(0),
IO => cellular_ram_dq_io(0),
O => cellular_ram_dq_i_0(0),
T => cellular_ram_dq_t_0(0)
);
cellular_ram_dq_iobuf_1: component IOBUF
port map (
I => cellular_ram_dq_o_1(1),
IO => cellular_ram_dq_io(1),
O => cellular_ram_dq_i_1(1),
T => cellular_ram_dq_t_1(1)
);
cellular_ram_dq_iobuf_10: component IOBUF
port map (
I => cellular_ram_dq_o_10(10),
IO => cellular_ram_dq_io(10),
O => cellular_ram_dq_i_10(10),
T => cellular_ram_dq_t_10(10)
);
cellular_ram_dq_iobuf_11: component IOBUF
port map (
I => cellular_ram_dq_o_11(11),
IO => cellular_ram_dq_io(11),
O => cellular_ram_dq_i_11(11),
T => cellular_ram_dq_t_11(11)
);
cellular_ram_dq_iobuf_12: component IOBUF
port map (
I => cellular_ram_dq_o_12(12),
IO => cellular_ram_dq_io(12),
O => cellular_ram_dq_i_12(12),
T => cellular_ram_dq_t_12(12)
);
cellular_ram_dq_iobuf_13: component IOBUF
port map (
I => cellular_ram_dq_o_13(13),
IO => cellular_ram_dq_io(13),
O => cellular_ram_dq_i_13(13),
T => cellular_ram_dq_t_13(13)
);
cellular_ram_dq_iobuf_14: component IOBUF
port map (
I => cellular_ram_dq_o_14(14),
IO => cellular_ram_dq_io(14),
O => cellular_ram_dq_i_14(14),
T => cellular_ram_dq_t_14(14)
);
cellular_ram_dq_iobuf_15: component IOBUF
port map (
I => cellular_ram_dq_o_15(15),
IO => cellular_ram_dq_io(15),
O => cellular_ram_dq_i_15(15),
T => cellular_ram_dq_t_15(15)
);
cellular_ram_dq_iobuf_2: component IOBUF
port map (
I => cellular_ram_dq_o_2(2),
IO => cellular_ram_dq_io(2),
O => cellular_ram_dq_i_2(2),
T => cellular_ram_dq_t_2(2)
);
cellular_ram_dq_iobuf_3: component IOBUF
port map (
I => cellular_ram_dq_o_3(3),
IO => cellular_ram_dq_io(3),
O => cellular_ram_dq_i_3(3),
T => cellular_ram_dq_t_3(3)
);
cellular_ram_dq_iobuf_4: component IOBUF
port map (
I => cellular_ram_dq_o_4(4),
IO => cellular_ram_dq_io(4),
O => cellular_ram_dq_i_4(4),
T => cellular_ram_dq_t_4(4)
);
cellular_ram_dq_iobuf_5: component IOBUF
port map (
I => cellular_ram_dq_o_5(5),
IO => cellular_ram_dq_io(5),
O => cellular_ram_dq_i_5(5),
T => cellular_ram_dq_t_5(5)
);
cellular_ram_dq_iobuf_6: component IOBUF
port map (
I => cellular_ram_dq_o_6(6),
IO => cellular_ram_dq_io(6),
O => cellular_ram_dq_i_6(6),
T => cellular_ram_dq_t_6(6)
);
cellular_ram_dq_iobuf_7: component IOBUF
port map (
I => cellular_ram_dq_o_7(7),
IO => cellular_ram_dq_io(7),
O => cellular_ram_dq_i_7(7),
T => cellular_ram_dq_t_7(7)
);
cellular_ram_dq_iobuf_8: component IOBUF
port map (
I => cellular_ram_dq_o_8(8),
IO => cellular_ram_dq_io(8),
O => cellular_ram_dq_i_8(8),
T => cellular_ram_dq_t_8(8)
);
cellular_ram_dq_iobuf_9: component IOBUF
port map (
I => cellular_ram_dq_o_9(9),
IO => cellular_ram_dq_io(9),
O => cellular_ram_dq_i_9(9),
T => cellular_ram_dq_t_9(9)
);
design_1_i: component design_1
port map (
cellular_ram_addr(22 downto 0) => cellular_ram_addr(22 downto 0),
cellular_ram_adv_ldn => cellular_ram_adv_ldn,
cellular_ram_ben(1 downto 0) => cellular_ram_ben(1 downto 0),
cellular_ram_ce_n => cellular_ram_ce_n,
cellular_ram_cre => cellular_ram_cre,
cellular_ram_dq_i(15) => cellular_ram_dq_i_15(15),
cellular_ram_dq_i(14) => cellular_ram_dq_i_14(14),
cellular_ram_dq_i(13) => cellular_ram_dq_i_13(13),
cellular_ram_dq_i(12) => cellular_ram_dq_i_12(12),
cellular_ram_dq_i(11) => cellular_ram_dq_i_11(11),
cellular_ram_dq_i(10) => cellular_ram_dq_i_10(10),
cellular_ram_dq_i(9) => cellular_ram_dq_i_9(9),
cellular_ram_dq_i(8) => cellular_ram_dq_i_8(8),
cellular_ram_dq_i(7) => cellular_ram_dq_i_7(7),
cellular_ram_dq_i(6) => cellular_ram_dq_i_6(6),
cellular_ram_dq_i(5) => cellular_ram_dq_i_5(5),
cellular_ram_dq_i(4) => cellular_ram_dq_i_4(4),
cellular_ram_dq_i(3) => cellular_ram_dq_i_3(3),
cellular_ram_dq_i(2) => cellular_ram_dq_i_2(2),
cellular_ram_dq_i(1) => cellular_ram_dq_i_1(1),
cellular_ram_dq_i(0) => cellular_ram_dq_i_0(0),
cellular_ram_dq_o(15) => cellular_ram_dq_o_15(15),
cellular_ram_dq_o(14) => cellular_ram_dq_o_14(14),
cellular_ram_dq_o(13) => cellular_ram_dq_o_13(13),
cellular_ram_dq_o(12) => cellular_ram_dq_o_12(12),
cellular_ram_dq_o(11) => cellular_ram_dq_o_11(11),
cellular_ram_dq_o(10) => cellular_ram_dq_o_10(10),
cellular_ram_dq_o(9) => cellular_ram_dq_o_9(9),
cellular_ram_dq_o(8) => cellular_ram_dq_o_8(8),
cellular_ram_dq_o(7) => cellular_ram_dq_o_7(7),
cellular_ram_dq_o(6) => cellular_ram_dq_o_6(6),
cellular_ram_dq_o(5) => cellular_ram_dq_o_5(5),
cellular_ram_dq_o(4) => cellular_ram_dq_o_4(4),
cellular_ram_dq_o(3) => cellular_ram_dq_o_3(3),
cellular_ram_dq_o(2) => cellular_ram_dq_o_2(2),
cellular_ram_dq_o(1) => cellular_ram_dq_o_1(1),
cellular_ram_dq_o(0) => cellular_ram_dq_o_0(0),
cellular_ram_dq_t(15) => cellular_ram_dq_t_15(15),
cellular_ram_dq_t(14) => cellular_ram_dq_t_14(14),
cellular_ram_dq_t(13) => cellular_ram_dq_t_13(13),
cellular_ram_dq_t(12) => cellular_ram_dq_t_12(12),
cellular_ram_dq_t(11) => cellular_ram_dq_t_11(11),
cellular_ram_dq_t(10) => cellular_ram_dq_t_10(10),
cellular_ram_dq_t(9) => cellular_ram_dq_t_9(9),
cellular_ram_dq_t(8) => cellular_ram_dq_t_8(8),
cellular_ram_dq_t(7) => cellular_ram_dq_t_7(7),
cellular_ram_dq_t(6) => cellular_ram_dq_t_6(6),
cellular_ram_dq_t(5) => cellular_ram_dq_t_5(5),
cellular_ram_dq_t(4) => cellular_ram_dq_t_4(4),
cellular_ram_dq_t(3) => cellular_ram_dq_t_3(3),
cellular_ram_dq_t(2) => cellular_ram_dq_t_2(2),
cellular_ram_dq_t(1) => cellular_ram_dq_t_1(1),
cellular_ram_dq_t(0) => cellular_ram_dq_t_0(0),
cellular_ram_oen => cellular_ram_oen,
cellular_ram_wait => cellular_ram_wait,
cellular_ram_wen => cellular_ram_wen,
eth_mdio_mdc_mdc => eth_mdio_mdc_mdc,
eth_mdio_mdc_mdio_i => eth_mdio_mdc_mdio_i,
eth_mdio_mdc_mdio_o => eth_mdio_mdc_mdio_o,
eth_mdio_mdc_mdio_t => eth_mdio_mdc_mdio_t,
eth_ref_clk => eth_ref_clk,
eth_rmii_crs_dv => eth_rmii_crs_dv,
eth_rmii_rx_er => eth_rmii_rx_er,
eth_rmii_rxd(1 downto 0) => eth_rmii_rxd(1 downto 0),
eth_rmii_tx_en => eth_rmii_tx_en,
eth_rmii_txd(1 downto 0) => eth_rmii_txd(1 downto 0),
reset => reset,
sys_clock => sys_clock,
usb_uart_rxd => usb_uart_rxd,
usb_uart_txd => usb_uart_txd
);
eth_mdio_mdc_mdio_iobuf: component IOBUF
port map (
I => eth_mdio_mdc_mdio_o,
IO => eth_mdio_mdc_mdio_io,
O => eth_mdio_mdc_mdio_i,
T => eth_mdio_mdc_mdio_t
);
end STRUCTURE;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/axi_emc_pkg.vhd | 4 | 2913 | library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package emc_pkg is
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
end emc_pkg;
package body emc_pkg is
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
end package body emc_pkg;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mdm_v3_2/fbb28dda/hdl/vhdl/mdm.vhd | 4 | 178472 | -------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2006-10-27 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2012-12-14 Removed legacy interfaces
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
-- stefana 2014-04-30 Added external trace support
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library mdm_v3_2;
use mdm_v3_2.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
entity MDM is
generic (
C_FAMILY : string := "virtex7";
C_JTAG_CHAIN : integer := 2;
C_USE_BSCAN : integer := 0;
C_USE_CONFIG_RESET : integer := 0;
C_INTERCONNECT : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_FFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"0000_0000";
C_MB_DBG_PORTS : integer := 1;
C_DBG_REG_ACCESS : integer := 0;
C_DBG_MEM_ACCESS : integer := 0;
C_USE_UART : integer := 1;
C_USE_CROSS_TRIGGER : integer := 0;
C_TRACE_OUTPUT : integer := 0;
C_TRACE_DATA_WIDTH : integer range 2 to 32 := 32;
C_TRACE_CLK_FREQ_HZ : integer := 200000000;
C_TRACE_CLK_OUT_PHASE : integer range 0 to 360 := 90;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_THREAD_ID_WIDTH : integer := 1;
C_DATA_SIZE : integer range 32 to 32 := 32;
C_M_AXIS_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXIS_ID_WIDTH : integer range 1 to 7 := 7
);
port (
-- Global signals
Config_Reset : in std_logic := '0';
Scan_Reset_Sel : in std_logic := '0';
Scan_Reset : in std_logic := '0';
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- External cross trigger signals
Trig_In_0 : in std_logic;
Trig_Ack_In_0 : out std_logic;
Trig_Out_0 : out std_logic;
Trig_Ack_Out_0 : in std_logic;
Trig_In_1 : in std_logic;
Trig_Ack_In_1 : out std_logic;
Trig_Out_1 : out std_logic;
Trig_Ack_Out_1 : in std_logic;
Trig_In_2 : in std_logic;
Trig_Ack_In_2 : out std_logic;
Trig_Out_2 : out std_logic;
Trig_Ack_Out_2 : in std_logic;
Trig_In_3 : in std_logic;
Trig_Ack_In_3 : out std_logic;
Trig_Out_3 : out std_logic;
Trig_Ack_Out_3 : in std_logic;
-- AXI slave signals
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Bus master signals
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
LMB_Data_Addr_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_0 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_0 : out std_logic;
LMB_Read_Strobe_0 : out std_logic;
LMB_Write_Strobe_0 : out std_logic;
LMB_Ready_0 : in std_logic;
LMB_Wait_0 : in std_logic;
LMB_CE_0 : in std_logic;
LMB_UE_0 : in std_logic;
LMB_Byte_Enable_0 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_1 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_1 : out std_logic;
LMB_Read_Strobe_1 : out std_logic;
LMB_Write_Strobe_1 : out std_logic;
LMB_Ready_1 : in std_logic;
LMB_Wait_1 : in std_logic;
LMB_CE_1 : in std_logic;
LMB_UE_1 : in std_logic;
LMB_Byte_Enable_1 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_2 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_2 : out std_logic;
LMB_Read_Strobe_2 : out std_logic;
LMB_Write_Strobe_2 : out std_logic;
LMB_Ready_2 : in std_logic;
LMB_Wait_2 : in std_logic;
LMB_CE_2 : in std_logic;
LMB_UE_2 : in std_logic;
LMB_Byte_Enable_2 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_3 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_3 : out std_logic;
LMB_Read_Strobe_3 : out std_logic;
LMB_Write_Strobe_3 : out std_logic;
LMB_Ready_3 : in std_logic;
LMB_Wait_3 : in std_logic;
LMB_CE_3 : in std_logic;
LMB_UE_3 : in std_logic;
LMB_Byte_Enable_3 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_4 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_4 : out std_logic;
LMB_Read_Strobe_4 : out std_logic;
LMB_Write_Strobe_4 : out std_logic;
LMB_Ready_4 : in std_logic;
LMB_Wait_4 : in std_logic;
LMB_CE_4 : in std_logic;
LMB_UE_4 : in std_logic;
LMB_Byte_Enable_4 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_5 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_5 : out std_logic;
LMB_Read_Strobe_5 : out std_logic;
LMB_Write_Strobe_5 : out std_logic;
LMB_Ready_5 : in std_logic;
LMB_Wait_5 : in std_logic;
LMB_CE_5 : in std_logic;
LMB_UE_5 : in std_logic;
LMB_Byte_Enable_5 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_6 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_6 : out std_logic;
LMB_Read_Strobe_6 : out std_logic;
LMB_Write_Strobe_6 : out std_logic;
LMB_Ready_6 : in std_logic;
LMB_Wait_6 : in std_logic;
LMB_CE_6 : in std_logic;
LMB_UE_6 : in std_logic;
LMB_Byte_Enable_6 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_7 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_7 : out std_logic;
LMB_Read_Strobe_7 : out std_logic;
LMB_Write_Strobe_7 : out std_logic;
LMB_Ready_7 : in std_logic;
LMB_Wait_7 : in std_logic;
LMB_CE_7 : in std_logic;
LMB_UE_7 : in std_logic;
LMB_Byte_Enable_7 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_8 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_8 : out std_logic;
LMB_Read_Strobe_8 : out std_logic;
LMB_Write_Strobe_8 : out std_logic;
LMB_Ready_8 : in std_logic;
LMB_Wait_8 : in std_logic;
LMB_CE_8 : in std_logic;
LMB_UE_8 : in std_logic;
LMB_Byte_Enable_8 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_9 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_9 : out std_logic;
LMB_Read_Strobe_9 : out std_logic;
LMB_Write_Strobe_9 : out std_logic;
LMB_Ready_9 : in std_logic;
LMB_Wait_9 : in std_logic;
LMB_CE_9 : in std_logic;
LMB_UE_9 : in std_logic;
LMB_Byte_Enable_9 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_10 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_10 : out std_logic;
LMB_Read_Strobe_10 : out std_logic;
LMB_Write_Strobe_10 : out std_logic;
LMB_Ready_10 : in std_logic;
LMB_Wait_10 : in std_logic;
LMB_CE_10 : in std_logic;
LMB_UE_10 : in std_logic;
LMB_Byte_Enable_10 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_11 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_11 : out std_logic;
LMB_Read_Strobe_11 : out std_logic;
LMB_Write_Strobe_11 : out std_logic;
LMB_Ready_11 : in std_logic;
LMB_Wait_11 : in std_logic;
LMB_CE_11 : in std_logic;
LMB_UE_11 : in std_logic;
LMB_Byte_Enable_11 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_12 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_12 : out std_logic;
LMB_Read_Strobe_12 : out std_logic;
LMB_Write_Strobe_12 : out std_logic;
LMB_Ready_12 : in std_logic;
LMB_Wait_12 : in std_logic;
LMB_CE_12 : in std_logic;
LMB_UE_12 : in std_logic;
LMB_Byte_Enable_12 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_13 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_13 : out std_logic;
LMB_Read_Strobe_13 : out std_logic;
LMB_Write_Strobe_13 : out std_logic;
LMB_Ready_13 : in std_logic;
LMB_Wait_13 : in std_logic;
LMB_CE_13 : in std_logic;
LMB_UE_13 : in std_logic;
LMB_Byte_Enable_13 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_14 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_14 : out std_logic;
LMB_Read_Strobe_14 : out std_logic;
LMB_Write_Strobe_14 : out std_logic;
LMB_Ready_14 : in std_logic;
LMB_Wait_14 : in std_logic;
LMB_CE_14 : in std_logic;
LMB_UE_14 : in std_logic;
LMB_Byte_Enable_14 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_15 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_15 : out std_logic;
LMB_Read_Strobe_15 : out std_logic;
LMB_Write_Strobe_15 : out std_logic;
LMB_Ready_15 : in std_logic;
LMB_Wait_15 : in std_logic;
LMB_CE_15 : in std_logic;
LMB_UE_15 : in std_logic;
LMB_Byte_Enable_15 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_16 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_16 : out std_logic;
LMB_Read_Strobe_16 : out std_logic;
LMB_Write_Strobe_16 : out std_logic;
LMB_Ready_16 : in std_logic;
LMB_Wait_16 : in std_logic;
LMB_CE_16 : in std_logic;
LMB_UE_16 : in std_logic;
LMB_Byte_Enable_16 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_17 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_17 : out std_logic;
LMB_Read_Strobe_17 : out std_logic;
LMB_Write_Strobe_17 : out std_logic;
LMB_Ready_17 : in std_logic;
LMB_Wait_17 : in std_logic;
LMB_CE_17 : in std_logic;
LMB_UE_17 : in std_logic;
LMB_Byte_Enable_17 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_18 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_18 : out std_logic;
LMB_Read_Strobe_18 : out std_logic;
LMB_Write_Strobe_18 : out std_logic;
LMB_Ready_18 : in std_logic;
LMB_Wait_18 : in std_logic;
LMB_CE_18 : in std_logic;
LMB_UE_18 : in std_logic;
LMB_Byte_Enable_18 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_19 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_19 : out std_logic;
LMB_Read_Strobe_19 : out std_logic;
LMB_Write_Strobe_19 : out std_logic;
LMB_Ready_19 : in std_logic;
LMB_Wait_19 : in std_logic;
LMB_CE_19 : in std_logic;
LMB_UE_19 : in std_logic;
LMB_Byte_Enable_19 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_20 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_20 : out std_logic;
LMB_Read_Strobe_20 : out std_logic;
LMB_Write_Strobe_20 : out std_logic;
LMB_Ready_20 : in std_logic;
LMB_Wait_20 : in std_logic;
LMB_CE_20 : in std_logic;
LMB_UE_20 : in std_logic;
LMB_Byte_Enable_20 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_21 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_21 : out std_logic;
LMB_Read_Strobe_21 : out std_logic;
LMB_Write_Strobe_21 : out std_logic;
LMB_Ready_21 : in std_logic;
LMB_Wait_21 : in std_logic;
LMB_CE_21 : in std_logic;
LMB_UE_21 : in std_logic;
LMB_Byte_Enable_21 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_22 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_22 : out std_logic;
LMB_Read_Strobe_22 : out std_logic;
LMB_Write_Strobe_22 : out std_logic;
LMB_Ready_22 : in std_logic;
LMB_Wait_22 : in std_logic;
LMB_CE_22 : in std_logic;
LMB_UE_22 : in std_logic;
LMB_Byte_Enable_22 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_23 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_23 : out std_logic;
LMB_Read_Strobe_23 : out std_logic;
LMB_Write_Strobe_23 : out std_logic;
LMB_Ready_23 : in std_logic;
LMB_Wait_23 : in std_logic;
LMB_CE_23 : in std_logic;
LMB_UE_23 : in std_logic;
LMB_Byte_Enable_23 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_24 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_24 : out std_logic;
LMB_Read_Strobe_24 : out std_logic;
LMB_Write_Strobe_24 : out std_logic;
LMB_Ready_24 : in std_logic;
LMB_Wait_24 : in std_logic;
LMB_CE_24 : in std_logic;
LMB_UE_24 : in std_logic;
LMB_Byte_Enable_24 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_25 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_25 : out std_logic;
LMB_Read_Strobe_25 : out std_logic;
LMB_Write_Strobe_25 : out std_logic;
LMB_Ready_25 : in std_logic;
LMB_Wait_25 : in std_logic;
LMB_CE_25 : in std_logic;
LMB_UE_25 : in std_logic;
LMB_Byte_Enable_25 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_26 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_26 : out std_logic;
LMB_Read_Strobe_26 : out std_logic;
LMB_Write_Strobe_26 : out std_logic;
LMB_Ready_26 : in std_logic;
LMB_Wait_26 : in std_logic;
LMB_CE_26 : in std_logic;
LMB_UE_26 : in std_logic;
LMB_Byte_Enable_26 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_27 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_27 : out std_logic;
LMB_Read_Strobe_27 : out std_logic;
LMB_Write_Strobe_27 : out std_logic;
LMB_Ready_27 : in std_logic;
LMB_Wait_27 : in std_logic;
LMB_CE_27 : in std_logic;
LMB_UE_27 : in std_logic;
LMB_Byte_Enable_27 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_28 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_28 : out std_logic;
LMB_Read_Strobe_28 : out std_logic;
LMB_Write_Strobe_28 : out std_logic;
LMB_Ready_28 : in std_logic;
LMB_Wait_28 : in std_logic;
LMB_CE_28 : in std_logic;
LMB_UE_28 : in std_logic;
LMB_Byte_Enable_28 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_29 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_29 : out std_logic;
LMB_Read_Strobe_29 : out std_logic;
LMB_Write_Strobe_29 : out std_logic;
LMB_Ready_29 : in std_logic;
LMB_Wait_29 : in std_logic;
LMB_CE_29 : in std_logic;
LMB_UE_29 : in std_logic;
LMB_Byte_Enable_29 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_30 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_30 : out std_logic;
LMB_Read_Strobe_30 : out std_logic;
LMB_Write_Strobe_30 : out std_logic;
LMB_Ready_30 : in std_logic;
LMB_Wait_30 : in std_logic;
LMB_CE_30 : in std_logic;
LMB_UE_30 : in std_logic;
LMB_Byte_Enable_30 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_31 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_31 : out std_logic;
LMB_Read_Strobe_31 : out std_logic;
LMB_Write_Strobe_31 : out std_logic;
LMB_Ready_31 : in std_logic;
LMB_Wait_31 : in std_logic;
LMB_CE_31 : in std_logic;
LMB_UE_31 : in std_logic;
LMB_Byte_Enable_31 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External BSCAN inputs
-- These signals are used when C_USE_BSCAN = 2 (EXTERNAL)
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
-- External JTAG ports
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end entity MDM;
architecture IMP of MDM is
function int2std (val : integer) return std_logic is
begin -- function int2std
if (val = 0) then
return '0';
else
return '1';
end if;
end function int2std;
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0) := X"00000000";
constant C_REG_NUM_CE : integer := 4 + 4 * C_DBG_REG_ACCESS;
constant C_REG_DATA_WIDTH : integer := 8 + 24 * C_DBG_REG_ACCESS;
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) :=
(31 downto 5 => '0', 4 => int2std(C_DBG_REG_ACCESS), 3 downto 0 => '1');
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := (
-- Registers Base Address (not used)
ZEROES & C_BASEADDR,
ZEROES & (C_BASEADDR or C_S_AXI_MIN_SIZE)
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (
0 => C_REG_NUM_CE
);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
constant C_TRACE_AXI_MASTER : boolean := C_TRACE_OUTPUT = 3;
--------------------------------------------------------------------------
-- Component declarations
--------------------------------------------------------------------------
component MDM_Core
generic (
C_JTAG_CHAIN : integer;
C_USE_BSCAN : integer;
C_USE_CONFIG_RESET : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MB_DBG_PORTS : integer;
C_EN_WIDTH : integer;
C_DBG_REG_ACCESS : integer;
C_REG_NUM_CE : integer;
C_REG_DATA_WIDTH : integer;
C_DBG_MEM_ACCESS : integer;
C_S_AXI_ACLK_FREQ_HZ : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8;
C_TRACE_OUTPUT : integer;
C_TRACE_DATA_WIDTH : integer;
C_TRACE_CLK_FREQ_HZ : integer;
C_TRACE_CLK_OUT_PHASE : integer;
C_M_AXIS_DATA_WIDTH : integer;
C_M_AXIS_ID_WIDTH : integer);
port (
-- Global signals
Config_Reset : in std_logic;
Scan_Reset_Sel : in std_logic;
Scan_Reset : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- Debug Register Access signals
DbgReg_DRCK : out std_logic;
DbgReg_UPDATE : out std_logic;
DbgReg_Select : out std_logic;
JTAG_Busy : in std_logic;
-- AXI IPIC signals
bus2ip_clk : in std_logic;
bus2ip_resetn : in std_logic;
bus2ip_data : in std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
bus2ip_rdce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_wrce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
ip2bus_data : out std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
-- Bus Master signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
Master_dwr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_dwr_len : out std_logic_vector(4 downto 0);
Master_dwr_data : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_dwr_start : out std_logic;
Master_dwr_next : in std_logic;
Master_dwr_done : in std_logic;
Master_dwr_resp : in std_logic_vector(1 downto 0);
-- JTAG signals
JTAG_TDI : in std_logic;
JTAG_RESET : in std_logic;
UPDATE : in std_logic;
JTAG_SHIFT : in std_logic;
JTAG_CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
JTAG_TDO : out std_logic;
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External Trigger Signals
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- External JTAG
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component MDM_Core;
component bus_master is
generic (
C_M_AXI_DATA_WIDTH : natural;
C_M_AXI_THREAD_ID_WIDTH : natural;
C_M_AXI_ADDR_WIDTH : natural;
C_DATA_SIZE : natural;
C_HAS_FIFO_PORTS : boolean;
C_HAS_DIRECT_PORT : boolean
);
port (
Rd_Start : in std_logic;
Rd_Addr : in std_logic_vector(31 downto 0);
Rd_Len : in std_logic_vector(4 downto 0);
Rd_Size : in std_logic_vector(1 downto 0);
Rd_Exclusive : in std_logic;
Rd_Idle : out std_logic;
Rd_Response : out std_logic_vector(1 downto 0);
Wr_Start : in std_logic;
Wr_Addr : in std_logic_vector(31 downto 0);
Wr_Len : in std_logic_vector(4 downto 0);
Wr_Size : in std_logic_vector(1 downto 0);
Wr_Exclusive : in std_logic;
Wr_Idle : out std_logic;
Wr_Response : out std_logic_vector(1 downto 0);
Data_Rd : in std_logic;
Data_Out : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Exists : out std_logic;
Data_Wr : in std_logic;
Data_In : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Empty : out std_logic;
Direct_Wr_Addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Direct_Wr_Len : in std_logic_vector(4 downto 0);
Direct_Wr_Data : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Direct_Wr_Start : in std_logic;
Direct_Wr_Next : out std_logic;
Direct_Wr_Done : out std_logic;
Direct_Wr_Resp : out std_logic_vector(1 downto 0);
LMB_Data_Addr : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe : out std_logic;
LMB_Read_Strobe : out std_logic;
LMB_Write_Strobe : out std_logic;
LMB_Ready : in std_logic;
LMB_Wait : in std_logic;
LMB_UE : in std_logic;
LMB_Byte_Enable : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WLAST : out std_logic;
M_AXI_WDATA : out std_logic_vector(31 downto 0);
M_AXI_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(31 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end component bus_master;
--------------------------------------------------------------------------
-- Functions
--------------------------------------------------------------------------
-- Returns at least 1
function MakePos (a : integer) return integer is
begin
if a < 1 then
return 1;
else
return a;
end if;
end function MakePos;
constant C_EN_WIDTH : integer := MakePos(C_MB_DBG_PORTS);
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal tdi : std_logic;
signal reset : std_logic;
signal update : std_logic;
signal capture : std_logic;
signal shift : std_logic;
signal sel : std_logic;
signal drck : std_logic;
signal tdo : std_logic;
signal drck_i : std_logic;
signal update_i : std_logic;
signal dbgreg_drck : std_logic;
signal dbgreg_update : std_logic;
signal dbgreg_select : std_logic;
signal jtag_busy : std_logic;
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
signal bus2ip_cs : std_logic_vector(((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal mb_debug_enabled : std_logic_vector(C_EN_WIDTH-1 downto 0);
signal master_rd_start : std_logic;
signal master_rd_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_rd_len : std_logic_vector(4 downto 0);
signal master_rd_size : std_logic_vector(1 downto 0);
signal master_rd_excl : std_logic;
signal master_rd_idle : std_logic;
signal master_rd_resp : std_logic_vector(1 downto 0);
signal master_wr_start : std_logic;
signal master_wr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_wr_len : std_logic_vector(4 downto 0);
signal master_wr_size : std_logic_vector(1 downto 0);
signal master_wr_excl : std_logic;
signal master_wr_idle : std_logic;
signal master_wr_resp : std_logic_vector(1 downto 0);
signal master_data_rd : std_logic;
signal master_data_out : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_exists : std_logic;
signal master_data_wr : std_logic;
signal master_data_in : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_empty : std_logic;
signal master_dwr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_dwr_len : std_logic_vector(4 downto 0);
signal master_dwr_data : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_dwr_start : std_logic;
signal master_dwr_next : std_logic;
signal master_dwr_done : std_logic;
signal master_dwr_resp : std_logic_vector(1 downto 0);
signal ext_trig_in : std_logic_vector(0 to 3);
signal ext_trig_Ack_In : std_logic_vector(0 to 3);
signal ext_trig_out : std_logic_vector(0 to 3);
signal ext_trig_Ack_Out : std_logic_vector(0 to 3);
--------------------------------------------------------------------------
-- Attibute declarations
--------------------------------------------------------------------------
attribute period : string;
attribute period of update : signal is "200 ns";
attribute buffer_type : string;
attribute buffer_type of update_i : signal is "none";
attribute buffer_type of MDM_Core_I1 : label is "none";
begin -- architecture IMP
Use_E2 : if C_USE_BSCAN /= 2 generate
begin
BSCANE2_I : BSCANE2
generic map (
DISABLE_JTAG => "FALSE",
JTAG_CHAIN => C_JTAG_CHAIN)
port map (
CAPTURE => capture, -- [out std_logic]
DRCK => drck_i, -- [out std_logic]
RESET => reset, -- [out std_logic]
RUNTEST => open, -- [out std_logic]
SEL => sel, -- [out std_logic]
SHIFT => shift, -- [out std_logic]
TCK => open, -- [out std_logic]
TDI => tdi, -- [out std_logic]
TMS => open, -- [out std_logic]
UPDATE => update_i, -- [out std_logic]
TDO => tdo); -- [in std_logic]
end generate Use_E2;
Use_External : if C_USE_BSCAN = 2 generate
begin
capture <= bscan_ext_capture;
drck_i <= bscan_ext_drck;
reset <= bscan_ext_reset;
sel <= bscan_ext_sel;
shift <= bscan_ext_shift;
tdi <= bscan_ext_tdi;
update_i <= bscan_ext_update;
bscan_ext_tdo <= tdo;
end generate Use_External;
No_External : if C_USE_BSCAN /= 2 generate
begin
bscan_ext_tdo <= '0';
end generate No_External;
Use_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 1 generate
signal dbgreg_select_n : std_logic;
signal dbgreg_drck_i : std_logic;
signal dbgreg_update_i : std_logic;
signal update_set : std_logic;
signal update_reset : std_logic;
begin
dbgreg_select_n <= not dbgreg_select;
-- drck <= dbgreg_drck when dbgreg_select = '1' else drck_i;
BUFG_DRCK : BUFG
port map (
O => dbgreg_drck_i,
I => dbgreg_drck
);
BUFGCTRL_DRCK : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => drck,
CE0 => '1',
CE1 => '1',
I0 => drck_i,
I1 => dbgreg_drck_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
-- update <= dbgreg_update when dbgreg_select = '1' else update_i;
BUFG_UPDATE : BUFG
port map (
O => dbgreg_update_i,
I => dbgreg_update
);
BUFGCTRL_UPDATE : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => update,
CE0 => '1',
CE1 => '1',
I0 => update_i,
I1 => dbgreg_update_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
JTAG_Busy_Detect : process (drck_i, sel, update_set, Config_Reset)
begin
if sel = '0' or update_set = '1' or Config_Reset = '1' then
jtag_busy <= '0';
update_reset <= '1';
elsif drck_i'event and drck_i = '1' then
if sel = '1' and capture = '1' then
jtag_busy <= '1';
end if;
update_reset <= '0';
end if;
end process JTAG_Busy_Detect;
JTAG_Update_Detect : process (update_i, update_reset, Config_Reset)
begin
if update_reset = '1' or Config_Reset = '1' then
update_set <= '0';
elsif update_i'event and update_i = '1' then
update_set <= '1';
end if;
end process JTAG_Update_Detect;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 0 generate
begin
BUFG_DRCK : BUFG
port map (
O => drck,
I => drck_i
);
update <= update_i;
jtag_busy <= '0';
end generate No_Dbg_Reg_Access;
---------------------------------------------------------------------------
-- MDM core
---------------------------------------------------------------------------
MDM_Core_I1 : MDM_Core
generic map (
C_JTAG_CHAIN => C_JTAG_CHAIN, -- [integer]
C_USE_BSCAN => C_USE_BSCAN, -- [integer]
C_USE_CONFIG_RESET => C_USE_CONFIG_RESET, -- [integer = 0]
C_BASEADDR => C_BASEADDR, -- [std_logic_vector(0 to 31)]
C_HIGHADDR => C_HIGHADDR, -- [std_logic_vector(0 to 31)]
C_MB_DBG_PORTS => C_MB_DBG_PORTS, -- [integer]
C_EN_WIDTH => C_EN_WIDTH, -- [integer]
C_DBG_REG_ACCESS => C_DBG_REG_ACCESS, -- [integer]
C_REG_NUM_CE => C_REG_NUM_CE, -- [integer]
C_REG_DATA_WIDTH => C_REG_DATA_WIDTH, -- [integer]
C_DBG_MEM_ACCESS => C_DBG_MEM_ACCESS, -- [integer]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ, -- [integer]
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH, -- [integer]
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH, -- [integer]
C_USE_CROSS_TRIGGER => C_USE_CROSS_TRIGGER, -- [integer]
C_USE_UART => C_USE_UART, -- [integer]
C_UART_WIDTH => 8, -- [integer]
C_TRACE_OUTPUT => C_TRACE_OUTPUT, -- [integer]
C_TRACE_DATA_WIDTH => C_TRACE_DATA_WIDTH, -- [integer]
C_TRACE_CLK_FREQ_HZ => C_TRACE_CLK_FREQ_HZ, -- [integer]
C_TRACE_CLK_OUT_PHASE => C_TRACE_CLK_OUT_PHASE, -- [integer]
C_M_AXIS_DATA_WIDTH => C_M_AXIS_DATA_WIDTH, -- [integer]
C_M_AXIS_ID_WIDTH => C_M_AXIS_ID_WIDTH -- [integer]
)
port map (
-- Global signals
Config_Reset => Config_Reset, -- [in std_logic]
Scan_Reset_Sel => Scan_Reset_Sel, -- [in std_logic]
Scan_Reset => Scan_Reset, -- [in std_logic]
M_AXIS_ACLK => M_AXIS_ACLK, -- [in std_logic]
M_AXIS_ARESETN => M_AXIS_ARESETN, -- [in std_logic]
Interrupt => Interrupt, -- [out std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst, -- [out std_logic]
-- Debug Register Access signals
DbgReg_DRCK => dbgreg_drck, -- [out std_logic]
DbgReg_UPDATE => dbgreg_update, -- [out std_logic]
DbgReg_Select => dbgreg_select, -- [out std_logic]
JTAG_Busy => jtag_busy, -- [in std_logic]
-- AXI IPIC signals
bus2ip_clk => bus2ip_clk,
bus2ip_resetn => bus2ip_resetn,
bus2ip_data => bus2ip_data(C_REG_DATA_WIDTH-1 downto 0),
bus2ip_rdce => bus2ip_rdce(C_REG_NUM_CE-1 downto 0),
bus2ip_wrce => bus2ip_wrce(C_REG_NUM_CE-1 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
ip2bus_data => ip2bus_data(C_REG_DATA_WIDTH-1 downto 0),
-- Bus Master signals
MB_Debug_Enabled => mb_debug_enabled,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
Master_rd_start => master_rd_start,
Master_rd_addr => master_rd_addr,
Master_rd_len => master_rd_len,
Master_rd_size => master_rd_size,
Master_rd_excl => master_rd_excl,
Master_rd_idle => master_rd_idle,
Master_rd_resp => master_rd_resp,
Master_wr_start => master_wr_start,
Master_wr_addr => master_wr_addr,
Master_wr_len => master_wr_len,
Master_wr_size => master_wr_size,
Master_wr_excl => master_wr_excl,
Master_wr_idle => master_wr_idle,
Master_wr_resp => master_wr_resp,
Master_data_rd => master_data_rd,
Master_data_out => master_data_out,
Master_data_exists => master_data_exists,
Master_data_wr => master_data_wr,
Master_data_in => master_data_in,
Master_data_empty => master_data_empty,
Master_dwr_addr => master_dwr_addr,
Master_dwr_len => master_dwr_len,
Master_dwr_data => master_dwr_data,
Master_dwr_start => master_dwr_start,
Master_dwr_next => master_dwr_next,
Master_dwr_done => master_dwr_done,
Master_dwr_resp => master_dwr_resp,
-- JTAG signals
JTAG_TDI => tdi, -- [in std_logic]
JTAG_RESET => reset, -- [in std_logic]
UPDATE => update, -- [in std_logic]
JTAG_SHIFT => shift, -- [in std_logic]
JTAG_CAPTURE => capture, -- [in std_logic]
SEL => sel, -- [in std_logic]
DRCK => drck, -- [in std_logic]
JTAG_TDO => tdo, -- [out std_logic]
-- External Trace AXI Stream output
M_AXIS_TDATA => M_AXIS_TDATA, -- [out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0)]
M_AXIS_TID => M_AXIS_TID, -- [out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0)]
M_AXIS_TREADY => M_AXIS_TREADY, -- [in std_logic]
M_AXIS_TVALID => M_AXIS_TVALID, -- [out std_logic]
-- External Trace output
TRACE_CLK_OUT => TRACE_CLK_OUT, -- [out std_logic]
TRACE_CLK => TRACE_CLK, -- [in std_logic]
TRACE_CTL => TRACE_CTL, -- [out std_logic]
TRACE_DATA => TRACE_DATA, -- [out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0)]
-- MicroBlaze Debug Signals
Dbg_Clk_0 => Dbg_Clk_0, -- [out std_logic]
Dbg_TDI_0 => Dbg_TDI_0, -- [out std_logic]
Dbg_TDO_0 => Dbg_TDO_0, -- [in std_logic]
Dbg_Reg_En_0 => Dbg_Reg_En_0, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_0 => Dbg_Capture_0, -- [out std_logic]
Dbg_Shift_0 => Dbg_Shift_0, -- [out std_logic]
Dbg_Update_0 => Dbg_Update_0, -- [out std_logic]
Dbg_Rst_0 => Dbg_Rst_0, -- [out std_logic]
Dbg_Trig_In_0 => Dbg_Trig_In_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_0 => Dbg_Trig_Ack_In_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_0 => Dbg_Trig_Out_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_0 => Dbg_Trig_Ack_Out_0, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_0 => Dbg_TrClk_0, -- [out std_logic]
Dbg_TrData_0 => Dbg_TrData_0, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_0 => Dbg_TrReady_0, -- [out std_logic]
Dbg_TrValid_0 => Dbg_TrValid_0, -- [in std_logic]
Dbg_Clk_1 => Dbg_Clk_1, -- [out std_logic]
Dbg_TDI_1 => Dbg_TDI_1, -- [out std_logic]
Dbg_TDO_1 => Dbg_TDO_1, -- [in std_logic]
Dbg_Reg_En_1 => Dbg_Reg_En_1, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_1 => Dbg_Capture_1, -- [out std_logic]
Dbg_Shift_1 => Dbg_Shift_1, -- [out std_logic]
Dbg_Update_1 => Dbg_Update_1, -- [out std_logic]
Dbg_Rst_1 => Dbg_Rst_1, -- [out std_logic]
Dbg_Trig_In_1 => Dbg_Trig_In_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_1 => Dbg_Trig_Ack_In_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_1 => Dbg_Trig_Out_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_1 => Dbg_Trig_Ack_Out_1, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_1 => Dbg_TrClk_1, -- [out std_logic]
Dbg_TrData_1 => Dbg_TrData_1, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_1 => Dbg_TrReady_1, -- [out std_logic]
Dbg_TrValid_1 => Dbg_TrValid_1, -- [in std_logic]
Dbg_Clk_2 => Dbg_Clk_2, -- [out std_logic]
Dbg_TDI_2 => Dbg_TDI_2, -- [out std_logic]
Dbg_TDO_2 => Dbg_TDO_2, -- [in std_logic]
Dbg_Reg_En_2 => Dbg_Reg_En_2, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_2 => Dbg_Capture_2, -- [out std_logic]
Dbg_Shift_2 => Dbg_Shift_2, -- [out std_logic]
Dbg_Update_2 => Dbg_Update_2, -- [out std_logic]
Dbg_Rst_2 => Dbg_Rst_2, -- [out std_logic]
Dbg_Trig_In_2 => Dbg_Trig_In_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_2 => Dbg_Trig_Ack_In_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_2 => Dbg_Trig_Out_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_2 => Dbg_Trig_Ack_Out_2, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_2 => Dbg_TrClk_2, -- [out std_logic]
Dbg_TrData_2 => Dbg_TrData_2, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_2 => Dbg_TrReady_2, -- [out std_logic]
Dbg_TrValid_2 => Dbg_TrValid_2, -- [in std_logic]
Dbg_Clk_3 => Dbg_Clk_3, -- [out std_logic]
Dbg_TDI_3 => Dbg_TDI_3, -- [out std_logic]
Dbg_TDO_3 => Dbg_TDO_3, -- [in std_logic]
Dbg_Reg_En_3 => Dbg_Reg_En_3, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_3 => Dbg_Capture_3, -- [out std_logic]
Dbg_Shift_3 => Dbg_Shift_3, -- [out std_logic]
Dbg_Update_3 => Dbg_Update_3, -- [out std_logic]
Dbg_Rst_3 => Dbg_Rst_3, -- [out std_logic]
Dbg_Trig_In_3 => Dbg_Trig_In_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_3 => Dbg_Trig_Ack_In_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_3 => Dbg_Trig_Out_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_3 => Dbg_Trig_Ack_Out_3, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_3 => Dbg_TrClk_3, -- [out std_logic]
Dbg_TrData_3 => Dbg_TrData_3, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_3 => Dbg_TrReady_3, -- [out std_logic]
Dbg_TrValid_3 => Dbg_TrValid_3, -- [in std_logic]
Dbg_Clk_4 => Dbg_Clk_4, -- [out std_logic]
Dbg_TDI_4 => Dbg_TDI_4, -- [out std_logic]
Dbg_TDO_4 => Dbg_TDO_4, -- [in std_logic]
Dbg_Reg_En_4 => Dbg_Reg_En_4, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_4 => Dbg_Capture_4, -- [out std_logic]
Dbg_Shift_4 => Dbg_Shift_4, -- [out std_logic]
Dbg_Update_4 => Dbg_Update_4, -- [out std_logic]
Dbg_Rst_4 => Dbg_Rst_4, -- [out std_logic]
Dbg_Trig_In_4 => Dbg_Trig_In_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_4 => Dbg_Trig_Ack_In_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_4 => Dbg_Trig_Out_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_4 => Dbg_Trig_Ack_Out_4, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_4 => Dbg_TrClk_4, -- [out std_logic]
Dbg_TrData_4 => Dbg_TrData_4, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_4 => Dbg_TrReady_4, -- [out std_logic]
Dbg_TrValid_4 => Dbg_TrValid_4, -- [in std_logic]
Dbg_Clk_5 => Dbg_Clk_5, -- [out std_logic]
Dbg_TDI_5 => Dbg_TDI_5, -- [out std_logic]
Dbg_TDO_5 => Dbg_TDO_5, -- [in std_logic]
Dbg_Reg_En_5 => Dbg_Reg_En_5, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_5 => Dbg_Capture_5, -- [out std_logic]
Dbg_Shift_5 => Dbg_Shift_5, -- [out std_logic]
Dbg_Update_5 => Dbg_Update_5, -- [out std_logic]
Dbg_Rst_5 => Dbg_Rst_5, -- [out std_logic]
Dbg_Trig_In_5 => Dbg_Trig_In_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_5 => Dbg_Trig_Ack_In_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_5 => Dbg_Trig_Out_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_5 => Dbg_Trig_Ack_Out_5, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_5 => Dbg_TrClk_5, -- [out std_logic]
Dbg_TrData_5 => Dbg_TrData_5, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_5 => Dbg_TrReady_5, -- [out std_logic]
Dbg_TrValid_5 => Dbg_TrValid_5, -- [in std_logic]
Dbg_Clk_6 => Dbg_Clk_6, -- [out std_logic]
Dbg_TDI_6 => Dbg_TDI_6, -- [out std_logic]
Dbg_TDO_6 => Dbg_TDO_6, -- [in std_logic]
Dbg_Reg_En_6 => Dbg_Reg_En_6, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_6 => Dbg_Capture_6, -- [out std_logic]
Dbg_Shift_6 => Dbg_Shift_6, -- [out std_logic]
Dbg_Update_6 => Dbg_Update_6, -- [out std_logic]
Dbg_Rst_6 => Dbg_Rst_6, -- [out std_logic]
Dbg_Trig_In_6 => Dbg_Trig_In_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_6 => Dbg_Trig_Ack_In_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_6 => Dbg_Trig_Out_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_6 => Dbg_Trig_Ack_Out_6, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_6 => Dbg_TrClk_6, -- [out std_logic]
Dbg_TrData_6 => Dbg_TrData_6, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_6 => Dbg_TrReady_6, -- [out std_logic]
Dbg_TrValid_6 => Dbg_TrValid_6, -- [in std_logic]
Dbg_Clk_7 => Dbg_Clk_7, -- [out std_logic]
Dbg_TDI_7 => Dbg_TDI_7, -- [out std_logic]
Dbg_TDO_7 => Dbg_TDO_7, -- [in std_logic]
Dbg_Reg_En_7 => Dbg_Reg_En_7, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_7 => Dbg_Capture_7, -- [out std_logic]
Dbg_Shift_7 => Dbg_Shift_7, -- [out std_logic]
Dbg_Update_7 => Dbg_Update_7, -- [out std_logic]
Dbg_Rst_7 => Dbg_Rst_7, -- [out std_logic]
Dbg_Trig_In_7 => Dbg_Trig_In_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_7 => Dbg_Trig_Ack_In_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_7 => Dbg_Trig_Out_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_7 => Dbg_Trig_Ack_Out_7, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_7 => Dbg_TrClk_7, -- [out std_logic]
Dbg_TrData_7 => Dbg_TrData_7, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_7 => Dbg_TrReady_7, -- [out std_logic]
Dbg_TrValid_7 => Dbg_TrValid_7, -- [in std_logic]
Dbg_Clk_8 => Dbg_Clk_8, -- [out std_logic]
Dbg_TDI_8 => Dbg_TDI_8, -- [out std_logic]
Dbg_TDO_8 => Dbg_TDO_8, -- [in std_logic]
Dbg_Reg_En_8 => Dbg_Reg_En_8, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_8 => Dbg_Capture_8, -- [out std_logic]
Dbg_Shift_8 => Dbg_Shift_8, -- [out std_logic]
Dbg_Update_8 => Dbg_Update_8, -- [out std_logic]
Dbg_Rst_8 => Dbg_Rst_8, -- [out std_logic]
Dbg_Trig_In_8 => Dbg_Trig_In_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_8 => Dbg_Trig_Ack_In_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_8 => Dbg_Trig_Out_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_8 => Dbg_Trig_Ack_Out_8, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_8 => Dbg_TrClk_8, -- [out std_logic]
Dbg_TrData_8 => Dbg_TrData_8, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_8 => Dbg_TrReady_8, -- [out std_logic]
Dbg_TrValid_8 => Dbg_TrValid_8, -- [in std_logic]
Dbg_Clk_9 => Dbg_Clk_9, -- [out std_logic]
Dbg_TDI_9 => Dbg_TDI_9, -- [out std_logic]
Dbg_TDO_9 => Dbg_TDO_9, -- [in std_logic]
Dbg_Reg_En_9 => Dbg_Reg_En_9, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_9 => Dbg_Capture_9, -- [out std_logic]
Dbg_Shift_9 => Dbg_Shift_9, -- [out std_logic]
Dbg_Update_9 => Dbg_Update_9, -- [out std_logic]
Dbg_Rst_9 => Dbg_Rst_9, -- [out std_logic]
Dbg_Trig_In_9 => Dbg_Trig_In_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_9 => Dbg_Trig_Ack_In_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_9 => Dbg_Trig_Out_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_9 => Dbg_Trig_Ack_Out_9, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_9 => Dbg_TrClk_9, -- [out std_logic]
Dbg_TrData_9 => Dbg_TrData_9, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_9 => Dbg_TrReady_9, -- [out std_logic]
Dbg_TrValid_9 => Dbg_TrValid_9, -- [in std_logic]
Dbg_Clk_10 => Dbg_Clk_10, -- [out std_logic]
Dbg_TDI_10 => Dbg_TDI_10, -- [out std_logic]
Dbg_TDO_10 => Dbg_TDO_10, -- [in std_logic]
Dbg_Reg_En_10 => Dbg_Reg_En_10, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_10 => Dbg_Capture_10, -- [out std_logic]
Dbg_Shift_10 => Dbg_Shift_10, -- [out std_logic]
Dbg_Update_10 => Dbg_Update_10, -- [out std_logic]
Dbg_Rst_10 => Dbg_Rst_10, -- [out std_logic]
Dbg_Trig_In_10 => Dbg_Trig_In_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_10 => Dbg_Trig_Ack_In_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_10 => Dbg_Trig_Out_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_10 => Dbg_Trig_Ack_Out_10, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_10 => Dbg_TrClk_10, -- [out std_logic]
Dbg_TrData_10 => Dbg_TrData_10, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_10 => Dbg_TrReady_10, -- [out std_logic]
Dbg_TrValid_10 => Dbg_TrValid_10, -- [in std_logic]
Dbg_Clk_11 => Dbg_Clk_11, -- [out std_logic]
Dbg_TDI_11 => Dbg_TDI_11, -- [out std_logic]
Dbg_TDO_11 => Dbg_TDO_11, -- [in std_logic]
Dbg_Reg_En_11 => Dbg_Reg_En_11, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_11 => Dbg_Capture_11, -- [out std_logic]
Dbg_Shift_11 => Dbg_Shift_11, -- [out std_logic]
Dbg_Update_11 => Dbg_Update_11, -- [out std_logic]
Dbg_Rst_11 => Dbg_Rst_11, -- [out std_logic]
Dbg_Trig_In_11 => Dbg_Trig_In_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_11 => Dbg_Trig_Ack_In_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_11 => Dbg_Trig_Out_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_11 => Dbg_Trig_Ack_Out_11, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_11 => Dbg_TrClk_11, -- [out std_logic]
Dbg_TrData_11 => Dbg_TrData_11, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_11 => Dbg_TrReady_11, -- [out std_logic]
Dbg_TrValid_11 => Dbg_TrValid_11, -- [in std_logic]
Dbg_Clk_12 => Dbg_Clk_12, -- [out std_logic]
Dbg_TDI_12 => Dbg_TDI_12, -- [out std_logic]
Dbg_TDO_12 => Dbg_TDO_12, -- [in std_logic]
Dbg_Reg_En_12 => Dbg_Reg_En_12, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_12 => Dbg_Capture_12, -- [out std_logic]
Dbg_Shift_12 => Dbg_Shift_12, -- [out std_logic]
Dbg_Update_12 => Dbg_Update_12, -- [out std_logic]
Dbg_Rst_12 => Dbg_Rst_12, -- [out std_logic]
Dbg_Trig_In_12 => Dbg_Trig_In_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_12 => Dbg_Trig_Ack_In_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_12 => Dbg_Trig_Out_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_12 => Dbg_Trig_Ack_Out_12, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_12 => Dbg_TrClk_12, -- [out std_logic]
Dbg_TrData_12 => Dbg_TrData_12, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_12 => Dbg_TrReady_12, -- [out std_logic]
Dbg_TrValid_12 => Dbg_TrValid_12, -- [in std_logic]
Dbg_Clk_13 => Dbg_Clk_13, -- [out std_logic]
Dbg_TDI_13 => Dbg_TDI_13, -- [out std_logic]
Dbg_TDO_13 => Dbg_TDO_13, -- [in std_logic]
Dbg_Reg_En_13 => Dbg_Reg_En_13, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_13 => Dbg_Capture_13, -- [out std_logic]
Dbg_Shift_13 => Dbg_Shift_13, -- [out std_logic]
Dbg_Update_13 => Dbg_Update_13, -- [out std_logic]
Dbg_Rst_13 => Dbg_Rst_13, -- [out std_logic]
Dbg_Trig_In_13 => Dbg_Trig_In_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_13 => Dbg_Trig_Ack_In_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_13 => Dbg_Trig_Out_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_13 => Dbg_Trig_Ack_Out_13, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_13 => Dbg_TrClk_13, -- [out std_logic]
Dbg_TrData_13 => Dbg_TrData_13, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_13 => Dbg_TrReady_13, -- [out std_logic]
Dbg_TrValid_13 => Dbg_TrValid_13, -- [in std_logic]
Dbg_Clk_14 => Dbg_Clk_14, -- [out std_logic]
Dbg_TDI_14 => Dbg_TDI_14, -- [out std_logic]
Dbg_TDO_14 => Dbg_TDO_14, -- [in std_logic]
Dbg_Reg_En_14 => Dbg_Reg_En_14, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_14 => Dbg_Capture_14, -- [out std_logic]
Dbg_Shift_14 => Dbg_Shift_14, -- [out std_logic]
Dbg_Update_14 => Dbg_Update_14, -- [out std_logic]
Dbg_Rst_14 => Dbg_Rst_14, -- [out std_logic]
Dbg_Trig_In_14 => Dbg_Trig_In_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_14 => Dbg_Trig_Ack_In_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_14 => Dbg_Trig_Out_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_14 => Dbg_Trig_Ack_Out_14, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_14 => Dbg_TrClk_14, -- [out std_logic]
Dbg_TrData_14 => Dbg_TrData_14, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_14 => Dbg_TrReady_14, -- [out std_logic]
Dbg_TrValid_14 => Dbg_TrValid_14, -- [in std_logic]
Dbg_Clk_15 => Dbg_Clk_15, -- [out std_logic]
Dbg_TDI_15 => Dbg_TDI_15, -- [out std_logic]
Dbg_TDO_15 => Dbg_TDO_15, -- [in std_logic]
Dbg_Reg_En_15 => Dbg_Reg_En_15, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_15 => Dbg_Capture_15, -- [out std_logic]
Dbg_Shift_15 => Dbg_Shift_15, -- [out std_logic]
Dbg_Update_15 => Dbg_Update_15, -- [out std_logic]
Dbg_Rst_15 => Dbg_Rst_15, -- [out std_logic]
Dbg_Trig_In_15 => Dbg_Trig_In_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_15 => Dbg_Trig_Ack_In_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_15 => Dbg_Trig_Out_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_15 => Dbg_Trig_Ack_Out_15, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_15 => Dbg_TrClk_15, -- [out std_logic]
Dbg_TrData_15 => Dbg_TrData_15, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_15 => Dbg_TrReady_15, -- [out std_logic]
Dbg_TrValid_15 => Dbg_TrValid_15, -- [in std_logic]
Dbg_Clk_16 => Dbg_Clk_16, -- [out std_logic]
Dbg_TDI_16 => Dbg_TDI_16, -- [out std_logic]
Dbg_TDO_16 => Dbg_TDO_16, -- [in std_logic]
Dbg_Reg_En_16 => Dbg_Reg_En_16, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_16 => Dbg_Capture_16, -- [out std_logic]
Dbg_Shift_16 => Dbg_Shift_16, -- [out std_logic]
Dbg_Update_16 => Dbg_Update_16, -- [out std_logic]
Dbg_Rst_16 => Dbg_Rst_16, -- [out std_logic]
Dbg_Trig_In_16 => Dbg_Trig_In_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_16 => Dbg_Trig_Ack_In_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_16 => Dbg_Trig_Out_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_16 => Dbg_Trig_Ack_Out_16, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_16 => Dbg_TrClk_16, -- [out std_logic]
Dbg_TrData_16 => Dbg_TrData_16, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_16 => Dbg_TrReady_16, -- [out std_logic]
Dbg_TrValid_16 => Dbg_TrValid_16, -- [in std_logic]
Dbg_Clk_17 => Dbg_Clk_17, -- [out std_logic]
Dbg_TDI_17 => Dbg_TDI_17, -- [out std_logic]
Dbg_TDO_17 => Dbg_TDO_17, -- [in std_logic]
Dbg_Reg_En_17 => Dbg_Reg_En_17, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_17 => Dbg_Capture_17, -- [out std_logic]
Dbg_Shift_17 => Dbg_Shift_17, -- [out std_logic]
Dbg_Update_17 => Dbg_Update_17, -- [out std_logic]
Dbg_Rst_17 => Dbg_Rst_17, -- [out std_logic]
Dbg_Trig_In_17 => Dbg_Trig_In_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_17 => Dbg_Trig_Ack_In_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_17 => Dbg_Trig_Out_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_17 => Dbg_Trig_Ack_Out_17, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_17 => Dbg_TrClk_17, -- [out std_logic]
Dbg_TrData_17 => Dbg_TrData_17, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_17 => Dbg_TrReady_17, -- [out std_logic]
Dbg_TrValid_17 => Dbg_TrValid_17, -- [in std_logic]
Dbg_Clk_18 => Dbg_Clk_18, -- [out std_logic]
Dbg_TDI_18 => Dbg_TDI_18, -- [out std_logic]
Dbg_TDO_18 => Dbg_TDO_18, -- [in std_logic]
Dbg_Reg_En_18 => Dbg_Reg_En_18, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_18 => Dbg_Capture_18, -- [out std_logic]
Dbg_Shift_18 => Dbg_Shift_18, -- [out std_logic]
Dbg_Update_18 => Dbg_Update_18, -- [out std_logic]
Dbg_Rst_18 => Dbg_Rst_18, -- [out std_logic]
Dbg_Trig_In_18 => Dbg_Trig_In_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_18 => Dbg_Trig_Ack_In_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_18 => Dbg_Trig_Out_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_18 => Dbg_Trig_Ack_Out_18, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_18 => Dbg_TrClk_18, -- [out std_logic]
Dbg_TrData_18 => Dbg_TrData_18, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_18 => Dbg_TrReady_18, -- [out std_logic]
Dbg_TrValid_18 => Dbg_TrValid_18, -- [in std_logic]
Dbg_Clk_19 => Dbg_Clk_19, -- [out std_logic]
Dbg_TDI_19 => Dbg_TDI_19, -- [out std_logic]
Dbg_TDO_19 => Dbg_TDO_19, -- [in std_logic]
Dbg_Reg_En_19 => Dbg_Reg_En_19, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_19 => Dbg_Capture_19, -- [out std_logic]
Dbg_Shift_19 => Dbg_Shift_19, -- [out std_logic]
Dbg_Update_19 => Dbg_Update_19, -- [out std_logic]
Dbg_Rst_19 => Dbg_Rst_19, -- [out std_logic]
Dbg_Trig_In_19 => Dbg_Trig_In_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_19 => Dbg_Trig_Ack_In_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_19 => Dbg_Trig_Out_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_19 => Dbg_Trig_Ack_Out_19, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_19 => Dbg_TrClk_19, -- [out std_logic]
Dbg_TrData_19 => Dbg_TrData_19, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_19 => Dbg_TrReady_19, -- [out std_logic]
Dbg_TrValid_19 => Dbg_TrValid_19, -- [in std_logic]
Dbg_Clk_20 => Dbg_Clk_20, -- [out std_logic]
Dbg_TDI_20 => Dbg_TDI_20, -- [out std_logic]
Dbg_TDO_20 => Dbg_TDO_20, -- [in std_logic]
Dbg_Reg_En_20 => Dbg_Reg_En_20, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_20 => Dbg_Capture_20, -- [out std_logic]
Dbg_Shift_20 => Dbg_Shift_20, -- [out std_logic]
Dbg_Update_20 => Dbg_Update_20, -- [out std_logic]
Dbg_Rst_20 => Dbg_Rst_20, -- [out std_logic]
Dbg_Trig_In_20 => Dbg_Trig_In_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_20 => Dbg_Trig_Ack_In_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_20 => Dbg_Trig_Out_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_20 => Dbg_Trig_Ack_Out_20, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_20 => Dbg_TrClk_20, -- [out std_logic]
Dbg_TrData_20 => Dbg_TrData_20, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_20 => Dbg_TrReady_20, -- [out std_logic]
Dbg_TrValid_20 => Dbg_TrValid_20, -- [in std_logic]
Dbg_Clk_21 => Dbg_Clk_21, -- [out std_logic]
Dbg_TDI_21 => Dbg_TDI_21, -- [out std_logic]
Dbg_TDO_21 => Dbg_TDO_21, -- [in std_logic]
Dbg_Reg_En_21 => Dbg_Reg_En_21, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_21 => Dbg_Capture_21, -- [out std_logic]
Dbg_Shift_21 => Dbg_Shift_21, -- [out std_logic]
Dbg_Update_21 => Dbg_Update_21, -- [out std_logic]
Dbg_Rst_21 => Dbg_Rst_21, -- [out std_logic]
Dbg_Trig_In_21 => Dbg_Trig_In_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_21 => Dbg_Trig_Ack_In_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_21 => Dbg_Trig_Out_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_21 => Dbg_Trig_Ack_Out_21, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_21 => Dbg_TrClk_21, -- [out std_logic]
Dbg_TrData_21 => Dbg_TrData_21, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_21 => Dbg_TrReady_21, -- [out std_logic]
Dbg_TrValid_21 => Dbg_TrValid_21, -- [in std_logic]
Dbg_Clk_22 => Dbg_Clk_22, -- [out std_logic]
Dbg_TDI_22 => Dbg_TDI_22, -- [out std_logic]
Dbg_TDO_22 => Dbg_TDO_22, -- [in std_logic]
Dbg_Reg_En_22 => Dbg_Reg_En_22, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_22 => Dbg_Capture_22, -- [out std_logic]
Dbg_Shift_22 => Dbg_Shift_22, -- [out std_logic]
Dbg_Update_22 => Dbg_Update_22, -- [out std_logic]
Dbg_Rst_22 => Dbg_Rst_22, -- [out std_logic]
Dbg_Trig_In_22 => Dbg_Trig_In_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_22 => Dbg_Trig_Ack_In_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_22 => Dbg_Trig_Out_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_22 => Dbg_Trig_Ack_Out_22, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_22 => Dbg_TrClk_22, -- [out std_logic]
Dbg_TrData_22 => Dbg_TrData_22, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_22 => Dbg_TrReady_22, -- [out std_logic]
Dbg_TrValid_22 => Dbg_TrValid_22, -- [in std_logic]
Dbg_Clk_23 => Dbg_Clk_23, -- [out std_logic]
Dbg_TDI_23 => Dbg_TDI_23, -- [out std_logic]
Dbg_TDO_23 => Dbg_TDO_23, -- [in std_logic]
Dbg_Reg_En_23 => Dbg_Reg_En_23, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_23 => Dbg_Capture_23, -- [out std_logic]
Dbg_Shift_23 => Dbg_Shift_23, -- [out std_logic]
Dbg_Update_23 => Dbg_Update_23, -- [out std_logic]
Dbg_Rst_23 => Dbg_Rst_23, -- [out std_logic]
Dbg_Trig_In_23 => Dbg_Trig_In_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_23 => Dbg_Trig_Ack_In_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_23 => Dbg_Trig_Out_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_23 => Dbg_Trig_Ack_Out_23, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_23 => Dbg_TrClk_23, -- [out std_logic]
Dbg_TrData_23 => Dbg_TrData_23, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_23 => Dbg_TrReady_23, -- [out std_logic]
Dbg_TrValid_23 => Dbg_TrValid_23, -- [in std_logic]
Dbg_Clk_24 => Dbg_Clk_24, -- [out std_logic]
Dbg_TDI_24 => Dbg_TDI_24, -- [out std_logic]
Dbg_TDO_24 => Dbg_TDO_24, -- [in std_logic]
Dbg_Reg_En_24 => Dbg_Reg_En_24, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_24 => Dbg_Capture_24, -- [out std_logic]
Dbg_Shift_24 => Dbg_Shift_24, -- [out std_logic]
Dbg_Update_24 => Dbg_Update_24, -- [out std_logic]
Dbg_Rst_24 => Dbg_Rst_24, -- [out std_logic]
Dbg_Trig_In_24 => Dbg_Trig_In_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_24 => Dbg_Trig_Ack_In_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_24 => Dbg_Trig_Out_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_24 => Dbg_Trig_Ack_Out_24, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_24 => Dbg_TrClk_24, -- [out std_logic]
Dbg_TrData_24 => Dbg_TrData_24, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_24 => Dbg_TrReady_24, -- [out std_logic]
Dbg_TrValid_24 => Dbg_TrValid_24, -- [in std_logic]
Dbg_Clk_25 => Dbg_Clk_25, -- [out std_logic]
Dbg_TDI_25 => Dbg_TDI_25, -- [out std_logic]
Dbg_TDO_25 => Dbg_TDO_25, -- [in std_logic]
Dbg_Reg_En_25 => Dbg_Reg_En_25, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_25 => Dbg_Capture_25, -- [out std_logic]
Dbg_Shift_25 => Dbg_Shift_25, -- [out std_logic]
Dbg_Update_25 => Dbg_Update_25, -- [out std_logic]
Dbg_Rst_25 => Dbg_Rst_25, -- [out std_logic]
Dbg_Trig_In_25 => Dbg_Trig_In_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_25 => Dbg_Trig_Ack_In_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_25 => Dbg_Trig_Out_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_25 => Dbg_Trig_Ack_Out_25, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_25 => Dbg_TrClk_25, -- [out std_logic]
Dbg_TrData_25 => Dbg_TrData_25, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_25 => Dbg_TrReady_25, -- [out std_logic]
Dbg_TrValid_25 => Dbg_TrValid_25, -- [in std_logic]
Dbg_Clk_26 => Dbg_Clk_26, -- [out std_logic]
Dbg_TDI_26 => Dbg_TDI_26, -- [out std_logic]
Dbg_TDO_26 => Dbg_TDO_26, -- [in std_logic]
Dbg_Reg_En_26 => Dbg_Reg_En_26, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_26 => Dbg_Capture_26, -- [out std_logic]
Dbg_Shift_26 => Dbg_Shift_26, -- [out std_logic]
Dbg_Update_26 => Dbg_Update_26, -- [out std_logic]
Dbg_Rst_26 => Dbg_Rst_26, -- [out std_logic]
Dbg_Trig_In_26 => Dbg_Trig_In_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_26 => Dbg_Trig_Ack_In_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_26 => Dbg_Trig_Out_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_26 => Dbg_Trig_Ack_Out_26, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_26 => Dbg_TrClk_26, -- [out std_logic]
Dbg_TrData_26 => Dbg_TrData_26, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_26 => Dbg_TrReady_26, -- [out std_logic]
Dbg_TrValid_26 => Dbg_TrValid_26, -- [in std_logic]
Dbg_Clk_27 => Dbg_Clk_27, -- [out std_logic]
Dbg_TDI_27 => Dbg_TDI_27, -- [out std_logic]
Dbg_TDO_27 => Dbg_TDO_27, -- [in std_logic]
Dbg_Reg_En_27 => Dbg_Reg_En_27, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_27 => Dbg_Capture_27, -- [out std_logic]
Dbg_Shift_27 => Dbg_Shift_27, -- [out std_logic]
Dbg_Update_27 => Dbg_Update_27, -- [out std_logic]
Dbg_Rst_27 => Dbg_Rst_27, -- [out std_logic]
Dbg_Trig_In_27 => Dbg_Trig_In_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_27 => Dbg_Trig_Ack_In_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_27 => Dbg_Trig_Out_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_27 => Dbg_Trig_Ack_Out_27, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_27 => Dbg_TrClk_27, -- [out std_logic]
Dbg_TrData_27 => Dbg_TrData_27, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_27 => Dbg_TrReady_27, -- [out std_logic]
Dbg_TrValid_27 => Dbg_TrValid_27, -- [in std_logic]
Dbg_Clk_28 => Dbg_Clk_28, -- [out std_logic]
Dbg_TDI_28 => Dbg_TDI_28, -- [out std_logic]
Dbg_TDO_28 => Dbg_TDO_28, -- [in std_logic]
Dbg_Reg_En_28 => Dbg_Reg_En_28, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_28 => Dbg_Capture_28, -- [out std_logic]
Dbg_Shift_28 => Dbg_Shift_28, -- [out std_logic]
Dbg_Update_28 => Dbg_Update_28, -- [out std_logic]
Dbg_Rst_28 => Dbg_Rst_28, -- [out std_logic]
Dbg_Trig_In_28 => Dbg_Trig_In_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_28 => Dbg_Trig_Ack_In_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_28 => Dbg_Trig_Out_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_28 => Dbg_Trig_Ack_Out_28, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_28 => Dbg_TrClk_28, -- [out std_logic]
Dbg_TrData_28 => Dbg_TrData_28, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_28 => Dbg_TrReady_28, -- [out std_logic]
Dbg_TrValid_28 => Dbg_TrValid_28, -- [in std_logic]
Dbg_Clk_29 => Dbg_Clk_29, -- [out std_logic]
Dbg_TDI_29 => Dbg_TDI_29, -- [out std_logic]
Dbg_TDO_29 => Dbg_TDO_29, -- [in std_logic]
Dbg_Reg_En_29 => Dbg_Reg_En_29, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_29 => Dbg_Capture_29, -- [out std_logic]
Dbg_Shift_29 => Dbg_Shift_29, -- [out std_logic]
Dbg_Update_29 => Dbg_Update_29, -- [out std_logic]
Dbg_Rst_29 => Dbg_Rst_29, -- [out std_logic]
Dbg_Trig_In_29 => Dbg_Trig_In_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_29 => Dbg_Trig_Ack_In_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_29 => Dbg_Trig_Out_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_29 => Dbg_Trig_Ack_Out_29, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_29 => Dbg_TrClk_29, -- [out std_logic]
Dbg_TrData_29 => Dbg_TrData_29, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_29 => Dbg_TrReady_29, -- [out std_logic]
Dbg_TrValid_29 => Dbg_TrValid_29, -- [in std_logic]
Dbg_Clk_30 => Dbg_Clk_30, -- [out std_logic]
Dbg_TDI_30 => Dbg_TDI_30, -- [out std_logic]
Dbg_TDO_30 => Dbg_TDO_30, -- [in std_logic]
Dbg_Reg_En_30 => Dbg_Reg_En_30, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_30 => Dbg_Capture_30, -- [out std_logic]
Dbg_Shift_30 => Dbg_Shift_30, -- [out std_logic]
Dbg_Update_30 => Dbg_Update_30, -- [out std_logic]
Dbg_Rst_30 => Dbg_Rst_30, -- [out std_logic]
Dbg_Trig_In_30 => Dbg_Trig_In_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_30 => Dbg_Trig_Ack_In_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_30 => Dbg_Trig_Out_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_30 => Dbg_Trig_Ack_Out_30, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_30 => Dbg_TrClk_30, -- [out std_logic]
Dbg_TrData_30 => Dbg_TrData_30, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_30 => Dbg_TrReady_30, -- [out std_logic]
Dbg_TrValid_30 => Dbg_TrValid_30, -- [in std_logic]
Dbg_Clk_31 => Dbg_Clk_31, -- [out std_logic]
Dbg_TDI_31 => Dbg_TDI_31, -- [out std_logic]
Dbg_TDO_31 => Dbg_TDO_31, -- [in std_logic]
Dbg_Reg_En_31 => Dbg_Reg_En_31, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_31 => Dbg_Capture_31, -- [out std_logic]
Dbg_Shift_31 => Dbg_Shift_31, -- [out std_logic]
Dbg_Update_31 => Dbg_Update_31, -- [out std_logic]
Dbg_Rst_31 => Dbg_Rst_31, -- [out std_logic]
Dbg_Trig_In_31 => Dbg_Trig_In_31, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_31 => Dbg_Trig_Ack_In_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_31 => Dbg_Trig_Out_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_31 => Dbg_Trig_Ack_Out_31, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_31 => Dbg_TrClk_31, -- [out std_logic]
Dbg_TrData_31 => Dbg_TrData_31, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_31 => Dbg_TrReady_31, -- [out std_logic]
Dbg_TrValid_31 => Dbg_TrValid_31, -- [in std_logic]
Ext_Trig_In => ext_trig_in, -- [in std_logic_vector(0 to 3)]
Ext_Trig_Ack_In => ext_trig_ack_in, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Out => ext_trig_out, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Ack_Out => ext_trig_ack_out, -- [in std_logic_vector(0 to 3)]
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
ext_trig_in <= Trig_In_0 & Trig_In_1 & Trig_In_2 & Trig_In_3;
ext_trig_ack_out <= Trig_Ack_Out_0 & Trig_Ack_Out_1 & Trig_Ack_Out_2 & Trig_Ack_Out_3;
Trig_Ack_In_0 <= ext_trig_ack_in(0);
Trig_Ack_In_1 <= ext_trig_ack_in(1);
Trig_Ack_In_2 <= ext_trig_ack_in(2);
Trig_Ack_In_3 <= ext_trig_ack_in(3);
Trig_Out_0 <= ext_trig_out(0);
Trig_Out_1 <= ext_trig_out(1);
Trig_Out_2 <= ext_trig_out(2);
Trig_Out_3 <= ext_trig_out(3);
-- Bus Master port
Use_Bus_MASTER : if (C_DBG_MEM_ACCESS = 1) generate
type LMB_vec_type is array (natural range <>) of std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_addr : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_write : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_addr_strobe : std_logic;
signal lmb_read_strobe : std_logic;
signal lmb_write_strobe : std_logic;
signal lmb_ready : std_logic;
signal lmb_wait : std_logic;
signal lmb_ue : std_logic;
signal lmb_byte_enable : std_logic_vector(0 to C_DATA_SIZE / 8 - 1);
signal lmb_addr_strobe_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec : LMB_vec_type(0 to 31);
signal lmb_ready_vec : std_logic_vector(0 to 31);
signal lmb_wait_vec : std_logic_vector(0 to 31);
signal lmb_ue_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec_q : LMB_vec_type(0 to C_EN_WIDTH - 1);
signal lmb_ready_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_wait_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_ue_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => true,
C_HAS_DIRECT_PORT => C_TRACE_AXI_MASTER
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => lmb_data_addr,
LMB_Data_Read => lmb_data_read,
LMB_Data_Write => lmb_data_write,
LMB_Addr_Strobe => lmb_addr_strobe,
LMB_Read_Strobe => lmb_read_strobe,
LMB_Write_Strobe => lmb_write_strobe,
LMB_Ready => lmb_ready,
LMB_Wait => lmb_wait,
LMB_UE => lmb_ue,
LMB_Byte_Enable => lmb_byte_enable,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
Generate_LMB_Outputs : process (mb_debug_enabled, lmb_addr_strobe)
begin -- process Generate_LMB_Outputs
lmb_addr_strobe_vec <= (others => '0');
for I in 0 to C_EN_WIDTH - 1 loop
lmb_addr_strobe_vec(I) <= lmb_addr_strobe and mb_debug_enabled(I);
end loop;
end process Generate_LMB_Outputs;
LMB_Addr_Strobe_0 <= lmb_addr_strobe_vec(0);
LMB_Addr_Strobe_1 <= lmb_addr_strobe_vec(1);
LMB_Addr_Strobe_2 <= lmb_addr_strobe_vec(2);
LMB_Addr_Strobe_3 <= lmb_addr_strobe_vec(3);
LMB_Addr_Strobe_4 <= lmb_addr_strobe_vec(4);
LMB_Addr_Strobe_5 <= lmb_addr_strobe_vec(5);
LMB_Addr_Strobe_6 <= lmb_addr_strobe_vec(6);
LMB_Addr_Strobe_7 <= lmb_addr_strobe_vec(7);
LMB_Addr_Strobe_8 <= lmb_addr_strobe_vec(8);
LMB_Addr_Strobe_9 <= lmb_addr_strobe_vec(9);
LMB_Addr_Strobe_10 <= lmb_addr_strobe_vec(10);
LMB_Addr_Strobe_11 <= lmb_addr_strobe_vec(11);
LMB_Addr_Strobe_12 <= lmb_addr_strobe_vec(12);
LMB_Addr_Strobe_13 <= lmb_addr_strobe_vec(13);
LMB_Addr_Strobe_14 <= lmb_addr_strobe_vec(14);
LMB_Addr_Strobe_15 <= lmb_addr_strobe_vec(15);
LMB_Addr_Strobe_16 <= lmb_addr_strobe_vec(16);
LMB_Addr_Strobe_17 <= lmb_addr_strobe_vec(17);
LMB_Addr_Strobe_18 <= lmb_addr_strobe_vec(18);
LMB_Addr_Strobe_19 <= lmb_addr_strobe_vec(19);
LMB_Addr_Strobe_20 <= lmb_addr_strobe_vec(20);
LMB_Addr_Strobe_21 <= lmb_addr_strobe_vec(21);
LMB_Addr_Strobe_22 <= lmb_addr_strobe_vec(22);
LMB_Addr_Strobe_23 <= lmb_addr_strobe_vec(23);
LMB_Addr_Strobe_24 <= lmb_addr_strobe_vec(24);
LMB_Addr_Strobe_25 <= lmb_addr_strobe_vec(25);
LMB_Addr_Strobe_26 <= lmb_addr_strobe_vec(26);
LMB_Addr_Strobe_27 <= lmb_addr_strobe_vec(27);
LMB_Addr_Strobe_28 <= lmb_addr_strobe_vec(28);
LMB_Addr_Strobe_29 <= lmb_addr_strobe_vec(29);
LMB_Addr_Strobe_30 <= lmb_addr_strobe_vec(30);
LMB_Addr_Strobe_31 <= lmb_addr_strobe_vec(31);
LMB_Data_Addr_0 <= lmb_data_addr;
LMB_Data_Addr_1 <= lmb_data_addr;
LMB_Data_Addr_2 <= lmb_data_addr;
LMB_Data_Addr_3 <= lmb_data_addr;
LMB_Data_Addr_4 <= lmb_data_addr;
LMB_Data_Addr_5 <= lmb_data_addr;
LMB_Data_Addr_6 <= lmb_data_addr;
LMB_Data_Addr_7 <= lmb_data_addr;
LMB_Data_Addr_8 <= lmb_data_addr;
LMB_Data_Addr_9 <= lmb_data_addr;
LMB_Data_Addr_10 <= lmb_data_addr;
LMB_Data_Addr_11 <= lmb_data_addr;
LMB_Data_Addr_12 <= lmb_data_addr;
LMB_Data_Addr_13 <= lmb_data_addr;
LMB_Data_Addr_14 <= lmb_data_addr;
LMB_Data_Addr_15 <= lmb_data_addr;
LMB_Data_Addr_16 <= lmb_data_addr;
LMB_Data_Addr_17 <= lmb_data_addr;
LMB_Data_Addr_18 <= lmb_data_addr;
LMB_Data_Addr_19 <= lmb_data_addr;
LMB_Data_Addr_20 <= lmb_data_addr;
LMB_Data_Addr_21 <= lmb_data_addr;
LMB_Data_Addr_22 <= lmb_data_addr;
LMB_Data_Addr_23 <= lmb_data_addr;
LMB_Data_Addr_24 <= lmb_data_addr;
LMB_Data_Addr_25 <= lmb_data_addr;
LMB_Data_Addr_26 <= lmb_data_addr;
LMB_Data_Addr_27 <= lmb_data_addr;
LMB_Data_Addr_28 <= lmb_data_addr;
LMB_Data_Addr_29 <= lmb_data_addr;
LMB_Data_Addr_30 <= lmb_data_addr;
LMB_Data_Addr_31 <= lmb_data_addr;
LMB_Data_write_0 <= lmb_data_write;
LMB_Data_write_1 <= lmb_data_write;
LMB_Data_write_2 <= lmb_data_write;
LMB_Data_write_3 <= lmb_data_write;
LMB_Data_write_4 <= lmb_data_write;
LMB_Data_write_5 <= lmb_data_write;
LMB_Data_write_6 <= lmb_data_write;
LMB_Data_write_7 <= lmb_data_write;
LMB_Data_write_8 <= lmb_data_write;
LMB_Data_write_9 <= lmb_data_write;
LMB_Data_write_10 <= lmb_data_write;
LMB_Data_write_11 <= lmb_data_write;
LMB_Data_write_12 <= lmb_data_write;
LMB_Data_write_13 <= lmb_data_write;
LMB_Data_write_14 <= lmb_data_write;
LMB_Data_write_15 <= lmb_data_write;
LMB_Data_write_16 <= lmb_data_write;
LMB_Data_write_17 <= lmb_data_write;
LMB_Data_write_18 <= lmb_data_write;
LMB_Data_write_19 <= lmb_data_write;
LMB_Data_write_20 <= lmb_data_write;
LMB_Data_write_21 <= lmb_data_write;
LMB_Data_write_22 <= lmb_data_write;
LMB_Data_write_23 <= lmb_data_write;
LMB_Data_write_24 <= lmb_data_write;
LMB_Data_write_25 <= lmb_data_write;
LMB_Data_write_26 <= lmb_data_write;
LMB_Data_write_27 <= lmb_data_write;
LMB_Data_write_28 <= lmb_data_write;
LMB_Data_write_29 <= lmb_data_write;
LMB_Data_write_30 <= lmb_data_write;
LMB_Data_write_31 <= lmb_data_write;
LMB_Read_strobe_0 <= lmb_read_strobe;
LMB_Read_strobe_1 <= lmb_read_strobe;
LMB_Read_strobe_2 <= lmb_read_strobe;
LMB_Read_strobe_3 <= lmb_read_strobe;
LMB_Read_strobe_4 <= lmb_read_strobe;
LMB_Read_strobe_5 <= lmb_read_strobe;
LMB_Read_strobe_6 <= lmb_read_strobe;
LMB_Read_strobe_7 <= lmb_read_strobe;
LMB_Read_strobe_8 <= lmb_read_strobe;
LMB_Read_strobe_9 <= lmb_read_strobe;
LMB_Read_strobe_10 <= lmb_read_strobe;
LMB_Read_strobe_11 <= lmb_read_strobe;
LMB_Read_strobe_12 <= lmb_read_strobe;
LMB_Read_strobe_13 <= lmb_read_strobe;
LMB_Read_strobe_14 <= lmb_read_strobe;
LMB_Read_strobe_15 <= lmb_read_strobe;
LMB_Read_strobe_16 <= lmb_read_strobe;
LMB_Read_strobe_17 <= lmb_read_strobe;
LMB_Read_strobe_18 <= lmb_read_strobe;
LMB_Read_strobe_19 <= lmb_read_strobe;
LMB_Read_strobe_20 <= lmb_read_strobe;
LMB_Read_strobe_21 <= lmb_read_strobe;
LMB_Read_strobe_22 <= lmb_read_strobe;
LMB_Read_strobe_23 <= lmb_read_strobe;
LMB_Read_strobe_24 <= lmb_read_strobe;
LMB_Read_strobe_25 <= lmb_read_strobe;
LMB_Read_strobe_26 <= lmb_read_strobe;
LMB_Read_strobe_27 <= lmb_read_strobe;
LMB_Read_strobe_28 <= lmb_read_strobe;
LMB_Read_strobe_29 <= lmb_read_strobe;
LMB_Read_strobe_30 <= lmb_read_strobe;
LMB_Read_strobe_31 <= lmb_read_strobe;
LMB_Write_strobe_0 <= lmb_write_strobe;
LMB_Write_strobe_1 <= lmb_write_strobe;
LMB_Write_strobe_2 <= lmb_write_strobe;
LMB_Write_strobe_3 <= lmb_write_strobe;
LMB_Write_strobe_4 <= lmb_write_strobe;
LMB_Write_strobe_5 <= lmb_write_strobe;
LMB_Write_strobe_6 <= lmb_write_strobe;
LMB_Write_strobe_7 <= lmb_write_strobe;
LMB_Write_strobe_8 <= lmb_write_strobe;
LMB_Write_strobe_9 <= lmb_write_strobe;
LMB_Write_strobe_10 <= lmb_write_strobe;
LMB_Write_strobe_11 <= lmb_write_strobe;
LMB_Write_strobe_12 <= lmb_write_strobe;
LMB_Write_strobe_13 <= lmb_write_strobe;
LMB_Write_strobe_14 <= lmb_write_strobe;
LMB_Write_strobe_15 <= lmb_write_strobe;
LMB_Write_strobe_16 <= lmb_write_strobe;
LMB_Write_strobe_17 <= lmb_write_strobe;
LMB_Write_strobe_18 <= lmb_write_strobe;
LMB_Write_strobe_19 <= lmb_write_strobe;
LMB_Write_strobe_20 <= lmb_write_strobe;
LMB_Write_strobe_21 <= lmb_write_strobe;
LMB_Write_strobe_22 <= lmb_write_strobe;
LMB_Write_strobe_23 <= lmb_write_strobe;
LMB_Write_strobe_24 <= lmb_write_strobe;
LMB_Write_strobe_25 <= lmb_write_strobe;
LMB_Write_strobe_26 <= lmb_write_strobe;
LMB_Write_strobe_27 <= lmb_write_strobe;
LMB_Write_strobe_28 <= lmb_write_strobe;
LMB_Write_strobe_29 <= lmb_write_strobe;
LMB_Write_strobe_30 <= lmb_write_strobe;
LMB_Write_strobe_31 <= lmb_write_strobe;
LMB_Byte_enable_0 <= lmb_byte_enable;
LMB_Byte_enable_1 <= lmb_byte_enable;
LMB_Byte_enable_2 <= lmb_byte_enable;
LMB_Byte_enable_3 <= lmb_byte_enable;
LMB_Byte_enable_4 <= lmb_byte_enable;
LMB_Byte_enable_5 <= lmb_byte_enable;
LMB_Byte_enable_6 <= lmb_byte_enable;
LMB_Byte_enable_7 <= lmb_byte_enable;
LMB_Byte_enable_8 <= lmb_byte_enable;
LMB_Byte_enable_9 <= lmb_byte_enable;
LMB_Byte_enable_10 <= lmb_byte_enable;
LMB_Byte_enable_11 <= lmb_byte_enable;
LMB_Byte_enable_12 <= lmb_byte_enable;
LMB_Byte_enable_13 <= lmb_byte_enable;
LMB_Byte_enable_14 <= lmb_byte_enable;
LMB_Byte_enable_15 <= lmb_byte_enable;
LMB_Byte_enable_16 <= lmb_byte_enable;
LMB_Byte_enable_17 <= lmb_byte_enable;
LMB_Byte_enable_18 <= lmb_byte_enable;
LMB_Byte_enable_19 <= lmb_byte_enable;
LMB_Byte_enable_20 <= lmb_byte_enable;
LMB_Byte_enable_21 <= lmb_byte_enable;
LMB_Byte_enable_22 <= lmb_byte_enable;
LMB_Byte_enable_23 <= lmb_byte_enable;
LMB_Byte_enable_24 <= lmb_byte_enable;
LMB_Byte_enable_25 <= lmb_byte_enable;
LMB_Byte_enable_26 <= lmb_byte_enable;
LMB_Byte_enable_27 <= lmb_byte_enable;
LMB_Byte_enable_28 <= lmb_byte_enable;
LMB_Byte_enable_29 <= lmb_byte_enable;
LMB_Byte_enable_30 <= lmb_byte_enable;
LMB_Byte_enable_31 <= lmb_byte_enable;
Generate_LMB_Inputs : process (mb_debug_enabled, lmb_data_read_vec_q, lmb_ready_vec_q, lmb_wait_vec_q, lmb_ue_vec_q)
variable data_mask : std_logic_vector(0 to C_DATA_SIZE - 1);
variable data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
variable ready : std_logic;
variable wait_i : std_logic;
variable ue : std_logic;
begin -- process Generate_LMB_Inputs
data_read := (others => '0');
ready := '0';
wait_i := '0';
ue := '0';
for I in 0 to C_EN_WIDTH - 1 loop
data_mask := (0 to C_DATA_SIZE - 1 => mb_debug_enabled(I));
data_read := data_read or (lmb_data_read_vec_q(I) and data_mask);
ready := ready or (lmb_ready_vec_q(I) and mb_debug_enabled(I));
wait_i := wait_i or (lmb_wait_vec_q(I) and mb_debug_enabled(I));
ue := ue or (lmb_ue_vec_q(I) and mb_debug_enabled(I));
end loop;
lmb_data_read <= data_read;
lmb_ready <= ready;
lmb_wait <= wait_i;
lmb_ue <= ue;
end process Generate_LMB_Inputs;
Clock_LMB_Inputs : process (M_AXI_ACLK)
begin
if M_AXI_ACLK'event and M_AXI_ACLK = '1' then -- rising clock edge
for I in 0 to C_EN_WIDTH - 1 loop
lmb_data_read_vec_q(I) <= lmb_data_read_vec(I);
lmb_ready_vec_q(I) <= lmb_ready_vec(I);
lmb_wait_vec_q(I) <= lmb_wait_vec(I);
lmb_ue_vec_q(I) <= lmb_ue_vec(I);
end loop;
end if;
end process Clock_LMB_Inputs;
lmb_data_read_vec(0) <= LMB_Data_Read_0;
lmb_data_read_vec(1) <= LMB_Data_Read_1;
lmb_data_read_vec(2) <= LMB_Data_Read_2;
lmb_data_read_vec(3) <= LMB_Data_Read_3;
lmb_data_read_vec(4) <= LMB_Data_Read_4;
lmb_data_read_vec(5) <= LMB_Data_Read_5;
lmb_data_read_vec(6) <= LMB_Data_Read_6;
lmb_data_read_vec(7) <= LMB_Data_Read_7;
lmb_data_read_vec(8) <= LMB_Data_Read_8;
lmb_data_read_vec(9) <= LMB_Data_Read_9;
lmb_data_read_vec(10) <= LMB_Data_Read_10;
lmb_data_read_vec(11) <= LMB_Data_Read_11;
lmb_data_read_vec(12) <= LMB_Data_Read_12;
lmb_data_read_vec(13) <= LMB_Data_Read_13;
lmb_data_read_vec(14) <= LMB_Data_Read_14;
lmb_data_read_vec(15) <= LMB_Data_Read_15;
lmb_data_read_vec(16) <= LMB_Data_Read_16;
lmb_data_read_vec(17) <= LMB_Data_Read_17;
lmb_data_read_vec(18) <= LMB_Data_Read_18;
lmb_data_read_vec(19) <= LMB_Data_Read_19;
lmb_data_read_vec(20) <= LMB_Data_Read_20;
lmb_data_read_vec(21) <= LMB_Data_Read_21;
lmb_data_read_vec(22) <= LMB_Data_Read_22;
lmb_data_read_vec(23) <= LMB_Data_Read_23;
lmb_data_read_vec(24) <= LMB_Data_Read_24;
lmb_data_read_vec(25) <= LMB_Data_Read_25;
lmb_data_read_vec(26) <= LMB_Data_Read_26;
lmb_data_read_vec(27) <= LMB_Data_Read_27;
lmb_data_read_vec(28) <= LMB_Data_Read_28;
lmb_data_read_vec(29) <= LMB_Data_Read_29;
lmb_data_read_vec(30) <= LMB_Data_Read_30;
lmb_data_read_vec(31) <= LMB_Data_Read_31;
lmb_ready_vec(0) <= LMB_Ready_0;
lmb_ready_vec(1) <= LMB_Ready_1;
lmb_ready_vec(2) <= LMB_Ready_2;
lmb_ready_vec(3) <= LMB_Ready_3;
lmb_ready_vec(4) <= LMB_Ready_4;
lmb_ready_vec(5) <= LMB_Ready_5;
lmb_ready_vec(6) <= LMB_Ready_6;
lmb_ready_vec(7) <= LMB_Ready_7;
lmb_ready_vec(8) <= LMB_Ready_8;
lmb_ready_vec(9) <= LMB_Ready_9;
lmb_ready_vec(10) <= LMB_Ready_10;
lmb_ready_vec(11) <= LMB_Ready_11;
lmb_ready_vec(12) <= LMB_Ready_12;
lmb_ready_vec(13) <= LMB_Ready_13;
lmb_ready_vec(14) <= LMB_Ready_14;
lmb_ready_vec(15) <= LMB_Ready_15;
lmb_ready_vec(16) <= LMB_Ready_16;
lmb_ready_vec(17) <= LMB_Ready_17;
lmb_ready_vec(18) <= LMB_Ready_18;
lmb_ready_vec(19) <= LMB_Ready_19;
lmb_ready_vec(20) <= LMB_Ready_20;
lmb_ready_vec(21) <= LMB_Ready_21;
lmb_ready_vec(22) <= LMB_Ready_22;
lmb_ready_vec(23) <= LMB_Ready_23;
lmb_ready_vec(24) <= LMB_Ready_24;
lmb_ready_vec(25) <= LMB_Ready_25;
lmb_ready_vec(26) <= LMB_Ready_26;
lmb_ready_vec(27) <= LMB_Ready_27;
lmb_ready_vec(28) <= LMB_Ready_28;
lmb_ready_vec(29) <= LMB_Ready_29;
lmb_ready_vec(30) <= LMB_Ready_30;
lmb_ready_vec(31) <= LMB_Ready_31;
lmb_wait_vec(0) <= LMB_Wait_0;
lmb_wait_vec(1) <= LMB_Wait_1;
lmb_wait_vec(2) <= LMB_Wait_2;
lmb_wait_vec(3) <= LMB_Wait_3;
lmb_wait_vec(4) <= LMB_Wait_4;
lmb_wait_vec(5) <= LMB_Wait_5;
lmb_wait_vec(6) <= LMB_Wait_6;
lmb_wait_vec(7) <= LMB_Wait_7;
lmb_wait_vec(8) <= LMB_Wait_8;
lmb_wait_vec(9) <= LMB_Wait_9;
lmb_wait_vec(10) <= LMB_Wait_10;
lmb_wait_vec(11) <= LMB_Wait_11;
lmb_wait_vec(12) <= LMB_Wait_12;
lmb_wait_vec(13) <= LMB_Wait_13;
lmb_wait_vec(14) <= LMB_Wait_14;
lmb_wait_vec(15) <= LMB_Wait_15;
lmb_wait_vec(16) <= LMB_Wait_16;
lmb_wait_vec(17) <= LMB_Wait_17;
lmb_wait_vec(18) <= LMB_Wait_18;
lmb_wait_vec(19) <= LMB_Wait_19;
lmb_wait_vec(20) <= LMB_Wait_20;
lmb_wait_vec(21) <= LMB_Wait_21;
lmb_wait_vec(22) <= LMB_Wait_22;
lmb_wait_vec(23) <= LMB_Wait_23;
lmb_wait_vec(24) <= LMB_Wait_24;
lmb_wait_vec(25) <= LMB_Wait_25;
lmb_wait_vec(26) <= LMB_Wait_26;
lmb_wait_vec(27) <= LMB_Wait_27;
lmb_wait_vec(28) <= LMB_Wait_28;
lmb_wait_vec(29) <= LMB_Wait_29;
lmb_wait_vec(30) <= LMB_Wait_30;
lmb_wait_vec(31) <= LMB_Wait_31;
lmb_ue_vec(0) <= LMB_UE_0;
lmb_ue_vec(1) <= LMB_UE_1;
lmb_ue_vec(2) <= LMB_UE_2;
lmb_ue_vec(3) <= LMB_UE_3;
lmb_ue_vec(4) <= LMB_UE_4;
lmb_ue_vec(5) <= LMB_UE_5;
lmb_ue_vec(6) <= LMB_UE_6;
lmb_ue_vec(7) <= LMB_UE_7;
lmb_ue_vec(8) <= LMB_UE_8;
lmb_ue_vec(9) <= LMB_UE_9;
lmb_ue_vec(10) <= LMB_UE_10;
lmb_ue_vec(11) <= LMB_UE_11;
lmb_ue_vec(12) <= LMB_UE_12;
lmb_ue_vec(13) <= LMB_UE_13;
lmb_ue_vec(14) <= LMB_UE_14;
lmb_ue_vec(15) <= LMB_UE_15;
lmb_ue_vec(16) <= LMB_UE_16;
lmb_ue_vec(17) <= LMB_UE_17;
lmb_ue_vec(18) <= LMB_UE_18;
lmb_ue_vec(19) <= LMB_UE_19;
lmb_ue_vec(20) <= LMB_UE_20;
lmb_ue_vec(21) <= LMB_UE_21;
lmb_ue_vec(22) <= LMB_UE_22;
lmb_ue_vec(23) <= LMB_UE_23;
lmb_ue_vec(24) <= LMB_UE_24;
lmb_ue_vec(25) <= LMB_UE_25;
lmb_ue_vec(26) <= LMB_UE_26;
lmb_ue_vec(27) <= LMB_UE_27;
lmb_ue_vec(28) <= LMB_UE_28;
lmb_ue_vec(29) <= LMB_UE_29;
lmb_ue_vec(30) <= LMB_UE_30;
lmb_ue_vec(31) <= LMB_UE_31;
end generate Use_Bus_MASTER;
Use_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and C_TRACE_AXI_MASTER) generate
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => false,
C_HAS_DIRECT_PORT => true
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => open,
LMB_Data_Read => (others => '0'),
LMB_Data_Write => open,
LMB_Addr_Strobe => open,
LMB_Read_Strobe => open,
LMB_Write_Strobe => open,
LMB_Ready => '0',
LMB_Wait => '0',
LMB_UE => '0',
LMB_Byte_Enable => open,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
end generate Use_Bus_MASTER_AXI;
No_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and not C_TRACE_AXI_MASTER) generate
begin
master_rd_idle <= '1';
master_rd_resp <= "00";
master_wr_idle <= '1';
master_wr_resp <= "00";
master_data_out <= (others => '0');
master_data_exists <= '0';
master_data_empty <= '1';
master_dwr_next <= '0';
master_dwr_done <= '0';
master_dwr_resp <= (others => '0');
M_AXI_AWID <= (others => '0');
M_AXI_AWADDR <= (others => '0');
M_AXI_AWLEN <= (others => '0');
M_AXI_AWSIZE <= (others => '0');
M_AXI_AWBURST <= (others => '0');
M_AXI_AWLOCK <= '0';
M_AXI_AWCACHE <= (others => '0');
M_AXI_AWPROT <= (others => '0');
M_AXI_AWQOS <= (others => '0');
M_AXI_AWVALID <= '0';
M_AXI_WDATA <= (others => '0');
M_AXI_WSTRB <= (others => '0');
M_AXI_WLAST <= '0';
M_AXI_WVALID <= '0';
M_AXI_BREADY <= '0';
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= (others => '0');
M_AXI_ARBURST <= (others => '0');
M_AXI_ARLOCK <= '0';
M_AXI_ARCACHE <= (others => '0');
M_AXI_ARPROT <= (others => '0');
M_AXI_ARQOS <= (others => '0');
M_AXI_ARVALID <= '0';
M_AXI_RREADY <= '0';
end generate No_Bus_MASTER_AXI;
No_Bus_MASTER_LMB : if (C_DBG_MEM_ACCESS = 0) generate
begin
LMB_Data_Addr_0 <= (others => '0');
LMB_Data_Write_0 <= (others => '0');
LMB_Addr_Strobe_0 <= '0';
LMB_Read_Strobe_0 <= '0';
LMB_Write_Strobe_0 <= '0';
LMB_Byte_Enable_0 <= (others => '0');
LMB_Data_Addr_1 <= (others => '0');
LMB_Data_Write_1 <= (others => '0');
LMB_Addr_Strobe_1 <= '0';
LMB_Read_Strobe_1 <= '0';
LMB_Write_Strobe_1 <= '0';
LMB_Byte_Enable_1 <= (others => '0');
LMB_Data_Addr_2 <= (others => '0');
LMB_Data_Write_2 <= (others => '0');
LMB_Addr_Strobe_2 <= '0';
LMB_Read_Strobe_2 <= '0';
LMB_Write_Strobe_2 <= '0';
LMB_Byte_Enable_2 <= (others => '0');
LMB_Data_Addr_3 <= (others => '0');
LMB_Data_Write_3 <= (others => '0');
LMB_Addr_Strobe_3 <= '0';
LMB_Read_Strobe_3 <= '0';
LMB_Write_Strobe_3 <= '0';
LMB_Byte_Enable_3 <= (others => '0');
LMB_Data_Addr_4 <= (others => '0');
LMB_Data_Write_4 <= (others => '0');
LMB_Addr_Strobe_4 <= '0';
LMB_Read_Strobe_4 <= '0';
LMB_Write_Strobe_4 <= '0';
LMB_Byte_Enable_4 <= (others => '0');
LMB_Data_Addr_5 <= (others => '0');
LMB_Data_Write_5 <= (others => '0');
LMB_Addr_Strobe_5 <= '0';
LMB_Read_Strobe_5 <= '0';
LMB_Write_Strobe_5 <= '0';
LMB_Byte_Enable_5 <= (others => '0');
LMB_Data_Addr_6 <= (others => '0');
LMB_Data_Write_6 <= (others => '0');
LMB_Addr_Strobe_6 <= '0';
LMB_Read_Strobe_6 <= '0';
LMB_Write_Strobe_6 <= '0';
LMB_Byte_Enable_6 <= (others => '0');
LMB_Data_Addr_7 <= (others => '0');
LMB_Data_Write_7 <= (others => '0');
LMB_Addr_Strobe_7 <= '0';
LMB_Read_Strobe_7 <= '0';
LMB_Write_Strobe_7 <= '0';
LMB_Byte_Enable_7 <= (others => '0');
LMB_Data_Addr_8 <= (others => '0');
LMB_Data_Write_8 <= (others => '0');
LMB_Addr_Strobe_8 <= '0';
LMB_Read_Strobe_8 <= '0';
LMB_Write_Strobe_8 <= '0';
LMB_Byte_Enable_8 <= (others => '0');
LMB_Data_Addr_9 <= (others => '0');
LMB_Data_Write_9 <= (others => '0');
LMB_Addr_Strobe_9 <= '0';
LMB_Read_Strobe_9 <= '0';
LMB_Write_Strobe_9 <= '0';
LMB_Byte_Enable_9 <= (others => '0');
LMB_Data_Addr_10 <= (others => '0');
LMB_Data_Write_10 <= (others => '0');
LMB_Addr_Strobe_10 <= '0';
LMB_Read_Strobe_10 <= '0';
LMB_Write_Strobe_10 <= '0';
LMB_Byte_Enable_10 <= (others => '0');
LMB_Data_Addr_11 <= (others => '0');
LMB_Data_Write_11 <= (others => '0');
LMB_Addr_Strobe_11 <= '0';
LMB_Read_Strobe_11 <= '0';
LMB_Write_Strobe_11 <= '0';
LMB_Byte_Enable_11 <= (others => '0');
LMB_Data_Addr_12 <= (others => '0');
LMB_Data_Write_12 <= (others => '0');
LMB_Addr_Strobe_12 <= '0';
LMB_Read_Strobe_12 <= '0';
LMB_Write_Strobe_12 <= '0';
LMB_Byte_Enable_12 <= (others => '0');
LMB_Data_Addr_13 <= (others => '0');
LMB_Data_Write_13 <= (others => '0');
LMB_Addr_Strobe_13 <= '0';
LMB_Read_Strobe_13 <= '0';
LMB_Write_Strobe_13 <= '0';
LMB_Byte_Enable_13 <= (others => '0');
LMB_Data_Addr_14 <= (others => '0');
LMB_Data_Write_14 <= (others => '0');
LMB_Addr_Strobe_14 <= '0';
LMB_Read_Strobe_14 <= '0';
LMB_Write_Strobe_14 <= '0';
LMB_Byte_Enable_14 <= (others => '0');
LMB_Data_Addr_15 <= (others => '0');
LMB_Data_Write_15 <= (others => '0');
LMB_Addr_Strobe_15 <= '0';
LMB_Read_Strobe_15 <= '0';
LMB_Write_Strobe_15 <= '0';
LMB_Byte_Enable_15 <= (others => '0');
LMB_Data_Addr_16 <= (others => '0');
LMB_Data_Write_16 <= (others => '0');
LMB_Addr_Strobe_16 <= '0';
LMB_Read_Strobe_16 <= '0';
LMB_Write_Strobe_16 <= '0';
LMB_Byte_Enable_16 <= (others => '0');
LMB_Data_Addr_17 <= (others => '0');
LMB_Data_Write_17 <= (others => '0');
LMB_Addr_Strobe_17 <= '0';
LMB_Read_Strobe_17 <= '0';
LMB_Write_Strobe_17 <= '0';
LMB_Byte_Enable_17 <= (others => '0');
LMB_Data_Addr_18 <= (others => '0');
LMB_Data_Write_18 <= (others => '0');
LMB_Addr_Strobe_18 <= '0';
LMB_Read_Strobe_18 <= '0';
LMB_Write_Strobe_18 <= '0';
LMB_Byte_Enable_18 <= (others => '0');
LMB_Data_Addr_19 <= (others => '0');
LMB_Data_Write_19 <= (others => '0');
LMB_Addr_Strobe_19 <= '0';
LMB_Read_Strobe_19 <= '0';
LMB_Write_Strobe_19 <= '0';
LMB_Byte_Enable_19 <= (others => '0');
LMB_Data_Addr_20 <= (others => '0');
LMB_Data_Write_20 <= (others => '0');
LMB_Addr_Strobe_20 <= '0';
LMB_Read_Strobe_20 <= '0';
LMB_Write_Strobe_20 <= '0';
LMB_Byte_Enable_20 <= (others => '0');
LMB_Data_Addr_21 <= (others => '0');
LMB_Data_Write_21 <= (others => '0');
LMB_Addr_Strobe_21 <= '0';
LMB_Read_Strobe_21 <= '0';
LMB_Write_Strobe_21 <= '0';
LMB_Byte_Enable_21 <= (others => '0');
LMB_Data_Addr_22 <= (others => '0');
LMB_Data_Write_22 <= (others => '0');
LMB_Addr_Strobe_22 <= '0';
LMB_Read_Strobe_22 <= '0';
LMB_Write_Strobe_22 <= '0';
LMB_Byte_Enable_22 <= (others => '0');
LMB_Data_Addr_23 <= (others => '0');
LMB_Data_Write_23 <= (others => '0');
LMB_Addr_Strobe_23 <= '0';
LMB_Read_Strobe_23 <= '0';
LMB_Write_Strobe_23 <= '0';
LMB_Byte_Enable_23 <= (others => '0');
LMB_Data_Addr_24 <= (others => '0');
LMB_Data_Write_24 <= (others => '0');
LMB_Addr_Strobe_24 <= '0';
LMB_Read_Strobe_24 <= '0';
LMB_Write_Strobe_24 <= '0';
LMB_Byte_Enable_24 <= (others => '0');
LMB_Data_Addr_25 <= (others => '0');
LMB_Data_Write_25 <= (others => '0');
LMB_Addr_Strobe_25 <= '0';
LMB_Read_Strobe_25 <= '0';
LMB_Write_Strobe_25 <= '0';
LMB_Byte_Enable_25 <= (others => '0');
LMB_Data_Addr_26 <= (others => '0');
LMB_Data_Write_26 <= (others => '0');
LMB_Addr_Strobe_26 <= '0';
LMB_Read_Strobe_26 <= '0';
LMB_Write_Strobe_26 <= '0';
LMB_Byte_Enable_26 <= (others => '0');
LMB_Data_Addr_27 <= (others => '0');
LMB_Data_Write_27 <= (others => '0');
LMB_Addr_Strobe_27 <= '0';
LMB_Read_Strobe_27 <= '0';
LMB_Write_Strobe_27 <= '0';
LMB_Byte_Enable_27 <= (others => '0');
LMB_Data_Addr_28 <= (others => '0');
LMB_Data_Write_28 <= (others => '0');
LMB_Addr_Strobe_28 <= '0';
LMB_Read_Strobe_28 <= '0';
LMB_Write_Strobe_28 <= '0';
LMB_Byte_Enable_28 <= (others => '0');
LMB_Data_Addr_29 <= (others => '0');
LMB_Data_Write_29 <= (others => '0');
LMB_Addr_Strobe_29 <= '0';
LMB_Read_Strobe_29 <= '0';
LMB_Write_Strobe_29 <= '0';
LMB_Byte_Enable_29 <= (others => '0');
LMB_Data_Addr_30 <= (others => '0');
LMB_Data_Write_30 <= (others => '0');
LMB_Addr_Strobe_30 <= '0';
LMB_Read_Strobe_30 <= '0';
LMB_Write_Strobe_30 <= '0';
LMB_Byte_Enable_30 <= (others => '0');
LMB_Data_Addr_31 <= (others => '0');
LMB_Data_Write_31 <= (others => '0');
LMB_Addr_Strobe_31 <= '0';
LMB_Read_Strobe_31 <= '0';
LMB_Write_Strobe_31 <= '0';
LMB_Byte_Enable_31 <= (others => '0');
end generate No_Bus_MASTER_LMB;
Use_AXI_IPIF : if (C_USE_UART = 1) or (C_DBG_REG_ACCESS = 1) generate
begin
-- ip2bus_data assignment - as core may use less than 32 bits
ip2bus_data(C_S_AXI_DATA_WIDTH-1 downto C_REG_DATA_WIDTH) <= (others => '0');
---------------------------------------------------------------------------
-- AXI lite IPIF
---------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map (
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end generate Use_AXI_IPIF;
No_AXI_IPIF : if (C_USE_UART = 0) and (C_DBG_REG_ACCESS = 0) generate
begin
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
S_AXI_BRESP <= (others => '0');
S_AXI_BVALID <= '0';
S_AXI_ARREADY <= '0';
S_AXI_RDATA <= (others => '0');
S_AXI_RRESP <= (others => '0');
S_AXI_RVALID <= '0';
bus2ip_clk <= '0';
bus2ip_resetn <= '0';
bus2ip_data <= (others => '0');
bus2ip_rdce <= (others => '0');
bus2ip_wrce <= (others => '0');
bus2ip_cs <= (others => '0');
end generate No_AXI_IPIF;
end architecture IMP;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mdm_v3_2/fbb28dda/hdl/vhdl/mdm.vhd | 4 | 178472 | -------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
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-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2006-10-27 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2012-12-14 Removed legacy interfaces
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
-- stefana 2014-04-30 Added external trace support
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library mdm_v3_2;
use mdm_v3_2.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
entity MDM is
generic (
C_FAMILY : string := "virtex7";
C_JTAG_CHAIN : integer := 2;
C_USE_BSCAN : integer := 0;
C_USE_CONFIG_RESET : integer := 0;
C_INTERCONNECT : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_FFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"0000_0000";
C_MB_DBG_PORTS : integer := 1;
C_DBG_REG_ACCESS : integer := 0;
C_DBG_MEM_ACCESS : integer := 0;
C_USE_UART : integer := 1;
C_USE_CROSS_TRIGGER : integer := 0;
C_TRACE_OUTPUT : integer := 0;
C_TRACE_DATA_WIDTH : integer range 2 to 32 := 32;
C_TRACE_CLK_FREQ_HZ : integer := 200000000;
C_TRACE_CLK_OUT_PHASE : integer range 0 to 360 := 90;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_THREAD_ID_WIDTH : integer := 1;
C_DATA_SIZE : integer range 32 to 32 := 32;
C_M_AXIS_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXIS_ID_WIDTH : integer range 1 to 7 := 7
);
port (
-- Global signals
Config_Reset : in std_logic := '0';
Scan_Reset_Sel : in std_logic := '0';
Scan_Reset : in std_logic := '0';
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- External cross trigger signals
Trig_In_0 : in std_logic;
Trig_Ack_In_0 : out std_logic;
Trig_Out_0 : out std_logic;
Trig_Ack_Out_0 : in std_logic;
Trig_In_1 : in std_logic;
Trig_Ack_In_1 : out std_logic;
Trig_Out_1 : out std_logic;
Trig_Ack_Out_1 : in std_logic;
Trig_In_2 : in std_logic;
Trig_Ack_In_2 : out std_logic;
Trig_Out_2 : out std_logic;
Trig_Ack_Out_2 : in std_logic;
Trig_In_3 : in std_logic;
Trig_Ack_In_3 : out std_logic;
Trig_Out_3 : out std_logic;
Trig_Ack_Out_3 : in std_logic;
-- AXI slave signals
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Bus master signals
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
LMB_Data_Addr_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_0 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_0 : out std_logic;
LMB_Read_Strobe_0 : out std_logic;
LMB_Write_Strobe_0 : out std_logic;
LMB_Ready_0 : in std_logic;
LMB_Wait_0 : in std_logic;
LMB_CE_0 : in std_logic;
LMB_UE_0 : in std_logic;
LMB_Byte_Enable_0 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_1 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_1 : out std_logic;
LMB_Read_Strobe_1 : out std_logic;
LMB_Write_Strobe_1 : out std_logic;
LMB_Ready_1 : in std_logic;
LMB_Wait_1 : in std_logic;
LMB_CE_1 : in std_logic;
LMB_UE_1 : in std_logic;
LMB_Byte_Enable_1 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_2 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_2 : out std_logic;
LMB_Read_Strobe_2 : out std_logic;
LMB_Write_Strobe_2 : out std_logic;
LMB_Ready_2 : in std_logic;
LMB_Wait_2 : in std_logic;
LMB_CE_2 : in std_logic;
LMB_UE_2 : in std_logic;
LMB_Byte_Enable_2 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_3 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_3 : out std_logic;
LMB_Read_Strobe_3 : out std_logic;
LMB_Write_Strobe_3 : out std_logic;
LMB_Ready_3 : in std_logic;
LMB_Wait_3 : in std_logic;
LMB_CE_3 : in std_logic;
LMB_UE_3 : in std_logic;
LMB_Byte_Enable_3 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_4 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_4 : out std_logic;
LMB_Read_Strobe_4 : out std_logic;
LMB_Write_Strobe_4 : out std_logic;
LMB_Ready_4 : in std_logic;
LMB_Wait_4 : in std_logic;
LMB_CE_4 : in std_logic;
LMB_UE_4 : in std_logic;
LMB_Byte_Enable_4 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_5 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_5 : out std_logic;
LMB_Read_Strobe_5 : out std_logic;
LMB_Write_Strobe_5 : out std_logic;
LMB_Ready_5 : in std_logic;
LMB_Wait_5 : in std_logic;
LMB_CE_5 : in std_logic;
LMB_UE_5 : in std_logic;
LMB_Byte_Enable_5 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_6 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_6 : out std_logic;
LMB_Read_Strobe_6 : out std_logic;
LMB_Write_Strobe_6 : out std_logic;
LMB_Ready_6 : in std_logic;
LMB_Wait_6 : in std_logic;
LMB_CE_6 : in std_logic;
LMB_UE_6 : in std_logic;
LMB_Byte_Enable_6 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_7 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_7 : out std_logic;
LMB_Read_Strobe_7 : out std_logic;
LMB_Write_Strobe_7 : out std_logic;
LMB_Ready_7 : in std_logic;
LMB_Wait_7 : in std_logic;
LMB_CE_7 : in std_logic;
LMB_UE_7 : in std_logic;
LMB_Byte_Enable_7 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_8 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_8 : out std_logic;
LMB_Read_Strobe_8 : out std_logic;
LMB_Write_Strobe_8 : out std_logic;
LMB_Ready_8 : in std_logic;
LMB_Wait_8 : in std_logic;
LMB_CE_8 : in std_logic;
LMB_UE_8 : in std_logic;
LMB_Byte_Enable_8 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_9 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_9 : out std_logic;
LMB_Read_Strobe_9 : out std_logic;
LMB_Write_Strobe_9 : out std_logic;
LMB_Ready_9 : in std_logic;
LMB_Wait_9 : in std_logic;
LMB_CE_9 : in std_logic;
LMB_UE_9 : in std_logic;
LMB_Byte_Enable_9 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_10 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_10 : out std_logic;
LMB_Read_Strobe_10 : out std_logic;
LMB_Write_Strobe_10 : out std_logic;
LMB_Ready_10 : in std_logic;
LMB_Wait_10 : in std_logic;
LMB_CE_10 : in std_logic;
LMB_UE_10 : in std_logic;
LMB_Byte_Enable_10 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_11 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_11 : out std_logic;
LMB_Read_Strobe_11 : out std_logic;
LMB_Write_Strobe_11 : out std_logic;
LMB_Ready_11 : in std_logic;
LMB_Wait_11 : in std_logic;
LMB_CE_11 : in std_logic;
LMB_UE_11 : in std_logic;
LMB_Byte_Enable_11 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_12 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_12 : out std_logic;
LMB_Read_Strobe_12 : out std_logic;
LMB_Write_Strobe_12 : out std_logic;
LMB_Ready_12 : in std_logic;
LMB_Wait_12 : in std_logic;
LMB_CE_12 : in std_logic;
LMB_UE_12 : in std_logic;
LMB_Byte_Enable_12 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_13 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_13 : out std_logic;
LMB_Read_Strobe_13 : out std_logic;
LMB_Write_Strobe_13 : out std_logic;
LMB_Ready_13 : in std_logic;
LMB_Wait_13 : in std_logic;
LMB_CE_13 : in std_logic;
LMB_UE_13 : in std_logic;
LMB_Byte_Enable_13 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_14 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_14 : out std_logic;
LMB_Read_Strobe_14 : out std_logic;
LMB_Write_Strobe_14 : out std_logic;
LMB_Ready_14 : in std_logic;
LMB_Wait_14 : in std_logic;
LMB_CE_14 : in std_logic;
LMB_UE_14 : in std_logic;
LMB_Byte_Enable_14 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_15 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_15 : out std_logic;
LMB_Read_Strobe_15 : out std_logic;
LMB_Write_Strobe_15 : out std_logic;
LMB_Ready_15 : in std_logic;
LMB_Wait_15 : in std_logic;
LMB_CE_15 : in std_logic;
LMB_UE_15 : in std_logic;
LMB_Byte_Enable_15 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_16 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_16 : out std_logic;
LMB_Read_Strobe_16 : out std_logic;
LMB_Write_Strobe_16 : out std_logic;
LMB_Ready_16 : in std_logic;
LMB_Wait_16 : in std_logic;
LMB_CE_16 : in std_logic;
LMB_UE_16 : in std_logic;
LMB_Byte_Enable_16 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_17 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_17 : out std_logic;
LMB_Read_Strobe_17 : out std_logic;
LMB_Write_Strobe_17 : out std_logic;
LMB_Ready_17 : in std_logic;
LMB_Wait_17 : in std_logic;
LMB_CE_17 : in std_logic;
LMB_UE_17 : in std_logic;
LMB_Byte_Enable_17 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_18 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_18 : out std_logic;
LMB_Read_Strobe_18 : out std_logic;
LMB_Write_Strobe_18 : out std_logic;
LMB_Ready_18 : in std_logic;
LMB_Wait_18 : in std_logic;
LMB_CE_18 : in std_logic;
LMB_UE_18 : in std_logic;
LMB_Byte_Enable_18 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_19 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_19 : out std_logic;
LMB_Read_Strobe_19 : out std_logic;
LMB_Write_Strobe_19 : out std_logic;
LMB_Ready_19 : in std_logic;
LMB_Wait_19 : in std_logic;
LMB_CE_19 : in std_logic;
LMB_UE_19 : in std_logic;
LMB_Byte_Enable_19 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_20 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_20 : out std_logic;
LMB_Read_Strobe_20 : out std_logic;
LMB_Write_Strobe_20 : out std_logic;
LMB_Ready_20 : in std_logic;
LMB_Wait_20 : in std_logic;
LMB_CE_20 : in std_logic;
LMB_UE_20 : in std_logic;
LMB_Byte_Enable_20 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_21 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_21 : out std_logic;
LMB_Read_Strobe_21 : out std_logic;
LMB_Write_Strobe_21 : out std_logic;
LMB_Ready_21 : in std_logic;
LMB_Wait_21 : in std_logic;
LMB_CE_21 : in std_logic;
LMB_UE_21 : in std_logic;
LMB_Byte_Enable_21 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_22 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_22 : out std_logic;
LMB_Read_Strobe_22 : out std_logic;
LMB_Write_Strobe_22 : out std_logic;
LMB_Ready_22 : in std_logic;
LMB_Wait_22 : in std_logic;
LMB_CE_22 : in std_logic;
LMB_UE_22 : in std_logic;
LMB_Byte_Enable_22 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_23 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_23 : out std_logic;
LMB_Read_Strobe_23 : out std_logic;
LMB_Write_Strobe_23 : out std_logic;
LMB_Ready_23 : in std_logic;
LMB_Wait_23 : in std_logic;
LMB_CE_23 : in std_logic;
LMB_UE_23 : in std_logic;
LMB_Byte_Enable_23 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_24 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_24 : out std_logic;
LMB_Read_Strobe_24 : out std_logic;
LMB_Write_Strobe_24 : out std_logic;
LMB_Ready_24 : in std_logic;
LMB_Wait_24 : in std_logic;
LMB_CE_24 : in std_logic;
LMB_UE_24 : in std_logic;
LMB_Byte_Enable_24 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_25 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_25 : out std_logic;
LMB_Read_Strobe_25 : out std_logic;
LMB_Write_Strobe_25 : out std_logic;
LMB_Ready_25 : in std_logic;
LMB_Wait_25 : in std_logic;
LMB_CE_25 : in std_logic;
LMB_UE_25 : in std_logic;
LMB_Byte_Enable_25 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_26 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_26 : out std_logic;
LMB_Read_Strobe_26 : out std_logic;
LMB_Write_Strobe_26 : out std_logic;
LMB_Ready_26 : in std_logic;
LMB_Wait_26 : in std_logic;
LMB_CE_26 : in std_logic;
LMB_UE_26 : in std_logic;
LMB_Byte_Enable_26 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_27 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_27 : out std_logic;
LMB_Read_Strobe_27 : out std_logic;
LMB_Write_Strobe_27 : out std_logic;
LMB_Ready_27 : in std_logic;
LMB_Wait_27 : in std_logic;
LMB_CE_27 : in std_logic;
LMB_UE_27 : in std_logic;
LMB_Byte_Enable_27 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_28 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_28 : out std_logic;
LMB_Read_Strobe_28 : out std_logic;
LMB_Write_Strobe_28 : out std_logic;
LMB_Ready_28 : in std_logic;
LMB_Wait_28 : in std_logic;
LMB_CE_28 : in std_logic;
LMB_UE_28 : in std_logic;
LMB_Byte_Enable_28 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_29 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_29 : out std_logic;
LMB_Read_Strobe_29 : out std_logic;
LMB_Write_Strobe_29 : out std_logic;
LMB_Ready_29 : in std_logic;
LMB_Wait_29 : in std_logic;
LMB_CE_29 : in std_logic;
LMB_UE_29 : in std_logic;
LMB_Byte_Enable_29 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_30 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_30 : out std_logic;
LMB_Read_Strobe_30 : out std_logic;
LMB_Write_Strobe_30 : out std_logic;
LMB_Ready_30 : in std_logic;
LMB_Wait_30 : in std_logic;
LMB_CE_30 : in std_logic;
LMB_UE_30 : in std_logic;
LMB_Byte_Enable_30 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_31 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_31 : out std_logic;
LMB_Read_Strobe_31 : out std_logic;
LMB_Write_Strobe_31 : out std_logic;
LMB_Ready_31 : in std_logic;
LMB_Wait_31 : in std_logic;
LMB_CE_31 : in std_logic;
LMB_UE_31 : in std_logic;
LMB_Byte_Enable_31 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External BSCAN inputs
-- These signals are used when C_USE_BSCAN = 2 (EXTERNAL)
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
-- External JTAG ports
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end entity MDM;
architecture IMP of MDM is
function int2std (val : integer) return std_logic is
begin -- function int2std
if (val = 0) then
return '0';
else
return '1';
end if;
end function int2std;
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0) := X"00000000";
constant C_REG_NUM_CE : integer := 4 + 4 * C_DBG_REG_ACCESS;
constant C_REG_DATA_WIDTH : integer := 8 + 24 * C_DBG_REG_ACCESS;
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) :=
(31 downto 5 => '0', 4 => int2std(C_DBG_REG_ACCESS), 3 downto 0 => '1');
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := (
-- Registers Base Address (not used)
ZEROES & C_BASEADDR,
ZEROES & (C_BASEADDR or C_S_AXI_MIN_SIZE)
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (
0 => C_REG_NUM_CE
);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
constant C_TRACE_AXI_MASTER : boolean := C_TRACE_OUTPUT = 3;
--------------------------------------------------------------------------
-- Component declarations
--------------------------------------------------------------------------
component MDM_Core
generic (
C_JTAG_CHAIN : integer;
C_USE_BSCAN : integer;
C_USE_CONFIG_RESET : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MB_DBG_PORTS : integer;
C_EN_WIDTH : integer;
C_DBG_REG_ACCESS : integer;
C_REG_NUM_CE : integer;
C_REG_DATA_WIDTH : integer;
C_DBG_MEM_ACCESS : integer;
C_S_AXI_ACLK_FREQ_HZ : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8;
C_TRACE_OUTPUT : integer;
C_TRACE_DATA_WIDTH : integer;
C_TRACE_CLK_FREQ_HZ : integer;
C_TRACE_CLK_OUT_PHASE : integer;
C_M_AXIS_DATA_WIDTH : integer;
C_M_AXIS_ID_WIDTH : integer);
port (
-- Global signals
Config_Reset : in std_logic;
Scan_Reset_Sel : in std_logic;
Scan_Reset : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- Debug Register Access signals
DbgReg_DRCK : out std_logic;
DbgReg_UPDATE : out std_logic;
DbgReg_Select : out std_logic;
JTAG_Busy : in std_logic;
-- AXI IPIC signals
bus2ip_clk : in std_logic;
bus2ip_resetn : in std_logic;
bus2ip_data : in std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
bus2ip_rdce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_wrce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
ip2bus_data : out std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
-- Bus Master signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
Master_dwr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_dwr_len : out std_logic_vector(4 downto 0);
Master_dwr_data : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_dwr_start : out std_logic;
Master_dwr_next : in std_logic;
Master_dwr_done : in std_logic;
Master_dwr_resp : in std_logic_vector(1 downto 0);
-- JTAG signals
JTAG_TDI : in std_logic;
JTAG_RESET : in std_logic;
UPDATE : in std_logic;
JTAG_SHIFT : in std_logic;
JTAG_CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
JTAG_TDO : out std_logic;
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External Trigger Signals
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- External JTAG
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component MDM_Core;
component bus_master is
generic (
C_M_AXI_DATA_WIDTH : natural;
C_M_AXI_THREAD_ID_WIDTH : natural;
C_M_AXI_ADDR_WIDTH : natural;
C_DATA_SIZE : natural;
C_HAS_FIFO_PORTS : boolean;
C_HAS_DIRECT_PORT : boolean
);
port (
Rd_Start : in std_logic;
Rd_Addr : in std_logic_vector(31 downto 0);
Rd_Len : in std_logic_vector(4 downto 0);
Rd_Size : in std_logic_vector(1 downto 0);
Rd_Exclusive : in std_logic;
Rd_Idle : out std_logic;
Rd_Response : out std_logic_vector(1 downto 0);
Wr_Start : in std_logic;
Wr_Addr : in std_logic_vector(31 downto 0);
Wr_Len : in std_logic_vector(4 downto 0);
Wr_Size : in std_logic_vector(1 downto 0);
Wr_Exclusive : in std_logic;
Wr_Idle : out std_logic;
Wr_Response : out std_logic_vector(1 downto 0);
Data_Rd : in std_logic;
Data_Out : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Exists : out std_logic;
Data_Wr : in std_logic;
Data_In : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Empty : out std_logic;
Direct_Wr_Addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Direct_Wr_Len : in std_logic_vector(4 downto 0);
Direct_Wr_Data : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Direct_Wr_Start : in std_logic;
Direct_Wr_Next : out std_logic;
Direct_Wr_Done : out std_logic;
Direct_Wr_Resp : out std_logic_vector(1 downto 0);
LMB_Data_Addr : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe : out std_logic;
LMB_Read_Strobe : out std_logic;
LMB_Write_Strobe : out std_logic;
LMB_Ready : in std_logic;
LMB_Wait : in std_logic;
LMB_UE : in std_logic;
LMB_Byte_Enable : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WLAST : out std_logic;
M_AXI_WDATA : out std_logic_vector(31 downto 0);
M_AXI_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(31 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end component bus_master;
--------------------------------------------------------------------------
-- Functions
--------------------------------------------------------------------------
-- Returns at least 1
function MakePos (a : integer) return integer is
begin
if a < 1 then
return 1;
else
return a;
end if;
end function MakePos;
constant C_EN_WIDTH : integer := MakePos(C_MB_DBG_PORTS);
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal tdi : std_logic;
signal reset : std_logic;
signal update : std_logic;
signal capture : std_logic;
signal shift : std_logic;
signal sel : std_logic;
signal drck : std_logic;
signal tdo : std_logic;
signal drck_i : std_logic;
signal update_i : std_logic;
signal dbgreg_drck : std_logic;
signal dbgreg_update : std_logic;
signal dbgreg_select : std_logic;
signal jtag_busy : std_logic;
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
signal bus2ip_cs : std_logic_vector(((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal mb_debug_enabled : std_logic_vector(C_EN_WIDTH-1 downto 0);
signal master_rd_start : std_logic;
signal master_rd_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_rd_len : std_logic_vector(4 downto 0);
signal master_rd_size : std_logic_vector(1 downto 0);
signal master_rd_excl : std_logic;
signal master_rd_idle : std_logic;
signal master_rd_resp : std_logic_vector(1 downto 0);
signal master_wr_start : std_logic;
signal master_wr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_wr_len : std_logic_vector(4 downto 0);
signal master_wr_size : std_logic_vector(1 downto 0);
signal master_wr_excl : std_logic;
signal master_wr_idle : std_logic;
signal master_wr_resp : std_logic_vector(1 downto 0);
signal master_data_rd : std_logic;
signal master_data_out : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_exists : std_logic;
signal master_data_wr : std_logic;
signal master_data_in : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_empty : std_logic;
signal master_dwr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_dwr_len : std_logic_vector(4 downto 0);
signal master_dwr_data : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_dwr_start : std_logic;
signal master_dwr_next : std_logic;
signal master_dwr_done : std_logic;
signal master_dwr_resp : std_logic_vector(1 downto 0);
signal ext_trig_in : std_logic_vector(0 to 3);
signal ext_trig_Ack_In : std_logic_vector(0 to 3);
signal ext_trig_out : std_logic_vector(0 to 3);
signal ext_trig_Ack_Out : std_logic_vector(0 to 3);
--------------------------------------------------------------------------
-- Attibute declarations
--------------------------------------------------------------------------
attribute period : string;
attribute period of update : signal is "200 ns";
attribute buffer_type : string;
attribute buffer_type of update_i : signal is "none";
attribute buffer_type of MDM_Core_I1 : label is "none";
begin -- architecture IMP
Use_E2 : if C_USE_BSCAN /= 2 generate
begin
BSCANE2_I : BSCANE2
generic map (
DISABLE_JTAG => "FALSE",
JTAG_CHAIN => C_JTAG_CHAIN)
port map (
CAPTURE => capture, -- [out std_logic]
DRCK => drck_i, -- [out std_logic]
RESET => reset, -- [out std_logic]
RUNTEST => open, -- [out std_logic]
SEL => sel, -- [out std_logic]
SHIFT => shift, -- [out std_logic]
TCK => open, -- [out std_logic]
TDI => tdi, -- [out std_logic]
TMS => open, -- [out std_logic]
UPDATE => update_i, -- [out std_logic]
TDO => tdo); -- [in std_logic]
end generate Use_E2;
Use_External : if C_USE_BSCAN = 2 generate
begin
capture <= bscan_ext_capture;
drck_i <= bscan_ext_drck;
reset <= bscan_ext_reset;
sel <= bscan_ext_sel;
shift <= bscan_ext_shift;
tdi <= bscan_ext_tdi;
update_i <= bscan_ext_update;
bscan_ext_tdo <= tdo;
end generate Use_External;
No_External : if C_USE_BSCAN /= 2 generate
begin
bscan_ext_tdo <= '0';
end generate No_External;
Use_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 1 generate
signal dbgreg_select_n : std_logic;
signal dbgreg_drck_i : std_logic;
signal dbgreg_update_i : std_logic;
signal update_set : std_logic;
signal update_reset : std_logic;
begin
dbgreg_select_n <= not dbgreg_select;
-- drck <= dbgreg_drck when dbgreg_select = '1' else drck_i;
BUFG_DRCK : BUFG
port map (
O => dbgreg_drck_i,
I => dbgreg_drck
);
BUFGCTRL_DRCK : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => drck,
CE0 => '1',
CE1 => '1',
I0 => drck_i,
I1 => dbgreg_drck_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
-- update <= dbgreg_update when dbgreg_select = '1' else update_i;
BUFG_UPDATE : BUFG
port map (
O => dbgreg_update_i,
I => dbgreg_update
);
BUFGCTRL_UPDATE : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => update,
CE0 => '1',
CE1 => '1',
I0 => update_i,
I1 => dbgreg_update_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
JTAG_Busy_Detect : process (drck_i, sel, update_set, Config_Reset)
begin
if sel = '0' or update_set = '1' or Config_Reset = '1' then
jtag_busy <= '0';
update_reset <= '1';
elsif drck_i'event and drck_i = '1' then
if sel = '1' and capture = '1' then
jtag_busy <= '1';
end if;
update_reset <= '0';
end if;
end process JTAG_Busy_Detect;
JTAG_Update_Detect : process (update_i, update_reset, Config_Reset)
begin
if update_reset = '1' or Config_Reset = '1' then
update_set <= '0';
elsif update_i'event and update_i = '1' then
update_set <= '1';
end if;
end process JTAG_Update_Detect;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 0 generate
begin
BUFG_DRCK : BUFG
port map (
O => drck,
I => drck_i
);
update <= update_i;
jtag_busy <= '0';
end generate No_Dbg_Reg_Access;
---------------------------------------------------------------------------
-- MDM core
---------------------------------------------------------------------------
MDM_Core_I1 : MDM_Core
generic map (
C_JTAG_CHAIN => C_JTAG_CHAIN, -- [integer]
C_USE_BSCAN => C_USE_BSCAN, -- [integer]
C_USE_CONFIG_RESET => C_USE_CONFIG_RESET, -- [integer = 0]
C_BASEADDR => C_BASEADDR, -- [std_logic_vector(0 to 31)]
C_HIGHADDR => C_HIGHADDR, -- [std_logic_vector(0 to 31)]
C_MB_DBG_PORTS => C_MB_DBG_PORTS, -- [integer]
C_EN_WIDTH => C_EN_WIDTH, -- [integer]
C_DBG_REG_ACCESS => C_DBG_REG_ACCESS, -- [integer]
C_REG_NUM_CE => C_REG_NUM_CE, -- [integer]
C_REG_DATA_WIDTH => C_REG_DATA_WIDTH, -- [integer]
C_DBG_MEM_ACCESS => C_DBG_MEM_ACCESS, -- [integer]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ, -- [integer]
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH, -- [integer]
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH, -- [integer]
C_USE_CROSS_TRIGGER => C_USE_CROSS_TRIGGER, -- [integer]
C_USE_UART => C_USE_UART, -- [integer]
C_UART_WIDTH => 8, -- [integer]
C_TRACE_OUTPUT => C_TRACE_OUTPUT, -- [integer]
C_TRACE_DATA_WIDTH => C_TRACE_DATA_WIDTH, -- [integer]
C_TRACE_CLK_FREQ_HZ => C_TRACE_CLK_FREQ_HZ, -- [integer]
C_TRACE_CLK_OUT_PHASE => C_TRACE_CLK_OUT_PHASE, -- [integer]
C_M_AXIS_DATA_WIDTH => C_M_AXIS_DATA_WIDTH, -- [integer]
C_M_AXIS_ID_WIDTH => C_M_AXIS_ID_WIDTH -- [integer]
)
port map (
-- Global signals
Config_Reset => Config_Reset, -- [in std_logic]
Scan_Reset_Sel => Scan_Reset_Sel, -- [in std_logic]
Scan_Reset => Scan_Reset, -- [in std_logic]
M_AXIS_ACLK => M_AXIS_ACLK, -- [in std_logic]
M_AXIS_ARESETN => M_AXIS_ARESETN, -- [in std_logic]
Interrupt => Interrupt, -- [out std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst, -- [out std_logic]
-- Debug Register Access signals
DbgReg_DRCK => dbgreg_drck, -- [out std_logic]
DbgReg_UPDATE => dbgreg_update, -- [out std_logic]
DbgReg_Select => dbgreg_select, -- [out std_logic]
JTAG_Busy => jtag_busy, -- [in std_logic]
-- AXI IPIC signals
bus2ip_clk => bus2ip_clk,
bus2ip_resetn => bus2ip_resetn,
bus2ip_data => bus2ip_data(C_REG_DATA_WIDTH-1 downto 0),
bus2ip_rdce => bus2ip_rdce(C_REG_NUM_CE-1 downto 0),
bus2ip_wrce => bus2ip_wrce(C_REG_NUM_CE-1 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
ip2bus_data => ip2bus_data(C_REG_DATA_WIDTH-1 downto 0),
-- Bus Master signals
MB_Debug_Enabled => mb_debug_enabled,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
Master_rd_start => master_rd_start,
Master_rd_addr => master_rd_addr,
Master_rd_len => master_rd_len,
Master_rd_size => master_rd_size,
Master_rd_excl => master_rd_excl,
Master_rd_idle => master_rd_idle,
Master_rd_resp => master_rd_resp,
Master_wr_start => master_wr_start,
Master_wr_addr => master_wr_addr,
Master_wr_len => master_wr_len,
Master_wr_size => master_wr_size,
Master_wr_excl => master_wr_excl,
Master_wr_idle => master_wr_idle,
Master_wr_resp => master_wr_resp,
Master_data_rd => master_data_rd,
Master_data_out => master_data_out,
Master_data_exists => master_data_exists,
Master_data_wr => master_data_wr,
Master_data_in => master_data_in,
Master_data_empty => master_data_empty,
Master_dwr_addr => master_dwr_addr,
Master_dwr_len => master_dwr_len,
Master_dwr_data => master_dwr_data,
Master_dwr_start => master_dwr_start,
Master_dwr_next => master_dwr_next,
Master_dwr_done => master_dwr_done,
Master_dwr_resp => master_dwr_resp,
-- JTAG signals
JTAG_TDI => tdi, -- [in std_logic]
JTAG_RESET => reset, -- [in std_logic]
UPDATE => update, -- [in std_logic]
JTAG_SHIFT => shift, -- [in std_logic]
JTAG_CAPTURE => capture, -- [in std_logic]
SEL => sel, -- [in std_logic]
DRCK => drck, -- [in std_logic]
JTAG_TDO => tdo, -- [out std_logic]
-- External Trace AXI Stream output
M_AXIS_TDATA => M_AXIS_TDATA, -- [out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0)]
M_AXIS_TID => M_AXIS_TID, -- [out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0)]
M_AXIS_TREADY => M_AXIS_TREADY, -- [in std_logic]
M_AXIS_TVALID => M_AXIS_TVALID, -- [out std_logic]
-- External Trace output
TRACE_CLK_OUT => TRACE_CLK_OUT, -- [out std_logic]
TRACE_CLK => TRACE_CLK, -- [in std_logic]
TRACE_CTL => TRACE_CTL, -- [out std_logic]
TRACE_DATA => TRACE_DATA, -- [out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0)]
-- MicroBlaze Debug Signals
Dbg_Clk_0 => Dbg_Clk_0, -- [out std_logic]
Dbg_TDI_0 => Dbg_TDI_0, -- [out std_logic]
Dbg_TDO_0 => Dbg_TDO_0, -- [in std_logic]
Dbg_Reg_En_0 => Dbg_Reg_En_0, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_0 => Dbg_Capture_0, -- [out std_logic]
Dbg_Shift_0 => Dbg_Shift_0, -- [out std_logic]
Dbg_Update_0 => Dbg_Update_0, -- [out std_logic]
Dbg_Rst_0 => Dbg_Rst_0, -- [out std_logic]
Dbg_Trig_In_0 => Dbg_Trig_In_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_0 => Dbg_Trig_Ack_In_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_0 => Dbg_Trig_Out_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_0 => Dbg_Trig_Ack_Out_0, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_0 => Dbg_TrClk_0, -- [out std_logic]
Dbg_TrData_0 => Dbg_TrData_0, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_0 => Dbg_TrReady_0, -- [out std_logic]
Dbg_TrValid_0 => Dbg_TrValid_0, -- [in std_logic]
Dbg_Clk_1 => Dbg_Clk_1, -- [out std_logic]
Dbg_TDI_1 => Dbg_TDI_1, -- [out std_logic]
Dbg_TDO_1 => Dbg_TDO_1, -- [in std_logic]
Dbg_Reg_En_1 => Dbg_Reg_En_1, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_1 => Dbg_Capture_1, -- [out std_logic]
Dbg_Shift_1 => Dbg_Shift_1, -- [out std_logic]
Dbg_Update_1 => Dbg_Update_1, -- [out std_logic]
Dbg_Rst_1 => Dbg_Rst_1, -- [out std_logic]
Dbg_Trig_In_1 => Dbg_Trig_In_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_1 => Dbg_Trig_Ack_In_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_1 => Dbg_Trig_Out_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_1 => Dbg_Trig_Ack_Out_1, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_1 => Dbg_TrClk_1, -- [out std_logic]
Dbg_TrData_1 => Dbg_TrData_1, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_1 => Dbg_TrReady_1, -- [out std_logic]
Dbg_TrValid_1 => Dbg_TrValid_1, -- [in std_logic]
Dbg_Clk_2 => Dbg_Clk_2, -- [out std_logic]
Dbg_TDI_2 => Dbg_TDI_2, -- [out std_logic]
Dbg_TDO_2 => Dbg_TDO_2, -- [in std_logic]
Dbg_Reg_En_2 => Dbg_Reg_En_2, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_2 => Dbg_Capture_2, -- [out std_logic]
Dbg_Shift_2 => Dbg_Shift_2, -- [out std_logic]
Dbg_Update_2 => Dbg_Update_2, -- [out std_logic]
Dbg_Rst_2 => Dbg_Rst_2, -- [out std_logic]
Dbg_Trig_In_2 => Dbg_Trig_In_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_2 => Dbg_Trig_Ack_In_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_2 => Dbg_Trig_Out_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_2 => Dbg_Trig_Ack_Out_2, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_2 => Dbg_TrClk_2, -- [out std_logic]
Dbg_TrData_2 => Dbg_TrData_2, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_2 => Dbg_TrReady_2, -- [out std_logic]
Dbg_TrValid_2 => Dbg_TrValid_2, -- [in std_logic]
Dbg_Clk_3 => Dbg_Clk_3, -- [out std_logic]
Dbg_TDI_3 => Dbg_TDI_3, -- [out std_logic]
Dbg_TDO_3 => Dbg_TDO_3, -- [in std_logic]
Dbg_Reg_En_3 => Dbg_Reg_En_3, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_3 => Dbg_Capture_3, -- [out std_logic]
Dbg_Shift_3 => Dbg_Shift_3, -- [out std_logic]
Dbg_Update_3 => Dbg_Update_3, -- [out std_logic]
Dbg_Rst_3 => Dbg_Rst_3, -- [out std_logic]
Dbg_Trig_In_3 => Dbg_Trig_In_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_3 => Dbg_Trig_Ack_In_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_3 => Dbg_Trig_Out_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_3 => Dbg_Trig_Ack_Out_3, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_3 => Dbg_TrClk_3, -- [out std_logic]
Dbg_TrData_3 => Dbg_TrData_3, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_3 => Dbg_TrReady_3, -- [out std_logic]
Dbg_TrValid_3 => Dbg_TrValid_3, -- [in std_logic]
Dbg_Clk_4 => Dbg_Clk_4, -- [out std_logic]
Dbg_TDI_4 => Dbg_TDI_4, -- [out std_logic]
Dbg_TDO_4 => Dbg_TDO_4, -- [in std_logic]
Dbg_Reg_En_4 => Dbg_Reg_En_4, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_4 => Dbg_Capture_4, -- [out std_logic]
Dbg_Shift_4 => Dbg_Shift_4, -- [out std_logic]
Dbg_Update_4 => Dbg_Update_4, -- [out std_logic]
Dbg_Rst_4 => Dbg_Rst_4, -- [out std_logic]
Dbg_Trig_In_4 => Dbg_Trig_In_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_4 => Dbg_Trig_Ack_In_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_4 => Dbg_Trig_Out_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_4 => Dbg_Trig_Ack_Out_4, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_4 => Dbg_TrClk_4, -- [out std_logic]
Dbg_TrData_4 => Dbg_TrData_4, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_4 => Dbg_TrReady_4, -- [out std_logic]
Dbg_TrValid_4 => Dbg_TrValid_4, -- [in std_logic]
Dbg_Clk_5 => Dbg_Clk_5, -- [out std_logic]
Dbg_TDI_5 => Dbg_TDI_5, -- [out std_logic]
Dbg_TDO_5 => Dbg_TDO_5, -- [in std_logic]
Dbg_Reg_En_5 => Dbg_Reg_En_5, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_5 => Dbg_Capture_5, -- [out std_logic]
Dbg_Shift_5 => Dbg_Shift_5, -- [out std_logic]
Dbg_Update_5 => Dbg_Update_5, -- [out std_logic]
Dbg_Rst_5 => Dbg_Rst_5, -- [out std_logic]
Dbg_Trig_In_5 => Dbg_Trig_In_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_5 => Dbg_Trig_Ack_In_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_5 => Dbg_Trig_Out_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_5 => Dbg_Trig_Ack_Out_5, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_5 => Dbg_TrClk_5, -- [out std_logic]
Dbg_TrData_5 => Dbg_TrData_5, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_5 => Dbg_TrReady_5, -- [out std_logic]
Dbg_TrValid_5 => Dbg_TrValid_5, -- [in std_logic]
Dbg_Clk_6 => Dbg_Clk_6, -- [out std_logic]
Dbg_TDI_6 => Dbg_TDI_6, -- [out std_logic]
Dbg_TDO_6 => Dbg_TDO_6, -- [in std_logic]
Dbg_Reg_En_6 => Dbg_Reg_En_6, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_6 => Dbg_Capture_6, -- [out std_logic]
Dbg_Shift_6 => Dbg_Shift_6, -- [out std_logic]
Dbg_Update_6 => Dbg_Update_6, -- [out std_logic]
Dbg_Rst_6 => Dbg_Rst_6, -- [out std_logic]
Dbg_Trig_In_6 => Dbg_Trig_In_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_6 => Dbg_Trig_Ack_In_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_6 => Dbg_Trig_Out_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_6 => Dbg_Trig_Ack_Out_6, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_6 => Dbg_TrClk_6, -- [out std_logic]
Dbg_TrData_6 => Dbg_TrData_6, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_6 => Dbg_TrReady_6, -- [out std_logic]
Dbg_TrValid_6 => Dbg_TrValid_6, -- [in std_logic]
Dbg_Clk_7 => Dbg_Clk_7, -- [out std_logic]
Dbg_TDI_7 => Dbg_TDI_7, -- [out std_logic]
Dbg_TDO_7 => Dbg_TDO_7, -- [in std_logic]
Dbg_Reg_En_7 => Dbg_Reg_En_7, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_7 => Dbg_Capture_7, -- [out std_logic]
Dbg_Shift_7 => Dbg_Shift_7, -- [out std_logic]
Dbg_Update_7 => Dbg_Update_7, -- [out std_logic]
Dbg_Rst_7 => Dbg_Rst_7, -- [out std_logic]
Dbg_Trig_In_7 => Dbg_Trig_In_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_7 => Dbg_Trig_Ack_In_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_7 => Dbg_Trig_Out_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_7 => Dbg_Trig_Ack_Out_7, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_7 => Dbg_TrClk_7, -- [out std_logic]
Dbg_TrData_7 => Dbg_TrData_7, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_7 => Dbg_TrReady_7, -- [out std_logic]
Dbg_TrValid_7 => Dbg_TrValid_7, -- [in std_logic]
Dbg_Clk_8 => Dbg_Clk_8, -- [out std_logic]
Dbg_TDI_8 => Dbg_TDI_8, -- [out std_logic]
Dbg_TDO_8 => Dbg_TDO_8, -- [in std_logic]
Dbg_Reg_En_8 => Dbg_Reg_En_8, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_8 => Dbg_Capture_8, -- [out std_logic]
Dbg_Shift_8 => Dbg_Shift_8, -- [out std_logic]
Dbg_Update_8 => Dbg_Update_8, -- [out std_logic]
Dbg_Rst_8 => Dbg_Rst_8, -- [out std_logic]
Dbg_Trig_In_8 => Dbg_Trig_In_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_8 => Dbg_Trig_Ack_In_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_8 => Dbg_Trig_Out_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_8 => Dbg_Trig_Ack_Out_8, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_8 => Dbg_TrClk_8, -- [out std_logic]
Dbg_TrData_8 => Dbg_TrData_8, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_8 => Dbg_TrReady_8, -- [out std_logic]
Dbg_TrValid_8 => Dbg_TrValid_8, -- [in std_logic]
Dbg_Clk_9 => Dbg_Clk_9, -- [out std_logic]
Dbg_TDI_9 => Dbg_TDI_9, -- [out std_logic]
Dbg_TDO_9 => Dbg_TDO_9, -- [in std_logic]
Dbg_Reg_En_9 => Dbg_Reg_En_9, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_9 => Dbg_Capture_9, -- [out std_logic]
Dbg_Shift_9 => Dbg_Shift_9, -- [out std_logic]
Dbg_Update_9 => Dbg_Update_9, -- [out std_logic]
Dbg_Rst_9 => Dbg_Rst_9, -- [out std_logic]
Dbg_Trig_In_9 => Dbg_Trig_In_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_9 => Dbg_Trig_Ack_In_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_9 => Dbg_Trig_Out_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_9 => Dbg_Trig_Ack_Out_9, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_9 => Dbg_TrClk_9, -- [out std_logic]
Dbg_TrData_9 => Dbg_TrData_9, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_9 => Dbg_TrReady_9, -- [out std_logic]
Dbg_TrValid_9 => Dbg_TrValid_9, -- [in std_logic]
Dbg_Clk_10 => Dbg_Clk_10, -- [out std_logic]
Dbg_TDI_10 => Dbg_TDI_10, -- [out std_logic]
Dbg_TDO_10 => Dbg_TDO_10, -- [in std_logic]
Dbg_Reg_En_10 => Dbg_Reg_En_10, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_10 => Dbg_Capture_10, -- [out std_logic]
Dbg_Shift_10 => Dbg_Shift_10, -- [out std_logic]
Dbg_Update_10 => Dbg_Update_10, -- [out std_logic]
Dbg_Rst_10 => Dbg_Rst_10, -- [out std_logic]
Dbg_Trig_In_10 => Dbg_Trig_In_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_10 => Dbg_Trig_Ack_In_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_10 => Dbg_Trig_Out_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_10 => Dbg_Trig_Ack_Out_10, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_10 => Dbg_TrClk_10, -- [out std_logic]
Dbg_TrData_10 => Dbg_TrData_10, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_10 => Dbg_TrReady_10, -- [out std_logic]
Dbg_TrValid_10 => Dbg_TrValid_10, -- [in std_logic]
Dbg_Clk_11 => Dbg_Clk_11, -- [out std_logic]
Dbg_TDI_11 => Dbg_TDI_11, -- [out std_logic]
Dbg_TDO_11 => Dbg_TDO_11, -- [in std_logic]
Dbg_Reg_En_11 => Dbg_Reg_En_11, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_11 => Dbg_Capture_11, -- [out std_logic]
Dbg_Shift_11 => Dbg_Shift_11, -- [out std_logic]
Dbg_Update_11 => Dbg_Update_11, -- [out std_logic]
Dbg_Rst_11 => Dbg_Rst_11, -- [out std_logic]
Dbg_Trig_In_11 => Dbg_Trig_In_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_11 => Dbg_Trig_Ack_In_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_11 => Dbg_Trig_Out_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_11 => Dbg_Trig_Ack_Out_11, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_11 => Dbg_TrClk_11, -- [out std_logic]
Dbg_TrData_11 => Dbg_TrData_11, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_11 => Dbg_TrReady_11, -- [out std_logic]
Dbg_TrValid_11 => Dbg_TrValid_11, -- [in std_logic]
Dbg_Clk_12 => Dbg_Clk_12, -- [out std_logic]
Dbg_TDI_12 => Dbg_TDI_12, -- [out std_logic]
Dbg_TDO_12 => Dbg_TDO_12, -- [in std_logic]
Dbg_Reg_En_12 => Dbg_Reg_En_12, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_12 => Dbg_Capture_12, -- [out std_logic]
Dbg_Shift_12 => Dbg_Shift_12, -- [out std_logic]
Dbg_Update_12 => Dbg_Update_12, -- [out std_logic]
Dbg_Rst_12 => Dbg_Rst_12, -- [out std_logic]
Dbg_Trig_In_12 => Dbg_Trig_In_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_12 => Dbg_Trig_Ack_In_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_12 => Dbg_Trig_Out_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_12 => Dbg_Trig_Ack_Out_12, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_12 => Dbg_TrClk_12, -- [out std_logic]
Dbg_TrData_12 => Dbg_TrData_12, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_12 => Dbg_TrReady_12, -- [out std_logic]
Dbg_TrValid_12 => Dbg_TrValid_12, -- [in std_logic]
Dbg_Clk_13 => Dbg_Clk_13, -- [out std_logic]
Dbg_TDI_13 => Dbg_TDI_13, -- [out std_logic]
Dbg_TDO_13 => Dbg_TDO_13, -- [in std_logic]
Dbg_Reg_En_13 => Dbg_Reg_En_13, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_13 => Dbg_Capture_13, -- [out std_logic]
Dbg_Shift_13 => Dbg_Shift_13, -- [out std_logic]
Dbg_Update_13 => Dbg_Update_13, -- [out std_logic]
Dbg_Rst_13 => Dbg_Rst_13, -- [out std_logic]
Dbg_Trig_In_13 => Dbg_Trig_In_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_13 => Dbg_Trig_Ack_In_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_13 => Dbg_Trig_Out_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_13 => Dbg_Trig_Ack_Out_13, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_13 => Dbg_TrClk_13, -- [out std_logic]
Dbg_TrData_13 => Dbg_TrData_13, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_13 => Dbg_TrReady_13, -- [out std_logic]
Dbg_TrValid_13 => Dbg_TrValid_13, -- [in std_logic]
Dbg_Clk_14 => Dbg_Clk_14, -- [out std_logic]
Dbg_TDI_14 => Dbg_TDI_14, -- [out std_logic]
Dbg_TDO_14 => Dbg_TDO_14, -- [in std_logic]
Dbg_Reg_En_14 => Dbg_Reg_En_14, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_14 => Dbg_Capture_14, -- [out std_logic]
Dbg_Shift_14 => Dbg_Shift_14, -- [out std_logic]
Dbg_Update_14 => Dbg_Update_14, -- [out std_logic]
Dbg_Rst_14 => Dbg_Rst_14, -- [out std_logic]
Dbg_Trig_In_14 => Dbg_Trig_In_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_14 => Dbg_Trig_Ack_In_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_14 => Dbg_Trig_Out_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_14 => Dbg_Trig_Ack_Out_14, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_14 => Dbg_TrClk_14, -- [out std_logic]
Dbg_TrData_14 => Dbg_TrData_14, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_14 => Dbg_TrReady_14, -- [out std_logic]
Dbg_TrValid_14 => Dbg_TrValid_14, -- [in std_logic]
Dbg_Clk_15 => Dbg_Clk_15, -- [out std_logic]
Dbg_TDI_15 => Dbg_TDI_15, -- [out std_logic]
Dbg_TDO_15 => Dbg_TDO_15, -- [in std_logic]
Dbg_Reg_En_15 => Dbg_Reg_En_15, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_15 => Dbg_Capture_15, -- [out std_logic]
Dbg_Shift_15 => Dbg_Shift_15, -- [out std_logic]
Dbg_Update_15 => Dbg_Update_15, -- [out std_logic]
Dbg_Rst_15 => Dbg_Rst_15, -- [out std_logic]
Dbg_Trig_In_15 => Dbg_Trig_In_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_15 => Dbg_Trig_Ack_In_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_15 => Dbg_Trig_Out_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_15 => Dbg_Trig_Ack_Out_15, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_15 => Dbg_TrClk_15, -- [out std_logic]
Dbg_TrData_15 => Dbg_TrData_15, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_15 => Dbg_TrReady_15, -- [out std_logic]
Dbg_TrValid_15 => Dbg_TrValid_15, -- [in std_logic]
Dbg_Clk_16 => Dbg_Clk_16, -- [out std_logic]
Dbg_TDI_16 => Dbg_TDI_16, -- [out std_logic]
Dbg_TDO_16 => Dbg_TDO_16, -- [in std_logic]
Dbg_Reg_En_16 => Dbg_Reg_En_16, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_16 => Dbg_Capture_16, -- [out std_logic]
Dbg_Shift_16 => Dbg_Shift_16, -- [out std_logic]
Dbg_Update_16 => Dbg_Update_16, -- [out std_logic]
Dbg_Rst_16 => Dbg_Rst_16, -- [out std_logic]
Dbg_Trig_In_16 => Dbg_Trig_In_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_16 => Dbg_Trig_Ack_In_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_16 => Dbg_Trig_Out_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_16 => Dbg_Trig_Ack_Out_16, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_16 => Dbg_TrClk_16, -- [out std_logic]
Dbg_TrData_16 => Dbg_TrData_16, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_16 => Dbg_TrReady_16, -- [out std_logic]
Dbg_TrValid_16 => Dbg_TrValid_16, -- [in std_logic]
Dbg_Clk_17 => Dbg_Clk_17, -- [out std_logic]
Dbg_TDI_17 => Dbg_TDI_17, -- [out std_logic]
Dbg_TDO_17 => Dbg_TDO_17, -- [in std_logic]
Dbg_Reg_En_17 => Dbg_Reg_En_17, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_17 => Dbg_Capture_17, -- [out std_logic]
Dbg_Shift_17 => Dbg_Shift_17, -- [out std_logic]
Dbg_Update_17 => Dbg_Update_17, -- [out std_logic]
Dbg_Rst_17 => Dbg_Rst_17, -- [out std_logic]
Dbg_Trig_In_17 => Dbg_Trig_In_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_17 => Dbg_Trig_Ack_In_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_17 => Dbg_Trig_Out_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_17 => Dbg_Trig_Ack_Out_17, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_17 => Dbg_TrClk_17, -- [out std_logic]
Dbg_TrData_17 => Dbg_TrData_17, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_17 => Dbg_TrReady_17, -- [out std_logic]
Dbg_TrValid_17 => Dbg_TrValid_17, -- [in std_logic]
Dbg_Clk_18 => Dbg_Clk_18, -- [out std_logic]
Dbg_TDI_18 => Dbg_TDI_18, -- [out std_logic]
Dbg_TDO_18 => Dbg_TDO_18, -- [in std_logic]
Dbg_Reg_En_18 => Dbg_Reg_En_18, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_18 => Dbg_Capture_18, -- [out std_logic]
Dbg_Shift_18 => Dbg_Shift_18, -- [out std_logic]
Dbg_Update_18 => Dbg_Update_18, -- [out std_logic]
Dbg_Rst_18 => Dbg_Rst_18, -- [out std_logic]
Dbg_Trig_In_18 => Dbg_Trig_In_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_18 => Dbg_Trig_Ack_In_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_18 => Dbg_Trig_Out_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_18 => Dbg_Trig_Ack_Out_18, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_18 => Dbg_TrClk_18, -- [out std_logic]
Dbg_TrData_18 => Dbg_TrData_18, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_18 => Dbg_TrReady_18, -- [out std_logic]
Dbg_TrValid_18 => Dbg_TrValid_18, -- [in std_logic]
Dbg_Clk_19 => Dbg_Clk_19, -- [out std_logic]
Dbg_TDI_19 => Dbg_TDI_19, -- [out std_logic]
Dbg_TDO_19 => Dbg_TDO_19, -- [in std_logic]
Dbg_Reg_En_19 => Dbg_Reg_En_19, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_19 => Dbg_Capture_19, -- [out std_logic]
Dbg_Shift_19 => Dbg_Shift_19, -- [out std_logic]
Dbg_Update_19 => Dbg_Update_19, -- [out std_logic]
Dbg_Rst_19 => Dbg_Rst_19, -- [out std_logic]
Dbg_Trig_In_19 => Dbg_Trig_In_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_19 => Dbg_Trig_Ack_In_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_19 => Dbg_Trig_Out_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_19 => Dbg_Trig_Ack_Out_19, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_19 => Dbg_TrClk_19, -- [out std_logic]
Dbg_TrData_19 => Dbg_TrData_19, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_19 => Dbg_TrReady_19, -- [out std_logic]
Dbg_TrValid_19 => Dbg_TrValid_19, -- [in std_logic]
Dbg_Clk_20 => Dbg_Clk_20, -- [out std_logic]
Dbg_TDI_20 => Dbg_TDI_20, -- [out std_logic]
Dbg_TDO_20 => Dbg_TDO_20, -- [in std_logic]
Dbg_Reg_En_20 => Dbg_Reg_En_20, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_20 => Dbg_Capture_20, -- [out std_logic]
Dbg_Shift_20 => Dbg_Shift_20, -- [out std_logic]
Dbg_Update_20 => Dbg_Update_20, -- [out std_logic]
Dbg_Rst_20 => Dbg_Rst_20, -- [out std_logic]
Dbg_Trig_In_20 => Dbg_Trig_In_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_20 => Dbg_Trig_Ack_In_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_20 => Dbg_Trig_Out_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_20 => Dbg_Trig_Ack_Out_20, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_20 => Dbg_TrClk_20, -- [out std_logic]
Dbg_TrData_20 => Dbg_TrData_20, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_20 => Dbg_TrReady_20, -- [out std_logic]
Dbg_TrValid_20 => Dbg_TrValid_20, -- [in std_logic]
Dbg_Clk_21 => Dbg_Clk_21, -- [out std_logic]
Dbg_TDI_21 => Dbg_TDI_21, -- [out std_logic]
Dbg_TDO_21 => Dbg_TDO_21, -- [in std_logic]
Dbg_Reg_En_21 => Dbg_Reg_En_21, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_21 => Dbg_Capture_21, -- [out std_logic]
Dbg_Shift_21 => Dbg_Shift_21, -- [out std_logic]
Dbg_Update_21 => Dbg_Update_21, -- [out std_logic]
Dbg_Rst_21 => Dbg_Rst_21, -- [out std_logic]
Dbg_Trig_In_21 => Dbg_Trig_In_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_21 => Dbg_Trig_Ack_In_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_21 => Dbg_Trig_Out_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_21 => Dbg_Trig_Ack_Out_21, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_21 => Dbg_TrClk_21, -- [out std_logic]
Dbg_TrData_21 => Dbg_TrData_21, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_21 => Dbg_TrReady_21, -- [out std_logic]
Dbg_TrValid_21 => Dbg_TrValid_21, -- [in std_logic]
Dbg_Clk_22 => Dbg_Clk_22, -- [out std_logic]
Dbg_TDI_22 => Dbg_TDI_22, -- [out std_logic]
Dbg_TDO_22 => Dbg_TDO_22, -- [in std_logic]
Dbg_Reg_En_22 => Dbg_Reg_En_22, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_22 => Dbg_Capture_22, -- [out std_logic]
Dbg_Shift_22 => Dbg_Shift_22, -- [out std_logic]
Dbg_Update_22 => Dbg_Update_22, -- [out std_logic]
Dbg_Rst_22 => Dbg_Rst_22, -- [out std_logic]
Dbg_Trig_In_22 => Dbg_Trig_In_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_22 => Dbg_Trig_Ack_In_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_22 => Dbg_Trig_Out_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_22 => Dbg_Trig_Ack_Out_22, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_22 => Dbg_TrClk_22, -- [out std_logic]
Dbg_TrData_22 => Dbg_TrData_22, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_22 => Dbg_TrReady_22, -- [out std_logic]
Dbg_TrValid_22 => Dbg_TrValid_22, -- [in std_logic]
Dbg_Clk_23 => Dbg_Clk_23, -- [out std_logic]
Dbg_TDI_23 => Dbg_TDI_23, -- [out std_logic]
Dbg_TDO_23 => Dbg_TDO_23, -- [in std_logic]
Dbg_Reg_En_23 => Dbg_Reg_En_23, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_23 => Dbg_Capture_23, -- [out std_logic]
Dbg_Shift_23 => Dbg_Shift_23, -- [out std_logic]
Dbg_Update_23 => Dbg_Update_23, -- [out std_logic]
Dbg_Rst_23 => Dbg_Rst_23, -- [out std_logic]
Dbg_Trig_In_23 => Dbg_Trig_In_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_23 => Dbg_Trig_Ack_In_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_23 => Dbg_Trig_Out_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_23 => Dbg_Trig_Ack_Out_23, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_23 => Dbg_TrClk_23, -- [out std_logic]
Dbg_TrData_23 => Dbg_TrData_23, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_23 => Dbg_TrReady_23, -- [out std_logic]
Dbg_TrValid_23 => Dbg_TrValid_23, -- [in std_logic]
Dbg_Clk_24 => Dbg_Clk_24, -- [out std_logic]
Dbg_TDI_24 => Dbg_TDI_24, -- [out std_logic]
Dbg_TDO_24 => Dbg_TDO_24, -- [in std_logic]
Dbg_Reg_En_24 => Dbg_Reg_En_24, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_24 => Dbg_Capture_24, -- [out std_logic]
Dbg_Shift_24 => Dbg_Shift_24, -- [out std_logic]
Dbg_Update_24 => Dbg_Update_24, -- [out std_logic]
Dbg_Rst_24 => Dbg_Rst_24, -- [out std_logic]
Dbg_Trig_In_24 => Dbg_Trig_In_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_24 => Dbg_Trig_Ack_In_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_24 => Dbg_Trig_Out_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_24 => Dbg_Trig_Ack_Out_24, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_24 => Dbg_TrClk_24, -- [out std_logic]
Dbg_TrData_24 => Dbg_TrData_24, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_24 => Dbg_TrReady_24, -- [out std_logic]
Dbg_TrValid_24 => Dbg_TrValid_24, -- [in std_logic]
Dbg_Clk_25 => Dbg_Clk_25, -- [out std_logic]
Dbg_TDI_25 => Dbg_TDI_25, -- [out std_logic]
Dbg_TDO_25 => Dbg_TDO_25, -- [in std_logic]
Dbg_Reg_En_25 => Dbg_Reg_En_25, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_25 => Dbg_Capture_25, -- [out std_logic]
Dbg_Shift_25 => Dbg_Shift_25, -- [out std_logic]
Dbg_Update_25 => Dbg_Update_25, -- [out std_logic]
Dbg_Rst_25 => Dbg_Rst_25, -- [out std_logic]
Dbg_Trig_In_25 => Dbg_Trig_In_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_25 => Dbg_Trig_Ack_In_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_25 => Dbg_Trig_Out_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_25 => Dbg_Trig_Ack_Out_25, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_25 => Dbg_TrClk_25, -- [out std_logic]
Dbg_TrData_25 => Dbg_TrData_25, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_25 => Dbg_TrReady_25, -- [out std_logic]
Dbg_TrValid_25 => Dbg_TrValid_25, -- [in std_logic]
Dbg_Clk_26 => Dbg_Clk_26, -- [out std_logic]
Dbg_TDI_26 => Dbg_TDI_26, -- [out std_logic]
Dbg_TDO_26 => Dbg_TDO_26, -- [in std_logic]
Dbg_Reg_En_26 => Dbg_Reg_En_26, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_26 => Dbg_Capture_26, -- [out std_logic]
Dbg_Shift_26 => Dbg_Shift_26, -- [out std_logic]
Dbg_Update_26 => Dbg_Update_26, -- [out std_logic]
Dbg_Rst_26 => Dbg_Rst_26, -- [out std_logic]
Dbg_Trig_In_26 => Dbg_Trig_In_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_26 => Dbg_Trig_Ack_In_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_26 => Dbg_Trig_Out_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_26 => Dbg_Trig_Ack_Out_26, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_26 => Dbg_TrClk_26, -- [out std_logic]
Dbg_TrData_26 => Dbg_TrData_26, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_26 => Dbg_TrReady_26, -- [out std_logic]
Dbg_TrValid_26 => Dbg_TrValid_26, -- [in std_logic]
Dbg_Clk_27 => Dbg_Clk_27, -- [out std_logic]
Dbg_TDI_27 => Dbg_TDI_27, -- [out std_logic]
Dbg_TDO_27 => Dbg_TDO_27, -- [in std_logic]
Dbg_Reg_En_27 => Dbg_Reg_En_27, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_27 => Dbg_Capture_27, -- [out std_logic]
Dbg_Shift_27 => Dbg_Shift_27, -- [out std_logic]
Dbg_Update_27 => Dbg_Update_27, -- [out std_logic]
Dbg_Rst_27 => Dbg_Rst_27, -- [out std_logic]
Dbg_Trig_In_27 => Dbg_Trig_In_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_27 => Dbg_Trig_Ack_In_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_27 => Dbg_Trig_Out_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_27 => Dbg_Trig_Ack_Out_27, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_27 => Dbg_TrClk_27, -- [out std_logic]
Dbg_TrData_27 => Dbg_TrData_27, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_27 => Dbg_TrReady_27, -- [out std_logic]
Dbg_TrValid_27 => Dbg_TrValid_27, -- [in std_logic]
Dbg_Clk_28 => Dbg_Clk_28, -- [out std_logic]
Dbg_TDI_28 => Dbg_TDI_28, -- [out std_logic]
Dbg_TDO_28 => Dbg_TDO_28, -- [in std_logic]
Dbg_Reg_En_28 => Dbg_Reg_En_28, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_28 => Dbg_Capture_28, -- [out std_logic]
Dbg_Shift_28 => Dbg_Shift_28, -- [out std_logic]
Dbg_Update_28 => Dbg_Update_28, -- [out std_logic]
Dbg_Rst_28 => Dbg_Rst_28, -- [out std_logic]
Dbg_Trig_In_28 => Dbg_Trig_In_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_28 => Dbg_Trig_Ack_In_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_28 => Dbg_Trig_Out_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_28 => Dbg_Trig_Ack_Out_28, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_28 => Dbg_TrClk_28, -- [out std_logic]
Dbg_TrData_28 => Dbg_TrData_28, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_28 => Dbg_TrReady_28, -- [out std_logic]
Dbg_TrValid_28 => Dbg_TrValid_28, -- [in std_logic]
Dbg_Clk_29 => Dbg_Clk_29, -- [out std_logic]
Dbg_TDI_29 => Dbg_TDI_29, -- [out std_logic]
Dbg_TDO_29 => Dbg_TDO_29, -- [in std_logic]
Dbg_Reg_En_29 => Dbg_Reg_En_29, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_29 => Dbg_Capture_29, -- [out std_logic]
Dbg_Shift_29 => Dbg_Shift_29, -- [out std_logic]
Dbg_Update_29 => Dbg_Update_29, -- [out std_logic]
Dbg_Rst_29 => Dbg_Rst_29, -- [out std_logic]
Dbg_Trig_In_29 => Dbg_Trig_In_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_29 => Dbg_Trig_Ack_In_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_29 => Dbg_Trig_Out_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_29 => Dbg_Trig_Ack_Out_29, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_29 => Dbg_TrClk_29, -- [out std_logic]
Dbg_TrData_29 => Dbg_TrData_29, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_29 => Dbg_TrReady_29, -- [out std_logic]
Dbg_TrValid_29 => Dbg_TrValid_29, -- [in std_logic]
Dbg_Clk_30 => Dbg_Clk_30, -- [out std_logic]
Dbg_TDI_30 => Dbg_TDI_30, -- [out std_logic]
Dbg_TDO_30 => Dbg_TDO_30, -- [in std_logic]
Dbg_Reg_En_30 => Dbg_Reg_En_30, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_30 => Dbg_Capture_30, -- [out std_logic]
Dbg_Shift_30 => Dbg_Shift_30, -- [out std_logic]
Dbg_Update_30 => Dbg_Update_30, -- [out std_logic]
Dbg_Rst_30 => Dbg_Rst_30, -- [out std_logic]
Dbg_Trig_In_30 => Dbg_Trig_In_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_30 => Dbg_Trig_Ack_In_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_30 => Dbg_Trig_Out_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_30 => Dbg_Trig_Ack_Out_30, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_30 => Dbg_TrClk_30, -- [out std_logic]
Dbg_TrData_30 => Dbg_TrData_30, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_30 => Dbg_TrReady_30, -- [out std_logic]
Dbg_TrValid_30 => Dbg_TrValid_30, -- [in std_logic]
Dbg_Clk_31 => Dbg_Clk_31, -- [out std_logic]
Dbg_TDI_31 => Dbg_TDI_31, -- [out std_logic]
Dbg_TDO_31 => Dbg_TDO_31, -- [in std_logic]
Dbg_Reg_En_31 => Dbg_Reg_En_31, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_31 => Dbg_Capture_31, -- [out std_logic]
Dbg_Shift_31 => Dbg_Shift_31, -- [out std_logic]
Dbg_Update_31 => Dbg_Update_31, -- [out std_logic]
Dbg_Rst_31 => Dbg_Rst_31, -- [out std_logic]
Dbg_Trig_In_31 => Dbg_Trig_In_31, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_31 => Dbg_Trig_Ack_In_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_31 => Dbg_Trig_Out_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_31 => Dbg_Trig_Ack_Out_31, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_31 => Dbg_TrClk_31, -- [out std_logic]
Dbg_TrData_31 => Dbg_TrData_31, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_31 => Dbg_TrReady_31, -- [out std_logic]
Dbg_TrValid_31 => Dbg_TrValid_31, -- [in std_logic]
Ext_Trig_In => ext_trig_in, -- [in std_logic_vector(0 to 3)]
Ext_Trig_Ack_In => ext_trig_ack_in, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Out => ext_trig_out, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Ack_Out => ext_trig_ack_out, -- [in std_logic_vector(0 to 3)]
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
ext_trig_in <= Trig_In_0 & Trig_In_1 & Trig_In_2 & Trig_In_3;
ext_trig_ack_out <= Trig_Ack_Out_0 & Trig_Ack_Out_1 & Trig_Ack_Out_2 & Trig_Ack_Out_3;
Trig_Ack_In_0 <= ext_trig_ack_in(0);
Trig_Ack_In_1 <= ext_trig_ack_in(1);
Trig_Ack_In_2 <= ext_trig_ack_in(2);
Trig_Ack_In_3 <= ext_trig_ack_in(3);
Trig_Out_0 <= ext_trig_out(0);
Trig_Out_1 <= ext_trig_out(1);
Trig_Out_2 <= ext_trig_out(2);
Trig_Out_3 <= ext_trig_out(3);
-- Bus Master port
Use_Bus_MASTER : if (C_DBG_MEM_ACCESS = 1) generate
type LMB_vec_type is array (natural range <>) of std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_addr : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_write : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_addr_strobe : std_logic;
signal lmb_read_strobe : std_logic;
signal lmb_write_strobe : std_logic;
signal lmb_ready : std_logic;
signal lmb_wait : std_logic;
signal lmb_ue : std_logic;
signal lmb_byte_enable : std_logic_vector(0 to C_DATA_SIZE / 8 - 1);
signal lmb_addr_strobe_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec : LMB_vec_type(0 to 31);
signal lmb_ready_vec : std_logic_vector(0 to 31);
signal lmb_wait_vec : std_logic_vector(0 to 31);
signal lmb_ue_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec_q : LMB_vec_type(0 to C_EN_WIDTH - 1);
signal lmb_ready_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_wait_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_ue_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => true,
C_HAS_DIRECT_PORT => C_TRACE_AXI_MASTER
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => lmb_data_addr,
LMB_Data_Read => lmb_data_read,
LMB_Data_Write => lmb_data_write,
LMB_Addr_Strobe => lmb_addr_strobe,
LMB_Read_Strobe => lmb_read_strobe,
LMB_Write_Strobe => lmb_write_strobe,
LMB_Ready => lmb_ready,
LMB_Wait => lmb_wait,
LMB_UE => lmb_ue,
LMB_Byte_Enable => lmb_byte_enable,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
Generate_LMB_Outputs : process (mb_debug_enabled, lmb_addr_strobe)
begin -- process Generate_LMB_Outputs
lmb_addr_strobe_vec <= (others => '0');
for I in 0 to C_EN_WIDTH - 1 loop
lmb_addr_strobe_vec(I) <= lmb_addr_strobe and mb_debug_enabled(I);
end loop;
end process Generate_LMB_Outputs;
LMB_Addr_Strobe_0 <= lmb_addr_strobe_vec(0);
LMB_Addr_Strobe_1 <= lmb_addr_strobe_vec(1);
LMB_Addr_Strobe_2 <= lmb_addr_strobe_vec(2);
LMB_Addr_Strobe_3 <= lmb_addr_strobe_vec(3);
LMB_Addr_Strobe_4 <= lmb_addr_strobe_vec(4);
LMB_Addr_Strobe_5 <= lmb_addr_strobe_vec(5);
LMB_Addr_Strobe_6 <= lmb_addr_strobe_vec(6);
LMB_Addr_Strobe_7 <= lmb_addr_strobe_vec(7);
LMB_Addr_Strobe_8 <= lmb_addr_strobe_vec(8);
LMB_Addr_Strobe_9 <= lmb_addr_strobe_vec(9);
LMB_Addr_Strobe_10 <= lmb_addr_strobe_vec(10);
LMB_Addr_Strobe_11 <= lmb_addr_strobe_vec(11);
LMB_Addr_Strobe_12 <= lmb_addr_strobe_vec(12);
LMB_Addr_Strobe_13 <= lmb_addr_strobe_vec(13);
LMB_Addr_Strobe_14 <= lmb_addr_strobe_vec(14);
LMB_Addr_Strobe_15 <= lmb_addr_strobe_vec(15);
LMB_Addr_Strobe_16 <= lmb_addr_strobe_vec(16);
LMB_Addr_Strobe_17 <= lmb_addr_strobe_vec(17);
LMB_Addr_Strobe_18 <= lmb_addr_strobe_vec(18);
LMB_Addr_Strobe_19 <= lmb_addr_strobe_vec(19);
LMB_Addr_Strobe_20 <= lmb_addr_strobe_vec(20);
LMB_Addr_Strobe_21 <= lmb_addr_strobe_vec(21);
LMB_Addr_Strobe_22 <= lmb_addr_strobe_vec(22);
LMB_Addr_Strobe_23 <= lmb_addr_strobe_vec(23);
LMB_Addr_Strobe_24 <= lmb_addr_strobe_vec(24);
LMB_Addr_Strobe_25 <= lmb_addr_strobe_vec(25);
LMB_Addr_Strobe_26 <= lmb_addr_strobe_vec(26);
LMB_Addr_Strobe_27 <= lmb_addr_strobe_vec(27);
LMB_Addr_Strobe_28 <= lmb_addr_strobe_vec(28);
LMB_Addr_Strobe_29 <= lmb_addr_strobe_vec(29);
LMB_Addr_Strobe_30 <= lmb_addr_strobe_vec(30);
LMB_Addr_Strobe_31 <= lmb_addr_strobe_vec(31);
LMB_Data_Addr_0 <= lmb_data_addr;
LMB_Data_Addr_1 <= lmb_data_addr;
LMB_Data_Addr_2 <= lmb_data_addr;
LMB_Data_Addr_3 <= lmb_data_addr;
LMB_Data_Addr_4 <= lmb_data_addr;
LMB_Data_Addr_5 <= lmb_data_addr;
LMB_Data_Addr_6 <= lmb_data_addr;
LMB_Data_Addr_7 <= lmb_data_addr;
LMB_Data_Addr_8 <= lmb_data_addr;
LMB_Data_Addr_9 <= lmb_data_addr;
LMB_Data_Addr_10 <= lmb_data_addr;
LMB_Data_Addr_11 <= lmb_data_addr;
LMB_Data_Addr_12 <= lmb_data_addr;
LMB_Data_Addr_13 <= lmb_data_addr;
LMB_Data_Addr_14 <= lmb_data_addr;
LMB_Data_Addr_15 <= lmb_data_addr;
LMB_Data_Addr_16 <= lmb_data_addr;
LMB_Data_Addr_17 <= lmb_data_addr;
LMB_Data_Addr_18 <= lmb_data_addr;
LMB_Data_Addr_19 <= lmb_data_addr;
LMB_Data_Addr_20 <= lmb_data_addr;
LMB_Data_Addr_21 <= lmb_data_addr;
LMB_Data_Addr_22 <= lmb_data_addr;
LMB_Data_Addr_23 <= lmb_data_addr;
LMB_Data_Addr_24 <= lmb_data_addr;
LMB_Data_Addr_25 <= lmb_data_addr;
LMB_Data_Addr_26 <= lmb_data_addr;
LMB_Data_Addr_27 <= lmb_data_addr;
LMB_Data_Addr_28 <= lmb_data_addr;
LMB_Data_Addr_29 <= lmb_data_addr;
LMB_Data_Addr_30 <= lmb_data_addr;
LMB_Data_Addr_31 <= lmb_data_addr;
LMB_Data_write_0 <= lmb_data_write;
LMB_Data_write_1 <= lmb_data_write;
LMB_Data_write_2 <= lmb_data_write;
LMB_Data_write_3 <= lmb_data_write;
LMB_Data_write_4 <= lmb_data_write;
LMB_Data_write_5 <= lmb_data_write;
LMB_Data_write_6 <= lmb_data_write;
LMB_Data_write_7 <= lmb_data_write;
LMB_Data_write_8 <= lmb_data_write;
LMB_Data_write_9 <= lmb_data_write;
LMB_Data_write_10 <= lmb_data_write;
LMB_Data_write_11 <= lmb_data_write;
LMB_Data_write_12 <= lmb_data_write;
LMB_Data_write_13 <= lmb_data_write;
LMB_Data_write_14 <= lmb_data_write;
LMB_Data_write_15 <= lmb_data_write;
LMB_Data_write_16 <= lmb_data_write;
LMB_Data_write_17 <= lmb_data_write;
LMB_Data_write_18 <= lmb_data_write;
LMB_Data_write_19 <= lmb_data_write;
LMB_Data_write_20 <= lmb_data_write;
LMB_Data_write_21 <= lmb_data_write;
LMB_Data_write_22 <= lmb_data_write;
LMB_Data_write_23 <= lmb_data_write;
LMB_Data_write_24 <= lmb_data_write;
LMB_Data_write_25 <= lmb_data_write;
LMB_Data_write_26 <= lmb_data_write;
LMB_Data_write_27 <= lmb_data_write;
LMB_Data_write_28 <= lmb_data_write;
LMB_Data_write_29 <= lmb_data_write;
LMB_Data_write_30 <= lmb_data_write;
LMB_Data_write_31 <= lmb_data_write;
LMB_Read_strobe_0 <= lmb_read_strobe;
LMB_Read_strobe_1 <= lmb_read_strobe;
LMB_Read_strobe_2 <= lmb_read_strobe;
LMB_Read_strobe_3 <= lmb_read_strobe;
LMB_Read_strobe_4 <= lmb_read_strobe;
LMB_Read_strobe_5 <= lmb_read_strobe;
LMB_Read_strobe_6 <= lmb_read_strobe;
LMB_Read_strobe_7 <= lmb_read_strobe;
LMB_Read_strobe_8 <= lmb_read_strobe;
LMB_Read_strobe_9 <= lmb_read_strobe;
LMB_Read_strobe_10 <= lmb_read_strobe;
LMB_Read_strobe_11 <= lmb_read_strobe;
LMB_Read_strobe_12 <= lmb_read_strobe;
LMB_Read_strobe_13 <= lmb_read_strobe;
LMB_Read_strobe_14 <= lmb_read_strobe;
LMB_Read_strobe_15 <= lmb_read_strobe;
LMB_Read_strobe_16 <= lmb_read_strobe;
LMB_Read_strobe_17 <= lmb_read_strobe;
LMB_Read_strobe_18 <= lmb_read_strobe;
LMB_Read_strobe_19 <= lmb_read_strobe;
LMB_Read_strobe_20 <= lmb_read_strobe;
LMB_Read_strobe_21 <= lmb_read_strobe;
LMB_Read_strobe_22 <= lmb_read_strobe;
LMB_Read_strobe_23 <= lmb_read_strobe;
LMB_Read_strobe_24 <= lmb_read_strobe;
LMB_Read_strobe_25 <= lmb_read_strobe;
LMB_Read_strobe_26 <= lmb_read_strobe;
LMB_Read_strobe_27 <= lmb_read_strobe;
LMB_Read_strobe_28 <= lmb_read_strobe;
LMB_Read_strobe_29 <= lmb_read_strobe;
LMB_Read_strobe_30 <= lmb_read_strobe;
LMB_Read_strobe_31 <= lmb_read_strobe;
LMB_Write_strobe_0 <= lmb_write_strobe;
LMB_Write_strobe_1 <= lmb_write_strobe;
LMB_Write_strobe_2 <= lmb_write_strobe;
LMB_Write_strobe_3 <= lmb_write_strobe;
LMB_Write_strobe_4 <= lmb_write_strobe;
LMB_Write_strobe_5 <= lmb_write_strobe;
LMB_Write_strobe_6 <= lmb_write_strobe;
LMB_Write_strobe_7 <= lmb_write_strobe;
LMB_Write_strobe_8 <= lmb_write_strobe;
LMB_Write_strobe_9 <= lmb_write_strobe;
LMB_Write_strobe_10 <= lmb_write_strobe;
LMB_Write_strobe_11 <= lmb_write_strobe;
LMB_Write_strobe_12 <= lmb_write_strobe;
LMB_Write_strobe_13 <= lmb_write_strobe;
LMB_Write_strobe_14 <= lmb_write_strobe;
LMB_Write_strobe_15 <= lmb_write_strobe;
LMB_Write_strobe_16 <= lmb_write_strobe;
LMB_Write_strobe_17 <= lmb_write_strobe;
LMB_Write_strobe_18 <= lmb_write_strobe;
LMB_Write_strobe_19 <= lmb_write_strobe;
LMB_Write_strobe_20 <= lmb_write_strobe;
LMB_Write_strobe_21 <= lmb_write_strobe;
LMB_Write_strobe_22 <= lmb_write_strobe;
LMB_Write_strobe_23 <= lmb_write_strobe;
LMB_Write_strobe_24 <= lmb_write_strobe;
LMB_Write_strobe_25 <= lmb_write_strobe;
LMB_Write_strobe_26 <= lmb_write_strobe;
LMB_Write_strobe_27 <= lmb_write_strobe;
LMB_Write_strobe_28 <= lmb_write_strobe;
LMB_Write_strobe_29 <= lmb_write_strobe;
LMB_Write_strobe_30 <= lmb_write_strobe;
LMB_Write_strobe_31 <= lmb_write_strobe;
LMB_Byte_enable_0 <= lmb_byte_enable;
LMB_Byte_enable_1 <= lmb_byte_enable;
LMB_Byte_enable_2 <= lmb_byte_enable;
LMB_Byte_enable_3 <= lmb_byte_enable;
LMB_Byte_enable_4 <= lmb_byte_enable;
LMB_Byte_enable_5 <= lmb_byte_enable;
LMB_Byte_enable_6 <= lmb_byte_enable;
LMB_Byte_enable_7 <= lmb_byte_enable;
LMB_Byte_enable_8 <= lmb_byte_enable;
LMB_Byte_enable_9 <= lmb_byte_enable;
LMB_Byte_enable_10 <= lmb_byte_enable;
LMB_Byte_enable_11 <= lmb_byte_enable;
LMB_Byte_enable_12 <= lmb_byte_enable;
LMB_Byte_enable_13 <= lmb_byte_enable;
LMB_Byte_enable_14 <= lmb_byte_enable;
LMB_Byte_enable_15 <= lmb_byte_enable;
LMB_Byte_enable_16 <= lmb_byte_enable;
LMB_Byte_enable_17 <= lmb_byte_enable;
LMB_Byte_enable_18 <= lmb_byte_enable;
LMB_Byte_enable_19 <= lmb_byte_enable;
LMB_Byte_enable_20 <= lmb_byte_enable;
LMB_Byte_enable_21 <= lmb_byte_enable;
LMB_Byte_enable_22 <= lmb_byte_enable;
LMB_Byte_enable_23 <= lmb_byte_enable;
LMB_Byte_enable_24 <= lmb_byte_enable;
LMB_Byte_enable_25 <= lmb_byte_enable;
LMB_Byte_enable_26 <= lmb_byte_enable;
LMB_Byte_enable_27 <= lmb_byte_enable;
LMB_Byte_enable_28 <= lmb_byte_enable;
LMB_Byte_enable_29 <= lmb_byte_enable;
LMB_Byte_enable_30 <= lmb_byte_enable;
LMB_Byte_enable_31 <= lmb_byte_enable;
Generate_LMB_Inputs : process (mb_debug_enabled, lmb_data_read_vec_q, lmb_ready_vec_q, lmb_wait_vec_q, lmb_ue_vec_q)
variable data_mask : std_logic_vector(0 to C_DATA_SIZE - 1);
variable data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
variable ready : std_logic;
variable wait_i : std_logic;
variable ue : std_logic;
begin -- process Generate_LMB_Inputs
data_read := (others => '0');
ready := '0';
wait_i := '0';
ue := '0';
for I in 0 to C_EN_WIDTH - 1 loop
data_mask := (0 to C_DATA_SIZE - 1 => mb_debug_enabled(I));
data_read := data_read or (lmb_data_read_vec_q(I) and data_mask);
ready := ready or (lmb_ready_vec_q(I) and mb_debug_enabled(I));
wait_i := wait_i or (lmb_wait_vec_q(I) and mb_debug_enabled(I));
ue := ue or (lmb_ue_vec_q(I) and mb_debug_enabled(I));
end loop;
lmb_data_read <= data_read;
lmb_ready <= ready;
lmb_wait <= wait_i;
lmb_ue <= ue;
end process Generate_LMB_Inputs;
Clock_LMB_Inputs : process (M_AXI_ACLK)
begin
if M_AXI_ACLK'event and M_AXI_ACLK = '1' then -- rising clock edge
for I in 0 to C_EN_WIDTH - 1 loop
lmb_data_read_vec_q(I) <= lmb_data_read_vec(I);
lmb_ready_vec_q(I) <= lmb_ready_vec(I);
lmb_wait_vec_q(I) <= lmb_wait_vec(I);
lmb_ue_vec_q(I) <= lmb_ue_vec(I);
end loop;
end if;
end process Clock_LMB_Inputs;
lmb_data_read_vec(0) <= LMB_Data_Read_0;
lmb_data_read_vec(1) <= LMB_Data_Read_1;
lmb_data_read_vec(2) <= LMB_Data_Read_2;
lmb_data_read_vec(3) <= LMB_Data_Read_3;
lmb_data_read_vec(4) <= LMB_Data_Read_4;
lmb_data_read_vec(5) <= LMB_Data_Read_5;
lmb_data_read_vec(6) <= LMB_Data_Read_6;
lmb_data_read_vec(7) <= LMB_Data_Read_7;
lmb_data_read_vec(8) <= LMB_Data_Read_8;
lmb_data_read_vec(9) <= LMB_Data_Read_9;
lmb_data_read_vec(10) <= LMB_Data_Read_10;
lmb_data_read_vec(11) <= LMB_Data_Read_11;
lmb_data_read_vec(12) <= LMB_Data_Read_12;
lmb_data_read_vec(13) <= LMB_Data_Read_13;
lmb_data_read_vec(14) <= LMB_Data_Read_14;
lmb_data_read_vec(15) <= LMB_Data_Read_15;
lmb_data_read_vec(16) <= LMB_Data_Read_16;
lmb_data_read_vec(17) <= LMB_Data_Read_17;
lmb_data_read_vec(18) <= LMB_Data_Read_18;
lmb_data_read_vec(19) <= LMB_Data_Read_19;
lmb_data_read_vec(20) <= LMB_Data_Read_20;
lmb_data_read_vec(21) <= LMB_Data_Read_21;
lmb_data_read_vec(22) <= LMB_Data_Read_22;
lmb_data_read_vec(23) <= LMB_Data_Read_23;
lmb_data_read_vec(24) <= LMB_Data_Read_24;
lmb_data_read_vec(25) <= LMB_Data_Read_25;
lmb_data_read_vec(26) <= LMB_Data_Read_26;
lmb_data_read_vec(27) <= LMB_Data_Read_27;
lmb_data_read_vec(28) <= LMB_Data_Read_28;
lmb_data_read_vec(29) <= LMB_Data_Read_29;
lmb_data_read_vec(30) <= LMB_Data_Read_30;
lmb_data_read_vec(31) <= LMB_Data_Read_31;
lmb_ready_vec(0) <= LMB_Ready_0;
lmb_ready_vec(1) <= LMB_Ready_1;
lmb_ready_vec(2) <= LMB_Ready_2;
lmb_ready_vec(3) <= LMB_Ready_3;
lmb_ready_vec(4) <= LMB_Ready_4;
lmb_ready_vec(5) <= LMB_Ready_5;
lmb_ready_vec(6) <= LMB_Ready_6;
lmb_ready_vec(7) <= LMB_Ready_7;
lmb_ready_vec(8) <= LMB_Ready_8;
lmb_ready_vec(9) <= LMB_Ready_9;
lmb_ready_vec(10) <= LMB_Ready_10;
lmb_ready_vec(11) <= LMB_Ready_11;
lmb_ready_vec(12) <= LMB_Ready_12;
lmb_ready_vec(13) <= LMB_Ready_13;
lmb_ready_vec(14) <= LMB_Ready_14;
lmb_ready_vec(15) <= LMB_Ready_15;
lmb_ready_vec(16) <= LMB_Ready_16;
lmb_ready_vec(17) <= LMB_Ready_17;
lmb_ready_vec(18) <= LMB_Ready_18;
lmb_ready_vec(19) <= LMB_Ready_19;
lmb_ready_vec(20) <= LMB_Ready_20;
lmb_ready_vec(21) <= LMB_Ready_21;
lmb_ready_vec(22) <= LMB_Ready_22;
lmb_ready_vec(23) <= LMB_Ready_23;
lmb_ready_vec(24) <= LMB_Ready_24;
lmb_ready_vec(25) <= LMB_Ready_25;
lmb_ready_vec(26) <= LMB_Ready_26;
lmb_ready_vec(27) <= LMB_Ready_27;
lmb_ready_vec(28) <= LMB_Ready_28;
lmb_ready_vec(29) <= LMB_Ready_29;
lmb_ready_vec(30) <= LMB_Ready_30;
lmb_ready_vec(31) <= LMB_Ready_31;
lmb_wait_vec(0) <= LMB_Wait_0;
lmb_wait_vec(1) <= LMB_Wait_1;
lmb_wait_vec(2) <= LMB_Wait_2;
lmb_wait_vec(3) <= LMB_Wait_3;
lmb_wait_vec(4) <= LMB_Wait_4;
lmb_wait_vec(5) <= LMB_Wait_5;
lmb_wait_vec(6) <= LMB_Wait_6;
lmb_wait_vec(7) <= LMB_Wait_7;
lmb_wait_vec(8) <= LMB_Wait_8;
lmb_wait_vec(9) <= LMB_Wait_9;
lmb_wait_vec(10) <= LMB_Wait_10;
lmb_wait_vec(11) <= LMB_Wait_11;
lmb_wait_vec(12) <= LMB_Wait_12;
lmb_wait_vec(13) <= LMB_Wait_13;
lmb_wait_vec(14) <= LMB_Wait_14;
lmb_wait_vec(15) <= LMB_Wait_15;
lmb_wait_vec(16) <= LMB_Wait_16;
lmb_wait_vec(17) <= LMB_Wait_17;
lmb_wait_vec(18) <= LMB_Wait_18;
lmb_wait_vec(19) <= LMB_Wait_19;
lmb_wait_vec(20) <= LMB_Wait_20;
lmb_wait_vec(21) <= LMB_Wait_21;
lmb_wait_vec(22) <= LMB_Wait_22;
lmb_wait_vec(23) <= LMB_Wait_23;
lmb_wait_vec(24) <= LMB_Wait_24;
lmb_wait_vec(25) <= LMB_Wait_25;
lmb_wait_vec(26) <= LMB_Wait_26;
lmb_wait_vec(27) <= LMB_Wait_27;
lmb_wait_vec(28) <= LMB_Wait_28;
lmb_wait_vec(29) <= LMB_Wait_29;
lmb_wait_vec(30) <= LMB_Wait_30;
lmb_wait_vec(31) <= LMB_Wait_31;
lmb_ue_vec(0) <= LMB_UE_0;
lmb_ue_vec(1) <= LMB_UE_1;
lmb_ue_vec(2) <= LMB_UE_2;
lmb_ue_vec(3) <= LMB_UE_3;
lmb_ue_vec(4) <= LMB_UE_4;
lmb_ue_vec(5) <= LMB_UE_5;
lmb_ue_vec(6) <= LMB_UE_6;
lmb_ue_vec(7) <= LMB_UE_7;
lmb_ue_vec(8) <= LMB_UE_8;
lmb_ue_vec(9) <= LMB_UE_9;
lmb_ue_vec(10) <= LMB_UE_10;
lmb_ue_vec(11) <= LMB_UE_11;
lmb_ue_vec(12) <= LMB_UE_12;
lmb_ue_vec(13) <= LMB_UE_13;
lmb_ue_vec(14) <= LMB_UE_14;
lmb_ue_vec(15) <= LMB_UE_15;
lmb_ue_vec(16) <= LMB_UE_16;
lmb_ue_vec(17) <= LMB_UE_17;
lmb_ue_vec(18) <= LMB_UE_18;
lmb_ue_vec(19) <= LMB_UE_19;
lmb_ue_vec(20) <= LMB_UE_20;
lmb_ue_vec(21) <= LMB_UE_21;
lmb_ue_vec(22) <= LMB_UE_22;
lmb_ue_vec(23) <= LMB_UE_23;
lmb_ue_vec(24) <= LMB_UE_24;
lmb_ue_vec(25) <= LMB_UE_25;
lmb_ue_vec(26) <= LMB_UE_26;
lmb_ue_vec(27) <= LMB_UE_27;
lmb_ue_vec(28) <= LMB_UE_28;
lmb_ue_vec(29) <= LMB_UE_29;
lmb_ue_vec(30) <= LMB_UE_30;
lmb_ue_vec(31) <= LMB_UE_31;
end generate Use_Bus_MASTER;
Use_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and C_TRACE_AXI_MASTER) generate
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => false,
C_HAS_DIRECT_PORT => true
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => open,
LMB_Data_Read => (others => '0'),
LMB_Data_Write => open,
LMB_Addr_Strobe => open,
LMB_Read_Strobe => open,
LMB_Write_Strobe => open,
LMB_Ready => '0',
LMB_Wait => '0',
LMB_UE => '0',
LMB_Byte_Enable => open,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
end generate Use_Bus_MASTER_AXI;
No_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and not C_TRACE_AXI_MASTER) generate
begin
master_rd_idle <= '1';
master_rd_resp <= "00";
master_wr_idle <= '1';
master_wr_resp <= "00";
master_data_out <= (others => '0');
master_data_exists <= '0';
master_data_empty <= '1';
master_dwr_next <= '0';
master_dwr_done <= '0';
master_dwr_resp <= (others => '0');
M_AXI_AWID <= (others => '0');
M_AXI_AWADDR <= (others => '0');
M_AXI_AWLEN <= (others => '0');
M_AXI_AWSIZE <= (others => '0');
M_AXI_AWBURST <= (others => '0');
M_AXI_AWLOCK <= '0';
M_AXI_AWCACHE <= (others => '0');
M_AXI_AWPROT <= (others => '0');
M_AXI_AWQOS <= (others => '0');
M_AXI_AWVALID <= '0';
M_AXI_WDATA <= (others => '0');
M_AXI_WSTRB <= (others => '0');
M_AXI_WLAST <= '0';
M_AXI_WVALID <= '0';
M_AXI_BREADY <= '0';
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= (others => '0');
M_AXI_ARBURST <= (others => '0');
M_AXI_ARLOCK <= '0';
M_AXI_ARCACHE <= (others => '0');
M_AXI_ARPROT <= (others => '0');
M_AXI_ARQOS <= (others => '0');
M_AXI_ARVALID <= '0';
M_AXI_RREADY <= '0';
end generate No_Bus_MASTER_AXI;
No_Bus_MASTER_LMB : if (C_DBG_MEM_ACCESS = 0) generate
begin
LMB_Data_Addr_0 <= (others => '0');
LMB_Data_Write_0 <= (others => '0');
LMB_Addr_Strobe_0 <= '0';
LMB_Read_Strobe_0 <= '0';
LMB_Write_Strobe_0 <= '0';
LMB_Byte_Enable_0 <= (others => '0');
LMB_Data_Addr_1 <= (others => '0');
LMB_Data_Write_1 <= (others => '0');
LMB_Addr_Strobe_1 <= '0';
LMB_Read_Strobe_1 <= '0';
LMB_Write_Strobe_1 <= '0';
LMB_Byte_Enable_1 <= (others => '0');
LMB_Data_Addr_2 <= (others => '0');
LMB_Data_Write_2 <= (others => '0');
LMB_Addr_Strobe_2 <= '0';
LMB_Read_Strobe_2 <= '0';
LMB_Write_Strobe_2 <= '0';
LMB_Byte_Enable_2 <= (others => '0');
LMB_Data_Addr_3 <= (others => '0');
LMB_Data_Write_3 <= (others => '0');
LMB_Addr_Strobe_3 <= '0';
LMB_Read_Strobe_3 <= '0';
LMB_Write_Strobe_3 <= '0';
LMB_Byte_Enable_3 <= (others => '0');
LMB_Data_Addr_4 <= (others => '0');
LMB_Data_Write_4 <= (others => '0');
LMB_Addr_Strobe_4 <= '0';
LMB_Read_Strobe_4 <= '0';
LMB_Write_Strobe_4 <= '0';
LMB_Byte_Enable_4 <= (others => '0');
LMB_Data_Addr_5 <= (others => '0');
LMB_Data_Write_5 <= (others => '0');
LMB_Addr_Strobe_5 <= '0';
LMB_Read_Strobe_5 <= '0';
LMB_Write_Strobe_5 <= '0';
LMB_Byte_Enable_5 <= (others => '0');
LMB_Data_Addr_6 <= (others => '0');
LMB_Data_Write_6 <= (others => '0');
LMB_Addr_Strobe_6 <= '0';
LMB_Read_Strobe_6 <= '0';
LMB_Write_Strobe_6 <= '0';
LMB_Byte_Enable_6 <= (others => '0');
LMB_Data_Addr_7 <= (others => '0');
LMB_Data_Write_7 <= (others => '0');
LMB_Addr_Strobe_7 <= '0';
LMB_Read_Strobe_7 <= '0';
LMB_Write_Strobe_7 <= '0';
LMB_Byte_Enable_7 <= (others => '0');
LMB_Data_Addr_8 <= (others => '0');
LMB_Data_Write_8 <= (others => '0');
LMB_Addr_Strobe_8 <= '0';
LMB_Read_Strobe_8 <= '0';
LMB_Write_Strobe_8 <= '0';
LMB_Byte_Enable_8 <= (others => '0');
LMB_Data_Addr_9 <= (others => '0');
LMB_Data_Write_9 <= (others => '0');
LMB_Addr_Strobe_9 <= '0';
LMB_Read_Strobe_9 <= '0';
LMB_Write_Strobe_9 <= '0';
LMB_Byte_Enable_9 <= (others => '0');
LMB_Data_Addr_10 <= (others => '0');
LMB_Data_Write_10 <= (others => '0');
LMB_Addr_Strobe_10 <= '0';
LMB_Read_Strobe_10 <= '0';
LMB_Write_Strobe_10 <= '0';
LMB_Byte_Enable_10 <= (others => '0');
LMB_Data_Addr_11 <= (others => '0');
LMB_Data_Write_11 <= (others => '0');
LMB_Addr_Strobe_11 <= '0';
LMB_Read_Strobe_11 <= '0';
LMB_Write_Strobe_11 <= '0';
LMB_Byte_Enable_11 <= (others => '0');
LMB_Data_Addr_12 <= (others => '0');
LMB_Data_Write_12 <= (others => '0');
LMB_Addr_Strobe_12 <= '0';
LMB_Read_Strobe_12 <= '0';
LMB_Write_Strobe_12 <= '0';
LMB_Byte_Enable_12 <= (others => '0');
LMB_Data_Addr_13 <= (others => '0');
LMB_Data_Write_13 <= (others => '0');
LMB_Addr_Strobe_13 <= '0';
LMB_Read_Strobe_13 <= '0';
LMB_Write_Strobe_13 <= '0';
LMB_Byte_Enable_13 <= (others => '0');
LMB_Data_Addr_14 <= (others => '0');
LMB_Data_Write_14 <= (others => '0');
LMB_Addr_Strobe_14 <= '0';
LMB_Read_Strobe_14 <= '0';
LMB_Write_Strobe_14 <= '0';
LMB_Byte_Enable_14 <= (others => '0');
LMB_Data_Addr_15 <= (others => '0');
LMB_Data_Write_15 <= (others => '0');
LMB_Addr_Strobe_15 <= '0';
LMB_Read_Strobe_15 <= '0';
LMB_Write_Strobe_15 <= '0';
LMB_Byte_Enable_15 <= (others => '0');
LMB_Data_Addr_16 <= (others => '0');
LMB_Data_Write_16 <= (others => '0');
LMB_Addr_Strobe_16 <= '0';
LMB_Read_Strobe_16 <= '0';
LMB_Write_Strobe_16 <= '0';
LMB_Byte_Enable_16 <= (others => '0');
LMB_Data_Addr_17 <= (others => '0');
LMB_Data_Write_17 <= (others => '0');
LMB_Addr_Strobe_17 <= '0';
LMB_Read_Strobe_17 <= '0';
LMB_Write_Strobe_17 <= '0';
LMB_Byte_Enable_17 <= (others => '0');
LMB_Data_Addr_18 <= (others => '0');
LMB_Data_Write_18 <= (others => '0');
LMB_Addr_Strobe_18 <= '0';
LMB_Read_Strobe_18 <= '0';
LMB_Write_Strobe_18 <= '0';
LMB_Byte_Enable_18 <= (others => '0');
LMB_Data_Addr_19 <= (others => '0');
LMB_Data_Write_19 <= (others => '0');
LMB_Addr_Strobe_19 <= '0';
LMB_Read_Strobe_19 <= '0';
LMB_Write_Strobe_19 <= '0';
LMB_Byte_Enable_19 <= (others => '0');
LMB_Data_Addr_20 <= (others => '0');
LMB_Data_Write_20 <= (others => '0');
LMB_Addr_Strobe_20 <= '0';
LMB_Read_Strobe_20 <= '0';
LMB_Write_Strobe_20 <= '0';
LMB_Byte_Enable_20 <= (others => '0');
LMB_Data_Addr_21 <= (others => '0');
LMB_Data_Write_21 <= (others => '0');
LMB_Addr_Strobe_21 <= '0';
LMB_Read_Strobe_21 <= '0';
LMB_Write_Strobe_21 <= '0';
LMB_Byte_Enable_21 <= (others => '0');
LMB_Data_Addr_22 <= (others => '0');
LMB_Data_Write_22 <= (others => '0');
LMB_Addr_Strobe_22 <= '0';
LMB_Read_Strobe_22 <= '0';
LMB_Write_Strobe_22 <= '0';
LMB_Byte_Enable_22 <= (others => '0');
LMB_Data_Addr_23 <= (others => '0');
LMB_Data_Write_23 <= (others => '0');
LMB_Addr_Strobe_23 <= '0';
LMB_Read_Strobe_23 <= '0';
LMB_Write_Strobe_23 <= '0';
LMB_Byte_Enable_23 <= (others => '0');
LMB_Data_Addr_24 <= (others => '0');
LMB_Data_Write_24 <= (others => '0');
LMB_Addr_Strobe_24 <= '0';
LMB_Read_Strobe_24 <= '0';
LMB_Write_Strobe_24 <= '0';
LMB_Byte_Enable_24 <= (others => '0');
LMB_Data_Addr_25 <= (others => '0');
LMB_Data_Write_25 <= (others => '0');
LMB_Addr_Strobe_25 <= '0';
LMB_Read_Strobe_25 <= '0';
LMB_Write_Strobe_25 <= '0';
LMB_Byte_Enable_25 <= (others => '0');
LMB_Data_Addr_26 <= (others => '0');
LMB_Data_Write_26 <= (others => '0');
LMB_Addr_Strobe_26 <= '0';
LMB_Read_Strobe_26 <= '0';
LMB_Write_Strobe_26 <= '0';
LMB_Byte_Enable_26 <= (others => '0');
LMB_Data_Addr_27 <= (others => '0');
LMB_Data_Write_27 <= (others => '0');
LMB_Addr_Strobe_27 <= '0';
LMB_Read_Strobe_27 <= '0';
LMB_Write_Strobe_27 <= '0';
LMB_Byte_Enable_27 <= (others => '0');
LMB_Data_Addr_28 <= (others => '0');
LMB_Data_Write_28 <= (others => '0');
LMB_Addr_Strobe_28 <= '0';
LMB_Read_Strobe_28 <= '0';
LMB_Write_Strobe_28 <= '0';
LMB_Byte_Enable_28 <= (others => '0');
LMB_Data_Addr_29 <= (others => '0');
LMB_Data_Write_29 <= (others => '0');
LMB_Addr_Strobe_29 <= '0';
LMB_Read_Strobe_29 <= '0';
LMB_Write_Strobe_29 <= '0';
LMB_Byte_Enable_29 <= (others => '0');
LMB_Data_Addr_30 <= (others => '0');
LMB_Data_Write_30 <= (others => '0');
LMB_Addr_Strobe_30 <= '0';
LMB_Read_Strobe_30 <= '0';
LMB_Write_Strobe_30 <= '0';
LMB_Byte_Enable_30 <= (others => '0');
LMB_Data_Addr_31 <= (others => '0');
LMB_Data_Write_31 <= (others => '0');
LMB_Addr_Strobe_31 <= '0';
LMB_Read_Strobe_31 <= '0';
LMB_Write_Strobe_31 <= '0';
LMB_Byte_Enable_31 <= (others => '0');
end generate No_Bus_MASTER_LMB;
Use_AXI_IPIF : if (C_USE_UART = 1) or (C_DBG_REG_ACCESS = 1) generate
begin
-- ip2bus_data assignment - as core may use less than 32 bits
ip2bus_data(C_S_AXI_DATA_WIDTH-1 downto C_REG_DATA_WIDTH) <= (others => '0');
---------------------------------------------------------------------------
-- AXI lite IPIF
---------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map (
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end generate Use_AXI_IPIF;
No_AXI_IPIF : if (C_USE_UART = 0) and (C_DBG_REG_ACCESS = 0) generate
begin
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
S_AXI_BRESP <= (others => '0');
S_AXI_BVALID <= '0';
S_AXI_ARREADY <= '0';
S_AXI_RDATA <= (others => '0');
S_AXI_RRESP <= (others => '0');
S_AXI_RVALID <= '0';
bus2ip_clk <= '0';
bus2ip_resetn <= '0';
bus2ip_data <= (others => '0');
bus2ip_rdce <= (others => '0');
bus2ip_wrce <= (others => '0');
bus2ip_cs <= (others => '0');
end generate No_AXI_IPIF;
end architecture IMP;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/tx_intrfce.vhd | 4 | 13100 | -------------------------------------------------------------------------------
-- tx_intrfce - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : tx_intrfce.vhd
-- Version : v2.0
-- Description : This is the ethernet transmit interface.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
library lib_cdc_v1_0;
library lib_fifo_v1_0;
--library fifo_generator_v11_0; --FIFO Hier
--use fifo_generator_v11_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Phy_tx_clk -- PHY TX Clock
-- Emac_tx_wr_data -- Ethernet transmit data
-- Tx_er -- Transmit error
-- Phy_tx_en -- Ethernet transmit enable
-- Tx_en -- Transmit enable
-- Emac_tx_wr -- TX FIFO write enable
-- Fifo_empty -- TX FIFO empty
-- Fifo_almost_emp -- TX FIFP almost empty
-- Fifo_full -- TX FIFO full
-- Phy_tx_data -- Ethernet transmit data
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity tx_intrfce is
generic
(
C_FAMILY : string := "virtex6"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
Phy_tx_clk : in std_logic;
Emac_tx_wr_data : in std_logic_vector (0 to 3);
Tx_er : in std_logic;
PhyTxEn : in std_logic;
Tx_en : in std_logic;
Emac_tx_wr : in std_logic;
Fifo_empty : out std_logic;
Fifo_full : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 5)
);
end tx_intrfce;
architecture implementation of tx_intrfce is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal bus_combo : std_logic_vector (0 to 5);
signal fifo_empty_i : std_logic;
signal fifo_empty_c : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
-------------------------------------------------------------------------------
component FDR
port
(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
--FIFO HIER
--component async_fifo_eth
-- port (
-- rst : in std_logic;
-- wr_clk : in std_logic;
-- rd_clk : in std_logic;
-- din : in std_logic_vector(5 downto 0);
-- wr_en : in std_logic;
-- rd_en : in std_logic;
-- dout : out std_logic_vector(5 downto 0);
-- full : out std_logic;
-- empty : out std_logic;
-- valid : out std_logic
-- );
--end component;
begin
I_TX_FIFO: entity lib_fifo_v1_0.async_fifo_fg
generic map(
C_ALLOW_2N_DEPTH => 0, -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY, -- new for FIFO Gen
C_DATA_WIDTH => 6,
C_ENABLE_RLOCS => 0, -- not supported in FG
C_FIFO_DEPTH => 15,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => 2,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => 0, -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => 2,
C_WR_ERR_LOW => 0
)
port map(
Din => bus_combo,
Wr_en => Emac_tx_wr,
Wr_clk => Clk,
Rd_en => Tx_en,
Rd_clk => Phy_tx_clk,
Ainit => Rst,
Dout => Phy_tx_data,
Full => Fifo_full,
Empty => fifo_empty_i,
Almost_full => open,
Almost_empty => open,
Wr_count => open,
Rd_count => open,
Rd_ack => open,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
-- I_TX_FIFO : async_fifo_eth
-- port map(
-- din => bus_combo,
-- wr_en => Emac_tx_wr,
-- wr_clk => Clk,
-- rd_en => Tx_en,
-- rd_clk => Phy_tx_clk,
-- rst => Rst,
-- dout => Phy_tx_data,
-- full => Fifo_full,
-- empty => fifo_empty_i,
-- valid => open
-- );
pipeIt: FDR
port map
(
Q => Fifo_empty, --[out]
C => Clk, --[in]
D => fifo_empty_c, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- CDC module for syncing tx_en_i in fifo_empty domain
----------------------------------------------------------------------------
CDC_FIFO_EMPTY: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 3
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => fifo_empty_i,
prmry_ack => open,
scndry_out => fifo_empty_c,
scndry_aclk => Clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
bus_combo <= (Emac_tx_wr_data & Tx_er & PhyTxEn);
end implementation;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_lmb_bram_0/synth/design_1_lmb_bram_0.vhd | 2 | 15379 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY design_1_lmb_bram_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_lmb_bram_0;
ARCHITECTURE design_1_lmb_bram_0_arch OF design_1_lmb_bram_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_lmb_bram_0_arch : ARCHITECTURE IS "design_1_lmb_bram_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "design_1_lmb_bram_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=design_1_lmb_bram_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=8192,C_READ_DEPTH_A=8192,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=8192,C_READ_DEPTH_B=8192,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 20.388 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "design_1_lmb_bram_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 8192,
C_READ_DEPTH_A => 8192,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 8192,
C_READ_DEPTH_B => 8192,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 20.388 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END design_1_lmb_bram_0_arch;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/axi_emc_address_decode.vhd | 4 | 20642 | -------------------------------------------------------------------------------
-- emc_emc_address_decoder - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: emc_emc_address_decoder.vhd
-- Version: v2.0
-- Description: This is the address decoder logic file for axi emc core.
-------------------------------------------------------------------------------
-- Structure:
-- axi_emc.vhd
-- -- axi_emc_native_interface.vhd
-- -- axi_emc_addr_gen.vhd
-- -- axi_emc_address_decode.vhd
-- -- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: SK
--
-- History:
-- SK 10/02/10 --
-- ^^^^^^
-- -- Created the new version v1.01.a
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_misc.or_reduce;
library axi_emc_v3_0;
use axi_emc_v3_0.all;
use axi_emc_v3_0.emc_pkg.all;
entity axi_emc_address_decode is
generic(
C_S_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_ADDR_DECODE_BITS : integer;
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_0FFF", -- IP user0 high address
X"0000_0000_1000_1000", -- IP user1 base address
X"0000_0000_1000_1FFF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0=> 1, -- User0 CE Number-- only 1 is allowed per addr range
1=> 1 -- User1 CE Number-- only 1 is allowed per addr range
);
C_FAMILY : string := "virtex6"
);
port(
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Enable_CS : in std_logic;
Enable_RdCE : in std_logic;
Enable_WrCE : in std_logic;
Rst_CS : in std_logic;
Rst_Wr_CE : in std_logic;
Rst_Rd_CE : in std_logic;
Addr_SM_PS_IDLE : in std_logic;
Addr_int : in std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
RNW : in std_logic;
RdFIFO_Space_two_int : in std_logic;
Bus2IP_CS : out std_logic_vector
((((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1)downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)downto 0);
ORed_cs : out std_logic
);
end entity axi_emc_address_decode;
-------------------------
---------------------------
-- architecture section starts
---------------------------
architecture imp of axi_emc_address_decode is
--------------------
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- constant declaration
-- Reset Active State
constant ACTIVE_LOW_RESET : std_logic := '0';
------------------------------------
-- local type declarations
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to(C_ADDR_DECODE_BITS-1));
----------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
----------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
--coverage off
return(slv_array);
--coverage on
end function slv64_2_slv_awidth;
----------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_ADDR_DECODE_BITS-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_ADDR_DECODE_BITS-1);
begin
addr_nor := x xor y;
for i in 0 to C_ADDR_DECODE_BITS-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_ADDR_DECODE_BITS);
--coverage on
end function Addr_Bits;
----------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
--coverage off
return(num_bits);
--coverage on
end function Get_Addr_Bits;
----------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
----------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := ce_array'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
--coverage off
return(num_addr_bits);
--coverage on
end function NEEDED_ADDR_BITS;
----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
--coverage off
return(ce_num_sum);
--coverage on
end function calc_start_ce_index;
------------------------
-- Constant Declarations
------------------------
-- convert 64 bit address array into 32 bit address array
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_ADDR_DECODE_BITS);
-- get the number of address pairs given in the ARD ADDR RANGE array
constant NUM_BASE_ADDRS : integer :=(C_ARD_ADDR_RANGE_ARRAY'length)/2;
-- 1 decode for 1 address pair from ARD ADDRESS RANGE array, by this
-- get total decode bits
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
----------------------
-- Signal Declarations
----------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal int_pselect : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal CE_reg : std_logic_vector
(0 to (NUM_CE_SIGNALS-1));
signal pselect_hit_reg : std_logic_vector
(0 to (NUM_CE_SIGNALS-1));
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_clear_int : std_logic;
signal rdce_clear_int : std_logic;
signal ored_ce_int : std_logic;
signal decode_addr_int : std_logic_vector(0 to C_ADDR_DECODE_BITS-1);
signal cs_reg : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1)
:=(others => '0');
signal cs_clear_int : std_logic;
----------------------
begin -- architecture imp
----------------------
decode_addr_int <= Addr_int((C_ADDR_DECODE_BITS-1) downto 0);
wrce_clear_int <= not(Bus2IP_Resetn) or Rst_Wr_CE or Rst_CS;
rdce_clear_int <= not(Bus2IP_Resetn) or Rst_Rd_CE or Rst_CS;
cs_clear_int <= not(Bus2IP_Resetn) or Rst_CS;
---------------------------------
-- Universal Address Decode Block
---------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
-- get the individual number of CE's
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE: Integer --range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
signal temp_avalid : std_logic;
------
begin
------
temp_avalid <= (Addr_SM_PS_IDLE and (Enable_CS));-- or S_AXI_MEM_AWVALID));
------------------------------
-- generate multiple chip selects
------------------------------
MULTI_CS_GEN : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_emc_v3_0.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_ADDR_DECODE_BITS,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => decode_addr_int, -- [in]
AValid => temp_avalid, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate MULTI_CS_GEN;
ONE_CS_GEN : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Addr_SM_PS_IDLE;
end generate ONE_CS_GEN;
--------
-- CS_REG_P:-- register Bus2IP_CS signals
--------
CS_REG_P : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Addr_SM_PS_IDLE='1')then
cs_reg(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process CS_REG_P;
--------
-- CS_OUT_P:-- register Bus2IP_CS signals
--------
CS_OUT_P : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(cs_clear_int='1')then
cs_out_i(bar_index) <= '0';
elsif((Addr_SM_PS_IDLE='1') and (Enable_CS='1'))then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process CS_OUT_P;
--------------
-- RDCE_REG_P: Register RdCE signal generation logic
--------------
RDCE_REG_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(rdce_clear_int='1') then
rdce_out_i(bar_index) <= '0';
elsif((Addr_SM_PS_IDLE='1') and
(RNW='1') and
(Enable_CS='1')
)then
rdce_out_i(bar_index) <= pselect_hit_i(bar_index);
elsif(Enable_RdCE='1')then
rdce_out_i(bar_index) <= cs_reg(bar_index);
end if;
end if;
end process RDCE_REG_P;
---------------
-- WRCE_REG_P: Register WrCE signal generation logic
---------------
WRCE_REG_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(wrce_clear_int='1') then
wrce_out_i(bar_index) <= '0';
elsif((Addr_SM_PS_IDLE='1') and
(RNW='0') and
(Enable_CS='1')
)then
wrce_out_i(bar_index) <= pselect_hit_i(bar_index);
elsif(Enable_WrCE='1')then
wrce_out_i(bar_index) <= cs_reg(bar_index);
end if;
end if;
end process WRCE_REG_P;
end generate MEM_DECODE_GEN;
-----------------------------
-- Assign registered output signals
BUS2IP_CS_GEN: for i in 0 to (NUM_BASE_ADDRS-1) generate
Bus2IP_CS(i) <= cs_out_i(i);
end generate BUS2IP_CS_GEN;
-----------------------------
BUS2IP_RDCE_GEN: for i in 0 to (NUM_BASE_ADDRS-1) generate
Bus2IP_RdCE(i) <= rdce_out_i(i) and
(not Rst_Rd_CE);-- and
-- RdFIFO_Space_two_int;
end generate BUS2IP_RDCE_GEN;
-----------------------------
BUS2IP_WRCE_GEN: for i in 0 to (NUM_BASE_ADDRS-1) generate
Bus2IP_WrCE(i) <= wrce_out_i(i);-- and not Rst_Wr_CE;
end generate BUS2IP_WRCE_GEN;
-----------------------------
ored_ce_int <= or_reduce(rdce_out_i) when (RNW='1')
else
or_reduce(wrce_out_i);
ORed_cs <= or_reduce(cs_out_i);
end architecture imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/lmb_bram_if_funcs.vhd | 4 | 8212 | -------------------------------------------------------------------------------
-- lmb_bram_if_funcs.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: lmb_bram_if_funcs.vhd
--
-- Description: Support functions for lmb_bram_if_cntlr
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_funcs.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package lmb_bram_if_funcs is
type TARGET_FAMILY_TYPE is (
-- pragma xilinx_rtl_off
VIRTEX7,
KINTEX7,
ARTIX7,
ZYNQ,
VIRTEXU,
KINTEXU,
ZYNQUE,
VIRTEXUM,
KINTEXUM,
-- pragma xilinx_rtl_on
RTL
);
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
-- Get the maximum number of inputs to a LUT.
function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer;
end package lmb_bram_if_funcs;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package body lmb_bram_if_funcs is
function LowerCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
end LowerCase_Char;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END Equal_String;
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
begin -- function String_To_Family
if ((Select_RTL) or Equal_String(S, "rtl")) then
return RTL;
elsif Equal_String(S, "virtex7") or Equal_String(S, "qvirtex7") then
return VIRTEX7;
elsif Equal_String(S, "kintex7") or Equal_String(S, "kintex7l") or
Equal_String(S, "qkintex7") or Equal_String(S, "qkintex7l") then
return KINTEX7;
elsif Equal_String(S, "artix7") or Equal_String(S, "artix7l") or Equal_String(S, "aartix7") or
Equal_String(S, "qartix7") or Equal_String(S, "qartix7l") then
return ARTIX7;
elsif Equal_String(S, "zynq") or Equal_String(S, "azynq") or Equal_String(S, "qzynq") then
return ZYNQ;
elsif Equal_String(S, "virtexu") or Equal_String(S, "qvirtexu") then
return VIRTEXU;
elsif Equal_String(S, "kintexu") or Equal_String(S, "kintexul") or
Equal_String(S, "qkintexu") or Equal_String(S, "qkintexul") then
return KINTEXU;
elsif Equal_String(S, "zynque") then
return ZYNQUE;
elsif Equal_String(S, "virtexum") then
return VIRTEXUM;
elsif Equal_String(S, "kintexum") then
return KINTEXUM;
else
-- assert (false) report "No known target family" severity failure;
return RTL;
end if;
end function String_To_Family;
function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer is
begin
return 6;
end function Family_To_LUT_Size;
end package body lmb_bram_if_funcs;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/crcnibshiftreg.vhd | 4 | 8788 | -------------------------------------------------------------------------------
-- crcnibshiftreg - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename : crcnibshiftreg.vhd
-- Version : v2.0
-- Description : CRC Nible Shift Register
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Clke -- Clock enable
-- Din -- Data in
-- Load -- Data load
-- Shift -- Data shift enable
-- Dout -- data out
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity crcnibshiftreg is
port (
Clk : in std_logic;
Rst : in std_logic;
Clken : in std_logic;
Din : in std_logic_vector(31 downto 0);
Load : in std_logic;
Shift : in std_logic;
Dout : out std_logic_vector(31 downto 0)
);
end crcnibshiftreg;
architecture implementation of crcnibshiftreg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal nibData : std_logic_vector (31 downto 0);
begin
----------------------------------------------------------------------------
-- PROCESS : SHIFTER
----------------------------------------------------------------------------
-- The process shifts the nibble data when shift is enabled.
----------------------------------------------------------------------------
SHIFTER : process (Clk)
begin --
if (Clk'event and Clk = '1') then
if Rst = '1' then
nibData <= (others => '0');
elsif (Clken = '1') then
if (Load = '1') then
nibData <= Din;
elsif (Shift = '1') then
nibData(3 downto 0) <= nibData(7 downto 4);
nibData(7 downto 4) <= nibData(11 downto 8);
nibData(11 downto 8) <= nibData(15 downto 12);
nibData(15 downto 12) <= nibData(19 downto 16);
nibData(19 downto 16) <= nibData(23 downto 20);
nibData(23 downto 20) <= nibData(27 downto 24);
nibData(27 downto 24) <= nibData(31 downto 28);
nibData(31 downto 28) <= (others => '0');
end if;
end if;
end if;
end process SHIFTER;
Dout <= nibData;
end implementation;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_intc_v4_1/e1d42edc/hdl/src/vhdl/double_synchronizer.vhd | 5 | 6181 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : double_synchronizer.vhd
-- Version : v3.0
-- Description: The double_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- RESET_2 signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
library unisim;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity double_synchronizer is
generic (
C_DWIDTH : integer range 1 to 32 := 1
);
port (
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active_low
DATA_IN : in std_logic_vector(C_DWIDTH-1 downto 0);
SYNC_DATA_OUT : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end entity;
-------------------------------------------------------------------------------
architecture RTL of double_synchronizer is
signal RESET_2_p : std_logic;
signal data_in_d1 : std_logic_vector(C_DWIDTH-1 downto 0);
-----
begin
-----
-- active high Reset
RESET_2_p <= not RESET_2_n;
REG_GEN : for i in 0 to (C_DWIDTH - 1) generate
BLOCK_GEN: block
attribute ASYNC_REG : string;
attribute ASYNC_REG of FIRST_FLOP_i : label is "TRUE";
begin
FIRST_FLOP_i: component FDR
port map (
Q => data_in_d1(i),
C => CLK_2,
D => DATA_IN(i),
R => RESET_2_p
);
SECOND_FLOP_i: component FDR
port map (
Q => SYNC_DATA_OUT(i),
C => CLK_2,
D => data_in_d1(i),
R => RESET_2_p
);
end block BLOCK_GEN;
end generate REG_GEN;
-------------------------------------------------------------------------------
end RTL;
-------------------------------------------------------------------------------
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/sequence.vhd | 30 | 22215 | -------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence;
architecture imp of sequence is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/sequence.vhd | 30 | 22215 | -------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence;
architecture imp of sequence is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/sequence.vhd | 30 | 22215 | -------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence;
architecture imp of sequence is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/counters.vhd | 4 | 18094 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: counters.vhd
-- Description: This file contains the counters for timing read/write
-- timing parameters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is same as in version v3_01_c - no change in the logic of this
-- module. Deleted the history from version v3_01_c.
-- ~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
-- ~~~~~~~~
-- ^^^^^^^^
-- KSB 08/08/08 version v4_00_a
-- 1. Added TPACC counter
-- ~~~~~~~~
-- SK 02/11/10 version v5_01_a
-- ^^^^^^^^
-- 1. Registered the IP2Bus_RdAck and IP2Bus_Data signals.
-- 2. Reduced utilization
-- ~~~~~~~~
-- SK 02/11/11 version v5_02_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library emc_common_v3_0;
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Inputs
-- Synch_mem -- Synchronous Memory Flag
-- Twr_data -- Write cycle counter data
-- Twr_load -- Write cycle counter load
-- Twr_cnt_en -- Write cycle count enable
-- Tlz_data -- Write End to Low-Z counter data
-- Tlz_load -- Write End to Low-Z counter load
-- Trd_data -- Read cycle counter data
-- Trd_load -- Read cycle counter load
-- Trd_cnt_en -- Read cycle count enable
-- Thz_data -- Read End to High-Z counter data
-- Thz_load -- Read End to High-Z counter load
--
-- Outputs
-- Twr_end -- Write cycle count complete
-- Tlz_end -- Write Recover count complete
-- Trd_end -- Read cycle count complete
-- Thz_end -- Read Recover count complete
--
-- Clock and reset
-- Clk -- System Clock
-- Rst -- System Reset
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity counters is
port (
Synch_mem : in std_logic;
Twr_data : in std_logic_vector(0 to 4);
Twr_load : in std_logic;
Twr_cnt_en : in std_logic;
Twph_data : in std_logic_vector(0 to 4);
Twph_load : in std_logic;
Twph_cnt_en : in std_logic;
Tlz_data : in std_logic_vector(0 to 4);
Tlz_load : in std_logic;
Trd_data : in std_logic_vector(0 to 4);
Trd_load : in std_logic;
Trd_cnt_en : in std_logic;
Thz_data : in std_logic_vector(0 to 4);
Thz_load : in std_logic;
Tpacc_data : in std_logic_vector(0 to 4);
Tpacc_load : in std_logic;
Tpacc_cnt_en : in std_logic;
Twr_end : out std_logic;
Tlz_end : out std_logic;
Twph_end : out std_logic;
Trd_end : out std_logic;
Thz_end : out std_logic;
Tpacc_end : out std_logic;
--
Twr_rec_data : in std_logic_vector(0 to 15);
Twr_rec_load : in std_logic;
Twr_rec_cnt_en : in std_logic;
Twr_rec_end : out std_logic;
--
Clk : in std_logic;
Rst : in std_logic
);
end entity counters;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of counters is
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assigning zero values
-------------------------------------------------------------------------------
constant ZERO_TWRCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TWPHCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TLZCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TRDCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TPACCCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_THZCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TWR_REC_CNT : std_logic_vector(0 to 9) := (others => '0');
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
signal twr_cnt : std_logic_vector(0 to 4);
signal twph_cnt : std_logic_vector(0 to 4);
signal tlz_cnt : std_logic_vector(0 to 4);
signal trd_cnt : std_logic_vector(0 to 4);
signal thz_cnt : std_logic_vector(0 to 4);
signal tpacc_cnt : std_logic_vector(0 to 4);
signal twr_rec_cnt : std_logic_vector(0 to 15);--9/6/2011
signal thz_cnt_en : std_logic;
signal tlz_cnt_en : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Write Cycle Delay Counter
-------------------------------------------------------------------------------
TWRCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => "11111",
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => twr_cnt,
LD => Twr_data,
AD => "1",
LOAD => Twr_load,
OP => Twr_cnt_en
);
-------------------------------------------------------------------------------
-- Write Cycle High Time Counter
-------------------------------------------------------------------------------
TWPHCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => ZERO_TWPHCNT,
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => twph_cnt,
LD => Twph_data,
AD => "1",
LOAD => Twph_load,
OP => Twph_cnt_en
);
-------------------------------------------------------------------------------
-- Write End to Data Low Impedance Counter
-------------------------------------------------------------------------------
tlz_cnt_en <= '0' when tlz_cnt = ZERO_TLZCNT
else '1';
TLZCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => ZERO_TLZCNT,
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => tlz_cnt,
LD => Tlz_data,
AD => "1",
LOAD => Tlz_load,
OP => tlz_cnt_en
);
-------------------------------------------------------------------------------
-- Read Cycle Delay Counter
-------------------------------------------------------------------------------
TRDCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => "11111",
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => trd_cnt,
LD => Trd_data,
AD => "1",
LOAD => Trd_load,
OP => Trd_cnt_en
);
-------------------------------------------------------------------------------
-- Page Read Cycle Delay Counter
-------------------------------------------------------------------------------
TPACCCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => "11111",
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => tpacc_cnt,
LD => Tpacc_data,
AD => "1",
LOAD => Tpacc_load,
OP => Tpacc_cnt_en
);
-------------------------------------------------------------------------------
-- Page Read Cycle Delay Counter
-------------------------------------------------------------------------------
T_WRREC_CNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 16,
C_RESET_VALUE => "1111111111111111",
C_LD_WIDTH => 16,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => twr_rec_cnt,
LD => Twr_rec_data,
AD => "1",
LOAD => Twr_rec_load,
OP => Twr_rec_cnt_en
);
-------------------------------------------------------------------------------
-- Read End to High Impedance Delay Counter
-------------------------------------------------------------------------------
thz_cnt_en <= '0' when thz_cnt = ZERO_THZCNT else
'1';
THZCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => ZERO_THZCNT,
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => thz_cnt,
LD => Thz_data,
AD => "1",
LOAD => Thz_load,
OP => thz_cnt_en
);
-------------------------------------------------------------------------------
-- Generation of Counter End Signals
-------------------------------------------------------------------------------
Twr_end <= '1' when twr_cnt = ZERO_TWRCNT or Synch_mem = '1' else
'0' ;
Twph_end <= '1' when twph_cnt = ZERO_TWPHCNT or Synch_mem = '1' else
'0' ;
Tlz_end <= '1' when tlz_cnt = ZERO_TLZCNT or Synch_mem = '1' else
'0' ;
Trd_end <= '1' when trd_cnt = ZERO_TRDCNT or Synch_mem = '1' else
'0' ;
thz_end <= '1' when thz_cnt = ZERO_THZCNT or Synch_mem = '1' else
'0' ;
Tpacc_end <= '1' when tpacc_cnt = ZERO_TPACCCNT or Synch_mem = '1' else
'0' ;
Twr_rec_end <= '1' when twr_rec_cnt = ZERO_TWR_REC_CNT or Synch_mem = '1' else
'0' ; -- 9/6/2011
end imp;
-------------------------------------------------------------------------------
-- End of File counters.vhd
-------------------------------------------------------------------------------
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/counters.vhd | 4 | 18094 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: counters.vhd
-- Description: This file contains the counters for timing read/write
-- timing parameters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is same as in version v3_01_c - no change in the logic of this
-- module. Deleted the history from version v3_01_c.
-- ~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
-- ~~~~~~~~
-- ^^^^^^^^
-- KSB 08/08/08 version v4_00_a
-- 1. Added TPACC counter
-- ~~~~~~~~
-- SK 02/11/10 version v5_01_a
-- ^^^^^^^^
-- 1. Registered the IP2Bus_RdAck and IP2Bus_Data signals.
-- 2. Reduced utilization
-- ~~~~~~~~
-- SK 02/11/11 version v5_02_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library emc_common_v3_0;
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Inputs
-- Synch_mem -- Synchronous Memory Flag
-- Twr_data -- Write cycle counter data
-- Twr_load -- Write cycle counter load
-- Twr_cnt_en -- Write cycle count enable
-- Tlz_data -- Write End to Low-Z counter data
-- Tlz_load -- Write End to Low-Z counter load
-- Trd_data -- Read cycle counter data
-- Trd_load -- Read cycle counter load
-- Trd_cnt_en -- Read cycle count enable
-- Thz_data -- Read End to High-Z counter data
-- Thz_load -- Read End to High-Z counter load
--
-- Outputs
-- Twr_end -- Write cycle count complete
-- Tlz_end -- Write Recover count complete
-- Trd_end -- Read cycle count complete
-- Thz_end -- Read Recover count complete
--
-- Clock and reset
-- Clk -- System Clock
-- Rst -- System Reset
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity counters is
port (
Synch_mem : in std_logic;
Twr_data : in std_logic_vector(0 to 4);
Twr_load : in std_logic;
Twr_cnt_en : in std_logic;
Twph_data : in std_logic_vector(0 to 4);
Twph_load : in std_logic;
Twph_cnt_en : in std_logic;
Tlz_data : in std_logic_vector(0 to 4);
Tlz_load : in std_logic;
Trd_data : in std_logic_vector(0 to 4);
Trd_load : in std_logic;
Trd_cnt_en : in std_logic;
Thz_data : in std_logic_vector(0 to 4);
Thz_load : in std_logic;
Tpacc_data : in std_logic_vector(0 to 4);
Tpacc_load : in std_logic;
Tpacc_cnt_en : in std_logic;
Twr_end : out std_logic;
Tlz_end : out std_logic;
Twph_end : out std_logic;
Trd_end : out std_logic;
Thz_end : out std_logic;
Tpacc_end : out std_logic;
--
Twr_rec_data : in std_logic_vector(0 to 15);
Twr_rec_load : in std_logic;
Twr_rec_cnt_en : in std_logic;
Twr_rec_end : out std_logic;
--
Clk : in std_logic;
Rst : in std_logic
);
end entity counters;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of counters is
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assigning zero values
-------------------------------------------------------------------------------
constant ZERO_TWRCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TWPHCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TLZCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TRDCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TPACCCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_THZCNT : std_logic_vector(0 to 4) := (others => '0');
constant ZERO_TWR_REC_CNT : std_logic_vector(0 to 9) := (others => '0');
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
signal twr_cnt : std_logic_vector(0 to 4);
signal twph_cnt : std_logic_vector(0 to 4);
signal tlz_cnt : std_logic_vector(0 to 4);
signal trd_cnt : std_logic_vector(0 to 4);
signal thz_cnt : std_logic_vector(0 to 4);
signal tpacc_cnt : std_logic_vector(0 to 4);
signal twr_rec_cnt : std_logic_vector(0 to 15);--9/6/2011
signal thz_cnt_en : std_logic;
signal tlz_cnt_en : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Write Cycle Delay Counter
-------------------------------------------------------------------------------
TWRCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => "11111",
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => twr_cnt,
LD => Twr_data,
AD => "1",
LOAD => Twr_load,
OP => Twr_cnt_en
);
-------------------------------------------------------------------------------
-- Write Cycle High Time Counter
-------------------------------------------------------------------------------
TWPHCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => ZERO_TWPHCNT,
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => twph_cnt,
LD => Twph_data,
AD => "1",
LOAD => Twph_load,
OP => Twph_cnt_en
);
-------------------------------------------------------------------------------
-- Write End to Data Low Impedance Counter
-------------------------------------------------------------------------------
tlz_cnt_en <= '0' when tlz_cnt = ZERO_TLZCNT
else '1';
TLZCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => ZERO_TLZCNT,
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => tlz_cnt,
LD => Tlz_data,
AD => "1",
LOAD => Tlz_load,
OP => tlz_cnt_en
);
-------------------------------------------------------------------------------
-- Read Cycle Delay Counter
-------------------------------------------------------------------------------
TRDCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => "11111",
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => trd_cnt,
LD => Trd_data,
AD => "1",
LOAD => Trd_load,
OP => Trd_cnt_en
);
-------------------------------------------------------------------------------
-- Page Read Cycle Delay Counter
-------------------------------------------------------------------------------
TPACCCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => "11111",
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => tpacc_cnt,
LD => Tpacc_data,
AD => "1",
LOAD => Tpacc_load,
OP => Tpacc_cnt_en
);
-------------------------------------------------------------------------------
-- Page Read Cycle Delay Counter
-------------------------------------------------------------------------------
T_WRREC_CNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 16,
C_RESET_VALUE => "1111111111111111",
C_LD_WIDTH => 16,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => twr_rec_cnt,
LD => Twr_rec_data,
AD => "1",
LOAD => Twr_rec_load,
OP => Twr_rec_cnt_en
);
-------------------------------------------------------------------------------
-- Read End to High Impedance Delay Counter
-------------------------------------------------------------------------------
thz_cnt_en <= '0' when thz_cnt = ZERO_THZCNT else
'1';
THZCNT_I: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => 5,
C_RESET_VALUE => ZERO_THZCNT,
C_LD_WIDTH => 5,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Clk,
RST => Rst,
Q => thz_cnt,
LD => Thz_data,
AD => "1",
LOAD => Thz_load,
OP => thz_cnt_en
);
-------------------------------------------------------------------------------
-- Generation of Counter End Signals
-------------------------------------------------------------------------------
Twr_end <= '1' when twr_cnt = ZERO_TWRCNT or Synch_mem = '1' else
'0' ;
Twph_end <= '1' when twph_cnt = ZERO_TWPHCNT or Synch_mem = '1' else
'0' ;
Tlz_end <= '1' when tlz_cnt = ZERO_TLZCNT or Synch_mem = '1' else
'0' ;
Trd_end <= '1' when trd_cnt = ZERO_TRDCNT or Synch_mem = '1' else
'0' ;
thz_end <= '1' when thz_cnt = ZERO_THZCNT or Synch_mem = '1' else
'0' ;
Tpacc_end <= '1' when tpacc_cnt = ZERO_TPACCCNT or Synch_mem = '1' else
'0' ;
Twr_rec_end <= '1' when twr_rec_cnt = ZERO_TWR_REC_CNT or Synch_mem = '1' else
'0' ; -- 9/6/2011
end imp;
-------------------------------------------------------------------------------
-- End of File counters.vhd
-------------------------------------------------------------------------------
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/876b8fe4/hdl/src/vhdl/axi_lite_ipif.vhd | 16 | 14520 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v2.0
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/parity.vhd | 4 | 10694 | -------------------------------------------------------------------------------
-- parity.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity Parity is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
architecture IMP of Parity is
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
component MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF7;
component MB_MUXF8 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF8;
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_FPGA : if (C_TARGET /= RTL) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MB_MUXF8
generic map(
C_TARGET => C_TARGET)
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
Res <= ParityGen(InA);
end generate Using_RTL;
end architecture IMP;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/xor18.vhd | 4 | 7111 | -------------------------------------------------------------------------------
-- xor18.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: xor18.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- xor18.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity XOR18 is
generic (
C_TARGET : TARGET_FAMILY_TYPE);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end entity XOR18;
architecture IMP of XOR18 is
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
component MB_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component MB_XORCY;
begin -- architecture IMP
Using_FPGA: if ( C_TARGET /= RTL ) generate
signal xor6_1 : std_logic;
signal xor6_2 : std_logic;
signal xor6_3 : std_logic;
signal xor18_c1 : std_logic;
signal xor18_c2 : std_logic;
begin -- generate Using_LUT6
XOR6_1_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => xor6_1,
I0 => InA(17),
I1 => InA(16),
I2 => InA(15),
I3 => InA(14),
I4 => InA(13),
I5 => InA(12));
XOR_1st_MUXCY : MB_MUXCY
generic map(
C_TARGET => C_TARGET)
port map (
DI => '1',
CI => '0',
S => xor6_1,
LO => xor18_c1);
XOR6_2_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => xor6_2,
I0 => InA(11),
I1 => InA(10),
I2 => InA(9),
I3 => InA(8),
I4 => InA(7),
I5 => InA(6));
XOR_2nd_MUXCY : MB_MUXCY
generic map(
C_TARGET => C_TARGET)
port map (
DI => xor6_1,
CI => xor18_c1,
S => xor6_2,
LO => xor18_c2);
XOR6_3_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => xor6_3,
I0 => InA(5),
I1 => InA(4),
I2 => InA(3),
I3 => InA(2),
I4 => InA(1),
I5 => InA(0));
XOR18_XORCY : MB_XORCY
generic map(
C_TARGET => C_TARGET)
port map (
LI => xor6_3,
CI => xor18_c2,
O => res);
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
res <= InA(17) xor InA(16) xor InA(15) xor InA(14) xor InA(13) xor InA(12) xor
InA(11) xor InA(10) xor InA(9) xor InA(8) xor InA(7) xor InA(6) xor
InA(5) xor InA(4) xor InA(3) xor InA(2) xor InA(1) xor InA(0);
end generate Using_RTL;
end architecture IMP;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/synth/design_1_rst_clk_wiz_1_100M_0.vhd | 2 | 6714 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY design_1_rst_clk_wiz_1_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_clk_wiz_1_100M_0;
ARCHITECTURE design_1_rst_clk_wiz_1_100M_0_arch OF design_1_rst_clk_wiz_1_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_clk_wiz_1_100M_0_arch : ARCHITECTURE IS "design_1_rst_clk_wiz_1_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "design_1_rst_clk_wiz_1_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_clk_wiz_1_100M_0_arch;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/a3d1bdff/hdl/src/vhdl/uartlite_tx.vhd | 6 | 22859 | -------------------------------------------------------------------------------
-- uartlite_tx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_tx.vhd
-- Version: v2.0
-- Description: UART Lite Transmit Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.UNSIGNED;
use IEEE.numeric_std.to_unsigned;
use IEEE.numeric_std."-";
library lib_srl_fifo_v1_0;
-- dynshreg_i_f refered from proc_common_v4_00_a
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.all;
-- srl_fifo_f refered from proc_common_v4_00_a
use lib_srl_fifo_v1_0.srl_fifo_f;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- TX -- Transmit Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Write_TX_FIFO -- Write transmit FIFO
-- Reset_TX_FIFO -- Reset transmit FIFO
-- TX_Data -- Transmit data input
-- TX_Buffer_Full -- Transmit buffer full
-- TX_Buffer_Empty -- Transmit buffer empty
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_tx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
TX : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_DATA_BITS-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic
);
end entity uartlite_tx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_tx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
-------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------
constant MUX_SEL_INIT : std_logic_vector(0 to 2) :=
std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
-------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------
signal parity : std_logic;
signal tx_Run1 : std_logic;
signal select_Parity : std_logic;
signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
signal div16 : std_logic;
signal tx_Data_Enable : std_logic;
signal tx_Start : std_logic;
signal tx_DataBits : std_logic;
signal tx_Run : std_logic;
signal mux_sel : std_logic_vector(0 to 2);
signal mux_sel_is_zero : std_logic;
signal mux_01 : std_logic;
signal mux_23 : std_logic;
signal mux_45 : std_logic;
signal mux_67 : std_logic;
signal mux_0123 : std_logic;
signal mux_4567 : std_logic;
signal mux_Out : std_logic;
signal serial_Data : std_logic;
signal fifo_Read : std_logic;
signal fifo_Data_Present : std_logic := '0';
signal fifo_Data_Empty : std_logic;
signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1);
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal tx_buffer_full_i : std_logic;
signal TX_FIFO_Reset : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
--MID_START_BIT_SRL16_I : Shift register is used to generate div16 that
-- gets shifted for 16 times(as Addr = 15) when
-- EN_16x_Baud is high.
---------------------------------------------------------------------------
MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_INIT_VALUE => X"8000",
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => div16,
Dout(0) => div16
);
------------------------------------------------------------------------
-- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and
-- EN_16x_Baud is 1. It will deasserted in the
-- next clock cycle.
------------------------------------------------------------------------
TX_DATA_ENABLE_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Data_Enable <= '0';
else
if (tx_Data_Enable = '1') then
tx_Data_Enable <= '0';
elsif (EN_16x_Baud = '1') then
tx_Data_Enable <= div16;
end if;
end if;
end if;
end process TX_DATA_ENABLE_DFF;
------------------------------------------------------------------------
-- TX_START_DFF : tx_start is '1' for the start bit in a transmission
------------------------------------------------------------------------
TX_START_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Start <= '0';
else
tx_Start <= (not(tx_Run) and (tx_Start or
(fifo_Data_Present and tx_Data_Enable)));
end if;
end if;
end process TX_START_DFF;
--------------------------------------------------------------------------
-- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission
--------------------------------------------------------------------------
TX_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_DataBits <= '0';
else
tx_DataBits <= (not(fifo_Read) and (tx_DataBits or
(tx_Start and tx_Data_Enable)));
end if;
end if;
end process TX_DATA_DFF;
-------------------------------------------------------------------------
-- COUNTER : If mux_sel is zero then reload with the init value else if
-- tx_DataBits = '1', decrement
-------------------------------------------------------------------------
COUNTER : process (Clk) is
begin -- process Mux_Addr_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1,
mux_sel'length));
elsif (tx_Data_Enable = '1') then
if (mux_sel_is_zero = '1') then
mux_sel <= MUX_SEL_INIT;
elsif (tx_DataBits = '1') then
mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1);
end if;
end if;
end if;
end process COUNTER;
------------------------------------------------------------------------
-- Detecting when mux_sel is zero, i.e. all data bits are transfered
------------------------------------------------------------------------
mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
--------------------------------------------------------------------------
-- FIFO_READ_DFF : Read out the next data from the transmit fifo when the
-- data has been transmitted
--------------------------------------------------------------------------
FIFO_READ_DFF : process (Clk) is
begin -- process FIFO_Read_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Read <= '0';
else
fifo_Read <= tx_Data_Enable and mux_sel_is_zero;
end if;
end if;
end process FIFO_READ_DFF;
--------------------------------------------------------------------------
-- Select which bit within the data word to transmit
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- PARITY_BIT_INSERTION : Need special treatment for inserting the parity
-- bit because of parity generation
--------------------------------------------------------------------------
data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2);
data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else
fifo_DOut(C_DATA_BITS-1);
mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else
data_to_transfer(0);
mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else
data_to_transfer(2);
--------------------------------------------------------------------------
-- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5
--------------------------------------------------------------------------
DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate
mux_45 <= data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_5;
--------------------------------------------------------------------------
-- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6
--------------------------------------------------------------------------
DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_6;
--------------------------------------------------------------------------
-- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7
--------------------------------------------------------------------------
DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(6);
end generate DATA_BITS_IS_7;
--------------------------------------------------------------------------
-- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8
--------------------------------------------------------------------------
DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else
data_to_transfer(6);
end generate DATA_BITS_IS_8;
mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01;
mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45;
mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123;
--------------------------------------------------------------------------
-- SERIAL_DATA_DFF : Register the mux_Out
--------------------------------------------------------------------------
SERIAL_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
serial_Data <= '0';
else
serial_Data <= mux_Out;
end if;
end if;
end process SERIAL_DATA_DFF;
--------------------------------------------------------------------------
-- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit
-- Force a '1' when tx_run is '0', Idle
-- otherwise put out the serial_data
--------------------------------------------------------------------------
SERIAL_OUT_DFF : process (Clk) is
begin -- process Serial_Out_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
TX <= '1';
else
TX <= (not(tx_Run) or serial_Data) and (not(tx_Start));
end if;
end if;
end process SERIAL_OUT_DFF;
--------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
--------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (tx_Start = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (tx_Data_Enable = '1') then
parity <= parity xor serial_Data;
end if;
end if;
end process PARITY_DFF;
TX_RUN1_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Run1 <= '0';
elsif (tx_Data_Enable = '1') then
tx_Run1 <= tx_DataBits;
end if;
end if;
end process TX_RUN1_DFF;
tx_Run <= tx_Run1 or tx_DataBits;
SELECT_PARITY_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
select_Parity <= '0';
elsif (tx_Data_Enable = '1') then
select_Parity <= mux_sel_is_zero;
end if;
end if;
end process SELECT_PARITY_DFF;
end generate USING_PARITY;
--------------------------------------------------------------------------
-- NO_PARITY : When C_USE_PARITY = 0 select parity as '0'
--------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
tx_Run <= tx_DataBits;
select_Parity <= '0';
end generate NO_PARITY;
--------------------------------------------------------------------------
-- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO
--------------------------------------------------------------------------
fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i);
--------------------------------------------------------------------------
-- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO
--------------------------------------------------------------------------
fifo_rd <= fifo_Read and (not fifo_Data_Empty);
--------------------------------------------------------------------------
-- Reset TX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
TX_FIFO_Reset <= Reset_TX_FIFO or Reset;
--------------------------------------------------------------------------
-- SRL_FIFO_I : Transmit FIFO Interface
--------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => TX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => TX_Data,
FIFO_Read => fifo_rd,
Data_Out => fifo_DOut,
FIFO_Full => tx_buffer_full_i,
FIFO_Empty => fifo_Data_Empty
);
TX_Buffer_Full <= tx_buffer_full_i;
TX_Buffer_Empty <= fifo_Data_Empty;
fifo_Data_Present <= not fifo_Data_Empty;
end architecture RTL;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lib_srl_fifo_v1_0/c6efbe92/hdl/src/vhdl/srl_fifo_f.vhd | 11 | 9367 | -- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/receive.vhd | 4 | 14925 | -------------------------------------------------------------------------------
-- receive - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : receive.vhd
-- Version : v2.0
-- Description : This is the receive path portion of the design
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
library unisim;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Phy_rx_clk -- Ethernet receive clock
-- Phy_dv -- Ethernet receive enable
-- Phy_rx_data -- Ethernet receive data
-- Phy_rx_col -- Ethernet collision indicator
-- Phy_rx_er -- Ethernet receive error
-- Rx_addr_en -- RX buufer address enable
-- Rx_start -- Receive start
-- Rx_done -- Receive complete
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write read enable
-- Rx_idle -- RX idle
-- Mac_addr_ram_addr_rd -- MAC Addr RAM read address
-- Mac_addr_ram_data -- MAC Addr RAM read data
-- Rx_buffer_ready -- RX buffer ready to accept new packet
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity receive is
generic
(
C_DUPLEX : integer := 1;
-- 1 = full duplex, 0 = half duplex
C_FAMILY : string := "virtex6"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
Phy_rx_clk : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Phy_rx_col : in std_logic;
Phy_rx_er : in std_logic;
Rx_addr_en : out std_logic;
Rx_start : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_idle : out std_logic;
Mac_addr_ram_addr_rd : out std_logic_vector(0 to 3);
Mac_addr_ram_data : in std_logic_vector (0 to 3);
Rx_buffer_ready : in std_logic
);
end receive;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of receive is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal fifo_empty_i : std_logic;
signal fifo_full_i : std_logic;
signal emac_rx_rd_i : std_logic;
signal emac_rx_rd_data_i : std_logic_vector(0 to 5);
signal emac_rx_rd_data_d1 : std_logic_vector(0 to 5); -- 03-26-04
signal rxAbortRst : std_logic;
signal rxChannelReset : std_logic;
signal rxBusFifoRdAck : std_logic;
signal rxComboCrcRst : std_logic;
signal rxComboCrcEn : std_logic;
signal crcOk_i : std_logic;
signal rxCrcRst : std_logic;
signal rxCrcEn : std_logic;
signal rxCrcEn_d1 : std_logic; -- 03-26-04
signal receive_enable : std_logic; -- 03-26-04
signal fifo_reset : std_logic; -- 03-26-04
begin
----------------------------------------------------------------------------
-- rx control state machine
----------------------------------------------------------------------------
INST_RX_STATE: entity axi_ethernetlite_v3_0.rx_statemachine
generic map (
C_DUPLEX => C_DUPLEX
)
port map (
Clk => Clk,
Rst => rxChannelReset,
Emac_rx_rd_data_d1 => emac_rx_rd_data_d1, -- 03-26-04
Receive_enable => receive_enable, -- 03-26-04
RxBusFifoRdAck => rxBusFifoRdAck,
BusFifoEmpty => fifo_empty_i,
Collision => Phy_rx_col,
DataValid => emac_rx_rd_data_i(4),
RxError => emac_rx_rd_data_i(5),
BusFifoData => emac_rx_rd_data_i(0 to 3),
CrcOk => crcOk_i,
BusFifoRd => emac_rx_rd_i,
RxAbortRst => rxAbortRst,
RxCrcRst => rxCrcRst,
RxCrcEn => rxCrcEn,
Rx_addr_en => Rx_addr_en,
Rx_start => Rx_start,
Rx_done => Rx_done,
Rx_pong_ping_l => Rx_pong_ping_l,
Rx_DPM_ce => Rx_DPM_ce,
Rx_DPM_wr_data => Rx_DPM_wr_data,
Rx_DPM_rd_data => Rx_DPM_rd_data,
Rx_DPM_wr_rd_n => Rx_DPM_wr_rd_n,
Rx_idle => Rx_idle,
Mac_addr_ram_addr_rd => Mac_addr_ram_addr_rd,
Mac_addr_ram_data => Mac_addr_ram_data,
Rx_buffer_ready => Rx_buffer_ready
);
rxChannelReset <= Rst;
----------------------------------------------------------------------------
-- rx interface contains the ethernet rx fifo
----------------------------------------------------------------------------
INST_RX_INTRFCE: entity axi_ethernetlite_v3_0.rx_intrfce
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Rst => fifo_reset,
Phy_rx_clk => Phy_rx_clk,
InternalWrapEn => '0',
Phy_rx_er => Phy_rx_er,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data,
Rcv_en => receive_enable,
Fifo_empty => fifo_empty_i,
Fifo_full => fifo_full_i,
Emac_rx_rd => emac_rx_rd_i,
Emac_rx_rd_data => emac_rx_rd_data_i,
RdAck => rxBusFifoRdAck
);
--fifo_reset <= Rst or not(receive_enable); -- 03-26-04
fifo_reset <= Rst; -- removing cross clock passing of signal(receive_enable is genrated in lite_clock domain and going to fifo working in rx_clk domain)
----------------------------------------------------------------------------
-- crc checker
----------------------------------------------------------------------------
INST_CRCGENRX: entity axi_ethernetlite_v3_0.crcgenrx
port map(
Clk => Clk,
Rst => rxComboCrcRst,
Data => emac_rx_rd_data_i(0 to 3),
DataEn => rxComboCrcEn,
CrcOk => crcOk_i);
rxComboCrcRst <= Rst or rxCrcRst or rxAbortRst;
rxComboCrcEn <= rxCrcEn_d1;
----------------------------------------------------------------------------
-- REG_PROCESS
----------------------------------------------------------------------------
-- This process registers the received read data and receive CRC enable.
----------------------------------------------------------------------------
REG_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
emac_rx_rd_data_d1 <= "000000";
rxCrcEn_d1 <= '0';
else
emac_rx_rd_data_d1 <= emac_rx_rd_data_i;
rxCrcEn_d1 <= rxCrcEn;
end if;
end if;
end process REG_PROCESS;
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/receive.vhd | 4 | 14925 | -------------------------------------------------------------------------------
-- receive - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : receive.vhd
-- Version : v2.0
-- Description : This is the receive path portion of the design
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
library unisim;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Phy_rx_clk -- Ethernet receive clock
-- Phy_dv -- Ethernet receive enable
-- Phy_rx_data -- Ethernet receive data
-- Phy_rx_col -- Ethernet collision indicator
-- Phy_rx_er -- Ethernet receive error
-- Rx_addr_en -- RX buufer address enable
-- Rx_start -- Receive start
-- Rx_done -- Receive complete
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write read enable
-- Rx_idle -- RX idle
-- Mac_addr_ram_addr_rd -- MAC Addr RAM read address
-- Mac_addr_ram_data -- MAC Addr RAM read data
-- Rx_buffer_ready -- RX buffer ready to accept new packet
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity receive is
generic
(
C_DUPLEX : integer := 1;
-- 1 = full duplex, 0 = half duplex
C_FAMILY : string := "virtex6"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
Phy_rx_clk : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Phy_rx_col : in std_logic;
Phy_rx_er : in std_logic;
Rx_addr_en : out std_logic;
Rx_start : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_idle : out std_logic;
Mac_addr_ram_addr_rd : out std_logic_vector(0 to 3);
Mac_addr_ram_data : in std_logic_vector (0 to 3);
Rx_buffer_ready : in std_logic
);
end receive;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of receive is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal fifo_empty_i : std_logic;
signal fifo_full_i : std_logic;
signal emac_rx_rd_i : std_logic;
signal emac_rx_rd_data_i : std_logic_vector(0 to 5);
signal emac_rx_rd_data_d1 : std_logic_vector(0 to 5); -- 03-26-04
signal rxAbortRst : std_logic;
signal rxChannelReset : std_logic;
signal rxBusFifoRdAck : std_logic;
signal rxComboCrcRst : std_logic;
signal rxComboCrcEn : std_logic;
signal crcOk_i : std_logic;
signal rxCrcRst : std_logic;
signal rxCrcEn : std_logic;
signal rxCrcEn_d1 : std_logic; -- 03-26-04
signal receive_enable : std_logic; -- 03-26-04
signal fifo_reset : std_logic; -- 03-26-04
begin
----------------------------------------------------------------------------
-- rx control state machine
----------------------------------------------------------------------------
INST_RX_STATE: entity axi_ethernetlite_v3_0.rx_statemachine
generic map (
C_DUPLEX => C_DUPLEX
)
port map (
Clk => Clk,
Rst => rxChannelReset,
Emac_rx_rd_data_d1 => emac_rx_rd_data_d1, -- 03-26-04
Receive_enable => receive_enable, -- 03-26-04
RxBusFifoRdAck => rxBusFifoRdAck,
BusFifoEmpty => fifo_empty_i,
Collision => Phy_rx_col,
DataValid => emac_rx_rd_data_i(4),
RxError => emac_rx_rd_data_i(5),
BusFifoData => emac_rx_rd_data_i(0 to 3),
CrcOk => crcOk_i,
BusFifoRd => emac_rx_rd_i,
RxAbortRst => rxAbortRst,
RxCrcRst => rxCrcRst,
RxCrcEn => rxCrcEn,
Rx_addr_en => Rx_addr_en,
Rx_start => Rx_start,
Rx_done => Rx_done,
Rx_pong_ping_l => Rx_pong_ping_l,
Rx_DPM_ce => Rx_DPM_ce,
Rx_DPM_wr_data => Rx_DPM_wr_data,
Rx_DPM_rd_data => Rx_DPM_rd_data,
Rx_DPM_wr_rd_n => Rx_DPM_wr_rd_n,
Rx_idle => Rx_idle,
Mac_addr_ram_addr_rd => Mac_addr_ram_addr_rd,
Mac_addr_ram_data => Mac_addr_ram_data,
Rx_buffer_ready => Rx_buffer_ready
);
rxChannelReset <= Rst;
----------------------------------------------------------------------------
-- rx interface contains the ethernet rx fifo
----------------------------------------------------------------------------
INST_RX_INTRFCE: entity axi_ethernetlite_v3_0.rx_intrfce
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Rst => fifo_reset,
Phy_rx_clk => Phy_rx_clk,
InternalWrapEn => '0',
Phy_rx_er => Phy_rx_er,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data,
Rcv_en => receive_enable,
Fifo_empty => fifo_empty_i,
Fifo_full => fifo_full_i,
Emac_rx_rd => emac_rx_rd_i,
Emac_rx_rd_data => emac_rx_rd_data_i,
RdAck => rxBusFifoRdAck
);
--fifo_reset <= Rst or not(receive_enable); -- 03-26-04
fifo_reset <= Rst; -- removing cross clock passing of signal(receive_enable is genrated in lite_clock domain and going to fifo working in rx_clk domain)
----------------------------------------------------------------------------
-- crc checker
----------------------------------------------------------------------------
INST_CRCGENRX: entity axi_ethernetlite_v3_0.crcgenrx
port map(
Clk => Clk,
Rst => rxComboCrcRst,
Data => emac_rx_rd_data_i(0 to 3),
DataEn => rxComboCrcEn,
CrcOk => crcOk_i);
rxComboCrcRst <= Rst or rxCrcRst or rxAbortRst;
rxComboCrcEn <= rxCrcEn_d1;
----------------------------------------------------------------------------
-- REG_PROCESS
----------------------------------------------------------------------------
-- This process registers the received read data and receive CRC enable.
----------------------------------------------------------------------------
REG_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
emac_rx_rd_data_d1 <= "000000";
rxCrcEn_d1 <= '0';
else
emac_rx_rd_data_d1 <= emac_rx_rd_data_i;
rxCrcEn_d1 <= rxCrcEn;
end if;
end if;
end process REG_PROCESS;
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_dlmb_v10_0/synth/design_1_dlmb_v10_0.vhd | 2 | 9038 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_v10_v3_0;
USE lmb_v10_v3_0.lmb_v10;
ENTITY design_1_dlmb_v10_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END design_1_dlmb_v10_0;
ARCHITECTURE design_1_dlmb_v10_0_arch OF design_1_dlmb_v10_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dlmb_v10_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_v10 IS
GENERIC (
C_LMB_NUM_SLAVES : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_LMB_AWIDTH : INTEGER;
C_EXT_RESET_HIGH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END COMPONENT lmb_v10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_dlmb_v10_0_arch: ARCHITECTURE IS "lmb_v10,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_dlmb_v10_0_arch : ARCHITECTURE IS "design_1_dlmb_v10_0,lmb_v10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_dlmb_v10_0_arch: ARCHITECTURE IS "design_1_dlmb_v10_0,lmb_v10,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_v10,x_ipVersion=3.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_LMB_NUM_SLAVES=1,C_LMB_DWIDTH=32,C_LMB_AWIDTH=32,C_EXT_RESET_HIGH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
BEGIN
U0 : lmb_v10
GENERIC MAP (
C_LMB_NUM_SLAVES => 1,
C_LMB_DWIDTH => 32,
C_LMB_AWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
PORT MAP (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
END design_1_dlmb_v10_0_arch;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/mii_to_rmii.vhd | 4 | 19556 | -----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_Im_SP1
-- Updated Release For V5 Porting
-- @END_CHANGELOG
------------------------------------------------------------------------------
-- Filename: mii_to_rmii.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
use mii_to_rmii_v2_0.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_INSTANCE -- Instance name in the system.
-- C_FIXED_SPEED -- selects a fixed data throughput or agile RX
-- -- side, TX side is will be fixed either way
-- C_SPEED_100 -- selects speed for TX, RX if C_FIXED_SPEED is
-- -- selected
--
-- Definition of Ports:
-- rst_n -- active low reset
-- ref_clk -- clk, must be 50 MHz
-- mac2rmii_tx_en -- active high transmit enable, valid txd
-- mac2rmii_txd -- 4 bits of tx data from MAC
-- mac2rmii_tx_er -- active high tx error indicator
-- rmii2mac_tx_clk -- 25 or 2.5 MHz clock to MAC
-- rmii2mac_rx_clk -- 25 or 2.5 MHz clock to MAC
-- rmii2mac_col -- active high colision indicator
-- rmii2mac_crs -- active high carrier sense
-- rmii2mac_rx_dv -- active high rx data valid
-- rmii2mac_rx_er -- acitve high rx error indicator
-- rmii2mac_rxd -- 4 bits of rx data to MAC
-- phy2rmii_crs_dv -- active high carrier sense / data valid to rmii
-- phy2rmii_rx_er -- active high rx error indicator
-- phy2rmii_rxd -- 2 bits of rx data to rmii
-- rmii2phy_txd -- 2 bits of tx data to phy
-- rmii2phy_tx_en -- active high tx enable, valid tx to phy
--
------------------------------------------------------------------------------
entity mii_to_rmii is
generic (
C_INSTANCE : string := "mii_to_rmii_inst";
C_FIXED_SPEED : std_logic := '1';
C_SPEED_100 : std_logic := '1'
);
port (
------------------ System Signals ----------------------
rst_n : in std_logic;
ref_clk : in std_logic;
------------------ Speed Setting -----------------------
--Tx_speed_100 : in std_logic; -- add if ever
--Rx_speed_100 : in std_logic; -- auto speed
------------------ MAC <--> RMII -----------------------
mac2rmii_tx_en : in std_logic;
mac2rmii_txd : in std_logic_vector(3 downto 0);
mac2rmii_tx_er : in std_logic;
rmii2mac_tx_clk : out std_logic;
rmii2mac_rx_clk : out std_logic;
rmii2mac_col : out std_logic;
rmii2mac_crs : out std_logic;
rmii2mac_rx_dv : out std_logic;
rmii2mac_rx_er : out std_logic;
rmii2mac_rxd : out std_logic_vector(3 downto 0);
------------------ RMII <--> PHY -----------------------
phy2rmii_crs_dv : in std_logic;
phy2rmii_rx_er : in std_logic;
phy2rmii_rxd : in std_logic_vector(1 downto 0);
rmii2phy_txd : out std_logic_vector(1 downto 0);
rmii2phy_tx_en : out std_logic
);
attribute HDL : string;
attribute IMP_NETLIST : string;
attribute IPTYPE : string;
attribute IP_GROUP : string;
attribute SIGIS : string;
attribute STYLE : string;
attribute XRANGE : string;
attribute HDL of mii_to_rmii:entity is "VHDL";
attribute IMP_NETLIST of mii_to_rmii:entity is "TRUE";
attribute IPTYPE of mii_to_rmii:entity is "IP";
attribute IP_GROUP of mii_to_rmii:entity is "LOGICORE";
attribute SIGIS of ref_clk:signal is "CLK";
-- attribute SIGIS of rmii2mac_tx_clk:signal is "CLK";
-- attribute SIGIS of rmii2mac_rx_clk:signal is "CLK";
attribute SIGIS of rst_n:signal is "RST";
attribute STYLE of mii_to_rmii:entity is "HDL";
attribute XRANGE of C_FIXED_SPEED:constant is "('0':'1')";
attribute XRANGE of C_SPEED_100:constant is "('0':'1')";
end mii_to_rmii;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of mii_to_rmii is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",mii_to_rmii,{"
& "c_instance = " & C_INSTANCE
& ",c_fixed_speed = " & str(C_FIXED_SPEED)
& ",c_speed_100 = " & str(C_SPEED_100)
& "}";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of simulation : architecture is C_CORE_GENERATION_INFO;
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '0';
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
signal tx_speed_100_i : std_logic;
signal rx_speed_100_i : std_logic;
signal sync_rst_n : std_logic;
signal rst_n_d : std_logic_vector(1 downto 0);
signal mac2Rmii_tx_en_d2 : std_logic;
signal mac2Rmii_tx_en_d1 : std_logic;
signal mac2Rmii_txd_d2 : std_logic_vector(3 downto 0);
signal mac2Rmii_txd_d1 : std_logic_vector(3 downto 0);
signal mac2Rmii_tx_er_d2 : std_logic;
signal mac2Rmii_tx_er_d1 : std_logic;
signal rmii2Mac_tx_clk_i : std_logic;
signal rmii2Mac_rx_clk_i : std_logic;
signal rmii2Mac_crs_i : std_logic;
signal rmii2Mac_rx_dv_i : std_logic;
signal rmii2Mac_rx_er_i : std_logic;
signal rmii2Mac_rxd_i : std_logic_vector(3 downto 0);
signal phy2Rmii_crs_dv_d2 : std_logic;
signal phy2Rmii_crs_dv_d1 : std_logic;
signal phy2Rmii_rx_er_d2 : std_logic;
signal phy2Rmii_rx_er_d1 : std_logic;
signal phy2Rmii_rxd_d2 : std_logic_vector(1 downto 0);
signal phy2Rmii_rxd_d1 : std_logic_vector(1 downto 0);
signal rmii2Phy_txd_i : std_logic_vector(1 downto 0);
signal rmii2Phy_tx_en_i : std_logic;
begin
------------------------------------------------------------------------------
-- SYNC_RST_N_PROCESS
------------------------------------------------------------------------------
SYNC_RST_N_PROCESS : process (
ref_clk,
rst_n,
rst_n_d
)
begin
sync_rst_n <= rst_n_d(1);
if (ref_clk'event and ref_clk = '1') then
rst_n_d <= rst_n_d(0) & rst_n;
end if;
end process;
------------------------------------------------------------------------------
-- INPUT_PIPELINE_PROCESS
------------------------------------------------------------------------------
INPUT_PIPELINE_PROCESS : process ( ref_clk )
begin
if (ref_clk'event and ref_clk = '1') then
if ( sync_rst_n = '0' ) then
mac2Rmii_tx_en_d2 <= '0';
mac2Rmii_tx_en_d1 <= '0';
mac2Rmii_txd_d2 <= "0000";
mac2Rmii_txd_d1 <= "0000";
mac2Rmii_tx_er_d2 <= '0';
mac2Rmii_tx_er_d1 <= '0';
phy2Rmii_crs_dv_d2 <= '0';
phy2Rmii_crs_dv_d1 <= '0';
phy2Rmii_rx_er_d2 <= '0';
phy2Rmii_rx_er_d1 <= '0';
phy2Rmii_rxd_d2 <= "00";
phy2Rmii_rxd_d1 <= "00";
else
mac2Rmii_tx_en_d2 <= mac2Rmii_tx_en_d1;
mac2Rmii_tx_en_d1 <= mac2rmii_tx_en;
mac2Rmii_txd_d2 <= mac2Rmii_txd_d1;
mac2Rmii_txd_d1 <= mac2rmii_txd;
mac2Rmii_tx_er_d2 <= mac2Rmii_tx_er_d1;
mac2Rmii_tx_er_d1 <= mac2rmii_tx_er;
phy2Rmii_crs_dv_d2 <= phy2Rmii_crs_dv_d1;
phy2Rmii_crs_dv_d1 <= phy2rmii_crs_dv;
phy2Rmii_rx_er_d2 <= phy2Rmii_rx_er_d1;
phy2Rmii_rx_er_d1 <= phy2rmii_rx_er;
phy2Rmii_rxd_d2 <= phy2Rmii_rxd_d1;
phy2Rmii_rxd_d1 <= phy2rmii_rxd;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- OUTPUT_PIPELINE_PROCESS
------------------------------------------------------------------------------
OUTPUT_PIPELINE_PROCESS : process ( ref_clk )
begin
if (ref_clk'event and ref_clk = '1') then
if ( sync_rst_n = '0' ) then
rmii2mac_tx_clk <= '0';
rmii2mac_rx_clk <= '0';
rmii2mac_col <= '0';
rmii2mac_crs <= '0';
rmii2mac_rx_dv <= '0';
rmii2mac_rx_er <= '0';
rmii2mac_rxd <= "0000";
rmii2phy_txd <= "00";
rmii2phy_tx_en <= '0';
else
rmii2mac_tx_clk <= rmii2Mac_tx_clk_i;
rmii2mac_rx_clk <= rmii2Mac_rx_clk_i;
rmii2mac_col <= rmii2Mac_crs_i and mac2Rmii_tx_en_d2;
rmii2mac_crs <= rmii2Mac_crs_i;
rmii2mac_rx_dv <= rmii2Mac_rx_dv_i;
rmii2mac_rx_er <= rmii2Mac_rx_er_i;
rmii2mac_rxd <= rmii2Mac_rxd_i;
rmii2phy_txd <= rmii2Phy_txd_i;
rmii2phy_tx_en <= rmii2Phy_tx_en_i;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Concurrent signal assignments
------------------------------------------------------------------------------
tx_speed_100_i <= C_SPEED_100;
rx_speed_100_i <= C_SPEED_100;
------------------------------------------------------------------------------
--
-- Conditional Generate for AGILE speed throughput
--
------------------------------------------------------------------------------
RMII_AGILE : if (C_FIXED_SPEED = '0') generate
begin
--------------------------------------------------------------------------
-- Component Instatiations
--------------------------------------------------------------------------
I_TX : entity mii_to_rmii_v2_0.rmii_tx_agile(simulation)
generic map(
C_RESET_ACTIVE => RESET_ACTIVE
)
port map (
Tx_speed_100 => tx_speed_100_i,
------------------ System Signals -------------
Sync_rst_n => sync_rst_n, -- in
ref_clk => ref_clk, -- in
------------------ MII <--> RMII ------------
mac2rmii_tx_en => mac2Rmii_tx_en_d2, -- in
mac2rmii_txd => mac2Rmii_txd_d2, -- in
mac2rmii_tx_er => mac2Rmii_tx_er_d2, -- in
rmii2mac_tx_clk => rmii2Mac_tx_clk_i, -- out
------------------ RMII <--> PHY ------------
rmii2phy_txd => rmii2Phy_txd_i, -- out
rmii2phy_tx_en => rmii2Phy_tx_en_i -- out
);
I_RX : entity mii_to_rmii_v2_0.rmii_rx_agile(simulation)
generic map(
C_RESET_ACTIVE => RESET_ACTIVE
)
port map (
Rx_speed_100 => rx_speed_100_i,
------------------ System Signals -------------
Sync_rst_n => sync_rst_n, -- in
ref_clk => ref_clk, -- in
------------------ MII <--> RMII ------------
rmii2mac_rx_clk => rmii2Mac_rx_clk_i, -- out
rmii2mac_crs => rmii2Mac_crs_i, -- out
rmii2mac_rx_dv => rmii2Mac_rx_dv_i, -- out
rmii2mac_rx_er => rmii2Mac_rx_er_i, -- out
rmii2mac_rxd => rmii2Mac_rxd_i, -- out
------------------ RMII <--> PHY ------------
phy2rmii_crs_dv => phy2Rmii_crs_dv_d2, -- in
phy2rmii_rx_er => phy2Rmii_rx_er_d2, -- in
phy2rmii_rxd => phy2Rmii_rxd_d2 -- in
);
end generate RMII_AGILE;
------------------------------------------------------------------------------
--
-- Conditional Generate for FIXED speed throughput
--
------------------------------------------------------------------------------
RMII_FIXED : if (C_FIXED_SPEED = '1') generate
begin
--------------------------------------------------------------------------
-- Component Instatiations
--------------------------------------------------------------------------
I_TX : entity mii_to_rmii_v2_0.rmii_tx_fixed(simulation)
generic map(
C_RESET_ACTIVE => RESET_ACTIVE
)
port map (
Tx_speed_100 => tx_speed_100_i,
------------------ System Signals -------------
Sync_rst_n => sync_rst_n, -- in
ref_clk => ref_clk, -- in
------------------ MII <--> RMII ------------
mac2rmii_tx_en => mac2Rmii_tx_en_d2, -- in
mac2rmii_txd => mac2Rmii_txd_d2, -- in
mac2rmii_tx_er => mac2Rmii_tx_er_d2, -- in
rmii2mac_tx_clk => rmii2Mac_tx_clk_i, -- out
------------------ RMII <--> PHY ------------
rmii2phy_txd => rmii2Phy_txd_i, -- out
rmii2phy_tx_en => rmii2Phy_tx_en_i -- out
);
I_RX : entity mii_to_rmii_v2_0.rmii_rx_fixed(simulation)
generic map(
C_RESET_ACTIVE => RESET_ACTIVE,
C_SPEED_100 => C_SPEED_100
)
port map (
Rx_speed_100 => rx_speed_100_i,
------------------ System Signals -------------
Sync_rst_n => sync_rst_n, -- in
ref_clk => ref_clk, -- in
------------------ MII <--> RMII ------------
rmii2mac_rx_clk => rmii2Mac_rx_clk_i, -- out
rmii2mac_crs => rmii2Mac_crs_i, -- out
rmii2mac_rx_dv => rmii2Mac_rx_dv_i, -- out
rmii2mac_rx_er => rmii2Mac_rx_er_i, -- out
rmii2mac_rxd => rmii2Mac_rxd_i, -- out
------------------ RMII <--> PHY ------------
phy2rmii_crs_dv => phy2Rmii_crs_dv_d2, -- in
phy2rmii_rx_er => phy2Rmii_rx_er_d2, -- in
phy2rmii_rxd => phy2Rmii_rxd_d2 -- in
);
end generate RMII_FIXED;
end simulation;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/mii_to_rmii.vhd | 4 | 19556 | -----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_Im_SP1
-- Updated Release For V5 Porting
-- @END_CHANGELOG
------------------------------------------------------------------------------
-- Filename: mii_to_rmii.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
use mii_to_rmii_v2_0.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_INSTANCE -- Instance name in the system.
-- C_FIXED_SPEED -- selects a fixed data throughput or agile RX
-- -- side, TX side is will be fixed either way
-- C_SPEED_100 -- selects speed for TX, RX if C_FIXED_SPEED is
-- -- selected
--
-- Definition of Ports:
-- rst_n -- active low reset
-- ref_clk -- clk, must be 50 MHz
-- mac2rmii_tx_en -- active high transmit enable, valid txd
-- mac2rmii_txd -- 4 bits of tx data from MAC
-- mac2rmii_tx_er -- active high tx error indicator
-- rmii2mac_tx_clk -- 25 or 2.5 MHz clock to MAC
-- rmii2mac_rx_clk -- 25 or 2.5 MHz clock to MAC
-- rmii2mac_col -- active high colision indicator
-- rmii2mac_crs -- active high carrier sense
-- rmii2mac_rx_dv -- active high rx data valid
-- rmii2mac_rx_er -- acitve high rx error indicator
-- rmii2mac_rxd -- 4 bits of rx data to MAC
-- phy2rmii_crs_dv -- active high carrier sense / data valid to rmii
-- phy2rmii_rx_er -- active high rx error indicator
-- phy2rmii_rxd -- 2 bits of rx data to rmii
-- rmii2phy_txd -- 2 bits of tx data to phy
-- rmii2phy_tx_en -- active high tx enable, valid tx to phy
--
------------------------------------------------------------------------------
entity mii_to_rmii is
generic (
C_INSTANCE : string := "mii_to_rmii_inst";
C_FIXED_SPEED : std_logic := '1';
C_SPEED_100 : std_logic := '1'
);
port (
------------------ System Signals ----------------------
rst_n : in std_logic;
ref_clk : in std_logic;
------------------ Speed Setting -----------------------
--Tx_speed_100 : in std_logic; -- add if ever
--Rx_speed_100 : in std_logic; -- auto speed
------------------ MAC <--> RMII -----------------------
mac2rmii_tx_en : in std_logic;
mac2rmii_txd : in std_logic_vector(3 downto 0);
mac2rmii_tx_er : in std_logic;
rmii2mac_tx_clk : out std_logic;
rmii2mac_rx_clk : out std_logic;
rmii2mac_col : out std_logic;
rmii2mac_crs : out std_logic;
rmii2mac_rx_dv : out std_logic;
rmii2mac_rx_er : out std_logic;
rmii2mac_rxd : out std_logic_vector(3 downto 0);
------------------ RMII <--> PHY -----------------------
phy2rmii_crs_dv : in std_logic;
phy2rmii_rx_er : in std_logic;
phy2rmii_rxd : in std_logic_vector(1 downto 0);
rmii2phy_txd : out std_logic_vector(1 downto 0);
rmii2phy_tx_en : out std_logic
);
attribute HDL : string;
attribute IMP_NETLIST : string;
attribute IPTYPE : string;
attribute IP_GROUP : string;
attribute SIGIS : string;
attribute STYLE : string;
attribute XRANGE : string;
attribute HDL of mii_to_rmii:entity is "VHDL";
attribute IMP_NETLIST of mii_to_rmii:entity is "TRUE";
attribute IPTYPE of mii_to_rmii:entity is "IP";
attribute IP_GROUP of mii_to_rmii:entity is "LOGICORE";
attribute SIGIS of ref_clk:signal is "CLK";
-- attribute SIGIS of rmii2mac_tx_clk:signal is "CLK";
-- attribute SIGIS of rmii2mac_rx_clk:signal is "CLK";
attribute SIGIS of rst_n:signal is "RST";
attribute STYLE of mii_to_rmii:entity is "HDL";
attribute XRANGE of C_FIXED_SPEED:constant is "('0':'1')";
attribute XRANGE of C_SPEED_100:constant is "('0':'1')";
end mii_to_rmii;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of mii_to_rmii is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",mii_to_rmii,{"
& "c_instance = " & C_INSTANCE
& ",c_fixed_speed = " & str(C_FIXED_SPEED)
& ",c_speed_100 = " & str(C_SPEED_100)
& "}";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of simulation : architecture is C_CORE_GENERATION_INFO;
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '0';
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
signal tx_speed_100_i : std_logic;
signal rx_speed_100_i : std_logic;
signal sync_rst_n : std_logic;
signal rst_n_d : std_logic_vector(1 downto 0);
signal mac2Rmii_tx_en_d2 : std_logic;
signal mac2Rmii_tx_en_d1 : std_logic;
signal mac2Rmii_txd_d2 : std_logic_vector(3 downto 0);
signal mac2Rmii_txd_d1 : std_logic_vector(3 downto 0);
signal mac2Rmii_tx_er_d2 : std_logic;
signal mac2Rmii_tx_er_d1 : std_logic;
signal rmii2Mac_tx_clk_i : std_logic;
signal rmii2Mac_rx_clk_i : std_logic;
signal rmii2Mac_crs_i : std_logic;
signal rmii2Mac_rx_dv_i : std_logic;
signal rmii2Mac_rx_er_i : std_logic;
signal rmii2Mac_rxd_i : std_logic_vector(3 downto 0);
signal phy2Rmii_crs_dv_d2 : std_logic;
signal phy2Rmii_crs_dv_d1 : std_logic;
signal phy2Rmii_rx_er_d2 : std_logic;
signal phy2Rmii_rx_er_d1 : std_logic;
signal phy2Rmii_rxd_d2 : std_logic_vector(1 downto 0);
signal phy2Rmii_rxd_d1 : std_logic_vector(1 downto 0);
signal rmii2Phy_txd_i : std_logic_vector(1 downto 0);
signal rmii2Phy_tx_en_i : std_logic;
begin
------------------------------------------------------------------------------
-- SYNC_RST_N_PROCESS
------------------------------------------------------------------------------
SYNC_RST_N_PROCESS : process (
ref_clk,
rst_n,
rst_n_d
)
begin
sync_rst_n <= rst_n_d(1);
if (ref_clk'event and ref_clk = '1') then
rst_n_d <= rst_n_d(0) & rst_n;
end if;
end process;
------------------------------------------------------------------------------
-- INPUT_PIPELINE_PROCESS
------------------------------------------------------------------------------
INPUT_PIPELINE_PROCESS : process ( ref_clk )
begin
if (ref_clk'event and ref_clk = '1') then
if ( sync_rst_n = '0' ) then
mac2Rmii_tx_en_d2 <= '0';
mac2Rmii_tx_en_d1 <= '0';
mac2Rmii_txd_d2 <= "0000";
mac2Rmii_txd_d1 <= "0000";
mac2Rmii_tx_er_d2 <= '0';
mac2Rmii_tx_er_d1 <= '0';
phy2Rmii_crs_dv_d2 <= '0';
phy2Rmii_crs_dv_d1 <= '0';
phy2Rmii_rx_er_d2 <= '0';
phy2Rmii_rx_er_d1 <= '0';
phy2Rmii_rxd_d2 <= "00";
phy2Rmii_rxd_d1 <= "00";
else
mac2Rmii_tx_en_d2 <= mac2Rmii_tx_en_d1;
mac2Rmii_tx_en_d1 <= mac2rmii_tx_en;
mac2Rmii_txd_d2 <= mac2Rmii_txd_d1;
mac2Rmii_txd_d1 <= mac2rmii_txd;
mac2Rmii_tx_er_d2 <= mac2Rmii_tx_er_d1;
mac2Rmii_tx_er_d1 <= mac2rmii_tx_er;
phy2Rmii_crs_dv_d2 <= phy2Rmii_crs_dv_d1;
phy2Rmii_crs_dv_d1 <= phy2rmii_crs_dv;
phy2Rmii_rx_er_d2 <= phy2Rmii_rx_er_d1;
phy2Rmii_rx_er_d1 <= phy2rmii_rx_er;
phy2Rmii_rxd_d2 <= phy2Rmii_rxd_d1;
phy2Rmii_rxd_d1 <= phy2rmii_rxd;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- OUTPUT_PIPELINE_PROCESS
------------------------------------------------------------------------------
OUTPUT_PIPELINE_PROCESS : process ( ref_clk )
begin
if (ref_clk'event and ref_clk = '1') then
if ( sync_rst_n = '0' ) then
rmii2mac_tx_clk <= '0';
rmii2mac_rx_clk <= '0';
rmii2mac_col <= '0';
rmii2mac_crs <= '0';
rmii2mac_rx_dv <= '0';
rmii2mac_rx_er <= '0';
rmii2mac_rxd <= "0000";
rmii2phy_txd <= "00";
rmii2phy_tx_en <= '0';
else
rmii2mac_tx_clk <= rmii2Mac_tx_clk_i;
rmii2mac_rx_clk <= rmii2Mac_rx_clk_i;
rmii2mac_col <= rmii2Mac_crs_i and mac2Rmii_tx_en_d2;
rmii2mac_crs <= rmii2Mac_crs_i;
rmii2mac_rx_dv <= rmii2Mac_rx_dv_i;
rmii2mac_rx_er <= rmii2Mac_rx_er_i;
rmii2mac_rxd <= rmii2Mac_rxd_i;
rmii2phy_txd <= rmii2Phy_txd_i;
rmii2phy_tx_en <= rmii2Phy_tx_en_i;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Concurrent signal assignments
------------------------------------------------------------------------------
tx_speed_100_i <= C_SPEED_100;
rx_speed_100_i <= C_SPEED_100;
------------------------------------------------------------------------------
--
-- Conditional Generate for AGILE speed throughput
--
------------------------------------------------------------------------------
RMII_AGILE : if (C_FIXED_SPEED = '0') generate
begin
--------------------------------------------------------------------------
-- Component Instatiations
--------------------------------------------------------------------------
I_TX : entity mii_to_rmii_v2_0.rmii_tx_agile(simulation)
generic map(
C_RESET_ACTIVE => RESET_ACTIVE
)
port map (
Tx_speed_100 => tx_speed_100_i,
------------------ System Signals -------------
Sync_rst_n => sync_rst_n, -- in
ref_clk => ref_clk, -- in
------------------ MII <--> RMII ------------
mac2rmii_tx_en => mac2Rmii_tx_en_d2, -- in
mac2rmii_txd => mac2Rmii_txd_d2, -- in
mac2rmii_tx_er => mac2Rmii_tx_er_d2, -- in
rmii2mac_tx_clk => rmii2Mac_tx_clk_i, -- out
------------------ RMII <--> PHY ------------
rmii2phy_txd => rmii2Phy_txd_i, -- out
rmii2phy_tx_en => rmii2Phy_tx_en_i -- out
);
I_RX : entity mii_to_rmii_v2_0.rmii_rx_agile(simulation)
generic map(
C_RESET_ACTIVE => RESET_ACTIVE
)
port map (
Rx_speed_100 => rx_speed_100_i,
------------------ System Signals -------------
Sync_rst_n => sync_rst_n, -- in
ref_clk => ref_clk, -- in
------------------ MII <--> RMII ------------
rmii2mac_rx_clk => rmii2Mac_rx_clk_i, -- out
rmii2mac_crs => rmii2Mac_crs_i, -- out
rmii2mac_rx_dv => rmii2Mac_rx_dv_i, -- out
rmii2mac_rx_er => rmii2Mac_rx_er_i, -- out
rmii2mac_rxd => rmii2Mac_rxd_i, -- out
------------------ RMII <--> PHY ------------
phy2rmii_crs_dv => phy2Rmii_crs_dv_d2, -- in
phy2rmii_rx_er => phy2Rmii_rx_er_d2, -- in
phy2rmii_rxd => phy2Rmii_rxd_d2 -- in
);
end generate RMII_AGILE;
------------------------------------------------------------------------------
--
-- Conditional Generate for FIXED speed throughput
--
------------------------------------------------------------------------------
RMII_FIXED : if (C_FIXED_SPEED = '1') generate
begin
--------------------------------------------------------------------------
-- Component Instatiations
--------------------------------------------------------------------------
I_TX : entity mii_to_rmii_v2_0.rmii_tx_fixed(simulation)
generic map(
C_RESET_ACTIVE => RESET_ACTIVE
)
port map (
Tx_speed_100 => tx_speed_100_i,
------------------ System Signals -------------
Sync_rst_n => sync_rst_n, -- in
ref_clk => ref_clk, -- in
------------------ MII <--> RMII ------------
mac2rmii_tx_en => mac2Rmii_tx_en_d2, -- in
mac2rmii_txd => mac2Rmii_txd_d2, -- in
mac2rmii_tx_er => mac2Rmii_tx_er_d2, -- in
rmii2mac_tx_clk => rmii2Mac_tx_clk_i, -- out
------------------ RMII <--> PHY ------------
rmii2phy_txd => rmii2Phy_txd_i, -- out
rmii2phy_tx_en => rmii2Phy_tx_en_i -- out
);
I_RX : entity mii_to_rmii_v2_0.rmii_rx_fixed(simulation)
generic map(
C_RESET_ACTIVE => RESET_ACTIVE,
C_SPEED_100 => C_SPEED_100
)
port map (
Rx_speed_100 => rx_speed_100_i,
------------------ System Signals -------------
Sync_rst_n => sync_rst_n, -- in
ref_clk => ref_clk, -- in
------------------ MII <--> RMII ------------
rmii2mac_rx_clk => rmii2Mac_rx_clk_i, -- out
rmii2mac_crs => rmii2Mac_crs_i, -- out
rmii2mac_rx_dv => rmii2Mac_rx_dv_i, -- out
rmii2mac_rx_er => rmii2Mac_rx_er_i, -- out
rmii2mac_rxd => rmii2Mac_rxd_i, -- out
------------------ RMII <--> PHY ------------
phy2rmii_crs_dv => phy2Rmii_crs_dv_d2, -- in
phy2rmii_rx_er => phy2Rmii_rx_er_d2, -- in
phy2rmii_rxd => phy2Rmii_rxd_d2 -- in
);
end generate RMII_FIXED;
end simulation;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/I2CTest/I2CTest.srcs/sim_1/new/topmodule_tb.vhd | 1 | 1974 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.01.2016 13:50:06
-- Design Name:
-- Module Name: topmodule_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity topmodule_tb is
-- Port ( );
end topmodule_tb;
architecture Behavioral of topmodule_tb is
constant Clk_period : time := 10ns;
signal clk : STD_LOGIC;
signal JA0 : STD_LOGIC;
signal JA1 : STD_LOGIC;
signal JA2 : STD_LOGIC;
signal JA3 : STD_LOGIC;
signal RsTx : STD_LOGIC;
signal btnCpuReset : STD_LOGIC := '1';
begin
UUT: entity work.topmodule(Behavioral)
port map (
clk => clk,
btnCpuReset => btnCpuReset,
JA0 => JA0,
JA1 => JA1,
JA2 => JA2,
JA3 => JA3,
RsTx => RsTx
);
-- Clock process definitions
Clk_process :process
begin
clk <= '0';
wait for Clk_period/2;
clk <= '1';
wait for Clk_period/2;
end process;
-- random reset program
reset_process : process
begin
btnCpuReset <= '0';
wait for Clk_period * 200;
btnCpuReset <= '1';
-- JA1 <= 'H';
wait for Clk_period * 2555;
-- JA1 <= '0';
wait for Clk_period * 249;
-- JA1 <= 'H';
wait for Clk_period * 999;
wait for Clk_period * 999;
wait;
end process;
JA0 <= 'H';
JA1 <= 'H';
end Behavioral;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/emac.vhd | 4 | 21370 | -------------------------------------------------------------------------------
-- emac - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : emac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
library lib_cdc_v1_0;
use lib_cdc_v1_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- NODE_MAC -- EMACLite MAC address
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_adr -- Tx buffer address
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_rd_data -- TX buffer read data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Tx_done -- Transmit done
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- Tx_idle -- Transmit idle
-- Rx_idle -- Receive idle
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_adr -- RX buffer address
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write/read enable
-- Rx_done -- Receive done
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Tx_packet_length -- Transmit packet length
-- Transmit_start -- Transmit Start
-- Mac_program_start -- MAC Program start
-- Rx_buffer_ready -- RX Buffer ready indicator
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity emac is
generic (
C_DUPLEX : integer := 1;
-- 1 = full duplex, 0 = half duplex
NODE_MAC : bit_vector := x"00005e00FACE";
C_FAMILY : string := "virtex6"
);
port (
Clk : in std_logic;
Rst : in std_logic;
Phy_tx_clk : in std_logic;
Phy_rx_clk : in std_logic;
Phy_crs : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Phy_col : in std_logic;
Phy_rx_er : in std_logic;
Phy_tx_en : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 3);
Tx_DPM_ce : out std_logic;
Tx_DPM_adr : out std_logic_vector (0 to 11);
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_rd_data : in std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Tx_done : out std_logic;
Tx_pong_ping_l : in std_logic;
Tx_idle : out std_logic;
Rx_idle : out std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_adr : out std_logic_vector (0 to 11);
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Tx_packet_length : in std_logic_vector(0 to 15);
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Rx_buffer_ready : in std_logic
);
end emac;
architecture imp of emac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
signal phy_col_d1 : std_logic; -- added 3-03-05 MSH
signal phy_crs_d1 : std_logic; -- added 3-03-05 MSH
signal phy_col_d2 : std_logic; -- added 27-jul-2011
signal phy_crs_d2 : std_logic; -- added 27-jul-2011
signal rxbuffer_addr : std_logic_vector(0 to 11);
signal rx_addr_en : std_logic;
signal rx_start : std_logic;
signal txbuffer_addr : std_logic_vector(0 to 11);
signal tx_addr_en : std_logic;
signal tx_start : std_logic;
signal mac_addr_ram_addr : std_logic_vector(0 to 3);
signal mac_addr_ram_addr_rd : std_logic_vector(0 to 3);
signal mac_addr_ram_we : std_logic;
signal mac_addr_ram_addr_wr : std_logic_vector(0 to 3);
signal mac_addr_ram_data : std_logic_vector(0 to 3);
signal txClkEn : std_logic;
signal tx_clk_reg_d1 : std_logic;
signal tx_clk_reg_d2 : std_logic;
signal tx_clk_reg_d3 : std_logic;
signal mac_tx_frame_length : std_logic_vector(0 to 15);
signal nibbleLength : std_logic_vector(0 to 11);
signal nibbleLength_orig : std_logic_vector(0 to 11);
signal en_pad : std_logic;
signal Phy_tx_clk_axi_d : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin
----------------------------------------------------------------------------
-- Receive Interface
----------------------------------------------------------------------------
RX: entity axi_ethernetlite_v3_0.receive
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
Phy_rx_clk => Phy_rx_clk,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data,
Phy_rx_col => phy_col_d2,
Phy_rx_er => Phy_rx_er,
Rx_addr_en => rx_addr_en,
Rx_start => rx_start,
Rx_done => Rx_done,
Rx_pong_ping_l => Rx_pong_ping_l,
Rx_DPM_ce => Rx_DPM_ce,
Rx_DPM_wr_data => Rx_DPM_wr_data,
Rx_DPM_rd_data => Rx_DPM_rd_data,
Rx_DPM_wr_rd_n => Rx_DPM_wr_rd_n,
Rx_idle => Rx_idle,
Mac_addr_ram_addr_rd => mac_addr_ram_addr_rd,
Mac_addr_ram_data => mac_addr_ram_data,
Rx_buffer_ready => Rx_buffer_ready
);
----------------------------------------------------------------------------
-- Transmit Interface
----------------------------------------------------------------------------
TX: entity axi_ethernetlite_v3_0.transmit
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
NibbleLength => nibbleLength,
NibbleLength_orig => nibbleLength_orig,
En_pad => en_pad,
TxClkEn => txClkEn,
Phy_tx_clk => Phy_tx_clk,
Phy_crs => phy_crs_d2,
Phy_col => phy_col_d2,
Phy_tx_en => phy_tx_en,
Phy_tx_data => phy_tx_data,
Tx_addr_en => tx_addr_en,
Tx_start => tx_start,
Tx_done => Tx_done,
Tx_pong_ping_l => Tx_pong_ping_l,
Tx_idle => Tx_idle,
Tx_DPM_ce => Tx_DPM_ce,
Tx_DPM_wr_data => Tx_DPM_wr_data,
Tx_DPM_rd_data => Tx_DPM_rd_data,
Tx_DPM_wr_rd_n => Tx_DPM_wr_rd_n,
Transmit_start => Transmit_start,
Mac_program_start => Mac_program_start,
Mac_addr_ram_we => mac_addr_ram_we,
Mac_addr_ram_addr_wr => mac_addr_ram_addr_wr
);
----------------------------------------------------------------------------
-- Registerign PHY Col
----------------------------------------------------------------------------
COLLISION_SYNC_1: FDR
port map
(
Q => phy_col_d1, --[out]
C => Clk, --[in]
D => Phy_col, --[in]
R => Rst --[in]
);
COLLISION_SYNC_2: FDR
port map
(
Q => phy_col_d2, --[out]
C => Clk, --[in]
D => phy_col_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Registerign PHY CRs
----------------------------------------------------------------------------
C_SENSE_SYNC_1: FDR
port map
(
Q => phy_crs_d1, --[out]
C => Clk, --[in]
D => Phy_crs, --[in]
R => Rst --[in]
);
C_SENSE_SYNC_2: FDR
port map
(
Q => phy_crs_d2, --[out]
C => Clk, --[in]
D => phy_crs_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- MAC Address RAM
----------------------------------------------------------------------------
NODEMACADDRRAMI: entity axi_ethernetlite_v3_0.MacAddrRAM
generic map
(
MACAddr => NODE_MAC
)
port map
(
addr => mac_addr_ram_addr,
dout => mac_addr_ram_data,
din => Tx_DPM_rd_data,
we => mac_addr_ram_we,
Clk => Clk
);
mac_addr_ram_addr <= mac_addr_ram_addr_rd when mac_addr_ram_we = '0' else
mac_addr_ram_addr_wr;
----------------------------------------------------------------------------
-- RX Address Counter for the RxBuffer
----------------------------------------------------------------------------
RXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_start = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_addr_en = '1' then
rxbuffer_addr <= rxbuffer_addr + 1;
end if;
end if;
end process RXADDRCNT;
Rx_DPM_adr <= rxbuffer_addr;
----------------------------------------------------------------------------
-- TX Address Counter for the TxBuffer (To Read)
----------------------------------------------------------------------------
TXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
txbuffer_addr <= (others => '0');
elsif tx_start = '1' then
txbuffer_addr <= (others => '0');
elsif tx_addr_en = '1' then
txbuffer_addr <= txbuffer_addr + 1;
end if;
end if;
end process TXADDRCNT;
Tx_DPM_adr <= txbuffer_addr;
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_clk in PHY_tx_clk domain
----------------------------------------------------------------------------
CDC_TX_CLK: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => Phy_tx_clk,
prmry_ack => open,
scndry_out => Phy_tx_clk_axi_d,
scndry_aclk => Clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- INT_tx_clk_sync_PROCESS
----------------------------------------------------------------------------
-- This process syncronizes the tx Clk and generates an enable pulse
----------------------------------------------------------------------------
INT_TX_CLK_SYNC_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
tx_clk_reg_d1 <= '0';
tx_clk_reg_d2 <= '0';
tx_clk_reg_d3 <= '0';
else
tx_clk_reg_d1 <= Phy_tx_clk_axi_d;
tx_clk_reg_d2 <= tx_clk_reg_d1;
tx_clk_reg_d3 <= tx_clk_reg_d2;
end if;
end if;
end process INT_TX_CLK_SYNC_PROCESS;
txClkEn <= '1' when tx_clk_reg_d2 = '1' and tx_clk_reg_d3 = '0' else
'0';
----------------------------------------------------------------------------
-- ADJP
----------------------------------------------------------------------------
-- Adjust the packet length is it is less than minimum
----------------------------------------------------------------------------
ADJP : process(mac_tx_frame_length)
begin
if mac_tx_frame_length > MinimumPacketLength then
nibbleLength <= mac_tx_frame_length(5 to 15) & '0';
en_pad <= '0';
else
nibbleLength <= MinimumPacketLength(5 to 15) & '0';
en_pad <= '1';
end if;
end process ADJP;
nibbleLength_orig <= mac_tx_frame_length(5 to 15) & '0';
mac_tx_frame_length <= Tx_packet_length;
----------------------------------------------------------------------------
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/emac.vhd | 4 | 21370 | -------------------------------------------------------------------------------
-- emac - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : emac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
library lib_cdc_v1_0;
use lib_cdc_v1_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- NODE_MAC -- EMACLite MAC address
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_adr -- Tx buffer address
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_rd_data -- TX buffer read data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Tx_done -- Transmit done
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- Tx_idle -- Transmit idle
-- Rx_idle -- Receive idle
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_adr -- RX buffer address
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write/read enable
-- Rx_done -- Receive done
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Tx_packet_length -- Transmit packet length
-- Transmit_start -- Transmit Start
-- Mac_program_start -- MAC Program start
-- Rx_buffer_ready -- RX Buffer ready indicator
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity emac is
generic (
C_DUPLEX : integer := 1;
-- 1 = full duplex, 0 = half duplex
NODE_MAC : bit_vector := x"00005e00FACE";
C_FAMILY : string := "virtex6"
);
port (
Clk : in std_logic;
Rst : in std_logic;
Phy_tx_clk : in std_logic;
Phy_rx_clk : in std_logic;
Phy_crs : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Phy_col : in std_logic;
Phy_rx_er : in std_logic;
Phy_tx_en : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 3);
Tx_DPM_ce : out std_logic;
Tx_DPM_adr : out std_logic_vector (0 to 11);
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_rd_data : in std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Tx_done : out std_logic;
Tx_pong_ping_l : in std_logic;
Tx_idle : out std_logic;
Rx_idle : out std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_adr : out std_logic_vector (0 to 11);
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Tx_packet_length : in std_logic_vector(0 to 15);
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Rx_buffer_ready : in std_logic
);
end emac;
architecture imp of emac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
signal phy_col_d1 : std_logic; -- added 3-03-05 MSH
signal phy_crs_d1 : std_logic; -- added 3-03-05 MSH
signal phy_col_d2 : std_logic; -- added 27-jul-2011
signal phy_crs_d2 : std_logic; -- added 27-jul-2011
signal rxbuffer_addr : std_logic_vector(0 to 11);
signal rx_addr_en : std_logic;
signal rx_start : std_logic;
signal txbuffer_addr : std_logic_vector(0 to 11);
signal tx_addr_en : std_logic;
signal tx_start : std_logic;
signal mac_addr_ram_addr : std_logic_vector(0 to 3);
signal mac_addr_ram_addr_rd : std_logic_vector(0 to 3);
signal mac_addr_ram_we : std_logic;
signal mac_addr_ram_addr_wr : std_logic_vector(0 to 3);
signal mac_addr_ram_data : std_logic_vector(0 to 3);
signal txClkEn : std_logic;
signal tx_clk_reg_d1 : std_logic;
signal tx_clk_reg_d2 : std_logic;
signal tx_clk_reg_d3 : std_logic;
signal mac_tx_frame_length : std_logic_vector(0 to 15);
signal nibbleLength : std_logic_vector(0 to 11);
signal nibbleLength_orig : std_logic_vector(0 to 11);
signal en_pad : std_logic;
signal Phy_tx_clk_axi_d : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin
----------------------------------------------------------------------------
-- Receive Interface
----------------------------------------------------------------------------
RX: entity axi_ethernetlite_v3_0.receive
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
Phy_rx_clk => Phy_rx_clk,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data,
Phy_rx_col => phy_col_d2,
Phy_rx_er => Phy_rx_er,
Rx_addr_en => rx_addr_en,
Rx_start => rx_start,
Rx_done => Rx_done,
Rx_pong_ping_l => Rx_pong_ping_l,
Rx_DPM_ce => Rx_DPM_ce,
Rx_DPM_wr_data => Rx_DPM_wr_data,
Rx_DPM_rd_data => Rx_DPM_rd_data,
Rx_DPM_wr_rd_n => Rx_DPM_wr_rd_n,
Rx_idle => Rx_idle,
Mac_addr_ram_addr_rd => mac_addr_ram_addr_rd,
Mac_addr_ram_data => mac_addr_ram_data,
Rx_buffer_ready => Rx_buffer_ready
);
----------------------------------------------------------------------------
-- Transmit Interface
----------------------------------------------------------------------------
TX: entity axi_ethernetlite_v3_0.transmit
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
NibbleLength => nibbleLength,
NibbleLength_orig => nibbleLength_orig,
En_pad => en_pad,
TxClkEn => txClkEn,
Phy_tx_clk => Phy_tx_clk,
Phy_crs => phy_crs_d2,
Phy_col => phy_col_d2,
Phy_tx_en => phy_tx_en,
Phy_tx_data => phy_tx_data,
Tx_addr_en => tx_addr_en,
Tx_start => tx_start,
Tx_done => Tx_done,
Tx_pong_ping_l => Tx_pong_ping_l,
Tx_idle => Tx_idle,
Tx_DPM_ce => Tx_DPM_ce,
Tx_DPM_wr_data => Tx_DPM_wr_data,
Tx_DPM_rd_data => Tx_DPM_rd_data,
Tx_DPM_wr_rd_n => Tx_DPM_wr_rd_n,
Transmit_start => Transmit_start,
Mac_program_start => Mac_program_start,
Mac_addr_ram_we => mac_addr_ram_we,
Mac_addr_ram_addr_wr => mac_addr_ram_addr_wr
);
----------------------------------------------------------------------------
-- Registerign PHY Col
----------------------------------------------------------------------------
COLLISION_SYNC_1: FDR
port map
(
Q => phy_col_d1, --[out]
C => Clk, --[in]
D => Phy_col, --[in]
R => Rst --[in]
);
COLLISION_SYNC_2: FDR
port map
(
Q => phy_col_d2, --[out]
C => Clk, --[in]
D => phy_col_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Registerign PHY CRs
----------------------------------------------------------------------------
C_SENSE_SYNC_1: FDR
port map
(
Q => phy_crs_d1, --[out]
C => Clk, --[in]
D => Phy_crs, --[in]
R => Rst --[in]
);
C_SENSE_SYNC_2: FDR
port map
(
Q => phy_crs_d2, --[out]
C => Clk, --[in]
D => phy_crs_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- MAC Address RAM
----------------------------------------------------------------------------
NODEMACADDRRAMI: entity axi_ethernetlite_v3_0.MacAddrRAM
generic map
(
MACAddr => NODE_MAC
)
port map
(
addr => mac_addr_ram_addr,
dout => mac_addr_ram_data,
din => Tx_DPM_rd_data,
we => mac_addr_ram_we,
Clk => Clk
);
mac_addr_ram_addr <= mac_addr_ram_addr_rd when mac_addr_ram_we = '0' else
mac_addr_ram_addr_wr;
----------------------------------------------------------------------------
-- RX Address Counter for the RxBuffer
----------------------------------------------------------------------------
RXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_start = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_addr_en = '1' then
rxbuffer_addr <= rxbuffer_addr + 1;
end if;
end if;
end process RXADDRCNT;
Rx_DPM_adr <= rxbuffer_addr;
----------------------------------------------------------------------------
-- TX Address Counter for the TxBuffer (To Read)
----------------------------------------------------------------------------
TXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
txbuffer_addr <= (others => '0');
elsif tx_start = '1' then
txbuffer_addr <= (others => '0');
elsif tx_addr_en = '1' then
txbuffer_addr <= txbuffer_addr + 1;
end if;
end if;
end process TXADDRCNT;
Tx_DPM_adr <= txbuffer_addr;
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_clk in PHY_tx_clk domain
----------------------------------------------------------------------------
CDC_TX_CLK: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => Phy_tx_clk,
prmry_ack => open,
scndry_out => Phy_tx_clk_axi_d,
scndry_aclk => Clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- INT_tx_clk_sync_PROCESS
----------------------------------------------------------------------------
-- This process syncronizes the tx Clk and generates an enable pulse
----------------------------------------------------------------------------
INT_TX_CLK_SYNC_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
tx_clk_reg_d1 <= '0';
tx_clk_reg_d2 <= '0';
tx_clk_reg_d3 <= '0';
else
tx_clk_reg_d1 <= Phy_tx_clk_axi_d;
tx_clk_reg_d2 <= tx_clk_reg_d1;
tx_clk_reg_d3 <= tx_clk_reg_d2;
end if;
end if;
end process INT_TX_CLK_SYNC_PROCESS;
txClkEn <= '1' when tx_clk_reg_d2 = '1' and tx_clk_reg_d3 = '0' else
'0';
----------------------------------------------------------------------------
-- ADJP
----------------------------------------------------------------------------
-- Adjust the packet length is it is less than minimum
----------------------------------------------------------------------------
ADJP : process(mac_tx_frame_length)
begin
if mac_tx_frame_length > MinimumPacketLength then
nibbleLength <= mac_tx_frame_length(5 to 15) & '0';
en_pad <= '0';
else
nibbleLength <= MinimumPacketLength(5 to 15) & '0';
en_pad <= '1';
end if;
end process ADJP;
nibbleLength_orig <= mac_tx_frame_length(5 to 15) & '0';
mac_tx_frame_length <= Tx_packet_length;
----------------------------------------------------------------------------
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/parityenable.vhd | 4 | 6289 | -------------------------------------------------------------------------------
-- parityenable.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity ParityEnable is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer := 4
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Enable : in std_logic;
Res : out std_logic
);
end entity ParityEnable;
architecture IMP of ParityEnable is
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
begin -- architecture IMP
Using_FPGA: if ( C_TARGET /= RTL ) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 5 generate
signal inA5 : std_logic_vector(0 to 4);
begin
Assign_InA : process (InA) is
begin
inA5 <= (others => '0');
inA5(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699600000000")
port map(
O => Res,
I0 => InA5(4),
I1 => inA5(3),
I2 => inA5(2),
I3 => inA5(1),
I4 => inA5(0),
I5 => Enable);
end generate Single_LUT6;
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
Res <= Enable and ParityGen(InA);
end generate Using_RTL;
end architecture IMP;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rx_fifo_disposer.vhd | 4 | 28176 | -----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo_disposer.vhd
--
-- Version: v1.01.a
-- Description: This
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo_disposer is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_10 : in std_logic;
Rx_100 : in std_logic;
Rmii_rx_eop : in std_logic_vector(1 downto 0);
Rmii_rx_crs : in std_logic_vector(1 downto 0);
Rmii_rx_er : in std_logic_vector(1 downto 0);
Rmii_rx_dv : in std_logic_vector(1 downto 0);
Rmii_rx_data : in std_logic_vector(7 downto 0);
Rx_fifo_mt_n : in std_logic;
Rx_fifo_rd_en : out std_logic;
Rmii2mac_crs : out std_logic;
Rmii2mac_rx_clk : out std_logic;
Rmii2mac_rx_er : out std_logic;
Rmii2mac_rx_dv : out std_logic;
Rmii2mac_rxd : out std_logic_vector(3 downto 0)
);
end rx_fifo_disposer;
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_RESET_ACTIVE -- Assertion level for Reset signal.
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo_disposer is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
-- Signal names begin with a lowercase letter. User defined types and the
-- enumerated values with a type are all uppercase letters.
-- Signals of a user-defined type should be declared after the type declaration
-- Group signals by interfaces
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_ClK_L,
IDLE_ClK_H,
RX_100_RD_FIFO_ClK_L,
RX_100_NIB_0_CLK_L,
RX_100_NIB_0_CLK_H,
RX_100_NIB_1_CLK_L,
RX_100_NIB_1_CLK_H,
RX_100_NIB_1_RD_FIFO_CLK_H,
RX_10_RD_FIFO_CLK_L,
RX_10_NIB_0_00_CLK_L,
RX_10_NIB_0_01_CLK_L,
RX_10_NIB_0_02_CLK_L,
RX_10_NIB_0_03_CLK_L,
RX_10_NIB_0_04_CLK_L,
RX_10_NIB_0_05_CLK_L,
RX_10_NIB_0_06_CLK_L,
RX_10_NIB_0_07_CLK_L,
RX_10_NIB_0_08_CLK_L,
RX_10_NIB_0_09_CLK_L,
RX_10_NIB_0_00_CLK_H,
RX_10_NIB_0_01_CLK_H,
RX_10_NIB_0_02_CLK_H,
RX_10_NIB_0_03_CLK_H,
RX_10_NIB_0_04_CLK_H,
RX_10_NIB_0_05_CLK_H,
RX_10_NIB_0_06_CLK_H,
RX_10_NIB_0_07_CLK_H,
RX_10_NIB_0_08_CLK_H,
RX_10_NIB_0_09_CLK_H,
RX_10_NIB_1_00_CLK_L,
RX_10_NIB_1_01_CLK_L,
RX_10_NIB_1_02_CLK_L,
RX_10_NIB_1_03_CLK_L,
RX_10_NIB_1_04_CLK_L,
RX_10_NIB_1_05_CLK_L,
RX_10_NIB_1_06_CLK_L,
RX_10_NIB_1_07_CLK_L,
RX_10_NIB_1_08_CLK_L,
RX_10_NIB_1_09_CLK_L,
RX_10_NIB_1_00_CLK_H,
RX_10_NIB_1_01_CLK_H,
RX_10_NIB_1_02_CLK_H,
RX_10_NIB_1_03_CLK_H,
RX_10_NIB_1_04_CLK_H,
RX_10_NIB_1_05_CLK_H,
RX_10_NIB_1_06_CLK_H,
RX_10_NIB_1_07_CLK_H,
RX_10_NIB_1_08_CLK_H,
RX_10_NIB_1_09_CLK_H,
RX_10_NIB_1_09_RD_FIFO_CLK_H
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
begin
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
-- No Concurrent Signal Assignments
------------------------------------------------------------------------------
-- State Machine SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_ClK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine NEXT_STATE_PROCESS
------------------------------------------------------------------------------
NEXT_STATE_PROCESS : process (
present_state,
Rx_100,
Rx_10,
RMII_rx_EOP,
Rmii_rx_er,
Rmii_rx_crs,
Rmii_rx_dv,
Rmii_rx_data,
Rx_fifo_mt_n--new addition of signal
)
begin
case present_state is
when IDLE_ClK_L =>
if (Rx_100 = '1') then
next_state <= RX_100_RD_FIFO_ClK_L;
elsif (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when IDLE_ClK_H =>
if (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_L;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_RD_FIFO_ClK_L =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_NIB_0_CLK_L =>
next_state <= RX_100_NIB_0_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_0_CLK_H =>
next_state <= RX_100_NIB_1_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_1_CLK_L =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1')) then
next_state <= RX_100_NIB_1_CLK_H;
else
next_state <= RX_100_NIB_1_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_RD_FIFO_CLK_H =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_RD_FIFO_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_10_NIB_0_00_CLK_L =>
next_state <= RX_10_NIB_0_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_L =>
next_state <= RX_10_NIB_0_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_L =>
next_state <= RX_10_NIB_0_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_L =>
next_state <= RX_10_NIB_0_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_L =>
next_state <= RX_10_NIB_0_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_L =>
next_state <= RX_10_NIB_0_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_L =>
next_state <= RX_10_NIB_0_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_L =>
next_state <= RX_10_NIB_0_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_L =>
next_state <= RX_10_NIB_0_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_00_CLK_H =>
next_state <= RX_10_NIB_0_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_H =>
next_state <= RX_10_NIB_0_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_H =>
next_state <= RX_10_NIB_0_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_H =>
next_state <= RX_10_NIB_0_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_H =>
next_state <= RX_10_NIB_0_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_H =>
next_state <= RX_10_NIB_0_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_H =>
next_state <= RX_10_NIB_0_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_H =>
next_state <= RX_10_NIB_0_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_H =>
next_state <= RX_10_NIB_0_09_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_H =>
next_state <= RX_10_NIB_1_00_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_1_00_CLK_L =>
next_state <= RX_10_NIB_1_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_L =>
next_state <= RX_10_NIB_1_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_L =>
next_state <= RX_10_NIB_1_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_L =>
next_state <= RX_10_NIB_1_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_L =>
next_state <= RX_10_NIB_1_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_L =>
next_state <= RX_10_NIB_1_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_L =>
next_state <= RX_10_NIB_1_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_L =>
next_state <= RX_10_NIB_1_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_L =>
next_state <= RX_10_NIB_1_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_L =>
next_state <= RX_10_NIB_1_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_00_CLK_H =>
next_state <= RX_10_NIB_1_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_H =>
next_state <= RX_10_NIB_1_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_H =>
next_state <= RX_10_NIB_1_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_H =>
next_state <= RX_10_NIB_1_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_H =>
next_state <= RX_10_NIB_1_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_H =>
next_state <= RX_10_NIB_1_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_H =>
next_state <= RX_10_NIB_1_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_H =>
next_state <= RX_10_NIB_1_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_H =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1') or (Rx_fifo_mt_n = '0')) then
next_state <= RX_10_NIB_1_09_CLK_H;
else
next_state <= RX_10_NIB_1_09_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_RD_FIFO_CLK_H =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
end case;
end process;
end simulation;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/ram16x4.vhd | 4 | 12011 | -------------------------------------------------------------------------------
-- ram16x4 - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2007, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename : ram16x4.vhd
-- Version : v4.00.a
-- Description: This is a LUT RAM design to provide 4 bits wide and 16 bits
-- deep memory structue. The initial string for rom16x4 is
-- specially designed to ease the initialization of this memory.
-- The initialization value is taken from the "INIT_XX" string.
-- Each string is read in the standard Xilinx format, which is to
-- take the right-most character as the least significant bit.
-- INIT_00 is for address 0 to address 3, INIT_01 is for address
-- 4 to address 7, ..., INIT_03 is for address 12 to address 15.
-- Uses 16 LUTs (16 RAM16x1)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity ram16x4 is
generic(
INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for addr(3 downto 0)
INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for addr(7 downto 4)
INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for addr(11 downto 8)
INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for addr(15 downto 12)
);
port(
Addr : in std_logic_vector(3 downto 0);
D : in std_logic_vector(3 downto 0);
We : in std_logic;
Clk : in std_logic;
Q : out std_logic_vector(3 downto 0));
end entity ram16x4 ;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of ram16x4 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
attribute INIT : string ;
attribute INIT of ram16x1_0 : label is GetInitString4(0, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_1 : label is GetInitString4(1, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_2 : label is GetInitString4(2, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_3 : label is GetInitString4(3, INIT_00,INIT_01,
INIT_02, INIT_03);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic ( init : bit_vector);
-- synopsys translate_on
-- synthesis translate_on
port (
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
d : in std_logic;
we : in std_logic;
wclk : in std_logic;
o : out std_logic);
end component;
begin
-----------------------------------------------------------------------------
-- RAM 0
-----------------------------------------------------------------------------
ram16x1_0 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(0, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(0), we => We, wclk => Clk, o => Q(0));
-----------------------------------------------------------------------------
-- RAM 1
-----------------------------------------------------------------------------
ram16x1_1 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(1, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(1), we => We, wclk => Clk, o => Q(1));
-----------------------------------------------------------------------------
-- RAM 2
-----------------------------------------------------------------------------
ram16x1_2 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(2, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(2), we => We, wclk => Clk, o => Q(2));
-----------------------------------------------------------------------------
-- RAM 3
-----------------------------------------------------------------------------
ram16x1_3 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(3, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(3), we => We, wclk => Clk, o => Q(3));
end imp;
| gpl-3.0 |
AlistairCheeseman/WindTunnelApparatus | Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rmii_tx_agile.vhd | 4 | 17992 | -----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rmii_tx_agile.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_GEN1 -- description of generic, if description doesn't fit
-- -- align with first part of description
-- C_GEN2 -- description of generic
--
-- Definition of Ports:
-- Port_name1 -- description of port, indicate source or destination
-- Port_name2 -- description of port
--
------------------------------------------------------------------------------
entity rmii_tx_agile is
generic (
C_RESET_ACTIVE : std_logic := '0'
);
port (
Tx_speed_100 : in std_logic;
------------------ System Signals -------------------------------
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
------------------ MII <--> RMII --------------------------------
Mac2Rmii_tx_en : in std_logic;
Mac2Rmii_txd : in std_logic_vector(3 downto 0);
Mac2Rmii_tx_er : in std_logic;
Rmii2Mac_tx_clk : out std_logic;
------------------ RMII <--> PHY --------------------------------
Rmii2Phy_txd : out std_logic_vector(1 downto 0);
Rmii2Phy_tx_en : out std_logic
);
end rmii_tx_agile;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of rmii_tx_agile is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should be
-- collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a register.
-- If no constants are required, simply state this in a comment below the file
-- section separation comments.
------------------------------------------------------------------------------
-- No Constants
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_CLK_L,
IDLE_CLK_H,
TX100_DIBIT_0_CLK_L,
TX100_DIBIT_1_CLK_H,
TX10_DIBIT_0_CLK_L0,
TX10_DIBIT_0_CLK_L1,
TX10_DIBIT_0_CLK_L2,
TX10_DIBIT_0_CLK_L3,
TX10_DIBIT_0_CLK_L4,
TX10_DIBIT_0_CLK_L5,
TX10_DIBIT_0_CLK_L6,
TX10_DIBIT_0_CLK_L7,
TX10_DIBIT_0_CLK_L8,
TX10_DIBIT_0_CLK_L9,
TX10_DIBIT_1_CLK_H0,
TX10_DIBIT_1_CLK_H1,
TX10_DIBIT_1_CLK_H2,
TX10_DIBIT_1_CLK_H3,
TX10_DIBIT_1_CLK_H4,
TX10_DIBIT_1_CLK_H5,
TX10_DIBIT_1_CLK_H6,
TX10_DIBIT_1_CLK_H7,
TX10_DIBIT_1_CLK_H8,
TX10_DIBIT_1_CLK_H9
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
signal mac2Rmii_tx_en_d : std_logic;
signal mac2Rmii_txd_d : std_logic_vector(3 downto 0);
signal mac2Rmii_tx_er_d : std_logic;
signal tx_in_reg_en : std_logic;
signal txd_dibit : std_logic;
signal txd_error : std_logic;
begin
------------------------------------------------------------------------------
-- TX_IN_REG_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
TX_IN_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
mac2Rmii_tx_en_d <= '0';
mac2Rmii_txd_d <= (others => '0');
mac2Rmii_tx_er_d <= '0';
elsif (tx_in_reg_en = '1') then
mac2Rmii_tx_en_d <= Mac2Rmii_tx_en;
mac2Rmii_txd_d <= Mac2Rmii_txd;
mac2Rmii_tx_er_d <= Mac2Rmii_tx_er;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_OUT_REG_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
TX_OUT_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rmii2Phy_txd(0) <= '0';
Rmii2Phy_txd(1) <= '0';
Rmii2Phy_tx_en <= '0';
elsif (txd_dibit = '0') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(0) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(1) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
elsif (txd_dibit = '1') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(2) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(3) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
TX_CONTROL_SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_CLK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_NEXT_STATE_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
TX_CONTROL_NEXT_STATE_PROCESS : process (
present_state,
mac2Rmii_tx_er_d,
Tx_speed_100--new addition of signals
)
begin
case present_state is
when IDLE_CLK_L =>
next_state <= IDLE_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '0';
txd_error <= '0';
when IDLE_CLK_H =>
if (Tx_speed_100 = '1') then
next_state <= TX100_DIBIT_0_CLK_L;
else
next_state <= TX10_DIBIT_0_CLK_L0;
end if;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX100_DIBIT_0_CLK_L =>
next_state <= TX100_DIBIT_1_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= mac2Rmii_tx_er_d;
when TX100_DIBIT_1_CLK_H =>
next_state <= TX100_DIBIT_0_CLK_L;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= mac2Rmii_tx_er_d;
when TX10_DIBIT_0_CLK_L0 =>
next_state <= TX10_DIBIT_0_CLK_L1;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L1 =>
next_state <= TX10_DIBIT_0_CLK_L2;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L2 =>
next_state <= TX10_DIBIT_0_CLK_L3;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L3 =>
next_state <= TX10_DIBIT_0_CLK_L4;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L4 =>
next_state <= TX10_DIBIT_0_CLK_L5;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L5 =>
next_state <= TX10_DIBIT_0_CLK_L6;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L6 =>
next_state <= TX10_DIBIT_0_CLK_L7;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L7 =>
next_state <= TX10_DIBIT_0_CLK_L8;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L8 =>
next_state <= TX10_DIBIT_0_CLK_L9;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L9 =>
next_state <= TX10_DIBIT_1_CLK_H0;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H0 =>
next_state <= TX10_DIBIT_1_CLK_H1;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H1 =>
next_state <= TX10_DIBIT_1_CLK_H2;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H2 =>
next_state <= TX10_DIBIT_1_CLK_H3;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H3 =>
next_state <= TX10_DIBIT_1_CLK_H4;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H4 =>
next_state <= TX10_DIBIT_1_CLK_H5;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H5 =>
next_state <= TX10_DIBIT_1_CLK_H6;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H6 =>
next_state <= TX10_DIBIT_1_CLK_H7;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H7 =>
next_state <= TX10_DIBIT_1_CLK_H8;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H8 =>
next_state <= TX10_DIBIT_1_CLK_H9;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H9 =>
next_state <= TX10_DIBIT_0_CLK_L0;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
end case;
end process;
end simulation;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/memlib/tb/tbd_fifo_simple_dram.vhd | 1 | 2014 | -- $Id: tbd_fifo_simple_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbd_fifo_simple_dram - syn
-- Description: Wrapper for fifo_simple_dram to avoid records & generics. It
-- has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: fifo_simple_dram
--
-- To test: fifo_simple_dram
--
-- Target Devices: generic
--
-- Tool versions: xst 14.7; viv 2017.2; ghdl 0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-09 1109 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.memlib.all;
entity tbd_fifo_simple_dram is -- fifo, CE/WE, dram based [tb design]
-- generic: AWIDTH=4; DWIDTH=16
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE : in slbit; -- clock enable
WE : in slbit; -- write enable
DI : in slv16; -- input data
DO : out slv16; -- output data
EMPTY : out slbit; -- fifo empty status
FULL : out slbit; -- fifo full status
SIZE : out slv4 -- number of used slots
);
end tbd_fifo_simple_dram;
architecture syn of tbd_fifo_simple_dram is
begin
FIFO : fifo_simple_dram
generic map (
AWIDTH => 4,
DWIDTH => 16)
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
WE => WE,
DI => DI,
DO => DO,
EMPTY => EMPTY,
FULL => FULL,
SIZE => SIZE
);
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/rbus/rb_sres_or_2.vhd | 1 | 2012 | -- $Id: rb_sres_or_2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_2 - syn
-- Description: rbus result or, 2 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
-- 2008-01-20 113 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sres_or_2 is -- rbus result or, 2 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_2;
architecture syn of rb_sres_or_2 is
begin
proc_comb : process (RB_SRES_1, RB_SRES_2)
begin
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => rb_sres_init,
RB_SRES_4 => rb_sres_init
);
-- synthesis translate_on
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/memlib/fifo_simple_dram.vhd | 1 | 5533 | -- $Id: fifo_simple_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fifo_simple_dram - syn
-- Description: FIFO, CE/WE interface, distributed RAM based
--
-- Dependencies: ram_1swar_gen
--
-- Test bench: tb/tb_fifo_simple_dram
-- Target Devices: generic Spartan, Artix
-- Tool versions: ise 14.7; viv 2017.2-2018.3; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-09 1109 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.memlib.all;
entity fifo_simple_dram is -- fifo, CE/WE interface, dram based
generic (
AWIDTH : positive := 6; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE : in slbit; -- clock enable
WE : in slbit; -- write enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
EMPTY : out slbit; -- fifo empty status
FULL : out slbit; -- fifo full status
SIZE : out slv(AWIDTH-1 downto 0) -- number of used slots
);
end fifo_simple_dram;
architecture syn of fifo_simple_dram is
type regs_type is record
waddr : slv(AWIDTH-1 downto 0); -- write address
raddr : slv(AWIDTH-1 downto 0); -- read address
empty : slbit; -- empty flag
full : slbit; -- full flag
end record regs_type;
constant memsize : positive := 2**AWIDTH;
constant regs_init : regs_type := (
slv(to_unsigned(0,AWIDTH)), -- waddr
slv(to_unsigned(0,AWIDTH)), -- raddr
'1','0' -- empty,full
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal RAM_WE : slbit := '0';
signal RAM_ADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
RAM : ram_1swar_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLK,
WE => RAM_WE,
ADDR => RAM_ADDR,
DI => DI,
DO => DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RESET, CE, WE)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iram_we : slbit := '0';
variable iram_addr : slv(AWIDTH-1 downto 0) := (others=>'0');
variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
iram_we := '0';
if WE = '1' then -- select RAM address
iram_addr := r.waddr; -- for write
else
iram_addr := r.raddr; -- for read
end if;
isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
if CE = '1' then -- do read or write
if WE = '1' then -- do write
if r.full = '0' then -- only if not full
iram_we := '1'; -- assert write enable
n.waddr := slv(unsigned(r.waddr) + 1); -- advance address
n.empty := '0'; -- can't be empty after write
if unsigned(isize) = memsize-2 then -- check for full
n.full := '1';
end if;
end if;
else -- do read
if r.empty = '0' then -- only if not empty
n.raddr := slv(unsigned(r.raddr) + 1); -- advance address
n.full := '0'; -- can't be full after read
if unsigned(isize) = 1 then -- check for empty
n.empty := '1';
end if;
end if;
end if;
end if;
N_REGS <= n;
RAM_ADDR <= iram_addr;
RAM_WE <= iram_we;
EMPTY <= r.empty;
FULL <= r.full;
SIZE <= isize;
end process proc_next;
-- synthesis translate_off
proc_moni: process (CLK)
variable oline : line;
begin
if rising_edge(CLK) then
if RESET='0' and CE='1' then -- not in reset and active
if WE = '0' then
if R_REGS.empty='1' then -- read on empty fifo
write(oline, now, right, 12);
write(oline, string'(" read on empty fifo - FAIL in "));
write(oline, fifo_simple_dram'path_name);
writeline(output, oline);
end if;
else
if R_REGS.full='1' then -- write on full fifo
write(oline, now, right, 12);
write(oline, string'(" write on full fifo - FAIL in "));
write(oline, fifo_simple_dram'path_name);
writeline(output, oline);
end if;
end if;
end if;
end if;
end process proc_moni;
-- synthesis translate_on
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/bplib/arty/tb/tb_arty_dram.vhd | 1 | 5635 | -- $Id: tb_arty_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_arty_dram - sim
-- Description: Test bench for arty (base+dram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_arty_core
-- serport/tb/serport_master_tb
-- arty_dram_aif [UUT]
--
-- To test: generic, any arty_dram_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.1.1 use sfs_gsim_core
-- 2018-10-28 1063 1.0 Initial version (derived from tb_arty)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.artylib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_arty_dram is
end tb_arty_dram;
architecture sim of tb_arty_dram is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv4 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv4 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_RGBLED2 : slv3 := (others=>'0');
signal O_RGBLED3 : slv3 := (others=>'0');
signal IO_DDR3_DQ : slv16 := (others=>'Z');
signal IO_DDR3_DQS_P : slv2 := (others=>'Z');
signal IO_DDR3_DQS_N : slv2 := (others=>'Z');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
GINIT : entity work.gsr_pulse;
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
ARTYCORE : entity work.tb_arty_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN
);
UUT : arty_dram_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_RGBLED2 => O_RGBLED2,
O_RGBLED3 => O_RGBLED3,
A_VPWRN => (others=>'0'),
A_VPWRP => (others=>'0'),
DDR3_DQ => IO_DDR3_DQ,
DDR3_DQS_P => IO_DDR3_DQS_P,
DDR3_DQS_N => IO_DDR3_DQS_N,
DDR3_ADDR => open,
DDR3_BA => open,
DDR3_RAS_N => open,
DDR3_CAS_N => open,
DDR3_WE_N => open,
DDR3_RESET_N => open,
DDR3_CK_P => open,
DDR3_CK_N => open,
DDR3_CKE => open,
DDR3_CS_N => open,
DDR3_DM => open,
DDR3_ODT => open
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
--
-- Notes on portsel and XON control:
-- - most arty designs will use hardwired XON=1
-- - but some (especially basis tests) might not use flow control
-- - that's why XON flow control must be optional and configurable !
--
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 |
wfjm/w11 | rtl/bplib/bpgen/bpgenrbuslib.vhd | 1 | 6141 | -- $Id: bpgenrbuslib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: bpgenrbuslib
-- Description: Generic Board/Part components using rbus
--
-- Dependencies: -
-- Tool versions: ise 12.1-14.7; viv 2014.4-2019.1; ghdl 0.26-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-11 912 1.3.2 add sn_humanio_emu_rbus
-- 2017-06-05 907 1.3.1 rgbdrv_analog_rbus: add ACTLOW generic
-- 2016-02-20 734 1.3 add rgbdrv_analog_rbus
-- 2015-01-25 637 1.2 add generics to sn_humanio_rbus
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
-- 2013-01-26 476 1.0 Initial version (extracted from bpgenlib)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
package bpgenrbuslib is
component bp_swibtnled_rbus is -- swi,btn,led handling /w rbus icept
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end component;
component sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: disp: segments (act.low)
);
end component;
component sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus
generic (
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end component;
component sn_humanio_emu_rbus is -- sn_humanio rbus emulator
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
DSP_DP : in slv((2**DCWIDTH)-1 downto 0) -- display decimal points
);
end component;
component rgbdrv_analog_rbus is -- rgb analog from rbus
generic (
DWIDTH : positive := 8; -- dimmer width
ACTLOW : slbit := '0'; -- invert output polarity
RB_ADDR : slv16 := x"0000");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RGBCNTL : in slv3; -- rgb control
DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
O_RGBLED : out slv3 -- pad-o: rgb led
);
end component;
end package bpgenrbuslib;
| gpl-3.0 |
wfjm/w11 | rtl/bplib/sysmon/sysmon_rbus_core.vhd | 1 | 12991 | -- $Id: sysmon_rbus_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sysmon_rbus_core - syn
-- Description: SYSMON interface to rbus (generic)
--
-- Dependencies: -
--
-- Test bench: -
--
-- Target Devices: generic (all with SYSMON or XADC)
-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-25 767 1.0.1 don't init N_REGS (vivado fix for fsm inference)
-- BUGFIX: use s_init in regs_init (was s_idle)
-- 2016-03-12 741 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers:
-- - in general 1-to-1 mapping to sysmon/xadc address space
-- --> see function in sysmon/xadc user guide
-- - 8 addresses are implemented on the controller (base is ibase, default x"78")
-- --> see function below
--
-- Addr Bits Name r/w/f Function
-- 000 cntl -/-/f cntl
-- 15 reset -/-/f reset SYSMON
-- 001 stat r/w/- stat
-- 3 jlock r/c/- JTAGLOCKED seen
-- 2 jmod r/c/- JTAGMODIFIED seen
-- 1 jbusy r/c/- JTAGBUSY seen
-- 0 ot r/c/- OT seen
-- 010 almh r/w/- alm history
-- *:00 alm r/c/- ALM(*:0) seen
-- 011 -/-/- <unused>
-- 100 temp r/-/- current temp value
-- 101 alm r/-/- current alm value
-- *:00 alm r/-/- alm(*:0)
-- 110 -/-/- <unused>
-- 111 eos r/-/- eos counter
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.sysmonrbuslib.all;
-- ----------------------------------------------------------------------------
entity sysmon_rbus_core is -- SYSMON interface to rbus
generic (
DAWIDTH : positive := 7; -- drp address bus width
ALWIDTH : positive := 8; -- alm width
TEWIDTH : positive := 12; -- temp width
IBASE : slv8 := x"78"; -- base of controller register window
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SM_DEN : out slbit; -- sysmon: drp enable
SM_DWE : out slbit; -- sysmon: drp write enable
SM_DADDR : out slv(DAWIDTH-1 downto 0); -- sysmon: drp address
SM_DI : out slv16; -- sysmon: data input
SM_DO : in slv16; -- sysmon: data output
SM_DRDY : in slbit; -- sysmon: data ready
SM_EOS : in slbit; -- sysmon: end of scan
SM_RESET : out slbit; -- sysmon: reset
SM_ALM : in slv(ALWIDTH-1 downto 0);-- sysmon: alarms
SM_OT : in slbit; -- sysmon: overtemperature
SM_JTAGBUSY : in slbit; -- sysmon: JTAGBUSY
SM_JTAGLOCKED : in slbit; -- sysmon: JTAGLOCKED
SM_JTAGMODIFIED : in slbit; -- sysmon: JTAGMODIFIED
TEMP : out slv(TEWIDTH-1 downto 0) -- die temp
);
end sysmon_rbus_core;
architecture syn of sysmon_rbus_core is
type state_type is (
s_init, -- init: wait for jtaglocked down
s_idle, -- idle: dispatch
s_wait, -- wait: wait on drdy
s_twait -- twait: wait on drdy of temp read
);
type regs_type is record
rbsel : slbit; -- rbus select
state : state_type; -- state
eoscnt : slv16; -- eos counter
stat_ot : slbit; -- stat: ot
stat_jlock : slbit; -- stat: jtag locked
stat_jmod : slbit; -- stat: jtag modified
stat_jbusy : slbit; -- stat: jtag busy
almh : slv(ALWIDTH-1 downto 0); -- almh
temp : slv(TEWIDTH-1 downto 0); -- temp value
tpend : slbit; -- temp pending
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
s_init, -- state
(others=>'0'), -- eoscnt
'0','0','0','0', -- stat_ot, stat_j*
slv(to_unsigned(0,ALWIDTH)), -- almh
slv(to_unsigned(0,TEWIDTH)), -- temp
'0' -- tpend
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
-- only internal regs have names, only 3 LSB in constant
constant rbaddr_cntl: slv3 := "000"; -- 0 -/-/f
constant rbaddr_stat: slv3 := "001"; -- 1 r/w/-
constant rbaddr_almh: slv3 := "010"; -- 2 r/w/-
constant rbaddr_temp: slv3 := "100"; -- 4 r/-/-
constant rbaddr_alm: slv3 := "101"; -- 5 r/-/-
constant rbaddr_eos: slv3 := "111"; -- 7 r/-/-
constant cntl_rbf_reset: integer := 15;
constant stat_rbf_jlock: integer := 3;
constant stat_rbf_jmod: integer := 2;
constant stat_rbf_jbusy: integer := 1;
constant stat_rbf_ot: integer := 0;
begin
assert DAWIDTH=7 or DAWIDTH=8
report "assert(DAWIDTH=7 or DAWIDTH=8): unsupported DAWIDTH"
severity failure;
assert ALWIDTH<=16
report "assert ALWIDTH<16: unsupported ALWIDTH"
severity failure;
assert TEWIDTH=10 or TEWIDTH=12
report "assert(TEWIDTH=10 or TEWIDTH=12): unsupported TEWIDTH"
severity failure;
assert IBASE(2 downto 0) = "000"
report "assert IBASE(2:0) = 000: invalid IBASE"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, SM_DO, SM_DRDY, SM_EOS, SM_ALM, SM_OT,
SM_JTAGLOCKED, SM_JTAGMODIFIED, SM_JTAGBUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable irb_addr_ext : slbit := '0';
variable irb_addr_int : slbit := '0';
variable ism_den : slbit := '0';
variable ism_dwe : slbit := '0';
variable ism_daddr : slv(DAWIDTH-1 downto 0) := (others=>'0');
variable ism_reset : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- check for internal rbus controller register window
irb_addr_int := '0';
if RB_MREQ.addr(DAWIDTH-1 downto 3) = IBASE(DAWIDTH-1 downto 3) then
irb_addr_int := '1';
end if;
ism_den := '0';
ism_dwe := '0';
ism_daddr := RB_MREQ.addr(DAWIDTH-1 downto 0); -- default
ism_reset := '0';
-- handle EOS
if SM_EOS = '1' then
n.tpend := '1'; -- queue temp read
n.eoscnt := slv(unsigned(r.eoscnt) + 1); -- and count it
end if;
-- update stat and almh register fields
n.stat_ot := r.stat_ot or SM_OT;
n.stat_jlock := r.stat_jlock or SM_JTAGLOCKED;
n.stat_jmod := r.stat_jmod or SM_JTAGMODIFIED;
n.stat_jbusy := r.stat_jbusy or SM_JTAGBUSY;
n.almh := r.almh or SM_ALM;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 7)=RB_ADDR(15 downto 7) then
n.rbsel := '1';
end if;
irb_ack := r.rbsel and irbena; -- ack all accesses
irb_busy := irb_ack; -- busy is default
-- internal state machine
case r.state is
when s_init => -- init: wait for jtaglocked down ----
if SM_JTAGLOCKED = '0' then
n.stat_jlock := '0'; -- clear status
n.state := s_idle; -- start working
end if;
when s_idle => -- idle: dispatch --------------------
if r.tpend = '1' then -- temp update pending ?
n.tpend := '0'; -- mark done
if SM_JTAGLOCKED = '0' then -- if not jlocked
ism_daddr := "0000000"; -- temp is reg 00h
ism_dwe := '0'; -- do read
ism_den := '1'; -- start drp cycle
n.state := s_twait;
end if;
elsif r.rbsel = '1' then -- rbus access ?
if irb_addr_int ='1' then -- internal controller regs
irb_busy := '0';
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we = '1' then
ism_reset := RB_MREQ.din(cntl_rbf_reset);
end if;
when rbaddr_stat =>
if RB_MREQ.we = '1' then
n.stat_jlock := r.stat_jlock and
not RB_MREQ.din(stat_rbf_jlock);
n.stat_jmod := r.stat_jmod and
not RB_MREQ.din(stat_rbf_jmod);
n.stat_jbusy := r.stat_jbusy and
not RB_MREQ.din(stat_rbf_jbusy);
n.stat_ot := r.stat_ot and
not RB_MREQ.din(stat_rbf_ot);
end if;
when rbaddr_almh =>
if RB_MREQ.we = '1' then
n.almh := r.almh and not RB_MREQ.din(r.almh'range);
end if;
when rbaddr_temp =>
irb_err := RB_MREQ.we;
when rbaddr_alm =>
irb_err := RB_MREQ.we;
when rbaddr_eos =>
irb_err := RB_MREQ.we;
when others =>
irb_err := irbena;
end case;
else -- sysmon reg access
if irbena = '1' then
if SM_JTAGLOCKED = '0' then -- if not jlocked
ism_daddr := RB_MREQ.addr(ism_daddr'range);
ism_dwe := RB_MREQ.we;
ism_den := '1'; -- start drp cycle
n.state := s_wait;
else
irb_err := '1'; -- quit with error if jlocked
end if;
end if;
end if;
end if;
when s_wait => -- wait: wait on drdy ----------------
n.state := s_wait;
if SM_DRDY = '1' then
irb_busy := '0';
n.state := s_idle;
end if;
when s_twait => -- twait: wait on drdy of temp read --
n.state := s_twait;
if SM_DRDY = '1' then
n.temp := SM_DO(15 downto 16-TEWIDTH); -- take msb's
n.state := s_idle;
end if;
when others => null; -- <> ------------------------------
end case; -- case r.state
-- rbus output driver
if r.rbsel = '1' then
if irb_addr_int = '1' then
case RB_MREQ.addr(2 downto 0) is
when rbaddr_stat =>
irb_dout(stat_rbf_jlock) := r.stat_jlock;
irb_dout(stat_rbf_jmod) := r.stat_jmod;
irb_dout(stat_rbf_jbusy) := r.stat_jbusy;
irb_dout(stat_rbf_ot) := r.stat_ot;
when rbaddr_almh =>
irb_dout(r.almh'range) := r.almh;
when rbaddr_temp =>
irb_dout(r.temp'range) := r.temp;
when rbaddr_alm =>
irb_dout(SM_ALM'range) := SM_ALM;
when rbaddr_eos =>
irb_dout := r.eoscnt;
when others =>
irb_dout := (others=>'0');
end case;
else
irb_dout := SM_DO;
end if;
end if;
N_REGS <= n;
SM_DEN <= ism_den;
SM_DWE <= ism_dwe;
SM_DADDR <= ism_daddr;
SM_DI <= RB_MREQ.din;
SM_RESET <= ism_reset;
TEMP <= r.temp;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
| gpl-3.0 |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01100_bad.vhd | 1 | 2858 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01100_bad.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of ports direction inside entity port name: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity CNE_01100_bad is
port (
Clock : in std_logic; -- Clock signal
Reset_n : in std_logic; -- Reset signal
D : in std_logic; -- D Flip-Flop input signal
Q : out std_logic -- D Flip-Flop output signal
);
end CNE_01100_bad;
--CODE
architecture Behavioral of CNE_01100_bad is
signal Q_temp : std_logic; -- D Flip-Flop output
begin
-- D FlipFlop process
P_FlipFlop:process(Clock, Reset_n)
begin
if (Reset_n='0') then
Q_temp <= '0';
elsif (rising_edge(Clock)) then
Q_temp <= D;
end if;
end process;
Q <= Q_temp;
end Behavioral; | gpl-3.0 |
wfjm/w11 | rtl/sys_gen/w11a/artys7_bram/tb/tb_w11a_br_as7.vhd | 1 | 785 | -- $Id: tb_w11a_br_as7.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_br_as7
-- Description: Configuration for tb_w11a_br_as7 for tb_artys7
--
-- Dependencies: sys_w11a_br_as7
--
-- To test: sys_w11a_br_as7
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-08-11 1038 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_w11a_br_as7 of tb_artys7 is
for sim
for all : artys7_aif
use entity work.sys_w11a_br_as7;
end for;
end for;
end tb_w11a_br_as7;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/genlib/clkdivce.vhd | 1 | 3235 | -- $Id: clkdivce.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: clkgen - syn
-- Description: Generate usec and msec enable signals
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 418 1.0.3 now numeric_std clean
-- 2008-01-20 112 1.0.2 rename clkgen->clkdivce; remove SYS_CLK port
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
-- Note: for test bench usage a copy of the clkdivce entity, with _tb
-- appended to the name, has been created in the /tb sub folder.
-- Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity clkdivce is -- generate usec/msec ce pulses
generic (
CDUWIDTH : positive := 6; -- usec clock divider width
USECDIV : positive := 50; -- divider ratio for usec pulse
MSECDIV : positive := 1000); -- divider ratio for msec pulse
port (
CLK : in slbit; -- input clock
CE_USEC : out slbit; -- usec pulse
CE_MSEC : out slbit -- msec pulse
);
end clkdivce;
architecture syn of clkdivce is
type regs_type is record
ucnt : slv(CDUWIDTH-1 downto 0); -- usec clock divider counter
mcnt : slv10; -- msec clock divider counter
usec : slbit; -- usec pulse
msec : slbit; -- msec pulse
end record regs_type;
constant regs_init : regs_type := (
slv(to_unsigned(USECDIV-1,CDUWIDTH)),
slv(to_unsigned(MSECDIV-1,10)),
'0','0'
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024
report "assert(USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024): " &
"USECDIV too large for given CDUWIDTH or MSECDIV>1024"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
n.usec := '0';
n.msec := '0';
n.ucnt := slv(unsigned(r.ucnt) - 1);
if unsigned(r.ucnt) = 0 then
n.usec := '1';
n.ucnt := slv(to_unsigned(USECDIV-1,CDUWIDTH));
n.mcnt := slv(unsigned(r.mcnt) - 1);
if unsigned(r.mcnt) = 0 then
n.msec := '1';
n.mcnt := slv(to_unsigned(MSECDIV-1,10));
end if;
end if;
N_REGS <= n;
CE_USEC <= r.usec;
CE_MSEC <= r.msec;
end process proc_next;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/ibus/sys_conf.vhd | 1 | 1911 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Default definitions for ibdr_maxisys
--
-- Dependencies: -
-- Tool versions: xst 14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-05-04 1146 1.1.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.1 use typ for DL,PC,LP; add dz11
-- 2018-09-08 1043 1.0.2 add sys_conf_ibd_kw11p
-- 2017-01-29 847 1.0.1 add sys_conf_ibd_deuna
-- 2015-03-14 658 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 4; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 4; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 5; -- DZ11
constant sys_conf_ibd_pc11 : integer := 4; -- PC11
constant sys_conf_ibd_lp11 : integer := 5; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
end package sys_conf;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd | 1 | 2926 | -- $Id: ram_1swsr_wfirst_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_1swsr_rfirst_gen - syn
-- Description: Single-Port RAM with with one synchronous read/write port
-- and 'read-through' semantics (as block RAM).
-- The 'ram_style' attribute is set to 'block', this will
-- force in XST a synthesis as block RAM.
--
-- Notes: For xst 8.1.03i: can be written with a signal or a shared
-- variable declared at the architecture level. Use variable
-- because this seemed better for simulation. Using a simple
-- variable declared at process level leads to an array of
-- registers and a big mux.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.4 now numeric_std clean
-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
-- 2008-03-02 122 1.0.1 change generic default for BRAM models
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w ports, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end ram_1swsr_wfirst_gen;
architecture syn of ram_1swsr_wfirst_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0);
shared variable sv_ram : ram_type := (others=>datzero);
attribute ram_style : string;
attribute ram_style of sv_ram : variable is "block";
signal R_DO : slv(DWIDTH-1 downto 0) := datzero;
begin
proc_clk: process (CLK)
begin
if rising_edge(CLK) then
if EN = '1' then
if WE = '1' then
sv_ram(to_integer(unsigned(ADDR))) := DI;
end if;
R_DO <= sv_ram(to_integer(unsigned(ADDR)));
end if;
end if;
end process proc_clk;
DO <= R_DO;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd | 1 | 1993 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_b3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-28 754 1.2 run at 120 MHz
-- 2016-03-12 741 1.1 add sysmon_rbus
-- 2016-02-26 735 1.0.2 use s7_cmt_sfs
-- 2015-01-16 636 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure further units -------------------------------------------------
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys2/sys_conf2.vhd | 1 | 1130 | -- $Id: sys_conf2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-25 419 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkudiv_usecdiv : integer := 100; -- default usec
constant sys_conf_clksdiv_usecdiv : integer := 60; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200
end package sys_conf;
| gpl-3.0 |
wfjm/w11 | rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd | 1 | 27540 | -- $Id: nx_cram_memctl_as.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nx_cram_memctl_as - syn
-- Description: nexys2/3/4: CRAM controller - async and page mode
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- Test bench: tb/tb_nx_cram_memctl_as
-- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
-- sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3
-- sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4
-- Target Devices: generic
-- Tool versions: ise 11.4-14.7; viv 2014.4-2019.1; ghdl 0.26-0.36
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2016-07-03 783 2016.3 xc7a100t-1 91 87 0 0 43
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2016-07-03 767 14.7 131013 xc6slx16-2 100 134 0 60 s 4.2
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 100 0 96 s 6.7
-- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7
-- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-08-17 1203 2.1.1 fix for ghdl V0.36 -Whide warnings
-- 2016-07-16 788 2.1 change *DELAY generics, now absolute delay cycles
-- add s_init1; drop "KEEP" for data (better for dbg)
-- 2016-07-10 786 2.0 add page mode support
-- 2016-05-22 767 1.2.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-12-26 718 1.2.1 BUGFIX: do_dispatch(): always define imem_oe
-- 2011-11-26 433 1.2 renamed from n2_cram_memctl_as
-- 2011-11-19 432 1.1 remove O_FLA_CE_N port
-- 2011-11-19 427 1.0.5 now numeric_std clean
-- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics
-- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read
-- cycle;
-- 2010-05-30 297 1.0.2 use READ(0|1)DELAY generic
-- 2010-05-24 294 1.0.1 more compact n.memdi logic; extra wait in s_rdwait1
-- 2010-05-23 293 1.0 Initial version
--
-- Notes:
-- 1. There is no 'bus-turn-around' cycle needed for a write->read change
-- FPGA_OE goes 1->0 and MEM_OE goes 0->1 on the s_wrput1->s_rdinit
-- transition simultaneously. The FPGA will go high-Z quickly, the memory
-- low-Z delay by the IOB and internal memory delays. No clash.
-- 2. There is a hidden 'bus-turn-around' cycle for a read->write change.
-- MEM_OE goes 1->0 on s_rdget1->s_wrinit and the memory will go high-z with
-- some delay. FPGA_OE goes 0->1 in the next cycle at s_wrinit->s_wrwait0.
-- Again no clash due to the 1 cycle delay.
--
-- Nominal timings:
-- READ0 = (T_aa + ext_read_delay) in cycles
-- READ1 = (T_pa + ext_read_delay) in cycles
-- WRITE = (T_aa + ext_write_delay) in cycles
-- with
-- ext_read_delay: output_IOB + 2*PCB_delay + input_IOB + skew
-- ext_write_delay: skew
--
--
-- Timing of some signals:
--
-- single read request:
--
-- state |_idle |_rdinit|_rdwt0 |_rdwt0 |_rdget0|_rdwt1 |_rdget1|
-- 0 20 40 60 80 100 120
-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
--
-- REQ _______|^^^^^|_____________________________________________
-- WE ___________________________________________________________
--
-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
-- IOB_OE _________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
--
-- DO oooooooooooooooooooooooooooooooooooooooooo|lllllll|lllllll|h
-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|________________
-- ACK_R ___________________________________________________________|^^^^^^^|_
--
-- single write request:
--
-- state |_idle |_wrinit|_wrwt0 |_wrwt0 |_wrwt0 |_wrput0|_idle |
-- 0 20 40 60 80 100 120
-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
--
-- REQ _______|^^^^^|______________________________________
-- WE _______|^^^^^|______________________________________
--
-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
-- IOB_BE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
-- IOB_OE ____________________________________________________
-- IOB_WE ______________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_____
--
-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_________
-- ACK_W __________________________________________|^^^^^^^|_
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
entity nx_cram_memctl_as is -- CRAM controller (async+page mode)
generic (
READ0DELAY : positive := 4; -- read word 0 delay in clock cycles
READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
WRITEDELAY : positive := 4); -- write delay in clock cycles
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv22; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end nx_cram_memctl_as;
architecture syn of nx_cram_memctl_as is
type state_type is (
s_init, -- s_init: startup state
s_init1, -- s_init1: reset released
s_wcinit, -- s_wcinit: write rcr init
s_wcwait, -- s_wcwait: write rcr wait
s_wcput, -- s_wcput: write rcr done
s_rainit, -- s_rainit: read array init
s_rawait, -- s_rawait: wait read array
s_idle, -- s_idle: wait for req
s_rdinit, -- s_rdinit: read init cycle
s_rdwait0, -- s_rdwait0: read wait low word
s_rdget0, -- s_rdget0: read get low word
s_rdwait1, -- s_rdwait1: read wait high word
s_rdget1, -- s_rdget1: read get high word
s_wrinit, -- s_wrinit: write init cycle
s_wrwait0, -- s_rdwait0: write wait 1st word
s_wrput0, -- s_rdput0: write put 1st word
s_wrini1, -- s_wrini1: write init 2nd word
s_wrwait1, -- s_wrwait1: write wait 2nd word
s_wrput1 -- s_wrput1: write put 2nd word
);
type regs_type is record
state : state_type; -- state
ackr : slbit; -- signal ack_r
addr0 : slbit; -- current addr0
be2nd : slv2; -- be's of 2nd write cycle
cntdly : slv3; -- wait delay counter
cntce : slv7; -- ce counter
fidle : slbit; -- force idle flag
memdo0 : slv16; -- mem data out, low word
memdi : slv32; -- mem data in
end record regs_type;
constant regs_init : regs_type := (
s_init, -- state
'0', -- ackr
'0', -- addr0
"00", -- be2nd
(others=>'0'), -- cntdly
(others=>'0'), -- cntce
'0', -- fidle
(others=>'0'), -- memdo0
(others=>'0') -- memdi
);
constant c_addrh_rcr_setup : slv22 :=
"000" & -- 22:20 reserved MBZ
"00" & -- 19:18 reg sel 00=RCR
"0000000000" & -- 17: 8 reserved MBZ
'1' & -- 7 page mode enable (1=enable)
"00" & -- 6: 5 reserved MBZ
'1' & -- 4 dpd disaable (1=disable)
"000"; -- 3: 1 rest is reserved or PAR, which should be 0
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal CLK_180 : slbit := '0';
signal MEM_CE_N : slbit := '1';
signal MEM_BE_N : slv2 := "11";
signal MEM_WE_N : slbit := '1';
signal MEM_OE_N : slbit := '1';
signal MEM_CRE : slbit := '0';
signal BE_CE : slbit := '0';
signal ADDRH_CE : slbit := '0';
signal ADDR0_CE : slbit := '0';
signal ADDRH : slv22 := (others=>'0');
signal ADDR0 : slbit := '0';
signal DATA_CEI : slbit := '0';
signal DATA_CEO : slbit := '0';
signal DATA_OE : slbit := '0';
signal MEM_DO : slv16 := (others=>'0');
signal MEM_DI : slv16 := (others=>'0');
begin
-- Notes:
-- used READ0DELAY-2 and READ0DELAY-3
-- used READ1DELAY-2
-- used WRITEDELAY-2
assert READ0DELAY-2 < 2**R_REGS.cntdly'length and
READ1DELAY-2 < 2**R_REGS.cntdly'length and
WRITEDELAY-2 < 2**R_REGS.cntdly'length
report "assert( (READ0,READ1,WRITE)DELAY-2 < 2**cntdly'length)"
severity failure;
assert READ0DELAY >= 3 and
READ1DELAY >= 2 and
WRITEDELAY >= 2
report "assert( (READ0,READ1,WRITE)DELAY-2 >= 2 or 3)"
severity failure;
CLK_180 <= not CLK;
IOB_MEM_CE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => MEM_CE_N,
PAD => O_MEM_CE_N
);
IOB_MEM_BE : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '1')
port map (
CLK => CLK,
CE => BE_CE,
DO => MEM_BE_N,
PAD => O_MEM_BE_N
);
IOB_MEM_WE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK_180,
CE => '1',
DO => MEM_WE_N,
PAD => O_MEM_WE_N
);
IOB_MEM_OE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => MEM_OE_N,
PAD => O_MEM_OE_N
);
IOB_MEM_CRE : iob_reg_o
generic map (
INIT => '0')
port map (
CLK => CLK,
CE => '1',
DO => MEM_CRE,
PAD => O_MEM_CRE
);
IOB_MEM_ADDRH : iob_reg_o_gen
generic map (
DWIDTH => 22)
port map (
CLK => CLK,
CE => ADDRH_CE,
DO => ADDRH,
PAD => O_MEM_ADDR(22 downto 1)
);
IOB_MEM_ADDR0 : iob_reg_o
port map (
CLK => CLK,
CE => ADDR0_CE,
DO => ADDR0,
PAD => O_MEM_ADDR(0)
);
IOB_MEM_DATA : iob_reg_io_gen
generic map (
DWIDTH => 16,
PULL => "NONE")
port map (
CLK => CLK,
CEI => DATA_CEI,
CEO => DATA_CEO,
OE => DATA_OE,
DI => MEM_DO,
DO => MEM_DI,
PAD => IO_MEM_DATA
);
O_MEM_ADV_N <= '0';
O_MEM_CLK <= '0';
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, REQ, WE, BE, DI, ADDR, MEM_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibusy : slbit := '0';
variable iackw : slbit := '0';
variable iactr : slbit := '0';
variable iactw : slbit := '0';
variable imem_ce : slbit := '0';
variable imem_be : slv2 := "00";
variable imem_we : slbit := '0';
variable imem_oe : slbit := '0';
variable imem_cre : slbit := '0';
variable ibe_ce : slbit := '0';
variable iaddrh_ce : slbit := '0';
variable iaddr0_ce : slbit := '0';
variable iaddrh : slv22 := (others=>'0');
variable iaddr0 : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
procedure do_dispatch(pnstate : out state_type;
piaddrh_ce : out slbit;
piaddr0_ce : out slbit;
piaddr0 : out slbit;
pibe_ce : out slbit;
pimem_be : out slv2;
pimem_ce : out slbit;
pimem_oe : out slbit;
pnbe2nd : out slv2) is
begin
piaddrh_ce := '1'; -- latch address (high part)
piaddr0_ce := '1'; -- latch address 0 bit
pibe_ce := '1'; -- latch be's
pimem_ce := '1'; -- ce CRAM next cycle
pnbe2nd := "00"; -- assume no 2nd write cycle
if WE = '0' then -- if READ requested
piaddr0 := '0'; -- go first for low word
pimem_be := "11"; -- on read always on
pimem_oe := '1'; -- oe CRAM next cycle
pnstate := s_rdinit; -- next: read init part
else -- if WRITE requested
if BE(1 downto 0) /= "00" then -- low word write
piaddr0 := '0'; -- access word 0
pimem_be := BE(1 downto 0); -- set be's for 1st cycle
pnbe2nd := BE(3 downto 2); -- keep be's for 2nd cycle
else -- high word write
piaddr0 := '1'; -- access word 1
pimem_be := BE(3 downto 2); -- set be's for 1st cycle
end if;
pimem_oe := '0'; -- oe=0
pnstate := s_wrinit; -- next: write init part
end if;
end procedure do_dispatch;
begin
r := R_REGS;
n := R_REGS;
n.ackr := '0';
ibusy := '0';
iackw := '0';
iactr := '0';
iactw := '0';
imem_ce := '0';
imem_be := "11";
imem_we := '0';
imem_oe := '0';
imem_cre := '0';
ibe_ce := '0';
iaddrh_ce := '0';
iaddr0_ce := '0';
iaddrh := ADDR;
iaddr0 := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
if unsigned(r.cntdly) /= 0 then
n.cntdly := slv(unsigned(r.cntdly) - 1);
end if;
case r.state is
when s_init => -- s_init: startup state
ibusy := '1'; -- signal busy, unable to handle req
n.state := s_init1;
when s_init1 => -- s_init1: reset released
ibusy := '1'; -- signal busy, unable to handle req
iaddrh := c_addrh_rcr_setup;
iaddr0 := '0';
iaddrh_ce := '1';
iaddr0_ce := '1';
imem_ce := '1'; -- ce CRAM next cycle
imem_cre := '1'; -- cre CRAM next cycle
n.state := s_wcinit;
when s_wcinit => -- s_wcinit: write rcr init
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
imem_cre := '1'; -- cre CRAM next cycle
imem_we := '1'; -- we CRAM next cycle
n.cntdly := slv(to_unsigned(WRITEDELAY-2, n.cntdly'length));
n.state := s_wcwait;
when s_wcwait => -- s_wcinit: write rcr wait
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM next cycle
imem_cre := '1'; -- cre CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_wcput; -- next: write rcr done
end if;
when s_wcput => -- s_wcput: write rcr done
ibusy := '1'; -- signal busy, unable to handle req
n.state := s_rainit; -- next: read array init
when s_rainit => -- s_rainit: read array init
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
n.cntdly:= slv(to_unsigned(READ0DELAY-2, n.cntdly'length));
n.state := s_rawait ; -- next: wait read array
when s_rawait => -- s_rawait: wait read array
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_idle; -- next: wait for req
end if;
when s_idle => -- s_idle: wait for req
if REQ = '1' then -- if IO requested
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
end if;
when s_rdinit => -- s_rdinit: read init cycle
ibusy := '1'; -- signal busy, unable to handle req
iactr := '1'; -- signal mem read
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
n.cntdly:= slv(to_unsigned(READ0DELAY-3, n.cntdly'length));
n.state := s_rdwait0; -- next: wait low word
when s_rdwait0 => -- s_rdwait0: read wait low word
ibusy := '1'; -- signal busy, unable to handle req
iactr := '1'; -- signal mem read
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_rdget0; -- next: get low word
end if;
when s_rdget0 => -- s_rdget0: read get low word
ibusy := '1'; -- signal busy, unable to handle req
iactr := '1'; -- signal mem read
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
idata_cei := '1'; -- latch input data
iaddr0_ce := '1'; -- latch address 0 bit
iaddr0 := '1'; -- now go for high word
n.cntdly:= slv(to_unsigned(READ1DELAY-2, n.cntdly'length));
n.state := s_rdwait1; -- next: wait high word
when s_rdwait1 => -- s_rdwait1: read wait high word
ibusy := '1'; -- signal busy, unable to handle req
iactr := '1'; -- signal mem read
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_rdget1; -- next: get high word
end if; --
when s_rdget1 => -- s_rdget1: read get high word
iactr := '1'; -- signal mem read
n.memdo0:= MEM_DO; -- save low word data
idata_cei := '1'; -- latch input data
n.ackr := '1'; -- ACK_R next cycle
n.state := s_idle; -- next: wait next request
if r.fidle = '1' then -- forced idle cycle
ibusy := '1'; -- signal busy, unable to handle req
else
if REQ = '1' then -- if IO requested
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
end if;
end if;
when s_wrinit => -- s_wrinit: write init cycle
ibusy := '1'; -- signal busy, unable to handle req
iactw := '1'; -- signal mem write
iackw := '1'; -- signal write done (all latched)
idata_ceo:= '1'; -- latch output data
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM in half cycle
n.cntdly:= slv(to_unsigned(WRITEDELAY-2, n.cntdly'length));
n.state := s_wrwait0; -- next: wait
when s_wrwait0 => -- s_rdput0: write wait 1st word
ibusy := '1'; -- signal busy, unable to handle req
iactw := '1'; -- signal mem write
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_wrput0; -- next: put 1st word
end if;
when s_wrput0 => -- s_rdput0: write put 1st word
iactw := '1'; -- signal mem write
imem_we := '0'; -- deassert we CRAM in half cycle
if r.be2nd /= "00" then
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
iaddr0_ce := '1'; -- latch address 0 bit
iaddr0 := '1'; -- now go for high word
ibe_ce := '1'; -- latch be's
imem_be := r.be2nd; -- now be's of high word
n.state := s_wrini1; -- next: start 2nd write
else
n.state := s_idle; -- next: wait next request
if r.fidle = '1' then -- forced idle cycle
ibusy := '1'; -- signal busy
else
if REQ = '1' then -- if IO requested
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
end if;
end if;
end if;
when s_wrini1 => -- s_wrini1: write init 2nd word
ibusy := '1'; -- signal busy, unable to handle req
iactw := '1'; -- signal mem write
idata_ceo:= '1'; -- latch output data
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM in half cycle
n.cntdly:= slv(to_unsigned(WRITEDELAY-2, n.cntdly'length));
n.state := s_wrwait1; -- next: wait
when s_wrwait1 => -- s_wrwait1: write wait 2nd word
ibusy := '1'; -- signal busy, unable to handle req
iactw := '1'; -- signal mem write
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_wrput1; -- next: put 2nd word
end if;
when s_wrput1 => -- s_wrput1: write put 2nd word
iactw := '1'; -- signal mem write
imem_we := '0'; -- deassert we CRAM in half cycle
n.state := s_idle; -- next: wait next request
if r.fidle = '1' then -- forced idle cycle
ibusy := '1'; -- signal busy, unable to handle req
else
if REQ = '1' then -- if IO requested
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
end if;
end if;
when others => null;
end case;
if imem_ce = '0' then -- if cmem not active
n.cntce := (others=>'0'); -- clear counter
n.fidle := '0'; -- clear force idle flag
else -- if cmem active
if unsigned(r.cntce) >= 127 then -- if max ce count expired
n.fidle := '1'; -- set forced idle flag
else -- if max ce count not yet reached
n.cntce := slv(unsigned(r.cntce) + 1); -- increment counter
end if;
end if;
if iaddrh_ce = '1' then -- if addresses are latched
n.memdi := DI; -- latch data too...
end if;
if iaddr0_ce = '1' then -- if address bit 0 changed
n.addr0 := iaddr0; -- mirror it in state regs
end if;
N_REGS <= n;
MEM_CE_N <= not imem_ce;
MEM_WE_N <= not imem_we;
MEM_BE_N <= not imem_be;
MEM_OE_N <= not imem_oe;
MEM_CRE <= imem_cre;
if r.addr0 = '0' then
MEM_DI <= r.memdi(15 downto 0);
else
MEM_DI <= r.memdi(31 downto 16);
end if;
BE_CE <= ibe_ce;
ADDRH_CE <= iaddrh_ce;
ADDR0_CE <= iaddr0_ce;
ADDRH <= iaddrh;
ADDR0 <= iaddr0;
DATA_CEI <= idata_cei;
DATA_CEO <= idata_ceo;
DATA_OE <= idata_oe;
BUSY <= ibusy;
ACK_R <= r.ackr;
ACK_W <= iackw;
ACT_R <= iactr;
ACT_W <= iactw;
DO <= MEM_DO & r.memdo0;
end process proc_next;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/bplib/cmoda7/tb/sys_conf_sim.vhd | 1 | 1705 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_cmoda7_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2016.4; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-04 906 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clksys_outdivide : positive := 9; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clkser_outdivide : positive := 6; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01400_good.vhd | 1 | 2741 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01400_good.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of generic port name: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity CNE_01400_good is
generic (g_Width : positive := 3);
port (
i_D0 : in std_logic_vector(g_Width downto 0); -- First Mux input
i_D1 : in std_logic_vector(g_Width downto 0); -- Second Mux input
i_Sel : in std_logic; -- Mux select input
o_D : out std_logic_vector(g_Width downto 0) -- Mux output
);
end CNE_01400_good;
--CODE
architecture Behavioral of CNE_01400_good is
begin
-- Simple Mux, output depends on select value
o_D <= i_D1 when i_Sel='1'
else i_D0;
end Behavioral; | gpl-3.0 |
wfjm/w11 | rtl/sys_gen/tst_snhumanio/s3board/sys_conf.vhd | 1 | 800 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_snhumanio_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-18 410 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
end package sys_conf;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4/sys_conf1.vhd | 1 | 1993 | -- $Id: sys_conf1.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop1_n4 (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-25 751 1.1 clock now from cmt and configurable
-- 2015-02-01 641 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkdiv_usecdiv : integer := 100; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
-- configure hio interfaces -----------------------------------------------
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure serport ------------------------------------------------------
constant sys_conf_uart_defbaud : integer := 115200; -- default 115k baud
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_uart_cdinit : integer :=
(sys_conf_clksys/sys_conf_uart_defbaud)-1;
end package sys_conf;
| gpl-3.0 |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_02000_bad.vhd | 1 | 4680 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-20 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_02000_bad.vhd
-- File Creation date : 2015-04-20
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of Finite State Machine: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_02000_bad is
port (
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
i_Start : in std_logic; -- Start counter signal
i_Stop : in std_logic -- Stop counter signal
);
end CNE_02000_bad;
architecture Behavioral of CNE_02000_bad is
constant c_Length : std_logic_vector(3 downto 0) := (others => '1'); -- How long we should count
--CODE
type t_state is (init, loading, enabled, finished); -- Enumerated type for state encoding
signal State : t_state; -- State signal
--CODE
signal Raz : std_logic; -- Load the length value and initialize the counter
signal Enable : std_logic; -- Counter enable signal
signal Length : std_logic_vector(3 downto 0); -- Counter length for counting
signal End_Count : std_logic; -- End signal of counter
begin
-- A simple counter with loading length and enable signal
Counter:Counter
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_Raz => Raz,
i_Enable => Enable,
i_Length => Length,
o_Done => End_Count
);
-- FSM process controlling the counter. Start or stop it in function of the input (i_Start & i_Stop),
-- load the length value, and wait for it to finish
P_FSM:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
State <= init;
elsif (rising_edge(i_Clock)) then
case State is
when init =>
-- Set the length value
Length <= c_Length;
State <= loading;
when loading =>
-- Load the counter and initialize it
Raz <= '1';
State <= enabled;
when enabled =>
-- Start or stop counting depending on inputs until it finishes
Raz <= '0';
if (End_Count='0') then
Enable <= i_Start xor not i_Stop;
State <= Enabled;
else
Enable <= '0';
State <= finished;
end if;
when others =>
State <= init;
end case;
end if;
end process;
end Behavioral; | gpl-3.0 |
nanomolina/vhdl_examples | datapath/flopr.vhd | 4 | 449 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY flopr IS
PORT (d: IN std_logic_vector(31 DOWNTO 0);
clk, reset: IN std_logic;
q: OUT std_logic_vector(31 DOWNTO 0));
END flopr;
ARCHITECTURE flopr_est OF flopr IS
BEGIN
PROCESS (clk, reset)
BEGIN
IF (reset='1') THEN
q <= x"00000000";
ELSIF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
END flopr_est;
| gpl-3.0 |
wfjm/w11 | rtl/w11a/pdp11_dspmux.vhd | 1 | 3056 | -- $Id: pdp11_dspmux.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dspmux - syn
-- Description: pdp11: hio dsp mux
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2015-02-22 650 1.0 Initial version
-- 2015-02-21 649 0.1 First draft
------------------------------------------------------------------------------
-- selects display data
-- 4 Digit Displays
-- SEL(1:0) 00 ABCLKDIV
-- 01 DM_STAT_EXP.dp_pc
-- 10 DISPREG
-- 11 DM_STAT_EXP.dp_dsrc
--
-- 8 Digit Displays
-- SEL(1) select DSP(7:4)
-- 0 ABCLKDIV
-- 1 DM_STAT_EXP.dp_pc
-- SEL(0) select DSP(7:4)
-- 0 DISPREG
-- 1 DM_STAT_EXP.dp_dsrc
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_dspmux is -- hio dsp mux
generic (
DCWIDTH : positive := 2); -- digit counter width (2 or 3)
port (
SEL : in slv2; -- select
ABCLKDIV : in slv16; -- serport clock divider
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
DISPREG : in slv16; -- display register
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data
);
end pdp11_dspmux;
architecture syn of pdp11_dspmux is
subtype dspdat_msb is integer range 4*(2**DCWIDTH)-1 downto 4*(2**DCWIDTH)-16;
subtype dspdat_lsb is integer range 15 downto 0;
begin
assert DCWIDTH=2 or DCWIDTH=3
report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH"
severity failure;
proc_mux: process (SEL, ABCLKDIV, DM_STAT_EXP, DISPREG)
variable idat : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0');
begin
idat := (others=>'0');
if DCWIDTH = 2 then
case SEL is
when "00" =>
idat(dspdat_lsb) := ABCLKDIV;
when "01" =>
idat(dspdat_lsb) := DM_STAT_EXP.dp_pc;
when "10" =>
idat(dspdat_lsb) := DISPREG;
when "11" =>
idat(dspdat_lsb) := DM_STAT_EXP.dp_dsrc;
when others => null;
end case;
else
if SEL(1) = '0' then
idat(dspdat_msb) := ABCLKDIV;
else
idat(dspdat_msb) := DM_STAT_EXP.dp_pc;
end if;
if SEL(0) = '0' then
idat(dspdat_lsb) := DISPREG;
else
idat(dspdat_lsb) := DM_STAT_EXP.dp_dsrc;
end if;
end if;
DSP_DAT <= idat;
end process proc_mux;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/w11a/arty/tb/tb_w11a_arty.vhd | 1 | 778 | -- $Id: tb_w11a_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_arty
-- Description: Configuration for tb_w11a_arty for tb_arty_dram
--
-- Dependencies: sys_w11a_arty
--
-- To test: sys_w11a_arty
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-17 1071 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_w11a_arty of tb_arty_dram is
for sim
for all : arty_dram_aif
use entity work.sys_w11a_arty;
end for;
end for;
end tb_w11a_arty;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/xlib/iob_keeper_gen.vhd | 1 | 1622 | -- $Id: iob_keeper_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: iob_keeper_gen - sim
-- Description: keeper for IOB, vector
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2010-06-03 299 1.1 add explicit R_KEEP and driver
-- 2008-05-22 148 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_keeper_gen is -- keeper for IOB, vector
generic (
DWIDTH : positive := 16); -- data port width
port (
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end iob_keeper_gen;
-- Is't possible to directly use 'PAD<='H' in proc_pad. Introduced R_KEEP and
-- the explicit driver 'PAD<=R_KEEP' to state the keeper function more clearly.
architecture sim of iob_keeper_gen is
signal R_KEEP : slv(DWIDTH-1 downto 0) := (others=>'W');
begin
proc_keep: process (PAD)
begin
for i in PAD'range loop
if PAD(i) = '1' then
R_KEEP(i) <= 'H';
elsif PAD(i) = '0' then
R_KEEP(i) <= 'L';
elsif PAD(i)='X' or PAD(i)='U' then
R_KEEP(i) <= 'W';
end if;
end loop;
PAD <= R_KEEP;
end process proc_keep;
end sim;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd | 1 | 5105 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.8.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.8 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-27 1108 1.7.5 drop iist
-- 2018-09-22 1050 1.7.4 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.7.3 add sys_conf_ibd_kw11p
-- 2017-04-22 884 1.7.2 use sys_conf_dmcmon_awidth=8 (proper value)
-- 2017-01-29 847 1.7.1 add sys_conf_ibd_deuna
-- 2016-07-16 788 1.7 use cram_*delay functions to determine delays
-- 2016-05-28 770 1.6.1 sys_conf_mem_losize now type natural
-- 2016-03-22 750 1.6 add sys_conf_cache_twidth
-- 2015-12-26 718 1.5.2 use clksys=64 (as since r692 in sys_conf.vhd)
-- 2015-06-26 695 1.5.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
-- 2015-03-14 658 1.5 add sys_conf_ibd_* definitions
-- 2015-02-15 647 1.4 drop bram and minisys options
-- 2014-12-22 619 1.3.1 add _rbmon_awidth
-- 2013-10-06 538 1.3 pll support, use clksys_vcodivide ect
-- 2013-04-21 509 1.2 add fx2 settings
-- 2011-11-25 432 1.0 Initial version (cloned from _n3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 25;
constant sys_conf_clksys_vcomultiply : positive := 16; -- dcm 64 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 64 MHz
constant sys_conf_clksys_gentype : string := "DCM";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- configure memory controller ---------------------------------------------
-- now under derived constants
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := true;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 4; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 4; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 5; -- DZ11
constant sys_conf_ibd_pc11 : integer := 4; -- PC11
constant sys_conf_ibd_lp11 : integer := 5; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := false; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
| gpl-3.0 |
wfjm/w11 | rtl/ibus/ibd_ibtst.vhd | 1 | 16470 | -- $Id: ibd_ibtst.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibd_ibtst - syn
-- Description: ibus dev(rem): ibus tester
--
-- Dependencies: memlib/fifo_simple_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2017.2; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-03-01 1116 1.0.1 rnam dly[rw]->bsy[rw]; datto for write; add datab
-- 2019-02-16 1112 1.0 Initial version
-- 2019-02-09 1110 0.1 First draft
------------------------------------------------------------------------------
--
-- ibus registers:
--
-- Addr Bits IB RB IR Name Function
-- 00 cntl Control register
-- 15 -- 0W 00 fclr fifo clear
-- 8 -- RW 00 datab ibus ack while busy for data nak
-- 7 -- RW 00 datto ibus timeout for data nak
-- 6 -- RW 00 nobyt disallow byte writes to data (loc+rem)
-- 5 -- RW 00 bsyw enable loc write busy for fifo/data
-- 4 -- RW 00 bsyr enable loc read busy for fifo/data
-- 3 -- RW 11 remw enable rem write for fifo/data
-- 2 -- RW 11 remr enable rem read for fifo/data
-- 1 -- RW 00 locw enable loc write for fifo/data
-- 0 -- RW 00 locr enable loc read for fifo/data
-- 01 -- R- stat Status register (moni last data/fifo)
-- 15:12 -- R- fsize fifo size
-- 6 -- R- racc remote access seen
-- 5 -- R- cacc console access seen
-- 4 -- R- be1 byte enable high seen
-- 3 -- R- be0 byte enable low seen
-- 2 -- R- rmw read-modify-write seen
-- 1 -- R- we write enable seen
-- 0 -- R- re read enable seen
-- 10 rw rw 00 data data register (byte/word writable)
-- 11 rw rw fifo fifo interface register
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibd_ibtst is -- ibus dev(rem): ibus tester
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#170000#,16))); -- base address
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end ibd_ibtst;
architecture syn of ibd_ibtst is
constant ibaddr_cntl : slv2 := "00"; -- cntl address offset
constant ibaddr_stat : slv2 := "01"; -- stat address offset
constant ibaddr_data : slv2 := "10"; -- bdat address offset
constant ibaddr_fifo : slv2 := "11"; -- wdat address offset
constant cntl_ibf_fclr : integer := 15;
constant cntl_ibf_datab : integer := 8;
constant cntl_ibf_datto : integer := 7;
constant cntl_ibf_nobyt : integer := 6;
constant cntl_ibf_bsyw : integer := 5;
constant cntl_ibf_bsyr : integer := 4;
constant cntl_ibf_remw : integer := 3;
constant cntl_ibf_remr : integer := 2;
constant cntl_ibf_locw : integer := 1;
constant cntl_ibf_locr : integer := 0;
subtype stat_ibf_fsize is integer range 15 downto 12;
constant stat_ibf_racc : integer := 6;
constant stat_ibf_cacc : integer := 5;
constant stat_ibf_be1 : integer := 4;
constant stat_ibf_be0 : integer := 3;
constant stat_ibf_rmw : integer := 2;
constant stat_ibf_we : integer := 1;
constant stat_ibf_re : integer := 0;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
datab : slbit; -- cntl: ibus busy for bad loc data
datto : slbit; -- cntl: ibus timeout for bad loc data
nobyt : slbit; -- cntl: disallow byte writes to data
bsyw : slbit; -- cntl: enable loc write busy
bsyr : slbit; -- cntl: enable loc read busy
remw : slbit; -- cntl: enable rem write
remr : slbit; -- cntl: enable rem read
locw : slbit; -- cntl: enable loc write
locr : slbit; -- cntl: enable loc read
racc : slbit; -- stat: racc seen
cacc : slbit; -- stat: cacc seen
be1 : slbit; -- stat: be1 seen
be0 : slbit; -- stat: be0 seen
rmw : slbit; -- stat: rmw seen
we : slbit; -- stat: we seen
re : slbit; -- stat: re seen
data : slv16; -- data register
dcnt : slv3; -- delay counter
req_1 : slbit; -- (re or we) of last cycle
rwm_1 : slbit; -- (re or we or rmw) of last cycle
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'0','0','0','0','0', -- datab,datto,nobyt,bsyw,bsyr
'1','1','0','0', -- remw,remr,locw,locr
'0','0','0','0', -- racc,cacc,be1,be0
'0','0','0', -- rmw,we,re
(others=>'0'), -- data
(others=>'0'), -- dcnt
'0','0' -- req_1,rwm_1
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal FIFO_CE : slbit := '0';
signal FIFO_WE : slbit := '0';
signal FIFO_RESET : slbit := '0';
signal FIFO_EMPTY : slbit := '0';
signal FIFO_FULL : slbit := '0';
signal FIFO_SIZE : slv4 := (others=>'0');
signal FIFO_DO : slv16 := (others=>'0');
begin
FIFO : fifo_simple_dram
generic map (
AWIDTH => 4,
DWIDTH => 16)
port map (
CLK => CLK,
RESET => FIFO_RESET,
CE => FIFO_CE,
WE => FIFO_WE,
DI => IB_MREQ.din,
DO => FIFO_DO,
EMPTY => FIFO_EMPTY,
FULL => FIFO_FULL,
SIZE => FIFO_SIZE
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, RESET, FIFO_DO, FIFO_EMPTY,
FIFO_FULL, FIFO_SIZE)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibreq : slbit := '0';
variable ibbusy : slbit := '0';
variable iback : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ififo_rst : slbit := '0';
variable ififo_ce : slbit := '0';
variable ififo_we : slbit := '0';
variable bsyok : slbit := '0'; -- fifo/data busy ok
variable dobsy : slbit := '0'; -- fifo/data do busy
variable wrok : slbit := '0'; -- fifo/data write ok
variable rdok : slbit := '0'; -- fifo/data read ok
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibbusy := '0';
iback := r.ibsel and ibreq;
ififo_rst := RESET;
ififo_ce := '0';
ififo_we := '0';
bsyok := '0';
if IB_MREQ.racc = '0' then -- loc
bsyok := (r.bsyr and IB_MREQ.re) or (r.bsyw and IB_MREQ.we);
end if;
dobsy := '0';
if IB_MREQ.racc = '1' then -- rem
wrok := r.remw;
rdok := r.remr;
else -- loc
wrok := r.locw;
rdok := r.locr;
end if;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
-- re,we,rmw edge detectors
n.req_1 := r.ibsel and (ibreq);
n.rwm_1 := r.ibsel and (ibreq or IB_MREQ.rmw);
-- ibus mreq monitor
if r.ibsel = '1' then
if (ibreq or IB_MREQ.rmw) = '1' and -- re or we or rmw
IB_MREQ.addr(2) = '1' then -- and addr = (data or fifo)
if r.rwm_1 = '0' then -- leading edge
n.racc := IB_MREQ.racc;
n.cacc := IB_MREQ.cacc;
n.be1 := IB_MREQ.be1;
n.be0 := IB_MREQ.be0;
n.rmw := IB_MREQ.rmw;
n.we := IB_MREQ.we;
n.re := IB_MREQ.re;
else -- later
n.we := r.we or IB_MREQ.we;
n.re := r.re or IB_MREQ.re;
end if;
end if;
end if;
-- delay counter
if r.ibsel='1' and ibreq='1' and bsyok='1' then -- selected,active,busy
if r.req_1 = '0' then -- leading edge
n.dcnt := "111";
dobsy := '1';
else -- later
if r.dcnt /= "000" then
n.dcnt := slv(unsigned(r.dcnt) - 1);
dobsy := '1';
end if;
end if;
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_cntl => -- CNTL
if IB_MREQ.racc = '1' then -- rem
if IB_MREQ.we = '1' then -- write
ififo_rst := IB_MREQ.din(cntl_ibf_fclr);
n.datab := IB_MREQ.din(cntl_ibf_datab);
n.datto := IB_MREQ.din(cntl_ibf_datto);
n.nobyt := IB_MREQ.din(cntl_ibf_nobyt);
n.bsyw := IB_MREQ.din(cntl_ibf_bsyw);
n.bsyr := IB_MREQ.din(cntl_ibf_bsyr);
n.remw := IB_MREQ.din(cntl_ibf_remw);
n.remr := IB_MREQ.din(cntl_ibf_remr);
n.locw := IB_MREQ.din(cntl_ibf_locw);
n.locr := IB_MREQ.din(cntl_ibf_locr);
end if;
else -- loc
iback := '0'; -- reject loc access to CNTL
end if;
when ibaddr_stat => -- STAT
if IB_MREQ.racc = '0' then -- loc
iback := '0'; -- reject loc access to STAT
end if;
when ibaddr_data => -- DATA
if IB_MREQ.we = '1' then -- write
if wrok = '1' then -- write enabled
if r.nobyt = '1' and -- byte write allowed check
(IB_MREQ.be1='0' or IB_MREQ.be0='0') then
iback := '0'; -- send nak
else -- byte check ok
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
else -- no busy active
if IB_MREQ.be1 = '1' then
n.data(ibf_byte1) := IB_MREQ.din(ibf_byte1);
end if;
if IB_MREQ.be0 = '1' then
n.data(ibf_byte0) := IB_MREQ.din(ibf_byte0);
end if;
end if; -- dobsy = '1'
end if; -- byte check
else -- write disabled
if dobsy = '1' then -- busy active
iback := r.datab; -- send ack when busy for nak
ibbusy := '1';
else -- no busy active
if r.datto = '1' then -- data time out enabled
iback := '0';
ibbusy := '1'; -- will cause timeout !
else
iback := '0'; -- send nak
end if;
end if; -- dobsy = '1'
end if; -- wrok = '1'
end if; -- IB_MREQ.we = '1'
if IB_MREQ.re = '1' then -- read
if rdok = '1' then -- read enabled
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
end if;
else -- read disabled
if dobsy = '1' then -- busy active
iback := r.datab; -- send ack when busy for nak
ibbusy := '1';
else -- no busy active
if r.datto = '1' then -- data time out enabled
iback := '0';
ibbusy := '1'; -- will cause timeout !
else
iback := '0'; -- send nak
end if;
end if; -- dobsy = '1'
end if; -- rdok = '0'
end if; -- IB_MREQ.re = '1'
when ibaddr_fifo => -- FIFO
if IB_MREQ.we = '1' then -- write
if wrok = '1' then -- write enabled
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
else -- busy not active
if FIFO_FULL = '0' then -- fifo not full
ififo_ce := '1';
ififo_we := '1';
else -- fifo full
iback := '0'; -- send nak
end if; -- FIFO_FULL = '0'
end if; -- dobsy = '1'
else -- write disabled
iback := '0'; -- send nak
end if; -- wrok = '1'
end if; -- IB_MREQ.we = '1'
if IB_MREQ.re = '1' then -- read
if rdok = '1' then -- read enabled
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
else -- busy not active
if FIFO_EMPTY = '0' then -- fifo not empty
ififo_ce := '1';
else -- fifo empty
iback := '0'; -- send nak
end if; -- FIFO_EMPTY = '0'
end if; -- dobsy = '1'
else -- read disabled
iback := '0'; -- send nak
end if; -- rdok = '1'
end if; -- IB_MREQ.re = '1'
when others => null;
end case; --
end if; --r.ibsel = '1'
-- ibus output driver
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_cntl => -- CNTL
idout(cntl_ibf_datab) := r.datab;
idout(cntl_ibf_datto) := r.datto;
idout(cntl_ibf_nobyt) := r.nobyt;
idout(cntl_ibf_bsyw) := r.bsyw;
idout(cntl_ibf_bsyr) := r.bsyr;
idout(cntl_ibf_remw) := r.remw;
idout(cntl_ibf_remr) := r.remr;
idout(cntl_ibf_locw) := r.locw;
idout(cntl_ibf_locr) := r.locr;
when ibaddr_stat => -- STAT
idout(stat_ibf_fsize) := FIFO_SIZE;
idout(stat_ibf_racc) := r.racc;
idout(stat_ibf_cacc) := r.cacc;
idout(stat_ibf_be1) := r.be1;
idout(stat_ibf_be0) := r.be0;
idout(stat_ibf_rmw) := r.rmw;
idout(stat_ibf_we) := r.we;
idout(stat_ibf_re) := r.re;
when ibaddr_data => -- DATA
idout := r.data;
when ibaddr_fifo => -- FIFO
idout := FIFO_DO;
when others => null;
end case;
end if;
N_REGS <= n;
FIFO_RESET <= ififo_rst;
FIFO_CE <= ififo_ce;
FIFO_WE <= ififo_we;
IB_SRES.dout <= idout;
IB_SRES.ack <= iback;
IB_SRES.busy <= ibbusy;
end process proc_next;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/serport/serport_uart_autobaud.vhd | 1 | 6458 | -- $Id: serport_uart_autobaud.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_autobaud - syn
-- Description: serial port UART - autobauder
--
-- Dependencies: -
-- Test bench: tb/tb_serport_autobaud
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2015-02-01 641 1.1 add CLKDIV_F
-- 2011-10-22 417 1.0.4 now numeric_std clean
-- 2010-04-18 279 1.0.3 change ccnt start value to -3, better rounding
-- 2007-10-14 89 1.0.2 all instantiation with CDINIT=0
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
-- !!!! appended to the name, has been created in the /tb sub folder.
-- !!!! Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity serport_uart_autobaud is -- serial port uart: autobauder
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT: natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
CLKDIV_F: out slv3; -- clock divider fractional part
ACT : out slbit; -- active; if 1 clkdiv is invalid
DONE : out slbit -- resync done
);
end serport_uart_autobaud;
architecture syn of serport_uart_autobaud is
type state_type is (
s_idle,
s_break,
s_wait,
s_sync
);
type regs_type is record
ccnt : slv(CDWIDTH-1+3 downto 0); -- clock divider counter
mcnt : slv7; -- msec counter
seen1 : slbit; -- seen a '1' in this msec
state : state_type; -- state
end record regs_type;
-- Note on initialization of ccnt:
-- - in the current logic ccnt is incremented n-1 times when n is number
-- clock cycles with a RXD of '0'. When running at 50 MBaud, ccnt will
-- be incremented 7 (not 8!) times.
-- - the three LSBs of ccnt should be at 100 under perfect conditions, this
-- gives the best rounded estimate of CLKDIV.
-- - therefore ccnt is inititialized with 111111.101: 101 + 111 -> 1100
-- --> ccntinit = -3
constant ccntinit : slv(CDWIDTH-1+3 downto 0) :=
slv(to_unsigned(2**(CDWIDTH+3)-3, CDWIDTH+3));
constant mcntzero : slv7 := (others=>'0');
constant mcntlast : slv7 := (others=>'1');
constant regs_init : regs_type := (
slv(to_unsigned(CDINIT,CDWIDTH))&"000",
(others=>'0'),
'0',
s_idle
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
begin
assert CDINIT <= 2**CDWIDTH-1
report "assert(CDINIT <= 2**CDWIDTH-1): CDINIT too large for given CDWIDTH"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, RESET, RXSD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iact : slbit := '0';
variable idone : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
iact := '1';
idone := '0';
case r.state is
when s_idle => -- s_idle: idle, detect break --------
iact := '0';
if CE_MSEC = '1' then -- if end of msec
if r.seen1 = '0' then -- if no '1' seen on RXD
n.mcnt := slv(unsigned(r.mcnt) + 1); -- up break timer counter
if r.mcnt = mcntlast then -- after 127 msec
n.state := s_break; -- break detected !
end if;
else -- otherwise if '1' seen
n.mcnt := mcntzero; -- clear break timer again
end if;
n.seen1 := RXSD; -- latch current RXD value
else -- otherwise if not at end-of-msec
n.seen1 := r.seen1 or RXSD; -- remember whether RXS=1 seen
end if;
when s_break => -- s_break: detect end of break ------
if RXSD = '1' then -- if end of break seen
n.state := s_wait; -- to s_wait to wait for sync char
n.ccnt := ccntinit; -- and initialize ccnt
end if; -- otherwise stay in s_break
when s_wait => -- s_wait: wait for sync char --------
if RXSD = '0' then -- if start bit if sync char seen
n.state := s_sync; -- to s_sync to wait for end of '0'
end if; -- otherwise stay in s_wait
when s_sync => -- s_sync: wait for end of '0' bits --
if RXSD = '1' then -- if end of '0' bits seen
n.state := s_idle; -- to s_idle, autobauding done
idone := '1'; -- emit done pulse
else -- otherwise still in '0' of sync
n.ccnt := slv(unsigned(n.ccnt) + 1); -- increment ccnt
end if;
when others => null; -- -----------------------------------
end case;
N_REGS <= n;
CLKDIV <= r.ccnt(CDWIDTH-1+3 downto 3);
CLKDIV_F <= r.ccnt(2 downto 0);
ACT <= iact or RESET;
DONE <= idone;
end process proc_next;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vhd | 1 | 3508 | -- $Id: tb_tst_serloop1_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop1_n4 - sim
-- Description: Test bench for sys_tst_serloop1_n4
--
-- Dependencies: simlib/simclk
-- xlib/sfs_gsim_core
-- sys_tst_serloop1_n4 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop1_n4
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.2.1 use sfs_gsim_core
-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report)
-- 2016-04-09 760 1.1 clock now from cmt and configurable
-- 2015-02-21 438 1.0 Initial version (cloned from tb_tst_serloop1_n3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
use work.sys_conf.all;
entity tb_tst_serloop1_n4 is
end tb_tst_serloop1_n4;
architecture sim of tb_tst_serloop1_n4 is
signal CLK100 : slbit := '0';
signal CLK : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100
);
GEN_CLKSYS : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide)
port map (
CLKIN => CLK100,
CLKFX => CLK,
LOCKED => open
);
UUT : entity work.sys_tst_serloop1_n4
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => '1',
O_LED => open,
O_RGBLED0 => open,
O_RGBLED1 => open,
O_ANO_N => open,
O_SEG_N => open
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLK,
CLKH => CLK,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => RTS_N,
P0_CTS_N => CTS_N,
P1_RXD => open, -- port 1 unused for n4 !
P1_TXD => '0',
P1_RTS_N => '0',
P1_CTS_N => open,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0)
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
RTS_N <= O_RTS_N after delay_time;
I_CTS_N <= CTS_N after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
| gpl-3.0 |
wfjm/w11 | rtl/w11a/pdp11_vmbox.vhd | 1 | 25563 | -- $Id: pdp11_vmbox.vhd 1320 2022-11-22 18:52:59Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_vmbox - syn
-- Description: pdp11: virtual memory
--
-- Dependencies: pdp11_mmu
-- pdp11_ubmap
-- ibus/ib_sres_or_4
-- ibus/ib_sres_or_2
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-11-21 1320 1.6.9 rename some rsv->ser; remove obsolete trap_done;
-- 2022-11-18 1317 1.6.8 BUGFIX: correct red/yellow zone boundary
-- 2019-06-22 1170 1.6.7 support membe for em cacc access
-- 2016-05-22 767 1.6.6 don't init N_REGS (vivado fix for fsm inference)
-- 2015-07-03 697 1.6.5 much wider DM_STAT_VM
-- 2015-04-04 662 1.6.4 atowidth now 6 (was 5) to support ibdr_rprm reset
-- 2011-11-18 427 1.6.3 now numeric_std clean
-- 2010-10-23 335 1.6.2 add r.paddr_iopage, use ib_sel
-- 2010-10-22 334 1.6.1 deassert ibus be's at end-cycle; fix rmw logic
-- 2010-10-17 333 1.6 implement ibus V2 interface
-- 2010-06-27 310 1.5 redo ibus driver logic, now ibus driven from flops
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 for cpacc: set cacc in ib_mreq, forward racc,be
-- from CP_ADDR; now all ibr handling via vmbox
-- 2010-06-13 305 1.4 rename CPADDR -> CP_ADDR
-- 2009-06-01 221 1.3.8 add dip signal in ib_mreq (set in s_ib)
-- 2009-05-30 220 1.3.7 final removal of snoopers (were already commented)
-- 2009-05-01 211 1.3.6 BUGFIX: add 177776 stack protect (SCCE)
-- 2008-08-22 161 1.3.5 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
-- 2008-04-25 138 1.3.4 add BRESET port, clear stklim with BRESET
-- 2008-04-20 137 1.3.3 add DM_STAT_VM port
-- 2008-03-19 127 1.3.2 ignore ack state when waiting on a busy IB in s_ib
-- 2008-03-02 121 1.3.1 remove snoopers
-- 2008-02-24 119 1.3 revamp paddr generation; add _ubmap
-- 2008-02-23 118 1.2.1 use sys_conf_mem_losize
-- 2008-02-17 117 1.2 use em_(mreq|sres) interface for external memory
-- 2008-01-26 114 1.1.4 rename 'ubus' to 'ib' (proper name of intbus now)
-- 2008-01-05 110 1.1.3 update snooper.
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2008-01-01 109 1.1.2 Use IB_SRES_(CPU|EXT); use r./n. coding style, move
-- all status into regs_type. add intbus HOLD support.
-- 2007-12-30 108 1.1.1 use ubf_byte[01]
-- 2007-12-30 107 1.1 Use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-09-16 83 1.0.2 Use ram_1swsr_wfirst_gen, not ram_2swsr_wfirst_gen
-- 2nd port was unused, connected ADDR caused slow net
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_vmbox is -- virtual memory
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
CRESET : in slbit; -- cpu reset
BRESET : in slbit; -- bus reset
CP_ADDR : in cp_addr_type; -- console port address
VM_CNTL : in vm_cntl_type; -- vm control port
VM_ADDR : in slv16; -- vm address
VM_DIN : in slv16; -- vm data in
VM_STAT : out vm_stat_type; -- vm status port
VM_DOUT : out slv16; -- vm data out
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
MMU_MONI : in mmu_moni_type; -- mmu monitor port
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
);
end pdp11_vmbox;
architecture syn of pdp11_vmbox is
constant ibaddr_slim : slv16 := slv(to_unsigned(8#177774#,16));
constant atowidth : natural := 6; -- size of access timeout counter
-- ! rbus tout must be > ibus tout !
-- ! ensure all BTOWIDTH > atowidth !
type state_type is (
s_idle, -- s_idle: wait for vm_cntl request
s_mem_w, -- s_mem_w: check mmu, wait for memory
s_ib_w, -- s_ib_w: wait for ibus
s_ib_wend, -- s_ib_wend: ibus write completion
s_ib_rend, -- s_ib_rend: ibus read completion
s_idle_mw_ib, -- s_idle_mw_ib: wait macc write (ibus)
s_idle_mw_mem, -- s_idle_mw_mem: wait macc write (mem)
s_mem_mw_w, -- s_mem_mw_w: wait for memory (macc)
s_fail, -- s_fail: vmbox fatal error catcher
s_errrsv, -- s_errrsv: red stack violation
s_errib -- s_errib: ibus error handler
);
type regs_type is record -- state registers
state : state_type; -- state
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access
bytop : slbit; -- byte operation
kstack : slbit; -- access through kernel stack
ysv : slbit; -- yellow stack violation detected
vaok : slbit; -- virtual address valid (from MMU)
trap_mmu : slbit; -- mmu trap requested
mdin : slv16; -- data input (memory order)
paddr : slv22; -- physical address register
paddr_iopage : slv9; -- iopage base (upper 9 bits of paddr)
atocnt : slv(atowidth-1 downto 0); -- access timeout counter
ibre : slbit; -- ibus re signal
ibwe : slbit; -- ibus we signal
ibbe : slv2; -- ibus be0,be1 signals
ibrmw : slbit; -- ibus rmw signal
ibcacc : slbit; -- ibus cacc signal
ibracc : slbit; -- ibus racc signal
ibdout : slv16; -- ibus dout register
end record regs_type;
constant atocnt_init : slv(atowidth-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
s_idle, -- state
'0','0','0','0', -- wacc,macc,cacc,bytop
'0','0','0','0', -- kstack,ysv,vaok,trap_mmu
(others=>'0'), -- mdin
(others=>'0'), -- paddr
(others=>'0'), -- paddr_iopage
atocnt_init, -- atocnt
'0','0',"00", -- ibre,ibwe,ibbe
'0','0','0', -- ibrmw,ibcacc,ibracc
(others=>'0') -- ibdout
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal R_SLIM : slv8 := (others=>'0'); -- stack limit register
signal MMU_CNTL : mmu_cntl_type := mmu_cntl_init;
signal MMU_STAT : mmu_stat_type := mmu_stat_init;
signal PADDRH : slv16 := (others=>'0');
signal IBSEL_SLIM :slbit := '0'; -- select stack limit reg
signal IB_SRES_SLIM : ib_sres_type := ib_sres_init;
signal IB_SRES_MMU : ib_sres_type := ib_sres_init;
signal IB_SRES_UBMAP : ib_sres_type := ib_sres_init;
signal UBMAP_MREQ : slbit := '0';
signal UBMAP_ADDR_PM : slv22_1 := (others=>'0');
signal VM_STAT_L : vm_stat_type := vm_stat_init; -- vm status (local)
signal VM_DOUT_L : slv16 := (others=>'0'); -- vm data out (local)
signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
signal IB_SRES_INT : ib_sres_type := ib_sres_init; -- ibus response (cpu)
signal EM_MREQ_L : em_mreq_type := em_mreq_init; -- ext mem: request (local)
begin
MMU : pdp11_mmu
port map (
CLK => CLK,
CRESET => CRESET,
BRESET => BRESET,
CNTL => MMU_CNTL,
VADDR => VM_ADDR,
MONI => MMU_MONI,
STAT => MMU_STAT,
PADDRH => PADDRH,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MMU
);
UBMAP : pdp11_ubmap
port map (
CLK => CLK,
MREQ => UBMAP_MREQ,
ADDR_UB => CP_ADDR.addr(17 downto 1),
ADDR_PM => UBMAP_ADDR_PM,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_UBMAP
);
SRES_OR_INT : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_CPU,
IB_SRES_2 => IB_SRES_SLIM,
IB_SRES_3 => IB_SRES_MMU,
IB_SRES_4 => IB_SRES_UBMAP,
IB_SRES_OR => IB_SRES_INT
);
SRES_OR_ALL : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_INT,
IB_SRES_2 => IB_SRES_EXT,
IB_SRES_OR => IB_SRES
);
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_slim)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SLIM
);
proc_ibres : process (IBSEL_SLIM, IB_MREQ, R_SLIM)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_SLIM = '1' then
idout(ibf_byte1) := R_SLIM;
end if;
IB_SRES_SLIM.dout <= idout;
IB_SRES_SLIM.ack <= IBSEL_SLIM and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_SLIM.busy <= '0';
end process proc_ibres;
proc_slim: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_SLIM <= (others=>'0');
elsif IBSEL_SLIM='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
R_SLIM <= IB_MREQ.din(ibf_byte1);
end if;
end if;
end if;
end process proc_slim;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, R_SLIM, CP_ADDR, VM_CNTL, VM_DIN, VM_ADDR,
IB_SRES, UBMAP_ADDR_PM,
EM_SRES, MMU_STAT, PADDRH)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ivm_stat : vm_stat_type := vm_stat_init;
variable ivm_dout : slv16 := (others=>'0');
variable iem_mreq : em_mreq_type := em_mreq_init;
variable immu_cntl : mmu_cntl_type := mmu_cntl_init;
variable ipaddr : slv22 := (others=>'0');
variable ipaddr_iopage : slv9 := (others=>'0');
variable iib_aval : slbit := '0';
variable ato_go : slbit := '0';
variable ato_end : slbit := '0';
variable is_stackyellow : slbit := '1'; -- VM_ADDR in yellow stack zone
variable is_stackred : slbit := '1'; -- VM_ADDR in red stack zone
variable iubmap_mreq : slbit := '0';
variable paddr_mmu : slbit := '0';
variable paddr_sel : slv2 := "00";
constant c_paddr_sel_vmaddr : slv2 := "00";
constant c_paddr_sel_rpaddr : slv2 := "01";
constant c_paddr_sel_cacc : slv2 := "10";
constant c_paddr_sel_ubmap : slv2 := "11";
begin
r := R_REGS;
n := R_REGS;
n.state := s_fail;
ivm_stat := vm_stat_init;
ivm_dout := EM_SRES.dout;
immu_cntl := mmu_cntl_init;
iib_aval := '0';
iem_mreq := em_mreq_init;
iem_mreq.din := VM_DIN;
if VM_CNTL.cacc = '1' then -- if cacc access
iem_mreq.be := CP_ADDR.be; -- use membe setup
elsif VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if VM_ADDR(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
iubmap_mreq :='0';
paddr_mmu := '1'; -- ipaddr selector, used in s_idle
-- and overwritten in s_idle_mw_mem
paddr_sel := "00";
if MMU_STAT.ena_mmu='0' or VM_CNTL.cacc='1' then
paddr_mmu := '0';
paddr_sel := c_paddr_sel_vmaddr;
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_ubmap='1' and MMU_STAT.ena_ubmap='1' then
paddr_sel := c_paddr_sel_ubmap;
else
paddr_sel := c_paddr_sel_cacc;
end if;
end if;
end if;
-- the iopage base is determined based on mmu regs and request type
-- r.paddr_iopage is updated during s_idle. This way the iopage base
-- address is determined in parallel to paddr and latched at end of s_idle.
-- Note: is VM_CNTL.cacc here, the status in s_idle is relevant !
ipaddr_iopage := "111111111"; -- iopage match pattern (for 22 bit)
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_22bit = '0' then
ipaddr_iopage := "000000111"; -- 16 bit cacc
end if;
else
if MMU_STAT.ena_mmu = '0' then
ipaddr_iopage := "000000111"; -- 16 bit mode
else
if MMU_STAT.ena_22bit = '0' then
ipaddr_iopage := "000011111"; -- 18 bit mode
end if;
end if;
end if;
ato_go := '0'; -- default: keep access timeout in reset
ato_end := '0';
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
ato_end := '1'; -- signal expiration
end if;
is_stackyellow := '0';
is_stackred := '0';
if unsigned(VM_ADDR(15 downto 8)) <= unsigned(R_SLIM) then
if unsigned(VM_ADDR(15 downto 8)) = unsigned(R_SLIM) and
unsigned(VM_ADDR(7 downto 5)) = 7 then
is_stackyellow := '1';
else
is_stackred := '1';
end if;
end if;
if VM_ADDR(15 downto 1) = "111111111111111" then -- PSW protection
is_stackred := '1';
end if;
immu_cntl.wacc := VM_CNTL.wacc;
immu_cntl.macc := VM_CNTL.macc;
immu_cntl.cacc := VM_CNTL.cacc;
immu_cntl.dspace := VM_CNTL.dspace;
immu_cntl.mode := VM_CNTL.mode;
case r.state is
when s_idle => -- s_idle: wait for vm_cntl request --
n.state := s_idle;
iubmap_mreq := '1'; -- activate ubmap always in s_idle
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.cacc := VM_CNTL.cacc;
n.bytop := VM_CNTL.bytop;
n.kstack := VM_CNTL.kstack;
n.ysv := '0';
n.vaok := MMU_STAT.vaok;
n.trap_mmu := MMU_STAT.trap;
n.mdin := iem_mreq.din;
-- n.paddr assignment handled separately in 'if state=s_idle' at the
-- end.
immu_cntl.req := '1';
if VM_CNTL.wacc='1' and VM_CNTL.macc='1' then
n.state := s_fail;
elsif VM_CNTL.kstack='1' and VM_CNTL.vecser='0' and
is_stackred='1' then
n.state := s_errrsv;
else
iem_mreq.req := '1';
iem_mreq.we := VM_CNTL.wacc;
if VM_CNTL.kstack='1' and VM_CNTL.vecser='0' then
n.ysv := is_stackyellow;
end if;
n.state := s_mem_w;
end if;
end if;
when s_mem_w => -- s_mem_w: check mmu, wait for memory
if r.bytop='0' and r.paddr(0)='1' then -- odd address ?
ivm_stat.err := '1';
ivm_stat.err_odd := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
elsif r.vaok = '0' then -- MMU abort ?
ivm_stat.err := '1';
ivm_stat.err_mmu := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if r.paddr(21 downto 13) = r.paddr_iopage then
-- I/O page decoded
iem_mreq.cancel := '1'; -- cancel pending mem request
iib_aval := '1'; -- declare ibus addr valid
n.ibre := not r.wacc;
n.ibwe := r.wacc;
n.ibcacc := r.cacc;
n.ibracc := r.cacc and CP_ADDR.racc;
n.ibbe := "11";
if r.cacc = '1' then -- console access ?
n.ibbe := CP_ADDR.be;
else -- cpu access ?
if r.bytop = '1' then
if r.paddr(0) = '0' then
n.ibbe(1) := '0';
else
n.ibbe(0) := '0';
end if;
end if;
end if;
n.ibrmw := r.macc;
n.state := s_ib_w;
else
if unsigned(r.paddr(21 downto 6)) > sys_conf_mem_losize then
ivm_stat.err := '1';
ivm_stat.err_nxm := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if EM_SRES.ack_r='1' or EM_SRES.ack_w='1' then
ivm_stat.ack := '1';
ivm_stat.trap_ysv := r.ysv;
ivm_stat.trap_mmu := r.trap_mmu;
if r.macc='1' and r.wacc='0' then
n.state := s_idle_mw_mem;
else
n.state := s_idle;
end if;
else
n.state := s_mem_w; -- keep waiting
end if;
end if;
end if;
end if;
when s_ib_w => -- s_ib_w: wait for ibus -------------
ato_go := '1'; -- activate timeout counter
iib_aval := '1'; -- declare ibus addr valid
n.ibre := '0'; -- end cycle, unless busy seen
n.ibwe := '0';
n.ibrmw := '0';
n.ibbe := "00";
n.ibcacc := '0';
n.ibracc := '0';
if IB_SRES.ack='1' and IB_SRES.busy='0' then -- ibus cycle finished
if r.wacc = '1' then
n.state := s_ib_wend;
else
if r.macc = '1' then -- if first part of rmw
n.ibrmw := r.macc; -- keep rmw
n.ibbe := r.ibbe; -- keep be's
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
end if;
n.ibdout := IB_SRES.dout;
n.state := s_ib_rend;
end if;
elsif IB_SRES.busy='1' and ato_end='0' then
n.ibre := r.ibre; -- continue ibus cycle
n.ibwe := r.ibwe;
n.ibrmw := r.ibrmw;
n.ibbe := r.ibbe;
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
n.state := s_ib_w;
else
n.state := s_errib;
end if;
when s_ib_wend => -- s_ib_wend: ibus write completion --
ivm_stat.ack := '1';
n.state := s_idle;
when s_ib_rend => -- s_ib_rend: ibus read completion ---
ivm_stat.ack := '1';
ivm_dout := r.ibdout;
if r.macc='1' then -- first part of read-mod-write
iib_aval := '1'; -- keep ibus addr valid
n.state := s_idle_mw_ib;
else
n.state := s_idle;
end if;
when s_idle_mw_ib => -- s_idle_mw_ib: wait macc write (ibus)
n.state := s_idle_mw_ib;
iib_aval := '1'; -- keep ibus addr valid
if r.ibbe = "10" then
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
n.ibwe := '1'; -- Note: all other ibus drivers
-- already set in 1st part
n.state := s_ib_w;
end if;
end if;
when s_idle_mw_mem => -- s_idle_mw_mem: wait macc write (mem)
n.state := s_idle_mw_mem;
paddr_mmu := '0';
paddr_sel := c_paddr_sel_rpaddr;
if VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if r.paddr(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.bytop := VM_CNTL.bytop;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
iem_mreq.req := '1';
iem_mreq.we := '1';
n.state := s_mem_mw_w;
end if;
end if;
when s_mem_mw_w => -- s_mem_mw_w: wait for memory (macc)
if EM_SRES.ack_w = '1' then
ivm_stat.ack := '1';
n.state := s_idle;
else
n.state := s_mem_mw_w; -- keep waiting
end if;
when s_fail => -- s_fail: vmbox fatal error catcher
ivm_stat.fail := '1';
n.state := s_idle;
when s_errrsv => -- s_errrsv: red stack violation -----
ivm_stat.err := '1';
ivm_stat.err_rsv := '1';
n.state := s_idle;
when s_errib => -- s_errib: ibus error handler -------
ivm_stat.err := '1';
ivm_stat.err_iobto := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
n.state := s_idle;
when others => null;
end case;
if r.bytop='1' and r.paddr(0)='1' then
ivm_dout(ibf_byte0) := ivm_dout(ibf_byte1);
end if;
if ato_go = '0' then -- handle access timeout counter
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
else
n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down
end if;
ipaddr := (others=>'0');
if paddr_mmu = '1' then
ipaddr( 5 downto 0) := VM_ADDR(5 downto 0);
ipaddr(21 downto 6) := PADDRH;
if MMU_STAT.ena_22bit = '0' then
ipaddr(21 downto 18) := (others=>'0');
end if;
else
case paddr_sel is
when c_paddr_sel_vmaddr =>
ipaddr(15 downto 0) := VM_ADDR(15 downto 0);
when c_paddr_sel_rpaddr =>
ipaddr := r.paddr;
when c_paddr_sel_cacc =>
ipaddr := CP_ADDR.addr & '0';
if CP_ADDR.ena_22bit = '0' then
ipaddr(21 downto 16) := (others=>'0');
end if;
when c_paddr_sel_ubmap =>
ipaddr := UBMAP_ADDR_PM & '0';
when others => null;
end case;
end if;
if r.state = s_idle then
n.paddr := ipaddr;
n.paddr_iopage := ipaddr_iopage;
end if;
iem_mreq.addr := ipaddr(21 downto 1);
N_REGS <= n;
UBMAP_MREQ <= iubmap_mreq;
IB_MREQ.aval <= iib_aval;
IB_MREQ.re <= r.ibre;
IB_MREQ.we <= r.ibwe;
IB_MREQ.be0 <= r.ibbe(0);
IB_MREQ.be1 <= r.ibbe(1);
IB_MREQ.rmw <= r.ibrmw;
IB_MREQ.cacc <= r.ibcacc;
IB_MREQ.racc <= r.ibracc;
IB_MREQ.addr <= r.paddr(12 downto 1);
IB_MREQ.din <= r.mdin;
VM_STAT_L <= ivm_stat;
VM_DOUT_L <= ivm_dout;
MMU_CNTL <= immu_cntl;
EM_MREQ_L <= iem_mreq;
end process proc_next;
VM_STAT <= VM_STAT_L;
VM_DOUT <= VM_DOUT_L;
IB_MREQ_M <= IB_MREQ; -- external drive master port
EM_MREQ <= EM_MREQ_L;
DM_STAT_VM.vmcntl <= VM_CNTL;
DM_STAT_VM.vmaddr <= VM_ADDR;
DM_STAT_VM.vmdin <= VM_DIN;
DM_STAT_VM.vmstat <= VM_STAT_L;
DM_STAT_VM.vmdout <= VM_DOUT_L;
DM_STAT_VM.ibmreq <= IB_MREQ;
DM_STAT_VM.ibsres <= IB_SRES;
DM_STAT_VM.emmreq <= EM_MREQ_L;
DM_STAT_VM.emsres <= EM_SRES;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/bplib/nexys4/tb/tb_nexys4.vhd | 1 | 5408 | -- $Id: tb_nexys4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4 - sim
-- Description: Test bench for nexys4 (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_nexys4_core
-- serport/tb/serport_master_tb
-- nexys4_aif [UUT]
--
-- To test: generic, any nexys4_aif target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4-2018.2; ghdl 0.29-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.3.5 use sfs_gsim_core
-- 2016-09-02 805 1.3.4 tbcore_rlink without CLK_STOP now
-- 2016-02-20 734 1.3.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
-- 2015-02-06 643 1.2 factor out memory
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-28 535 1.0.1 use proper clock manager
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys4lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4 is
end tb_nexys4;
architecture sim of tb_nexys4 is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 |
wfjm/w11 | rtl/w11a/pdp11_dmcmon.vhd | 1 | 34371 | -- $Id: pdp11_dmcmon.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dmcmon- syn
-- Description: pdp11: debug&moni: cpu monitor
--
-- Dependencies: memlib/ram_2swsr_rfirst_gen
-- memlib/ram_1swar_1ar_gen
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.31-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-08-02 707 14.7 131013 xc6slx16-2 213 233 16 151 s 5.9
--
-- Revision History: -
-- Date Rev Version Comment
-- 2022-10-25 1309 2.0.2 rename _gpr -> _gr
-- 2019-06-02 1159 2.0.1 use rbaddr_ constants
-- 2017-04-22 884 2.0 use DM_STAT_SE.idle; revised interface, add suspend
-- 2015-08-03 709 1.0 Initial version
-- 2015-07-05 697 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 000 cntl r/w/f Control register
-- 05 mwsup r/w/- mem wait suppress
-- 04 imode r/w/- instruction mode
-- 03 wstop r/w/- stop on wrap
-- 02:00 func 0/-/f change run status if != noop
-- 0xx noop
-- 100 sto stop
-- 101 sta start and latch all options
-- 110 sus suspend (noop if not started)
-- 111 res resume (noop if not started)
-- 001 stat r/-/- Status register
-- 15:13 bsize r/-/- buffer size (AWIDTH-8)
-- 12:09 malcnt r/-/- valid entries in memory access log
-- 08 snum r/-/- snum support
-- 02 wrap r/-/- line address wrapped (cleared on start)
-- 01 susp r/-/- suspended
-- 00 run r/-/- running (can be suspended)
-- 010 addr r/w/- Address register (writable when stopped)
-- *:04 laddr r/w/- line address
-- 03:00 waddr r/w/- word address (0000 to 1000)
-- 011 data r/w/- Data register
-- 100 iaddr r/-/- Last instruction cmon address
-- *:04 laddr r/-/- line address
-- 03:00 r/-/- -always zero-
-- 101 ipc r/-/- Last instruction pc
-- 110 ireg r/-/- Last instruction
-- 111 imal r/-/- Last instruction memory access log
--
-- data format:
-- word 8 15 : vm.vmcntl.req
-- if req = 1
-- 14 : vm.vmcntl.wacc
-- 13 : vm.vmcntl.macc
-- 12 : vm.vmcntl.cacc
-- 11 : vm.vmcntl.bytop
-- 10 : vm.vmcntl.dspace
-- if req = 0
-- 14 : vm.vmcntl.ack
-- 13 : vm.vmcntl.err
-- if ack = 1 and err = 0
-- 12 : vm.vmcntl.trap_ysv
-- 11 : vm.vmcntl.trap_mmu
-- 10 : mwdrop (signals memwait suppress when mwsup=1)
-- if ack = 0 and err = 1
-- 12:10 : vm error code (priority encoded, but only one anyone)
-- 000 err_odd = 1
-- 001 err_mmu = 1
-- 010 err_nxm = 1
-- 011 err_iobto = 1
-- 100 err_rsv = 1
--
-- 09 : se.istart
-- 08 : se.idone
--
-- if imode = 0
-- 07:00 : se.snum
-- if imode = 1
-- 07:00 : cnum
--
-- word 7 15:01 : dp.pc (captured at se.istart)
-- 00 : idecode (is dp.ireg_we delayed by 1 cycle)
-- word 6 15:00 : dp.ireg
-- word 5 15:14 : dp.psw.cmode
-- 13:12 : dp.psw.pmode
-- 11 : dp.psw.rset
-- if imode = 0
-- 10 : dp.dres valid
-- 09 : dp.ddst_we
-- 08 : dp.dsrc_we
-- if imode = 1
-- 10 : -- unused --
-- 09 : -- unused --
-- 08 : se.vfetch
-- always
-- 07:05 : dp.psw.pri
-- 04 : dp.psw.tflag
-- 03:00 : dp.psw.cc
-- word 4 15:00 : dp.dsrc
-- word 3 15:00 : dp.ddst
-- word 2 15:00 : dp.dres (reged)
-- word 1 15:00 : vm.vmaddr (captured at vm.vmcntl.req)
-- word 0 15:00 : vm.vmdin or vm.vmdout (captured at req or ack)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates
-- to control the instantiation. ghdl checks even for not instantiated
-- entities the validity of generics, that's why natural needed here ....
entity pdp11_dmcmon is -- debug&moni: cpu monitor
generic (
RB_ADDR : slv16 := rbaddr_dmcmon_off;
AWIDTH : natural := 8;
SNUM : boolean := false);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core
);
end pdp11_dmcmon;
architecture syn of pdp11_dmcmon is
constant rbaddr_cntl : slv3 := "000"; -- cntl address offset
constant rbaddr_stat : slv3 := "001"; -- stat address offset
constant rbaddr_addr : slv3 := "010"; -- addr address offset
constant rbaddr_data : slv3 := "011"; -- data address offset
constant rbaddr_iaddr : slv3 := "100"; -- iaddr address offset
constant rbaddr_ipc : slv3 := "101"; -- ipc address offset
constant rbaddr_ireg : slv3 := "110"; -- ireg address offset
constant rbaddr_imal : slv3 := "111"; -- imal address offset
constant cntl_rbf_mwsup : integer := 5;
constant cntl_rbf_imode : integer := 4;
constant cntl_rbf_wstop : integer := 3;
subtype cntl_rbf_func is integer range 2 downto 0;
subtype stat_rbf_bsize is integer range 15 downto 13;
subtype stat_rbf_malcnt is integer range 12 downto 9;
constant stat_rbf_snum : integer := 8;
constant stat_rbf_wrap : integer := 2;
constant stat_rbf_susp : integer := 1;
constant stat_rbf_run : integer := 0;
subtype addr_rbf_laddr is integer range 4+AWIDTH-1 downto 4;
subtype addr_rbf_waddr is integer range 3 downto 0;
subtype bram_mf_port11 is integer range 143 downto 108;
subtype bram_mf_port10 is integer range 107 downto 72;
subtype bram_mf_port01 is integer range 71 downto 36;
subtype bram_mf_port00 is integer range 35 downto 0;
subtype bram_df_word8 is integer range 143 downto 128;
subtype bram_df_word7 is integer range 127 downto 112;
subtype bram_df_word6 is integer range 111 downto 96;
subtype bram_df_word5 is integer range 95 downto 80;
subtype bram_df_word4 is integer range 79 downto 64;
subtype bram_df_word3 is integer range 63 downto 48;
subtype bram_df_word2 is integer range 47 downto 32;
subtype bram_df_word1 is integer range 31 downto 16;
subtype bram_df_word0 is integer range 15 downto 0;
constant dat8_rbf_req : integer := 15;
constant dat8_rbf_wacc : integer := 14; -- if req=1
constant dat8_rbf_macc : integer := 13; -- "
constant dat8_rbf_cacc : integer := 12; -- "
constant dat8_rbf_bytop : integer := 11; -- "
constant dat8_rbf_dspace : integer := 10; -- "
constant dat8_rbf_ack : integer := 14; -- if req=0
constant dat8_rbf_err : integer := 13; -- "
constant dat8_rbf_trap_ysv : integer := 12; -- if req=0 ack=1 err=0
constant dat8_rbf_trap_mmu : integer := 11; -- "
constant dat8_rbf_mwdrop : integer := 10; -- "
subtype dat8_rbf_vmerr is integer range 12 downto 10;-- if req=0 ack=0 err=1
constant dat8_rbf_istart : integer := 9; -- always
constant dat8_rbf_idone : integer := 8; -- "
constant vmerr_odd : slv3 := "001"; -- vm error code: err_odd
constant vmerr_mmu : slv3 := "010"; -- vm error code: err_mmu
constant vmerr_nxm : slv3 := "011"; -- vm error code: err_nxm
constant vmerr_iobto : slv3 := "100"; -- vm error code: err_iobto
constant vmerr_rsv : slv3 := "101"; -- vm error code: err_rsv
subtype dat8_rbf_snum is integer range 7 downto 0;
subtype dat8_rbf_cnum is integer range 7 downto 0;
subtype dat7_rbf_pc is integer range 15 downto 1;
constant dat7_rbf_idecode : integer := 0;
subtype dat5_rbf_cmode is integer range 15 downto 14;
subtype dat5_rbf_pmode is integer range 13 downto 12;
constant dat5_rbf_rset : integer := 11;
constant dat5_rbf_dres_val : integer := 10; -- if imode=0
constant dat5_rbf_ddst_we : integer := 9;
constant dat5_rbf_dsrc_we : integer := 8;
constant dat5_rbf_vfetch : integer := 8; -- if imode=1
subtype dat5_rbf_pri is integer range 7 downto 5;
constant dat5_rbf_tflag : integer := 4;
subtype dat5_rbf_cc is integer range 3 downto 0;
constant func_sto : slv3 := "100"; -- func: stop
constant func_sta : slv3 := "101"; -- func: start
constant func_sus : slv3 := "110"; -- func: suspend
constant func_res : slv3 := "111"; -- func: resume
constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0');
constant laddrlast : slv(AWIDTH-1 downto 0) := (others=>'1');
type regs_type is record
rbsel : slbit; -- rbus select
mwsup : slbit; -- mwsup flag (mem wait suppress)
imode : slbit; -- imode flag
wstop : slbit; -- wstop flag (stop on wrap)
susp : slbit; -- suspended flag
go : slbit; -- go flag (actively running)
active : slbit; -- active flag
wrap : slbit; -- laddr wrap flag
laddr : slv(AWIDTH-1 downto 0); -- line address
waddr : slv4; -- word address
cnum : slv8; -- clk counter
mal_waddr : slv4; -- mem acc log: write address
mal_raddr : slv4; -- mem acc log: read address
dp_pc_fet : slv16_1; -- dp.pc_fet (capture on se.istart)
dp_pc_dec : slv16_1; -- dp.pc_dec (capture on dp.ireg_we + 1)
dp_ireg : slv16; -- dp.ireg
dp_ireg_we : slbit; -- dp.ireg_we
dp_ireg_we_1 : slbit; -- dp.ireg_we last cycle
dp_dres : slv16; -- dp.dres
dp_dsrc_we : slbit; -- dp.dsrc_we
dp_ddst_we : slbit; -- dp.ddst_we
dp_dres_val : slbit; -- dp.dres valid
vm_addr : slv16; -- vm.vmaddr
vm_din : slv16; -- vm.vmdin
vm_dout : slv16; -- vm.vmdout
vm_req : slbit; -- vm.vmcntl.req
vm_wacc : slbit; -- vm.vmcntl.wacc
vm_macc : slbit; -- vm.vmcntl.macc
vm_cacc : slbit; -- vm.vmcntl.cacc
vm_bytop : slbit; -- vm.vmcntl.bytop
vm_dspace : slbit; -- vm.vmcntl.dspace
vm_addr_1 : slv16; -- vm.vmaddr last request
vm_dout_1 : slv16; -- vm.vmdout last request
vm_wacc_1 : slbit; -- vm.vmcntl.wacc last request
vm_macc_1 : slbit; -- vm.vmcntl.macc last request
vm_cacc_1 : slbit; -- vm.vmcntl.cacc last request
vm_bytop_1 : slbit; -- vm.vmcntl.bytop last request
vm_dspace_1 : slbit; -- vm.vmcntl.dspace last request
vm_ack : slbit; -- vm.vmstat.ack
vm_err : slbit; -- vm.vmstat.err
vm_err_odd : slbit; -- vm.vmstat.err_odd
vm_err_mmu : slbit; -- vm.vmstat.err_mmu
vm_err_nxm : slbit; -- vm.vmstat.err_nxm
vm_err_iobto : slbit; -- vm.vmstat.err_iobto
vm_err_rsv : slbit; -- vm.vmstat.err_rsv
vm_trap_ysv : slbit; -- vm.vmstat.trap_ysv
vm_trap_mmu : slbit; -- vm.vmstat.trap_mmu
vm_pend : slbit; -- vm req pending
se_idle : slbit; -- se.idle
se_istart : slbit; -- se.istart
se_istart_1 : slbit; -- se.istart last cycle
se_idone : slbit; -- se.idone
se_vfetch : slbit; -- se.vfetch
se_snum : slv8; -- se.snum
mwdrop : slbit; -- mem wait drop flag
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
'0','1','0', -- mwsup,imode,wstop
'0','1','0', -- susp,go,active
'0', -- wrap
laddrzero, -- laddr
"0000", -- waddr
(others=>'0'), -- cnum
(others=>'0'), -- macwaddr
(others=>'0'), -- macraddr
(others=>'0'), -- dp_pc_fet
(others=>'0'), -- dp_pc_dec
(others=>'0'), -- dp_ireq
'0','0', -- dp_ireq_we,dp_ireq_we_1
(others=>'0'), -- dp_dres
'0','0','0', -- dp_dsrc_we,dp_ddst_we,dp_dres_val
(others=>'0'), -- vm_addr
(others=>'0'), -- vm_din
(others=>'0'), -- vm_dout
'0','0','0','0','0','0', -- vm_req,..,vm_dspace
(others=>'0'), -- vm_addr_1
(others=>'0'), -- vm_dout_1
'0','0','0','0','0', -- vm_wacc_1,..,vm_dspace_1
'0','0', -- vm_ack,vm_err
'0','0','0','0','0', -- vm_err_*
'0','0', -- vm_trap_*
'0', -- vm_pend
'0','0','0', -- se_idle,se_istart(_1)
'0','0', -- se_idone,se_vfetch
(others=>'0'), -- se_snum
'0' -- mwdrop
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal BRAM_EN : slbit := '0';
signal BRAM_WE : slbit := '0';
signal BRAM_ADDRA : slv(AWIDTH downto 0) := (others=>'0');
signal BRAM_ADDRB : slv(AWIDTH downto 0) := (others=>'0');
signal BRAM_DI : slv(143 downto 0) := (others=>'0');
signal BRAM_DO : slv(143 downto 0) := (others=>'0');
signal MAL_WE : slbit := '0';
signal MAL_DI : slv16 := (others=>'0');
signal MAL_DO : slv16 := (others=>'0');
begin
assert AWIDTH>=8 and AWIDTH<=11
report "assert(AWIDTH>=8 and AWIDTH<=11): unsupported AWIDTH"
severity failure;
BRAM0 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH+1,
DWIDTH => 36)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => BRAM_EN,
ENB => BRAM_EN,
WEA => BRAM_WE,
WEB => BRAM_WE,
ADDRA => BRAM_ADDRA,
ADDRB => BRAM_ADDRB,
DIA => BRAM_DI(bram_mf_port00),
DIB => BRAM_DI(bram_mf_port01),
DOA => BRAM_DO(bram_mf_port00),
DOB => BRAM_DO(bram_mf_port01)
);
BRAM1 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH+1,
DWIDTH => 36)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => BRAM_EN,
ENB => BRAM_EN,
WEA => BRAM_WE,
WEB => BRAM_WE,
ADDRA => BRAM_ADDRA,
ADDRB => BRAM_ADDRB,
DIA => BRAM_DI(bram_mf_port10),
DIB => BRAM_DI(bram_mf_port11),
DOA => BRAM_DO(bram_mf_port10),
DOB => BRAM_DO(bram_mf_port11)
);
MAL : ram_1swar_1ar_gen
generic map (
AWIDTH => 4,
DWIDTH => 16)
port map (
CLK => CLK,
WE => MAL_WE,
ADDRA => R_REGS.mal_waddr,
ADDRB => R_REGS.mal_raddr,
DI => MAL_DI,
DOA => open,
DOB => MAL_DO);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, DM_STAT_SE,
DM_STAT_DP, DM_STAT_DP.psw, -- xst needs sub-records
DM_STAT_VM, DM_STAT_VM.vmcntl, DM_STAT_VM.vmstat,
DM_STAT_CO, BRAM_DO, MAL_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_err : slbit := '0'; -- FIXME: needed ??
variable irb_busy : slbit := '0'; -- FIXME: needed ??
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable ibramen : slbit := '0'; -- BRAM enable
variable ibramwe : slbit := '0'; -- BRAN we
variable igoeff : slbit := '0';
variable iactive : slbit := '0';
variable itake : slbit := '0';
variable laddr_inc : slbit := '0';
variable idat : slv(143 downto 0) := (others=>'0');
variable idat8 : slv16 := (others=>'0');
variable idat7 : slv16 := (others=>'0');
variable idat5 : slv16 := (others=>'0');
variable ivmerr : slv3 := (others=>'0');
variable imal_we : slbit := '0';
variable imal_re : slbit := '0';
variable imal_di : slv16 := (others=>'0');
variable imal_waddr_clr : slbit := '0';
variable imal_raddr_clr : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_err := '0';
irb_busy := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
ibramen := '0';
ibramwe := '0';
igoeff := '0';
iactive := '0';
itake := '0';
laddr_inc := '0';
imal_we := '0';
imal_re := '0';
imal_di := r.vm_addr;
imal_waddr_clr := '0';
imal_raddr_clr := '0';
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(12 downto 3)=RB_ADDR(12 downto 3) then
n.rbsel := '1';
ibramen := '1'; -- ensure bram read before rbus read
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl => -- cntl ------------------
if RB_MREQ.we = '1' then
case RB_MREQ.din(cntl_rbf_func) is
when func_sto => -- func: stop ------------
n.go := '0';
n.susp := '0';
when func_sta => -- func: start -----------
n.mwsup := RB_MREQ.din(cntl_rbf_mwsup);
n.imode := RB_MREQ.din(cntl_rbf_imode);
n.wstop := RB_MREQ.din(cntl_rbf_wstop);
n.go := '1';
n.susp := '0';
n.wrap := '0';
n.laddr := laddrzero;
n.waddr := "0000";
when func_sus => -- func: susp ------------
if r.go = '1' then -- noop unless running
n.go := '0';
n.susp := r.go;
end if;
when func_res => -- func: resu ------------
n.go := r.susp;
n.susp := '0';
when others => null; -- <> --------------------
end case;
end if;
when rbaddr_stat => -- stat ------------------
irb_err := RB_MREQ.we;
when rbaddr_addr => -- addr ------------------
if RB_MREQ.we = '1' then
if r.go = '0' then -- if not active OK
n.laddr := RB_MREQ.din(addr_rbf_laddr);
n.waddr := RB_MREQ.din(addr_rbf_waddr);
else
irb_err := '1'; -- otherwise error
end if;
end if;
when rbaddr_data => -- data ------------------
-- write to data is an error
if RB_MREQ.we='1' then
irb_err := '1'; -- error
end if;
-- read to data always allowed, addr only incremented when not active
if RB_MREQ.re = '1' and r.go = '0' then
if r.waddr(3) = '1' then -- equivalent waddr>=1000
n.waddr := (others=>'0');
laddr_inc := '1';
else
n.waddr := slv(unsigned(r.waddr) + 1);
end if;
end if;
when rbaddr_iaddr => -- iaddr -----------------
irb_err := RB_MREQ.we;
when rbaddr_ipc => -- ipc -------------------
irb_err := RB_MREQ.we;
when rbaddr_ireg => -- ireg ------------------
irb_err := RB_MREQ.we;
when rbaddr_imal => -- imal ------------------
irb_err := RB_MREQ.we;
imal_re := RB_MREQ.re;
when others => null; -- <> --------------------
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl => -- cntl ------------------
irb_dout(cntl_rbf_mwsup) := r.mwsup;
irb_dout(cntl_rbf_imode) := r.imode;
irb_dout(cntl_rbf_wstop) := r.wstop;
when rbaddr_stat => -- stat ------------------
irb_dout(stat_rbf_bsize) := slv(to_unsigned(AWIDTH-8,3));
irb_dout(stat_rbf_malcnt) := r.mal_waddr;
if SNUM then
irb_dout(stat_rbf_snum) := '1';
end if;
irb_dout(stat_rbf_wrap) := r.wrap;
irb_dout(stat_rbf_susp) := r.susp; -- started and suspended
irb_dout(stat_rbf_run) := r.go or r.susp; -- started
when rbaddr_addr => -- addr ------------------
irb_dout(addr_rbf_laddr) := r.laddr;
irb_dout(addr_rbf_waddr) := r.waddr;
when rbaddr_data => -- data ------------------
case r.waddr is
when "1000" => irb_dout := BRAM_DO(bram_df_word8);
when "0111" => irb_dout := BRAM_DO(bram_df_word7);
when "0110" => irb_dout := BRAM_DO(bram_df_word6);
when "0101" => irb_dout := BRAM_DO(bram_df_word5);
when "0100" => irb_dout := BRAM_DO(bram_df_word4);
when "0011" => irb_dout := BRAM_DO(bram_df_word3);
when "0010" => irb_dout := BRAM_DO(bram_df_word2);
when "0001" => irb_dout := BRAM_DO(bram_df_word1);
when "0000" => irb_dout := BRAM_DO(bram_df_word0);
when others => irb_dout := (others=>'0');
end case;
when rbaddr_iaddr => -- iaddr -----------------
null; -- FIXME_code: implement
when rbaddr_ipc => -- ipc -------------------
irb_dout(r.dp_pc_dec'range) := r.dp_pc_dec;
n.mal_raddr := (others=>'0');
when rbaddr_ireg => -- ireg ------------------
irb_dout := r.dp_ireg;
when rbaddr_imal => -- imal ------------------
irb_dout := MAL_DO;
when others => null;
end case;
end if;
-- cpu monitor
-- capture CPU state signals which are combinatorial logic
if DM_STAT_SE.istart = '1' then
n.dp_pc_fet := DM_STAT_DP.pc(15 downto 1);
end if;
n.dp_ireg := DM_STAT_DP.ireg;
n.dp_ireg_we := DM_STAT_DP.ireg_we;
n.dp_ireg_we_1 := r.dp_ireg_we;
if r.dp_ireg_we = '1' then -- dp_pc_dec update when dp_ireg changes
n.dp_pc_dec := r.dp_pc_fet;
end if;
n.dp_dsrc_we := DM_STAT_DP.dsrc_we;
n.dp_ddst_we := DM_STAT_DP.ddst_we;
n.dp_dres_val := '0';
if ((DM_STAT_DP.gr_we or DM_STAT_DP.psr_we or -- capture dres only when
DM_STAT_DP.dsrc_we or DM_STAT_DP.ddst_we or -- actually used
DM_STAT_DP.dtmp_we or DM_STAT_DP.cpdout_we or
DM_STAT_VM.vmcntl.req) = '1') then
n.dp_dres := DM_STAT_DP.dres;
n.dp_dres_val := '1';
end if;
n.vm_req := DM_STAT_VM.vmcntl.req;
-- capture vm request data when vm_req asserted, need them in later cycles
-- don't update vmaddr for write part of rmw sequence
-- no valid address vmaddr given, address is kept in vmbox
if DM_STAT_VM.vmcntl.req = '1' then
n.vm_wacc_1 := r.vm_wacc;
n.vm_macc_1 := r.vm_macc;
n.vm_cacc_1 := r.vm_cacc;
n.vm_bytop_1 := r.vm_bytop;
n.vm_dspace_1 := r.vm_dspace;
n.vm_wacc := DM_STAT_VM.vmcntl.wacc;
n.vm_macc := DM_STAT_VM.vmcntl.macc;
n.vm_cacc := DM_STAT_VM.vmcntl.cacc;
n.vm_bytop := DM_STAT_VM.vmcntl.bytop;
n.vm_dspace := DM_STAT_VM.vmcntl.dspace;
if (DM_STAT_VM.vmcntl.macc and DM_STAT_VM.vmcntl.wacc) = '0' then
n.vm_addr_1 := r.vm_addr;
n.vm_addr := DM_STAT_VM.vmaddr;
end if;
n.vm_din := DM_STAT_VM.vmdin;
end if;
n.vm_ack := DM_STAT_VM.vmstat.ack;
n.vm_err := DM_STAT_VM.vmstat.err;
if DM_STAT_VM.vmstat.ack = '1' then
n.vm_dout_1 := r.vm_dout;
n.vm_dout := DM_STAT_VM.vmdout;
n.vm_trap_ysv := DM_STAT_VM.vmstat.trap_ysv;
n.vm_trap_mmu := DM_STAT_VM.vmstat.trap_mmu;
end if;
if DM_STAT_VM.vmstat.err = '1' then
n.vm_err_odd := DM_STAT_VM.vmstat.err_odd;
n.vm_err_mmu := DM_STAT_VM.vmstat.err_mmu;
n.vm_err_nxm := DM_STAT_VM.vmstat.err_nxm;
n.vm_err_iobto := DM_STAT_VM.vmstat.err_iobto;
n.vm_err_rsv := DM_STAT_VM.vmstat.err_rsv;
end if;
n.se_istart_1 := r.se_istart;
n.se_idle := DM_STAT_SE.idle;
n.se_istart := DM_STAT_SE.istart;
n.se_idone := DM_STAT_SE.idone;
n.se_vfetch := DM_STAT_SE.vfetch;
n.se_snum := DM_STAT_SE.snum;
-- active state logic
igoeff := '0';
if r.go = '1' then
if DM_STAT_CO.cpugo='1' and DM_STAT_CO.cpususp='0' then
igoeff := '1';
end if;
if DM_STAT_CO.cpustep = '1' then
igoeff := '1';
end if;
end if;
iactive := r.active;
if r.se_idle = '1' then -- in idle state
if igoeff = '0' then -- if goeff=0 stop running
n.active := '0';
end if;
else -- in non-idle state
if igoeff = '1' then -- if goerr=1 start running
iactive := '1';
n.active := '1';
end if;
end if;
if r.vm_req = '1' then
n.mwdrop := '0';
n.vm_pend := '1';
elsif (r.vm_ack or r.vm_err) = '1' then
n.vm_pend := '0';
end if;
itake := '0';
if r.imode = '0' then -- imode=0
itake := '1'; -- take all
if r.mwsup = '1' then -- if mem wait suppress
if (r.vm_pend and not (r.vm_ack or r.vm_err)) = '1' then
itake := '0';
n.mwdrop := '1';
end if;
end if;
else -- imode=1
itake := r.se_idone or r.se_vfetch or r.vm_err;
end if;
if iactive='1' and itake='1' then -- active and enabled
ibramen := '1';
ibramwe := '1';
laddr_inc := '1';
end if;
if laddr_inc = '1' then
n.laddr := slv(unsigned(r.laddr) + 1);
if r.go='1' and r.laddr=laddrlast then
n.wrap := '1';
if r.wstop = '1' then
n.go := '0';
end if;
end if;
end if;
-- last but not least: the clock cycle counter
n.cnum := slv(unsigned(r.cnum) + 1);
-- now build memory data word
idat := (others=>'0');
-- encode vm errors
ivmerr := (others=>'0');
if r.vm_err_odd = '1' then
ivmerr := vmerr_odd;
elsif r.vm_err_mmu = '1' then
ivmerr := vmerr_mmu;
elsif r.vm_err_nxm = '1' then
ivmerr := vmerr_nxm;
elsif r.vm_err_iobto = '1' then
ivmerr := vmerr_iobto;
elsif r.vm_err_rsv = '1' then
ivmerr := vmerr_rsv;
end if;
-- Note for imode=1
-- Write vm request data unless there is an error.
-- If in current or last cycle a ifetch (istart=1) was done use
-- attributes of previous request. If last cycle was an ifetch
-- and vm_ack set use also previous data. That ensures that the
-- values of current instruction are shown, and not of pre-fetch
-- build word8
idat8 := (others=>'0');
if r.vm_req = '1' or (r.imode='1' and r.vm_err='0') then
idat8(dat8_rbf_req) := '1';
if r.imode = '1' and (r.se_istart='1' or r.se_istart_1='1') then
idat8(dat8_rbf_wacc) := R_REGS.vm_wacc_1;
idat8(dat8_rbf_macc) := R_REGS.vm_macc_1;
idat8(dat8_rbf_cacc) := R_REGS.vm_cacc_1;
idat8(dat8_rbf_bytop) := R_REGS.vm_bytop_1;
idat8(dat8_rbf_dspace) := R_REGS.vm_dspace_1;
else
idat8(dat8_rbf_wacc) := R_REGS.vm_wacc;
idat8(dat8_rbf_macc) := R_REGS.vm_macc;
idat8(dat8_rbf_cacc) := R_REGS.vm_cacc;
idat8(dat8_rbf_bytop) := R_REGS.vm_bytop;
idat8(dat8_rbf_dspace) := R_REGS.vm_dspace;
end if;
else
idat8(dat8_rbf_ack) := R_REGS.vm_ack;
idat8(dat8_rbf_err) := R_REGS.vm_err;
if r.vm_ack = '1' then
idat8(dat8_rbf_trap_ysv) := R_REGS.vm_trap_ysv;
idat8(dat8_rbf_trap_mmu) := R_REGS.vm_trap_mmu;
idat8(dat8_rbf_mwdrop) := R_REGS.mwdrop;
elsif r.vm_err = '1' then
idat8(dat8_rbf_vmerr) := ivmerr;
end if;
end if;
idat8(dat8_rbf_istart) := R_REGS.se_istart;
idat8(dat8_rbf_idone) := R_REGS.se_idone;
if r.imode = '0' then
idat8(dat8_rbf_snum) := R_REGS.se_snum;
else
idat8(dat8_rbf_cnum) := R_REGS.cnum;
end if;
idat(bram_df_word8) := idat8;
-- build word7
idat7 := (others=>'0');
idat7(dat7_rbf_pc) := R_REGS.dp_pc_dec;
idat7(dat7_rbf_idecode):= R_REGS.dp_ireg_we_1;
idat(bram_df_word7) := idat7;
-- build word6
idat(bram_df_word6) := R_REGS.dp_ireg;
-- build word5
idat5 := (others=>'0');
idat5(dat5_rbf_cmode) := DM_STAT_DP.psw.cmode;
idat5(dat5_rbf_pmode) := DM_STAT_DP.psw.pmode;
idat5(dat5_rbf_rset) := DM_STAT_DP.psw.rset;
if r.imode = '0' then
idat5(dat5_rbf_dres_val) := R_REGS.dp_dres_val;
idat5(dat5_rbf_ddst_we) := R_REGS.dp_ddst_we;
idat5(dat5_rbf_dsrc_we) := R_REGS.dp_dsrc_we;
else
idat5(dat5_rbf_vfetch) := R_REGS.se_vfetch;
end if;
idat5(dat5_rbf_pri) := DM_STAT_DP.psw.pri;
idat5(dat5_rbf_tflag) := DM_STAT_DP.psw.tflag;
idat5(dat5_rbf_cc) := DM_STAT_DP.psw.cc;
idat(bram_df_word5) := idat5;
-- build word4 to word2
idat(bram_df_word4) := DM_STAT_DP.dsrc;
idat(bram_df_word3) := DM_STAT_DP.ddst;
idat(bram_df_word2) := R_REGS.dp_dres;
-- build word1
if r.imode = '1' and (r.se_istart='1' or r.se_istart_1='1') then
idat(bram_df_word1) := R_REGS.vm_addr_1;
else
idat(bram_df_word1) := R_REGS.vm_addr;
end if;
-- build word0
if r.vm_wacc = '1' then
idat(bram_df_word0) := R_REGS.vm_din;
else
if r.imode = '1' and r.se_istart_1 = '1' and r.vm_ack = '1' then
idat(bram_df_word0) := R_REGS.vm_dout_1;
else
idat(bram_df_word0) := R_REGS.vm_dout;
end if;
end if;
-- finally memory access log buffer logic
if r.vm_cacc = '0' then
if r.vm_req = '1' then
imal_we := '1';
imal_di := r.vm_addr;
elsif r.vm_ack='1' then
imal_we := '1';
if r.vm_wacc='1' then
imal_di := r.vm_din;
else
imal_di := r.vm_dout;
end if;
if r.vm_bytop = '1' then -- for byte read/write data
imal_di(15 downto 8) := (others=>'0'); -- zero msb (is undefined)
end if;
end if;
end if;
imal_waddr_clr := r.dp_ireg_we; -- FIXME: very preliminary !!!
if imal_waddr_clr = '1' then
n.mal_waddr := (others=>'0');
elsif imal_we = '1' then
n.mal_waddr := slv(unsigned(r.mal_waddr) + 1);
end if;
if imal_raddr_clr = '1' then
n.mal_raddr := (others=>'0');
elsif imal_re = '1' then
n.mal_raddr := slv(unsigned(r.mal_raddr) + 1);
end if;
N_REGS <= n;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
BRAM_ADDRA <= '0' & R_REGS.laddr;
BRAM_ADDRB <= '1' & R_REGS.laddr;
BRAM_DI <= idat;
MAL_WE <= imal_we;
MAL_DI <= imal_di;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/bplib/basys3/tb/basys3_dummy.vhd | 1 | 1743 | -- $Id: basys3_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: basys3_dummy - syn
-- Description: basys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_basys3
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2014.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-31 726 1.0.1 fix typos
-- 2015-01-15 634 1.0 Initial version (derived from nexys4_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity basys3_dummy is -- BASYS 3 dummy (base; loopback)
-- implements basys3_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv16; -- b3 switches
I_BTN : in slv5; -- b3 buttons
O_LED : out slv16; -- b3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end basys3_dummy;
architecture syn of basys3_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_SWI; -- mirror SWI on LED
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/rlink/tbcore/rlink_cext_vhpi.vhd | 1 | 1653 | -- $Id: rlink_cext_vhpi.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: rlink_cext_vhpi
-- Description: VHDL procedural interface: VHDL declaration side
--
-- Dependencies: -
-- Tool versions: ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.1 rename vhpi_rriext->rlink_cext_vhpi; new rbv3 names
-- 2007-08-26 76 1.0 Initial version
------------------------------------------------------------------------------
package rlink_cext_vhpi is
impure function rlink_cext_getbyte (
clk : integer) -- clock cycle
return integer;
attribute foreign of rlink_cext_getbyte :
function is "VHPIDIRECT rlink_cext_getbyte";
impure function rlink_cext_putbyte (
dat : integer) -- data byte
return integer;
attribute foreign of rlink_cext_putbyte :
function is "VHPIDIRECT rlink_cext_putbyte";
end package rlink_cext_vhpi;
package body rlink_cext_vhpi is
impure function rlink_cext_getbyte (
clk : integer) -- clock cycle
return integer is
begin
report "rlink_cext_getbyte not vhpi'ed" severity failure;
end rlink_cext_getbyte;
impure function rlink_cext_putbyte (
dat : integer) -- data byte
return integer is
begin
report "rlink_cext_getbyte not vhpi'ed" severity failure;
end rlink_cext_putbyte;
end package body rlink_cext_vhpi;
| gpl-3.0 |
wfjm/w11 | rtl/bplib/mig/tb/sys_conf_ba4_bram.vhd | 1 | 1343 | -- $Id: sys_conf_ba4_bram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf_ba4_msim
-- Description: Definitions for tb_sramif2migui_core (bawidth=4;btyp=bram)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-16 1069 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sys_conf is
-- define constants --------------------------------------------------------
constant c_btyp_msim : string := "MSIM";
constant c_btyp_bram : string := "BRAM";
-- configure ---------------------------------------------------------------
constant sys_conf_mawidth : positive := 28;
constant sys_conf_bawidth : positive := 4; -- 128 bit data path
constant sys_conf_sawidth : positive := 19; -- msim memory size
constant sys_conf_rawidth : positive := 19; -- bram memory size
constant sys_conf_rdelay : positive := 1; -- bram read delay
constant sys_conf_btyp : string := c_btyp_bram;
end package sys_conf;
| gpl-3.0 |
abcsds/Micros | RS232Read_DEPRECATED/RS232Read.vhd | 2 | 1468 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity RS232Read is
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
DATARead: in std_logic_vector(7 downto 0);
NBaud : in std_logic_vector(3 downto 0);
EOR : out std_logic;
Tx : out std_logic
);
end RS232Read;
architecture moore of RS232Read is
signal CTRL : std_logic_vector(3 downto 0);
signal FBaud : std_logic;
component BaudRate
port(
RST : in std_logic;
CLK : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end component;
component register_of_displacement
port(
RST : in std_logic;
CLK : in std_logic;
Rx : in std_logic;
CTRL : in std_logic_vector(1 downto 0);
DATARead : out std_logic_vector(8 downto 0)
);
end component;
component FsmRead is
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
FBaud : in std_logic;
EOR : out std_logic;
CTRL : out std_logic_vector(3 downto 0)
);
end component;
begin
U00 : BaudRate port map(RST,CLK,NBaud,FBaud);
U01 : register_of_displacement port map(RST,CLK,Rx,CTRL,DATARead);
U02 : FsmRead port map(RST,CLK,STR,FBaud,EOR,CTRL);
end moore;
| gpl-3.0 |
nanomolina/vhdl_examples | datapath/mux2.vhd | 4 | 433 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY mux2 IS
GENERIC (N: INTEGER:=32);
PORT (d0, d1: IN std_logic_vector(N-1 DOWNTO 0);
s: IN std_logic;
y: OUT std_logic_vector(N-1 DOWNTO 0));
END mux2;
ARCHITECTURE mux_est OF mux2 IS
BEGIN
PROCESS(s)
BEGIN
IF (s='0') THEN
y <= d0;
ELSIF (s='1') THEN
y <= d1;
END IF;
END PROCESS;
END mux_est;
| gpl-3.0 |
wfjm/w11 | rtl/w11a/pdp11_mmu.vhd | 1 | 14453 | -- $Id: pdp11_mmu.vhd 1294 2022-09-07 14:21:20Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_mmu - syn
-- Description: pdp11: mmu - memory management unit
--
-- Dependencies: pdp11_mmu_padr
-- pdp11_mmu_mmr12
-- ibus/ib_sres_or_3
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-09-05 1294 1,4.4 BUGFIX: correct trap and PDR A logic
-- 2022-08-13 1279 1.4.3 ssr->mmr rename
-- 2011-11-18 427 1.4.2 now numeric_std clean
-- 2010-10-23 335 1.4.1 use ib_sel
-- 2010-10-17 333 1.4 use ibus V2 interface
-- 2010-06-20 307 1.3.7 rename cpacc to cacc in mmu_cntl_type
-- 2009-05-30 220 1.3.6 final removal of snoopers (were already commented)
-- 2009-05-09 213 1.3.5 BUGFIX: tie inst_compl permanentely '0'
-- BUGFIX: set mmr0 trap_mmu even when traps disabled
-- 2008-08-22 161 1.3.4 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
-- 2008-04-27 139 1.3.3 allow mmr1/2 tracing even with mmu_ena=0
-- 2008-04-25 138 1.3.2 add BRESET port, clear mmr0/3 with BRESET
-- 2008-03-02 121 1.3.1 remove snoopers
-- 2008-02-24 119 1.3 return always mapped address in PADDRH; remove
-- cpacc handling; PADDR generation now on _vmbox
-- 2008-01-05 110 1.2.1 rename _mmu_regs -> _mmu_sadr
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2008-01-01 109 1.2 use pdp11_mmu_regs (rather than _regset)
-- 2007-12-31 108 1.1.1 remove SADR memory address mux (-> _mmu_regfile)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_mmu is -- mmu - memory management unit
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
BRESET : in slbit; -- bus reset
CNTL : in mmu_cntl_type; -- control port
VADDR : in slv16; -- virtual address
MONI : in mmu_moni_type; -- monitor port
STAT : out mmu_stat_type; -- status port
PADDRH : out slv16; -- physical address (upper 16 bit)
IB_MREQ: in ib_mreq_type; -- ibus request
IB_SRES: out ib_sres_type -- ibus response
);
end pdp11_mmu;
architecture syn of pdp11_mmu is
constant ibaddr_mmr0 : slv16 := slv(to_unsigned(8#177572#,16));
constant ibaddr_mmr3 : slv16 := slv(to_unsigned(8#172516#,16));
constant mmr0_ibf_abo_nonres : integer := 15;
constant mmr0_ibf_abo_length : integer := 14;
constant mmr0_ibf_abo_rdonly : integer := 13;
constant mmr0_ibf_trap_mmu : integer := 12;
constant mmr0_ibf_ena_trap : integer := 9;
constant mmr0_ibf_inst_compl : integer := 7;
subtype mmr0_ibf_page_mode is integer range 6 downto 5;
constant mmr0_ibf_dspace : integer := 4;
subtype mmr0_ibf_page_num is integer range 3 downto 1;
constant mmr0_ibf_ena_mmu : integer := 0;
constant mmr3_ibf_ena_ubmap : integer := 5;
constant mmr3_ibf_ena_22bit : integer := 4;
constant mmr3_ibf_dspace_km : integer := 2;
constant mmr3_ibf_dspace_sm : integer := 1;
constant mmr3_ibf_dspace_um : integer := 0;
signal IBSEL_MMR0 : slbit := '0'; -- ibus select MMR0
signal IBSEL_MMR3 : slbit := '0'; -- ibus select MMR3
signal R_MMR0 : mmu_mmr0_type := mmu_mmr0_init;
signal N_MMR0 : mmu_mmr0_type := mmu_mmr0_init;
signal R_MMR3 : mmu_mmr3_type := mmu_mmr3_init;
signal APN : slv4 := "0000"; -- augmented page number (1+3 bit)
signal AIB_WE : slbit := '0'; -- update AIB
signal AIB_SETA : slbit := '0'; -- set A bit in access information bits
signal AIB_SETW : slbit := '0'; -- set W bit in access information bits
signal TRACE : slbit := '0'; -- enable tracing in mmr1/2
signal DSPACE : slbit := '0'; -- use dspace
signal IB_SRES_PADR : ib_sres_type := ib_sres_init;
signal IB_SRES_MMR12 : ib_sres_type := ib_sres_init;
signal IB_SRES_MMR03 : ib_sres_type := ib_sres_init;
signal PARPDR : parpdr_type := parpdr_init;
begin
PADR : pdp11_mmu_padr port map (
CLK => CLK,
MODE => CNTL.mode,
APN => APN,
AIB_WE => AIB_WE,
AIB_SETA => AIB_SETA,
AIB_SETW => AIB_SETW,
PARPDR => PARPDR,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_PADR);
MMR12 : pdp11_mmu_mmr12 port map (
CLK => CLK,
CRESET => CRESET,
TRACE => TRACE,
MONI => MONI,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MMR12);
SRES_OR : ib_sres_or_3
port map (
IB_SRES_1 => IB_SRES_PADR,
IB_SRES_2 => IB_SRES_MMR12,
IB_SRES_3 => IB_SRES_MMR03,
IB_SRES_OR => IB_SRES);
SEL_MMR0 : ib_sel
generic map (
IB_ADDR => ibaddr_mmr0)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_MMR0
);
SEL_MMR3 : ib_sel
generic map (
IB_ADDR => ibaddr_mmr3)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_MMR3
);
proc_ibres : process (IBSEL_MMR0, IBSEL_MMR3, IB_MREQ, R_MMR0, R_MMR3)
variable mmr0out : slv16 := (others=>'0');
variable mmr3out : slv16 := (others=>'0');
begin
mmr0out := (others=>'0');
if IBSEL_MMR0 = '1' then
mmr0out(mmr0_ibf_abo_nonres) := R_MMR0.abo_nonres;
mmr0out(mmr0_ibf_abo_length) := R_MMR0.abo_length;
mmr0out(mmr0_ibf_abo_rdonly) := R_MMR0.abo_rdonly;
mmr0out(mmr0_ibf_trap_mmu) := R_MMR0.trap_mmu;
mmr0out(mmr0_ibf_ena_trap) := R_MMR0.ena_trap;
mmr0out(mmr0_ibf_inst_compl) := R_MMR0.inst_compl;
mmr0out(mmr0_ibf_page_mode) := R_MMR0.page_mode;
mmr0out(mmr0_ibf_dspace) := R_MMR0.dspace;
mmr0out(mmr0_ibf_page_num) := R_MMR0.page_num;
mmr0out(mmr0_ibf_ena_mmu) := R_MMR0.ena_mmu;
end if;
mmr3out := (others=>'0');
if IBSEL_MMR3 = '1' then
mmr3out(mmr3_ibf_ena_ubmap) := R_MMR3.ena_ubmap;
mmr3out(mmr3_ibf_ena_22bit) := R_MMR3.ena_22bit;
mmr3out(mmr3_ibf_dspace_km) := R_MMR3.dspace_km;
mmr3out(mmr3_ibf_dspace_sm) := R_MMR3.dspace_sm;
mmr3out(mmr3_ibf_dspace_um) := R_MMR3.dspace_um;
end if;
IB_SRES_MMR03.dout <= mmr0out or mmr3out;
IB_SRES_MMR03.ack <= (IBSEL_MMR0 or IBSEL_MMR3) and
(IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_MMR03.busy <= '0';
end process proc_ibres;
proc_mmr0 : process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_MMR0 <= mmu_mmr0_init;
else
R_MMR0 <= N_MMR0;
end if;
end if;
end process proc_mmr0;
proc_mmr3 : process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_MMR3 <= mmu_mmr3_init;
elsif IBSEL_MMR3='1' and IB_MREQ.we='1' then
if IB_MREQ.be0 = '1' then
R_MMR3.ena_ubmap <= IB_MREQ.din(mmr3_ibf_ena_ubmap);
R_MMR3.ena_22bit <= IB_MREQ.din(mmr3_ibf_ena_22bit);
R_MMR3.dspace_km <= IB_MREQ.din(mmr3_ibf_dspace_km);
R_MMR3.dspace_sm <= IB_MREQ.din(mmr3_ibf_dspace_sm);
R_MMR3.dspace_um <= IB_MREQ.din(mmr3_ibf_dspace_um);
end if;
end if;
end if;
end process proc_mmr3;
proc_paddr : process (R_MMR0, R_MMR3, CNTL, PARPDR, VADDR)
variable ipaddrh : slv16 := (others=>'0');
variable dspace_ok : slbit := '0';
variable dspace_en : slbit := '0';
variable apf : slv3 := (others=>'0'); -- va: active page field
variable bn : slv7 := (others=>'0'); -- va: block number
variable iapn : slv4 := (others=>'0');-- augmented page number
begin
apf := VADDR(15 downto 13);
bn := VADDR(12 downto 6);
dspace_en := '0';
case CNTL.mode is
when "00" => dspace_en := R_MMR3.dspace_km;
when "01" => dspace_en := R_MMR3.dspace_sm;
when "11" => dspace_en := R_MMR3.dspace_um;
when others => null;
end case;
dspace_ok := CNTL.dspace and dspace_en;
iapn(3) := dspace_ok;
iapn(2 downto 0) := apf;
ipaddrh := slv(unsigned("000000000"&bn) + unsigned(PARPDR.paf));
DSPACE <= dspace_ok;
APN <= iapn;
PADDRH <= ipaddrh;
end process proc_paddr;
proc_nmmr0 : process (R_MMR0, R_MMR3, IB_MREQ, IBSEL_MMR0, DSPACE,
CNTL, MONI, PARPDR, VADDR)
variable nmmr0 : mmu_mmr0_type := mmu_mmr0_init;
variable apf : slv3 := (others=>'0');
variable bn : slv7 := (others=>'0');
variable abo_nonres : slbit := '0';
variable abo_length : slbit := '0';
variable abo_rdonly : slbit := '0';
variable mmr_freeze : slbit := '0';
variable doabort : slbit := '0';
variable dotrap : slbit := '0';
variable dotrace : slbit := '0';
variable iswrite : slbit := '0';
begin
nmmr0 := R_MMR0;
AIB_WE <= '0';
AIB_SETA <= '0';
AIB_SETW <= '0';
mmr_freeze := R_MMR0.abo_nonres or R_MMR0.abo_length or R_MMR0.abo_rdonly;
dotrace := not(CNTL.cacc or mmr_freeze);
iswrite := CNTL.wacc or CNTL.macc;
apf := VADDR(15 downto 13);
bn := VADDR(12 downto 6);
abo_nonres := '0';
abo_length := '0';
abo_rdonly := '0';
doabort := '0';
dotrap := '0';
if PARPDR.ed = '0' then -- ed=0: upward expansion
if unsigned(bn) > unsigned(PARPDR.plf) then
abo_length := '1';
end if;
else -- ed=0: downward expansion
if unsigned(bn) < unsigned(PARPDR.plf) then
abo_length := '1';
end if;
end if;
-- ACF decision logic
-- w11 has 4 memory cycle types, the ACF is based only on read or write
-- wacc='0' macc'0' : read cycle --> read
-- wacc='1' macc'0' : write cycle --> write
-- wacc='0' macc'1' : read part of rmw --> write
-- wacc='1' macc'1' : write part of rmw --> write
-- Depending of ACF the MMU aborts, queues a trap, sets A and W bit in PDR
-- ACF abort trap Comment
-- 000 nonres - non-resident: abort all accesses
-- 001 rdonly R read-only: abort on write, trap on read
-- 010 rdonly read-only: abort on write
-- 011 nonres - unused: abort all accesses
-- 100 - R+W read/write: no abort, trap on read or write
-- 101 - W read/write: no abort, trap on write
-- 110 - - read/write: no abort, no trap
-- 111 nonres - unused: abort all accesses
--
-- The PDR W bit is set for non-aborted write accesses
-- The PDR A bit is set if the trap condition is fulfilled and not aborted
case PARPDR.acf is -- evaluate accecc control field
when "000" => -- page non-resident
abo_nonres := '1';
when "001" => -- read-only; trap on read
if iswrite='1' then
abo_rdonly := '1';
end if;
dotrap := not iswrite;
when "010" => -- read-only
if iswrite='1' then
abo_rdonly := '1';
end if;
when "100" => -- read/write; trap on read&write
dotrap := '1';
when "101" => -- read/write; trap on write
dotrap := iswrite;
when "110" => null; -- read/write;
when others => -- unused codes: abort access
abo_nonres := '1';
end case;
if IBSEL_MMR0='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
nmmr0.abo_nonres := IB_MREQ.din(mmr0_ibf_abo_nonres);
nmmr0.abo_length := IB_MREQ.din(mmr0_ibf_abo_length);
nmmr0.abo_rdonly := IB_MREQ.din(mmr0_ibf_abo_rdonly);
nmmr0.trap_mmu := IB_MREQ.din(mmr0_ibf_trap_mmu);
nmmr0.ena_trap := IB_MREQ.din(mmr0_ibf_ena_trap);
end if;
if IB_MREQ.be0 = '1' then
nmmr0.ena_mmu := IB_MREQ.din(mmr0_ibf_ena_mmu);
end if;
elsif nmmr0.ena_mmu='1' and CNTL.cacc='0' then
if dotrace = '1' then
if MONI.istart = '1' then
nmmr0.inst_compl := '0';
elsif MONI.idone = '1' then
nmmr0.inst_compl := '0'; -- disable instr.compl logic
end if;
end if;
if CNTL.req = '1' then
AIB_WE <= '1';
if mmr_freeze = '0' then
nmmr0.abo_nonres := abo_nonres;
nmmr0.abo_length := abo_length;
nmmr0.abo_rdonly := abo_rdonly;
end if;
doabort := abo_nonres or abo_length or abo_rdonly;
if doabort = '0' then
AIB_SETA <= dotrap;
AIB_SETW <= iswrite;
end if;
if mmr_freeze = '0' then
nmmr0.dspace := DSPACE;
nmmr0.page_num := apf;
nmmr0.page_mode := CNTL.mode;
end if;
end if;
end if;
if CNTL.req='1' and R_MMR0.ena_mmu='1' and CNTL.cacc='0' and
dotrap='1' then
nmmr0.trap_mmu := '1';
end if;
nmmr0.trace_prev := dotrace;
if MONI.trace_prev = '0' then
TRACE <= dotrace;
else
TRACE <= R_MMR0.trace_prev;
end if;
N_MMR0 <= nmmr0;
if R_MMR0.ena_mmu='1' and CNTL.cacc='0' then
STAT.vaok <= not doabort;
else
STAT.vaok <= '1';
end if;
if R_MMR0.ena_mmu='1' and CNTL.cacc='0' and doabort='0' and
R_MMR0.ena_trap='1' and R_MMR0.trap_mmu='0' and dotrap='1' then
STAT.trap <= '1';
else
STAT.trap <= '0';
end if;
STAT.ena_mmu <= R_MMR0.ena_mmu;
STAT.ena_22bit <= R_MMR3.ena_22bit;
STAT.ena_ubmap <= R_MMR3.ena_ubmap;
end process proc_nmmr0;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/bplib/bpgen/bp_rs232_4line_iob.vhd | 1 | 2339 | -- $Id: bp_rs232_4line_iob.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_4line_iob - syn
-- Description: iob's for 4 line rs232 (RXD,TXD and RTS,CTS)
--
-- Dependencies: xlib/iob_reg_i
-- xlib/iob_reg_o
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-01 386 1.1 moved and renamed to bpgen
-- 2010-04-17 278 1.0 Initial version (as s3_rs232_iob_ext)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
-- ----------------------------------------------------------------------------
entity bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit; -- pad-o: transmit data (board view)
I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
O_RTS_N : out slbit -- pad-o: request to send (act. low)
);
end bp_rs232_4line_iob;
architecture syn of bp_rs232_4line_iob is
begin
IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD);
IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD);
IOB_CTS : iob_reg_i
port map (CLK => CLK, CE => '1', DI => CTS_N, PAD => I_CTS_N);
IOB_RTS : iob_reg_o
port map (CLK => CLK, CE => '1', DO => RTS_N, PAD => O_RTS_N);
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/serport/serport_2clock.vhd | 1 | 12604 | -- $Id: serport_2clock.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_2clock - syn
-- Description: serial port: serial port module, 2 clock domain
--
-- Dependencies: cdclib/cdc_pulse
-- serport_uart_rxtx_ab
-- serport_xonrx
-- serport_xontx
-- memlib/fifo_2c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-04-12 666 14.7 131013 xc6slx16-2 285 283 32 138 s 6.2/5.9
-- 2011-11-13 424 13.1 O40d xc3s1000-4 224 362 64 295 s 8.6/10.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-28 755 1.1.2 check assertions only at raising clock
-- 2015-04-11 666 1.1.1 add sim assertions for RXOVR and RXERR
-- 2015-02-01 641 1.1 add CLKDIV_F for autobaud;
-- 2011-12-10 438 1.0.2 internal reset on abact
-- 2011-12-09 437 1.0.1 rename stat->moni port
-- 2011-11-13 424 1.0 Initial version
-- 2011-11-07 421 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.cdclib.all;
use work.memlib.all;
entity serport_2clock is -- serial port module, 2 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLKU : in slbit; -- clock (backend:user)
RESET : in slbit; -- reset
CLKS : in slbit; -- clock (frontend:serial)
CES_MSEC : in slbit; -- S|1 msec clock enable
ENAXON : in slbit; -- U|enable xon/xoff handling
ENAESC : in slbit; -- U|enable xon/xoff escaping
RXDATA : out slv8; -- U|receiver data out
RXVAL : out slbit; -- U|receiver data valid
RXHOLD : in slbit; -- U|receiver data hold
TXDATA : in slv8; -- U|transmit data in
TXENA : in slbit; -- U|transmit data enable
TXBUSY : out slbit; -- U|transmit busy
MONI : out serport_moni_type; -- U|serport monitor port
RXSD : in slbit; -- S|receive serial data (uart view)
TXSD : out slbit; -- S|transmit serial data (uart view)
RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
);
end serport_2clock;
architecture syn of serport_2clock is
type synu_type is record
rxact_c : slbit; -- rxact (capt from CLKS->CLKU)
rxact_s : slbit; -- rxact (sync in CLKU)
txact_c : slbit; -- txact (capt from CLKS->CLKU)
txact_s : slbit; -- txact (sync in CLKU)
abact_c : slbit; -- abact (capt from CLKS->CLKU)
abact_s : slbit; -- abact (sync in CLKU)
rxok_c : slbit; -- rxok (capt from CLKS->CLKU)
rxok_s : slbit; -- rxok (sync in CLKU)
txok_c : slbit; -- txok (capt from CLKS->CLKU)
txok_s : slbit; -- txok (sync in CLKU)
abclkdiv_c : slv(CDWIDTH-1 downto 0); -- abclkdiv (capt from CLKS->CLKU)
abclkdiv_s : slv(CDWIDTH-1 downto 0); -- abclkdiv (sync in CLKU)
end record synu_type;
constant synu_init : synu_type := (
'0','0', -- rxact_c,_s
'0','0', -- txact_c,_s
'0','0', -- abact_c,_s
'0','0', -- rxok_c,_s
'0','0', -- txok_c,_s
slv(to_unsigned(0,CDWIDTH)), -- abclkdiv_c
slv(to_unsigned(0,CDWIDTH)) -- abclkdiv_s
);
type syns_type is record
enaxon_c : slbit; -- enaxon (capt from CLKU->CLKS)
enaxon_s : slbit; -- enaxon (sync in CLKS)
enaesc_c : slbit; -- enaesc (capt from CLKU->CLKS)
enaesc_s : slbit; -- enaesc (sync in CLKS)
end record syns_type;
constant syns_init : syns_type := (
'0','0', -- enaxon_c,_s
'0','0' -- enaxon_c,_s
);
signal R_SYNU : synu_type := synu_init; -- sync registers (clku)
signal R_SYNS : syns_type := syns_init; -- sync registers (clks)
signal R_RXOK : slbit := '1';
signal RESET_INT : slbit := '0';
signal RESET_CLKS : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXFIFO_SIZEW : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal RXERR : slbit := '0';
signal RXOVR : slbit := '0';
signal RXACT : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
signal TXOK : slbit := '0';
signal RXOK : slbit := '0';
signal RXERR_CLKU : slbit := '0';
signal RXOVR_CLKU : slbit := '0';
signal ABDONE_CLKU : slbit := '0';
begin
assert CDWIDTH<=16
report "assert(CDWIDTH<=16): max width of UART clock divider"
severity failure;
CDC_RESET : cdc_pulse
generic map (
POUT_SINGLE => false,
BUSY_WACK => false)
port map (
CLKM => CLKU,
RESET => '0',
CLKS => CLKS,
PIN => RESET,
BUSY => open,
POUT => RESET_CLKS
);
UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLKS,
CE_MSEC => CES_MSEC,
RESET => RESET_CLKS,
RXSD => RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
ABACT => ABACT,
ABDONE => ABDONE,
ABCLKDIV => ABCLKDIV,
ABCLKDIV_F => open
);
RESET_INT <= RESET_CLKS or ABACT;
XONRX : serport_xonrx -- xon/xoff logic rx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => R_SYNS.enaxon_s,
ENAESC => R_SYNS.enaesc_s,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXFIFO_DI,
RXVAL => RXFIFO_ENA,
RXHOLD => RXFIFO_BUSY,
RXOVR => RXOVR,
TXOK => TXOK
);
XONTX : serport_xontx -- xon/xoff logic tx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => R_SYNS.enaxon_s,
ENAESC => R_SYNS.enaesc_s,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXFIFO_DO,
TXENA => TXFIFO_VAL,
TXBUSY => TXFIFO_HOLD,
RXOK => RXOK,
TXOK => TXOK
);
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKS,
CLKR => CLKU,
RESETW => ABACT, -- clear fifo on abact
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXFIFO_SIZEW,
SIZER => open
);
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKU,
CLKR => CLKS,
RESETW => RESET,
RESETR => ABACT, -- clear fifo on abact
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => open,
SIZER => open
);
-- receive back pressure
-- on if fifo more than 3/4 full (less than 1/4 free)
-- off if fifo less than 1/2 full (more than 1/2 free)
proc_rxok: process (CLKS)
constant rxsize_rxok_off : slv2 := "01";
constant rxsize_rxok_on : slv2 := "10";
variable rxsize_msb : slv2 := "00";
begin
if rising_edge(CLKS) then
if RESET_INT = '1' then
R_RXOK <= '1';
else
rxsize_msb := RXFIFO_SIZEW(RXFAWIDTH-1 downto RXFAWIDTH-2);
if unsigned(rxsize_msb) < unsigned(rxsize_rxok_off) then
R_RXOK <= '0';
elsif unsigned(RXSIZE_MSB) >= unsigned(rxsize_rxok_on) then
R_RXOK <= '1';
end if;
end if;
end if;
end process proc_rxok;
RXOK <= R_RXOK;
RXRTS_N <= not R_RXOK;
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
proc_synu: process (CLKU)
begin
if rising_edge(CLKU) then
R_SYNU.rxact_c <= RXACT;
R_SYNU.rxact_s <= R_SYNU.rxact_c;
R_SYNU.txact_c <= UART_TXBUSY;
R_SYNU.txact_s <= R_SYNU.txact_c;
R_SYNU.abact_c <= ABACT;
R_SYNU.abact_s <= R_SYNU.abact_c;
R_SYNU.rxok_c <= RXOK;
R_SYNU.rxok_s <= R_SYNU.rxok_c;
R_SYNU.txok_c <= TXOK;
R_SYNU.txok_s <= R_SYNU.txok_c;
R_SYNU.abclkdiv_c <= ABCLKDIV;
R_SYNU.abclkdiv_s <= R_SYNU.abclkdiv_c;
end if;
end process proc_synu;
proc_syns: process (CLKS)
begin
if rising_edge(CLKS) then
R_SYNS.enaxon_c <= ENAXON;
R_SYNS.enaxon_s <= R_SYNS.enaxon_c;
R_SYNS.enaesc_c <= ENAESC;
R_SYNS.enaesc_s <= R_SYNS.enaesc_c;
end if;
end process proc_syns;
CDC_RXERR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXERR,
BUSY => open,
POUT => RXERR_CLKU
);
CDC_RXOVR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXOVR,
BUSY => open,
POUT => RXOVR_CLKU
);
CDC_ABDONE : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => ABDONE,
BUSY => open,
POUT => ABDONE_CLKU
);
MONI.rxerr <= RXERR_CLKU;
MONI.rxovr <= RXOVR_CLKU;
MONI.rxact <= R_SYNU.rxact_s;
MONI.txact <= R_SYNU.txact_s;
MONI.abact <= R_SYNU.abact_s;
MONI.abdone <= ABDONE_CLKU;
MONI.rxok <= R_SYNU.rxok_s;
MONI.txok <= R_SYNU.txok_s;
proc_abclkdiv: process (R_SYNU.abclkdiv_s)
begin
MONI.abclkdiv <= (others=>'0');
MONI.abclkdiv(R_SYNU.abclkdiv_s'range) <= R_SYNU.abclkdiv_s;
end process proc_abclkdiv;
-- synthesis translate_off
proc_check: process (CLKS)
begin
if rising_edge(CLKS) then
assert RXOVR = '0'
report "serport_2clock-W: RXOVR = " & slbit'image(RXOVR) &
"; data loss in receive fifo"
severity warning;
assert RXERR = '0'
report "serport_2clock-W: RXERR = " & slbit'image(RXERR) &
"; spurious receive error"
severity warning;
end if;
end process proc_check;
-- synthesis translate_on
end syn;
| gpl-3.0 |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_02400_good.vhd | 1 | 2764 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-15 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_02400_good.vhd
-- File Creation date : 2015-04-15
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Preservation of reset name: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
--CODE
entity CNE_02400_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_02400_good;
architecture Behavioral of CNE_02400_good is
begin
DFF1:DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => open
);
end Behavioral;
--CODE | gpl-3.0 |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4d/tb/sys_conf1_sim.vhd | 1 | 2090 | -- $Id: sys_conf1_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop1_n4d (for test bench)
--
-- Dependencies: -
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec stays to 120 cycles (1.0 usec) and a msec to
-- 240 cycles (2 usec). This affects mainly the autobauder. A break will be
-- detected after 128 msec periods, this in simulation after 256 usec or
-- 30720 cycles. This is compatible with bitrates of 115200 baud or higher
-- (115200 <-> 8.68 usec <-> 1040 cycles)
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkdiv_msecdiv : integer := 2; -- shortened !!
-- configure hio interfaces -----------------------------------------------
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure serport ------------------------------------------------------
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/rlink/tbcore/rlink_cext_iface_vhpi.vhd | 1 | 2443 | -- $Id: rlink_cext_iface_vhpi.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_cext_iface - sim
-- Description: Interface to external C code for tbcore_rlink - VHPI version
--
-- Dependencies: -
--
-- To test: -
--
-- Target Devices: generic
-- Tool versions: ghdl 0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-07 729 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlink_cext_vhpi.all;
entity rlink_cext_iface is -- interface to external C code - VHPI
port (
CLK : in slbit; -- clock
CLK_CYCLE : in slv32; -- clock cycle number
RX_DATA : out slv32; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end rlink_cext_iface;
architecture sim of rlink_cext_iface is
signal R_RXDATA : slv32 := (others=>'1');
signal R_RXVAL : slbit := '0';
begin
proc_put: process (CLK)
variable itxrc : integer := 0;
begin
if rising_edge(CLK) then
if TX_ENA = '1' then
itxrc := rlink_cext_putbyte(to_integer(unsigned(TX_DATA)));
assert itxrc=0
report "rlink_cext_putbyte error: " & integer'image(itxrc)
severity failure;
end if;
end if;
end process proc_put;
proc_get: process (CLK)
variable irxint : integer := 0;
begin
if rising_edge(CLK) then
if RX_HOLD = '0' or R_RXVAL = '0' then
irxint := rlink_cext_getbyte(to_integer(signed(CLK_CYCLE)));
R_RXDATA <= slv(to_signed(irxint, 32));
if irxint >= 0 then
R_RXVAL <= '1';
else
R_RXVAL <= '0';
end if;
end if;
end if;
end process proc_get;
RX_DATA <= R_RXDATA;
RX_VAL <= R_RXVAL;
end sim;
| gpl-3.0 |
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