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wfjm/w11 | rtl/bplib/issi/is61wv5128bll.vhd | 1 | 3388 | -- $Id: is61wv5128bll.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: is61wv5128bll - sim
-- Description: ISSI IS61WV5128BLL SRAM model
-- Currently a truely minimalistic functional model, without
-- any timing checks. It assumes, that addr/data is stable at
-- the trailing edge of we.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2016.4; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-04 906 1.0 Initial version (derived from is61lv25616al)
------------------------------------------------------------------------------
-- Truth table accoring to data sheet:
--
-- Mode WE_N CE_N OE_N D
-- Not selected X H X high-Z
-- Output disabled H L H high-Z
-- X L X high-Z
-- Read H L L D_out
-- Write L L X D_in
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity is61wv5128bll is -- ISSI 61WV5128bll SRAM model
port (
CE_N : in slbit; -- chip enable (act.low)
OE_N : in slbit; -- output enable (act.low)
WE_N : in slbit; -- write enable (act.low)
ADDR : in slv19; -- address lines
DATA : inout slv8 -- data lines
);
end is61wv5128bll;
architecture sim of is61wv5128bll is
constant T_rc : Delay_length := 10 ns; -- read cycle time (min)
constant T_aa : Delay_length := 10 ns; -- address access time (max)
constant T_oha : Delay_length := 2 ns; -- output hold time (min)
constant T_ace : Delay_length := 10 ns; -- ce access time (max)
constant T_doe : Delay_length :=4.5 ns; -- oe access time (max)
constant T_hzoe : Delay_length := 4 ns; -- oe to high-Z output (max)
constant T_lzoe : Delay_length := 0 ns; -- oe to low-Z output (min)
constant T_hzce : Delay_length := 4 ns; -- ce to high-Z output (min=0,max=4)
constant T_lzce : Delay_length := 3 ns; -- ce to low-Z output (min)
constant memsize : positive := 2**(ADDR'length);
constant datzero : slv(DATA'range) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DATA'range);
signal CE : slbit := '0';
signal OE : slbit := '0';
signal WE : slbit := '0';
signal WE_EFF : slbit := '0';
begin
CE <= not CE_N;
OE <= not OE_N;
WE <= not WE_N;
WE_EFF <= CE and WE;
proc_sram: process (CE, OE, WE, WE_EFF, ADDR, DATA)
variable ram : ram_type := (others=>datzero);
begin
if falling_edge(WE_EFF) then -- end of write cycle
-- note: to_x01 used below to prevent
-- that 'z' a written into mem.
ram(to_integer(unsigned(ADDR))) := to_x01(DATA);
end if;
if CE='1' and OE='1' and WE='0' then -- output driver
DATA <= ram(to_integer(unsigned(ADDR)));
else
DATA <= (others=>'Z');
end if;
end process proc_sram;
end sim;
| gpl-3.0 |
wfjm/w11 | rtl/bplib/fx2lib/tb/fx2_2fifo_core.vhd | 1 | 7472 | -- $Id: fx2_2fifo_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifo_core - sim
-- Description: Cypress EZ-USB FX2 (2 fifo core model)
--
-- Dependencies: memlib/fifo_2c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.0.1 proc_ifclk: remove clock stop (not needed anymore)
-- 2013-01-04 469 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
use work.fx2lib.all;
use work.memlib.all;
entity fx2_2fifo_core is -- EZ-USB FX2 (2 fifo core model)
port (
CLK : in slbit; -- uplink clock
RESET : in slbit; -- reset
RXDATA : in slv8; -- rx data (ext->fx2)
RXENA : in slbit; -- rx enable
RXBUSY : out slbit; -- rx busy
TXDATA : out slv8; -- tx data (fx2->ext)
TXVAL : out slbit; -- tx valid
IFCLK : out slbit; -- fx2 interface clock
FIFO : in slv2; -- fx2 fifo address
FLAG : out slv4; -- fx2 fifo flags
SLRD_N : in slbit; -- fx2 read enable (act.low)
SLWR_N : in slbit; -- fx2 write enable (act.low)
SLOE_N : in slbit; -- fx2 output enable (act.low)
PKTEND_N : in slbit; -- fx2 packet end (act.low)
DATA : inout slv8 -- fx2 data lines
);
end fx2_2fifo_core;
architecture sim of fx2_2fifo_core is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
constant bufsize : positive := 1024;
constant datzero : slv(DATA'range) := (others=>'0');
type buf_type is array (0 to bufsize-1) of slv(DATA'range);
signal CLK30 : slbit := '0';
signal RXFIFO_DO : slv8 := (others=>'0');
signal RXFIFO_VAL : slbit := '0';
signal RXFIFO_HOLD : slbit := '0';
signal TXFIFO_DI : slv8 := (others=>'0');
signal TXFIFO_ENA : slbit := '0';
signal TXFIFO_BUSY : slbit := '0';
signal R_FLAG : slv4 := (others=>'0');
signal R_DATA : slv8 := (others=>'0');
-- added for debug purposes
signal R_rxbuf_rind : natural := 0;
signal R_rxbuf_wind : natural := 0;
signal R_rxbuf_nbyt : natural := 0;
signal R_txbuf_rind : natural := 0;
signal R_txbuf_wind : natural := 0;
signal R_txbuf_nbyt : natural := 0;
begin
RXFIFO : fifo_2c_dram
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => CLK30,
RESETW => '0',
RESETR => '0',
DI => RXDATA,
ENA => RXENA,
BUSY => RXBUSY,
DO => RXFIFO_DO,
VAL => RXFIFO_VAL,
HOLD => RXFIFO_HOLD,
SIZEW => open,
SIZER => open
);
TXFIFO : fifo_2c_dram
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLKW => CLK30,
CLKR => CLK,
RESETW => '0',
RESETR => '0',
DI => TXFIFO_DI,
ENA => TXFIFO_ENA,
BUSY => TXFIFO_BUSY,
DO => TXDATA,
VAL => TXVAL,
HOLD => '0',
SIZEW => open,
SIZER => open
);
proc_ifclk: process
constant offset : Delay_length := 200 ns;
constant halfperiod_7 : Delay_length := 16700 ps;
constant halfperiod_6 : Delay_length := 16600 ps;
begin
CLK30 <= '0';
wait for offset;
loop
CLK30 <= '1';
wait for halfperiod_7;
CLK30 <= '0';
wait for halfperiod_7;
CLK30 <= '1';
wait for halfperiod_6;
CLK30 <= '0';
wait for halfperiod_7;
CLK30 <= '1';
wait for halfperiod_7;
CLK30 <= '0';
wait for halfperiod_6;
end loop;
end process proc_ifclk;
proc_state: process (CLK30)
variable rxbuf : buf_type := (others=>datzero);
variable rxbuf_rind : natural := 0;
variable rxbuf_wind : natural := 0;
variable rxbuf_nbyt : natural := 0;
variable txbuf : buf_type := (others=>datzero);
variable txbuf_rind : natural := 0;
variable txbuf_wind : natural := 0;
variable txbuf_nbyt : natural := 0;
variable oline : line;
begin
if rising_edge(CLK30) then
RXFIFO_HOLD <= '0';
TXFIFO_ENA <= '0';
-- rxfifo -> rxbuf
if RXFIFO_VAL = '1' then
if rxbuf_nbyt < bufsize then
rxbuf(rxbuf_wind) := RXFIFO_DO;
rxbuf_wind := (rxbuf_wind + 1) mod bufsize;
rxbuf_nbyt := rxbuf_nbyt + 1;
else
RXFIFO_HOLD <= '1';
end if;
end if;
-- txbuf -> txfifo
if txbuf_nbyt>0 and TXFIFO_BUSY='0' then
TXFIFO_DI <= txbuf(txbuf_rind);
TXFIFO_ENA <= '1';
txbuf_rind := (txbuf_rind + 1) mod bufsize;
txbuf_nbyt := txbuf_nbyt - 1;
end if;
-- slrd cycle: rxbuf -> data
if SLRD_N = '0' then
if rxbuf_nbyt > 0 then
rxbuf_rind := (rxbuf_rind + 1) mod bufsize;
rxbuf_nbyt := rxbuf_nbyt - 1;
else
write(oline, string'("fx2_2fifo_core: SLRD_N=0 when rxbuf empty"));
writeline(output, oline);
end if;
end if;
R_DATA <= rxbuf(rxbuf_rind);
-- slwr cycle: data -> txbuf
if SLWR_N = '0' then
if txbuf_nbyt < bufsize then
txbuf(txbuf_wind) := DATA;
txbuf_wind := (txbuf_wind + 1) mod bufsize;
txbuf_nbyt := txbuf_nbyt + 1;
else
write(oline, string'("fx2_2fifo_core: SLWR_N=0 when txbuf full"));
writeline(output, oline);
end if;
end if;
-- prepare flags (note that FLAGs are act.low!)
R_FLAG <= (others=>'1');
-- FLAGA = indexed, PF
-- rx endpoint -> PF 'almost empty' at 3 bytes to go
if FIFO = c_rxfifo then
if rxbuf_nbyt < 4 then
R_FLAG(0) <= '0';
end if;
-- tx endpoint -> PF 'almost full' at 3 bytes to go
elsif FIFO = c_txfifo then
if txbuf_nbyt > bufsize-4 then
R_FLAG(0) <= '0';
end if;
end if;
-- FLAGB = EP6 FF
if txbuf_nbyt = bufsize then
R_FLAG(1) <= '0';
end if;
-- FLAGC = EP4 EF
if rxbuf_nbyt = 0 then
R_FLAG(2) <= '0';
end if;
-- FLAGD = EP8 FF
R_FLAG(3) <= '1';
-- added for debug purposes
R_rxbuf_rind <= rxbuf_rind;
R_rxbuf_wind <= rxbuf_wind;
R_rxbuf_nbyt <= rxbuf_nbyt;
R_txbuf_rind <= txbuf_rind;
R_txbuf_wind <= txbuf_wind;
R_txbuf_nbyt <= txbuf_nbyt;
end if;
end process proc_state;
IFCLK <= CLK30;
FLAG <= R_FLAG;
proc_data: process (SLOE_N, R_DATA)
begin
if SLOE_N = '1' then
DATA <= (others=>'Z');
else
DATA <= R_DATA;
end if;
end process proc_data;
end sim;
| gpl-3.0 |
wfjm/w11 | rtl/ibus/ibd_kw11l.vhd | 1 | 5887 | -- $Id: ibd_kw11l.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibd_kw11l - syn
-- Description: ibus dev(loc): KW11-L (line clock)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2017.2; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 9 23 0 14 s 5.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 8 25 0 15 s 5.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-24 1138 1.2.1 add csr.ir; csr only loc writable;
-- csr.moni can be cleared, but not set by loc write
-- 2015-05-09 676 1.2 add CPUSUSP, freeze timer when cpu suspended
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2009-06-01 221 1.0.5 BUGFIX: add RESET; don't clear tcnt on ibus reset
-- 2008-08-22 161 1.0.4 use iblib; add EI_ACK to proc_next sens. list
-- 2008-05-09 144 1.0.3 use intreq flop, use EI_ACK
-- 2008-01-20 112 1.0.2 fix proc_next sensitivity list; use BRESET
-- 2008-01-06 111 1.0.1 Renamed to ibd_kw11l (RRI_REQ not used)
-- 2008-01-05 110 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibd_kw11l is -- ibus dev(loc): KW11-L (line clock)
-- fixed address: 177546
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
CPUSUSP : in slbit; -- cpu suspended
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibd_kw11l;
architecture syn of ibd_kw11l is
constant ibaddr_kw11l : slv16 := slv(to_unsigned(8#177546#,16));
constant lks_ibf_moni : integer := 7;
constant lks_ibf_ie : integer := 6;
constant lks_ibf_ir : integer := 5;
constant twidth : natural := 5;
constant tdivide : natural := 20;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
ie : slbit; -- interrupt enable
moni : slbit; -- monitor bit
intreq : slbit; -- interrupt request
tcnt : slv(twidth-1 downto 0); -- timer counter
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'0', -- ie
'1', -- moni (set on reset !!)
'0', -- intreq
(others=>'0') -- tcnt
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.tcnt <= N_REGS.tcnt; -- don't clear msec tick counter
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, CE_MSEC, CPUSUSP, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibw0 : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr=ibaddr_kw11l(12 downto 1) then
n.ibsel := '1';
end if;
-- ibus output driver
if r.ibsel = '1' then
idout(lks_ibf_moni) := r.moni;
idout(lks_ibf_ie) := r.ie;
if IB_MREQ.racc = '1' then -- rri ---------------------
idout(lks_ibf_ir) := r.intreq;
end if;
end if;
-- ibus write transactions
if r.ibsel='1' and ibw0='1' then
if IB_MREQ.racc = '0' then -- cpu ---------------------
n.ie := IB_MREQ.din(lks_ibf_ie);
if IB_MREQ.din(lks_ibf_moni) = '0' then -- write 0 to moni
n.moni := '0'; -- clears moni
end if;
if IB_MREQ.din(lks_ibf_ie) = '0' then -- ie set 0
n.intreq := '0'; -- cancel interrupt
end if;
end if;
end if;
-- other state changes
if CE_MSEC='1' and CPUSUSP='0' then -- on msec and not suspended
n.tcnt := slv(unsigned(r.tcnt) + 1);
if unsigned(r.tcnt) = tdivide-1 then
n.tcnt := (others=>'0');
n.moni := '1';
if r.ie = '1' then
n.intreq := '1';
end if;
end if;
end if;
if EI_ACK = '1' then
n.intreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
EI_REQ <= r.intreq;
end process proc_next;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/xlib/usr_access_unisim.vhd | 1 | 1576 | -- $Id: usr_access_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: usr_access_unisim - syn
-- Description: Wrapper for USR_ACCESS* entities
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Series-7
-- Tool versions: viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-02 758 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity usr_access_unisim is -- wrapper for USR_ACCESS family
port (
DATA : out slv32 -- usr_access register value
);
end usr_access_unisim;
architecture syn of usr_access_unisim is
signal DATA_RAW : slv32 := (others=>'0');
begin
UA : USR_ACCESSE2
port map (
CFGCLK => open,
DATA => DATA_RAW,
DATAVALID => open
);
-- the USR_ACCESSE2 simulation model unfortunately returns always 'UUUU'
-- no way to configure it for reasonable simulation behavior
-- there this sanitiser
proc_data: process (DATA_RAW)
variable idata : slv32 := (others=>'0');
begin
idata := to_x01(DATA_RAW);
if is_x(idata) then
idata := (others=>'0');
end if;
DATA <= idata;
end process proc_data;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/bplib/nexys3/tb/sys_conf_sim.vhd | 1 | 1300 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2013 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_nexys3_fusp_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2011-11-25 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 4;
constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 75 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 75 MHz
constant sys_conf_clksys_gentype : string := "DCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/serport/serport_uart_rxtx.vhd | 1 | 2609 | -- $Id: serport_uart_rxtx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_rxtx - syn
-- Description: serial port UART - transmitter + receiver
--
-- Dependencies: serport_uart_rx
-- serport_uart_tx
-- Test bench: tb/tb_serport_uart_rxtx
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2007-06-24 60 1.0 Initial version
------------------------------------------------------------------------------
-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
-- !!!! appended to the name, has been created in the /tb sub folder.
-- !!!! Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity serport_uart_rxtx is -- serial port uart: rx+tx combo
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end serport_uart_rxtx;
architecture syn of serport_uart_rxtx is
begin
RX : serport_uart_rx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT
);
TX : serport_uart_tx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/rbus/rbd_usracc.vhd | 1 | 2546 | -- $Id: rbd_usracc.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rbd_usracc - syn
-- Description: rbus dev: return usr_access register (bitfile+jtag timestamp)
--
-- Dependencies: xlib/usr_access_unisim
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2015.4-2018.2; ghdl 0.33-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-02 758 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 0 ua0 r/-/- use_accress lsb
-- 1 ua1 r/-/- use_accress msb
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.rblib.all;
use work.rbdlib.all;
entity rbd_usracc is -- rbus dev: return usr_access register
generic (
RB_ADDR : slv16 := rbaddr_usracc);
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type -- rbus: response
);
end entity rbd_usracc;
architecture syn of rbd_usracc is
signal R_SEL : slbit := '0';
signal DATA : slv32 := (others=>'0');
begin
RBSEL : rb_sel
generic map (
RB_ADDR => RB_ADDR,
SAWIDTH => 1)
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
SEL => R_SEL
);
UA : usr_access_unisim
port map (DATA => DATA);
proc_next : process (R_SEL, RB_MREQ, DATA)
variable irb_ack : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
begin
irb_ack := '0';
irb_err := '0';
irb_dout := (others=>'0');
-- rbus transactions
if R_SEL = '1' then
irb_ack := RB_MREQ.re or RB_MREQ.we;
if RB_MREQ.we = '1' then
irb_err := '1';
end if;
if RB_MREQ.re = '1' then
case (RB_MREQ.addr(0)) is
when '0' => irb_dout := DATA(15 downto 0);
when '1' => irb_dout := DATA(31 downto 16);
when others => null;
end case;
end if;
end if;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= '0';
end process proc_next;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/bplib/arty/miglib_arty.vhd | 1 | 6062 | -- $Id: miglib_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: miglib_arty
-- Description: MIG interface components - for arty
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-17 1071 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.miglib.all;
package miglib_arty is
constant mig_bawidth : positive := 4; -- byte addr width
constant mig_mawidth : positive := 28; -- mem addr width
constant mig_mwidth : positive := 2**mig_bawidth; -- mask width ( 16)
constant mig_dwidth : positive := 8*mig_mwidth; -- data width (128)
component sramif_mig_arty is -- SRAM to DDR via MIG for arty
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
CLKMIG : in slbit; -- sys clock for mig core
CLKREF : in slbit; -- ref clock for mig core
TEMP : in slv12; -- die temperature
MONI : out sramif2migui_moni_type;-- monitor signals
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end component;
component migui_arty is -- MIG generated for arty
port (
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1; -- dram: on-die termination
APP_ADDR : in slv(mig_mawidth-1 downto 0); -- MIGUI address
APP_CMD : in slv3; -- MIGUI command
APP_EN : in slbit; -- MIGUI command enable
APP_WDF_DATA : in slv(mig_dwidth-1 downto 0); -- MIGUI write data
APP_WDF_END : in slbit; -- MIGUI write end
APP_WDF_MASK : in slv(mig_mwidth-1 downto 0); -- MIGUI write mask
APP_WDF_WREN : in slbit; -- MIGUI write enable
APP_RD_DATA : out slv(mig_dwidth-1 downto 0); -- MIGUI read data
APP_RD_DATA_END : out slbit; -- MIGUI read end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_SR_REQ : in slbit; -- MIGUI reserved (tie to 0)
APP_REF_REQ : in slbit; -- MIGUI refresh reques
APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
APP_SR_ACTIVE : out slbit; -- MIGUI reserved (ignore)
APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
APP_ZQ_ACK : out slbit; -- MIGUI ZQ calibrate acknowledge
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI calibration done
SYS_CLK_I : in slbit; -- MIGUI system clock
CLK_REF_I : in slbit; -- MIGUI reference clock
DEVICE_TEMP_I : in slv12; -- MIGUI xadc temperature
SYS_RST : in slbit -- MIGUI system reset
);
end component;
end package miglib_arty;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vhd | 1 | 3560 | -- $Id: tb_tst_serloop1_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop1_n2 - sim
-- Description: Test bench for sys_tst_serloop1_n2
--
-- Dependencies: simlib/simclk
-- sys_tst_serloop2_n2 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop1_n2
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report)
-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop1_n2 is
end tb_tst_serloop1_n2;
architecture sim of tb_tst_serloop1_n2 is
signal CLK50 : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50
);
UUT : entity work.sys_tst_serloop1_n2
port map (
I_CLK50 => CLK50,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_FLA_CE_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLK50,
CLKH => CLK50,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd | 1 | 7172 | -- $Id: sys_tst_serloop2_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop2_n4d - syn
-- Description: Tester serial link for nexys4d (serport_2clock case)
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bpgen/bp_rs232_4line_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_2clock2
-- tst_serloop
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2016.2-2022.1; ghdl 0.33-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a100t-1 537 482 12 0 238
-- 2019-02-02 1108 2018.3 xc7a100t-1 537 510 16 0 232
-- 2019-02-02 1108 2017.2 xc7a100t-1 537 552 16 0 238
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.1 use s7_cmt_1ce1ce
-- 2017-01-04 838 1.0 Initial version (derived from sys_tst_serloop2_n4)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop2_n4d is -- top level
-- implements nexys4d_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_serloop2_n4d;
architecture syn of sys_tst_serloop2_n4d is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 8,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => sys_conf_clksys_msecdiv,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => sys_conf_clkser_msecdiv)
port map (
CLKIN => I_CLK100,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
HIO : sn_humanio
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0),
LED => LED(7 downto 0),
DSP_DAT => DSP_DAT(15 downto 0),
DSP_DP => DSP_DP(3 downto 0)
);
IOB_RS232 : bp_rs232_4line_iob
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
SERPORT : serport_2clock2
generic map (
CDWIDTH => 12,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLKU => CLK,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
-- show autobauder clock divisor on msb of display
DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0);
DSP_DAT(19) <= '0';
DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f;
DSP_DP(7 downto 4) <= "0010";
-- setup unused outputs in nexys4d
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vhd | 1 | 7766 | -- $Id: sys_tst_rlink_c7.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_c7 - syn
-- Description: rlink tester design for CmodA7 board
--
-- Dependencies: vlib/xlib/s7_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- bplib/bpgen/rgbdrv_master
-- bplib/bpgen/rgbdrv_analog_rbus
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_4
-- vlib/xlib/iob_reg_o_gen
--
-- Test bench: tb/tb_tst_rlink_c7
--
-- Target Devices: generic
-- Tool versions: viv 2016.4-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1 913 1402 34 3.0 494
-- 2019-02-02 1108 2018.3 xc7a35t-1 913 1494 36 3.0 496
-- 2019-02-02 1108 2017.2 xc7a35t-1 914 1581 36 3.0 510
-- 2017-06-05 907 2016.4 xc7a35t-1 913 1556 36 3.0 513
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-04 906 1.0 Initial version (derived from sys_tst_rlink_arty)
------------------------------------------------------------------------------
-- Usage of CmodA7 Buttons, LEDs, RGBLEDs:
--
-- LED(1): SER_MONI.txact (shows tx activity)
-- LED(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_c7 is -- top level
-- implements cmoda7_aif
port (
I_CLK12 : in slbit; -- 12 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_BTN : in slv2; -- c7 buttons
O_LED : out slv2; -- c7 leds
O_RGBLED0_N : out slv3 -- c7 rgb-led 0
);
end sys_tst_rlink_c7;
architecture syn of sys_tst_rlink_c7 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal LED : slv2 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_RGB0 : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
signal RGBCNTL : slv3 := (others=>'0');
signal DIMCNTL : slv12 := (others=>'0');
constant rbaddr_rgb0 : slv16 := x"fc00"; -- fe00/0004: 1111 1100 0000 00xx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0101"; -- tst_rlink
constant sysid_board : slv8 := x"09"; -- cmoda7
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
GEN_CLKSYS : s7_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 83.3,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK12,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
RBMON_RBADDR => (others=>'0'))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => '1',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RGBMSTR : rgbdrv_master
generic map (
DWIDTH => DIMCNTL'length)
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL
);
RGB0 : rgbdrv_analog_rbus
generic map (
DWIDTH => DIMCNTL'length,
ACTLOW => '1', -- CmodA7 has active low RGBLED
RB_ADDR => rbaddr_rgb0)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_RGB0,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL,
O_RGBLED => O_RGBLED0_N
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_base
generic map ( -- use default INIT_ (LP: Vccint=0.95)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR1 : rb_sres_or_4
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_RGB0,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
IOB_LED : iob_reg_o_gen
generic map (DWIDTH => O_LED'length)
port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED);
LED(1) <= SER_MONI.txact;
LED(0) <= SER_MONI.rxact;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/bplib/basys3/tb/sys_conf_sim.vhd | 1 | 1728 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_basys3_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-10-01 810 1.0 Initial version (cloned from nexys4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/simlib/simbididly.vhd | 1 | 3782 | -- $Id: simbididly.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: simbididly - sim
-- Description: Bi-directional bus delay for test benches
--
-- Dependencies: -
-- Test bench: tb_simbididly
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-23 793 1.0.1 ensure non-zero DELAY
-- 2016-07-17 789 1.0 Initial version (use separate driver regs now)
-- 2016-07-16 787 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity simbididly is -- test bench bi-directional bus delay
generic (
DELAY : Delay_length; -- transport delay between A and B (>0ns!)
DWIDTH : positive := 16); -- data port width
port (
A : inout slv(DWIDTH-1 downto 0); -- port A
B : inout slv(DWIDTH-1 downto 0) -- port B
);
end entity simbididly;
architecture sim of simbididly is
type state_type is (
s_idle, -- s_idle: both ports high-z
s_a2b, -- s_a2b: A drives, B listens
s_b2a -- s_b2a: B drives, A listens
);
constant all_z : slv(DWIDTH-1 downto 0) := (others=>'Z');
signal R_STATE : state_type := s_idle;
signal R_A : slv(DWIDTH-1 downto 0) := (others=>'Z');
signal R_B : slv(DWIDTH-1 downto 0) := (others=>'Z');
begin
process
variable istate : state_type := s_idle;
begin
-- the delay model can enter into a delta cycle oszillation mode
-- when DELAY is 0 ns. So ensure the delay is non-zero
assert DELAY > 0 ns report "DELAY > 0 ns" severity failure;
while true loop
-- if idle check whether A or B port starts to drive bus
-- Note: both signal R_STATE and variable istate is updated
-- istate is needed to control the driver section below in the
-- same delta cycle based on the most recent state state
istate := R_STATE;
if now > 0 ns then -- to avoid startup problems
if R_STATE = s_idle then
if A /= all_z then
R_STATE <= s_a2b;
istate := s_a2b;
elsif B /= all_z then
R_STATE <= s_b2a;
istate := s_b2a;
end if;
end if;
end if;
case istate is
when s_a2b =>
R_B <= transport A after DELAY;
if A = all_z then R_STATE <= s_idle after DELAY; end if;
when s_b2a =>
R_A <= transport B after DELAY;
if B = all_z then R_STATE <= s_idle after DELAY; end if;
when others => null;
end case;
-- Note: the driver clash check is done by comparing an internal signal
-- with the external signal. If they differ this indicates a clash.
-- Just checking for 'x' gives false alarms when the bus is driven
-- with 'x', which can for example come from a memory model before
-- valid data is available.
if now > 0 ns then -- to avoid startup problems
case istate is
when s_a2b =>
assert B = R_B report "driver clash B port" severity error;
when s_b2a =>
assert A = R_A report "driver clash A port" severity error;
when others => null;
end case;
end if;
wait on A,B;
end loop;
end process;
A <= R_A;
B <= R_B;
end sim;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop1_n4d.vhd | 1 | 3381 | -- $Id: tb_tst_serloop1_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop1_n4d - sim
-- Description: Test bench for sys_tst_serloop1_n4d
--
-- Dependencies: simlib/simclk
-- xlib/sfs_gsim_core
-- sys_tst_serloop1_n4d [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop1_n4d
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.0.1 use sfs_gsim_core
-- 2017-01-04 838 1.0 Initial version (cloned from tb_tst_serloop1_n4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
use work.sys_conf.all;
entity tb_tst_serloop1_n4d is
end tb_tst_serloop1_n4d;
architecture sim of tb_tst_serloop1_n4d is
signal CLK100 : slbit := '0';
signal CLK : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100
);
GEN_CLKSYS : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide)
port map (
CLKIN => CLK100,
CLKFX => CLK,
LOCKED => open
);
UUT : entity work.sys_tst_serloop1_n4d
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => '1',
O_LED => open,
O_RGBLED0 => open,
O_RGBLED1 => open,
O_ANO_N => open,
O_SEG_N => open
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLK,
CLKH => CLK,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => RTS_N,
P0_CTS_N => CTS_N,
P1_RXD => open, -- port 1 unused for n4d !
P1_TXD => '0',
P1_RTS_N => '0',
P1_CTS_N => open,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0)
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
RTS_N <= O_RTS_N after delay_time;
I_CTS_N <= CTS_N after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/w11a/artys7_bram/sys_conf.vhd | 1 | 4773 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_br_artys7 (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.1.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.1 use typ for DL,PC,LP; add dz11,ibtst
-- 2018-09-22 1050 1.0.2 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.0.1 add sys_conf_ibd_kw11p
-- 2018-08-11 1038 1.0 Initial version (derived from _aa7 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_mawidth : positive := 4;
constant sys_conf_memctl_nblock : positive := 16;
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
-- sys_conf_mem_losize is highest 64 byte MMU block number
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1;
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 |
wfjm/w11 | rtl/ibus/ibd_iist.vhd | 1 | 28642 | -- $Id: ibd_iist.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2009-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibd_iist - syn
-- Description: ibus dev(loc): IIST
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 112 510 0 291 s 15.8
-- 2010-10-17 314 12.1 M53d xc3s1000-4 111 504 0 290 s 15.6
-- 2009-06-01 223 10.1.03 K39 xc3s1000-4 111 439 0 256 s 9.8
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 111 449 0 258 s 13.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 0.8.2 don't init N_REGS (vivado fix for fsm inference)
-- 2011-11-18 427 0.8.1 now numeric_std clean
-- 2010-10-17 333 0.8 use ibus V2 interface
-- 2009-06-07 224 0.7 send inverted stc_stp; remove pgc_err; honor msk_im
-- also for dcf_dcf and exc_rte; add iist_mreq and
-- iist_sreq, boot and lock interfaces
-- 2009-06-05 223 0.6 level interrupt, parity logic, exc.ui logic
-- st logic modified (partially tested)
-- 2009-06-01 221 0.5 Initial version (untested, lock&boot missing)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.ibdlib.all;
-- ----------------------------------------------------------------------------
entity ibd_iist is -- ibus dev(loc): IIST
-- fixed address: 177500
generic (
SID : slv2 := "00"); -- self id
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit; -- interrupt acknowledge
IIST_BUS : in iist_bus_type; -- iist bus (input from all iist's)
IIST_OUT : out iist_line_type; -- iist output
IIST_MREQ : out iist_mreq_type; -- iist->cpu requests
IIST_SRES : in iist_sres_type -- cpu->iist responses
);
end ibd_iist;
architecture syn of ibd_iist is
constant ibaddr_iist : slv16 := slv(to_unsigned(8#177500#,16));
constant tdlysnd : natural := 150; -- send delay timer
constant ibaddr_acr : slv1 := "0"; -- acr address offset
constant ibaddr_adr : slv1 := "1"; -- adr address offset
constant acr_ibf_clr : integer := 15; -- clear flag
subtype acr_ibf_sid is integer range 9 downto 8; -- self id
subtype acr_ibf_ac is integer range 3 downto 0; -- ac code
constant ac_pge : slv4 := "0000"; -- 0 program generated enables
constant ac_pgc : slv4 := "0001"; -- 1 program generated control/status
constant ac_ste : slv4 := "0010"; -- 2 sanity timer enables
constant ac_stc : slv4 := "0011"; -- 3 sanity timer control/status
constant ac_msk : slv4 := "0100"; -- 4 input masks
constant ac_pgf : slv4 := "0101"; -- 5 program generated flags
constant ac_stf : slv4 := "0110"; -- 6 sanity timer flags
constant ac_dcf : slv4 := "0111"; -- 7 disconnect flags
constant ac_exc : slv4 := "1000"; -- 10 exceptions
constant ac_mtc : slv4 := "1101"; -- 15 maintenance control
subtype pge_ibf_pbe is integer range 11 downto 8; -- pg boot ena
subtype pge_ibf_pie is integer range 3 downto 0; -- pg int ena
constant pgc_ibf_err : integer := 15; -- error
constant pgc_ibf_grj : integer := 14; -- go reject
constant pgc_ibf_pgrmr : integer := 13; -- pg req refused
constant pgc_ibf_strmr : integer := 12; -- st req refused
constant pgc_ibf_rdy : integer := 11; -- ready flag
subtype pgc_ibf_sid is integer range 9 downto 8; -- self id
constant pgc_ibf_ip : integer := 3; -- int pending
constant pgc_ibf_ie : integer := 2; -- int enable
constant pgc_ibf_ptp : integer := 1; -- pg parity
constant pgc_ibf_go : integer := 0; -- go flag
subtype ste_ibf_sbe is integer range 11 downto 8; -- st boot enable
subtype ste_ibf_sie is integer range 3 downto 0; -- st int enable
subtype stc_ibf_count is integer range 15 downto 8; -- count
constant stc_ibf_tmo : integer := 3; -- timeout
constant stc_ibf_lke : integer := 2; -- lockup enable
constant stc_ibf_stp : integer := 1; -- st parity
constant stc_ibf_enb : integer := 0; -- enable
subtype msk_ibf_bm is integer range 11 downto 8; -- boot mask
subtype msk_ibf_im is integer range 3 downto 0; -- int mask
subtype pgf_ibf_pbf is integer range 11 downto 8; -- boot flags
subtype pgf_ibf_pif is integer range 3 downto 0; -- int flags
subtype stf_ibf_sbf is integer range 11 downto 8; -- boot flags
subtype stf_ibf_sif is integer range 3 downto 0; -- int flags
subtype dcf_ibf_brk is integer range 11 downto 8; -- break flags
subtype dcf_ibf_dcf is integer range 3 downto 0; -- disconnect flags
subtype exc_ibf_ui is integer range 11 downto 8; -- unexpected int
subtype exc_ibf_rte is integer range 3 downto 0; -- transm. error
constant mtc_ibf_mttp : integer := 11; -- maint. type
constant mtc_ibf_mfrm : integer := 10; -- maint. frame err
subtype mtc_ibf_mid is integer range 9 downto 8; -- maint. id
constant mtc_ibf_dsbt : integer := 3; -- disable boot
constant mtc_ibf_enmxd : integer := 2; -- enable maint mux
constant mtc_ibf_enmlp : integer := 1; -- enable maint loop
constant mtc_ibf_dsdrv : integer := 0; -- disable driver
type state_type is (
s_idle, -- idle state
s_clear, -- handle acr clr
s_stsnd, -- handle st transmit
s_pgsnd -- handle pg transmit
);
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
acr_ac : slv4; -- acr: ac
pge_pbe : slv4; -- pge: pg boot ena
pge_pie : slv4; -- pge: pg int ena
pgc_grj : slbit; -- pgc: go reject
pgc_pgrmr : slbit; -- pgc: pg req refused
pgc_strmr : slbit; -- pgc: st req refused
pgc_ie : slbit; -- pgc: int enable
pgc_ptp : slbit; -- pgc: pg parity
ste_sbe : slv4; -- ste: st boot enable
ste_sie : slv4; -- ste: st int enable
stc_count : slv8; -- stc: count
stc_tmo : slbit; -- stc: timeout
stc_lke : slbit; -- stc: lockup enable
stc_stp : slbit; -- stc: st parity
stc_enb : slbit; -- stc: enable
msk_bm : slv4; -- msk: boot mask
msk_im : slv4; -- msk: int mask
pgf_pbf : slv4; -- pgf: boot flags
pgf_pif : slv4; -- pgf: int flags
stf_sbf : slv4; -- stf: boot flags
stf_sif : slv4; -- stf: int flags
dcf_brk : slv4; -- dcf: break flags
dcf_dcf : slv4; -- dcf: disconnect flags
exc_ui : slv4; -- exc: unexpected int
exc_rte : slv4; -- exc: transm. error
mtc_mttp : slbit; -- mtc: maint. type
mtc_mfrm : slbit; -- mtc: maint. frame err
mtc_mid : slv2; -- mtc: maint. id
mtc_dsbt : slbit; -- mtc: disable boot
mtc_enmxd : slbit; -- mtc: enable maint mux
mtc_enmlp : slbit; -- mtc: enable maint loop
mtc_dsdrv : slbit; -- mtc: disable driver
state : state_type; -- state
req_clear : slbit; -- request clear
req_stsnd : slbit; -- request sanity timer transmit
req_pgsnd : slbit; -- request prog. gen. transmit
tcnt256 : slv8; -- usec clock divider for st clock
tcntsnd : slv8; -- timer for transmit delay
req_lock : slbit; -- cpu lock request
req_boot : slbit; -- cpu boot request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
"0000", -- acr_ac
"0000","0000", -- pge_pbe, pge_pie
'0', -- pgc_grj
'0','0', -- pgc_pgrmr, pgc_strmr
'0','0', -- pgc_ie, pgc_ptp
"0000","0000", -- ste_sbe, ste_sie
(others=>'0'), -- stc_count
'0','0', -- stc_tmo, stc_lke
'0','0', -- stc_stp, stc_enb
"0000","0000", -- msk_bm, msk_im
"0000","0000", -- pgf_pbf, pgf_pif
"0000","0000", -- stf_sbf, stf_sif
"0000","0000", -- dcf_brk, dcf_dcf
"0000","0000", -- exc_ui, exc_rte
'0','0', -- mtc_mttp, mtc_mfrm
"00", -- mtc_mid
'0','0', -- mtc_dsbt, mtc_enmxd
'0','0', -- mtc_enmlp, mtc_dsdrv
s_idle, -- state
'0', -- req_clear
'0','0', -- req_stsnd, req_pgsnd
(others=>'0'), -- tcnt256
(others=>'0'), -- tcntsnd
'0','0' -- req_lock, req_boot
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' or -- BRESET is 1 for system and ibus reset
R_REGS.req_clear='1' then
R_REGS <= regs_init; --
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.pgf_pbf <= N_REGS.pgf_pbf; -- don't reset pg boot flags
R_REGS.stf_sbf <= N_REGS.stf_sbf; -- don't reset st boot flags
R_REGS.tcnt256 <= N_REGS.tcnt256; -- don't reset st clock divider
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_USEC, IB_MREQ,
IIST_BUS(0), IIST_BUS(1), IIST_BUS(2), IIST_BUS(3),
IIST_SRES)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable int_or : slbit := '0';
variable tcnt256_end : slbit := '0';
variable tcntsnd_end : slbit := '0';
variable eff_id : slv2 := "00";
variable eff_bus : iist_bus_type := iist_bus_init;
variable par_err : slbit := '0';
variable act_ibit : slbit := '0';
variable act_bbit : slbit := '0';
variable iout : iist_line_type := iist_line_init;
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
int_or := r.pgc_grj or r.pgc_pgrmr or r.pgc_strmr;
for i in r.dcf_dcf'range loop
int_or := int_or or r.dcf_dcf(i) or
r.exc_rte(i) or
r.pgf_pif(i) or
r.stf_sif(i);
end loop; -- i
tcnt256_end := '0';
if CE_USEC='1' and r.stc_enb='1'then -- if st enabled on every usec
n.tcnt256 := slv(unsigned(r.tcnt256) + 1); -- advance 8 bit counter
if unsigned(r.tcnt256) = 255 then -- if wrap
tcnt256_end := '1'; -- signal 256 usec passed
end if;
end if;
tcntsnd_end := '0';
n.tcntsnd := slv(unsigned(r.tcntsnd) + 1); -- advance send timer counter
if unsigned(r.tcntsnd) = tdlysnd-1 then -- if delay time reached
tcntsnd_end := '1'; -- signal end
end if;
eff_id := SID; -- effective self-id, normally SID
if r.mtc_enmxd = '1' then -- if maint. mux enabled
eff_id := r.mtc_mid; -- use maint. id
end if;
eff_bus := IIST_BUS;
par_err := '0';
act_ibit := '0';
act_bbit := '0';
iout := iist_line_init; -- default state of out line
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 2)=ibaddr_iist(12 downto 2) then
n.ibsel := '1';
end if;
-- internal state machine
case r.state is
when s_idle => -- idle state
n.tcntsnd := (others=>'0'); -- keep send delay timer zero
if r.req_stsnd = '1' then -- sanity timer request pending
n.state := s_stsnd;
elsif r.req_pgsnd = '1' then -- prog. gen. request pending
n.state := s_pgsnd;
end if;
when s_clear => -- handle acr clr
ibhold := r.ibsel; -- keep req pending if selected
-- r.req_clear is set when in this state and cause a reset in prog_regs
-- --> n.req_clear := '0';
-- --> n.state := s_idle;
when s_stsnd => -- handle st transmit
if tcntsnd_end = '1' then -- send delay expired
n.req_stsnd := '0'; -- clear st transmit request
iout.req := '1'; -- do transmit
iout.stf := '1'; -- signal type = st
iout.imask := r.ste_sie; -- int enables
iout.bmask := r.ste_sbe; -- boot enables
iout.par := not r.stc_stp; -- send parity (odd incl. stf!)
iout.frm := '0'; -- frame always ok
n.state := s_idle;
end if;
when s_pgsnd => -- handle pg transmit
if tcntsnd_end = '1' then -- send delay expired
n.req_pgsnd := '0'; -- clear pg transmit request
iout.req := '1'; -- do transmit
iout.stf := '0'; -- signal type = pg
iout.imask := r.pge_pie; -- int enables
iout.bmask := r.pge_pbe; -- boot enables
iout.par := r.pgc_ptp; -- send parity
iout.frm := '0'; -- frame always ok
n.state := s_idle;
end if;
when others => null;
end case;
if r.mtc_enmxd = '1' then -- if maintenance mux enabled
iout.stf := r.mtc_mttp; -- force type from mtc_mttp
iout.frm := r.mtc_mfrm; -- force frame from mtc_mfrm
end if;
-- ibus transactions
if r.ibsel = '1' and ibhold='0' then
if IB_MREQ.addr(1 downto 1) = "0" then -- ACR -- access control reg -----
idout(acr_ibf_sid) := SID;
idout(acr_ibf_ac) := r.acr_ac;
if ibw1 = '1' then
if IB_MREQ.din(acr_ibf_clr) = '1' then
n.req_clear := '1';
n.state := s_clear;
end if;
end if;
if ibw0 = '1' then
n.acr_ac := IB_MREQ.din(acr_ibf_ac);
end if;
else -- ADR -- access data reg --------
case r.acr_ac is
when ac_pge => -- PGE -- program gen enables --------
idout(pge_ibf_pbe) := r.pge_pbe;
idout(pge_ibf_pie) := r.pge_pie;
if IB_MREQ.we = '1' then
if r.req_pgsnd = '0' then -- no pg transmit pending
if ibw1 = '1' then
n.pge_pbe := IB_MREQ.din(pge_ibf_pbe);
end if;
if ibw0 = '1' then
n.pge_pie := IB_MREQ.din(pge_ibf_pie);
end if;
else -- if collision with pg transmit
n.pgc_pgrmr := '1'; -- set pge refused flag
end if;
end if;
when ac_pgc => -- PGC -- program gen control/status -
idout(pgc_ibf_err) := r.pgc_grj or r.pgc_pgrmr or r.pgc_strmr;
idout(pgc_ibf_grj) := r.pgc_grj;
idout(pgc_ibf_pgrmr) := r.pgc_pgrmr;
idout(pgc_ibf_strmr) := r.pgc_strmr;
idout(pgc_ibf_rdy) := not r.req_pgsnd;
idout(pgc_ibf_sid) := eff_id;
idout(pgc_ibf_ip) := int_or;
idout(pgc_ibf_ie) := r.pgc_ie;
idout(pgc_ibf_ptp) := r.pgc_ptp;
if ibw1 = '1' then
if IB_MREQ.din(pgc_ibf_err) = '1' then -- '1' written into ERR
n.pgc_grj := '0'; -- clears GRJ
n.pgc_pgrmr := '0'; -- clears PGRMR
n.pgc_strmr := '0'; -- clears STRMR
end if;
end if;
if ibw0 = '1' then
n.pgc_ie := IB_MREQ.din(pgc_ibf_ie);
n.pgc_ptp := IB_MREQ.din(pgc_ibf_ptp);
if IB_MREQ.din(pgc_ibf_go) = '1' then -- GO bit set
if r.req_pgsnd = '0' then -- if ready (no pgsnd pend)
n.req_pgsnd := '1'; -- request pgsnd
else -- if not ready
n.pgc_grj := '1'; -- set go reject flag
end if;
end if;
end if;
when ac_ste => -- STE -- sanity timer enables -------
idout(ste_ibf_sbe) := r.ste_sbe;
idout(ste_ibf_sie) := r.ste_sie;
if IB_MREQ.we = '1' then
if r.req_stsnd = '0' then -- no st transmit pending
if ibw1 = '1' then
n.ste_sbe := IB_MREQ.din(ste_ibf_sbe);
end if;
if ibw0 = '1' then
n.ste_sie := IB_MREQ.din(ste_ibf_sie);
end if;
else -- if collision with st transmit
n.pgc_strmr := '1'; -- set ste refused flag
end if;
end if;
when ac_stc => -- STC -- sanity timer control/status
idout(stc_ibf_count) := r.stc_count;
idout(stc_ibf_tmo) := r.stc_tmo;
idout(stc_ibf_lke) := r.stc_lke;
idout(stc_ibf_stp) := r.stc_stp;
idout(stc_ibf_enb) := r.stc_enb;
if ibw1 = '1' then
n.stc_count := IB_MREQ.din(stc_ibf_count); -- reset st count
n.tcnt256 := (others=>'0'); -- reset usec count
end if;
if ibw0 = '1' then
if IB_MREQ.din(stc_ibf_tmo) = '1' then -- 1 written into TMO
n.stc_tmo := '0';
end if;
n.stc_lke := IB_MREQ.din(stc_ibf_lke);
n.stc_stp := IB_MREQ.din(stc_ibf_stp);
n.stc_enb := IB_MREQ.din(stc_ibf_enb);
end if;
when ac_msk => -- MSK -- input masks ----------------
idout(msk_ibf_bm) := r.msk_bm;
idout(msk_ibf_im) := r.msk_im;
if ibw1 = '1' then
n.msk_bm := IB_MREQ.din(msk_ibf_bm);
end if;
if ibw0 = '1' then
n.msk_im := IB_MREQ.din(msk_ibf_im);
end if;
when ac_pgf => -- PGF -- program generated flags ----
idout(pgf_ibf_pbf) := r.pgf_pbf;
idout(pgf_ibf_pif) := r.pgf_pif;
if ibw1 = '1' then
n.pgf_pbf := r.pgf_pbf and not IB_MREQ.din(pgf_ibf_pbf);
end if;
if ibw0 = '1' then
n.pgf_pif := r.pgf_pif and not IB_MREQ.din(pgf_ibf_pif);
end if;
when ac_stf => -- STF -- sanity timer flags ---------
idout(stf_ibf_sbf) := r.stf_sbf;
idout(stf_ibf_sif) := r.stf_sif;
if ibw1 = '1' then
n.stf_sbf := r.stf_sbf and not IB_MREQ.din(stf_ibf_sbf);
end if;
if ibw0 = '1' then
n.stf_sif := r.stf_sif and not IB_MREQ.din(stf_ibf_sif);
end if;
when ac_dcf => -- DCE -- disconnect flags -----------
idout(dcf_ibf_brk) := r.dcf_brk;
idout(dcf_ibf_dcf) := r.dcf_dcf;
if ibw0 = '1' then
n.dcf_dcf := r.dcf_dcf and not IB_MREQ.din(dcf_ibf_dcf);
end if;
when ac_exc => -- EXC -- exceptions -----------------
idout(exc_ibf_ui) := r.exc_ui;
idout(exc_ibf_rte) := r.exc_rte;
if ibw1 = '1' then
n.exc_ui := r.exc_ui and not IB_MREQ.din(exc_ibf_ui);
end if;
if ibw0 = '1' then
n.exc_rte := r.exc_rte and not IB_MREQ.din(exc_ibf_rte);
end if;
when ac_mtc => -- MTC -- maintenance control --------
idout(mtc_ibf_mttp) := r.mtc_mttp;
idout(mtc_ibf_mfrm) := r.mtc_mfrm;
idout(mtc_ibf_mid) := r.mtc_mid;
idout(mtc_ibf_dsbt) := r.mtc_dsbt;
idout(mtc_ibf_enmxd) := r.mtc_enmxd;
idout(mtc_ibf_enmlp) := r.mtc_enmlp;
idout(mtc_ibf_dsdrv) := r.mtc_dsdrv;
if ibw1 = '1' then
n.mtc_mttp := IB_MREQ.din(mtc_ibf_mttp);
n.mtc_mfrm := IB_MREQ.din(mtc_ibf_mfrm);
n.mtc_mid := IB_MREQ.din(mtc_ibf_mid);
end if;
if ibw0 = '1' then
n.mtc_dsbt := IB_MREQ.din(mtc_ibf_dsbt);
n.mtc_enmxd := IB_MREQ.din(mtc_ibf_enmxd);
n.mtc_enmlp := IB_MREQ.din(mtc_ibf_enmlp);
n.mtc_dsdrv := IB_MREQ.din(mtc_ibf_dsdrv);
end if;
when others => -- access to undefined AC code -------
null;
end case;
if unsigned(r.acr_ac) <= unsigned(ac_exc) then -- if ac 0,..,10
if IB_MREQ.rmw = '0' then -- if not 1st part of rmw
n.acr_ac := slv(unsigned(r.acr_ac) + 1); -- autoincrement
end if;
end if;
end if;
end if;
-- sanity timer
if tcnt256_end = '1' then -- if 256 usec expired (and enabled)
n.stc_count := slv(unsigned(r.stc_count) - 1);
if unsigned(r.stc_count) = 0 then -- if sanity timer expired
n.stc_tmo := '1'; -- set timeout flag
n.req_stsnd := '1'; -- request st transmit
if r.stc_lke = '1' then -- if lockup enabled
n.req_lock := '1'; -- request lockup
end if;
end if;
end if;
-- process iist bus inputs
if r.mtc_enmlp = '1' then -- if mainentance loop
for i in eff_bus'range loop
eff_bus(i) := iout; -- local signal on all input ports
eff_bus(i).dcf := '0'; -- all ports considered connected
end loop; -- i
end if;
for i in eff_bus'range loop
par_err := eff_bus(i).stf xor
eff_bus(i).imask(0) xor eff_bus(i).imask(1) xor
eff_bus(i).imask(2) xor eff_bus(i).imask(3) xor
eff_bus(i).bmask(0) xor eff_bus(i).bmask(1) xor
eff_bus(i).bmask(2) xor eff_bus(i).bmask(3) xor
not eff_bus(i).par;
act_ibit := eff_bus(i).imask(to_integer(unsigned(eff_id)));
act_bbit := eff_bus(i).bmask(to_integer(unsigned(eff_id)));
n.dcf_brk(i) := eff_bus(i).dcf; -- trace dcf state in brk
if eff_bus(i).dcf = '1' then -- if disconnected
if r.msk_im(i) = '0' then -- if not disabled
n.dcf_dcf(i) := '1'; -- set dcf flag
end if;
else -- if connected
if eff_bus(i).req = '1' then -- request received ?
if eff_bus(i).frm='1' or -- frame error seen ?
par_err='1' then -- parity error seen ?
if r.msk_im(i) = '0' then -- if not disabled
n.exc_rte(i) := '1'; -- set rte flag
end if;
else -- here if valid request seen
if act_ibit = '1' then -- interrupt request
if r.msk_im(i) = '1' then -- if disabled
n.exc_ui(i) := '1'; -- set ui flag
else -- if enabled
n.req_lock := '0'; -- release lock
if eff_bus(i).stf = '0' then -- and pg request
n.pgf_pif(i) := '1'; -- set pif flag
else -- and st request
n.stf_sif(i) := '1'; -- set sif flag
end if;
end if;
end if; -- act_ibit='1'
if act_bbit = '1' then -- boot request
if r.msk_bm(i) = '1' then -- if msk disabled
n.exc_ui(i) := '1'; -- set ui flag
else -- if msk enabled
if r.mtc_dsbt = '0' then -- if mtc enabled
n.req_lock := '0'; -- release lock
n.req_boot := '1'; -- request boot
end if;
if eff_bus(i).stf = '0' then -- and pg request
n.pgf_pbf(i) := '1'; -- set pbf flag
else -- and st request
n.stf_sbf(i) := '1'; -- set sbf flag
end if;
end if;
end if; -- act_bbit='1'
end if;
end if;
end if;
end loop;
-- process cpu->iist responses
if IIST_SRES.ack_lock = '1' then
n.req_lock := '0';
end if;
if IIST_SRES.ack_boot = '1' then
n.req_boot := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
EI_REQ <= r.pgc_ie and int_or;
if r.mtc_dsdrv = '1' then -- if driver disconnected
iout.dcf := '1'; -- set dcf flag
iout.req := '0'; -- suppress requests
end if;
IIST_OUT <= iout; -- and finally send it out...
IIST_MREQ.lock <= r.req_lock;
IIST_MREQ.boot <= r.req_boot;
end process proc_next;
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/w11a/nexys4d/tb/sys_conf_sim.vhd | 1 | 4217 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n4d (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.1.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.1 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-02 1101 1.0 Initial version (cloned from _n4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 7; -- 32kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_04900_bad.vhd | 1 | 2910 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-17 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_04900_bad.vhd
-- File Creation date : 2015-04-17
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Use of clock signal: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
entity CNE_04900_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Enable : in std_logic; -- Enable signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_04900_bad;
--CODE
architecture Behavioral of CNE_04900_bad is
signal Gated_Clock : std_logic; -- Gated clock signal
begin
Gated_Clock <= i_Clock and i_Enable;
DFF:DFlipFlop
port map (
i_Clock => Gated_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => open
);
end Behavioral;
--CODE | gpl-3.0 |
wfjm/w11 | rtl/sys_gen/w11a/artys7/tb/sys_conf_sim.vhd | 1 | 4186 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_as7 (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2018.3; ghdl 0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.1.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.1 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-12 1105 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 9; -- vco 900 MHz
constant sys_conf_clksys_outdivide : positive := 12; -- sys 75 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 7; -- 32kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 |
abcsds/Micros | RS232Write/RightShift.vhd | 4 | 1386 | library IEEE;
use IEEE.std_logic_1164.all;
entity RightShft is
port(
RST : in std_logic;
CLK : in std_logic;
CTRL : in std_logic_vector(3 downto 0);
DATAWR : in std_logic_vector(7 downto 0);
Tx : out std_logic
);
end RightShft;
architecture simple of RightShft is
signal Txn, Txp: std_logic;
begin
MUX: process(CTRL,DATAWR)
begin
case CTRL is
when "0000"=> Txn<= '1';-- Hold
when "0001"=> Txn<= '0';-- Start
when "0010"=> Txn<= DATAWR(0);-- DATARD(0)
when "0011"=> Txn<= DATAWR(1);-- DATARD(1)
when "0100"=> Txn<= DATAWR(2);-- DATARD(2)
when "0101"=> Txn<= DATAWR(3);-- DATARD(3)
when "0110"=> Txn<= DATAWR(4);-- DATARD(4)
when "0111"=> Txn<= DATAWR(5);-- DATARD(5)
when "1000"=> Txn<= DATAWR(6);-- DATARD(6)
when "1001"=> Txn<= DATAWR(7);-- DATARD(7)
when "1010"=> Txn<= '1';-- Stop
when others => Txn<= '1';
end case;
end process MUX;
FF: process(RST,CLK)
begin
if(RST='0')then
Txp<= '0';
elsif(CLK'event and CLK='1')then
Txp<= Txn;
end if;
end process FF;
Tx <= Txp;
end simple; | gpl-3.0 |
wfjm/w11 | rtl/ibus/ib_sres_or_mon.vhd | 1 | 3030 | -- $Id: ib_sres_or_mon.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_mon - sim
-- Description: ibus result or monitor
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-28 336 1.0.1 log errors only if now>0ns (drop startup glitches)
-- 2010-10-23 335 1.0 Initial version (derived from rritb_sres_or_mon)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_mon is -- ibus result or monitor
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4
);
end ib_sres_or_mon;
architecture sim of ib_sres_or_mon is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3, IB_SRES_4)
constant dzero : slv16 := (others=>'0');
variable oline : line;
variable nack : integer := 0;
variable nbusy : integer := 0;
variable ndout : integer := 0;
begin
nack := 0;
nbusy := 0;
ndout := 0;
if IB_SRES_1.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_2.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_3.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_4.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_1.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_2.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_3.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_4.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_1.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_2.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_3.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_4.dout /= dzero then ndout := ndout + 1; end if;
if now > 0 ns and (nack>1 or nbusy>1 or ndout>1) then
write(oline, now, right, 12);
if nack > 1 then
write(oline, string'(" #ack="));
write(oline, nack);
end if;
if nbusy > 1 then
write(oline, string'(" #busy="));
write(oline, nbusy);
end if;
if ndout > 1 then
write(oline, string'(" #dout="));
write(oline, ndout);
end if;
write(oline, string'(" FAIL in "));
write(oline, ib_sres_or_mon'path_name);
writeline(output, oline);
end if;
end process proc_comb;
end sim;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/rlink/rlink_core8.vhd | 1 | 5162 | -- $Id: rlink_core8.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_core8 - syn
-- Description: rlink core with 8bit interface (core+b2c/c2b+rlmon+rbmon)
--
-- Dependencies: rlink_core
-- comlib/byte2cdata
-- comlib/cdata2byte
-- rlink_mon_sb [sim only, for 8bit level]
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-12-05 596 14.7 131013 xc6slx16-2 352 492 24 176 s 7.0 ver 4.0
-- 2011-12-09 437 13.1 O40d xc3s1000-4 184 403 0 244 s 9.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-11 666 4.1 add ESCXON,ESCFILL in signals, for cdata2byte
-- 2014-10-12 596 4.0 now rlink v4 iface, 4 bit STAT
-- 2011-12-09 437 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.rblib.all;
use work.rlinklib.all;
entity rlink_core8 is -- rlink core with 8bit interface
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1); -- SB_CNTL for rbmon (-1=none)
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rlink ato time unit clock enable
RESET : in slbit; -- reset
ESCXON : in slbit; -- enable xon/xoff escaping
ESCFILL : in slbit; -- enable fill escaping
RLB_DI : in slv8; -- rlink 8b: data in
RLB_ENA : in slbit; -- rlink 8b: data enable
RLB_BUSY : out slbit; -- rlink 8b: data busy
RLB_DO : out slv8; -- rlink 8b: data out
RLB_VAL : out slbit; -- rlink 8b: data valid
RLB_HOLD : in slbit; -- rlink 8b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4 -- rbus: status flags
);
end entity rlink_core8;
architecture syn of rlink_core8 is
signal RL_DI : slv9 := (others=>'0');
signal RL_ENA : slbit := '0';
signal RL_BUSY : slbit := '0';
signal RL_DO : slv9 := (others=>'0');
signal RL_VAL : slbit := '0';
signal RL_HOLD : slbit := '0';
signal RLB_BUSY_L : slbit := '0';
signal RLB_DO_L : slv8 := (others=>'0');
signal RLB_VAL_L : slbit := '0';
begin
RL : rlink_core
generic map (
BTOWIDTH => BTOWIDTH,
RTAWIDTH => RTAWIDTH,
SYSID => SYSID,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
-- RLB -> RL converter (DI handling) -------------
B2CD : byte2cdata -- byte stream -> 9bit comma,data
port map (
CLK => CLK,
RESET => RESET,
DI => RLB_DI,
ENA => RLB_ENA,
ERR => '0',
BUSY => RLB_BUSY_L,
DO => RL_DI,
VAL => RL_ENA,
HOLD => RL_BUSY
);
-- RL -> RLB converter (DO handling) -------------
CD2B : cdata2byte -- 9bit comma,data -> byte stream
port map (
CLK => CLK,
RESET => RESET,
ESCXON => ESCXON,
ESCFILL => ESCFILL,
DI => RL_DO,
ENA => RL_VAL,
BUSY => RL_HOLD,
DO => RLB_DO_L,
VAL => RLB_VAL_L,
HOLD => RLB_HOLD
);
RLB_BUSY <= RLB_BUSY_L;
RLB_DO <= RLB_DO_L;
RLB_VAL <= RLB_VAL_L;
-- synthesis translate_off
RLBMON: if ENAPIN_RLBMON >= 0 generate
MON : rlink_mon_sb
generic map (
DWIDTH => RLB_DI'length,
ENAPIN => ENAPIN_RLBMON)
port map (
CLK => CLK,
RL_DI => RLB_DI,
RL_ENA => RLB_ENA,
RL_BUSY => RLB_BUSY_L,
RL_DO => RLB_DO_L,
RL_VAL => RLB_VAL_L,
RL_HOLD => RLB_HOLD
);
end generate RLBMON;
-- synthesis translate_on
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/w11a/pdp11.vhd | 1 | 70913 | -- $Id: pdp11.vhd 1321 2022-11-24 15:06:47Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: pdp11
-- Description: Definitions for pdp11 components
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2016.2-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-11-24 1321 1.5.17 add cpustat_type intpend
-- 2022-11-21 1320 1.6.16 rename some rsv->ser and cpustat_type trap_->treq_;
-- remove vm_cntl_type.trap_done; add in_vecysv;
-- 2022-10-25 1309 1.6.15 rename _gpr -> _gr
-- 2022-10-03 1301 1.6.14 add decode_stat_type.is_dstpcmode1
-- 2022-08-13 1279 1.6.13 ssr->mmr rename
-- 2019-06-02 1159 1.6.12 add rbaddr_ constants
-- 2019-03-01 1116 1.6.11 define c_init_rbf_greset
-- 2018-10-07 1054 1.6.10 add DM_STAT_EXP; add DM_STAT_SE.itimer
-- 2018-10-05 1053 1.6.9 drop DM_STAT_SY; add DM_STAT_CA, use in pdp11_cache
-- add DM_STAT_SE.pcload
-- 2018-09-29 1051 1.6.8 add pdp11_dmpcnt; add DM_STAT_SE.(cpbusy,idec)
-- 2017-04-22 884 1.6.7 dm_stat_se: add idle; pdp11_dmcmon: add SNUM generic
-- 2016-12-26 829 1.6.6 BUGFIX: psw init with pri=0, as on real 11/70
-- 2015-11-01 712 1.6.5 define sbcntl_sbf_tmu := 12; use for pdp11_tmu_sb
-- 2015-07-19 702 1.6.4 change DM_STAT_(DP|CO); add DM_STAT_SE
-- 2015-07-10 700 1.6.3 define c_cpurust_hbpt;
-- 2015-07-04 697 1.6.2 add pdp11_dm(hbpt|cmon); change DM_STAT_(SY|VM|CO)
-- 2015-06-26 695 1.6.1 add pdp11_dmscnt (add support)
-- 2015-05-09 677 1.6 start/stop/suspend overhaul; reset overhaul
-- 2015-05-01 672 1.5.5 add pdp11_sys70, sys_hio70
-- 2015-04-30 670 1.5.4 rename pdp11_sys70 -> pdp11_reg70
-- 2015-02-20 649 1.5.3 add pdp11_statleds
-- 2015-02-08 644 1.5.2 add pdp11_bram_memctl
-- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
-- 2014-08-10: 581 1.4.10 add c_cc_f_* field defs for condition code array
-- 2014-07-12 569 1.4.9 dpath_stat_type: merge div_zero+div_ovfl to div_quit
-- dpath_cntl_type: add munit_s_div_sr
-- 2011-11-18 427 1.4.8 now numeric_std clean
-- 2010-12-30 351 1.4.7 rename pdp11_core_rri->pdp11_core_rbus; use rblib
-- 2010-10-23 335 1.4.6 rename RRI_LAM->RB_LAM;
-- 2010-10-16 332 1.4.5 renames of pdp11_du_drv port names
-- 2010-09-18 330 1.4.4 rename (adlm)box->(oalm)unit
-- 2010-06-20 308 1.4.3 add c_ibrb_ibf_ def's
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 add racc, be to cp_addr_type; rm pdp11_ibdr_rri
-- 2010-06-13 305 1.4 add rnum to cp_cntl_type, cprnum to cpustat_type;
-- reassign cp command codes and rename: c_cp_func_...
-- -> c_cpfunc_...; remove cpaddr_(lal|lah|inc) from
-- dpath_cntl_type; add cpdout_we to dpath_cntl_type;
-- reassign rbus adresses and rename: c_rb_addr_...
-- -> c_rbaddr_...; rename rbus fields: c_rb_statf_...
-- -> c_stat_rbf_...
-- 2010-06-12 304 1.3.3 add cpuwait to cp_stat_type and cpustat_type
-- 2010-06-11 303 1.3.2 use IB_MREQ.racc instead of RRI_REQ
-- 2010-05-02 287 1.3.1 rename RP_STAT->RB_STAT
-- 2010-05-01 285 1.3 port to rri V2 interface; drop pdp11_rri_2rp;
-- rename c_rp_addr_* -> c_rb_addr_*
-- 2010-03-21 270 1.2.6 add pdp11_du_drv
-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
-- 2009-05-10 214 1.2.4 add ENA (trace enable) for _tmu; add _pdp11_tmu_sb
-- 2009-05-09 213 1.2.3 BUGFIX: default for inst_compl now '0'
-- 2008-12-14 177 1.2.2 add gpr_* fields to DM_STAT_DP
-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc;
-- 2008-08-22 161 1.2 move slvnn_m subtypes to slvtypes;
-- move (and rename) intbus defs to iblib package;
-- move intbus devices to ibdlib package;
-- rename ubf_ --> ibf_;
-- 2008-05-09 144 1.1.17 use EI_ACK with _kw11l, _dl11
-- 2008-05-03 143 1.1.16 rename _cpursta->_cpurust
-- 2008-04-27 140 1.1.15 add c_cpursta_xxx defs; cpufail->cpursta in cp_stat
-- 2008-04-25 138 1.1.14 add BRESET port to _mmu, _vmbox, use in _irq
-- 2008-04-19 137 1.1.13 add _tmu,_sys70 entity, dm_stat_** types and ports
-- 2008-04-18 136 1.1.12 ibdr_sdreg: use RESET; ibdr_minisys: add RESET
-- 2008-03-02 121 1.1.11 remove snoopers; add waitsusp in cpustat_type
-- 2008-02-24 119 1.1.10 add lah,rps,wps commands, cp_addr_type.
-- _vmbox,_mmu interface changed
-- 2008-02-17 117 1.1.9 add em_(mreq|sres)_type, pdp11_cache, pdp11_bram
-- 2008-01-27 115 1.1.8 add pdp11_ubmap, pdp11_mem70
-- 2008-01-26 114 1.1.7 add c_rp_addr_ibr(b) defs (for ibr addresses)
-- 2008-01-20 113 1.1.6 _core_rri: use RRI_LAM; _minisys: RRI_LAM vector
-- 2008-01-20 112 1.1.5 added ibdr_minisys; _ibdr_rri
-- 2008-01-06 111 1.1.4 rename ibdr_kw11l->ibd_kw11l; add ibdr_(dl11|rk11)
-- mod pdp11_intmap;
-- 2008-01-05 110 1.1.3 delete _mmu_regfile; rename _mmu_regs->_mmu_sadr
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- add ibdr_kw11l.
-- 2008-01-01 109 1.1.2 _vmbox w/ IB_SRES_(CPU|EXT); remove vm_regs_type
-- 2007-12-30 108 1.1.1 add ibdr_sdreg, ubf_byte[01]
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-08-16 74 1.0.6 add AP_LAM interface to pdp11_core_rri
-- 2007-08-12 73 1.0.5 add c_rp_addr_xxx and c_rp_statf_xxx def's
-- 2007-08-10 72 1.0.4 added c_cp_func_xxx constant def's for commands
-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.rblib.all;
package pdp11 is
-- default rbus base addresses and offsets
constant rbaddr_cpu0_core : slv16 := x"0000"; -- cpu0 core base
constant rbaddr_cpu0_ibus : slv16 := x"4000"; -- cpu0 ibus window base
constant rbaddr_dmscnt_off : slv16 := x"0040"; -- dmscnt offset
constant rbaddr_dmcmon_off : slv16 := x"0048"; -- dmcmon offset
constant rbaddr_dmhbpt_off : slv16 := x"0050"; -- dmhbpt offset
constant rbaddr_dmpcnt_off : slv16 := x"0060"; -- dmpcnt offset
type psw_type is record -- processor status
cmode : slv2; -- current mode
pmode : slv2; -- previous mode
rset : slbit; -- register set
pri : slv3; -- processor priority
tflag : slbit; -- trace flag
cc : slv4; -- condition codes (NZVC).
end record psw_type;
constant c_cc_f_n: integer := 3; -- condition code: n
constant c_cc_f_z: integer := 2; -- condition code: z
constant c_cc_f_v: integer := 1; -- condition code: v
constant c_cc_f_c: integer := 0; -- condition code: c
constant psw_init : psw_type := (
"00","00", -- cmode, pmode (=kernel)
'0',"000",'0', -- rset, pri (=0), tflag
"0000" -- cc NZVC=0
);
constant c_psw_kmode : slv2 := "00"; -- processor mode: kernel
constant c_psw_smode : slv2 := "01"; -- processor mode: supervisor
constant c_psw_umode : slv2 := "11"; -- processor mode: user
subtype psw_ibf_cmode is integer range 15 downto 14;
subtype psw_ibf_pmode is integer range 13 downto 12;
constant psw_ibf_rset: integer := 11;
subtype psw_ibf_pri is integer range 7 downto 5;
constant psw_ibf_tflag: integer := 4;
subtype psw_ibf_cc is integer range 3 downto 0;
type parpdr_type is record -- combined PAR/PDR MMU status
paf : slv16; -- page address field
plf : slv7; -- page length field
ed : slbit; -- expansion direction
acf : slv3; -- access control field
end record parpdr_type;
constant parpdr_init : parpdr_type := (
(others=>'0'), -- paf
"0000000",'0',"000" -- plf, ed, acf
);
type dpath_cntl_type is record -- data path control
gr_asrc : slv3; -- src register address
gr_adst : slv3; -- dst register address
gr_mode : slv2; -- psw mode for gr access
gr_rset : slbit; -- register set
gr_we : slbit; -- gr write enable
gr_bytop : slbit; -- gr high byte enable
gr_pcinc : slbit; -- pc increment enable
psr_ccwe : slbit; -- enable update cc
psr_we: slbit; -- write enable psw (from DIN)
psr_func : slv3; -- write function psw (from DIN)
dsrc_sel : slbit; -- src data register source select
dsrc_we : slbit; -- src data register write enable
ddst_sel : slbit; -- dst data register source select
ddst_we : slbit; -- dst data register write enable
dtmp_sel : slv2; -- tmp data register source select
dtmp_we : slbit; -- tmp data register write enable
ounit_asel : slv2; -- ounit a port selector
ounit_azero : slbit; -- ounit a port force zero
ounit_const : slv9; -- ounit b port const
ounit_bsel : slv2; -- ounit b port selector
ounit_opsub : slbit; -- ounit operation
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
aunit_bytop : slbit; -- aunit byte operation
lunit_func : slv4; -- lunit function
lunit_bytop : slbit; -- lunit byte operation
munit_func : slv2; -- munit function
munit_s_div : slbit; -- munit s_opg_div state
munit_s_div_cn : slbit; -- munit s_opg_div_cn state
munit_s_div_cr : slbit; -- munit s_opg_div_cr state
munit_s_div_sr : slbit; -- munit s_opg_div_sr state
munit_s_ash : slbit; -- munit s_opg_ash state
munit_s_ash_cn : slbit; -- munit s_opg_ash_cn state
munit_s_ashc : slbit; -- munit s_opg_ashc state
munit_s_ashc_cn : slbit; -- munit s_opg_ashc_cn state
ireg_we : slbit; -- ireg register write enable
cres_sel : slv3; -- result bus (cres) select
dres_sel : slv3; -- result bus (dres) select
vmaddr_sel : slv2; -- virtual address select
cpdout_we : slbit; -- capture dres for cpdout
end record dpath_cntl_type;
constant dpath_cntl_init : dpath_cntl_type := (
"000","000","00",'0','0','0','0', -- gr
'0','0',"000", -- psr
'0','0','0','0',"00",'0', -- dsrc,..,dtmp
"00",'0',"000000000","00",'0', -- ounit
"00","00","00",'0',"000",'0', -- aunit
"0000",'0', -- lunit
"00",'0','0','0','0','0','0','0','0',-- munit
'0',"000","000","00",'0' -- rest
);
constant c_dpath_dsrc_src : slbit := '0'; -- DSRC = R(SRC)
constant c_dpath_dsrc_res : slbit := '1'; -- DSRC = DRES
constant c_dpath_ddst_dst : slbit := '0'; -- DDST = R(DST)
constant c_dpath_ddst_res : slbit := '1'; -- DDST = DRES
constant c_dpath_dtmp_dsrc : slv2 := "00"; -- DTMP = DSRC
constant c_dpath_dtmp_psw : slv2 := "01"; -- DTMP = PSW
constant c_dpath_dtmp_dres : slv2 := "10"; -- DTMP = DRES
constant c_dpath_dtmp_drese : slv2 := "11"; -- DTMP = DRESE
constant c_dpath_res_ounit : slv3 := "000"; -- D/CRES = OUNIT
constant c_dpath_res_aunit : slv3 := "001"; -- D/CRES = AUNIT
constant c_dpath_res_lunit : slv3 := "010"; -- D/CRES = LUNIT
constant c_dpath_res_munit : slv3 := "011"; -- D/CRES = MUNIT
constant c_dpath_res_vmdout : slv3 := "100"; -- D/CRES = VMDOUT
constant c_dpath_res_fpdout : slv3 := "101"; -- D/CRES = FPDOUT
constant c_dpath_res_ireg : slv3 := "110"; -- D/CRES = IREG
constant c_dpath_res_cpdin : slv3 := "111"; -- D/CRES = CPDIN
constant c_dpath_vmaddr_dsrc : slv2 := "00"; -- VMADDR = DSRC
constant c_dpath_vmaddr_ddst : slv2 := "01"; -- VMADDR = DDST
constant c_dpath_vmaddr_pc : slv2 := "10"; -- VMADDR = PC
constant c_dpath_vmaddr_dtmp : slv2 := "11"; -- VMADDR = DTMP
type dpath_stat_type is record -- data path status
ccout_z : slbit; -- current effective Z cc flag
shc_tc : slbit; -- last shc cycle (shc==0)
div_cr : slbit; -- division: remainder correction needed
div_cq : slbit; -- division: quotient correction needed
div_quit : slbit; -- division: abort (0/ or /0 or V=1)
end record dpath_stat_type;
constant dpath_stat_init : dpath_stat_type := (others=>'0');
type decode_stat_type is record -- decode status
is_dstmode0 : slbit; -- dest. is register mode
is_srcpc : slbit; -- source is pc
is_srcpcmode1 : slbit; -- source is pc and mode=1
is_dstpc : slbit; -- dest. is pc
is_dstpcmode1 : slbit; -- dest. is pc and mode=1
is_dstw_reg : slbit; -- dest. register to be written
is_dstw_pc : slbit; -- pc register to be written
is_rmwop : slbit; -- read-modify-write operation
is_bytop : slbit; -- byte operation
is_res : slbit; -- reserved operation code
op_rtt : slbit; -- RTT instruction
op_mov : slbit; -- MOV instruction
trap_vec : slv3; -- trap vector addr bits 4:2
force_srcsp : slbit; -- force src register to be sp
updt_dstadsrc : slbit; -- update dsrc in dsta flow
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
lunit_func : slv4; -- lunit function
munit_func : slv2; -- munit function
res_sel : slv3; -- result bus (cres/dres) select
fork_op : slv4; -- op fork after idecode state
fork_srcr : slv2; -- src-read fork after idecode state
fork_dstr : slv2; -- dst-read fork after src read state
fork_dsta : slv2; -- dst-addr fork after idecode state
fork_opg : slv4; -- opg fork
fork_opa : slv3; -- opa fork
do_fork_op : slbit; -- execute fork_op
do_fork_srcr : slbit; -- execute fork_srcr
do_fork_dstr : slbit; -- execute fork_dstr
do_fork_dsta : slbit; -- execute fork_dsta
do_fork_opg : slbit; -- execute fork_opg
do_pref_dec : slbit; -- can do prefetch at decode phase
end record decode_stat_type;
constant decode_stat_init : decode_stat_type := (
'0','0','0','0','0','0','0','0','0','0', -- is_
'0','0',"000",'0','0', -- op_, trap_, force_, updt_
"00","00","00",'0',"000", -- aunit_
"0000","00","000", -- lunit_, munit_, res_
"0000","00","00","00","0000","000", -- fork_
'0','0','0','0','0', -- do_fork_
'0' -- do_pref_
);
constant c_fork_op_halt : slv4 := "0000";
constant c_fork_op_wait : slv4 := "0001";
constant c_fork_op_rtti : slv4 := "0010";
constant c_fork_op_trap : slv4 := "0011";
constant c_fork_op_reset: slv4 := "0100";
constant c_fork_op_rts : slv4 := "0101";
constant c_fork_op_spl : slv4 := "0110";
constant c_fork_op_mcc : slv4 := "0111";
constant c_fork_op_br : slv4 := "1000";
constant c_fork_op_mark : slv4 := "1001";
constant c_fork_op_sob : slv4 := "1010";
constant c_fork_op_mtp : slv4 := "1011";
constant c_fork_srcr_def : slv2:= "00";
constant c_fork_srcr_inc : slv2:= "01";
constant c_fork_srcr_dec : slv2:= "10";
constant c_fork_srcr_ind : slv2:= "11";
constant c_fork_dstr_def : slv2:= "00";
constant c_fork_dstr_inc : slv2:= "01";
constant c_fork_dstr_dec : slv2:= "10";
constant c_fork_dstr_ind : slv2:= "11";
constant c_fork_dsta_def : slv2:= "00";
constant c_fork_dsta_inc : slv2:= "01";
constant c_fork_dsta_dec : slv2:= "10";
constant c_fork_dsta_ind : slv2:= "11";
constant c_fork_opg_gen : slv4 := "0000";
constant c_fork_opg_wdef : slv4 := "0001";
constant c_fork_opg_winc : slv4 := "0010";
constant c_fork_opg_wdec : slv4 := "0011";
constant c_fork_opg_wind : slv4 := "0100";
constant c_fork_opg_mul : slv4 := "0101";
constant c_fork_opg_div : slv4 := "0110";
constant c_fork_opg_ash : slv4 := "0111";
constant c_fork_opg_ashc : slv4 := "1000";
constant c_fork_opa_jsr : slv3 := "000";
constant c_fork_opa_jmp : slv3 := "001";
constant c_fork_opa_mtp : slv3 := "010";
constant c_fork_opa_mfp_reg : slv3 := "011";
constant c_fork_opa_mfp_mem : slv3 := "100";
-- Note: MSB=0 are 'normal' states, MSB=1 are fatal errors
constant c_cpurust_init : slv4 := "0000"; -- cpu in init state
constant c_cpurust_halt : slv4 := "0001"; -- cpu executed HALT
constant c_cpurust_reset : slv4 := "0010"; -- cpu was reset
constant c_cpurust_stop : slv4 := "0011"; -- cpu was stopped
constant c_cpurust_step : slv4 := "0100"; -- cpu was stepped
constant c_cpurust_susp : slv4 := "0101"; -- cpu was suspended
constant c_cpurust_hbpt : slv4 := "0110"; -- cpu had hardware bpt
constant c_cpurust_runs : slv4 := "0111"; -- cpu running
constant c_cpurust_vecfet : slv4 := "1000"; -- vector fetch error halt
constant c_cpurust_recser : slv4 := "1001"; -- recursive stack error halt
constant c_cpurust_sfail : slv4 := "1100"; -- sequencer failure
constant c_cpurust_vfail : slv4 := "1101"; -- vmbox failure
type cpustat_type is record -- CPU status
cmdbusy : slbit; -- command busy
cmdack : slbit; -- command acknowledge
cmderr : slbit; -- command error
cmdmerr : slbit; -- command memory access error
cpugo : slbit; -- CPU go state
cpustep : slbit; -- CPU step flag
cpususp : slbit; -- CPU susp flag
cpuwait : slbit; -- CPU wait flag
cpurust : slv4; -- CPU run status
suspint : slbit; -- internal suspend flag
suspext : slbit; -- external suspend flag
cpfunc : slv5; -- current control port function
cprnum : slv3; -- current control port register number
waitsusp : slbit; -- WAIT instruction suspended
itimer : slbit; -- ITIMER pulse
creset : slbit; -- CRESET pulse
breset : slbit; -- BRESET pulse
intack : slbit; -- INT_ACK pulse
intpend : slbit; -- interrupt pending
intvect : slv9_2; -- current interrupt vector
treq_mmu : slbit; -- mmu trap requested
treq_ysv : slbit; -- ysv trap requested
prefdone : slbit; -- prefetch done
do_grwe : slbit; -- pending gr_we
in_vecser : slbit; -- in fatal stack error vector flow
in_vecysv : slbit; -- in ysv trap flow
end record cpustat_type;
constant cpustat_init : cpustat_type := (
'0','0','0','0', -- cmdbusy,cmdack,cmderr,cmdmerr
'0','0','0','0', -- cpugo,cpustep,cpususp,cpuwait
c_cpurust_init, -- cpurust
'0','0', -- suspint,suspext
"00000","000", -- cpfunc, cprnum
'0', -- waitsusp
'0','0','0','0','0', -- itimer,creset,breset,intack,intpend
(others=>'0'), -- intvect
'0','0','0', -- treq_(mmu|ysv), prefdone
'0','0','0' -- do_grwe, in_vec(ser|ysv)
);
type cpuerr_type is record -- CPU error register
illhlt : slbit; -- illegal halt (in non-kernel mode)
adderr : slbit; -- address error (odd, jmp/jsr reg)
nxm : slbit; -- non-existent memory
iobto : slbit; -- I/O bus timeout (non-exist UB)
ysv : slbit; -- yellow stack violation
rsv : slbit; -- red stack violation
end record cpuerr_type;
constant cpuerr_init : cpuerr_type := (others=>'0');
type vm_cntl_type is record -- virt memory control port
req : slbit; -- request
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access
bytop : slbit; -- byte operation
dspace : slbit; -- dspace operation
kstack : slbit; -- access through kernel stack
vecser : slbit; -- in fatal stack error vector flow
mode : slv2; -- mode
end record vm_cntl_type;
constant vm_cntl_init : vm_cntl_type := (
'0','0','0','0', -- req, wacc, macc,cacc
'0','0','0', -- bytop, dspace, kstack
'0',"00" -- vecser, mode
);
type vm_stat_type is record -- virt memory status port
ack : slbit; -- acknowledge
err : slbit; -- error (see err_xxx for reason)
fail : slbit; -- failure (machine check)
err_odd : slbit; -- abort: odd address error
err_mmu : slbit; -- abort: mmu reject
err_nxm : slbit; -- abort: non-existing memory
err_iobto : slbit; -- abort: non-existing I/O resource
err_rsv : slbit; -- abort: red stack violation
trap_ysv : slbit; -- trap: yellow stack violation
trap_mmu : slbit; -- trap: mmu trap
end record vm_stat_type;
constant vm_stat_init : vm_stat_type := (others=>'0');
type em_mreq_type is record -- external memory - master request
req : slbit; -- request
we : slbit; -- write enable
be : slv2; -- byte enables
cancel : slbit; -- cancel request
addr : slv22_1; -- address
din : slv16; -- data in (input to memory)
end record em_mreq_type;
constant em_mreq_init : em_mreq_type := (
'0','0',"00",'0', -- req, we, be, cancel
(others=>'0'),(others=>'0') -- addr, din
);
type em_sres_type is record -- external memory - slave response
ack_r : slbit; -- acknowledge read
ack_w : slbit; -- acknowledge write
dout : slv16; -- data out (output from memory)
end record em_sres_type;
constant em_sres_init : em_sres_type := (
'0','0', -- ack_r, ack_w
(others=>'0') -- dout
);
type mmu_cntl_type is record -- mmu control port
req : slbit; -- translate request
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access (bypass mmu)
dspace : slbit; -- dspace access
mode : slv2; -- processor mode
trap_done : slbit; -- mmu trap taken (set mmr0 bit)
end record mmu_cntl_type;
constant mmu_cntl_init : mmu_cntl_type := (
'0','0','0','0', -- req, wacc, macc, cacc
'0',"00",'0' -- dspace, mode, trap_done
);
type mmu_stat_type is record -- mmu status port
vaok : slbit; -- virtual address valid
trap : slbit; -- mmu trap request
ena_mmu : slbit; -- mmu enable (mmr0 bit 0)
ena_22bit : slbit; -- mmu in 22 bit mode (mmr3 bit 4)
ena_ubmap : slbit; -- ubmap enable (mmr3 bit 5)
end record mmu_stat_type;
constant mmu_stat_init : mmu_stat_type := (others=>'0');
type mmu_moni_type is record -- mmu monitor port
istart : slbit; -- instruction start
idone : slbit; -- instruction done
pc : slv16; -- PC of new instruction
regmod : slbit; -- register modified
regnum : slv3; -- register number
delta : slv4; -- register offset
isdec : slbit; -- offset to be subtracted
trace_prev : slbit; -- use mmr12 trace state of prev. state
end record mmu_moni_type;
constant mmu_moni_init : mmu_moni_type := (
'0','0',(others=>'0'), -- istart, idone, pc
'0',"000","0000", -- regmod, regnum, delta
'0','0' -- isdec, trace_prev
);
type mmu_mmr0_type is record -- MMU mmr0
abo_nonres : slbit; -- abort non resident
abo_length : slbit; -- abort page length
abo_rdonly : slbit; -- abort read-only
trap_mmu : slbit; -- trap management
ena_trap : slbit; -- enable traps
inst_compl : slbit; -- instruction complete
page_mode : slv2; -- page mode
dspace : slbit; -- address space (D=1, I=0)
page_num : slv3; -- page number
ena_mmu : slbit; -- enable memory management
trace_prev : slbit; -- mmr12 trace status in prev. state
end record mmu_mmr0_type;
constant mmu_mmr0_init : mmu_mmr0_type := (
inst_compl=>'0', page_mode=>"00", page_num=>"000",
others=>'0'
);
type mmu_mmr1_type is record -- MMU mmr1
rb_delta : slv5; -- RB: amount change
rb_num : slv3; -- RB: register number
ra_delta : slv5; -- RA: amount change
ra_num : slv3; -- RA: register number
end record mmu_mmr1_type;
constant mmu_mmr1_init : mmu_mmr1_type := (
"00000","000", -- rb_...
"00000","000" -- ra_...
);
type mmu_mmr3_type is record -- MMU mmr3
ena_ubmap : slbit; -- enable unibus mapping
ena_22bit : slbit; -- enable 22 bit mapping
dspace_km : slbit; -- enable dspace kernel
dspace_sm : slbit; -- enable dspace supervisor
dspace_um : slbit; -- enable dspace user
end record mmu_mmr3_type;
constant mmu_mmr3_init : mmu_mmr3_type := (others=>'0');
-- control port definitions --------------------------------------------------
type cp_cntl_type is record -- control port control
req : slbit; -- request
func : slv5; -- function
rnum : slv3; -- register number
end record cp_cntl_type;
constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation
constant c_cpfunc_start : slv5 := "00001"; -- sta : cpu start
constant c_cpfunc_stop : slv5 := "00010"; -- sto : cpu stop
constant c_cpfunc_step : slv5 := "00011"; -- cont : cpu step
constant c_cpfunc_creset : slv5 := "00100"; -- step : cpu cpu reset
constant c_cpfunc_breset : slv5 := "00101"; -- rst : cpu bus reset
constant c_cpfunc_suspend : slv5 := "00110"; -- rst : cpu suspend
constant c_cpfunc_resume : slv5 := "00111"; -- rst : cpu resume
constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register
constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register
constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw
constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw
constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory
constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory
constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000");
type cp_stat_type is record -- control port status
cmdbusy : slbit; -- command busy
cmdack : slbit; -- command acknowledge
cmderr : slbit; -- command error
cmdmerr : slbit; -- command memory access error
cpugo : slbit; -- CPU go state
cpustep : slbit; -- CPU step flag
cpuwait : slbit; -- CPU wait flag
cpususp : slbit; -- CPU susp flag
cpurust : slv4; -- CPU run status
suspint : slbit; -- internal suspend
suspext : slbit; -- external suspend
end record cp_stat_type;
constant cp_stat_init : cp_stat_type := (
'0','0','0','0', -- cmd...
'0','0','0','0', -- cpu...
(others=>'0'), -- cpurust
'0','0' -- susp...
);
type cp_addr_type is record -- control port address
addr : slv22_1; -- address
racc : slbit; -- ibus remote access
be : slv2; -- byte enables
ena_22bit : slbit; -- enable 22 bit mode
ena_ubmap : slbit; -- enable unibus mapper
end record cp_addr_type;
constant cp_addr_init : cp_addr_type := (
(others=>'0'), -- addr
'0',"00", -- racc, be
'0','0' -- ena_...
);
-- debug and monitoring port definitions -------------------------------------
type dm_stat_se_type is record -- debug and monitor status - sequencer
idle : slbit; -- sequencer ideling (for pdp11_dcmon)
cpbusy : slbit; -- in cp states
istart : slbit; -- instruction start
idec : slbit; -- instruction decode (for ibd_kw11p)
idone : slbit; -- instruction done
itimer : slbit; -- instruction timer (for ibdr_rhrp)
pcload : slbit; -- PC loaded (flow change)
vfetch : slbit; -- vector fetch
snum : slv8; -- current state number
end record dm_stat_se_type;
constant dm_stat_se_init : dm_stat_se_type := (
'0','0', -- idle,cpbusy
'0','0','0','0', -- istart,idec,idone,itimer
'0','0', -- pcload,vfetch
(others=>'0') -- snum
);
constant c_snum_f_con: integer := 0; -- control state flag
constant c_snum_f_ins: integer := 1; -- instruction state flag
constant c_snum_f_vec: integer := 2; -- vector state flag
constant c_snum_f_err: integer := 3; -- error state flag
constant c_snum_f_vmw: integer := 7; -- vm wait flag
type dm_stat_dp_type is record -- debug and monitor status - dpath
pc : slv16; -- pc
psw : psw_type; -- psw
psr_we: slbit; -- psr_we
ireg : slv16; -- ireg
ireg_we : slbit; -- ireg we
dsrc : slv16; -- dsrc register
dsrc_we: slbit; -- dsrc we
ddst : slv16; -- ddst register
ddst_we : slbit; -- ddst we
dtmp : slv16; -- dtmp register
dtmp_we : slbit; -- dtmp we
dres : slv16; -- dres bus
cpdout_we : slbit; -- cpdout we
gr_adst : slv3; -- gr dst regsiter
gr_mode : slv2; -- gr mode
gr_bytop : slbit; -- gr bytop
gr_we : slbit; -- gr we
end record dm_stat_dp_type;
constant dm_stat_dp_init : dm_stat_dp_type := (
(others=>'0'), -- pc
psw_init,'0', -- psw,psr_we
(others=>'0'),'0', -- ireg,ireg_we
(others=>'0'),'0', -- dsrc,dsrc_we
(others=>'0'),'0', -- ddst,ddst_we
(others=>'0'),'0', -- dtmp,dtmp_we
(others=>'0'), -- dres
'0', -- cpdout_we
(others=>'0'),(others=>'0'), -- gr_adst, gr_mode
'0','0' -- gr_bytop, gr_we
);
type dm_stat_vm_type is record -- debug and monitor status - vmbox
vmcntl : vm_cntl_type; -- vmbox: control
vmaddr : slv16; -- vmbox: address
vmdin : slv16; -- vmbox: data in
vmstat : vm_stat_type; -- vmbox: status
vmdout : slv16; -- vmbox: data out
ibmreq : ib_mreq_type; -- ibus: request
ibsres : ib_sres_type; -- ibus: response
emmreq : em_mreq_type; -- external memory: request
emsres : em_sres_type; -- external memory: response
end record dm_stat_vm_type;
constant dm_stat_vm_init : dm_stat_vm_type := (
vm_cntl_init, -- vmcntl
(others=>'0'), -- vmaddr
(others=>'0'), -- vmdin
vm_stat_init, -- vmstat
(others=>'0'), -- vmdout
ib_mreq_init, -- ibmreq
ib_sres_init, -- ibsres
em_mreq_init, -- emmreq
em_sres_init -- emsres
);
type dm_stat_co_type is record -- debug and monitor status - core
cpugo : slbit; -- cpugo state flag
cpustep : slbit; -- cpustep state flag
cpususp : slbit; -- cpususp state flag
suspint : slbit; -- suspint state flag
suspext : slbit; -- suspext state flag
end record dm_stat_co_type;
constant dm_stat_co_init : dm_stat_co_type := (
'0','0','0', -- cpu...
'0','0' -- susp...
);
type dm_stat_ca_type is record -- debug and monitor status - cache
rd : slbit; -- read request
wr : slbit; -- write request
rdhit : slbit; -- read hit
wrhit : slbit; -- write hit
rdmem : slbit; -- read memory
wrmem : slbit; -- write memory
rdwait : slbit; -- read wait
wrwait : slbit; -- write wait
end record dm_stat_ca_type;
constant dm_stat_ca_init : dm_stat_ca_type := (
'0','0','0','0', -- rd,wr,rdhit,wrhit
'0','0','0','0' -- rdmem,wrmem,rdwait,wrwait
);
type dm_stat_exp_type is record -- debug and monitor - sys70 export
dp_pc : slv16; -- DM_STAT_DP: pc
dp_psw : psw_type; -- DM_STAT_DP: psw
dp_dsrc : slv16; -- DM_STAT_DP: dsrc register
se_idec : slbit; -- DM_STAT_SE: instruction decode
se_itimer : slbit; -- DM_STAT_SE: instruction timer
end record dm_stat_exp_type;
constant dm_stat_exp_init : dm_stat_exp_type := (
(others=>'0'), -- dp_pc
psw_init, -- dp_psw
(others=>'0'), -- dp_dsrc
'0','0' -- se_idec,se_itimer
);
-- rbus interface definitions ------------------------------------------------
constant c_rbaddr_conf : slv5 := "00000"; -- R/W configuration reg
constant c_rbaddr_cntl : slv5 := "00001"; -- -/F control reg
constant c_rbaddr_stat : slv5 := "00010"; -- R/- status reg
constant c_rbaddr_psw : slv5 := "00011"; -- R/W psw access
constant c_rbaddr_al : slv5 := "00100"; -- R/W address low reg
constant c_rbaddr_ah : slv5 := "00101"; -- R/W address high reg
constant c_rbaddr_mem : slv5 := "00110"; -- R/W memory access
constant c_rbaddr_memi : slv5 := "00111"; -- R/W memory access; inc addr
constant c_rbaddr_r0 : slv5 := "01000"; -- R/W gr 0
constant c_rbaddr_r1 : slv5 := "01001"; -- R/W gr 1
constant c_rbaddr_r2 : slv5 := "01010"; -- R/W gr 2
constant c_rbaddr_r3 : slv5 := "01011"; -- R/W gr 3
constant c_rbaddr_r4 : slv5 := "01100"; -- R/W gr 4
constant c_rbaddr_r5 : slv5 := "01101"; -- R/W gr 5
constant c_rbaddr_sp : slv5 := "01110"; -- R/W gr 6 (sp)
constant c_rbaddr_pc : slv5 := "01111"; -- R/W gr 7 (pc)
constant c_rbaddr_membe: slv5 := "10000"; -- R/W memory write byte enables
constant c_init_rbf_greset: integer := 0;
subtype c_al_rbf_addr is integer range 15 downto 1; -- al: address
constant c_ah_rbf_ena_ubmap: integer := 7; -- ah: ubmap
constant c_ah_rbf_ena_22bit: integer := 6; -- ah: 22bit
subtype c_ah_rbf_addr is integer range 5 downto 0; -- ah: address
constant c_stat_rbf_suspext: integer := 9; -- stat field: suspext
constant c_stat_rbf_suspint: integer := 8; -- stat field: suspint
subtype c_stat_rbf_cpurust is integer range 7 downto 4; -- cpurust
constant c_stat_rbf_cpususp: integer := 3; -- stat field: cpususp
constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo
constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr
constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr
subtype c_membe_rbf_be is integer range 1 downto 0; -- membe: be's
constant c_membe_rbf_stick: integer := 2; -- membe: sticky flag
-- -------------------------------------
component pdp11_gr is -- general registers
port (
CLK : in slbit; -- clock
DIN : in slv16; -- input data
ASRC : in slv3; -- source register number
ADST : in slv3; -- destination register number
MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
RSET : in slbit; -- register set
WE : in slbit; -- write enable
BYTOP : in slbit; -- byte operation (write low byte only)
PCINC : in slbit; -- increment PC
DSRC : out slv16; -- source register data
DDST : out slv16; -- destination register data
PC : out slv16 -- current PC value
);
end component;
constant c_gr_r5 : slv3 := "101"; -- register number of r5
constant c_gr_sp : slv3 := "110"; -- register number of SP
constant c_gr_pc : slv3 := "111"; -- register number of PC
component pdp11_psr is -- processor status word register
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
DIN : in slv16; -- input data
CCIN : in slv4; -- cc input
CCWE : in slbit; -- enable update cc
WE : in slbit; -- write enable (from DIN)
FUNC : in slv3; -- write function (from DIN)
PSW : out psw_type; -- current psw
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
constant c_psr_func_wspl : slv3 := "000"; -- SPL mode: set pri
constant c_psr_func_wcc : slv3 := "001"; -- CC mode: set/clear cc
constant c_psr_func_wint : slv3 := "010"; -- interupt mode: pmode=cmode
constant c_psr_func_wrti : slv3 := "011"; -- rti mode: protect modes
constant c_psr_func_wall : slv3 := "100"; -- write all fields
component pdp11_ounit is -- offset adder for addresses (ounit)
port (
DSRC : in slv16; -- 'src' data for port A
DDST : in slv16; -- 'dst' data for port A
DTMP : in slv16; -- 'tmp' data for port A
PC : in slv16; -- PC data for port A
ASEL : in slv2; -- selector for port A
AZERO : in slbit; -- force zero for port A
IREG8 : in slv8; -- 'ireg' data for port B
VMDOUT : in slv16; -- virt. memory data for port B
CONST : in slv9; -- sequencer const data for port B
BSEL : in slv2; -- selector for port B
OPSUB : in slbit; -- operation: 0 add, 1 sub
DOUT : out slv16; -- data output
NZOUT : out slv2 -- NZ condition codes out
);
end component;
constant c_ounit_asel_ddst : slv2 := "00"; -- A = DDST
constant c_ounit_asel_dsrc : slv2 := "01"; -- A = DSRC
constant c_ounit_asel_pc : slv2 := "10"; -- A = PC
constant c_ounit_asel_dtmp : slv2 := "11"; -- A = DTMP
constant c_ounit_bsel_const : slv2 := "00"; -- B = CONST
constant c_ounit_bsel_vmdout : slv2 := "01"; -- B = VMDOUT
constant c_ounit_bsel_ireg6 : slv2 := "10"; -- B = 2*IREG(6bit)
constant c_ounit_bsel_ireg8 : slv2 := "11"; -- B = 2*IREG(8bit,sign-extend)
component pdp11_aunit is -- arithmetic unit for data (aunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CI : in slbit; -- carry flag in
SRCMOD : in slv2; -- src modifier mode
DSTMOD : in slv2; -- dst modifier mode
CIMOD : in slv2; -- ci modifier mode
CC1OP : in slbit; -- use cc modes (1 op instruction)
CCMODE : in slv3; -- cc mode
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_aunit_mod_pass : slv2 := "00"; -- pass data
constant c_aunit_mod_inv : slv2 := "01"; -- invert data
constant c_aunit_mod_zero : slv2 := "10"; -- set to 0
constant c_aunit_mod_one : slv2 := "11"; -- set to 1
-- the c_aunit_ccmode codes follow exactly the opcode format (bit 8:6)
constant c_aunit_ccmode_clr : slv3 := "000"; -- do clr instruction
constant c_aunit_ccmode_com : slv3 := "001"; -- do com instruction
constant c_aunit_ccmode_inc : slv3 := "010"; -- do inc instruction
constant c_aunit_ccmode_dec : slv3 := "011"; -- do dec instruction
constant c_aunit_ccmode_neg : slv3 := "100"; -- do neg instruction
constant c_aunit_ccmode_adc : slv3 := "101"; -- do adc instruction
constant c_aunit_ccmode_sbc : slv3 := "110"; -- do sbc instruction
constant c_aunit_ccmode_tst : slv3 := "111"; -- do tst instruction
component pdp11_lunit is -- logic unit for data (lunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CCIN : in slv4; -- condition codes in
FUNC : in slv4; -- function
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_lunit_func_asr : slv4 := "0000"; -- ASR/ASRB ??? recheck coding !!
constant c_lunit_func_asl : slv4 := "0001"; -- ASL/ASLB
constant c_lunit_func_ror : slv4 := "0010"; -- ROR/RORB
constant c_lunit_func_rol : slv4 := "0011"; -- ROL/ROLB
constant c_lunit_func_bis : slv4 := "0100"; -- BIS/BISB
constant c_lunit_func_bic : slv4 := "0101"; -- BIC/BICB
constant c_lunit_func_bit : slv4 := "0110"; -- BIT/BITB
constant c_lunit_func_mov : slv4 := "0111"; -- MOV/MOVB
constant c_lunit_func_sxt : slv4 := "1000"; -- SXT
constant c_lunit_func_swap : slv4 := "1001"; -- SWAB
constant c_lunit_func_xor : slv4 := "1010"; -- XOR
component pdp11_munit is -- mul/div unit for data (munit)
port (
CLK : in slbit; -- clock
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
DTMP : in slv16; -- 'tmp' data in
GR_DSRC : in slv16; -- 'src' data from GR
FUNC : in slv2; -- function
S_DIV : in slbit; -- s_opg_div state (load dd_low)
S_DIV_CN : in slbit; -- s_opg_div_cn state (1st..16th cycle)
S_DIV_CR : in slbit; -- s_opg_div_cr state (remainder corr.)
S_DIV_SR : in slbit; -- s_opg_div_sr state (store remainder)
S_ASH : in slbit; -- s_opg_ash state
S_ASH_CN : in slbit; -- s_opg_ash_cn state
S_ASHC : in slbit; -- s_opg_ashc state
S_ASHC_CN : in slbit; -- s_opg_ashc_cn state
SHC_TC : out slbit; -- last shc cycle (shc==0)
DIV_CR : out slbit; -- division: remainder correction needed
DIV_CQ : out slbit; -- division: quotient correction needed
DIV_QUIT : out slbit; -- division: abort (0/ or /0 or V=1)
DOUT : out slv16; -- data output
DOUTE : out slv16; -- data output extra
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_munit_func_mul : slv2 := "00"; -- MUL
constant c_munit_func_div : slv2 := "01"; -- DIV
constant c_munit_func_ash : slv2 := "10"; -- ASH
constant c_munit_func_ashc : slv2 := "11"; -- ASHC
component pdp11_mmu_padr is -- mmu PAR/PDR register set
port (
CLK : in slbit; -- clock
MODE : in slv2; -- mode
APN : in slv4; -- augmented page number (1+3 bit)
AIB_WE : in slbit; -- update AIB
AIB_SETA : in slbit; -- set access AIB
AIB_SETW : in slbit; -- set write AIB
PARPDR : out parpdr_type; -- combined PAR/PDR
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mmu_mmr12 is -- mmu register mmr1 and mmr2
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
TRACE : in slbit; -- trace enable
MONI : in mmu_moni_type; -- MMU monitor port data
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mmu is -- mmu - memory management unit
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
BRESET : in slbit; -- bus reset
CNTL : in mmu_cntl_type; -- control port
VADDR : in slv16; -- virtual address
MONI : in mmu_moni_type; -- monitor port
STAT : out mmu_stat_type; -- status port
PADDRH : out slv16; -- physical address (upper 16 bit)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_vmbox is -- virtual memory
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
CRESET : in slbit; -- cpu reset
BRESET : in slbit; -- bus reset
CP_ADDR : in cp_addr_type; -- console port address
VM_CNTL : in vm_cntl_type; -- vm control port
VM_ADDR : in slv16; -- vm address
VM_DIN : in slv16; -- vm data in
VM_STAT : out vm_stat_type; -- vm status port
VM_DOUT : out slv16; -- vm data out
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
MMU_MONI : in mmu_moni_type; -- mmu monitor port
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
);
end component;
component pdp11_dpath is -- CPU datapath
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
CNTL : in dpath_cntl_type; -- control interface
STAT : out dpath_stat_type; -- status interface
CP_DIN : in slv16; -- console port data in
CP_DOUT : out slv16; -- console port data out
PSWOUT : out psw_type; -- current psw
PCOUT : out slv16; -- current pc
IREG : out slv16; -- ireg out
VM_ADDR : out slv16; -- virt. memory address
VM_DOUT : in slv16; -- virt. memory data out
VM_DIN : out slv16; -- virt. memory data in
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status - dpath
);
end component;
component pdp11_decode is -- instruction decoder
port (
IREG : in slv16; -- input instruction word
STAT : out decode_stat_type -- status output
);
end component;
component pdp11_sequencer is -- cpu sequencer
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
PSW : in psw_type; -- processor status
PC : in slv16; -- program counter
IREG : in slv16; -- IREG
ID_STAT : in decode_stat_type; -- instr. decoder status
DP_STAT : in dpath_stat_type; -- data path status
CP_CNTL : in cp_cntl_type; -- console port control
VM_STAT : in vm_stat_type; -- virtual memory status port
INT_PRI : in slv3; -- interrupt priority
INT_VECT : in slv9_2; -- interrupt vector
INT_ACK : out slbit; -- interrupt acknowledge
CRESET : out slbit; -- cpu reset
BRESET : out slbit; -- bus reset
MMU_MONI : out mmu_moni_type; -- mmu monitor port
DP_CNTL : out dpath_cntl_type; -- data path control
VM_CNTL : out vm_cntl_type; -- virtual memory control port
CP_STAT : out cp_stat_type; -- console port status
ESUSP_O : out slbit; -- external suspend output
ESUSP_I : in slbit; -- external suspend input
HBPT : in slbit; -- hardware bpt
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DM_STAT_SE : out dm_stat_se_type -- debug and monitor status - sequencer
);
end component;
component pdp11_irq is -- interrupt requester
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- bus reset
INT_ACK : in slbit; -- interrupt acknowledge from CPU
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
PRI : out slv3; -- interrupt priority
VECT : out slv9_2; -- interrupt vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_ubmap is -- 11/70 unibus mapper
port (
CLK : in slbit; -- clock
MREQ : in slbit; -- request mapping
ADDR_UB : in slv18_1; -- UNIBUS address (in)
ADDR_PM : out slv22_1; -- physical memory address (out)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_reg70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mem70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
HM_ENA : in slbit; -- hit/miss enable
HM_VAL : in slbit; -- hit/miss value
CACHE_FMISS : out slbit; -- cache force miss
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_cache is -- cache
generic (
TWIDTH : positive := 9); -- tag width (5 to 9)
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type; -- em response
FMISS : in slbit; -- force miss
MEM_REQ : out slbit; -- memory: request
MEM_WE : out slbit; -- memory: write enable
MEM_BUSY : in slbit; -- memory: controller busy
MEM_ACK_R : in slbit; -- memory: acknowledge read
MEM_ADDR : out slv20; -- memory: address
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32; -- memory: data out (memory view)
DM_STAT_CA : out dm_stat_ca_type -- debug and monitor status - cache
);
end component;
component pdp11_core is -- full processor core
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CP_CNTL : in cp_cntl_type; -- console control port
CP_ADDR : in cp_addr_type; -- console address port
CP_DIN : in slv16; -- console data in
CP_STAT : out cp_stat_type; -- console status port
CP_DOUT : out slv16; -- console data out
ESUSP_O : out slbit; -- external suspend output
ESUSP_I : in slbit; -- external suspend input
HBPT : in slbit; -- hardware bpt
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
CRESET : out slbit; -- cpu reset
BRESET : out slbit; -- bus reset
IB_MREQ_M : out ib_mreq_type; -- ibus master request (master)
IB_SRES_M : in ib_sres_type; -- ibus slave response (master)
DM_STAT_SE : out dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
);
end component;
component pdp11_tmu is -- trace and monitor unit
port (
CLK : in slbit; -- clock
ENA : in slbit := '0'; -- enable trace output
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache
);
end component;
-- this definition logically belongs into a 'for test benches' section'
-- it is here for convenience to simplify instantiations.
constant sbcntl_sbf_tmu : integer := 12;
component pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
generic (
ENAPIN : integer := sbcntl_sbf_tmu); -- SB_CNTL for tmu
port (
CLK : in slbit; -- clock
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache
);
end component;
component pdp11_du_drv is -- display unit low level driver
generic (
CDWIDTH : positive := 3); -- clock divider width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
ROW0 : in slv22; -- led row 0 (22 leds, top)
ROW1 : in slv16; -- led row 1 (16 leds)
ROW2 : in slv16; -- led row 2 (16 leds)
ROW3 : in slv10; -- led row 3 (10 leds, bottom)
SWOPT : out slv8; -- option pattern from du
SWOPT_RDY : out slbit; -- marks update of swopt
DU_SCLK : out slbit; -- DU: sclk
DU_SS_N : out slbit; -- DU: ss_n
DU_MOSI : out slbit; -- DU: mosi (master out, slave in)
DU_MISO : in slbit -- DU: miso (master in, slave out)
);
end component;
component pdp11_bram is -- BRAM based ext. memory dummy
generic (
AWIDTH : positive := 14); -- address width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type -- em response
);
end component;
component pdp11_bram_memctl is -- BRAM based memctl
generic (
MAWIDTH : positive := 4; -- mux address width
NBLOCK : positive := 11); -- number of 16 kByte blocks
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32 -- data out (memory view)
);
end component;
component pdp11_statleds is -- status leds
port (
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
STATLEDS : out slv8 -- 8 bit CPU status
);
end component;
component pdp11_ledmux is -- hio led mux
generic (
LWIDTH : positive := 8); -- led width
port (
SEL : in slbit; -- select (0=stat;1=dr)
STATLEDS : in slv8; -- 8 bit CPU status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
LED : out slv(LWIDTH-1 downto 0) -- hio leds
);
end component;
component pdp11_dspmux is -- hio dsp mux
generic (
DCWIDTH : positive := 2); -- digit counter width (2 or 3)
port (
SEL : in slv2; -- select
ABCLKDIV : in slv16; -- serport clock divider
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
DISPREG : in slv16; -- display register
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data
);
end component;
component pdp11_core_rbus is -- core to rbus interface
generic (
RB_ADDR_CORE : slv16 := rbaddr_cpu0_core;
RB_ADDR_IBUS : slv16 := rbaddr_cpu0_ibus);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_STAT : out slv4; -- rbus: status flags
RB_LAM : out slbit; -- remote attention
GRESET : out slbit; -- general reset
CP_CNTL : out cp_cntl_type; -- console control port
CP_ADDR : out cp_addr_type; -- console address port
CP_DIN : out slv16; -- console data in
CP_STAT : in cp_stat_type; -- console status port
CP_DOUT : in slv16 -- console data out
);
end component;
component pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus request (slave)
RB_SRES : out rb_sres_type; -- rbus response
RB_STAT : out slv4; -- rbus status flags
RB_LAM_CPU : out slbit; -- rbus lam (cpu)
GRESET : out slbit; -- general reset (from rbus)
CRESET : out slbit; -- cpu reset (from cp)
BRESET : out slbit; -- bus reset (from cp or cpu)
CP_STAT : out cp_stat_type; -- console port status
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
PERFEXT : in slv8; -- cpu external perf counter signals
IB_MREQ : out ib_mreq_type; -- ibus request (master)
IB_SRES : in ib_sres_type; -- ibus response (from IO system)
MEM_REQ : out slbit; -- memory: request
MEM_WE : out slbit; -- memory: write enable
MEM_BUSY : in slbit; -- memory: controller busy
MEM_ACK_R : in slbit; -- memory: acknowledge read
MEM_ADDR : out slv20; -- memory: address
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32; -- memory: data out (memory view)
DM_STAT_EXP : out dm_stat_exp_type -- debug and monitor - sys70 exports
);
end component;
component pdp11_hio70 is -- hio led and dsp for sys70
generic (
LWIDTH : positive := 8; -- led width
DCWIDTH : positive := 2); -- digit counter width (2 or 3)
port (
SEL_LED : in slbit; -- led select (0=stat;1=dr)
SEL_DSP : in slv2; -- dsp select
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
ABCLKDIV : in slv16; -- serport clock divider
DISPREG : in slv16; -- display register
LED : out slv(LWIDTH-1 downto 0); -- hio leds
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data
);
end component;
component pdp11_dmscnt is -- debug&moni: state counter
generic (
RB_ADDR : slv16 := rbaddr_dmscnt_off);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core
);
end component;
component pdp11_dmcmon is -- debug&moni: cpu monitor
generic (
RB_ADDR : slv16 := rbaddr_dmcmon_off;
AWIDTH : natural := 8;
SNUM : boolean := false);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core
);
end component;
component pdp11_dmhbpt is -- debug&moni: hardware breakpoint
generic (
RB_ADDR : slv16 := rbaddr_dmhbpt_off;
NUNIT : natural := 2);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
HBPT : out slbit -- hw break flag
);
end component;
component pdp11_dmhbpt_unit is -- dmhbpt - indivitial unit
generic (
RB_ADDR : slv16 := rbaddr_dmhbpt_off;
INDEX : natural := 0);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
HBPT : out slbit -- hw break flag
);
end component;
component pdp11_dmpcnt is -- debug&moni: performance counters
generic (
RB_ADDR : slv16 := rbaddr_dmpcnt_off; -- rbus address
VERS : slv8 := slv(to_unsigned(0, 8)); -- counter layout version
CENA : slv32 := (others=>'1')); -- counter enables
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
PERFSIG : in slv32 -- signals to count
);
end component;
-- ----- move later to pdp11_conf --------------------------------------------
constant conf_vect_pirq : integer := 8#240#;
constant conf_pri_pirq_1 : integer := 1;
constant conf_pri_pirq_2 : integer := 2;
constant conf_pri_pirq_3 : integer := 3;
constant conf_pri_pirq_4 : integer := 4;
constant conf_pri_pirq_5 : integer := 5;
constant conf_pri_pirq_6 : integer := 6;
constant conf_pri_pirq_7 : integer := 7;
end package pdp11;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd | 1 | 2496 | -- $Id: ram_2swsr_rfirst_gen_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_rfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-before-write' semantics (as block RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim
-- 2008-03-02 122 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.memlib.all;
entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
generic (
AWIDTH : positive := 13; -- address port width 11/9 or 13/8
DWIDTH : positive := 8); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_rfirst_gen;
architecture syn of ram_2swsr_rfirst_gen is
begin
UMEM: ram_2swsr_xfirst_gen_unisim
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH,
WRITE_MODE => "READ_FIRST")
port map (
CLKA => CLKA,
CLKB => CLKB,
ENA => ENA,
ENB => ENB,
WEA => WEA,
WEB => WEB,
ADDRA => ADDRA,
ADDRB => ADDRB,
DIA => DIA,
DIB => DIB,
DOA => DOA,
DOB => DOB
);
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/rlink/tbcore/tbcore_rlink.vhd | 1 | 9457 | -- $Id: tbcore_rlink.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbcore_rlink - sim
-- Description: Core for a rlink_cext based test bench
--
-- Dependencies: simlib/simclkcnt
-- rlink_cext_iface
--
-- To test: generic, any rlink_cext based target
--
-- Target Devices: generic
-- Tool versions: ghdl 0.26-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-25 1074 3.3 wait 40 cycles after CONF_DONE
-- 2016-09-17 807 3.2.2 conf: .sinit -> .sdata; finite length SB_VAL pulse
-- 2016-09-02 805 3.2.1 conf: add .wait and CONF_DONE; drop CLK_STOP
-- 2016-02-07 729 3.2 use rlink_cext_iface (allow VHPI and DPI backend)
-- 2015-11-01 712 3.1.3 proc_stim: drive SB_CNTL from start to avoid 'U'
-- 2013-01-04 469 3.1.2 use 1ns wait for .sinit to allow simbus debugging
-- 2011-12-25 445 3.1.1 add SB_ init drivers to avoid SB_VAL='U' at start
-- 2011-12-23 444 3.1 redo clock handling, remove simclk, CLK now input
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 rename rritb_core->tbcore_rlink; use rbv3 naming
-- 2010-06-05 301 1.1.2 rename .rpmon -> .rbmon
-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit;
-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib;
-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rblib.all;
use work.rlinklib.all;
entity tbcore_rlink is -- core of rlink_cext based test bench
port (
CLK : in slbit; -- control interface clock
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end tbcore_rlink;
architecture sim of tbcore_rlink is
signal CLK_CYCLE : integer := 0;
signal CEXT_CYCLE : slv32 := (others=>'0');
signal CEXT_RXDATA : slv32 := (others=>'0');
signal CEXT_RXVAL : slbit := '0';
signal CEXT_RXHOLD : slbit := '1';
signal CONF_DONE : slbit := '0';
begin
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
CEXT_IFACE : entity work.rlink_cext_iface
port map (
CLK => CLK,
CLK_CYCLE => CEXT_CYCLE,
RX_DATA => CEXT_RXDATA,
RX_VAL => CEXT_RXVAL,
RX_HOLD => CEXT_RXHOLD,
TX_DATA => TX_DATA,
TX_ENA => TX_ENA
);
CEXT_CYCLE <= slv(to_signed(CLK_CYCLE,32));
proc_conf: process
file fconf : text open read_mode is "rlink_cext_conf";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable ien : slbit := '0';
variable ibit : integer := 0;
variable twait : Delay_length := 0 ns;
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
CONF_DONE <= '0';
SB_SIMSTOP <= 'L';
SB_CNTL <= (others=>'L');
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
file_loop: while not endfile(fconf) loop
readline (fconf, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".scntl" => -- .scntl
read_ea(iline, ibit);
read_ea(iline, ien);
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
report "assert bit number in range of SB_CNTL"
severity failure;
wait for 1 ns;
if ien = '1' then
SB_CNTL(ibit) <= 'H';
else
SB_CNTL(ibit) <= 'L';
end if;
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
wait for 1 ns;
if ien = '1' then
SB_CNTL(sbcntl_sbf_rlmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_rlmon) <= 'L';
end if;
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
wait for 1 ns;
if ien = '1' then
SB_CNTL(sbcntl_sbf_rbmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_rbmon) <= 'L';
end if;
when ".sdata" => -- .sdata
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
wait for 1 ns;
SB_ADDR <= iaddr;
SB_DATA <= idata;
SB_VAL <= 'H';
wait for 1 ns;
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
when ".wait " => -- .wait
read_ea(iline, twait);
wait for twait;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
CONF_DONE <= '1';
wait; -- halt process here
end process proc_conf;
proc_stim: process
variable irxint : integer := 0;
variable irxslv : slv24 := (others=>'0');
variable ibit : integer := 0;
variable oline : line;
variable r_sb_cntl : slv16 := (others=>'Z');
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
-- setup init values for all output ports
RX_DATA <= (others=>'0');
RX_VAL <= '0';
SB_VAL <= 'Z';
SB_ADDR <= (others=>'Z');
SB_DATA <= (others=>'Z');
SB_CNTL <= (others=>'Z');
CEXT_RXHOLD <= '1';
-- wait for CONF_DONE, plus addional 40 clock cycles (conf+design run up)
while CONF_DONE = '0' loop
wait until rising_edge(CLK);
end loop;
for i in 0 to 39 loop
wait until rising_edge(CLK);
end loop; -- i
writetimestamp(oline, CLK_CYCLE, ": START");
writeline(output, oline);
stim_loop: loop
wait until falling_edge(CLK);
SB_ADDR <= (others=>'Z');
SB_DATA <= (others=>'Z');
RX_VAL <= '0';
CEXT_RXHOLD <= RX_HOLD;
if RX_HOLD = '0' then
irxint := to_integer(signed(CEXT_RXDATA));
if CEXT_RXVAL = '1' then
if irxint <= 16#ff# then -- normal data byte
RX_DATA <= slv(to_unsigned(irxint, 8));
RX_VAL <= '1';
elsif irxint >= 16#1000000# then -- out-of-band message
irxslv := slv(to_unsigned(irxint mod 16#1000000#, 24));
iaddr := irxslv(23 downto 16);
idata := irxslv(15 downto 0);
writetimestamp(oline, CLK_CYCLE, ": OOB-MSG");
write(oline, irxslv(23 downto 16), right, 9);
write(oline, irxslv(15 downto 8), right, 9);
write(oline, irxslv( 7 downto 0), right, 9);
write(oline, string'(" : "));
writeoct(oline, iaddr, right, 3);
writeoct(oline, idata, right, 7);
writeline(output, oline);
if unsigned(iaddr) = 0 then
ibit := to_integer(unsigned(idata(15 downto 8)));
r_sb_cntl(ibit) := idata(0);
else
SB_ADDR <= iaddr;
SB_DATA <= idata;
-- In principle a delta cycle long pulse is enough to make the
-- simbus transfer. A 500 ps long pulse is generated to ensure
-- that SB_VAL is visible in a viewer. That works up to 1 GHz
SB_VAL <= '1';
wait for 500 ps;
SB_VAL <= 'Z';
wait for 0 ps;
end if;
end if;
elsif irxint = -1 then -- end-of-file seen
exit stim_loop;
else
report "rlink_cext_getbyte error: " & integer'image(-irxint)
severity failure;
end if; -- CEXT_RXVAL = '1'
end if; -- RX_HOLD = '0'
SB_CNTL <= r_sb_cntl;
end loop;
-- wait for 50 clock cycles (design run down)
for i in 0 to 49 loop
wait until rising_edge(CLK);
end loop; -- i
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
SB_SIMSTOP <= '1'; -- signal simulation stop
wait for 100 ns; -- monitor grace time
report "Simulation Finished" severity failure; -- end simulation
end process proc_stim;
end sim;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd | 1 | 18448 | -- $Id: tb_tst_serloop.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop - sim
-- Description: Generic test bench for sys_tst_serloop_xx
--
-- Dependencies: vlib/simlib/simclkcnt
-- vlib/serport/serport_uart_rxtx_tb
-- vlib/serport/serport_xontx_tb
--
-- To test: sys_tst_serloop_xx
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2.2 remove CLK_STOP logic (simstop via report)
-- 2016-08-18 799 1.2.1 remove 'assert false' from report statements
-- 2016-04-23 764 1.2 use serport/tb/serport_(uart_rxtx|xontx)_tb
-- use assert to halt simulation
-- 2011-12-23 444 1.1 use new simclkcnt
-- 2011-11-13 425 1.0 Initial version
-- 2011-11-06 420 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.serportlib_tb.all;
entity tb_tst_serloop is
port (
CLKS : in slbit; -- clock for serport
CLKH : in slbit; -- clock for humanio
P0_RXD : out slbit; -- port 0 receive data (board view)
P0_TXD : in slbit; -- port 0 transmit data (board view)
P0_RTS_N : in slbit; -- port 0 rts_n
P0_CTS_N : out slbit; -- port 0 cts_n
P1_RXD : out slbit; -- port 1 receive data (board view)
P1_TXD : in slbit; -- port 1 transmit data (board view)
P1_RTS_N : in slbit; -- port 1 rts_n
P1_CTS_N : out slbit; -- port 1 cts_n
SWI : out slv8; -- hio switches
BTN : out slv4 -- hio buttons
);
end tb_tst_serloop;
architecture sim of tb_tst_serloop is
signal CLK_CYCLE : integer := 0;
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal CLKDIV : slv13 := (others=>'0');
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal ACTPORT : slbit := '0';
signal BREAK : slbit := '0';
signal CTS_CYCLE : integer := 0;
signal CTS_FRACT : integer := 0;
signal XON_CYCLE : integer := 0;
signal XON_FRACT : integer := 0;
signal S2M_ACTIVE : slbit := '0';
signal S2M_SIZE : integer := 0;
signal S2M_ENAESC : slbit := '0';
signal S2M_ENAXON : slbit := '0';
signal M2S_XONSEEN : slbit := '0';
signal M2S_XOFFSEEN : slbit := '0';
signal R_XONRXOK : slbit := '1';
signal R_XONTXOK : slbit := '1';
begin
CLKCNT : simclkcnt port map (CLK => CLKS, CLK_CYCLE => CLK_CYCLE);
UART : entity work.serport_uart_rxtx_tb
generic map (
CDWIDTH => 13)
port map (
CLK => CLKS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
);
XONTX : entity work.serport_xontx_tb
port map (
CLK => CLKS,
RESET => UART_RESET,
ENAXON => S2M_ENAXON,
ENAESC => S2M_ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => UART_TXENA,
UART_TXBUSY => UART_TXBUSY,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXOK => R_XONRXOK,
TXOK => R_XONTXOK
);
proc_port_mux: process (ACTPORT, BREAK, UART_TXD, CTS_N,
P0_TXD, P0_RTS_N, P1_TXD, P1_RTS_N)
variable eff_txd : slbit := '0';
begin
if BREAK = '0' then -- if no break active
eff_txd := UART_TXD; -- send uart
else -- otherwise
eff_txd := '0'; -- force '0'
end if;
if ACTPORT = '0' then -- use port 0
P0_RXD <= eff_txd; -- write port 0 inputs
P0_CTS_N <= CTS_N;
UART_RXD <= P0_TXD; -- get port 0 outputs
RTS_N <= P0_RTS_N;
P1_RXD <= '1'; -- port 1 inputs to idle state
P1_CTS_N <= '0';
else -- use port 1
P1_RXD <= eff_txd; -- write port 1 inputs
P1_CTS_N <= CTS_N;
UART_RXD <= P1_TXD; -- get port 1 outputs
RTS_N <= P1_RTS_N;
P0_RXD <= '1'; -- port 0 inputs to idle state
P0_CTS_N <= '0';
end if;
end process proc_port_mux;
proc_cts: process(CLKS)
variable cts_timer : integer := 0;
begin
if rising_edge(CLKS) then
if CTS_CYCLE = 0 then -- if cts throttle off
CTS_N <= '0'; -- cts permanently asserted
else -- otherwise determine throttling
if cts_timer>0 and cts_timer<CTS_CYCLE then -- unless beyond ends
cts_timer := cts_timer - 1; -- decrement
else
cts_timer := CTS_CYCLE-1; -- otherwise reload
end if;
if cts_timer < cts_fract then -- if in lower 'fract' counts
CTS_N <= '1'; -- throttle: deassert CTS
else -- otherwise
CTS_N <= '0'; -- let go: assert CTS
end if;
end if;
end if;
end process proc_cts;
proc_xonrxok: process(CLKS)
variable xon_timer : integer := 0;
begin
if rising_edge(CLKS) then
if XON_CYCLE = 0 then -- if xon throttle off
R_XONRXOK <= '1'; -- xonrxok permanently asserted
else -- otherwise determine throttling
if xon_timer>0 and xon_timer<XON_CYCLE then -- unless beyond ends
xon_timer := xon_timer - 1; -- decrement
else
xon_timer := XON_CYCLE-1; -- otherwise reload
end if;
if xon_timer < xon_fract then -- if in lower 'fract' counts
R_XONRXOK <= '0'; -- throttle: deassert xonrxok
else -- otherwise
R_XONRXOK <= '1'; -- let go: assert xonrxok
end if;
end if;
end if;
end process proc_xonrxok;
proc_xontxok: process(CLKS)
begin
if rising_edge(CLKS) then
if M2S_XONSEEN = '1' then
R_XONTXOK <= '1';
elsif M2S_XOFFSEEN = '1' then
R_XONTXOK <= '0';
end if;
end if;
end process proc_xontxok;
proc_stim: process
file fstim : text open read_mode is "tb_tst_serloop_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable iactport : slbit := '0';
variable iswi : slv8 := (others=>'0');
variable btn_num : integer := 0;
variable i_cycle : integer := 0;
variable i_fract : integer := 0;
variable nbyte : integer := 0;
variable enaesc : slbit := '0';
variable enaxon : slbit := '0';
variable bcnt : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
procedure waitclk(ncyc : in integer) is
begin
for i in 1 to ncyc loop
wait until rising_edge(CLKS);
end loop; -- i
end procedure waitclk;
begin
-- initialize some top level out signals
SWI <= (others=>'0');
BTN <= (others=>'0');
wait until rising_edge(CLKS);
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when "wait " => -- wait
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": wait ");
write(oline, idelta, right, 5);
writeline(output, oline);
waitclk(idelta);
when "port " => -- switch rs232 port
read_ea(iline, iactport);
ACTPORT <= iactport;
writetimestamp(oline, CLK_CYCLE, ": port ");
write(oline, iactport, right, 5);
writeline(output, oline);
when "cts " => -- setup cts throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
CTS_CYCLE <= i_cycle;
CTS_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "xon " => -- setup xon throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
XON_CYCLE <= i_cycle;
XON_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "swi " => -- new SWI settings
read_ea(iline, iswi);
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": swi ");
write(oline, iswi, right, 10);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
SWI <= iswi;
wait until rising_edge(CLKS);
waitclk(idelta);
when "btn " => -- BTN push (3 cyc down + 3 cyc wait)
read_ea(iline, btn_num);
read_ea(iline, idelta);
if btn_num>=0 and btn_num<=3 then
writetimestamp(oline, CLK_CYCLE, ": btn ");
write(oline, btn_num, right, 5);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
BTN(btn_num) <= '1'; -- 3 cycle BTN pulse
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
BTN(btn_num) <= '0';
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKS);
waitclk(idelta);
else
write(oline, string'("!! btn: btn number out of range"));
writeline(output, oline);
end if;
when "expect" => -- expect n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": expect");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
if nbyte > 0 then
S2M_ACTIVE <= '1';
S2M_SIZE <= nbyte;
else
S2M_ACTIVE <= '0';
end if;
S2M_ENAESC <= enaesc;
S2M_ENAXON <= enaxon;
wait until rising_edge(CLKS);
when "send " => -- send n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
bcnt := 0;
itxdata := (others=>'0');
wait until falling_edge(CLKS);
while bcnt < nbyte loop
while TXBUSY='1' or RTS_N='1' loop
wait until falling_edge(CLKS);
end loop;
TXDATA <= itxdata;
itxdata := slv(unsigned(itxdata) + 1);
bcnt := bcnt + 1;
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until falling_edge(CLKS);
end loop;
while TXBUSY='1' or RTS_N='1' loop -- wait till last char send...
wait until falling_edge(CLKS);
end loop;
wait until rising_edge(CLKS);
when "break " => -- send a break for n cycles
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": break ");
write(oline, idelta, right, 5);
writeline(output, oline);
-- send break for n cycles
BREAK <= '1';
waitclk(idelta);
BREAK <= '0';
-- wait for 3 bit cell width
waitclk(3*to_integer(unsigned(CLKDIV)+1));
-- send 'sync' character
wait until falling_edge(CLKS);
TXDATA <= "10000000";
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until rising_edge(CLKS);
when "clkdiv" => -- set new clock divider
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": clkdiv");
write(oline, idelta, right, 5);
writeline(output, oline);
CLKDIV <= slv(to_unsigned(idelta, CLKDIV'length));
UART_RESET <= '1';
wait until rising_edge(CLKS);
UART_RESET <= '0';
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop
-- extra wait for at least two character times (20 bit times)
-- to allow tx and rx of the last character
waitclk(20*(to_integer(unsigned(CLKDIV))+1));
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
SB_SIMSTOP <= '1'; -- signal simulation stop
wait for 100 ns; -- monitor grace time
report "Simulation Finished" severity failure; -- end simulation
end process proc_stim;
proc_moni: process
variable oline : line;
variable dclk : integer := 0;
variable active_1 : slbit := '0';
variable irxdata : slv8 := (others=>'0');
variable irxeff : slv8 := (others=>'0');
variable irxval : slbit := '0';
variable doesc : slbit := '0';
variable bcnt : integer := 0;
variable xseen : slbit := '0';
begin
loop
wait until falling_edge(CLKS);
M2S_XONSEEN <= '0';
M2S_XOFFSEEN <= '0';
if S2M_ACTIVE='1' and active_1='0' then -- start expect message
irxdata := (others=>'0');
bcnt := 0;
end if;
if S2M_ACTIVE='0' and active_1='1' then -- end expect message
if bcnt = S2M_SIZE then
writetimestamp(oline, CLK_CYCLE, ": OK: message seen");
else
writetimestamp(oline, CLK_CYCLE, ": FAIL: missing chars, seen=");
write(oline, bcnt, right, 5);
write(oline, string'(" expect="));
write(oline, S2M_SIZE, right, 5);
end if;
writeline(output, oline);
end if;
active_1 := S2M_ACTIVE;
if RXVAL = '1' then
writetimestamp(oline, CLK_CYCLE, ": char: ");
write(oline, RXDATA, right, 10);
write(oline, string'(" ("));
writeoct(oline, RXDATA, right, 3);
write(oline, string'(") dt="));
write(oline, dclk, right, 4);
irxeff := RXDATA;
irxval := '1';
if doesc = '1' then
irxeff := not RXDATA;
irxval := '1';
doesc := '0';
write(oline, string'(" eff="));
write(oline, irxeff, right, 10);
write(oline, string'(" ("));
writeoct(oline, irxeff, right, 3);
write(oline, string'(")"));
elsif S2M_ENAESC='1' and RXDATA=c_serport_xesc then
doesc := '1';
irxval := '0';
write(oline, string'(" XESC seen"));
end if;
xseen := '0';
if S2M_ENAXON = '1' then
if RXDATA = c_serport_xon then
write(oline, string'(" XON seen"));
M2S_XONSEEN <= '1';
xseen := '1';
elsif RXDATA = c_serport_xoff then
write(oline, string'(" XOFF seen"));
M2S_XOFFSEEN <= '1';
xseen := '1';
end if;
end if;
if S2M_ACTIVE='1' and irxval='1' and xseen='0' then
if irxeff = irxdata then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL: expect="));
write(oline, irxdata, right, 10);
end if;
irxdata := slv(unsigned(irxdata) + 1);
bcnt := bcnt + 1;
end if;
writeline(output, oline);
dclk := 0;
end if;
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, ": FAIL: RXERR='1'");
writeline(output, oline);
end if;
dclk := dclk + 1;
end loop;
end process proc_moni;
end sim;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/w11a/basys3/sys_conf.vhd | 1 | 5384 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_b3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2014.4-2018.3; ghdl 0.31-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.4.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.4 use typ for DL,PC,LP; add dz11,ibtst
-- 2018-09-22 1050 1.3.7 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.3.6 add sys_conf_ibd_kw11p
-- 2017-03-04 858 1.3.5 enable deuna
-- 2017-01-29 847 1.3.4 add sys_conf_ibd_deuna
-- 2016-06-18 775 1.3.3 use PLL for clkser_gentype
-- 2016-05-28 770 1.3.2 sys_conf_mem_losize now type natural
-- 2016-05-26 768 1.3.1 set dmscnt=0 (vivado fsm issue) (@80 MHz)
-- 2016-03-28 755 1.3 use serport_2clock2 -> define clkser (@75 MHz)
-- 2016-03-22 750 1.2 add sys_conf_cache_twidth
-- 2016-03-13 742 1.1.2 add sysmon_bus; use 72 MHz, no tc otherwise
-- 2015-06-26 695 1.1.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
-- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions
-- 2015-02-08 644 1.0 Initial version (derived from _n4 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_mawidth : positive := 4;
constant sys_conf_memctl_nblock : positive := 11;
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
-- sys_conf_mem_losize is highest 64 byte MMU block number
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1;
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 |
wfjm/w11 | rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vhd | 1 | 18787 | -- $Id: sys_tst_mig_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_mig_n4d - syn
-- Description: test of nexyx4d ddr and its mig controller
--
-- Dependencies: vlib/xlib/bufg_unisim
-- bplib/bpgen/s7_cmt_1ce1ce2c
-- cdclib/cdc_signal_s1_as
-- cdclib/cdc_pulse
-- bplib/bpgen/bp_rs232_4line_iob
-- rlink/rlink_sp2c
-- tst_mig
-- bplib/nexyx4d/migui_nexyx4d (generated core)
-- bplib/sysmon/sysmonx_rbus_base
-- rbus/rbd_usracc
-- rbus/rb_sres_or_3
--
-- Test bench: tb/tb_tst_mig_n4d
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a100t-1l 4216 3821 412 1 1726
-- 2019-08-10 1201 2019.1 xc7a100t-1l 4217 4173 440 1 1709 +clkmon
-- 2019-02-02 1108 2018.3 xc7a100t-1l 4106 4145 440 1 1689
-- 2019-02-02 1108 2017.2 xc7a100t-1l 4097 4310 440 1 1767
-- 2019-01-02 1101 2017.2 xc7a100t-1l 4097 4310 457 1 1767
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-07-05 1247 1.1.1 use bufg_unisim
-- 2019-08-10 1201 1.1 use 100 MHz MIG SYS_CLK; add clock monitor
-- 2018-12-30 1099 1.0 Initial version
------------------------------------------------------------------------------
--
-- Usage of Nexys 4 Switches, Buttons, LEDs
--
-- SWI -- unused --
--
-- BTN
-- (4) ce -- unused --
-- (3) le issue MIG_SYS_RST
-- (2) do light LED(12:15)
-- (1) ri light LED(8:11)
-- (0) up light LED(4:7)
--
-- LEDs
-- (15) I_BTN(2) or R_FLG_UI_CLK (MIG UI clock monitor 75 MHz)
-- (14) I_BTN(2) or R_FLG_CLKREF (CLKREF clock monitor 200 MHz)
-- (13) I_BTN(2) or R_FLG_CLKSER (CLKSER clock monitor 120 MHz)
-- (12) I_BTN(2) or R_FLG_XX_CLK (sysclk clock monitor 80 MHz)
-- (11) I_BTN(1) or not APP_WDF_RDY
-- (10) I_BTN(1) or not APP_RDY
-- (8:9) I_BTN(1)
-- (7) I_BTN(0) or not MIG_INIT_CALIB_COMPLETE
-- (6) I_BTN(0) or MIG_UI_CLK_SYNC_RST
-- (5) I_BTN(0)
-- (4) I_BTN(0) or not LOCKED
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.miglib_nexys4d.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_mig_n4d is -- top level
-- implements nexys4d_mig_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1 -- dram: on-die termination
);
end sys_tst_mig_n4d;
architecture syn of sys_tst_mig_n4d is
signal CLK100_BUF : slbit := '0';
signal XX_CLK : slbit := '0'; -- kept to keep clock setup similar
signal XX_CE_USEC : slbit := '0'; -- to w11a or other 'normal' systems
signal XX_CE_MSEC : slbit := '0'; --
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLKMIG : slbit := '0'; -- sync'ed to CLKMIG
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
signal APP_CMD : slv3 := (others=>'0');
signal APP_EN : slbit := '0';
signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_WDF_END : slbit := '0';
signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
signal APP_WDF_WREN : slbit := '0';
signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_RD_DATA_END : slbit := '0';
signal APP_RD_DATA_VALID : slbit := '0';
signal APP_RDY : slbit := '0';
signal APP_WDF_RDY : slbit := '0';
signal APP_SR_REQ : slbit := '0';
signal APP_REF_REQ : slbit := '0';
signal APP_ZQ_REQ : slbit := '0';
signal APP_SR_ACTIVE : slbit := '0';
signal APP_REF_ACK : slbit := '0';
signal APP_ZQ_ACK : slbit := '0';
signal MIG_UI_CLK : slbit := '0';
signal MIG_UI_CLK_SYNC_RST : slbit := '0';
signal MIG_INIT_CALIB_COMPLETE : slbit := '0';
signal MIG_SYS_RST : slbit := '0';
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
signal R_CNT_UI_CLK : slv(25 downto 0) := (others=>'0');
signal R_CNT_CLKREF : slv(26 downto 0) := (others=>'0');
signal R_CNT_CLKSER : slv(25 downto 0) := (others=>'0');
signal R_CNT_XX_CLK : slv(25 downto 0) := (others=>'0');
signal R_FLG_UI_CLK : slbit := '0';
signal R_FLG_CLKREF : slbit := '0';
signal R_FLG_CLKSER : slbit := '0';
signal R_FLG_XX_CLK : slbit := '0';
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0105"; -- tst_mig
constant sysid_board : slv8 := x"08"; -- nexys4d
constant sysid_vers : slv8 := x"00";
begin
CLK100_BUFG: bufg_unisim
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 12, -- vco 1200 MHz
CLK2_OUTDIV => 12, -- mig sys 100.0 MHz (unused)
CLK3_OUTDIV => 6, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => XX_CLK,
CE0_USEC => XX_CE_USEC,
CE0_MSEC => XX_CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => open,
CLK3 => CLKREF,
LOCKED => LOCKED
);
-- Note: CLK0 is generated as in 'normal' systems to keep PPL/MMCM setup
-- as similar as possible. The CE_USEC and CE_MSEC pulses are forwarded
-- from the 80 MHz CLK0 domain to the 75.000 MHz MIG UI_CLK domain
CDC_CEUSEC : cdc_pulse -- provide CLK side CE_USEC
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => XX_CLK,
RESET => '0',
CLKS => CLK,
PIN => XX_CE_USEC,
BUSY => open,
POUT => CE_USEC
);
CDC_CEMSEC : cdc_pulse -- provide CLK side CE_MSEC
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => XX_CLK,
RESET => '0',
CLKS => CLK,
PIN => XX_CE_MSEC,
BUSY => open,
POUT => CE_MSEC
);
CDC_CLKMIG_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLK100_BUF,
DI => LOCKED,
DO => LOCKED_CLKMIG
);
IOB_RS232 : bp_rs232_4line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
RLINK : rlink_sp2c
generic map (
BTOWIDTH => 8, -- 256 cycles, for slow mem iface
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => '0', -- FIXME: no RESET
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '0',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_mig
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
MAWIDTH => mig_mawidth,
MWIDTH => mig_mwidth)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => '0', -- FIXME: no RESET
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => APP_SR_REQ,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_SR_ACTIVE => APP_SR_ACTIVE,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK,
MIG_UI_CLK_SYNC_RST => MIG_UI_CLK_SYNC_RST,
MIG_INIT_CALIB_COMPLETE => MIG_INIT_CALIB_COMPLETE,
MIG_DEVICE_TEMP_I => XADC_TEMP
);
MIG_CTL: migui_nexys4d -- MIG iface -----------------
port map (
DDR2_DQ => DDR2_DQ,
DDR2_DQS_P => DDR2_DQS_P,
DDR2_DQS_N => DDR2_DQS_N,
DDR2_ADDR => DDR2_ADDR,
DDR2_BA => DDR2_BA,
DDR2_RAS_N => DDR2_RAS_N,
DDR2_CAS_N => DDR2_CAS_N,
DDR2_WE_N => DDR2_WE_N,
DDR2_CK_P => DDR2_CK_P,
DDR2_CK_N => DDR2_CK_N,
DDR2_CKE => DDR2_CKE,
DDR2_CS_N => DDR2_CS_N,
DDR2_DM => DDR2_DM,
DDR2_ODT => DDR2_ODT,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => APP_SR_REQ,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_SR_ACTIVE => APP_SR_ACTIVE,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK,
UI_CLK => CLK,
UI_CLK_SYNC_RST => MIG_UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => MIG_INIT_CALIB_COMPLETE,
SYS_CLK_I => CLK100_BUF,
CLK_REF_I => CLKREF,
DEVICE_TEMP_I => XADC_TEMP,
SYS_RST => MIG_SYS_RST
);
MIG_SYS_RST <= (not LOCKED_CLKMIG) or I_BTN(3); -- provisional !
SMRB: sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => '0', -- FIXME: no RESET
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
proc_mon_ui_clk: process (CLK, I_BTN(3))
begin
if I_BTN(3) = '1' then
R_FLG_UI_CLK <= '1';
R_CNT_UI_CLK <= (others=>'0');
end if;
if rising_edge(CLK) then
if unsigned(R_CNT_UI_CLK) = 37500000-1 then
R_FLG_UI_CLK <= not R_FLG_UI_CLK;
R_CNT_UI_CLK <= (others=>'0');
else
R_CNT_UI_CLK <= slv(unsigned(R_CNT_UI_CLK) + 1);
end if;
end if;
end process proc_mon_ui_clk;
proc_mon_clkref: process (CLKREF, I_BTN(3))
begin
if I_BTN(3) = '1' then
R_FLG_CLKREF <= '1';
R_CNT_CLKREF <= (others=>'0');
end if;
if rising_edge(CLKREF) then
if unsigned(R_CNT_CLKREF) = 100000000-1 then
R_FLG_CLKREF <= not R_FLG_CLKREF;
R_CNT_CLKREF <= (others=>'0');
else
R_CNT_CLKREF <= slv(unsigned(R_CNT_CLKREF) + 1);
end if;
end if;
end process proc_mon_clkref;
proc_mon_clkser: process (CLKS, I_BTN(3))
begin
if I_BTN(3) = '1' then
R_FLG_CLKSER <= '1';
R_CNT_CLKSER <= (others=>'0');
end if;
if rising_edge(CLKS) then
if unsigned(R_CNT_CLKSER) = 60000000-1 then
R_FLG_CLKSER <= not R_FLG_CLKSER;
R_CNT_CLKSER <= (others=>'0');
else
R_CNT_CLKSER <= slv(unsigned(R_CNT_CLKSER) + 1);
end if;
end if;
end process proc_mon_clkser;
proc_mon_xx_clk: process (XX_CLK, I_BTN(3))
begin
if I_BTN(3) = '1' then
R_FLG_XX_CLK <= '1';
R_CNT_XX_CLK <= (others=>'0');
end if;
if rising_edge(XX_CLK) then
if unsigned(R_CNT_XX_CLK) = 40000000-1 then
R_FLG_XX_CLK <= not R_FLG_XX_CLK;
R_CNT_XX_CLK <= (others=>'0');
else
R_CNT_XX_CLK <= slv(unsigned(R_CNT_XX_CLK) + 1);
end if;
end if;
end process proc_mon_xx_clk;
RB_LAM(0) <= RB_LAM_TST;
-- LED group(0:3): rlink traffic
O_LED(0) <= SER_MONI.rxact;
O_LED(1) <= not SER_MONI.rxok;
O_LED(2) <= SER_MONI.txact;
O_LED(3) <= not SER_MONI.txok;
-- LED group(4:7) serious error conditions
O_LED(4) <= I_BTN(0) or not LOCKED;
O_LED(5) <= I_BTN(0);
O_LED(6) <= I_BTN(0) or MIG_UI_CLK_SYNC_RST;
O_LED(7) <= I_BTN(0) or not MIG_INIT_CALIB_COMPLETE;
-- LED group(8:11) for activity
O_LED(8) <= I_BTN(1);
O_LED(9) <= I_BTN(1);
O_LED(10) <= I_BTN(1) or not APP_RDY;
O_LED(11) <= I_BTN(1) or not APP_WDF_RDY;
-- LED group(12:15) for clock monitoring
O_LED(12) <= I_BTN(2) or R_FLG_XX_CLK;
O_LED(13) <= I_BTN(2) or R_FLG_CLKSER;
O_LED(14) <= I_BTN(2) or R_FLG_CLKREF;
O_LED(15) <= I_BTN(2) or R_FLG_UI_CLK;
-- RGB LEDs unused
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>'0');
-- 7 segment disp unused
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
end syn;
| gpl-3.0 |
wfjm/w11 | rtl/vlib/xlib/iob_reg_io_gen.vhd | 1 | 3657 | -- $Id: iob_reg_io_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2008 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_io_gen - syn
-- Description: Registered IOB, in/output, vector
--
-- Dependencies: iob_keeper_gen [sim only]
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2008-05-22 149 1.0.4 use internally TE to match OBUFT T polarity
-- 2008-05-22 148 1.0.3 remove UNISIM prim's; PULL implemented only for sim
-- 2008-05-18 147 1.0.2 add PULL generic, to enable PULL-UP,-DOWN or KEEPER
-- 2007-12-16 101 1.0.1 add INIT generic ports
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_io_gen is -- registered IOB, in/output, vector
generic (
DWIDTH : positive := 16; -- data port width
INITI : slbit := '0'; -- initial state ( in flop)
INITO : slbit := '0'; -- initial state (out flop)
INITE : slbit := '0'; -- initial state ( oe flop)
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
CLK : in slbit; -- clock
CEI : in slbit := '1'; -- clock enable ( in flops)
CEO : in slbit := '1'; -- clock enable (out flops)
OE : in slbit; -- output enable
DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end iob_reg_io_gen;
architecture syn of iob_reg_io_gen is
signal R_TE : slbit := not INITE;
signal R_DI : slv(DWIDTH-1 downto 0) := (others=>INITI);
signal R_DO : slv(DWIDTH-1 downto 0) := (others=>INITO);
constant all_z : slv(DWIDTH-1 downto 0) := (others=>'Z');
constant all_l : slv(DWIDTH-1 downto 0) := (others=>'L');
constant all_h : slv(DWIDTH-1 downto 0) := (others=>'H');
attribute iob : string;
attribute iob of R_TE : signal is "true";
attribute iob of R_DI : signal is "true";
attribute iob of R_DO : signal is "true";
begin
assert PULL="NONE" or PULL="UP" or PULL="DOWN" or PULL="KEEP"
report "assert(PULL): only NONE, UP, DOWN, OR KEEP supported"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_TE <= not OE;
if CEI = '1' then
R_DI <= to_x01(PAD);
end if;
if CEO = '1' then
R_DO <= DO;
end if;
end if;
end process proc_regs;
proc_comb: process (R_TE, R_DO)
begin
if R_TE = '1' then
PAD <= all_z;
else
PAD <= R_DO;
end if;
end process proc_comb;
DI <= R_DI;
-- Note: PULL (UP, DOWN or KEEP) is only implemented for simulation, not
-- for inference in synthesis. Use pin attributes in UCF's or XDC's
--
-- synthesis translate_off
PULL_UP: if PULL = "UP" generate
PAD <= all_h;
end generate PULL_UP;
PULL_DOWN: if PULL = "DOWN" generate
PAD <= all_l;
end generate PULL_DOWN;
PULL_KEEP: if PULL = "KEEP" generate
KEEPER : iob_keeper_gen
generic map (DWIDTH => DWIDTH)
port map (PAD => PAD);
end generate PULL_KEEP;
-- synthesis translate_on
end syn;
| gpl-3.0 |
andbet050197/IS773UTP | Registros/PISO.vhd | 1 | 593 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PISO is
Port ( SL : in STD_LOGIC;
clk : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (3 downto 0);
S : out STD_LOGIC);
end PISO;
architecture Behavioral of PISO is
signal aux : std_logic := '0';
begin
S <= aux;
process (clk , SL, A) is
variable temp : std_logic_vector (3 downto 0);
begin
if (SL='1') then
temp := A ;
elsif (rising_edge (clk)) then
aux <= temp(0);
temp := '0' & temp(3 downto 1);
end if;
end process;
end Behavioral;
| gpl-3.0 |
TierraDelFuego/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_Xilinx_Port/sha256_e1.vhd | 4 | 1129 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:53:21 06/02/2011
-- Design Name:
-- Module Name: sha256_e1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_e1 is
Port ( d : in STD_LOGIC_VECTOR (31 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0));
end sha256_e1;
architecture Behavioral of sha256_e1 is
begin
q <= (d(5 downto 0) & d(31 downto 6)) xor (d(10 downto 0) & d(31 downto 11)) xor (d(24 downto 0) & d(31 downto 25));
end Behavioral;
| gpl-3.0 |
andbet050197/IS773UTP | modulo1/Detectordepulso_TB.vhd | 1 | 2675 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:40:32 02/20/2017
-- Design Name:
-- Module Name: C:/ANDREStemp/LabElecDig/Detector_De_Pulso/Detectordepulso_TB.vhd
-- Project Name: Detector_De_Pulso
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Detectordepulso
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Detectordepulso_TB IS
END Detectordepulso_TB;
ARCHITECTURE behavior OF Detectordepulso_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Detectordepulso
PORT(
Button : IN std_logic;
Clk : IN std_logic;
S : OUT std_logic
);
END COMPONENT;
--Inputs
signal Button : std_logic := '0';
signal Clk : std_logic := '0';
--Outputs
signal S : std_logic;
-- Clock period definitions
constant Clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Detectordepulso PORT MAP (
Button => Button,
Clk => Clk,
S => S
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
Button <= '0';
wait for 190 ns;
Button <= '1';
wait for 20 ms;
Button <= '0';
wait for 20 ms;
Button <= '1';
wait for 20 ms;
Button <= '0';
wait for 20 ms;
Button <= '1';
wait for 130 ms;
Button <= '0';
wait for 200 ms;
Button <= '1';
wait for 20 ms;
Button <= '0';
wait for 20 ms;
Button <= '1';
wait for 20 ms;
Button <= '0';
wait for 20 ms;
Button <= '1';
wait for 200 ms;
Button <= '0';
wait for 10 ns;
wait for Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
TierraDelFuego/Open-Source-FPGA-Bitcoin-Miner | projects/VHDL_Xilinx_Port/sha256_pipeline.vhd | 4 | 3834 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:22:06 05/28/2011
-- Design Name:
-- Module Name: sha256_pipeline - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_pipeline is
generic ( DEPTH : integer );
Port ( clk : in STD_LOGIC;
step : in STD_LOGIC_VECTOR (5 downto 0);
state : in STD_LOGIC_VECTOR (255 downto 0);
input : in STD_LOGIC_VECTOR (511 downto 0);
hash : out STD_LOGIC_VECTOR (255 downto 0));
end sha256_pipeline;
architecture Behavioral of sha256_pipeline is
COMPONENT sha256_transform
PORT(
clk : IN std_logic;
w_in : IN std_logic_vector(511 downto 0);
s_in : IN std_logic_vector(255 downto 0);
w_out : OUT std_logic_vector(511 downto 0);
s_out : OUT std_logic_vector(255 downto 0);
k : IN std_logic_vector(31 downto 0)
);
END COMPONENT;
type k_array is array(integer range 0 to 63) of std_logic_vector(31 downto 0);
constant K : k_array := (
x"428a2f98", x"71374491", x"b5c0fbcf", x"e9b5dba5", x"3956c25b", x"59f111f1", x"923f82a4", x"ab1c5ed5",
x"d807aa98", x"12835b01", x"243185be", x"550c7dc3", x"72be5d74", x"80deb1fe", x"9bdc06a7", x"c19bf174",
x"e49b69c1", x"efbe4786", x"0fc19dc6", x"240ca1cc", x"2de92c6f", x"4a7484aa", x"5cb0a9dc", x"76f988da",
x"983e5152", x"a831c66d", x"b00327c8", x"bf597fc7", x"c6e00bf3", x"d5a79147", x"06ca6351", x"14292967",
x"27b70a85", x"2e1b2138", x"4d2c6dfc", x"53380d13", x"650a7354", x"766a0abb", x"81c2c92e", x"92722c85",
x"a2bfe8a1", x"a81a664b", x"c24b8b70", x"c76c51a3", x"d192e819", x"d6990624", x"f40e3585", x"106aa070",
x"19a4c116", x"1e376c08", x"2748774c", x"34b0bcb5", x"391c0cb3", x"4ed8aa4a", x"5b9cca4f", x"682e6ff3",
x"748f82ee", x"78a5636f", x"84c87814", x"8cc70208", x"90befffa", x"a4506ceb", x"bef9a3f7", x"c67178f2"
);
type w_array is array(integer range 0 to 64) of std_logic_vector(511 downto 0);
signal w : w_array;
type s_array is array(integer range 0 to 64) of std_logic_vector(255 downto 0);
signal s : s_array;
begin
w(0) <= input;
s(0) <= state;
hash(255 downto 224) <= state(255 downto 224) + s(2 ** DEPTH)(255 downto 224);
hash(223 downto 192) <= state(223 downto 192) + s(2 ** DEPTH)(223 downto 192);
hash(191 downto 160) <= state(191 downto 160) + s(2 ** DEPTH)(191 downto 160);
hash(159 downto 128) <= state(159 downto 128) + s(2 ** DEPTH)(159 downto 128);
hash(127 downto 96) <= state(127 downto 96) + s(2 ** DEPTH)(127 downto 96);
hash(95 downto 64) <= state(95 downto 64) + s(2 ** DEPTH)(95 downto 64);
hash(63 downto 32) <= state(63 downto 32) + s(2 ** DEPTH)(63 downto 32);
hash(31 downto 0) <= state(31 downto 0) + s(2 ** DEPTH)(31 downto 0);
rounds: for i in 0 to 2 ** DEPTH - 1 generate
signal round_k : std_logic_vector(31 downto 0);
signal round_w : std_logic_vector(511 downto 0);
signal round_s : std_logic_vector(255 downto 0);
begin
round_k <= K(i * 2 ** (6 - DEPTH) + conv_integer(step));
round_w <= w(i) when step = "000000" else w(i + 1);
round_s <= s(i) when step = "000000" else s(i + 1);
transform: sha256_transform
port map (
clk => clk,
w_in => round_w,
w_out => w(i + 1),
s_in => round_s,
s_out => s(i + 1),
k => round_k
);
end generate;
end Behavioral;
| gpl-3.0 |
andbet050197/IS773UTP | modulo3/Tx.vhd | 1 | 2014 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Tx is
Port ( Campana : in STD_LOGIC;
CLK : in STD_LOGIC;
Dato_entrada : in STD_LOGIC_VECTOR (7 downto 0);
Dato_salida : out STD_LOGIC);
end Tx;
architecture Behavioral of Tx is
COMPONENT Divisor
PORT(
clk : IN std_logic;
newC : OUT std_logic
);
END COMPONENT;
signal reloj_baudios : std_logic := '0';
signal estado : std_logic_vector(1 downto 0) := "00";
-- 00 -> Salida Idle
-- 01 -> Envio de dato
-- 10 -> Envio de bit de paridad
-- 11 -> Envio de bits de parada
signal contador_de_bits : std_logic_vector(3 downto 0) := "0000";
signal Paridad : std_logic := '0';
signal aux : std_logic := '1'; -- inicializar la salida en '1', en idle.
begin
Inst_Divisor: Divisor PORT MAP(
clk => CLK,
newC => reloj_baudios
);
Dato_salida <= aux;
process (CLK)
variable Dato_temporal : std_logic_vector(7 downto 0) := (others => '0');
begin
if (rising_edge(CLK) and reloj_baudios = '1') then
if (estado = "00") then
aux <= '1';
if (Campana = '1') then
Dato_temporal := Dato_entrada;
estado <= "01";
aux <= '0';
end if;
elsif (estado = "01") then
if (Dato_temporal(0) = '1') then
Paridad <= not Paridad;
end if;
aux <= Dato_temporal(0);
Dato_temporal := '0' & Dato_temporal(7 downto 1);
contador_de_bits <= contador_de_bits + 1;
if (contador_de_bits >= "0111") then
contador_de_bits <= (others => '0');
estado <= "10";
end if;
elsif (estado = "10") then
aux <= Paridad;
estado <= "11";
elsif (estado = "11") then
if (contador_de_bits = "0001") then
estado <= "00";
contador_de_bits <= (others => '0');
aux <= '1';
Paridad <= '0';
else
aux <= '1';
contador_de_bits <= contador_de_bits + 1;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
andbet050197/IS773UTP | modulo4/memoria_tb.vhd | 1 | 2008 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY memoria_tb IS
END memoria_tb;
ARCHITECTURE behavior OF memoria_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Memoria
PORT(
clk : IN std_logic;
lectura_escritura : IN std_logic;
habilitador : IN std_logic;
direccion : IN std_logic_vector(3 downto 0);
dato_entrada : IN std_logic_vector(2 downto 0);
dato_salida : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal lectura_escritura : std_logic := '0';
signal habilitador : std_logic := '0';
signal direccion : std_logic_vector(3 downto 0) := (others => '0');
signal dato_entrada : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal dato_salida : std_logic_vector(2 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Memoria PORT MAP (
clk => clk,
lectura_escritura => lectura_escritura,
habilitador => habilitador,
direccion => direccion,
dato_entrada => dato_entrada,
dato_salida => dato_salida
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
habilitador <= '1';
lectura_escritura <= '1'; -- Escritura
wait for 10 ns;
direccion <= "0000"; -- Guardando dato
dato_entrada <= "101";
wait for 30 ns;
direccion <= "0100"; -- Guardando dato
dato_entrada <= "001";
wait for 30 ns;
lectura_escritura <= '0'; -- Lectura
direccion <= "0000"; -- Leyendo dato
wait for 30 ns;
direccion <= "0100"; -- Leyendo dato
wait for 30 ns;
direccion <= "1111"; -- Leyendo de una posicion no asignada
wait;
end process;
END;
| gpl-3.0 |
andbet050197/IS773UTP | Registros/PISO_TB.vhd | 1 | 1180 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PISO_TB IS
END PISO_TB;
ARCHITECTURE behavior OF PISO_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PISO
PORT(
SL : IN std_logic;
clk : IN std_logic;
A : IN std_logic_vector(3 downto 0);
S : OUT std_logic
);
END COMPONENT;
--Inputs
signal SL : std_logic := '0';
signal clk : std_logic := '0';
signal A : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal S : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PISO PORT MAP (
SL => SL,
clk => clk,
A => A,
S => S
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
SL <= '1';
A <= "1011";
wait for 10 ns;
SL <= '0';
A <= "0000";
wait;
end process;
END;
| gpl-3.0 |
luccas641/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/cpu.vhd | 1 | 28019 | -- Processador Versao 3: 23/05/2013
-- Jeg e Ceg concertado!!
-- Video com 16 cores e tela de 40 colunas por 30 linhas
libraRY ieee;
use ieee.std_LOGIC_1164.all;
use ieee.std_LOGIC_ARITH.all;
use ieee.std_LOGIC_unsigned.all;
entity cpu is
port( clk : in std_LOGIC;
reset : in std_LOGIC;
Mem : in STD_LOGIC_VECTOR(15 downto 0);
M5 : out STD_LOGIC_VECTOR(15 downto 0);
M1 : out STD_LOGIC_VECTOR(15 downto 0);
RW : out std_LOGIC;
key : in STD_LOGIC_VECTOR(7 downto 0);
videoflag : out std_LOGIC;
vga_pos : out STD_LOGIC_VECTOR(15 downto 0);
vga_char : out STD_LOGIC_VECTOR(15 downto 0);
Ponto : out STD_LOGIC_VECTOR(2 downto 0);
halt_ack : out std_LOGIC;
halt_req : in std_LOGIC;
PC_data : out STD_LOGIC_VECTOR(15 downto 0);
break : out STD_LOGIC
);
end cpu;
ARCHITECTURE main of cpu is
TYPE STATES is (fetch, decode, exec, halted); -- Estados da Maquina de Controle do Processador
TYPE Registers is array(0 to 7) of STD_LOGIC_VECTOR(15 downto 0); -- Banco de Registradores
TYPE LoadRegisters is array(0 to 7) of std_LOGIC; -- Sinais de LOAD dos Registradores do Banco
-- INSTRUCTION SET: 29 INSTRUCTIONS
-- Data Manipulation Instructions: -- Usage -- Action -- Format
CONSTANT LOAD : STD_LOGIC_VECTOR(5 downto 0) := "110000"; -- LOAD RX END -- RX <- M[END] Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END
CONSTANT STORE : STD_LOGIC_VECTOR(5 downto 0) := "110001"; -- STORE END RX -- M[END] <- RX Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END
CONSTANT LOADIMED : STD_LOGIC_VECTOR(5 downto 0) := "111000"; -- LOADN RX Nr -- RX <- Nr Format: < inst(6) | RX(3) | xxxxxxb0 > + 16bit Numero
CONSTANT LOADINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111100"; -- LOADI RX RY -- RX <- M[RY] Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT STOREINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111101"; -- STOREI RX RY -- M[RX] <- RY Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT MOV : STD_LOGIC_VECTOR(5 downto 0) := "110011"; -- MOV RX RY -- RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 >
-- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 >
-- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 >
-- I/O Instructions:
CONSTANT OUTCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110010"; -- OUTCHAR RX RY -- Video[RY] <- Char(RX) Format: < inst(6) | RX(3) | RY(3) | xxxx >
-- RX contem o codigo do caracter de 0 a 127, sendo que 96 iniciais estao prontos com a tabela ASCII
-- RX(6 downto 0) + 32 = Caractere da tabela ASCII - Ver Manual PDF
-- RX(10 downto 7) = Cor : 0-branco, 1-marrom, 2-verde, 3-oliva, 4-azul marinho, 5-roxo, 6-teal, 7-prata, 8-cinza, 9-vermelho, 10-lima, 11-amarelo, 12-azul, 13-rosa, 14-aqua, 15-preto
-- RY(10 downto 0) = tamanho da tela = 30 linhas x 40 colunas: posicao continua de 0 a 1199 no RY
CONSTANT INCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110101"; -- INCHAR RX -- RX[5..0] <- KeyPressed RX[15..6] <- 0's Format: < inst(6) | RX(3) | xxxxxxx >
-- Se nao pressionar nenhuma tecla, RX recebe 00FF
CONSTANT ARITH : STD_LOGIC_VECTOR(1 downto 0) := "10";
-- Aritmethic Instructions(All should begin wiht "10"):
CONSTANT ADD : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- ADD RX RY RZ / ADDC RX RY RZ -- RX <- RY + RZ / RX <- RY + RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT SUB : STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- SUB RX RY RZ / SUBC RX RY RZ -- RX <- RY - RZ / RX <- RY - RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT MULT : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- MUL RX RY RZ / MUL RX RY RZ -- RX <- RY * RZ / RX <- RY * RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT DIV : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- DIV RX RY RZ -- RX <- RY / RZ / RX <- RY / RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT INC : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- INC RX / DEC RX -- RX <- RX + 1 / RX <- RX - 1 -- b6= INC/DEC : 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
CONSTANT LMOD : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- MOD RX RY RZ -- RX <- RY MOD RZ Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LOGIC : STD_LOGIC_VECTOR(1 downto 0) := "01";
-- LOGIC Instructions (All should begin wiht "01"):
CONSTANT LAND : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- AND RX RY RZ -- RZ <- RX AND RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LOR : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- OR RX RY RZ -- RZ <- RX OR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LXOR : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- XOR RX RY RZ -- RZ <- RX XOR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LNOT : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- NOT RX RY -- RX <- NOT(RY) Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT SHIFT : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- SHIFTL0 RX,n / SHIFTL1 RX,n / SHIFTR0 RX,n / SHIFTR1 RX,n / ROTL RX,n / ROTR RX,n
-- SHIFT/Rotate RX -- b6=shif/rotate: 0/1 b5=left/right: 0/1; b4=fill;
-- Format: < inst(6) | RX(3) | b6 b5 b4 | nnnn >
CONSTANT CMP : STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- CMP RX RY -- Compare RX and RY and set FR : Format: < inst(6) | RX(3) | RY(3) | xxxx > Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
-- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED)
-- FLOW CONTROL Instructions:
CONSTANT JMP : STD_LOGIC_VECTOR(5 downto 0) := "000010"; -- JMP END -- PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END
CONSTANT CALL : STD_LOGIC_VECTOR(5 downto 0) := "000011"; -- CALL END -- M[SP] <- PC | SP-- | PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END
CONSTANT RTS : STD_LOGIC_VECTOR(5 downto 0) := "000100"; -- RTS -- SP++ | PC <- M[SP] | b6=RX/FR: 1/0 Format: < inst(6) | xxxxxxxxxx >
CONSTANT PUSH : STD_LOGIC_VECTOR(5 downto 0) := "000101"; -- PUSH RX / PUSH FR -- M[SP] <- RX / M[SP] <- FR | SP-- : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
CONSTANT POP : STD_LOGIC_VECTOR(5 downto 0) := "000110"; -- POP RX / POP FR -- SP++ | RX <- M[SP] / FR <- M[SP] : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
-- Control Instructions:
CONSTANT NOP : STD_LOGIC_VECTOR(5 downto 0) := "000000"; -- NOP -- Do Nothing Format: < inst(6) | xxxxxxxxxx >
CONSTANT HALT : STD_LOGIC_VECTOR(5 downto 0) := "001111"; -- HALT -- StOP Here Format: < inst(6) | xxxxxxxxxx >
CONSTANT SETC : STD_LOGIC_VECTOR(5 downto 0) := "001000"; -- CLEARC / SETC -- Set/Clear CarRY: b9 = 1-set; 0-clear Format: < inst(6) | b9 | xxxxxxxxx >
CONSTANT BREAKP : STD_LOGIC_VECTOR(5 downto 0) := "001110"; -- BREAK POINT -- Switch to manual clock Format: < inst(6) | xxxxxxxxxx >
-- CONSTANTes para controle do Mux2: Estes sinais selecionam as respectivas entradas para o Mux2
CONSTANT sULA : STD_LOGIC_VECTOR (2 downto 0) := "000";
CONSTANT sMem : STD_LOGIC_VECTOR (2 downto 0) := "001";
CONSTANT sM4 : STD_LOGIC_VECTOR (2 downto 0) := "010";
CONSTANT sTECLADO : STD_LOGIC_VECTOR (2 downto 0) := "011"; -- nao tinha
CONSTANT sSP : STD_LOGIC_VECTOR (2 downto 0) := "100";
-- Sinais para o Processo da ULA
signal OP : STD_LOGIC_VECTOR(6 downto 0); -- OP(6) deve ser setado para OPeracoes com carRY
signal x, y, result : STD_LOGIC_VECTOR(15 downto 0);
signal FR : STD_LOGIC_VECTOR(15 downto 0); -- Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
signal auxFR : STD_LOGIC_VECTOR(15 downto 0); -- Representa um barramento conectando a ULA ao Mux6 para escrever no FR
begin
-- Maquina de Controle
process(clk, reset)
--Register Declaration:
variable PC : STD_LOGIC_VECTOR(15 downto 0); -- Program Counter
variable IR : STD_LOGIC_VECTOR(15 downto 0); -- Instruction Register
variable SP : STD_LOGIC_VECTOR(15 downto 0); -- Stack Pointer
variable MAR : STD_LOGIC_VECTOR(15 downto 0); -- Memory address Register
VARIABLE TECLADO :STD_LOGIC_VECTOR(15 downto 0); -- Registrador para receber dados do teclado -- nao tinha
variable reg : Registers;
-- Mux dos barramentos de dados internos
VARIABLE M2 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos barramentos de dados internos para os Registradores
VARIABLE M3, M4 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos Registradores para as entradas da ULA
-- Novos Sinais da Versao 2: Controle dos registradores internos (Load-Inc-Dec)
variable LoadReg : LoadRegisters;
variable LoadIR : std_LOGIC;
variable LoadMAR : std_LOGIC;
variable LoadPC : std_LOGIC;
variable IncPC : std_LOGIC;
VARIABLE LoadSP : STD_LOGIC;
variable IncSP : std_LOGIC;
variable DecSP : std_LOGIC;
-- Selecao dos Mux 2 e 6
variable selM2 : STD_LOGIC_VECTOR(2 downto 0);
variable selM6 : STD_LOGIC_VECTOR(2 downto 0);
VARIABLE BreakFlag : STD_LOGIC; -- Para sinalizar a mudanca para Clock manual/Clock Automatico para a nova instrucao Break
variable state : STATES; -- Estados do processador: fetch, decode, exec, halted
-- Seletores dos registradores para execussao das instrucoes
variable RX : integer;
variable RY : integer;
variable RZ : integer;
begin
if(reset = '1') then
state := fetch; -- inicializa o estado na busca!
M1(15 downto 0) <= x"0000"; -- inicializa na linha Zero da memoria -> Programa tem que comecar na linha Zero !!
videoflag <= '0';
RX := 0;
RY := 0;
RZ := 0;
RW <= '0';
LoadIR := '0';
LoadMAR := '0';
LoadPC := '0';
IncPC := '0';
IncSP := '0';
DecSP := '0';
selM2 := sMem;
selM6 := sULA;
LoadReg(0) := '0';
LoadReg(1) := '0';
LoadReg(2) := '0';
LoadReg(3) := '0';
LoadReg(4) := '0';
LoadReg(5) := '0';
LoadReg(6) := '0';
LoadReg(7) := '0';
REG(0) := x"0000";
REG(1) := x"0000";
REG(2) := x"0000";
REG(3) := x"0000";
REG(4) := x"0000";
REG(5) := x"0000";
REG(6) := x"0000";
REG(7) := x"0000";
PC := x"0000"; -- inicializa na linha Zero da memoria -> Programa tem que comecar na linha Zero !!
SP := x"3ffc"; -- Inicializa a Pilha no final da mem�ria: 7ffc
IR := x"0000";
MAR := x"0000";
BreakFlag:= '0'; -- Break Point Flag
BREAK <= '0'; -- Break Point output to switch to manual clock
-- Novo na Versao 3
HALT_ack <= '0';
elsif(clk'event and clk = '1') then
if(LoadIR = '1') then IR := Mem; end if;
if(LoadPC = '1') then PC := Mem; end if;
if(IncPC = '1') then PC := PC + x"0001"; end if;
if(LoadMAR = '1') then MAR := Mem; end if;
if(LoadSP = '1') then SP := M3; end if;
if(IncSP = '1') then SP := SP + x"0001"; end if;
if(DecSP = '1') then SP := SP - x"0001"; end if;
-- Selecao do Mux6
if (selM6 = sULA) THEN FR <= auxFR; -- Sempre recebe flags da ULA
ELSIF (selM6 = sMem) THEN FR <= Mem; END IF; -- A menos que seja POP FR, quando recebe da Memoria
-- Atualiza o nome dos registradores!!!
RX := conv_integer(IR(9 downto 7));
RY := conv_integer(IR(6 downto 4));
RZ := conv_integer(IR(3 downto 1));
-- Selecao do Mux2
if (selM2 = sULA) THEN M2 := RESULT;
ELSIF (selM2 = sMem) THEN M2 := Mem;
ELSIF (selM2 = sM4) THEN M2 := M4;
ELSIF (selM2 = sTECLADO)THEN M2 := TECLADO;
ELSIF (selM2 = sSP) THEN M2 := SP;
END IF;
-- Carrega dados do Mux 2 para os registradores
if(LoadReg(RX) = '1') then reg(RX) := M2; end if;
-- Reseta os sinais de controle APOS usa-los acima
-- Zera todos os sinais de controle, para depois ligar um por um nas instrucoes a medida que for necessario: a ultima atribuicao e' a que vale no processo!!!
LoadIR := '0';
LoadMAR := '0';
LoadPC := '0';
IncPC := '0';
IncSP := '0';
DecSP := '0';
LoadSP := '0';
selM6 := sULA; -- Sempre atualiza o FR da ULA, a nao ser que a instrucao seja POP FR
LoadReg(0) := '0';
LoadReg(1) := '0';
LoadReg(2) := '0';
LoadReg(3) := '0';
LoadReg(4) := '0';
LoadReg(5) := '0';
LoadReg(6) := '0';
LoadReg(7) := '0';
videoflag <= '0'; -- Abaixa o sinal para a "Placa de Video" : sobe a cada OUTCHAR
RW <= '0'; -- Sinal de Letura/Ecrita da mem�ria em Leitura
-- Novo na Versao 3
if(halt_req = '1') then state := halted; end if;
-- Novo na Versao 3: para escrever PC no LCD da placa
PC_data <= PC;
case state is
--************************************************************************
-- FETCH STATE
--************************************************************************
when fetch =>
PONTO <= "001";
-- Inicio das acoes do ciclo de Busca !!
M1 <= PC;
RW <= '0';
LoadIR := '1';
IncPC := '1';
STATE := decode;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- DECODE STATE
--************************************************************************
when decode =>
PONTO <= "010";
--========================================================================
-- INCHAR RX[7..0] <- KeyPressed RX[15..8] <- 0
--========================================================================
IF(IR(15 DOWNTO 10) = INCHAR) THEN -- Se nenhuma tecla for pressionada no momento da leitura, Rx <- x"00FF"
TECLADO(7 downto 0) := key(7 downto 0);
TECLADO(15 downto 8) := X"00";
selM2 := sTECLADO;
LoadReg(RX) := '1';
state := fetch;
END IF;
--========================================================================
-- OUTCHAR Video[RY] <- Char(RX)
--========================================================================
IF(IR(15 DOWNTO 10) = OUTCHAR) THEN
M3 := Reg(Rx); -- M3 <- Rx
M4 := Reg(Ry); -- M4 <- Ry
-- Este bloco troca a cor do preto pelo branco: agora a cor "0000" = Branco !
if( M3(11 downto 8) = "0000" ) then
M3(11 downto 8) := "1111";
elsif( M3(11 downto 8) = "1111" ) then
M3(11 downto 8) := "0000";
end if;
vga_char <= M3; --vga_char <= M3 : C�digo do Character vem do Rx via M3
vga_pos <= M4; -- Posicao na tela do Character vem do Ry via M4
videoflag <= '1'; -- Sobe o videoflag para gravar o charactere na mem�ria de video
state := fetch;
END IF;
--========================================================================
-- MOV RX/SP <- RY/SP
-- MOV RX RY RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 >
-- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 >
-- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 >
--========================================================================
IF(IR(15 DOWNTO 10) = MOV) THEN
state := fetch;
END IF;
--========================================================================
-- STORE DIReto M[END] <- RX
--========================================================================
IF(IR(15 DOWNTO 10) = STORE) THEN -- Busca o endereco
state := exec; -- Vai para o estado de Executa para gravar Registrador no endereco
END IF;
--========================================================================
-- STORE indexado por registrador M[RX] <- RY
--========================================================================
IF(IR(15 DOWNTO 10) = STOREINDEX) THEN
state := fetch;
END IF;
--========================================================================
-- LOAD Direto RX <- M[End]
--========================================================================
IF(IR(15 DOWNTO 10) = LOAD) THEN -- Busca o endereco
state := exec; -- Vai para o estado de Executa para buscar o dado do endereco
END IF;
--========================================================================
-- LOAD Imediato RX <- Nr
--========================================================================
IF(IR(15 DOWNTO 10) = LOADIMED) THEN
M1 <= PC; -- M1 <- PC
Rw <= '0'; -- Rw <= '0'
selM2 := sMeM; -- M2 <- MEM
LoadReg(RX) := '1'; -- LRx <- 1
IncPC := '1'; -- IncPC <- 1
state := fetch;
END IF;
--========================================================================
-- LOAD Indexado por registrador RX <- M(RY)
--========================================================================
IF(IR(15 DOWNTO 10) = LOADINDEX) THEN
state := fetch;
END IF;
--========================================================================
-- LOGIC OPERATION ('SHIFT', and 'CMP' NOT INCLUDED) RX <- RY (?) RZ
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) /= SHIFT AND IR(13 DOWNTO 10) /= CMP) THEN
state := fetch;
END IF;
--========================================================================
-- CMP RX, RY
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) = CMP) THEN
state := fetch;
END IF;
--========================================================================
-- SHIFT RX, RY RX <- SHIFT[ RY] ROTATE INCluded !
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC and (IR(13 DOWNTO 10) = SHIFT)) THEN
if(IR(6 DOWNTO 4) = "000") then -- SHIFT LEFT 0
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))sll conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 4) = "001") then -- SHIFT LEFT 1
Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))sll conv_integer(IR(3 DOWNTO 0))));
elsif(IR(6 DOWNTO 4) = "010") then -- SHIFT RIGHT 0
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))srl conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 4) = "011") then -- SHIFT RIGHT 0
Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))srl conv_integer(IR(3 DOWNTO 0))));
elsif(IR(6 DOWNTO 5) = "11") then -- ROTATE RIGHT
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))ror conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 5) = "10") then -- ROTATE LEFT
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))rol conv_integer(IR(3 DOWNTO 0)));
end if;
state := fetch;
end if;
--========================================================================
-- JMP END PC <- 16bit END : b9-b6 = COND
-- Flag Register: <...Negative|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
-- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED)
--========================================================================
IF(IR(15 DOWNTO 10) = JMP) THEN
state := fetch;
END IF;
--========================================================================
-- PUSH RX
--========================================================================
IF(IR(15 DOWNTO 10) = PUSH) THEN
state := fetch;
END IF;
--========================================================================
-- POP RX
--========================================================================
IF(IR(15 DOWNTO 10) = POP) THEN
state := exec;
END IF;
--========================================================================
-- CALL END PC <- 16bit END : b9-b6 = COND PUSH(PC)
-- Flag Register: <...Negative|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
-- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED)
--========================================================================
IF(IR(15 DOWNTO 10) = CALL) THEN
END IF;
--========================================================================
-- RTS PC <- Mem[SP]
--========================================================================
IF(IR(15 DOWNTO 10) = RTS) THEN
state := exec;
END IF;
--========================================================================
-- ARITH OPERATION ('INC' NOT INCLUDED) RX <- RY (?) RZ
--========================================================================
IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) /= INC) THEN
state := fetch;
END IF;
--========================================================================
-- INC/DEC RX <- RX (+ or -) 1
--========================================================================
IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) = INC) THEN
state := fetch;
END IF;
--========================================================================
-- NOP
--========================================================================
IF( IR(15 DOWNTO 10) = NOP) THEN
state := fetch;
end if;
--========================================================================
-- HALT
--========================================================================
IF( IR(15 DOWNTO 10) = HALT) THEN
state := halted;
END IF;
--========================================================================
-- SETC/CLEARC
--========================================================================
IF( IR(15 DOWNTO 10) = SETC) THEN
FR(4) <= IR(9); -- Bit 9 define se vai ser SET ou CLEAR
state := fetch;
end if;
--========================================================================
-- BREAKP
--========================================================================
IF( IR(15 DOWNTO 10) = BREAKP) THEN
BreakFlag := not(BreakFlag); -- Troca entre clock manual e clock autom�tico
BREAK <= BreakFlag;
state := fetch;
PONTO <= "101";
END IF;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- EXECUTE STATE
--************************************************************************
when exec =>
PONTO <= "100";
--========================================================================
-- EXEC STORE DIReto M[END] <- RX
--========================================================================
IF(IR(15 DOWNTO 10) = STORE) THEN
state := fetch;
END IF;
--========================================================================
-- EXEC LOAD DIReto RX <- M[END]
--========================================================================
IF(IR(15 DOWNTO 10) = LOAD) THEN
state := fetch;
END IF;
--========================================================================
-- EXEC POP RX/FR
--========================================================================
IF(IR(15 DOWNTO 10) = POP) THEN
state := fetch;
END IF;
--========================================================================
-- EXEC CALL Pilha <- PC e PC <- 16bit END :
--========================================================================
IF(IR(15 DOWNTO 10) = CALL) THEN
state := fetch;
END IF;
--========================================================================
-- EXEC RTS PC <- Mem[SP]
--========================================================================
IF(IR(15 DOWNTO 10) = RTS) THEN
state := fetch;
END IF;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- HALT STATE
--************************************************************************
WHEN halted =>
PONTO <= "111";
state := halted;
halt_ack <= '1';
WHEN OTHERS =>
state := fetch;
videoflag <= '0';
PONTO <= "000";
END CASE;
end if;
end process;
--************************************************************************
-- ULA ---> 3456 (3042)
--************************************************************************
PROCESS (OP, X, Y, reset)
VARIABLE AUX : STD_LOGIC_VECTOR(15 downto 0);
VARIABLE RESULT32 : STD_LOGIC_VECTOR(31 downto 0);
BEGIN
IF (reset = '1') THEN
auxFR <= x"0000";
RESULT <= x"0000";
else
auxFR <= FR;
--========================================================================
-- ARITH
--========================================================================
IF (OP (5 downto 4) = ARITH) THEN
CASE OP (3 downto 0) IS
WHEN ADD =>
IF (OP(6) = '1') THEN --Soma com carRY
AUX := X + Y + FR(4);
RESULT32 := (x"00000000" + X + Y + FR(4));
ELSE --Soma sem carRY
AUX := X + Y;
RESULT32 := (x"00000000" + X + Y);
end if;
if(RESULT32 > "01111111111111111") THEN -- CarRY
auxFR(4) <= '1';
ELSE
auxFR(4) <= '0';
end if;
WHEN SUB =>
AUX := X - Y;
WHEN MULT =>
RESULT32 := X * Y;
AUX := RESULT32(15 downto 0);
if(RESULT32 > x"0000FFFF") THEN -- ARITHmetic Overflow
auxFR(5) <= '1';
ELSE
auxFR(5) <= '0';
end if;
WHEN DIV =>
IF(Y = x"0000") THEN
AUX := x"0000";
auxFR(6) <= '1'; -- DIV by Zero
ELSE
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X)/CONV_INTEGER(Y), 16);
auxFR(6) <= '0';
END IF;
WHEN LMOD =>
IF(Y = x"0000") THEN
AUX := x"0000";
auxFR(6) <= '1'; -- DIV by Zero
ELSE
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X) mod CONV_INTEGER(Y), 16);
auxFR(6) <= '0';
END IF;
WHEN others => -- invalid operation, defaults to nothing
AUX := X;
END CASE;
if(AUX = x"0000") THEN
auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater>
ELSE
auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater>
end if;
if(AUX < x"0000") THEN -- NEGATIVO
auxFR(9) <= '1';
ELSE
auxFR(9) <= '0';
end if;
RESULT <= AUX;
ELSIF (OP (5 downto 4) = LOGIC) THEN
IF (OP (3 downto 0) = CMP) THEN
result <= x;
IF (x > y) THEN
auxFR(2 downto 0) <= "001"; -- FR = <...|zero|equal|lesser|greater>
ELSIF (x < y) THEN
auxFR(2 downto 0) <= "010"; -- FR = <...|zero|equal|lesser|greater>
ELSIF (x = y) THEN
auxFR(2 downto 0) <= "100"; -- FR = <...|zero|equal|lesser|greater>
END IF;
ELSE
CASE OP (3 downto 0) IS
WHEN LAND => result <= x and y;
WHEN LXOR => result <= x xor y;
WHEN LOR => result <= x or y;
WHEN LNOT => result <= not x;
WHEN others => -- invalid operation, defaults to nothing
RESULT <= X;
END CASE;
if(result = x"0000") THEN
auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater>
ELSE
auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater>
end if;
END IF;
END IF;
END IF; -- Reset
END PROCESS;
end main;
| gpl-3.0 |
luccas641/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/keyboard.vhd | 4 | 1566 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY keyboard IS
PORT( keyboard_clk, keyboard_data,
reset, read : IN STD_LOGIC;
scan_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
scan_ready : OUT STD_LOGIC);
END keyboard;
ARCHITECTURE a OF keyboard IS
SIGNAL INCNT : std_logic_vector(3 downto 0);
SIGNAL SHIFTIN : std_logic_vector(8 downto 0);
SIGNAL READ_CHAR : std_logic;
SIGNAL INFLAG, ready_set : std_logic;
SIGNAL filter : std_logic_vector(7 downto 0);
BEGIN
PROCESS (read, ready_set)
BEGIN
IF read = '1' THEN scan_ready <= '0';
ELSIF ready_set'EVENT and ready_set = '1' THEN
scan_ready <= '1';
END IF;
END PROCESS;
--This process reads in serial data coming from the terminal
PROCESS
BEGIN
WAIT UNTIL (KEYBOARD_CLK'EVENT AND KEYBOARD_CLK='1');
IF RESET='1' THEN
INCNT <= "0000";
READ_CHAR <= '0';
ELSE
IF KEYBOARD_DATA='0' AND READ_CHAR='0' THEN
READ_CHAR<= '1';
ready_set<= '0';
ELSE
-- Shift in next 8 data bits to assemble a scan code
IF READ_CHAR = '1' THEN
IF INCNT < "1001" THEN
INCNT <= INCNT + 1;
SHIFTIN(7 DOWNTO 0) <= SHIFTIN(8 DOWNTO 1);
SHIFTIN(8) <= KEYBOARD_DATA;
ready_set <= '0';
-- End of scan code character, so set flags and exit loop
ELSE
scan_code <= SHIFTIN(7 DOWNTO 0);
READ_CHAR <='0';
ready_set <= '1';
INCNT <= "0000";
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END a;
| gpl-3.0 |
kjellhar/fpga_mcu_main | src/vhdl/sd_spi/sd_spi_pkg.vhd | 1 | 664 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/05/2015 03:03:28 PM
-- Design Name:
-- Module Name: sd_spi_pkg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package SdSpi_pkg is
type CardType_t is (SD_CARD_E, SDHC_CARD_E); -- Define the different types of SD cards.
end package; | gpl-3.0 |
luccas641/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE115/hex_2_7seg.vhd | 2 | 3170 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY hex_2_7seg IS
PORT(
rst : in std_logic;
clk : in std_logic;
bus_dq : IN STD_LOGIC_VECTOR(15 downto 0);
bus_addr : in std_logic_vector(15 downto 0);
bus_req : in std_LOGIC;
bus_rw : in std_LOGIC;
HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX4 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX5 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX6 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
HEX7 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END hex_2_7seg;
ARCHITECTURE main OF hex_2_7seg IS
SIGNAL data0 : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
SIGNAL data1 : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
SIGNAL data2 : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
SIGNAL data3 : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
SIGNAL data4 : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
SIGNAL data5 : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
SIGNAL data6 : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
SIGNAL data7 : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
function hex2seg(hex : std_logic_vector(15 downto 0))
return std_logic_vector is
begin
CASE hex(3 downto 0) IS
WHEN "0000" =>
return "0111111";
WHEN "0001" =>
return "0000110";
WHEN "0010" =>
return "1011011";
WHEN "0011" =>
return "1001111";
WHEN "0100" =>
return "1100110";
WHEN "0101" =>
return "1101101";
WHEN "0110" =>
return "1111101";
WHEN "0111" =>
return "0000111";
WHEN "1000" =>
return "1111111";
WHEN "1001" =>
return "1101111";
WHEN "1010" =>
return "1110111";
WHEN "1011" =>
return "1111100";
WHEN "1100" =>
return "0111001";
WHEN "1101" =>
return "1011110";
WHEN "1110" =>
return "1111001";
WHEN "1111" =>
return "1110001";
WHEN OTHERS =>
return "1000000";
END CASE;
end hex2seg;
BEGIN
PROCESS(clk, rst)
BEGIN
if rst='1' then
data0 <= "0000000";
data1 <= "0000000";
data2 <= "0000000";
data3 <= "0000000";
data4 <= "0000000";
data5 <= "0000000";
data6 <= "0000000";
data7 <= "0000000";
elsif(rising_edge(clk)) then
if(bus_rw = '1' and bus_req= '1') then
case bus_addr is
when x"0970" =>
data0 <= hex2seg(bus_dq);
when x"0971" =>
data1 <= hex2seg(bus_dq);
when x"0972" =>
data2 <= hex2seg(bus_dq);
when x"0973" =>
data3 <= hex2seg(bus_dq);
when x"0974" =>
data4 <= hex2seg(bus_dq);
when x"0975" =>
data5 <= hex2seg(bus_dq);
when x"0976" =>
data6 <= hex2seg(bus_dq);
when x"0977" =>
data7 <= hex2seg(bus_dq);
when others =>
end case;
end if;
end if;
HEX0 <= NOT data0;
HEX1 <= NOT data1;
HEX2 <= NOT data2;
HEX3 <= NOT data3;
HEX4 <= NOT data4;
HEX5 <= NOT data5;
HEX6 <= NOT data6;
HEX7 <= NOT data7;
END PROCESS;
END main; | gpl-3.0 |
luccas641/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/vga_sync.vhd | 3 | 1626 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY VGA_SYNC IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
PIXELECT : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
HSYNC : OUT STD_LOGIC;
VSYNC : OUT STD_LOGIC;
VIDEO_EN : OUT STD_LOGIC;
STACK_EN : OUT STD_LOGIC
);
END VGA_SYNC;
ARCHITECTURE main OF VGA_SYNC IS
SIGNAL Hcnt : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL Vcnt : STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
PROCESS(CLK, RST)
BEGIN
IF(RST = '1') THEN
Hcnt <= "0000000000";
ELSIF(CLK'EVENT AND CLK = '1') THEN
IF(Hcnt = 799) THEN
Hcnt <= "0000000000";
ELSE
Hcnt <= Hcnt + 1;
END IF;
IF(Hcnt <= 755 AND Hcnt >= 659) THEN
HSYNC <= '0';
ELSE
HSYNC <= '1';
END IF;
END IF;
END PROCESS;
PROCESS(CLK, RST)
BEGIN
IF(RST = '1') THEN
Vcnt <= "0000000000";
ELSIF(CLK'EVENT AND CLK = '1') THEN
IF(Vcnt >= 524 AND Hcnt >= 699) THEN
Vcnt <= "0000000000";
ELSIF(Hcnt = 699) THEN
Vcnt <= Vcnt + 1;
END IF;
IF(Vcnt <= 494 AND Vcnt >= 493) THEN
VSYNC <= '0';
ELSE
VSYNC <= '1';
END IF;
END IF;
END PROCESS;
PROCESS(Hcnt, Vcnt)
BEGIN
IF(Hcnt <= 639 AND Vcnt <= 479) THEN
PIXELECT <= conv_std_logic_vector(conv_integer(Hcnt(9 DOWNTO 1)) + 320 * conv_integer(Vcnt(9 DOWNTO 1)), 17);
VIDEO_EN <= '1';
ELSE
PIXELECT <= "00000000000000000";
VIDEO_EN <= '0';
END IF;
END PROCESS;
PROCESS(CLK, RST)
BEGIN
IF(Hcnt > 640 AND Hcnt < 790 AND Vcnt > 480 AND Vcnt < 514) THEN
STACK_EN <= '1';
ELSE
STACK_EN <= '0';
END IF;
END PROCESS;
END main;
| gpl-3.0 |
hacklabmikkeli/knobs-galore | synthesizer_test.vhdl | 2 | 1014 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity synthesizer_test is
end entity;
architecture synthesizer_test_impl of synthesizer_test is
begin
end architecture;
| gpl-3.0 |
freecores/usb_fpga_2_13 | examples/usb-fpga-1.11/1.11b/lightshow/fpga/lightshow.vhd | 36 | 2235 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led : out std_logic_vector(11 downto 0);
CLK : in std_logic -- 32 MHz
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern is array(11 downto 0) of integer range 0 to 15;
signal pattern1 : tPattern := (0, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2, 1);
signal pattern2 : tPattern := (6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5);
signal pattern3 : tPattern := (0, 1, 4, 9, 4, 1, 0, 0, 0, 0, 0, 0);
type tXlatTable1 is array(0 to 12) of integer range 0 to 1023;
constant xt1 : tXlatTable1 := (0, 0, 1, 4, 13, 31, 64, 118, 202, 324, 493, 722, 1023);
type tXlatTable2 is array(0 to 9) of integer range 0 to 255;
--constant xt2 : tXlatTable2 := (0, 1, 11, 38, 90, 175, 303, 481, 718, 1023);
constant xt2 : tXlatTable2 := (0, 0, 3, 9, 22, 44, 76, 120, 179, 255);
signal cp1 : std_logic_vector(22 downto 0);
signal cp2 : std_logic_vector(22 downto 0);
signal cp3 : std_logic_vector(22 downto 0);
signal d : std_logic_vector(16 downto 0);
begin
dpCLK: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( cp1 = conv_std_logic_vector(3000000,23) )
then
pattern1(10 downto 0) <= pattern1(11 downto 1);
pattern1(11) <= pattern1(0);
cp1 <= (others => '0');
else
cp1 <= cp1 + 1;
end if;
if ( cp2 = conv_std_logic_vector(2200000,23) )
then
pattern2(10 downto 0) <= pattern2(11 downto 1);
pattern2(11) <= pattern2(0);
cp2 <= (others => '0');
else
cp2 <= cp2 + 1;
end if;
if ( cp3 = conv_std_logic_vector(1500000,23) )
then
pattern3(11 downto 1) <= pattern3(10 downto 0);
pattern3(0) <= pattern3(11);
cp3 <= (others => '0');
else
cp3 <= cp3 + 1;
end if;
if ( d = conv_std_logic_vector(1278*64-1,17) )
then
d <= (others => '0');
else
d <= d + 1;
end if;
for i in 0 to 11 loop
if ( d(16 downto 6) < conv_std_logic_vector( xt1(pattern1(i) + pattern2(i)) + xt2(pattern3(i)) ,11) )
then
led(i) <= '1';
else
led(i) <= '0';
end if;
end loop;
end if;
end process dpCLK;
end RTL;
| gpl-3.0 |
hacklabmikkeli/knobs-galore | voice_allocator_test.vhdl | 2 | 1026 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity voice_allocator_test is
end entity;
architecture voice_allocator_test_impl of voice_allocator_test is
begin
end architecture;
| gpl-3.0 |
freecores/usb_fpga_2_13 | examples/usb-fpga-2.16/2.16b/ucecho/fpga/ucecho.vhd | 4 | 2477 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk_in : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
signal clk : std_logic;
signal fxclk_fb : std_logic;
begin
-- PLL used as clock filter
fxclk_pll : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 10,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
CLKOUT0 => clk,
CLKFBOUT => fxclk_fb, -- 1-bit output: Feedback clock
CLKIN1 => fxclk_in, -- 1-bit input: Input clock
PWRDWN => '0', -- 1-bit input: Power-down
RST => '0', -- 1-bit input: Reset
CLKFBIN => fxclk_fb -- 1-bit input: Feedback clock
);
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pd >= 97 ) and ( pd <= 122)
then
pb_buf <= pd - 32;
else
pb_buf <= pd;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
| gpl-3.0 |
hacklabmikkeli/knobs-galore | preset_selector.vhdl | 2 | 5513 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity preset_selector is
port (EN: in std_logic
;CLK: in std_logic
;KEY_CODE: in keys_signal
;KEY_EVENT: in key_event_t
;PARAMS: out synthesis_params
);
end entity;
architecture preset_selector_impl of preset_selector is
subtype quantized_t is unsigned(2 downto 0);
function time_unquantize(quantized: quantized_t)
return ctl_signal is
begin
case quantized is
when "000" => return x"01";
when "001" => return x"02";
when "010" => return x"04";
when "011" => return x"08";
when "100" => return x"10";
when "101" => return x"20";
when "110" => return x"80";
when "111" => return x"F0";
when others => return x"FF";
end case;
end function;
function level_unquantize(quantized: quantized_t)
return ctl_signal is
begin
case quantized is
when "000" => return x"00";
when "001" => return x"20";
when "010" => return x"40";
when "011" => return x"60";
when "100" => return x"80";
when "101" => return x"A0";
when "110" => return x"C0";
when "111" => return x"E0";
when others => return x"FF";
end case;
end function;
signal mode: mode_t := mode_saw;
signal transform: voice_transform_t := voice_transform_none;
signal q_cutoff_base: quantized_t := "000";
signal q_cutoff_env: quantized_t := "111";
signal q_cutoff_attack: quantized_t := "111";
signal q_cutoff_decay: quantized_t := "000";
signal q_cutoff_sustain: quantized_t := "111";
signal q_cutoff_rel: quantized_t := "111";
signal q_gain_attack: quantized_t := "111";
signal q_gain_decay: quantized_t := "111";
signal q_gain_sustain: quantized_t := "111";
signal q_gain_rel: quantized_t := "111";
begin
process(CLK)
begin
if EN = '1' and rising_edge(CLK) then
if KEY_EVENT = key_event_make then
case KEY_CODE is
-- Preset editing
when "001100" => mode <= mode - 1;
when "001101" => mode <= mode + 1;
when "001001" => transform <= transform - 1;
when "001010" => transform <= transform + 1;
when "001111" => q_cutoff_base <= q_cutoff_base - 1;
when "001110" => q_cutoff_base <= q_cutoff_base + 1;
when "100010" => q_cutoff_env <= q_cutoff_env - 1;
when "001000" => q_cutoff_env <= q_cutoff_env + 1;
when "000010" => q_cutoff_attack <= q_cutoff_attack + 1;
when "000011" => q_cutoff_attack <= q_cutoff_attack - 1;
when "000001" => q_cutoff_decay <= q_cutoff_decay + 1;
when "000000" => q_cutoff_decay <= q_cutoff_decay - 1;
when "000111" => q_cutoff_sustain <= q_cutoff_sustain - 1;
when "000110" => q_cutoff_sustain <= q_cutoff_sustain + 1;
when "000101" => q_cutoff_rel <= q_cutoff_rel + 1;
when "000100" => q_cutoff_rel <= q_cutoff_rel - 1;
when "010000" => q_gain_attack <= q_gain_attack + 1;
when "010001" => q_gain_attack <= q_gain_attack - 1;
when "010010" => q_gain_decay <= q_gain_decay + 1;
when "010011" => q_gain_decay <= q_gain_decay - 1;
when "010111" => q_gain_sustain <= q_gain_sustain - 1;
when "010110" => q_gain_sustain <= q_gain_sustain + 1;
when "010101" => q_gain_rel <= q_gain_rel + 1;
when "010100" => q_gain_rel <= q_gain_rel - 1;
when others => null;
end case;
end if;
end if;
end process;
PARAMS <= (mode
,transform
,level_unquantize(q_cutoff_base)
,level_unquantize(q_cutoff_env)
,time_unquantize(q_cutoff_attack)
,time_unquantize(q_cutoff_decay)
,level_unquantize(q_cutoff_sustain)
,time_unquantize(q_cutoff_rel)
,time_unquantize(q_gain_attack)
,time_unquantize(q_gain_decay)
,level_unquantize(q_gain_sustain)
,time_unquantize(q_gain_rel)
);
end architecture;
| gpl-3.0 |
freecores/usb_fpga_2_13 | examples/usb-fpga-1.15/1.15d/intraffic/fpga/intraffic.vhd | 42 | 1939 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity intraffic is
port(
RESET : in std_logic;
CONT : in std_logic;
IFCLK : in std_logic;
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic
);
end intraffic;
architecture RTL of intraffic is
----------------------------
-- test pattern generator --
----------------------------
-- 30 bit counter
signal GEN_CNT : std_logic_vector(29 downto 0);
signal INT_CNT : std_logic_vector(6 downto 0);
signal FIFO_WORD : std_logic;
begin
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1'; -- no data alignment
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
INT_CNT <= ( others => '0' );
FIFO_WORD <= '0';
SLWR <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
if CONT = '1' or FLAGB = '1'
then
if FIFO_WORD = '0'
then
FD(14 downto 0) <= GEN_CNT(14 downto 0);
else
FD(14 downto 0) <= GEN_CNT(29 downto 15);
end if;
FD(15) <= FIFO_WORD;
if FIFO_WORD = '1'
then
GEN_CNT <= GEN_CNT + '1';
if INT_CNT = conv_std_logic_vector(99,7)
then
INT_CNT <= ( others => '0' );
else
INT_CNT <= INT_CNT + '1';
end if;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
if ( INT_CNT >= conv_std_logic_vector(90,7) ) and ( CONT = '0' )
then
SLWR <= '1';
else
SLWR <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
| gpl-3.0 |
AUT-CEIT/Arch101 | mux/mux_t.vhd | 1 | 864 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 26-02-2017
-- Module Name: mux_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mux_t is
end entity mux_t;
architecture arch_mux_t of mux_t is
component mux is
port (sel : in std_logic_vector(1 downto 0);
i : in std_logic_vector(3 downto 0);
o : out std_logic);
end component mux;
signal i : std_logic_vector(3 downto 0);
signal sel : std_logic_vector(1 downto 0);
signal o : std_logic;
for all:mux use entity work.mux(beh_arch_mux);
-- for all:mux use entity work.mux(seq_arch_mux);
begin
m : mux port map (sel, i, o);
i <= "1101";
sel <= "00", "10" after 100 ns;
end architecture arch_mux_t;
| gpl-3.0 |
AUT-CEIT/Arch101 | sample-rtl/datapath.vhd | 1 | 816 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 05-03-2017
-- Module Name: datapath.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity datapath is
port (register_load, register_shift : in std_logic;
clk : in std_logic;
register_out : out std_logic;
register_in : in std_logic_vector (3 downto 0));
end entity;
architecture rtl of datapath is
component four_register is
port (d : in std_logic_vector(3 downto 0);
clk, load, shift : in std_logic;
qout : out std_logic);
end component;
begin
r: four_register port map (register_in, clk, register_load, register_shift, register_out);
end architecture;
| gpl-3.0 |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/TBIM.vhd | 3 | 2345 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:51:54 09/27/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/Procesador/TBIM.vhd
-- Project Name: Procesador
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IM
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TBIM IS
END TBIM;
ARCHITECTURE behavior OF TBIM IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IM
PORT(
Address : IN std_logic_vector(31 downto 0);
Reset : IN std_logic;
Instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Address : std_logic_vector(31 downto 0) := (others => '0');
signal Reset : std_logic := '0';
--Outputs
signal Instruction : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IM PORT MAP (
Address => Address,
Reset => Reset,
Instruction => Instruction
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Address <= "00000000000000000000000000000000";
Reset <= '1';
wait for 100 ns;
Address <= "00000000000000000000000000000000";
Reset <= '0';
wait for 100 ns;
Address <= "00000000000000000000000000000001";
Reset <= '0';
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
Kalugy/Procesadorarquitectura | Segundoprocesador19oct/TBIM.vhd | 3 | 2345 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:51:54 09/27/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/Procesador/TBIM.vhd
-- Project Name: Procesador
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IM
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TBIM IS
END TBIM;
ARCHITECTURE behavior OF TBIM IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IM
PORT(
Address : IN std_logic_vector(31 downto 0);
Reset : IN std_logic;
Instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Address : std_logic_vector(31 downto 0) := (others => '0');
signal Reset : std_logic := '0';
--Outputs
signal Instruction : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IM PORT MAP (
Address => Address,
Reset => Reset,
Instruction => Instruction
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Address <= "00000000000000000000000000000000";
Reset <= '1';
wait for 100 ns;
Address <= "00000000000000000000000000000000";
Reset <= '0';
wait for 100 ns;
Address <= "00000000000000000000000000000001";
Reset <= '0';
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/Tbfirstpartnew.vhd | 2 | 2778 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:28:33 10/18/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/secondooooooooo/Tbfirstpartnew.vhd
-- Project Name: secondooooooooo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: firstrpart
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Tbfirstpartnew IS
END Tbfirstpartnew;
ARCHITECTURE behavior OF Tbfirstpartnew IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT firstrpart
PORT(
Resetext : IN std_logic;
Clkinext : IN std_logic;
Adressext : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Resetext : std_logic := '0';
signal Clkinext : std_logic := '0';
--Outputs
signal Adressext : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clkinext_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: firstrpart PORT MAP (
Resetext => Resetext,
Clkinext => Clkinext,
Adressext => Adressext
);
-- Clock process definitions
Clkinext_process :process
begin
Clkinext <= '0';
wait for Clkinext_period/2;
Clkinext <= '1';
wait for Clkinext_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Resetext <= '0';
wait for 100 ns;
Resetext <= '1';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
-- insert stimulus here
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
Kalugy/Procesadorarquitectura | Segmentado/Writeback.vhd | 1 | 1774 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:37:36 11/11/2017
-- Design Name:
-- Module Name: Writeback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Writeback is
Port ( datatomenin : in STD_LOGIC_VECTOR (31 downto 0);
aluresultin : in STD_LOGIC_VECTOR (31 downto 0);
pc : in STD_LOGIC_VECTOR (31 downto 0);
rfsourcein : in STD_LOGIC_VECTOR (1 downto 0);
datatoreg : out STD_LOGIC_VECTOR (31 downto 0));
end Writeback;
architecture Behavioral of Writeback is
COMPONENT MuxDM
PORT(
DataMem : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
RFSC : in STD_LOGIC_VECTOR (1 downto 0);
DWR : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
signal a999: std_logic_vector(31 downto 0);
begin ints_muxdatamemory: MuxDM PORT MAP(
DataMem => datatomenin,
AluResult => aluresultin,
PC => pc,
RFSC => rfsourcein,
DWR => a999
);
datatoreg<=a999;
end Behavioral;
| gpl-3.0 |
Kalugy/Procesadorarquitectura | Segmentado/Execute.vhd | 1 | 3794 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:00:50 11/11/2017
-- Design Name:
-- Module Name: Execute - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Execute is
Port ( callin : in STD_LOGIC_VECTOR (31 downto 0);
ifin : in STD_LOGIC_VECTOR (31 downto 0);
pcsourcein : in STD_LOGIC_VECTOR (1 downto 0);
aluopin : in STD_LOGIC_VECTOR (5 downto 0);
op1in : in STD_LOGIC_VECTOR (31 downto 0);
op2in : in STD_LOGIC_VECTOR (31 downto 0);
cwp : out STD_LOGIC;
ncwp : in STD_LOGIC;
icc : out STD_LOGIC_VECTOR (3 downto 0);
nextpc : out STD_LOGIC_VECTOR (31 downto 0);
aluresult : out STD_LOGIC_VECTOR (31 downto 0);
Clkinext : in STD_LOGIC;
Resetext : in STD_LOGIC);
end Execute;
architecture Behavioral of Execute is
COMPONENT ALU
PORT(
OPER1 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : in STD_LOGIC_VECTOR (31 downto 0);
c :in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT PSR
PORT(
nzvc : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC ;
cwp : out STD_LOGIC;
ncwp : in STD_LOGIC;
icc : out STD_LOGIC_VECTOR (3 downto 0);
rest : in STD_LOGIC;
c : out STD_LOGIC
);
END COMPONENT;
COMPONENT PSR_Modifier
PORT(
oper1 : in STD_LOGIC_VECTOR (31 downto 0);
oper2 : in STD_LOGIC_VECTOR (31 downto 0);
aluop : in STD_LOGIC_VECTOR (5 downto 0);
aluResult : in STD_LOGIC_VECTOR (31 downto 0);
conditionalCodes : out STD_LOGIC_VECTOR (3 downto 0)
);
END COMPONENT;
COMPONENT MuxPC
PORT(
Disp30 : in STD_LOGIC_VECTOR (31 downto 0);
Disp22 : in STD_LOGIC_VECTOR (31 downto 0);
PC1 : in STD_LOGIC_VECTOR (31 downto 0);
Direccion : in STD_LOGIC_VECTOR (31 downto 0);
Selector : in STD_LOGIC_VECTOR (1 downto 0);
Direccion_Out : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
signal a23: std_logic_vector(31 downto 0);
signal a29: STD_LOGIC;
signal a28: std_logic_vector(3 downto 0);
begin
ints_alu: ALU PORT MAP(
OPER1 => op1in,
OPER2 => op2in,
c =>a29,
ALURESULT => a23,
ALUOP => aluopin
);
aluresult<= a23;
ints_psr: PSR PORT MAP(
nzvc => a28,
clk => Clkinext,
cwp => cwp,
rest => Resetext,
ncwp => ncwp,
icc => icc,
c => a29
);
ints_psrmodifier: PSR_Modifier PORT MAP(
oper1 => op1in,
oper2 => op2in,
aluop => aluopin,
aluResult => a23,
conditionalCodes => a28
);
ints_muxPC: MuxPC PORT MAP(
Disp30 => callin,
Disp22 => ifin,
PC1 => "00000000000000000000000000000000",
Direccion => a23,
Selector => pcsourcein,
Direccion_Out => nextpc
);
end Behavioral;
| gpl-3.0 |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/DataMemory.vhd | 2 | 1298 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:19:25 10/20/2017
-- Design Name:
-- Module Name: DataMemory - tbDataMemory
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity DataMemory is
Port ( cRD : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
WRENMEM : in STD_LOGIC;
Reset : in STD_LOGIC;
DataMem : out STD_LOGIC_VECTOR (31 downto 0));
end DataMemory;
architecture Behavioral of DataMemory is
type reg is array (0 to 31) of std_logic_vector (31 downto 0);
signal myReg : reg := (others => x"00000000");
begin
process(cRD,AluResult,Reset,WRENMEM)
begin
if (Reset='1') then
DataMem <= x"00000000";
else
if (WRENMEM='1') then
myReg(conv_integer(AluResult(4 downto 0))) <= cRD;
else
DataMem <= myReg(conv_integer(AluResult(4 downto 0)));
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
Kalugy/Procesadorarquitectura | Segmentado/DataMemory.vhd | 2 | 1298 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:19:25 10/20/2017
-- Design Name:
-- Module Name: DataMemory - tbDataMemory
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity DataMemory is
Port ( cRD : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
WRENMEM : in STD_LOGIC;
Reset : in STD_LOGIC;
DataMem : out STD_LOGIC_VECTOR (31 downto 0));
end DataMemory;
architecture Behavioral of DataMemory is
type reg is array (0 to 31) of std_logic_vector (31 downto 0);
signal myReg : reg := (others => x"00000000");
begin
process(cRD,AluResult,Reset,WRENMEM)
begin
if (Reset='1') then
DataMem <= x"00000000";
else
if (WRENMEM='1') then
myReg(conv_integer(AluResult(4 downto 0))) <= cRD;
else
DataMem <= myReg(conv_integer(AluResult(4 downto 0)));
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/SEU.vhd | 4 | 1231 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:39:43 10/04/2017
-- Design Name:
-- Module Name: SEU - arqSEU
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SEU is
Port ( Instruction : in STD_LOGIC_VECTOR (31 downto 0);
OUTSEU : out STD_LOGIC_VECTOR (31 downto 0));
end SEU;
architecture arqSEU of SEU is
begin
process(Instruction)
begin
if(Instruction(12) = '1')then
OUTSEU<= "1111111111111111111" & Instruction(12 downto 0);
elsif(Instruction(12) = '0')then
OUTSEU<= "0000000000000000000" & Instruction(12 downto 0);
end if;
end process;
end arqSEU;
| gpl-3.0 |
Kalugy/Procesadorarquitectura | Segundoprocesador19oct/WindowsManager.vhd | 2 | 2607 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity WindowsManager is
Port ( cwp : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cwpout : out STD_LOGIC;
rs1out : out STD_LOGIC_VECTOR (5 downto 0);
rs2out : out STD_LOGIC_VECTOR (5 downto 0);
rdout : out STD_LOGIC_VECTOR (5 downto 0):=(others=>'0'));
end WindowsManager;
architecture Behavioral of WindowsManager is
signal int_rs1, int_rs2, int_rd : integer range 0 to 39 := 0;
begin
process(cwp,rs1,rs2,rd,op,op3)
begin
--guardar instruccion save
if (op = "10" and op3 = "111100") then
cwpout <= '0';
--reset instruction
elsif (op = "10" and op3 = "111101") then
cwpout <= '1';
end if;
--registros goli rs1
if (rs1 >= "11000" and rs1 <= "11111") then
int_rs1 <= conv_integer(rs1) - conv_integer(cwp) * 16; --input
elsif (rs1 >= "10000" and rs1 <= "10111") then
int_rs1 <= conv_integer(rs1) + conv_integer(cwp) * 16; --local
elsif (rs1 >= "01000" and rs1 <= "01111") then
int_rs1 <= conv_integer(rs1) + conv_integer(cwp) * 16; --output
elsif (rs1 >= "00000" and rs1 <= "00111") then
int_rs1 <= conv_integer(rs1); --global
end if;
--registros goli rs2
if (rs2 >= "11000" and rs2 <= "11111") then
int_rs2 <= conv_integer(rs2) - conv_integer(cwp) * 16; --input
elsif (rs2 >= "10000" and rs2 <= "10111") then
int_rs2 <= conv_integer(rs2) + conv_integer(cwp) * 16; --local
elsif (rs2 >= "01000" and rs2 <= "01111") then
int_rs2 <= conv_integer(rs2) + conv_integer(cwp) * 16; --output
elsif (rs2 >= "00000" and rs2 <= "00111") then
int_rs2 <= conv_integer(rs2); --global
end if;
--registros goli rd
if (rd >= "11000" and rd <= "11111") then
int_rd <= conv_integer(rd) - conv_integer(cwp) * 16; --input
elsif (rd >= "10000" and rd <= "10111") then
int_rd <= conv_integer(rd) + conv_integer(cwp) * 16; --local
elsif (rd >= "01000" and rd <= "01111") then
int_rd <= conv_integer(rd) + conv_integer(cwp) * 16; --output
elsif (rd >= "00000" and rd <= "00111") then
int_rd <= conv_integer(rd); --global
end if;
end process;
rs1out <= conv_std_logic_vector(int_rs1, 6);
rs2out <= conv_std_logic_vector(int_rs2, 6);
rdout <= conv_std_logic_vector(int_rd, 6);
end Behavioral; | gpl-3.0 |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/WindowsManager.vhd | 2 | 2607 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity WindowsManager is
Port ( cwp : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cwpout : out STD_LOGIC;
rs1out : out STD_LOGIC_VECTOR (5 downto 0);
rs2out : out STD_LOGIC_VECTOR (5 downto 0);
rdout : out STD_LOGIC_VECTOR (5 downto 0):=(others=>'0'));
end WindowsManager;
architecture Behavioral of WindowsManager is
signal int_rs1, int_rs2, int_rd : integer range 0 to 39 := 0;
begin
process(cwp,rs1,rs2,rd,op,op3)
begin
--guardar instruccion save
if (op = "10" and op3 = "111100") then
cwpout <= '0';
--reset instruction
elsif (op = "10" and op3 = "111101") then
cwpout <= '1';
end if;
--registros goli rs1
if (rs1 >= "11000" and rs1 <= "11111") then
int_rs1 <= conv_integer(rs1) - conv_integer(cwp) * 16; --input
elsif (rs1 >= "10000" and rs1 <= "10111") then
int_rs1 <= conv_integer(rs1) + conv_integer(cwp) * 16; --local
elsif (rs1 >= "01000" and rs1 <= "01111") then
int_rs1 <= conv_integer(rs1) + conv_integer(cwp) * 16; --output
elsif (rs1 >= "00000" and rs1 <= "00111") then
int_rs1 <= conv_integer(rs1); --global
end if;
--registros goli rs2
if (rs2 >= "11000" and rs2 <= "11111") then
int_rs2 <= conv_integer(rs2) - conv_integer(cwp) * 16; --input
elsif (rs2 >= "10000" and rs2 <= "10111") then
int_rs2 <= conv_integer(rs2) + conv_integer(cwp) * 16; --local
elsif (rs2 >= "01000" and rs2 <= "01111") then
int_rs2 <= conv_integer(rs2) + conv_integer(cwp) * 16; --output
elsif (rs2 >= "00000" and rs2 <= "00111") then
int_rs2 <= conv_integer(rs2); --global
end if;
--registros goli rd
if (rd >= "11000" and rd <= "11111") then
int_rd <= conv_integer(rd) - conv_integer(cwp) * 16; --input
elsif (rd >= "10000" and rd <= "10111") then
int_rd <= conv_integer(rd) + conv_integer(cwp) * 16; --local
elsif (rd >= "01000" and rd <= "01111") then
int_rd <= conv_integer(rd) + conv_integer(cwp) * 16; --output
elsif (rd >= "00000" and rd <= "00111") then
int_rd <= conv_integer(rd); --global
end if;
end process;
rs1out <= conv_std_logic_vector(int_rs1, 6);
rs2out <= conv_std_logic_vector(int_rs2, 6);
rdout <= conv_std_logic_vector(int_rd, 6);
end Behavioral; | gpl-3.0 |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/UnidadControl.vhd | 1 | 7392 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:49:14 10/20/2017
-- Design Name:
-- Module Name: UnidadControl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UnidadControl is
Port ( Op : in STD_LOGIC_VECTOR (1 downto 0);
Op2 : in STD_LOGIC_VECTOR (2 downto 0);
Op3 : in STD_LOGIC_VECTOR (5 downto 0);
icc: in STD_LOGIC_VECTOR (3 downto 0);
cond: in STD_LOGIC_VECTOR (3 downto 0);
rfDest : out STD_LOGIC;
rfSource : out STD_LOGIC_VECTOR (1 downto 0);
wrEnMem : out STD_LOGIC;
wrEnRF : out STD_LOGIC;
pcSource : out STD_LOGIC_VECTOR (1 downto 0);
AluOp : out STD_LOGIC_VECTOR (5 downto 0));
end UnidadControl;
architecture Behavioral of UnidadControl is
begin
process(Op, Op2, Op3, icc, cond)
begin
wrEnMem <= '0';
rfDest <= '0';
if(op = "01")then --CALL
rfDest <= '1';
rfSource <= "10";
wrEnRF <= '1';
pcSource <= "00";
AluOp <= "111111";
else
if(Op = "00")then
if(Op2 = "010")then
case cond is
when "1000" => --ba
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
when "1001" => --bne
if(not(icc(2)) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "0001" => --be
if(icc(2) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "1010" => --bg
if((not(icc(2) or (icc(3) xor icc(1)))) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "0010" => --ble
if((icc(2) or (icc(3) xor icc(1))) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <="111111";
else
rfSource <="01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "1011" => --bge
if((not(icc(3) xor icc(1))) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "0011" => --bl
if((icc(3) xor icc(1)) = '1')then --sacado de manual
rfSource <="01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <="01" ;
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when others =>
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end case;
else
if(Op2 = "100")then -- NOP
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
end if;
else
if(Op = "10")then
case Op3 is
when "000000" => --Add
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000000";
when "010000" => --Addcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010000";
when "001000" => --Addx
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "001000";
when "011000" => --Addxcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "011000";
when "000100" => --Sub
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000100";
when "010100" => --Subcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010100";
when "001100" => --Subx
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "001100";
when "011100" => --Subxcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "011100";
when "000001" => --And
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000001";
when "010001" => --Andcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010001";
when "000101" => --AndN
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000101";
when "010101" => --AndNcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010101";
when "000010" => --Or
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000010";
rfDest <= '0';
when "010010" => --Orcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010010";
when "000110" => --OrN
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000110";
when "010110" => --OrNcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010110";
when "000011" => --Xor
rfSource <= "01";
wrEnRF <='1' ;
pcSource <="10";
AluOp <= "000011";
when "010011" => --Xorcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010011";
when "111000" => -- JMPL
rfSource <= "10";
wrEnRF <= '1';
pcSource <="11";
AluOp <= "000000";
when "000111" => --XorN
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000111";
when "010111" => --XnorNcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010111";
when "111100" => -- SAVE
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000000";
when "111101" => -- RESTORE
rfSource <= "01";
wrEnRF <='1';
pcSource <="10";
AluOp <= "000000";
when others =>
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end case;
else
if(op = "11")then
case op3 is
when "000100" => -- STORE
rfSource <= "01"; -- leer
wrEnMem <= '1';
wrEnRF <= '0';
pcSource <="10";
AluOp <= "000000";
when "000000" => -- LOAD
rfSource <= "00"; --guardar
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000000";
when others =>
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
Kalugy/Procesadorarquitectura | Segmentado/tbfetchhhh.vhd | 1 | 3306 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:22:34 12/02/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/jummmmmmmm/tbfetchhhh.vhd
-- Project Name: jummmmmmmm
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fetch
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tbfetchhhh IS
END tbfetchhhh;
ARCHITECTURE behavior OF tbfetchhhh IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fetch
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
CUentrada : IN std_logic_vector(1 downto 0);
Entradain : IN std_logic_vector(31 downto 0);
Instruccionout : OUT std_logic_vector(31 downto 0);
PCout : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal CUentrada : std_logic_vector(1 downto 0) := (others => '0');
signal Entradain : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Instruccionout : std_logic_vector(31 downto 0);
signal PCout : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fetch PORT MAP (
Clk => Clk,
Reset => Reset,
CUentrada => CUentrada,
Entradain => Entradain,
Instruccionout => Instruccionout,
PCout => PCout
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000101";
wait for 100 ns;
Reset <= '1';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000101";
wait for 100 ns;
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000101";
wait for 100 ns;
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000101";
wait for 100 ns;
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000000";
wait for 100 ns;
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000001";
wait for 100 ns;
wait;
end process;
END;
| gpl-3.0 |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/PSR_Modifier.vhd | 3 | 2095 | ----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity PSR_Modifier is
Port ( oper1 : in STD_LOGIC_VECTOR (31 downto 0);
oper2 : in STD_LOGIC_VECTOR (31 downto 0);
aluop : in STD_LOGIC_VECTOR (5 downto 0);
aluResult : in STD_LOGIC_VECTOR (31 downto 0);
conditionalCodes : out STD_LOGIC_VECTOR (3 downto 0));
end PSR_Modifier;
architecture Behavioral of PSR_Modifier is
begin
process(aluop,oper1,oper2,aluResult)
begin
if (aluop="010001" or aluop="010101" or aluop="010010" or aluop="010110" or aluop="010011" or aluop="010111") then -- ANDcc,ANDNcc,ORcc,ORNcc,XORcc,XNORcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<= '0'; --V
conditionalCodes(0)<= '0'; --C
elsif (aluop="010000" or aluop="011000") then --ADDcc, ADDXcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<=(oper1(31) and oper2(31) and (not aluResult(31))) or ((not oper1(31)) and (not oper2(31)) and aluResult(31));
conditionalCodes(0)<=(oper1(31) and oper2(31)) or ((not aluResult(31)) and (oper1(31) or oper2(31)));
elsif (aluop="010100" or aluop="011100") then --SUBcc, SUBXcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<=(oper1(31) and (not oper2(31)) and (not aluResult(31))) or ((not oper1(31)) and oper2(31) and aluResult(31));
conditionalCodes(0)<=((not oper1(31)) and oper2(31)) or (aluResult(31) and ((not oper1(31)) or oper2(31)));
end if;
end process;
end Behavioral; | gpl-3.0 |
Kalugy/Procesadorarquitectura | Segmentado/MuxDM.vhd | 2 | 1427 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:33:41 10/20/2017
-- Design Name:
-- Module Name: MuxDM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MuxDM is
Port ( DataMem : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
RFSC : in STD_LOGIC_VECTOR (1 downto 0);
DWR : out STD_LOGIC_VECTOR (31 downto 0));
end MuxDM;
architecture Behavioral of MuxDM is
begin
process (DataMem,AluResult,PC,RFSC) begin
case (RFSC) is
when "00" =>
DWR <= DataMem;
when "01" =>
DWR <= AluResult;
when "10" =>
DWR <= PC;
when others =>
DWR <= AluResult;
end case;
end process;
end Behavioral;
| gpl-3.0 |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/MuxDM.vhd | 2 | 1427 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:33:41 10/20/2017
-- Design Name:
-- Module Name: MuxDM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MuxDM is
Port ( DataMem : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
RFSC : in STD_LOGIC_VECTOR (1 downto 0);
DWR : out STD_LOGIC_VECTOR (31 downto 0));
end MuxDM;
architecture Behavioral of MuxDM is
begin
process (DataMem,AluResult,PC,RFSC) begin
case (RFSC) is
when "00" =>
DWR <= DataMem;
when "01" =>
DWR <= AluResult;
when "10" =>
DWR <= PC;
when others =>
DWR <= AluResult;
end case;
end process;
end Behavioral;
| gpl-3.0 |
Kalugy/Procesadorarquitectura | Segmentado/fetch.vhd | 1 | 2926 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:40:53 11/09/2017
-- Design Name:
-- Module Name: fetch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fetch is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
CUentrada : in STD_LOGIC_VECTOR(1 downto 0);
Entradain : in STD_LOGIC_VECTOR (31 downto 0);
Instruccionout : out STD_LOGIC_VECTOR (31 downto 0);
PCout : out STD_LOGIC_VECTOR (31 downto 0));
end fetch;
architecture Behavioral of fetch is
COMPONENT Sumador32bit
PORT(
Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Result : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT PC
PORT(
inPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outPC : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT IM
PORT(
Address : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT Mux2
PORT(
Entrada : in STD_LOGIC_VECTOR (31 downto 0);
sumador : in STD_LOGIC_VECTOR (31 downto 0);
Cuentrada : in STD_LOGIC_VECTOR (1 downto 0);
posicion : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
signal a2,a3,a5,a35: std_logic_vector(31 downto 0);
begin
ints_NPC: PC PORT MAP(
inPC => a35,
Reset => Reset,
Clk => Clk,
outPC => a2
);
ints_PC: PC PORT MAP(
inPC => a2,
Reset => Reset,
Clk => Clk,
outPC => a5
);
PCout<=a5;
ints_sum: Sumador32bit PORT MAP(
Oper1 => a5,
Reset => Reset,
Oper2 =>"00000000000000000000000000000001",
Result => a3
);
ints_Mux2: Mux2 PORT MAP(
Entrada => Entradain,
sumador => a3,
Cuentrada => CUentrada,
posicion=> a35
);
ints_IM: IM PORT MAP(
Address => a5,
Reset => Reset,
Instruction =>Instruccionout
);
end Behavioral;
| gpl-3.0 |
makestuff/s3b_sdram | try1/memctrl/memctrl_pkg.vhdl | 1 | 1372 | --
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package memctrl_pkg is
component memctrl is
generic (
INIT_COUNT : unsigned(12 downto 0)
);
port(
-- Client interface
mcClk_in : in std_logic;
mcRDV_out : out std_logic;
-- SDRAM interface
ramRAS_out : out std_logic;
ramCAS_out : out std_logic;
ramWE_out : out std_logic;
ramAddr_out : out std_logic_vector(11 downto 0);
ramData_io : inout std_logic_vector(15 downto 0);
ramBank_out : out std_logic_vector(1 downto 0);
ramLDQM_out : out std_logic;
ramUDQM_out : out std_logic
);
end component;
end package;
| gpl-3.0 |
mmoraless/ecc_vhdl | F2mArithmetic/F2m_divider/MAIA/maia_wrapper_163.vhd | 1 | 2779 | ---------------------------------------------------------------------------------------------------
--
-- Title : GF2m_MoC
-- Design : someone
-- Author : Leumig
-- Company : INAOE
--
---------------------------------------------------------------------------------------------------
--
-- File : multiplier_wrapper.vhd
-- Generated : Thu May 18 12:06:43 2006
---------------------------------------------------------------------------------------------------
--
-- Description :
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity maia_163 is
generic(
-- Para el bloque in
SH_IN : positive := 29; -- 29, 23, 11, 5, :- bits que "faltan" para ser multiplo de 32
G_IN : positive := 32; -- 32, 32, 32, 32, :- Numero de palabra de entrada
ITR : positive := 6; -- 6, 8, 9, 9, :- No. de iteraciones en la máquina de estados
NUM_BITS : positive := 163 -- 163, 233, 277, 283, :- Orden del campo
);
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
w1 : in STD_LOGIC_VECTOR(31 downto 0);
v_data : out STD_LOGIC;
w3 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture behave of maia_163 is
-----------------------------------------------------------------------
-- conexion entre el inversor f2m y el modulo de entrada 1
signal donew1 : std_logic;
signal Ax : std_logic_vector(NUM_BITS-1 downto 0);
-----------------------------------------------------------------------
-- salidas del inversor F2m a la interface out.
signal rst_and : std_logic;
signal Cx_out : std_logic_vector(NUM_BITS-1 downto 0);
signal done_inv : std_logic;
begin
-----------------------------------------------------------------------
-- WORD_TO_FIELD 1
-----------------------------------------------------------------------
W2F1: ENTITY work.word_to_field(behave)
Generic Map (SH_IN, G_IN, ITR, NUM_BITS)
PORT MAP(w1, clk, rst, donew1, Ax);
-----------------------------------------------------------------------
-- El inversor
-----------------------------------------------------------------------
maiaGF2m_INV: entity work.inverter_maia_163(behave)
Generic map (NUM_BITS)
Port Map(Ax, clk, donew1, done_inv, Cx_out);
-----------------------------------------------------------------------
F2W: ENTITY work.field_to_word(behave)
Generic Map (SH_IN, G_IN, ITR, NUM_BITS)
PORT MAP(Cx_out, clk, done_inv, w3, v_data);
-----------------------------------------------------------------------
end behave;
| gpl-3.0 |
mmoraless/ecc_vhdl | F2mArithmetic/F2m_divider/Shantz/SingleFile/f2m_divider_571.vhd | 1 | 8920 | ---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_571 is
generic(
NUM_BITS : positive := 571
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
Ux : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_571 is
----------------------------------------------------------------------------------------------------
-- Signal for up-date regsiters A and B
signal A,B : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
--constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------------------------
-- control signals
signal a_greater_b, a_eq_b, A_par, B_par, U_par, V_par, u_mas_v_par: std_logic;
signal A_div_t, B_div_t, U_div_t, V_div_t : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M, v_mas_M, u_mas_v, u_mas_v_mas_M, a_mas_b : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M_div_t, v_mas_M_div_t, u_mas_v_div_t, u_mas_v_mas_M_div_t, a_mas_b_div_t: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, INIT, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Control signals
A_par <= '1' when A(0) = '0' else
'0';
B_par <= '1' when B(0) = '0' else
'0';
U_par <= '1' when U(0) = '0' else
'0';
V_par <= '1' when V(0) = '0' else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
----------------------------------------------------------------------------------------------------
-- Mux definitions
----------------------------------------------------------------------------------------------------
u_mas_M <= U xor F;
v_mas_M <= V xor F;
u_mas_v <= U xor V;
u_mas_v_mas_M <= u_mas_v xor F;
a_mas_b <= A xor B;
-- Muxes for A and B
a_div_t <= '0'& A(NUM_BITS downto 1);
b_div_t <= '0'& B(NUM_BITS downto 1);
u_div_t <= '0'& U(NUM_BITS downto 1);
v_div_t <= '0'& V(NUM_BITS downto 1);
u_mas_M_div_t <= '0' & u_mas_M(NUM_BITS downto 1);
v_mas_M_div_t <= '0' & v_mas_M(NUM_BITS downto 1);
u_mas_v_div_t <= '0' & u_mas_v(NUM_BITS downto 1);
u_mas_v_mas_M_div_t <= '0' & u_mas_v_mas_M(NUM_BITS downto 1);
a_mas_b_div_t <= '0' & a_mas_b(NUM_BITS downto 1);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= '0' & y;
B <= F;
U <= '0' & x;
v <= (others => '0');
Ux <= (others => '0');
done <= '0';
currentState <= CYCLE;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
Ux <= U(NUM_BITS-1 downto 0);
elsif A_par = '1' then
A <= A_div_t;
if U_par = '1' then
U <= U_div_t;
else
U <= u_mas_M_div_t;
end if;
elsif B_par = '1' then
B <= B_div_t;
if V_par = '1' then
V <= V_div_t;
else
V <= V_mas_M_div_t;
end if;
elsif a_greater_b = '1' then
A <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
U <= u_mas_v_div_t;
else
U <= u_mas_v_mas_M_div_t;
end if;
else
B <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
V <= u_mas_v_div_t;
else
V <= u_mas_v_mas_M_div_t;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave; | gpl-3.0 |
mmoraless/ecc_vhdl | F2mArithmetic/F2m_divider/MAIA/poly_grade.vhd | 1 | 3706 | ----------------------------------------------------------------------------------------------------
-- poly_grade.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: It calculates the grade of the input polynomial
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
----------------------------------------------------------------------------------------------------
entity grade is
port(
rst : in std_logic;
clk : in std_logic;
a : in std_logic_vector(163 downto 0);
done : out std_logic;
c : out std_logic_vector(7 downto 0)
);
end grade;
----------------------------------------------------------------------------------------------------
architecture grade of grade is
----------------------------------------------------------------------------------------------------
signal counter : std_logic_vector (7 downto 0); -- keeps the track of the grade
signal a_int : std_logic_vector(163 downto 0); -- register and shifter for the input a
signal a_shift : std_logic_vector(163 downto 0);
----------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, E0); -- the finite stte machine
signal State: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
c <= counter; -- Output
a_shift <= a_int(162 downto 0) & '0'; -- shift to lefts of the internal register for the input
----------------------------------------------------------------------------------------------------
-- Finite state machine for computing the grade of the input polynomial
----------------------------------------------------------------------------------------------------
GRADE_FST : process(clk)
begin
if CLK'event and CLK = '1' then
if (rst = '1')then -- synchronous resert signal, the input needs to be valid at the moment
a_int <= a;
counter <= "10100011"; -- NUM_BITS , in this case it is 163
Done <= '0';
State <= E0;
else
case State is
------------------------------------------------------------------------------
when E0 => -- The operation concludes when it founds the most significant bit of the input
if a_int(163) = '1' or counter = "00000000" then
done <= '1';
State <= END_STATE;
else
counter <= counter - 1;
a_int <= a_shift; -- Check out if the next bit of the input is '1'
end if;
------------------------------------------------------------------------------
when END_STATE => -- Do nothing, just wait the reset signal again
State <= END_STATE;
------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end; | gpl-3.0 |
mmoraless/ecc_vhdl | F2mArithmetic/F2m_Multiplication/Serial_Mul_Paar/multiplier_131_1.vhd | 1 | 17351 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- Con celda y sin maquina de estados
--------------------------------------------------------
-- x^131 + x^8 + x^3 + x^2 + 1
entity serial_multiplier_131 is
generic (
NUM_BITS : positive := 131 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_131;
-----------------------------------------------------------
architecture behave of serial_multiplier_131 is
-----------------------------------------------------------
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
signal done_int : std_logic;
--señales para las xor de la reduccion:
signal xor_1 : std_logic;
signal xor_2 : std_logic;
signal xor_3 : std_logic;
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
--type CurrentState_type is (NOTHING, END_STATE, MUL_STATE);
--signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
xor_1 <= Cx_int(1) xor Cx_int(NUM_BITS-1);
xor_2 <= Cx_int(2) xor Cx_int(NUM_BITS-1);
xor_3 <= Cx_int(7) xor Cx_int(NUM_BITS-1);
--Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position
bx_int <= Bx_shift;
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
CELL_0: ENTITY basic_cell(behave)
PORT MAP(Ax(0),Bx_int(NUM_BITS-1),Cx_int(NUM_BITS-1),clk,reset,Cx_int(0));
CELL_1: ENTITY basic_cell(behave)
PORT MAP(Ax(1),Bx_int(NUM_BITS-1),Cx_int(0),clk,reset,Cx_int(1));
CELL_2: ENTITY basic_cell(behave)
PORT MAP(Ax(2),Bx_int(NUM_BITS-1),xor_1,clk,reset,Cx_int(2));
CELL_3: ENTITY basic_cell(behave)
PORT MAP(Ax(3),Bx_int(NUM_BITS-1),xor_2,clk,reset,Cx_int(3));
CELL_4: ENTITY basic_cell(behave)
PORT MAP(Ax(4),Bx_int(NUM_BITS-1),Cx_int(3),clk,reset,Cx_int(4));
CELL_5: ENTITY basic_cell(behave)
PORT MAP(Ax(5),Bx_int(NUM_BITS-1),Cx_int(4),clk,reset,Cx_int(5));
CELL_6: ENTITY basic_cell(behave)
PORT MAP(Ax(6),Bx_int(NUM_BITS-1),Cx_int(5),clk,reset,Cx_int(6));
CELL_7: ENTITY basic_cell(behave)
PORT MAP(Ax(7),Bx_int(NUM_BITS-1),Cx_int(6),clk,reset,Cx_int(7));
CELL_8: ENTITY basic_cell(behave)
PORT MAP(Ax(8),Bx_int(NUM_BITS-1),xor_3,clk,reset,Cx_int(8));
CELL_9: ENTITY basic_cell(behave)
PORT MAP(Ax(9),Bx_int(NUM_BITS-1),Cx_int(8),clk,reset,Cx_int(9));
CELL_10: ENTITY basic_cell(behave)
PORT MAP(Ax(10),Bx_int(NUM_BITS-1),Cx_int(9),clk,reset,Cx_int(10));
CELL_11: ENTITY basic_cell(behave)
PORT MAP(Ax(11),Bx_int(NUM_BITS-1),Cx_int(10),clk,reset,Cx_int(11));
CELL_12: ENTITY basic_cell(behave)
PORT MAP(Ax(12),Bx_int(NUM_BITS-1),Cx_int(11),clk,reset,Cx_int(12));
CELL_13: ENTITY basic_cell(behave)
PORT MAP(Ax(13),Bx_int(NUM_BITS-1),Cx_int(12),clk,reset,Cx_int(13));
CELL_14: ENTITY basic_cell(behave)
PORT MAP(Ax(14),Bx_int(NUM_BITS-1),Cx_int(13),clk,reset,Cx_int(14));
CELL_15: ENTITY basic_cell(behave)
PORT MAP(Ax(15),Bx_int(NUM_BITS-1),Cx_int(14),clk,reset,Cx_int(15));
CELL_16: ENTITY basic_cell(behave)
PORT MAP(Ax(16),Bx_int(NUM_BITS-1),Cx_int(15),clk,reset,Cx_int(16));
CELL_17: ENTITY basic_cell(behave)
PORT MAP(Ax(17),Bx_int(NUM_BITS-1),Cx_int(16),clk,reset,Cx_int(17));
CELL_18: ENTITY basic_cell(behave)
PORT MAP(Ax(18),Bx_int(NUM_BITS-1),Cx_int(17),clk,reset,Cx_int(18));
CELL_19: ENTITY basic_cell(behave)
PORT MAP(Ax(19),Bx_int(NUM_BITS-1),Cx_int(18),clk,reset,Cx_int(19));
CELL_20: ENTITY basic_cell(behave)
PORT MAP(Ax(20),Bx_int(NUM_BITS-1),Cx_int(19),clk,reset,Cx_int(20));
CELL_21: ENTITY basic_cell(behave)
PORT MAP(Ax(21),Bx_int(NUM_BITS-1),Cx_int(20),clk,reset,Cx_int(21));
CELL_22: ENTITY basic_cell(behave)
PORT MAP(Ax(22),Bx_int(NUM_BITS-1),Cx_int(21),clk,reset,Cx_int(22));
CELL_23: ENTITY basic_cell(behave)
PORT MAP(Ax(23),Bx_int(NUM_BITS-1),Cx_int(22),clk,reset,Cx_int(23));
CELL_24: ENTITY basic_cell(behave)
PORT MAP(Ax(24),Bx_int(NUM_BITS-1),Cx_int(23),clk,reset,Cx_int(24));
CELL_25: ENTITY basic_cell(behave)
PORT MAP(Ax(25),Bx_int(NUM_BITS-1),Cx_int(24),clk,reset,Cx_int(25));
CELL_26: ENTITY basic_cell(behave)
PORT MAP(Ax(26),Bx_int(NUM_BITS-1),Cx_int(25),clk,reset,Cx_int(26));
CELL_27: ENTITY basic_cell(behave)
PORT MAP(Ax(27),Bx_int(NUM_BITS-1),Cx_int(26),clk,reset,Cx_int(27));
CELL_28: ENTITY basic_cell(behave)
PORT MAP(Ax(28),Bx_int(NUM_BITS-1),Cx_int(27),clk,reset,Cx_int(28));
CELL_29: ENTITY basic_cell(behave)
PORT MAP(Ax(29),Bx_int(NUM_BITS-1),Cx_int(28),clk,reset,Cx_int(29));
CELL_30: ENTITY basic_cell(behave)
PORT MAP(Ax(30),Bx_int(NUM_BITS-1),Cx_int(29),clk,reset,Cx_int(30));
CELL_31: ENTITY basic_cell(behave)
PORT MAP(Ax(31),Bx_int(NUM_BITS-1),Cx_int(30),clk,reset,Cx_int(31));
CELL_32: ENTITY basic_cell(behave)
PORT MAP(Ax(32),Bx_int(NUM_BITS-1),Cx_int(31),clk,reset,Cx_int(32));
CELL_33: ENTITY basic_cell(behave)
PORT MAP(Ax(33),Bx_int(NUM_BITS-1),Cx_int(32),clk,reset,Cx_int(33));
CELL_34: ENTITY basic_cell(behave)
PORT MAP(Ax(34),Bx_int(NUM_BITS-1),Cx_int(33),clk,reset,Cx_int(34));
CELL_35: ENTITY basic_cell(behave)
PORT MAP(Ax(35),Bx_int(NUM_BITS-1),Cx_int(34),clk,reset,Cx_int(35));
CELL_36: ENTITY basic_cell(behave)
PORT MAP(Ax(36),Bx_int(NUM_BITS-1),Cx_int(35),clk,reset,Cx_int(36));
CELL_37: ENTITY basic_cell(behave)
PORT MAP(Ax(37),Bx_int(NUM_BITS-1),Cx_int(36),clk,reset,Cx_int(37));
CELL_38: ENTITY basic_cell(behave)
PORT MAP(Ax(38),Bx_int(NUM_BITS-1),Cx_int(37),clk,reset,Cx_int(38));
CELL_39: ENTITY basic_cell(behave)
PORT MAP(Ax(39),Bx_int(NUM_BITS-1),Cx_int(38),clk,reset,Cx_int(39));
CELL_40: ENTITY basic_cell(behave)
PORT MAP(Ax(40),Bx_int(NUM_BITS-1),Cx_int(39),clk,reset,Cx_int(40));
CELL_41: ENTITY basic_cell(behave)
PORT MAP(Ax(41),Bx_int(NUM_BITS-1),Cx_int(40),clk,reset,Cx_int(41));
CELL_42: ENTITY basic_cell(behave)
PORT MAP(Ax(42),Bx_int(NUM_BITS-1),Cx_int(41),clk,reset,Cx_int(42));
CELL_43: ENTITY basic_cell(behave)
PORT MAP(Ax(43),Bx_int(NUM_BITS-1),Cx_int(42),clk,reset,Cx_int(43));
CELL_44: ENTITY basic_cell(behave)
PORT MAP(Ax(44),Bx_int(NUM_BITS-1),Cx_int(43),clk,reset,Cx_int(44));
CELL_45: ENTITY basic_cell(behave)
PORT MAP(Ax(45),Bx_int(NUM_BITS-1),Cx_int(44),clk,reset,Cx_int(45));
CELL_46: ENTITY basic_cell(behave)
PORT MAP(Ax(46),Bx_int(NUM_BITS-1),Cx_int(45),clk,reset,Cx_int(46));
CELL_47: ENTITY basic_cell(behave)
PORT MAP(Ax(47),Bx_int(NUM_BITS-1),Cx_int(46),clk,reset,Cx_int(47));
CELL_48: ENTITY basic_cell(behave)
PORT MAP(Ax(48),Bx_int(NUM_BITS-1),Cx_int(47),clk,reset,Cx_int(48));
CELL_49: ENTITY basic_cell(behave)
PORT MAP(Ax(49),Bx_int(NUM_BITS-1),Cx_int(48),clk,reset,Cx_int(49));
CELL_50: ENTITY basic_cell(behave)
PORT MAP(Ax(50),Bx_int(NUM_BITS-1),Cx_int(49),clk,reset,Cx_int(50));
CELL_51: ENTITY basic_cell(behave)
PORT MAP(Ax(51),Bx_int(NUM_BITS-1),Cx_int(50),clk,reset,Cx_int(51));
CELL_52: ENTITY basic_cell(behave)
PORT MAP(Ax(52),Bx_int(NUM_BITS-1),Cx_int(51),clk,reset,Cx_int(52));
CELL_53: ENTITY basic_cell(behave)
PORT MAP(Ax(53),Bx_int(NUM_BITS-1),Cx_int(52),clk,reset,Cx_int(53));
CELL_54: ENTITY basic_cell(behave)
PORT MAP(Ax(54),Bx_int(NUM_BITS-1),Cx_int(53),clk,reset,Cx_int(54));
CELL_55: ENTITY basic_cell(behave)
PORT MAP(Ax(55),Bx_int(NUM_BITS-1),Cx_int(54),clk,reset,Cx_int(55));
CELL_56: ENTITY basic_cell(behave)
PORT MAP(Ax(56),Bx_int(NUM_BITS-1),Cx_int(55),clk,reset,Cx_int(56));
CELL_57: ENTITY basic_cell(behave)
PORT MAP(Ax(57),Bx_int(NUM_BITS-1),Cx_int(56),clk,reset,Cx_int(57));
CELL_58: ENTITY basic_cell(behave)
PORT MAP(Ax(58),Bx_int(NUM_BITS-1),Cx_int(57),clk,reset,Cx_int(58));
CELL_59: ENTITY basic_cell(behave)
PORT MAP(Ax(59),Bx_int(NUM_BITS-1),Cx_int(58),clk,reset,Cx_int(59));
CELL_60: ENTITY basic_cell(behave)
PORT MAP(Ax(60),Bx_int(NUM_BITS-1),Cx_int(59),clk,reset,Cx_int(60));
CELL_61: ENTITY basic_cell(behave)
PORT MAP(Ax(61),Bx_int(NUM_BITS-1),Cx_int(60),clk,reset,Cx_int(61));
CELL_62: ENTITY basic_cell(behave)
PORT MAP(Ax(62),Bx_int(NUM_BITS-1),Cx_int(61),clk,reset,Cx_int(62));
CELL_63: ENTITY basic_cell(behave)
PORT MAP(Ax(63),Bx_int(NUM_BITS-1),Cx_int(62),clk,reset,Cx_int(63));
CELL_64: ENTITY basic_cell(behave)
PORT MAP(Ax(64),Bx_int(NUM_BITS-1),Cx_int(63),clk,reset,Cx_int(64));
CELL_65: ENTITY basic_cell(behave)
PORT MAP(Ax(65),Bx_int(NUM_BITS-1),Cx_int(64),clk,reset,Cx_int(65));
CELL_66: ENTITY basic_cell(behave)
PORT MAP(Ax(66),Bx_int(NUM_BITS-1),Cx_int(65),clk,reset,Cx_int(66));
CELL_67: ENTITY basic_cell(behave)
PORT MAP(Ax(67),Bx_int(NUM_BITS-1),Cx_int(66),clk,reset,Cx_int(67));
CELL_68: ENTITY basic_cell(behave)
PORT MAP(Ax(68),Bx_int(NUM_BITS-1),Cx_int(67),clk,reset,Cx_int(68));
CELL_69: ENTITY basic_cell(behave)
PORT MAP(Ax(69),Bx_int(NUM_BITS-1),Cx_int(68),clk,reset,Cx_int(69));
CELL_70: ENTITY basic_cell(behave)
PORT MAP(Ax(70),Bx_int(NUM_BITS-1),Cx_int(69),clk,reset,Cx_int(70));
CELL_71: ENTITY basic_cell(behave)
PORT MAP(Ax(71),Bx_int(NUM_BITS-1),Cx_int(70),clk,reset,Cx_int(71));
CELL_72: ENTITY basic_cell(behave)
PORT MAP(Ax(72),Bx_int(NUM_BITS-1),Cx_int(71),clk,reset,Cx_int(72));
CELL_73: ENTITY basic_cell(behave)
PORT MAP(Ax(73),Bx_int(NUM_BITS-1),Cx_int(72),clk,reset,Cx_int(73));
CELL_74: ENTITY basic_cell(behave)
PORT MAP(Ax(74),Bx_int(NUM_BITS-1),Cx_int(73),clk,reset,Cx_int(74));
CELL_75: ENTITY basic_cell(behave)
PORT MAP(Ax(75),Bx_int(NUM_BITS-1),Cx_int(74),clk,reset,Cx_int(75));
CELL_76: ENTITY basic_cell(behave)
PORT MAP(Ax(76),Bx_int(NUM_BITS-1),Cx_int(75),clk,reset,Cx_int(76));
CELL_77: ENTITY basic_cell(behave)
PORT MAP(Ax(77),Bx_int(NUM_BITS-1),Cx_int(76),clk,reset,Cx_int(77));
CELL_78: ENTITY basic_cell(behave)
PORT MAP(Ax(78),Bx_int(NUM_BITS-1),Cx_int(77),clk,reset,Cx_int(78));
CELL_79: ENTITY basic_cell(behave)
PORT MAP(Ax(79),Bx_int(NUM_BITS-1),Cx_int(78),clk,reset,Cx_int(79));
CELL_80: ENTITY basic_cell(behave)
PORT MAP(Ax(80),Bx_int(NUM_BITS-1),Cx_int(79),clk,reset,Cx_int(80));
CELL_81: ENTITY basic_cell(behave)
PORT MAP(Ax(81),Bx_int(NUM_BITS-1),Cx_int(80),clk,reset,Cx_int(81));
CELL_82: ENTITY basic_cell(behave)
PORT MAP(Ax(82),Bx_int(NUM_BITS-1),Cx_int(81),clk,reset,Cx_int(82));
CELL_83: ENTITY basic_cell(behave)
PORT MAP(Ax(83),Bx_int(NUM_BITS-1),Cx_int(82),clk,reset,Cx_int(83));
CELL_84: ENTITY basic_cell(behave)
PORT MAP(Ax(84),Bx_int(NUM_BITS-1),Cx_int(83),clk,reset,Cx_int(84));
CELL_85: ENTITY basic_cell(behave)
PORT MAP(Ax(85),Bx_int(NUM_BITS-1),Cx_int(84),clk,reset,Cx_int(85));
CELL_86: ENTITY basic_cell(behave)
PORT MAP(Ax(86),Bx_int(NUM_BITS-1),Cx_int(85),clk,reset,Cx_int(86));
CELL_87: ENTITY basic_cell(behave)
PORT MAP(Ax(87),Bx_int(NUM_BITS-1),Cx_int(86),clk,reset,Cx_int(87));
CELL_88: ENTITY basic_cell(behave)
PORT MAP(Ax(88),Bx_int(NUM_BITS-1),Cx_int(87),clk,reset,Cx_int(88));
CELL_89: ENTITY basic_cell(behave)
PORT MAP(Ax(89),Bx_int(NUM_BITS-1),Cx_int(88),clk,reset,Cx_int(89));
CELL_90: ENTITY basic_cell(behave)
PORT MAP(Ax(90),Bx_int(NUM_BITS-1),Cx_int(89),clk,reset,Cx_int(90));
CELL_91: ENTITY basic_cell(behave)
PORT MAP(Ax(91),Bx_int(NUM_BITS-1),Cx_int(90),clk,reset,Cx_int(91));
CELL_92: ENTITY basic_cell(behave)
PORT MAP(Ax(92),Bx_int(NUM_BITS-1),Cx_int(91),clk,reset,Cx_int(92));
CELL_93: ENTITY basic_cell(behave)
PORT MAP(Ax(93),Bx_int(NUM_BITS-1),Cx_int(92),clk,reset,Cx_int(93));
CELL_94: ENTITY basic_cell(behave)
PORT MAP(Ax(94),Bx_int(NUM_BITS-1),Cx_int(93),clk,reset,Cx_int(94));
CELL_95: ENTITY basic_cell(behave)
PORT MAP(Ax(95),Bx_int(NUM_BITS-1),Cx_int(94),clk,reset,Cx_int(95));
CELL_96: ENTITY basic_cell(behave)
PORT MAP(Ax(96),Bx_int(NUM_BITS-1),Cx_int(95),clk,reset,Cx_int(96));
CELL_97: ENTITY basic_cell(behave)
PORT MAP(Ax(97),Bx_int(NUM_BITS-1),Cx_int(96),clk,reset,Cx_int(97));
CELL_98: ENTITY basic_cell(behave)
PORT MAP(Ax(98),Bx_int(NUM_BITS-1),Cx_int(97),clk,reset,Cx_int(98));
CELL_99: ENTITY basic_cell(behave)
PORT MAP(Ax(99),Bx_int(NUM_BITS-1),Cx_int(98),clk,reset,Cx_int(99));
CELL_100: ENTITY basic_cell(behave)
PORT MAP(Ax(100),Bx_int(NUM_BITS-1),Cx_int(99),clk,reset,Cx_int(100));
CELL_101: ENTITY basic_cell(behave)
PORT MAP(Ax(101),Bx_int(NUM_BITS-1),Cx_int(100),clk,reset,Cx_int(101));
CELL_102: ENTITY basic_cell(behave)
PORT MAP(Ax(102),Bx_int(NUM_BITS-1),Cx_int(101),clk,reset,Cx_int(102));
CELL_103: ENTITY basic_cell(behave)
PORT MAP(Ax(103),Bx_int(NUM_BITS-1),Cx_int(102),clk,reset,Cx_int(103));
CELL_104: ENTITY basic_cell(behave)
PORT MAP(Ax(104),Bx_int(NUM_BITS-1),Cx_int(103),clk,reset,Cx_int(104));
CELL_105: ENTITY basic_cell(behave)
PORT MAP(Ax(105),Bx_int(NUM_BITS-1),Cx_int(104),clk,reset,Cx_int(105));
CELL_106: ENTITY basic_cell(behave)
PORT MAP(Ax(106),Bx_int(NUM_BITS-1),Cx_int(105),clk,reset,Cx_int(106));
CELL_107: ENTITY basic_cell(behave)
PORT MAP(Ax(107),Bx_int(NUM_BITS-1),Cx_int(106),clk,reset,Cx_int(107));
CELL_108: ENTITY basic_cell(behave)
PORT MAP(Ax(108),Bx_int(NUM_BITS-1),Cx_int(107),clk,reset,Cx_int(108));
CELL_109: ENTITY basic_cell(behave)
PORT MAP(Ax(109),Bx_int(NUM_BITS-1),Cx_int(108),clk,reset,Cx_int(109));
CELL_110: ENTITY basic_cell(behave)
PORT MAP(Ax(110),Bx_int(NUM_BITS-1),Cx_int(109),clk,reset,Cx_int(110));
CELL_111: ENTITY basic_cell(behave)
PORT MAP(Ax(111),Bx_int(NUM_BITS-1),Cx_int(110),clk,reset,Cx_int(111));
CELL_112: ENTITY basic_cell(behave)
PORT MAP(Ax(112),Bx_int(NUM_BITS-1),Cx_int(111),clk,reset,Cx_int(112));
CELL_113: ENTITY basic_cell(behave)
PORT MAP(Ax(113),Bx_int(NUM_BITS-1),Cx_int(112),clk,reset,Cx_int(113));
CELL_114: ENTITY basic_cell(behave)
PORT MAP(Ax(114),Bx_int(NUM_BITS-1),Cx_int(113),clk,reset,Cx_int(114));
CELL_115: ENTITY basic_cell(behave)
PORT MAP(Ax(115),Bx_int(NUM_BITS-1),Cx_int(114),clk,reset,Cx_int(115));
CELL_116: ENTITY basic_cell(behave)
PORT MAP(Ax(116),Bx_int(NUM_BITS-1),Cx_int(115),clk,reset,Cx_int(116));
CELL_117: ENTITY basic_cell(behave)
PORT MAP(Ax(117),Bx_int(NUM_BITS-1),Cx_int(116),clk,reset,Cx_int(117));
CELL_118: ENTITY basic_cell(behave)
PORT MAP(Ax(118),Bx_int(NUM_BITS-1),Cx_int(117),clk,reset,Cx_int(118));
CELL_119: ENTITY basic_cell(behave)
PORT MAP(Ax(119),Bx_int(NUM_BITS-1),Cx_int(118),clk,reset,Cx_int(119));
CELL_120: ENTITY basic_cell(behave)
PORT MAP(Ax(120),Bx_int(NUM_BITS-1),Cx_int(119),clk,reset,Cx_int(120));
CELL_121: ENTITY basic_cell(behave)
PORT MAP(Ax(121),Bx_int(NUM_BITS-1),Cx_int(120),clk,reset,Cx_int(121));
CELL_122: ENTITY basic_cell(behave)
PORT MAP(Ax(122),Bx_int(NUM_BITS-1),Cx_int(121),clk,reset,Cx_int(122));
CELL_123: ENTITY basic_cell(behave)
PORT MAP(Ax(123),Bx_int(NUM_BITS-1),Cx_int(122),clk,reset,Cx_int(123));
CELL_124: ENTITY basic_cell(behave)
PORT MAP(Ax(124),Bx_int(NUM_BITS-1),Cx_int(123),clk,reset,Cx_int(124));
CELL_125: ENTITY basic_cell(behave)
PORT MAP(Ax(125),Bx_int(NUM_BITS-1),Cx_int(124),clk,reset,Cx_int(125));
CELL_126: ENTITY basic_cell(behave)
PORT MAP(Ax(126),Bx_int(NUM_BITS-1),Cx_int(125),clk,reset,Cx_int(126));
CELL_127: ENTITY basic_cell(behave)
PORT MAP(Ax(127),Bx_int(NUM_BITS-1),Cx_int(126),clk,reset,Cx_int(127));
CELL_128: ENTITY basic_cell(behave)
PORT MAP(Ax(128),Bx_int(NUM_BITS-1),Cx_int(127),clk,reset,Cx_int(128));
CELL_129: ENTITY basic_cell(behave)
PORT MAP(Ax(129),Bx_int(NUM_BITS-1),Cx_int(128),clk,reset,Cx_int(129));
CELL_130: ENTITY basic_cell(behave)
PORT MAP(Ax(130),Bx_int(NUM_BITS-1),Cx_int(129),clk,reset,Cx_int(130));
done <= done_int;
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "10000011"; -- m value, in this case, it is 112, be sure to set the correct value
cx <= (others => '0');
Done_int <= '0';
else
if counter = "0000000" then -- The done signal is asserted at the same time that the result is computed.
if (done_int = '0') then
done_int <= '1';
Cx <= Cx_int;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
SHIFT_REGISTER: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
Bx_shift <= Bx;
else
Bx_shift <= Bx_shift(NUM_BITS-2 downto 0) & '0'; -- carga paralela
end if;
end if;
end process;
end behave;
| gpl-3.0 |
mmoraless/ecc_vhdl | F2mArithmetic/F2m_divider/Guerric/SingleFile/guerric_divider_1.vhd | 1 | 5908 | ---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Different to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_163 is
generic(
NUM_BITS : positive := 163
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_163 is
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
----------------------------------------------------------------------------------------------------
-- control signals
signal en_VS, C_0, C_3, ISPos: std_logic;
signal V, S, to_V, to_S : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, R, to_U, to_R : STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- Internal registers
signal u_div_2, v_div_2, r_div_2, s_div_2, p_div_2, op1: STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- Internal registers
signal D: STD_LOGIC_VECTOR(3 downto 0); -- Internal registers
signal counter: STD_LOGIC_VECTOR(8 downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, LOAD2, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
U_div_2 <= '0' & U(NUM_BITS-1 downto 1);
R_div_2 <= '0' & R(NUM_BITS-1 downto 1);
P_div_2 <= p(NUM_BITS downto 1);
S_div_2 <= S(NUM_BITS downto 1);
V_div_2 <= V(NUM_BITS downto 1);
to_U <= U_div_2 xor V_div_2 when c_0 = '1' else
U_div_2;
op1 <= R_div_2 xor P_div_2 when c_3 = '1' else
R_div_2;
to_R <= op1 xor S_div_2 when c_0 = '1' else
op1;
to_V <= Y & '0' when rst = '1' else
p when CurrentState = LOAD1 else
'0' & U;
to_S <= X & '0' when rst = '1' else
(others => '0') when CurrentState = LOAD1 else
'0' & R;
en_VS <= '1' when rst = '1' or CurrentState = LOAD1 or (U(0) = '1' and IsPos = '0') else
'0';
c_0 <= '1' when CurrentState = LOAD1 or U(0) = '1' else
'0';
c_3 <= '0' when (CurrentState = LOAD1 or R(0) = '0') else
'1';
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
R <= (others => '0');
U <= (others => '0');
x_div_y <= (others => '0');
if en_VS = '1' then
V <= to_V;
S <= to_S;
end if;
done <= '0';
counter <= "101000110"; --2*m - 2
IsPos <= '0';
D <= "0001";
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
R <= to_R;
U <= to_U;
if en_VS = '1' then
V <= to_V;
S <= to_S;
end if;
currentState <= Cycle;
when CYCLE =>
counter <= counter - 1;
R <= to_R;
U <= to_U;
if en_VS = '1' then
V <= to_V;
S <= to_S;
end if;
if U(0) = '0' then
if IsPos = '0' then D <= D + 1;
elsif D = "0000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
elsif IsPos = '1' then
if D = "0000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
else
D <= D - 1;
IsPos <= '1';
end if;
if counter = "000000000" then
done <= '1';
x_div_y <= S(NUM_BITS-1 downto 0);
CurrentState <= END_STATE;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave; | gpl-3.0 |
mmoraless/ecc_vhdl | F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_571.vhd | 1 | 5088 | ----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_571 is
generic (
NUM_BITS : positive := 571 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_571;
-----------------------------------------------------------
architecture behave of serial_multiplier_571 is
-----------------------------------------------------------
-- m = 571 x571 + x10 + x5 + x2 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(9 downto 0); -- 8-bit counter, controling the number of iterations: m
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "1000111010"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
if counter = "0000000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
Done <= '1';
else
bx_int <= bx_shift;
end if;
when END_STATE =>
CurrentState <= END_STATE;
Done <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
| gpl-3.0 |
mmoraless/ecc_vhdl | F2mArithmetic/F2m_divider/Gura/Modular/celda_V.vhd | 1 | 1242 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_V is
generic(
NUM_BITS : positive := 163
);
port(
R : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
X2 : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c_1 : in STD_LOGIC;
c_2 : in STD_LOGIC;
toV : out STD_LOGIC_VECTOR(NUM_BITS downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_V is
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
toV <= X2 when c_1 = '0' and c_2 = '0' else
(others => '0') when c_1 = '0' and c_2 = '1' else
R;
end behave; | gpl-3.0 |
mmoraless/ecc_vhdl | F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_163_2.vhd | 1 | 4150 | ----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
-- FSM are not used.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_163 is
generic (
NUM_BITS : positive := 163 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_163;
-----------------------------------------------------------
architecture behave of serial_multiplier_163 is
-----------------------------------------------------------
-- m = 163 x163 + x7 + x6 + x3 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
signal done_int : std_logic;
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
done <= done_int;
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "10100010"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done_int <= '0';
else
if done_int = '0' then
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
bx_int <= bx_shift;
if counter = "00000000" then -- The done signal is asserted at the same time that the result is computed.
Done_int <= '1';
end if;
end if;
end if;
end if;
end process;
end behave;
| gpl-3.0 |
mmoraless/ecc_vhdl | F2mArithmetic/F2m_divider/Shantz/SingleFile/f2m_divider_163.vhd | 1 | 8941 | ---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_163 is
generic(
NUM_BITS : positive := 163
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_163 is
----------------------------------------------------------------------------------------------------
-- Signal for up-date regsiters A and B
signal A,B : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------------------------
-- control signals
signal a_greater_b, a_eq_b, A_par, B_par, U_par, V_par, u_mas_v_par: std_logic;
signal A_div_t, B_div_t, U_div_t, V_div_t : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M, v_mas_M, u_mas_v, u_mas_v_mas_M, a_mas_b : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M_div_t, v_mas_M_div_t, u_mas_v_div_t, u_mas_v_mas_M_div_t, a_mas_b_div_t: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Control signals
A_par <= '1' when A(0) = '0' else
'0';
B_par <= '1' when B(0) = '0' else
'0';
U_par <= '1' when U(0) = '0' else
'0';
V_par <= '1' when V(0) = '0' else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
----------------------------------------------------------------------------------------------------
-- Mux definitions
----------------------------------------------------------------------------------------------------
u_mas_M <= U xor F;
v_mas_M <= V xor F;
u_mas_v <= U xor V;
u_mas_v_mas_M <= u_mas_v xor F;
a_mas_b <= A xor B;
-- Muxes for A and B
a_div_t <= '0'& A(NUM_BITS downto 1);
b_div_t <= '0'& B(NUM_BITS downto 1);
u_div_t <= '0'& U(NUM_BITS downto 1);
v_div_t <= '0'& V(NUM_BITS downto 1);
u_mas_M_div_t <= '0' & u_mas_M(NUM_BITS downto 1);
v_mas_M_div_t <= '0' & v_mas_M(NUM_BITS downto 1);
u_mas_v_div_t <= '0' & u_mas_v(NUM_BITS downto 1);
u_mas_v_mas_M_div_t <= '0' & u_mas_v_mas_M(NUM_BITS downto 1);
a_mas_b_div_t <= '0' & a_mas_b(NUM_BITS downto 1);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= '0' & Y;
B <= F;
U <= '0' & X;
v <= (others => '0');
x_div_y <= (others => '0');
done <= '0';
currentState <= CYCLE;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
x_div_y <= U(NUM_BITS-1 downto 0);
elsif A_par = '1' then
A <= A_div_t;
if U_par = '1' then
U <= U_div_t;
else
U <= u_mas_M_div_t;
end if;
elsif B_par = '1' then
B <= B_div_t;
if V_par = '1' then
V <= V_div_t;
else
V <= V_mas_M_div_t;
end if;
elsif a_greater_b = '1' then
A <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
U <= u_mas_v_div_t;
else
U <= u_mas_v_mas_M_div_t;
end if;
else
B <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
V <= u_mas_v_div_t;
else
V <= u_mas_v_mas_M_div_t;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
-- done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave; | gpl-3.0 |
mmoraless/ecc_vhdl | F2mArithmetic/F2m_divider/Guerric/Modular/celda_s.vhd | 1 | 1496 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_s is
generic(
NUM_BITS : positive := 163
);
port(
R : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
X2 : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c_1 : in STD_LOGIC;
c_2 : in STD_LOGIC;
en : in STD_LOGIC;
clk : in STD_LOGIC;
S : out STD_LOGIC_VECTOR(NUM_BITS downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_s is
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
Celda_s_process: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if en = '1' then
if c_1 = '0' and c_2 = '0' then
S <= X2;
elsif c_1 = '0' and c_2 = '1' then
S <= (others => '0');
else
S <= R;
end if;
end if;
end if;
end process;
end behave; | gpl-3.0 |
alextrem/red-diamond | fpga/vhdl/hdmi_pkg.vhd | 1 | 1161 | ------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geißler
--
-- Create Date: 23:40:00 11/26/2016
-- Design Name: hdmi_pkg.vhd
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This package contains stuff for the hdmi receiver
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package hdmi_pkg is
type t_hdmi_out is record
-- I2C Interface
scl : std_ulogic;
sda : std_ulogic;
csn : std_logic;
reset : std_logic;
end record t_hdmi_out;
type t_hdmi_in is record
lrck : std_logic; -- word clock
sclk : std_logic; -- Bit clock
ap : std_logic_vector(4 downto 0);
int : std_logic; --interrupt
end record t_hdmi_in;
component hdmi is
port (
reset : in std_logic;
mclk : in std_logic;
hdmi_in : in t_hdmi_in;
hdmi_out : out t_hdmi_out
);
end component;
end package;
| gpl-3.0 |
alextrem/red-diamond | fpga/vhdl/ahb_slave.vhd | 1 | 2011 | ------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 11/19/2016
-- Design Name:
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 17.0
-- Description: AHB slave interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.amba.all;
entity ahb_slave is
port(
hclk : in std_ulogic;
hreset_n : in std_ulogic;
ahb_in : in t_ahb_slave_in;
ahb_out : out t_ahb_slave_out
);
end entity;
architecture rtl of ahb_slave is
type t_ahb_state is (ADDRESS, DATA, FINISH);
signal AHBSTATE : t_ahb_state;
type t_register is record
hwrite : std_ulogic;
haddr : std_logic_vector(31 downto 0);
hsize : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
hreadyout : std_ulogic;
state : t_ahb_state;
end record;
--
signal r, r_next : t_register;
begin
-- Cominatorical process
comb_proc : process(ahb_in, r, hreset_n)
variable v : t_register;
begin
v := r;
case AHBSTATE is
when ADDRESS => -- Address state
if ahb_in.hready = '1' and ahb_in.hsel = '1' and ahb_in.htrans(1)= '1' then
v.haddr := ahb_in.haddr; -- store address
v.hwrite := ahb_in.hwrite; -- store write
v.hreadyout := '0';
v.state := DATA;
end if;
when DATA => -- Data state
if r.hwrite = '1' then
--ahb_write_data();
else
--ahb_read_word();
v.hreadyout := '1';
end if;
when FINISH =>
when others =>
null;
end case;
if (hreset_n = '0') then
v.state := ADDRESS;
end if;
r <= v;
ahb_out.hreadyout <= v.hreadyout;
end process comb_proc;
end rtl;
| gpl-3.0 |
alextrem/red-diamond | fpga/vhdl/axi_pkg.vhd | 1 | 9142 | ------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 11/19/2016
-- Design Name:
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This is the package for the AXI interfaces.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
-- Revision 0.2 - Changed indentation
-- Revision 0.3 - Updated package name
-- Added constants, subprograms and interface definition
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package axi is
------------------------------------------------------------------------------
-- Constants
------------------------------------------------------------------------------
constant cslv_axsize_1 : std_logic_vector(2 downto 0) := "000";
constant cslv_axsize_2 : std_logic_vector(2 downto 0) := "001";
constant cslv_axsize_4 : std_logic_vector(2 downto 0) := "010";
constant cslv_axsize_8 : std_logic_vector(2 downto 0) := "011";
constant cslv_axsize_16 : std_logic_vector(2 downto 0) := "100";
constant cslv_axsize_32 : std_logic_vector(2 downto 0) := "101";
constant cslv_axsize_64 : std_logic_vector(2 downto 0) := "110";
constant cslv_axsize_128 : std_logic_vector(2 downto 0) := "111";
constant cslv_axburst_fixed : std_logic_vector(1 downto 0) := "00";
constant cslv_axburst_incr : std_logic_vector(1 downto 0) := "01";
constant cslv_axburst_wrap : std_logic_vector(1 downto 0) := "10";
constant cslv_awlock_normal : std_logic_vector(1 downto 0) := "00";
constant cslv_awlock_exclusive : std_logic_vector(1 downto 0) := "01";
constant cslv_awlock_locked : std_logic_vector(1 downto 0) := "10";
constant cslv_axcache_dev_non_buf : std_logic_vector(3 downto 0) := "0000";
constant cslv_axcache_dev_buf : std_logic_vector(3 downto 0) := "0001";
constant cslv_axcache_norm_nc_nb : std_logic_vector(3 downto 0) := "0010";
constant cslv_axcache_norm_nc_b : std_logic_vector(3 downto 0) := "0010";
constant cslv_arcache_wt_no_alloc : std_logic_vector(3 downto 0) := "0011";
constant cslv_awcache_wt_no_alloc : std_logic_vector(3 downto 0) := "0110";
constant cslv_arcache_wt_r_alloc : std_logic_vector(3 downto 0) := "1110";
constant cslv_awcache_wt_r_alloc : std_logic_vector(3 downto 0) := "0110";
constant cslv_arcache_wt_w_alloc : std_logic_vector(3 downto 0) := "1010";
constant cslv_awcache_wt_w_alloc : std_logic_vector(3 downto 0) := "1110";
constant cslv_axcache_wtr_w_alloc : std_logic_vector(3 downto 0) := "1110";
constant cslv_arcache_wb_no_alloc : std_logic_vector(3 downto 0) := "1011";
constant cslv_awcache_wb_no_alloc : std_logic_vector(3 downto 0) := "0111";
constant cslv_arcache_wb_r_alloc : std_logic_vector(3 downto 0) := "1111";
constant cslv_awcache_wb_r_alloc : std_logic_vector(3 downto 0) := "0111";
constant cslv_axprot_u_access : std_logic_vector(2 downto 0) := "000";
constant cslv_axprot_p_access : std_logic_vector(2 downto 0) := "001";
constant cslv_axprot_s_access : std_logic_vector(2 downto 0) := "010";
constant cslv_axprot_ns_access : std_logic_vector(2 downto 0) := "011";
constant cslv_axprot_d_access : std_logic_vector(2 downto 0) := "100";
constant cslv_axprot_i_access : std_logic_vector(2 downto 0) := "100";
constant cslv_xresp_okay : std_logic_vector(1 downto 0) := "00";
constant cslv_xresp_exokay : std_logic_vector(1 downto 0) := "01";
constant cslv_xresp_slverr : std_logic_vector(1 downto 0) := "10";
constant cslv_xresp_decerr : std_logic_vector(1 downto 0) := "11";
------------------------------------------------------------------------------
-- AXI-4 Global Signals
------------------------------------------------------------------------------
type t_axi_wa_slv_in is record
slv_awid : std_logic_vector(3 downto 0);
slv_awaddr : std_logic_vector(31 downto 0);
slv_awlen : std_logic_vector(7 downto 0);
slv_awsize : std_logic_vector(2 downto 0);
slv_awburst : std_logic_vector(1 downto 0);
slv_awlock : std_logic_vector(1 downto 0);
slv_awcache : std_logic_Vector(3 downto 0);
slv_awprot : std_logic_vector(2 downto 0);
sl_awvalid : std_ulogic;
end record;
type t_axi_wa_slv_out is record
sl_awready : std_ulogic;
end record;
type t_axi_wd_slv_in is record
slv_wdata : std_logic_vector(31 downto 0);
slv_wstrb : std_logic_vector(3 downto 0);
sl_wlast : std_ulogic;
sl_wvalid : std_ulogic;
end record;
type t_axi_wd_slv_out is record
sl_wready : std_ulogic;
end record;
type t_axi_wr_slv_in is record
sl_bready : std_ulogic;
end record;
type t_axi_wr_slv_out is record
sl_bid : std_ulogic;
sl_bresp : std_ulogic;
sl_bvalid : std_ulogic;
end record;
type t_axi4_wd_slv_in is record
r_axi : t_axi_wd_slv_in;
sl_wuser : std_ulogic;
end record;
type t_axi_ra_slv_in is record
slv_arid : std_logic_vector(1 downto 0);
slv_araddr : std_logic_vector(31 downto 0);
slv_arlen : std_logic_vector(7 downto 0);
slv_arsize : std_logic_vector(2 downto 0);
slv_arburst : std_logic_vector(1 downto 0);
sl_arlock : std_logic;
slv_arcache : std_logic_vector(3 downto 0);
slv_arprot : std_logic_vector(2 downto 0);
slv_arqos : std_logic_vector(3 downto 0);
slv_arregion : std_logic_vector(3 downto 0);
sl_aruser : std_logic;
sl_arvalid : std_logic;
end record;
type t_axi_ra_slv_out is record
sl_arready : std_ulogic;
end record;
type t_axi_rd_slv_in is record
sl_rready : std_logic;
end record;
type t_axi_rd_slv_out is record
sl_rid : std_logic;
slv_rdata : std_logic_vector(31 downto 0);
slv_rresp : std_logic_vector(1 downto 0);
sl_rlast : std_logic;
sl_ruser : std_logic;
sl_rvalid : std_logic;
end record;
type t_axi_lpi_slv_in is record
sl_csysreq : std_ulogic;
end record;
type t_axi_lpi_slv_out is record
sl_csysack : std_ulogic;
sl_cactive : std_ulogic;
end record;
------------------------------------------------------------------------------
-- Sub-programs
------------------------------------------------------------------------------
--function axi_device_reg()
--return std_logic_vector;
function axireadword (
rdata : std_logic_vector(31 downto 0);
raddr : std_logic_vector(4 downto 0))
return std_logic_vector;
procedure axireadword (
rdata : in std_logic_vector(31 downto 0);
raddr : in std_logic_vector(4 downto 0);
data : out std_logic_vector(31 downto 0));
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
component axi3_slave
port (
-- global signals
sl_aclk : in std_ulogic;
sl_aresetn : in std_ulogic;
-- write address channel
-- write data channel
-- write response channel
-- read data channel
-- low power interface
r_lpi_in : in t_axi_lpi_slv_in;
r_lpi_out : out t_axi_lpi_slv_out
);
end component;
component axi4_slave
port (
-- global signals
sl_aclk : in std_ulogic;
sl_areset_n : in std_ulogic;
-- write address channel
r_wac_in : in t_axi_wa_slv_in;
awqos : in std_logic_vector(3 downto 0);
awregion : in std_logic_vector(3 downto 0);
awuser : in std_ulogic;
r_wac_out : out t_axi_wa_slv_out;
-- write data channel
r_wdc_in : in t_axi4_wd_slv_in;
r_wdc_out : out t_axi_wd_slv_out;
-- write response channel
r_wrc_in : in t_axi_wr_slv_in;
r_wrc_out : out t_axi_wr_slv_out;
-- read address channel
r_rac_in : in t_axi_ra_slv_in;
r_rac_out : out t_axi_ra_slv_out;
-- read data channel
r_rdc_in : in t_axi_rd_slv_in;
r_rdc_out : out t_axi_rd_slv_out;
-- low power interface
r_lpi_in : in t_axi_lpi_slv_in;
r_lpi_out : out t_axi_lpi_slv_out
);
end component;
component axi4_light_slave
port (
-- global signals
sl_aclk : in std_ulogic;
sl_areset_n : in std_ulogic
);
end component;
end axi;
package body axi is
function axireadword (
rdata : std_logic_vector(31 downto 0);
raddr : std_logic_vector(4 downto 0))
return std_logic_vector is
begin
end axireadword;
procedure axireadword (
rdata : in std_logic_vector(31 downto 0);
raddr : in std_logic_vector(4 downto 0);
data : out std_logic_vector(31 downto 0)) is
begin
end axireadword;
end;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | TP3/addition/normalizer/normalizer_tb.vhd | 1 | 2878 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity normalizer_tb is
end entity;
architecture normalizer_tb_arq of normalizer_tb is
signal man_in : std_logic_vector(16 downto 0) := (others => '0');
signal exp_in : std_logic_vector(5 downto 0) := (others => '0');
signal cin : std_logic := '0';
signal diff_signs : std_logic := '0';
signal rounding_bit : std_logic := '0';
signal man_out : std_logic_vector(15 downto 0) := (others => '0');
signal exp_out : std_logic_vector(5 downto 0) := (others => '0');
component normalizer is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
man_in : in std_logic_vector((TOTAL_BITS - EXP_BITS - 1) downto 0);
exp_in : in std_logic_vector(EXP_BITS - 1 downto 0);
cin : in std_logic; --To check if the sum had a carry
diff_signs : in std_logic;
rounding_bit : in std_logic;
man_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end component;
for normalizer_0 : normalizer use entity work.normalizer;
begin
normalizer_0 : normalizer
generic map(TOTAL_BITS => 23, EXP_BITS => 6)
port map(
man_in => man_in,
exp_in => exp_in,
cin => cin,
diff_signs => diff_signs,
rounding_bit => rounding_bit,
man_out => man_out,
exp_out => exp_out
);
process
type pattern_type is record
mi : std_logic_vector(16 downto 0);
ei : std_logic_vector(5 downto 0);
ci : std_logic;
ds : std_logic;
rb : std_logic;
mo : std_logic_vector(15 downto 0);
eo : std_logic_vector(5 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("00000000000000000","000000",'0','1','0',"0000000000000000","000000"),
("00000000000000000","111111",'0','1','0',"0000000000000000","000000"),
("00000000000000001","011111",'0','1','0',"0000000000000000","001111"),
("01000000000000000","111111",'1','1','0',"0000000000000000","111110"),
("00000111000000000","000101",'0','1','0',"0000000000000000","000000"),
("01110001001010010","011101",'0','0','0',"1100010010100100","011100"),
("01110001001010010","011101",'0','0','1',"1100010010100101","011100")
);
begin
for i in patterns'range loop
-- Set the inputs.
man_in <= patterns(i).mi;
exp_in <= patterns(i).ei;
cin <= patterns(i).ci;
diff_signs <= patterns(i).ds;
rounding_bit <= patterns(i).rb;
wait for 1 ns;
assert patterns(i).mo = man_out report "BAD MANTISSA, GOT: " & integer'image(to_integer(unsigned(man_out)));
assert patterns(i).eo = exp_out report "BAD EXPONENT, GOT: " & integer'image(to_integer(unsigned(exp_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
| gpl-3.0 |
ruygargar/LCSE_lab | ram/spr.vhd | 1 | 11333 | -------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: ram.vhd
-- Module Name: spr.vhd
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
entity spr is
PORT (
Clk : in std_logic;
Reset : in std_logic;
WriteEnable : in std_logic;
OutputEnable : in std_logic;
Address : in std_logic_vector(5 downto 0);
Databus : inout std_logic_vector(7 downto 0) := (others => 'Z');
Switches : out std_logic_vector(7 downto 0);
Temp_L : out std_logic_vector(6 downto 0);
Temp_H : out std_logic_vector(6 downto 0)
);
end spr;
architecture Behavioral of spr is
-- Señales usadas para inferir los biestables necesarios para cada uno de
-- los registros de función específica.
-- Cada señal tiene la longitud necesaria para almacenar únicamente
-- información útil, despreciando los bits de la palabra que no son
-- utilizados.
signal DMA_RX_BUFFER_MSB_REG : std_logic_vector (7 downto 0);
signal DMA_RX_BUFFER_MID_REG : std_logic_vector (7 downto 0);
signal DMA_RX_BUFFER_LSB_REG : std_logic_vector (7 downto 0);
signal NEW_INST_REG : std_logic_vector (7 downto 0);
signal DMA_TX_BUFFER_MSB_REG : std_logic_vector (7 downto 0);
signal DMA_TX_BUFFER_LSB_REG : std_logic_vector (7 downto 0);
signal SWITCH_0_REG : std_logic;
signal SWITCH_1_REG : std_logic;
signal SWITCH_2_REG : std_logic;
signal SWITCH_3_REG : std_logic;
signal SWITCH_4_REG : std_logic;
signal SWITCH_5_REG : std_logic;
signal SWITCH_6_REG : std_logic;
signal SWITCH_7_REG : std_logic;
signal LEVER_0_REG : std_logic_vector (3 downto 0);
signal LEVER_1_REG : std_logic_vector (3 downto 0);
signal LEVER_2_REG : std_logic_vector (3 downto 0);
signal LEVER_3_REG : std_logic_vector (3 downto 0);
signal LEVER_4_REG : std_logic_vector (3 downto 0);
signal LEVER_5_REG : std_logic_vector (3 downto 0);
signal LEVER_6_REG : std_logic_vector (3 downto 0);
signal LEVER_7_REG : std_logic_vector (3 downto 0);
signal LEVER_8_REG : std_logic_vector (3 downto 0);
signal LEVER_9_REG : std_logic_vector (3 downto 0);
signal T_STAT_REG : std_logic_vector (7 downto 0);
begin
-- Proceso secuencial utilizado para la actualización del valor almacenado
-- en los registros.
-- Únicamente cuando la señal de control WriteEnable esté activada,
-- almacenará el valor del bus de datos en el registro cuya dirección
-- esté seleccionada en el bus de direcciones.
-- Dispone de una señal de reset asíncrona, activa a nivel bajo, para
-- inicializar el valor de los biestables.
process (Clk, Reset)
begin
if Reset = '0' then
DMA_RX_BUFFER_MSB_REG <= X"00";
DMA_RX_BUFFER_MID_REG <= X"00";
DMA_RX_BUFFER_LSB_REG <= X"00";
NEW_INST_REG <= X"00";
DMA_TX_BUFFER_MSB_REG <= X"00";
DMA_TX_BUFFER_LSB_REG <= X"00";
SWITCH_0_REG <= '0';
SWITCH_1_REG <= '0';
SWITCH_2_REG <= '0';
SWITCH_3_REG <= '0';
SWITCH_4_REG <= '0';
SWITCH_5_REG <= '0';
SWITCH_6_REG <= '0';
SWITCH_7_REG <= '0';
LEVER_0_REG <= X"0";
LEVER_1_REG <= X"0";
LEVER_2_REG <= X"0";
LEVER_3_REG <= X"0";
LEVER_4_REG <= X"0";
LEVER_5_REG <= X"0";
LEVER_6_REG <= X"0";
LEVER_7_REG <= X"0";
LEVER_8_REG <= X"0";
LEVER_9_REG <= X"0";
T_STAT_REG <= X"20";
elsif Clk'event and Clk = '1' then
if WriteEnable = '1' then
case Address is
when DMA_RX_BUFFER_MSB(5 downto 0) =>
DMA_RX_BUFFER_MSB_REG <= Databus;
when DMA_RX_BUFFER_MID(5 downto 0) =>
DMA_RX_BUFFER_MID_REG <= Databus;
when DMA_RX_BUFFER_LSB(5 downto 0) =>
DMA_RX_BUFFER_LSB_REG <= Databus;
when NEW_INST(5 downto 0) =>
NEW_INST_REG <= Databus;
when DMA_TX_BUFFER_MSB(5 downto 0) =>
DMA_TX_BUFFER_MSB_REG <= Databus;
when DMA_TX_BUFFER_LSB(5 downto 0) =>
DMA_TX_BUFFER_LSB_REG <= Databus;
when SWITCH_BASE(5 downto 0) =>
SWITCH_0_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000001") =>
SWITCH_1_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000010") =>
SWITCH_2_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000011") =>
SWITCH_3_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000100") =>
SWITCH_4_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000101") =>
SWITCH_5_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000110") =>
SWITCH_6_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000111") =>
SWITCH_7_REG <= Databus(0);
when LEVER_BASE(5 downto 0) =>
LEVER_0_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000001") =>
LEVER_1_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000010") =>
LEVER_2_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000011") =>
LEVER_3_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000100") =>
LEVER_4_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000101") =>
LEVER_5_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000110") =>
LEVER_6_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000111") =>
LEVER_7_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"001000") =>
LEVER_8_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"001001") =>
LEVER_9_REG <= Databus(3 downto 0);
when T_STAT(5 downto 0) =>
T_STAT_REG <= Databus;
when others =>
end case;
end if;
end if;
end process;
-- Proceso combinacional que multiplexa la salida de los registros hacia el
-- bus de datos en función de la dirección indicada en el bus de
-- direcciones.
-- La salida al bus de datos se mantendrá a alta impedancia siempre que la
-- señal de control OutputEnable este desactivada.
process (OutputEnable, Address,
DMA_RX_BUFFER_MSB_REG, DMA_RX_BUFFER_MID_REG,
DMA_RX_BUFFER_LSB_REG, NEW_INST_REG,
DMA_TX_BUFFER_MSB_REG, DMA_TX_BUFFER_LSB_REG,
SWITCH_0_REG, SWITCH_1_REG, SWITCH_2_REG, SWITCH_3_REG,
SWITCH_4_REG, SWITCH_5_REG, SWITCH_6_REG, SWITCH_7_REG,
LEVER_0_REG, LEVER_1_REG, LEVER_2_REG, LEVER_3_REG, LEVER_4_REG,
LEVER_5_REG, LEVER_6_REG, LEVER_7_REG, LEVER_8_REG, LEVER_9_REG,
T_STAT_REG)
begin
if OutputEnable = '1' then
case Address is
when DMA_RX_BUFFER_MSB(5 downto 0) =>
Databus <= DMA_RX_BUFFER_MSB_REG;
when DMA_RX_BUFFER_MID(5 downto 0) =>
Databus <= DMA_RX_BUFFER_MID_REG;
when DMA_RX_BUFFER_LSB(5 downto 0) =>
Databus <= DMA_RX_BUFFER_LSB_REG;
when NEW_INST(5 downto 0) =>
Databus <= NEW_INST_REG;
when DMA_TX_BUFFER_MSB(5 downto 0) =>
Databus <= DMA_TX_BUFFER_MSB_REG;
when DMA_TX_BUFFER_LSB(5 downto 0) =>
Databus <= DMA_TX_BUFFER_LSB_REG;
when SWITCH_BASE(5 downto 0) =>
Databus <= "0000000"&SWITCH_0_REG;
when (SWITCH_BASE(5 downto 0)+"000001") =>
Databus <= "0000000"&SWITCH_1_REG;
when (SWITCH_BASE(5 downto 0)+"000010") =>
Databus <= "0000000"&SWITCH_2_REG;
when (SWITCH_BASE(5 downto 0)+"000011") =>
Databus <= "0000000"&SWITCH_3_REG;
when (SWITCH_BASE(5 downto 0)+"000100") =>
Databus <= "0000000"&SWITCH_4_REG;
when (SWITCH_BASE(5 downto 0)+"000101") =>
Databus <= "0000000"&SWITCH_5_REG;
when (SWITCH_BASE(5 downto 0)+"000110") =>
Databus <= "0000000"&SWITCH_6_REG;
when (SWITCH_BASE(5 downto 0)+"000111") =>
Databus <= "0000000"&SWITCH_7_REG;
when LEVER_BASE(5 downto 0) =>
Databus <= "0000"&LEVER_0_REG;
when (LEVER_BASE(5 downto 0)+"000001") =>
Databus <= "0000"&LEVER_1_REG;
when (LEVER_BASE(5 downto 0)+"000010") =>
Databus <= "0000"&LEVER_2_REG;
when (LEVER_BASE(5 downto 0)+"000011") =>
Databus <= "0000"&LEVER_3_REG;
when (LEVER_BASE(5 downto 0)+"000100") =>
Databus <= "0000"&LEVER_4_REG;
when (LEVER_BASE(5 downto 0)+"000101") =>
Databus <= "0000"&LEVER_5_REG;
when (LEVER_BASE(5 downto 0)+"000110") =>
Databus <= "0000"&LEVER_6_REG;
when (LEVER_BASE(5 downto 0)+"000111") =>
Databus <= "0000"&LEVER_7_REG;
when (LEVER_BASE(5 downto 0)+"001000") =>
Databus <= "0000"&LEVER_8_REG;
when (LEVER_BASE(5 downto 0)+"001001") =>
Databus <= "0000"&LEVER_9_REG;
when T_STAT(5 downto 0) =>
Databus <= T_STAT_REG;
when others =>
Databus <= (others => '0');
end case;
else
Databus <= (others => 'Z');
end if;
end process;
-- Concatenación de las señales de salida de todos los registros de
-- "Switch" para la creación del bus de salida "Switches".
Switches <= SWITCH_7_REG&SWITCH_6_REG&SWITCH_5_REG&SWITCH_4_REG&
SWITCH_3_REG&SWITCH_2_REG&SWITCH_1_REG&SWITCH_0_REG;
-- Lógica necesaria para transformar el valor almacenado en el registro de
-- temperatura (binario) a su representación en dos dígitos sobre un display
-- alfanumérico (7 segmentos).
-- Los 4 bits superiores del registro se utilizarán para representar el
-- dígito correspondiente a decenas. Los 4 bits inferiores, para el de las
-- unidades.
with T_STAT_REG(7 downto 4) select
Temp_H <=
"0000110" when "0001", -- 1
"1011011" when "0010", -- 2
"1001111" when "0011", -- 3
"1100110" when "0100", -- 4
"1101101" when "0101", -- 5
"1111101" when "0110", -- 6
"0000111" when "0111", -- 7
"1111111" when "1000", -- 8
"1101111" when "1001", -- 9
"1110111" when "1010", -- A
"1111100" when "1011", -- B
"0111001" when "1100", -- C
"1011110" when "1101", -- D
"1111001" when "1110", -- E
"1110001" when "1111", -- F
"0111111" when others; -- 0
with T_STAT_REG(3 downto 0) select
Temp_L <=
"0000110" when "0001", -- 1
"1011011" when "0010", -- 2
"1001111" when "0011", -- 3
"1100110" when "0100", -- 4
"1101101" when "0101", -- 5
"1111101" when "0110", -- 6
"0000111" when "0111", -- 7
"1111111" when "1000", -- 8
"1101111" when "1001", -- 9
"1110111" when "1010", -- A
"1111100" when "1011", -- B
"0111001" when "1100", -- C
"1011110" when "1101", -- D
"1111001" when "1110", -- E
"1110001" when "1111", -- F
"0111111" when others; -- 0
end Behavioral;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | ghdl/lib/ghdl/src/synopsys/std_logic_signed.vhdl | 13 | 12622 | --------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | TP3/addition/bit_xor/bit_xor_tb.vhd | 1 | 1226 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bit_xor_tb is
end entity;
architecture bit_xor_tb_arq of bit_xor_tb is
signal bit1 : std_logic;
signal bit2 : std_logic;
signal result : std_logic;
component bit_xor is
port (
bit1_in: in std_logic := '0';
bit2_in: in std_logic := '0';
result: out std_logic := '0'
);
end component;
begin
bit_xor_0 : bit_xor
port map(
bit1_in => bit1,
bit2_in => bit2,
result => result
);
process
type pattern_type is record
b1 : std_logic;
b2 : std_logic;
r : std_logic;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
('0','0','0'),
('0','1','1'),
('1','0','1'),
('1','1','0')
);
begin
for i in patterns'range loop
-- Set the inputs.
bit1 <= patterns(i).b1;
bit2 <= patterns(i).b2;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert result = patterns(i).r report "BAD RESULT: " & std_logic'image(result);
end loop;
assert false report "end of test" severity note;
wait;
end process;
end bit_xor_tb_arq;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | TP3/addition/sign_computer/sign_computer_tb.vhd | 1 | 3609 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sign_computer_tb is
end entity;
architecture sign_computer_tb_arq of sign_computer_tb is
signal man_1_in: std_logic_vector(15 downto 0) := (others => '0');
signal man_2_in: std_logic_vector(15 downto 0) := (others => '0');
signal sign_1_in: std_logic := '0';
signal sign_2_in: std_logic := '0';
signal man_greater_in: std_logic_vector(15 downto 0) := (others => '0');
signal pre_complemented_result: std_logic_vector(16 downto 0) := (others => '0');
signal complemented_result: std_logic_vector(16 downto 0) := (others => '0');
signal sign_out: std_logic := '0';
component sign_computer is
generic(
BITS : natural := 16
);
port(
man_1_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
man_2_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
sign_1_in: in std_logic := '0';
sign_2_in: in std_logic := '0';
man_greater_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
pre_complemented_result: in std_logic_vector(BITS downto 0) := (others => '0');
complemented_result: in std_logic_vector(BITS downto 0) := (others => '0');
sign_out: out std_logic := '0'
);
end component;
for sign_computer_0 : sign_computer use entity work.sign_computer;
begin
sign_computer_0 : sign_computer
generic map(BITS => 16)
port map(
man_1_in => man_1_in,
man_2_in => man_2_in,
sign_1_in => sign_1_in,
sign_2_in => sign_2_in,
man_greater_in => man_greater_in,
pre_complemented_result => pre_complemented_result,
complemented_result => complemented_result,
sign_out => sign_out
);
process
type pattern_type is record
m1 : std_logic_vector(15 downto 0);
m2 : std_logic_vector(15 downto 0);
s1 : std_logic;
s2 : std_logic;
mg : std_logic_vector(15 downto 0);
pcr : std_logic_vector(16 downto 0);
cr : std_logic_vector(16 downto 0);
so : std_logic;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("0000000000000000","0000000000000000",'0','0',"0000000000000000","00000000000000000","00000000000000000",'0'),
("0000000000000000","0000000000000000",'1','1',"0000000000000000","00000000000000000","00000000000000000",'1'),
("0000000000000000","1111111111111111",'0','1',"1111111111111111","00000000000000000","00000000000000000",'1'),
("0000000000000000","1111111111111111",'1','0',"1111111111111111","00000000000000000","00000000000000000",'0'),
("0000000000000000","1111111111111111",'0','1',"0000000000000000","00000000000000000","00000000000000000",'0'),
("0000000000000000","1111111111111111",'1','0',"0000000000000000","00000000000000000","00000000000000000",'1'),
("0000000000000000","1111111111111111",'0','1',"0000000000000000","00000000000000000","00000000000000000",'0'),
("0000000000000000","1111111111111111",'1','0',"0000000000000000","00000000000000000","00000000000000000",'1')
);
begin
for i in patterns'range loop
-- Set the inputs.
man_1_in <= patterns(i).m1;
man_2_in <= patterns(i).m2;
sign_1_in <= patterns(i).s1;
sign_2_in <= patterns(i).s2;
man_greater_in <= patterns(i).mg;
pre_complemented_result <= patterns(i).pcr;
complemented_result <= patterns(i).cr;
wait for 1 ms;
assert patterns(i).so = sign_out report "BAD RESULT, GOT: " & std_logic'image(sign_out);
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-LuGus/TP2-Voltimetro/display.vhd | 1 | 7782 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utility.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity display is
port (
mclk: in std_logic;
mrst: in std_logic;
mena: in std_logic;
v_in_plus: in std_logic;
v_in_minus: in std_logic;
v_out: out std_logic;
hs: out std_logic;
vs: out std_logic;
red_o: out std_logic_vector(2 downto 0);
grn_o: out std_logic_vector(2 downto 0);
blu_o: out std_logic_vector(1 downto 0)
-- red_o: out std_logic;
-- grn_o: out std_logic;
-- blu_o: out std_logic
);
attribute loc: string;
-- Mapeo de pines para el kit Nexys 2 (spartan 3E)
attribute loc of mclk: signal is "B8";
attribute loc of hs: signal is "T4";
attribute loc of vs: signal is "U3";
attribute loc of red_o: signal is "R8 T8 R9";
attribute loc of grn_o: signal is "P6 P8 N8";
attribute loc of blu_o: signal is "U4 U5";
attribute loc of mrst: signal is "H13";
attribute loc of mena: signal is "E18";
attribute loc of v_in_plus: signal is "G15";
attribute loc of v_in_minus: signal is "G16";
attribute loc of v_out: signal is "H16";
--attribute loc of mclk: signal is "C9";
--attribute loc of mrst: signal is "H13";
--attribute loc of mena: signal is "D18";
--attribute loc of hs: signal is "F15";
--attribute loc of vs: signal is "F14";
--attribute loc of red_o: signal is "H14";
--attribute loc of grn_o: signal is "H15";
--attribute loc of blu_o: signal is "G15";
end;
architecture display_arq of display is
component vga_ctrl is
port (
mclk: in std_logic;
red_i: in std_logic;
grn_i: in std_logic;
blu_i: in std_logic;
hs: out std_logic;
vs: out std_logic;
red_o: out std_logic_vector(2 downto 0);
grn_o: out std_logic_vector(2 downto 0);
blu_o: out std_logic_vector(1 downto 0);
-- red_o: out std_logic;
-- grn_o: out std_logic;
-- blu_o: out std_logic;
pixel_row: out std_logic_vector(9 downto 0);
pixel_col: out std_logic_vector(9 downto 0)
);
end component;
component ones_generator is
generic (
PERIOD: natural := 30000;
COUNT: natural := 15500
);
port(
clk: in std_logic;
count_o: out std_logic
);
end component;
component bcd_1_counter is
generic (
COUNTERS:natural := 5;
OUTPUT:natural := 3
);
port (
clk_in: in std_logic;
rst_in: in std_logic;
ena_in: in std_logic;
counter_out: out bcd_vector (OUTPUT-1 downto 0)
);
end component;
component char_ROM is
generic(
N: integer:= 6;
M: integer:= 3;
W: integer:= 8
);
port(
char_address: in std_logic_vector(5 downto 0);
font_row, font_col: in std_logic_vector(M-1 downto 0);
rom_out: out std_logic
);
end component;
component bcd_multiplexer is
port(
bcd0_input : in std_logic_vector(3 downto 0);
bcd1_input : in std_logic_vector(3 downto 0);
bcd2_input : in std_logic_vector(3 downto 0);
bcd3_input : in std_logic_vector(3 downto 0);
bcd4_input : in std_logic_vector(3 downto 0);
bcd5_input : in std_logic_vector(3 downto 0);
mux_selector : in std_logic_vector (2 downto 0);
mux_output : out std_logic_vector (5 downto 0)
);
end component;
component rom_manager is
generic (
SCREEN_H:natural := 1080;
SCREEN_W:natural := 1920;
BITS:natural := 11
);
port (
pixel_x_v: in std_logic_vector(BITS-1 downto 0);
pixel_y_v: in std_logic_vector(BITS-1 downto 0);
to_mux_v: out std_logic_vector(2 downto 0);
char_x_v: out std_logic_vector(2 downto 0);
char_y_v: out std_logic_vector(2 downto 0)
);
end component;
component FFD_Array is
generic (
SIZE: natural := 12
);
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
Q: out std_logic_vector(SIZE-1 downto 0);
D: in std_logic_vector(SIZE-1 downto 0)
);
end component;
component voltage_registry_enabler is
port (
clk_in: in std_logic;
rst_in: in std_logic;
ena_in: in std_logic;
out_1: out std_logic;
out_2: out std_logic
);
end component;
signal pixel_row: std_logic_vector(9 downto 0);
signal pixel_col: std_logic_vector(9 downto 0);
signal color: std_logic;
signal mux_to_rom: std_logic_vector(5 downto 0);
signal manager_to_rom_row: std_logic_vector(2 downto 0);
signal manager_to_rom_col: std_logic_vector(2 downto 0);
signal manager_to_mux: std_logic_vector(2 downto 0);
signal reg_to_mux1: std_logic_vector(3 downto 0);
signal reg_to_mux2: std_logic_vector(3 downto 0);
signal reg_to_mux3: std_logic_vector(3 downto 0);
signal ones_generator_to_counter: std_logic;
signal enabler_to_reg: std_logic;
signal enabler_to_counter: std_logic;
signal reg_in0: std_logic_vector(3 downto 0);
signal reg_in1: std_logic_vector(3 downto 0);
signal reg_in2: std_logic_vector(3 downto 0);
signal reg_in: std_logic_vector(11 downto 0);
signal v_out_aux: std_logic;
signal to_ff:std_logic;
begin
reg_in <= reg_in0®_in1®_in2;
vga_controller_map: vga_ctrl
port map(
mclk => mclk,
red_i => color,
grn_i => color,
blu_i => '1',
hs => hs,
vs => vs,
red_o => red_o,
grn_o => grn_o,
blu_o => blu_o,
pixel_row => pixel_row,
pixel_col => pixel_col
);
char_ROM_map: char_ROM
port map(
char_address => mux_to_rom,
font_row => manager_to_rom_row,
font_col => manager_to_rom_col,
rom_out => color
);
rom_manager_map: rom_manager
generic map(384,680,10)
port map(
pixel_x_v => pixel_col,
pixel_y_v => pixel_row,
to_mux_v => manager_to_mux,
char_x_v => manager_to_rom_col,
char_y_v => manager_to_rom_row
);
FFD_Array_map: FFD_Array
generic map(12)
port map(
enable => enabler_to_reg,
reset => mrst,
clk => mclk,
Q(3 downto 0) => reg_to_mux1,
Q(7 downto 4) => reg_to_mux2,
Q(11 downto 8) => reg_to_mux3,
D => reg_in
);
bcd_multiplexer_map: bcd_multiplexer
port map(
bcd0_input => reg_to_mux1,
bcd1_input => "1010", --comma in rom
bcd2_input => reg_to_mux2,
bcd3_input => reg_to_mux3,
bcd4_input => "1100",--V in rom
bcd5_input => "1011", --space in rom
mux_selector => manager_to_mux,
mux_output => mux_to_rom
);
ones_generator_map: ones_generator
generic map(33000,23100)
port map(
clk => mclk,
count_o => ones_generator_to_counter
);
v_out <= v_out_aux;
bcd_1_counter_map: bcd_1_counter
port map(
clk_in => mclk,
rst_in => enabler_to_counter,
ena_in => v_out_aux,
counter_out(0) => reg_in0,
counter_out(1) => reg_in1,
counter_out(2) => reg_in2
);
voltage_registry_enabler_map: voltage_registry_enabler
port map(
clk_in => mclk,
rst_in => mrst,
ena_in => '1',
out_1 => enabler_to_reg,
out_2 => enabler_to_counter
);
IBUFDS_inst : IBUFDS
-- generic map (
-- CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Spartan-3 only)
-- DIFF_TERM => FALSE, -- Differential Termination
-- IOSTANDARD => "DEFAULT")
port map (
O => to_ff, -- Buffer output
I => v_in_plus, -- Diff_p buffer input (connect directly to top-level port)
IB => v_in_minus -- Diff_n buffer input (connect directly to top-level port)
);
FFD_Array_map2: FFD_Array
generic map(1)
port map(
enable => '1',
reset => mrst,
clk => mclk,
Q(0) => v_out_aux,
D(0) => to_ff
);
end; | gpl-3.0 |
Xero-Hige/LuGus-VHDL | TPS-2016/relocate/FFD.vhd | 2 | 503 | library IEEE;
use IEEE.std_logic_1164.all;
entity FFD is
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
Q: out std_logic;
D: in std_logic
);
end;
architecture FFD_Funct of FFD is
begin
process(clk, reset)
begin
if reset = '1' then
Q <= '0';
elsif rising_edge(clk) then
if enable = '1' then
Q <= D;
end if; --No va else para considerar todos los casos porque asi deja el valor anterior de Q.
end if;
end process;
end;
| gpl-3.0 |
pwuertz/digitizer2fw | sim/adc_program_tb.vhd | 1 | 3029 | -------------------------------------------------------------------------------
-- ADS5403 ADC, serial programming test bench
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
entity adc_program_tb is
end adc_program_tb;
architecture adc_program_tb_arch of adc_program_tb is
signal ADC_SDENB, ADC_SDIO, ADC_SCLK: std_logic;
component adc_program
port (
-- application interface
clk_main: in std_logic;
start: in std_logic;
rd: in std_logic;
busy: out std_logic;
addr: in std_logic_vector(6 downto 0);
din: in std_logic_vector(15 downto 0);
dout: out std_logic_vector(15 downto 0);
-- adc interface
adc_sdenb: out std_logic;
adc_sdio: inout std_logic;
adc_sclk: out std_logic
);
end component;
signal adc_prog_start: std_logic := '0';
signal adc_prog_rd: std_logic := '0';
signal adc_prog_busy: std_logic;
signal adc_prog_addr: std_logic_vector(6 downto 0) := (others => '-');
signal adc_prog_din: std_logic_vector(15 downto 0) := (others => '-');
signal adc_prog_dout: std_logic_vector(15 downto 0) := (others => '-');
constant clk_period : time := 10 ns;
signal clk: std_logic;
begin
adc_program_inst: adc_program
port map (
clk_main => clk,
start => adc_prog_start,
rd => adc_prog_rd,
busy => adc_prog_busy,
addr => adc_prog_addr,
din => adc_prog_din,
dout => adc_prog_dout,
adc_sdenb => ADC_SDENB,
adc_sdio => ADC_SDIO,
adc_sclk => ADC_SCLK
);
clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stimulus: process
constant ADDRESS: std_logic_vector := "0100011";
constant WORD: std_logic_vector := "1100000011111111";
begin
ADC_SDIO <= 'Z';
adc_prog_start <= '0';
adc_prog_addr <= ADDRESS;
adc_prog_din <= WORD;
-- start read cycle
wait for clk_period/2;
wait for 10 * clk_period;
adc_prog_rd <= '1';
adc_prog_start <= '1';
wait for clk_period;
adc_prog_start <= '0';
-- wait until adc_prog stops driving SDIO and drive test signal
wait until ADC_SDIO = 'Z';
ADC_SDIO <= '0';
wait for 200 ns;
ADC_SDIO <= '1';
wait until adc_prog_busy = '0';
ADC_SDIO <= 'Z';
-- wait a bit
wait for 100 * clk_period;
-- start write cycle
adc_prog_rd <= '0';
adc_prog_start <= '1';
wait for clk_period;
adc_prog_start <= '0';
-- wait for finished
wait until adc_prog_busy = '0';
assert false report "Stimulus finished" severity note;
wait;
end process;
end adc_program_tb_arch;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | TP3/addition/base_complementer/base_complementer_tb.vhd | 1 | 1498 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity base_complementer_tb is
end entity;
architecture base_complementer_tb_arq of base_complementer_tb is
signal number_in : std_logic_vector(15 downto 0) := (others => '0');
signal number_out : std_logic_vector(15 downto 0) := (others => '0');
component base_complementer is
generic(
TOTAL_BITS : natural := 16
);
port(
number_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
number_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
for base_complementer_0 : base_complementer use entity work.base_complementer;
begin
base_complementer_0 : base_complementer
generic map(TOTAL_BITS => 16)
port map(
number_in => number_in,
number_out => number_out
);
process
type pattern_type is record
ni : integer;
no : integer;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
(1,-1),
(0,0),
(10,-10)
);
begin
for i in patterns'range loop
-- Set the inputs.
number_in <= std_logic_vector(to_signed(patterns(i).ni,16));
wait for 1 ns;
assert patterns(i).no = to_integer(signed(number_out)) report "BAD COMPLEMENT, GOT: " & integer'image(to_integer(signed(number_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | TP3/multiplication/mantissa_multiplier/mantissa_multiplier.vhd | 1 | 950 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mantissa_multiplier is
generic(
BITS:natural := 16
);
port (
man1_in: in std_logic_vector(BITS - 1 downto 0);
man2_in: in std_logic_vector(BITS - 1 downto 0);
result: out std_logic_vector(BITS + 1 downto 0) --Add one to shift if necessary
);
end;
architecture mantissa_multiplier_arq of mantissa_multiplier is
begin
process(man1_in, man2_in)
variable expanded_mantissa_1 : std_logic_vector(BITS downto 0) := (others => '0');
variable expanded_mantissa_2 : std_logic_vector(BITS downto 0) := (others => '0');
variable tmp_result: std_logic_vector((BITS*2) + 1 downto 0) := (others => '0');
begin
expanded_mantissa_1 := '1' & man1_in;
expanded_mantissa_2 := '1' & man2_in;
tmp_result := std_logic_vector(unsigned(expanded_mantissa_1) * unsigned(expanded_mantissa_2));
result <= tmp_result(BITS*2 + 1 downto BITS);
end process;
end architecture;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | TP3/multiplication/sign_computer/sign_computer_tb.vhd | 1 | 1367 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sign_computer_tb is
end entity;
architecture sign_computer_tb_arq of sign_computer_tb is
signal sign1_in : std_logic := '0';
signal sign2_in : std_logic := '0';
signal sign_out : std_logic := '0';
component sign_computer is
port(
sign1_in : in std_logic;
sign2_in : in std_logic;
sign_out : out std_logic
);
end component;
for sign_computer_0: sign_computer use entity work.sign_computer;
begin
sign_computer_0: sign_computer port map(
sign1_in => sign1_in,
sign2_in => sign2_in,
sign_out => sign_out
);
process
type pattern_type is record
s1i : std_logic;
s2i : std_logic;
so : std_logic;
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
('0','0','0'),
('0','1','1'),
('1','0','1'),
('1','1','0')
);
begin
for i in patterns'range loop
-- Set the inputs.
sign1_in <= patterns(i).s1i;
sign2_in <= patterns(i).s2i;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert sign_out = patterns(i).so report "BAD SIGN: " & std_logic'image(sign_out) severity error;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | ghdl/lib/ghdl/src/mentor/std_logic_arith.vhdl | 7 | 14183 | ----------------------------------------------------------------------------
-- --
-- Copyright (c) 1993 by Mentor Graphics --
-- --
-- This source file is proprietary information of Mentor Graphics,Inc. --
-- It may be distributed in whole without restriction provided that --
-- this copyright statement is not removed from the file and that --
-- any derivative work contains this copyright notice. --
-- --
-- Package Name : std_logic_arith --
-- --
-- Purpose : This package is to allow the synthesis of the 1164 package. --
-- This package add the capability of SIGNED/UNSIGNED math. --
-- --
----------------------------------------------------------------------------
LIBRARY ieee ;
PACKAGE std_logic_arith IS
USE ieee.std_logic_1164.ALL;
TYPE SIGNED IS ARRAY (Natural RANGE <>) OF STD_LOGIC ;
TYPE UNSIGNED IS ARRAY (Natural RANGE <>) OF STD_LOGIC ;
FUNCTION std_ulogic_wired_or ( input : std_ulogic_vector ) RETURN std_ulogic;
FUNCTION std_ulogic_wired_and ( input : std_ulogic_vector ) RETURN std_ulogic;
-------------------------------------------------------------------------------
-- Note that all functions that take two vector arguments will
-- handle unequal argument lengths
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Conversion Functions
-------------------------------------------------------------------
-- Except for the to_integer and conv_integer functions for the
-- signed argument all others assume the input vector to be of
-- magnitude representation. The signed functions assume
-- a 2's complement representation.
FUNCTION to_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER;
FUNCTION to_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER;
FUNCTION to_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL;
FUNCTION to_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL;
FUNCTION to_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER;
FUNCTION conv_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER;
FUNCTION conv_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER;
FUNCTION conv_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL;
FUNCTION conv_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL;
FUNCTION conv_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER;
-- Following functions will return the natural argument in magnitude representation.
FUNCTION to_stdlogic ( arg1 : BOOLEAN ) RETURN STD_LOGIC;
FUNCTION to_stdlogicvector ( arg1 : INTEGER; size : NATURAL ) RETURN STD_LOGIC_VECTOR;
FUNCTION to_stdulogicvector ( arg1 : INTEGER; size : NATURAL ) RETURN STD_ULOGIC_VECTOR;
FUNCTION to_unsigned ( arg1 : NATURAL; size : NATURAL ) RETURN UNSIGNED;
FUNCTION conv_unsigned ( arg1 : NATURAL; size : NATURAL ) RETURN UNSIGNED;
-- The integer argument is returned in 2's complement representation.
FUNCTION to_signed ( arg1 : INTEGER; size : NATURAL ) RETURN SIGNED;
FUNCTION conv_signed ( arg1 : INTEGER; size : NATURAL ) RETURN SIGNED;
-------------------------------------------------------------------------------
-- sign/zero extend FUNCTIONs
-------------------------------------------------------------------------------
-- The zero_extend functions will perform zero padding to the input vector,
-- returning a vector of length equal to size (the second argument). Note that
-- if size is less than the length of the input argument an assertion will occur.
FUNCTION zero_extend ( arg1 : STD_ULOGIC_VECTOR; size : NATURAL ) RETURN STD_ULOGIC_VECTOR;
FUNCTION zero_extend ( arg1 : STD_LOGIC_VECTOR; size : NATURAL ) RETURN STD_LOGIC_VECTOR;
FUNCTION zero_extend ( arg1 : STD_LOGIC; size : NATURAL ) RETURN STD_LOGIC_VECTOR;
FUNCTION zero_extend ( arg1 : UNSIGNED; size : NATURAL ) RETURN UNSIGNED;
FUNCTION sign_extend ( arg1 : SIGNED; size : NATURAL ) RETURN SIGNED;
-------------------------------------------------------------------------------
-- Arithmetic functions
-------------------------------------------------------------------------------
-- All arithmetic functions except multiplication will return a vector
-- of size equal to the size of its largest argument. For multiplication,
-- the resulting vector has a size equal to the sum of the size of its inputs.
-- Note that arguments of unequal lengths are allowed.
FUNCTION "+" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC;
FUNCTION "+" ( arg1, arg2 : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "+" ( arg1, arg2 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "+" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED ;
FUNCTION "+" ( arg1, arg2 : SIGNED ) RETURN SIGNED ;
FUNCTION "-" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC;
FUNCTION "-" ( arg1, arg2 : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "-" ( arg1, arg2 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "-" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "-" ( arg1, arg2 : SIGNED ) RETURN SIGNED;
FUNCTION "+" ( arg1 : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "+" ( arg1 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "+" ( arg1 : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "+" ( arg1 : SIGNED ) RETURN SIGNED;
FUNCTION "-" ( arg1 : SIGNED ) RETURN SIGNED;
FUNCTION "*" ( arg1, arg2 : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "*" ( arg1, arg2 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "*" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED ;
FUNCTION "*" ( arg1, arg2 : SIGNED ) RETURN SIGNED ;
FUNCTION "abs" ( arg1 : SIGNED) RETURN SIGNED;
-- Vectorized Overloaded Arithmetic Operators, not supported for synthesis.
-- The following operators are not supported for synthesis.
FUNCTION "/" ( l, r : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "/" ( l, r : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "/" ( l, r : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "/" ( l, r : SIGNED ) RETURN SIGNED;
FUNCTION "MOD" ( l, r : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "MOD" ( l, r : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "MOD" ( l, r : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "REM" ( l, r : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "REM" ( l, r : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "REM" ( l, r : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "**" ( l, r : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "**" ( l, r : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "**" ( l, r : UNSIGNED ) RETURN UNSIGNED;
-------------------------------------------------------------------------------
-- Shift and rotate functions.
-------------------------------------------------------------------------------
-- Note that all the shift and rotate functions below will change to overloaded
-- operators in the train1 release.
FUNCTION "sla" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "sla" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "sla" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ;
FUNCTION "sla" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ;
FUNCTION "sra" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "sra" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "sra" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ;
FUNCTION "sra" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ;
FUNCTION "sll" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "sll" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "sll" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ;
FUNCTION "sll" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ;
FUNCTION "srl" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "srl" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "srl" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ;
FUNCTION "srl" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ;
FUNCTION "rol" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "rol" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "rol" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ;
FUNCTION "rol" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ;
FUNCTION "ror" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "ror" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "ror" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ;
FUNCTION "ror" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ;
-------------------------------------------------------------------------------
-- Comparision functions and operators.
-------------------------------------------------------------------------------
-- For all comparision operators, the default operator for signed and unsigned
-- types has been overloaded to perform logical comparisions. Note that for
-- other types the default operator is not overloaded and the use will result
-- in literal comparisions which is not supported for synthesis.
--
-- Unequal operator widths are supported for all the comparision functions.
FUNCTION eq ( l, r : STD_LOGIC ) RETURN BOOLEAN;
FUNCTION eq ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION eq ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION eq ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION eq ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION "=" ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION "=" ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION ne ( l, r : STD_LOGIC ) RETURN BOOLEAN;
FUNCTION ne ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION ne ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION ne ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION ne ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION "/=" ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION "/=" ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION lt ( l, r : STD_LOGIC ) RETURN BOOLEAN;
FUNCTION lt ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION lt ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION lt ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION lt ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION "<" ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION "<" ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION gt ( l, r : STD_LOGIC ) RETURN BOOLEAN;
FUNCTION gt ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION gt ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION gt ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION gt ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION ">" ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION ">" ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION le ( l, r : STD_LOGIC ) RETURN BOOLEAN;
FUNCTION le ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION le ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION le ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION le ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION "<=" ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION "<=" ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION ge ( l, r : STD_LOGIC ) RETURN BOOLEAN;
FUNCTION ge ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION ge ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION ge ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION ge ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION ">=" ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION ">=" ( l, r : SIGNED ) RETURN BOOLEAN ;
-------------------------------------------------------------------------------
-- Logical operators.
-------------------------------------------------------------------------------
-- allows operands of unequal lengths, return vector is
-- equal to the size of the largest argument.
FUNCTION "and" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "and" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "nand" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "nand" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "or" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "or" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "nor" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "nor" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "xor" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "xor" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "not" (arg1:SIGNED) RETURN SIGNED;
FUNCTION "not" (arg1:UNSIGNED) RETURN UNSIGNED;
FUNCTION "xnor" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR;
FUNCTION "xnor" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION "xnor" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "xnor" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
END std_logic_arith ;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-Lucho/TP1-Contador/bcd_controller/4_port_multiplexer.vhd | 2 | 969 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity four_port_multiplexer is
generic(
BITS:natural := 1);
port (
data_in_a: in std_logic_vector(BITS-1 downto 0);
data_in_b: in std_logic_vector(BITS-1 downto 0);
data_in_c: in std_logic_vector(BITS-1 downto 0);
data_in_d: in std_logic_vector(BITS-1 downto 0);
select_in: in std_logic_vector(1 downto 0); --2 bits, 4 opciones
data_out: out std_logic_vector(BITS-1 downto 0)
);
end;
architecture four_port_multiplexer_arq of four_port_multiplexer is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(select_in)
begin
SELECTED: case to_integer(unsigned(select_in)) is
when 0 =>
data_out <= data_in_a;
when 1 =>
data_out <= data_in_b;
when 2 =>
data_out <= data_in_c;
when 3 =>
data_out <= data_in_d;
when others => --Redundante
end case SELECTED;
end process;
end; | gpl-3.0 |
Xero-Hige/LuGus-VHDL | ghdl/lib/ghdl/src/synopsys/std_logic_misc.vhdl | 2 | 6037 | --------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--library SYNOPSYS;
--use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR; --!V08
--synopsys synthesis_off
--attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
--START-!V08
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
--END-!V08
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--START-!V08
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--END-!V08
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
--START-!V08
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
--END-!V08
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-Gaston/TP1-Contador/bcd_multiplexer.vhd | 1 | 1034 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_multiplexer is
port(
bcd0_input : in std_logic_vector(3 downto 0);
bcd1_input : in std_logic_vector(3 downto 0);
bcd2_input : in std_logic_vector(3 downto 0);
bcd3_input : in std_logic_vector(3 downto 0);
mux_selector : in std_logic_vector (1 downto 0);
mux_output : out std_logic_vector (3 downto 0)
);
end bcd_multiplexer;
architecture bcd_multiplexer_arq of bcd_multiplexer is
begin
process (mux_selector,bcd0_input,bcd1_input,bcd2_input,bcd3_input) is
begin
case mux_selector is
when "00" => mux_output <= bcd0_input;
when "01" => mux_output <= bcd1_input;
when "10" => mux_output <= bcd2_input;
when "11" => mux_output <= bcd3_input;
when others => mux_output <= (others => '0');
end case;
end process;
end bcd_multiplexer_arq;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-Gaston/tp1/bcd_counter/cont_bcd_tb.vhd | 2 | 754 | library ieee;
use ieee.std_logic_1164.all;
entity cont_bcd_tb is
end;
architecture cont_bcd_tb_func of cont_bcd_tb is
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal n_out: std_logic_vector(3 downto 0);
signal c_out: std_logic:='0';
component cont_bcd is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 20 ns;
rst_in <= '0' after 50 ns;
enable_in <= '1' after 60 ns;
contadorBCDMap: cont_bcd port map(
clk => clk_in,
rst => rst_in,
ena => enable_in,
s => n_out,
co => c_out
);
end architecture;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | TP4/UART/mode_decoder.vhd | 1 | 4470 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mode_decoder is
generic(
N: integer:= 6;
M: integer:= 3;
W: integer:= 8
);
port(
clk: in std_logic := '0';
char_in: in std_logic_vector(7 downto 0) := (others => '0');
RxRdy: in std_logic := '0';
mode: out std_logic_vector(1 downto 0) := (others => '0');
angle: out std_logic_vector(31 downto 0) := (others => '0')
);
end mode_decoder;
architecture mode_decoder_arq of mode_decoder is
constant LETTER_R : std_logic_vector(7 downto 0) := "01010010";
constant LETTER_O : std_logic_vector(7 downto 0) := "01001111";
constant LETTER_T : std_logic_vector(7 downto 0) := "01010100";
constant LETTER_SPACE : std_logic_vector(7 downto 0) := "00100000";
constant LETTER_C : std_logic_vector(7 downto 0) := "01000011";
constant LETTER_A : std_logic_vector(7 downto 0) := "01000001";
constant LETTER_H : std_logic_vector(7 downto 0) := "01001000";
constant LETTER_0 : std_logic_vector(7 downto 0) := "00110000";
constant LETTER_1 : std_logic_vector(7 downto 0) := "00110001";
constant LETTER_2 : std_logic_vector(7 downto 0) := "00110010";
constant LETTER_3 : std_logic_vector(7 downto 0) := "00110011";
constant LETTER_4 : std_logic_vector(7 downto 0) := "00110100";
constant LETTER_5 : std_logic_vector(7 downto 0) := "00110101";
constant LETTER_6 : std_logic_vector(7 downto 0) := "00110110";
constant LETTER_7 : std_logic_vector(7 downto 0) := "00110111";
constant LETTER_8 : std_logic_vector(7 downto 0) := "00111000";
constant LETTER_9 : std_logic_vector(7 downto 0) := "00111001";
constant LETTER_ENTER : std_logic_vector(7 downto 0) := "00001010";
constant SINGLE_ROTATION : std_logic_vector(1 downto 0) := "00";
constant CONSTANT_ROTATION_RIGHT : std_logic_vector(1 downto 0) := "11";
constant CONSTANT_ROTATION_LEFT : std_logic_vector(1 downto 0) := "01";
signal rom_out, enable: std_logic;
signal address: std_logic_vector(5 downto 0);
signal font_row, font_col: std_logic_vector(M-1 downto 0);
signal red_in, grn_in, blu_in: std_logic;
signal pixel_row, pixel_col, pixel_col_aux, pixel_row_aux: std_logic_vector(9 downto 0);
signal sig_startTX: std_logic;
function CHAR_TO_NUMBER(INPUT_CHARACTER : std_logic_vector(7 downto 0) := "00000000") return integer is
begin
case( INPUT_CHARACTER ) is
when LETTER_O => return 0;
when LETTER_1 => return 1;
when LETTER_2 => return 2;
when LETTER_3 => return 3;
when LETTER_4 => return 4;
when LETTER_5 => return 5;
when LETTER_6 => return 6;
when LETTER_7 => return 7;
when LETTER_8 => return 8;
when LETTER_9 => return 9;
when others => return 0;
end case ;
end CHAR_TO_NUMBER;
begin
process(RxRdy)
variable step_to_check : integer := 0;
variable valid : boolean := false;
variable tmp_angle : integer := 0;
variable angle_integer_part : std_logic_vector(15 downto 0) := (others => '0');
variable position : integer := 0;
type string_array is array (8 downto 0) of std_logic_vector(7 downto 0);
variable accumm_chars : string_array := (LETTER_R,LETTER_O,LETTER_C,LETTER_SPACE,LETTER_A,LETTER_SPACE,LETTER_0,LETTER_0,LETTER_0);
begin
if(char_in = LETTER_ENTER) then
if(accumm_chars(0) = LETTER_R and
accumm_chars(1) = LETTER_O and
accumm_chars(2) = LETTER_C and
accumm_chars(3) = LETTER_SPACE) then
if(accumm_chars(4) = LETTER_C) then
if(accumm_chars(5) = LETTER_SPACE) then
if(accumm_chars(6) = LETTER_A) then
mode <= CONSTANT_ROTATION_LEFT;
elsif (accumm_chars(6) = LETTER_H) then
mode <= CONSTANT_ROTATION_RIGHT;
end if;
end if;
elsif(accumm_chars(4) = LETTER_A) then
if(accumm_chars(5) = LETTER_SPACE) then
if(position = 8) then --Means that the angle is a 3 digit one
tmp_angle := CHAR_TO_NUMBER(accumm_chars(6)) * 100 + CHAR_TO_NUMBER(accumm_chars(7)) * 10 + CHAR_TO_NUMBER(accumm_chars(8));
else --2 digit angle
tmp_angle := CHAR_TO_NUMBER(accumm_chars(6)) * 10 + CHAR_TO_NUMBER(accumm_chars(7));
end if;
angle_integer_part := std_logic_vector(to_signed(tmp_angle,16));
angle <= angle_integer_part & "0000000000000000";
mode <= SINGLE_ROTATION;
end if;
end if;
end if;
elsif(position > 8) then
valid := false;
else
accumm_chars(position) := char_in;
position := position + 1;
end if;
end process;
end mode_decoder_arq; | gpl-3.0 |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-Gaston/tp1.vhd | 1 | 2352 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tp1 is
port (
clk_in: in std_logic;
rst_in: in std_logic;
clk_anode_ouput: out std_logic_vector(3 downto 0);
clk_led_output: out std_logic_vector(7 downto 0)
);
end;
architecture tp1_arq of tp1 is
signal enabler_output : std_logic := '0';
signal bcd0_out : std_logic_vector(3 downto 0) := (others => '0');
signal bcd1_out : std_logic_vector(3 downto 0) := (others => '0');
signal bcd2_out : std_logic_vector(3 downto 0) := (others => '0');
signal bcd3_out : std_logic_vector(3 downto 0) := (others => '0');
signal co_bcd0 : std_logic := '0';
signal co_bcd1 : std_logic := '0';
signal co_bcd2 : std_logic := '0';
signal co_bcd3 : std_logic := '0';
component led_display_controller is
port (
clk_in: in std_logic;
bcd0: in std_logic_vector(3 downto 0);
bcd1: in std_logic_vector(3 downto 0);
bcd2: in std_logic_vector(3 downto 0);
bcd3: in std_logic_vector(3 downto 0);
anode_output: out std_logic_vector(3 downto 0);
led_output: out std_logic_vector(7 downto 0)
);
end component;
component cont_bcd is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end component;
component generic_enabler is
generic(PERIOD:natural := 1000000 ); --1MHz
port(
clk: in std_logic;
rst: in std_logic;
ena_out: out std_logic
);
end component;
begin
generic_enablerMap: generic_enabler generic map(10000)
port map (
clk => clk_in,
rst => rst_in,
ena_out => enabler_output
);
cont_bcd0Map: cont_bcd port map(
clk => clk_in,
rst => rst_in,
ena => enabler_output,
s => bcd0_out,
co => co_bcd0
);
cont_bcd1Map: cont_bcd port map(
clk => clk_in,
rst => rst_in,
ena => co_bcd0,
s => bcd1_out,
co => co_bcd1
);
cont_bcd2Map: cont_bcd port map(
clk => clk_in,
rst => rst_in,
ena => co_bcd1,
s => bcd2_out,
co => co_bcd2
);
cont_bcd3Map: cont_bcd port map(
clk => clk_in,
rst => rst_in,
ena => co_bcd2,
s => bcd3_out,
co => co_bcd3
);
led_display_controllerMap: led_display_controller port map (
clk_in => clk_in,
bcd0 => bcd0_out,
bcd1 => bcd1_out,
bcd2 => bcd2_out,
bcd3 => bcd3_out,
anode_output => clk_anode_ouput,
led_output => clk_led_output
);
end;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | TP3/addition/class_adder/class_adder_tb.vhd | 1 | 2417 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity class_adder_tb is
end entity;
architecture class_adder_tb_arq of class_adder_tb is
signal number1_in: std_logic_vector(3 downto 0);
signal number2_in: std_logic_vector(3 downto 0);
signal result: std_logic_vector(3 downto 0);
signal cout: std_logic;
signal cin: std_logic;
component class_adder is
generic(N: integer:= 4);
port(
number1_in: in std_logic_vector(N-1 downto 0);
number2_in: in std_logic_vector(N-1 downto 0);
cin: in std_logic;
result: out std_logic_vector(N-1 downto 0);
cout: out std_logic
);
end component;
for class_adder_0: class_adder use entity work.class_adder;
begin
class_adder_0: class_adder
port map(
number1_in => number1_in,
number2_in => number2_in,
result => result,
cout => cout,
cin => cin
);
process
type pattern_type is record
in1 : std_logic_vector(3 downto 0); --input number
in2 : std_logic_vector(3 downto 0); --output
cin : std_logic;
r: std_logic_vector(3 downto 0); --output mantisa
co : std_logic; --output exponent
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
("1111", "1111",'0', "1110", '1'),
("0000", "0000",'1', "0001", '0'),
(std_logic_vector(to_unsigned(2,4)), std_logic_vector(to_unsigned(2,4)),'0', std_logic_vector(to_unsigned(4,4)), '0'),
(std_logic_vector(to_unsigned(4,4)), std_logic_vector(to_unsigned(4,4)),'0', std_logic_vector(to_unsigned(8,4)), '0')
);
begin
for i in patterns'range loop
-- Set the inputs.
number1_in <= patterns(i).in1;
number2_in <= patterns(i).in2;
cin <= patterns(i).cin;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert cout = patterns(i).co report "BAD CARRY: " & std_logic'image(cout) & ", ON " & integer'image(to_integer(unsigned(number1_in))) & " + " & integer'image(to_integer(unsigned(number2_in))) severity error;
assert result = patterns(i).r report "BAD RESULT: " & integer'image(to_integer(unsigned(result))) & ", ON " & integer'image(to_integer(unsigned(number1_in))) & " + " & integer'image(to_integer(unsigned(number2_in))) severity error;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
| gpl-3.0 |
ruygargar/LCSE_lab | PIC/tb_PICtop.vhd | 1 | 2050 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
use work.PIC_pkg.all;
use work.RS232_test.all;
entity PICtop_tb is
end PICtop_tb;
architecture TestBench of PICtop_tb is
component PICtop
port (
Reset : in std_logic;
Clk : in std_logic;
RS232_RX : in std_logic;
RS232_TX : out std_logic;
switches : out std_logic_vector(7 downto 0);
Temp_L : out std_logic_vector(6 downto 0);
Temp_H : out std_logic_vector(6 downto 0));
end component;
-----------------------------------------------------------------------------
-- Internal signals
-----------------------------------------------------------------------------
signal Reset : std_logic;
signal Clk : std_logic;
signal RS232_RX : std_logic;
signal RS232_TX : std_logic;
signal switches : std_logic_vector(7 downto 0);
signal Temp_L : std_logic_vector(6 downto 0);
signal Temp_H : std_logic_vector(6 downto 0);
begin -- TestBench
UUT: PICtop
port map (
Reset => Reset,
Clk => Clk,
RS232_RX => RS232_RX,
RS232_TX => RS232_TX,
switches => switches,
Temp_L => Temp_L,
Temp_H => Temp_H);
-----------------------------------------------------------------------------
-- Reset & clock generator
-----------------------------------------------------------------------------
Reset <= '0', '1' after 75 ns;
p_clk : PROCESS
BEGIN
clk <= '1', '0' after 25 ns;
wait for 50 ns;
END PROCESS;
-------------------------------------------------------------------------------
-- Sending some stuff through RS232 port
-------------------------------------------------------------------------------
SEND_STUFF : process
begin
RS232_RX <= '1';
wait for 40 us;
Transmit(RS232_RX, X"49");
wait for 40 us;
Transmit(RS232_RX, X"34");
wait for 40 us;
Transmit(RS232_RX, X"31");
wait;
end process SEND_STUFF;
end TestBench;
| gpl-3.0 |
Xero-Hige/LuGus-VHDL | TP4/arctg_lut/arctg_lut_tb.vhd | 1 | 1321 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity arctg_lut_tb is
end entity;
architecture arctg_lut_tb_arq of arctg_lut_tb is
signal step_index : integer := 0;
signal angle : std_logic_vector(31 downto 0) := (others => '0');
component arctg_lut is
generic(TOTAL_BITS: integer := 32);
port(
step_index: in integer := 0;
angle: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
for arctg_lut_0 : arctg_lut use entity work.arctg_lut;
begin
arctg_lut_0 : arctg_lut
generic map(TOTAL_BITS => 32)
port map(
step_index => step_index,
angle => angle
);
process
type pattern_type is record
i : integer;
a : std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
(0,"00000000001011010000000000000000"),
(15,"00000000000000000000000001110010")
);
begin
for i in patterns'range loop
-- Set the inputs.
step_index <= patterns(i).i;
wait for 1 ns;
assert patterns(i).a = angle report "BAD ANGLE, GOT: " & integer'image(to_integer(unsigned(angle)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
| gpl-3.0 |
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