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ruygargar/LCSE_lab | uc/uc.vhd | 1 | 11158 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06:17:01 01/26/2014
-- Design Name:
-- Module Name: uc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.PIC_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uc is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
ROM_Data : in STD_LOGIC_VECTOR (11 downto 0);
ROM_Address : out STD_LOGIC_VECTOR (11 downto 0);
Databus : out STD_LOGIC_VECTOR (7 downto 0);
RAM_Address : out STD_LOGIC_VECTOR (7 downto 0);
RAM_CS : out STD_LOGIC;
RAM_WE : out STD_LOGIC;
RAM_OE : out STD_LOGIC;
ALU_Operation : out alu_op;
ALU_Index : in STD_LOGIC_VECTOR (7 downto 0);
Flag_Z : in STD_LOGIC;
Flag_C : in STD_LOGIC;
Flag_N : in STD_LOGIC;
Flag_E : in STD_LOGIC;
DMA_RQ : in STD_LOGIC;
DMA_ACK : out STD_LOGIC;
Send : out STD_LOGIC;
DMA_Ready : in STD_LOGIC);
end uc;
architecture pipelined of uc is
-- Fetch signals.
signal I_data_i, I_add_i : std_logic_vector(11 downto 0);
signal PC_reg, PC_in : std_logic_vector(11 downto 0);
signal IR_reg : std_logic_vector(11 downto 0);
signal LT_latch : std_logic_vector(11 downto 0);
signal LN : std_logic; -- Literal Needed.
signal PC1, jump_address, no_jump_address : std_logic_vector(11 downto 0);
signal jumping : std_logic;
-- Decode signals.
signal Jump_reg, Jump_in : std_logic;
signal JumpC_reg, JumpC_in : std_logic;
signal A_op_reg, A_op_in : alu_op;
signal D_ctl_reg, D_ctl_in : std_logic_vector(2 downto 0); -- CS&WE&OE
signal D_valid_reg, D_valid_in : std_logic;
signal IDN : std_logic; -- Index Needed.
signal D_data_reg, D_data_in : std_logic_vector(7 downto 0);
signal D_add_aux, D_add_aux_id : std_logic_vector(7 downto 0);
signal D_add_reg, D_add_in : std_logic_vector(7 downto 0);
signal jump_add_reg : std_logic_vector(11 downto 0);
signal start_send_reg, start_send_in : std_logic;
-- Execute signals.
signal NVD_reg : std_logic; -- Not Valid Data.
signal BR : std_logic; -- Buses Released.
signal RAM_Address_i : std_logic_vector(7 downto 0);
signal RAM_CS_i : std_logic;
signal RAM_WE_i : std_logic;
signal RAM_OE_i : std_logic;
-- FSM Send/DMA_RQ Controller.
type FSM_state is (idle, SND_free, SND_wait, SND_catch,
DMA_wait_non_jumpc, DMA_free, DMA_wait, DMA_catch);
signal FSM_now, FSM_next : FSM_state;
signal FF_enable : std_logic;
begin
-- Fetch Stage Logic:
I_data_i <= ROM_Data;
ROM_Address <= I_add_i;
-- -- Program Counter and Instruction Register.
process(Clk, Reset, PC_in, I_data_i)
begin
if Reset = '0' then
PC_reg <= X"000";
IR_reg <= X"000";
elsif Clk'event and Clk = '1' then
if FF_enable = '1' then
PC_reg <= PC_in;
IR_reg <= I_data_i;
end if;
end if;
end process;
-- -- Latch used to store the literal in 2-word instructions.
process(Clk, LN, I_data_i, LT_latch)
begin
if Clk = '1' and LN = '1' then
LT_latch <= I_data_i;
else
LT_latch <= LT_latch;
end if;
end process;
-- -- Next PC and ROM Address combinational logic.
PC1 <= PC_reg + X"001";
jump_address <= jump_add_reg;
no_jump_address <= PC1 when (Clk = '0' and LN = '1')
else PC_reg;
I_add_i <= jump_address when jumping = '1'
else no_jump_address;
PC_in <= I_add_i + X"001";
-- Decode Stage Logic:
-- -- Internal Pipeline's Registers.
process(Clk, Reset)
begin
if Reset = '0' then
A_op_reg <= nop;
Jump_reg <= '0';
JumpC_reg <= '0';
D_ctl_reg <= "000";
D_valid_reg <= '0';
D_data_reg <= X"00";
D_add_reg <= X"00";
jump_add_reg <= X"000";
start_send_reg <= '0';
elsif Clk'event and Clk = '1' then
if FF_enable = '1' then
A_op_reg <= A_op_in;
Jump_reg <= Jump_in;
JumpC_reg <= JumpC_in;
D_ctl_reg <= D_ctl_in;
D_valid_reg <= D_valid_in;
D_data_reg <= D_data_in;
D_add_reg <= D_add_in;
jump_add_reg <= LT_latch;
start_send_reg <= start_send_in;
end if;
end if;
end process;
-- -- Combinational Microinstruction Decoder.
process(IR_reg)
begin
A_op_in <= nop;
Jump_in <= '0';
JumpC_in <= '0';
D_ctl_in <= "000";
D_valid_in <= '1';
LN <= '0';
IDN <= '0';
start_send_in <= '0';
case IR_reg(7 downto 6) is
when TYPE_1 =>
case IR_reg(5 downto 0) is
when ALU_ADD => A_op_in <= op_add;
when ALU_SUB => A_op_in <= op_sub;
when ALU_SHIFTL => A_op_in <= op_shiftl;
when ALU_SHIFTR => A_op_in <= op_shiftr;
when ALU_AND => A_op_in <= op_and;
when ALU_OR => A_op_in <= op_or;
when ALU_XOR => A_op_in <= op_xor;
when ALU_CMPE => A_op_in <= op_cmpe;
when ALU_CMPG => A_op_in <= op_cmpg;
when ALU_CMPL => A_op_in <= op_cmpl;
when ALU_ASCII2BIN => A_op_in <= op_ascii2bin;
when ALU_BIN2ASCII => A_op_in <= op_bin2ascii;
when others =>
end case;
when TYPE_2 =>
LN <= '1';
case IR_reg(5 downto 0) is
when JMP_UNCOND => Jump_in <= '1';
when JMP_COND => JumpC_in <= '1';
when others =>
end case;
when TYPE_3 =>
case IR_reg(5 downto 0) is
-- LD entre registros.
when LD&SRC_ACC&DST_A => A_op_in <= op_mvacc2a;
when LD&SRC_ACC&DST_B => A_op_in <= op_mvacc2b;
when LD&SRC_ACC&DST_INDX => A_op_in <= op_mvacc2id;
-- LD en registros desde dato literal.
when LD&SRC_CONSTANT&DST_A => A_op_in <= op_lda;
LN <= '1';
when LD&SRC_CONSTANT&DST_B => A_op_in <= op_ldb;
LN <= '1';
when LD&SRC_CONSTANT&DST_ACC => A_op_in <= op_ldacc;
LN <= '1';
when LD&SRC_CONSTANT&DST_INDX => A_op_in <= op_ldid;
LN <= '1';
-- LD en registros desde dirección de memoria literal.
when LD&SRC_MEM&DST_A => A_op_in <= op_lda;
LN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
when LD&SRC_MEM&DST_B => A_op_in <= op_ldb;
LN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
when LD&SRC_MEM&DST_ACC => A_op_in <= op_ldacc;
LN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
when LD&SRC_MEM&DST_INDX => A_op_in <= op_ldid;
LN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
-- LD en registros desde dirección de memoria indexada.
when LD&SRC_INDXD_MEM&DST_A => A_op_in <= op_lda;
LN <= '1';
IDN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
when LD&SRC_INDXD_MEM&DST_B => A_op_in <= op_ldb;
LN <= '1';
IDN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
when LD&SRC_INDXD_MEM&DST_ACC => A_op_in <= op_ldacc;
LN <= '1';
IDN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
when LD&SRC_INDXD_MEM&DST_INDX => A_op_in <= op_ldid;
LN <= '1';
IDN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
-- WR desde registro ACC en memoria literal.
when WR&SRC_ACC&DST_MEM => A_op_in <= op_oeacc;
LN <= '1';
D_valid_in <= '0';
D_ctl_in <= "110";
-- WR desde registro ACC en memoria indexada.
when WR&SRC_ACC&DST_INDXD_MEM => A_op_in <= op_oeacc;
LN <= '1';
IDN <= '1';
D_valid_in <= '0';
D_ctl_in <= "110";
when others =>
end case;
when TYPE_4 =>
start_send_in <= '1';
when others =>
end case;
end process;
D_data_in <= LT_latch(7 downto 0);
D_add_aux <= LT_latch(7 downto 0);
D_add_aux_id <= LT_latch(7 downto 0) + ALU_Index;
D_add_in <= D_add_aux_id when IDN = '1'
else D_add_aux;
-- Execute Stage Logic:
jumping <= Jump_reg or (JumpC_reg and Flag_Z);
process(Clk, Reset)
begin
if Reset = '0' then
NVD_reg <= '0';
elsif Clk'event and Clk = '1' then
if FF_enable = '1' then
NVD_reg <= jumping;
end if;
end if;
end process;
ALU_Operation <= A_op_reg when NVD_reg = '0'
else nop;
Databus <= D_data_reg(7 downto 0) when (D_valid_reg = '1' and BR = '0')
else (others => 'Z');
RAM_Address_i <= D_add_reg;
RAM_Address <= RAM_Address_i when BR = '0'
else (others => 'Z');
RAM_CS_i <= D_ctl_reg(2) when NVD_reg = '0'
else '0';
RAM_CS <= RAM_CS_i when BR = '0'
else 'Z';
RAM_WE_i <= D_ctl_reg(1) when NVD_reg = '0'
else '0';
RAM_WE <= RAM_WE_i when BR = '0'
else 'Z';
RAM_OE_i <= D_ctl_reg(0) when NVD_reg = '0'
else '0';
RAM_OE <= RAM_OE_i when BR = '0'
else 'Z';
-- FSM Send/DMA Ack Controller:
process(Clk, Reset)
begin
if Reset <= '0' then
FSM_now <= idle;
elsif Clk'event and Clk = '1' then
FSM_now <= FSM_next;
end if;
end process;
process(FSM_now, start_send_reg, DMA_Ready, DMA_RQ)
begin
BR <= '0';
FF_enable <= '1';
Send <= '0';
DMA_ACK <= '0';
case FSM_now is
when idle =>
if start_send_reg = '1' then
FSM_next <= SND_free;
elsif DMA_RQ = '1' then
FSM_next <= DMA_wait_non_jumpc;
else
FSM_next <= idle;
end if;
when SND_free =>
FF_enable <= '0';
Send <= '1';
if DMA_Ready <= '0' then
FSM_next <= SND_wait;
else
FSM_next <= SND_free;
end if;
when SND_wait =>
BR <= '1';
FF_enable <= '0';
Send <= '1';
if DMA_Ready <= '1' then
FSM_next <= SND_catch;
else
FSM_next <= SND_wait;
end if;
when SND_catch =>
BR <= '1';
FF_enable <= '0';
Send <= '0';
FSM_next <= idle;
when DMA_wait_non_jumpc =>
if JumpC_in = '1' then
FSM_next <= DMA_wait_non_jumpc;
else
FSM_next <= DMA_free;
end if;
when DMA_free =>
DMA_ACK <= '1';
FSM_next <= DMA_wait;
when DMA_wait =>
BR <= '1';
FF_enable <= '0';
DMA_ACK <= '1';
if DMA_RQ <= '0' then
FSM_next <= DMA_catch;
else
FSM_next <= DMA_wait;
end if;
when DMA_catch =>
BR <= '1';
FF_enable <= '0';
DMA_ACK <= '0';
FSM_next <= idle;
end case;
end process;
end pipelined;
| gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/03CAMARA/Version_01/02 verilog/frame_buffer.vhd | 1 | 5977 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file frame_buffer.vhd when simulating
-- the core, frame_buffer. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY frame_buffer IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END frame_buffer;
ARCHITECTURE frame_buffer_a OF frame_buffer IS
-- synthesis translate_off
COMPONENT wrapped_frame_buffer
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_frame_buffer USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 19,
c_addrb_width => 19,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "zynq",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 307200,
c_read_depth_b => 307200,
c_read_width_a => 12,
c_read_width_b => 12,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 307200,
c_write_depth_b => 307200,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 12,
c_write_width_b => 12,
c_xdevicefamily => "zynq"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_frame_buffer
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END frame_buffer_a;
| gpl-3.0 |
INTI-CMNB-FPGA/fpga_helpers | examples/mpf300eval/mpf300eval.vhdl | 4 | 411 | library IEEE;
use IEEE.std_logic_1164.all;
library Examples;
use Examples.examples.all;
entity Top is
port (
clk_i : in std_logic;
led_o : out std_logic
);
end entity Top;
architecture Structural of Top is
constant FREQ : positive := 50e6;
begin
dut: Blinking
generic map (FREQ => FREQ, SECS => 1)
port map (clk_i => clk_i, led_o => led_o);
end architecture Structural;
| gpl-3.0 |
INTI-CMNB-FPGA/fpga_helpers | examples/s6micro/s6micro.vhdl | 4 | 411 | library IEEE;
use IEEE.std_logic_1164.all;
library Examples;
use Examples.examples.all;
entity Top is
port (
clk_i : in std_logic;
led_o : out std_logic
);
end entity Top;
architecture Structural of Top is
constant FREQ : positive := 50e6;
begin
dut: Blinking
generic map (FREQ => FREQ, SECS => 1)
port map (clk_i => clk_i, led_o => led_o);
end architecture Structural;
| gpl-3.0 |
zhangry868/MIPSCPU | PipelineTimeSimulation/simulation/modelsim/rtl_work/@num@expansion/_primary.vhd | 1 | 288 | library verilog;
use verilog.vl_types.all;
entity NumExpansion is
port(
Imm : in vl_logic_vector(15 downto 0);
Ex_top : in vl_logic_vector(1 downto 0);
Immediate32 : out vl_logic_vector(31 downto 0)
);
end NumExpansion;
| gpl-3.0 |
zhangry868/MIPSCPU | PipelineTimeSimulation/simulation/modelsim/rtl_work/@p@c/_primary.vhd | 1 | 249 | library verilog;
use verilog.vl_types.all;
entity PC is
port(
Clk : in vl_logic;
PC_in : in vl_logic_vector(31 downto 0);
PC_out : out vl_logic_vector(31 downto 0)
);
end PC;
| gpl-3.0 |
zhangry868/MIPSCPU | PipelineTimeSimulation/simulation/modelsim/rtl_work/@instru@memory/_primary.vhd | 1 | 637 | library verilog;
use verilog.vl_types.all;
entity InstruMemory is
generic(
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 32
);
port(
data : in vl_logic_vector;
addr : in vl_logic_vector;
we : in vl_logic_vector(3 downto 0);
clk : in vl_logic;
q : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1;
attribute mti_svvh_generic_type of ADDR_WIDTH : constant is 1;
end InstruMemory;
| gpl-3.0 |
zhangry868/MIPSCPU | PipelineTimeSimulation/simulation/modelsim/rtl_work/@judge@bit/_primary.vhd | 2 | 218 | library verilog;
use verilog.vl_types.all;
entity JudgeBit is
port(
NumIn : in vl_logic_vector(31 downto 0);
Num : out vl_logic_vector(31 downto 0)
);
end JudgeBit;
| gpl-3.0 |
behzady/ManoBasicComputer | Computer.vhd | 1 | 5202 | --Part of Mano Basic Computer
--Behzad Mokhtari; [email protected]
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--Basic Computer
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity basicMano is
generic(CLK_period:TIME := 100 ns);
port(
CLK : in std_logic;
MEM :buffer word;
PC :buffer word;
DR :buffer word;
AC :buffer word;
IR :buffer word;
TR :buffer word;
BUSo:buffer word;
AR :buffer adr ;
INPR: in std_logic_vector(7 downto 0);
OUTR: out std_logic_vector(7 downto 0);
FGI : buffer std_logic;
FGO : buffer std_logic;
sFGI: in std_logic:='0';
sFGO: in std_logic:='0'
);
end basicMano;
architecture Scheme of basicMano is
signal init: std_logic;
signal I, R, E, IEN, S:std_logic;
signal Ij, Rj, Ej, IENj, Sj, FGIj, FGOj:std_logic;
signal Ik, Rk, Ek, IENk, Sk, FGIk, FGOk:std_logic;
signal T, D:std_logic_vector(7 downto 0);
signal B:std_logic_vector(11 downto 0);
signal MEMld, ARld, PCld, DRld, ACld, IRld, TRld:std_logic;
signal ARinc, PCinc, DRinc, ACinc, TRinc:std_logic;
signal ARclr, PCclr, ACclr, SCclr:std_logic;
signal ACin:word;
signal OUTRld:std_logic;
signal rPC, rMEM, rIR, rTR, rAC, rAR, rDR:std_logic;
signal BUSs:ctrlBUS;
signal G, P:std_logic;
signal cAND, cADD, cDR, cINR, cCOM, cSHR, cSHL:std_logic;
signal Z, N:std_logic;
signal Eo:std_logic;
begin
Iff: flipflopJK port map(Ij, Ik, CLK, init, I);
Rff: flipflopJK port map(Rj, Rk, CLK, init, R);
Eff: flipflopJK port map(Ej, Ek, CLK, init, E);
IENff: flipflopJK port map(IENj, IENk, CLK, init, IEN);
Sff: flipflopJK port map(Sj, Sk, CLK, init, S);
FGIff: flipflopJK port map(FGIj, FGIk, CLK, init, FGI);
FGOff: flipflopJK port map(FGOj, FGOk, CLK, init, FGO);
MEMM: Memory port map(CLK, AR, S, MEMld, BUSo, MEM);
ARR: reg generic map(width => sizeof_Adr)
port map(ARinc, ARld, ARclr, CLK, BUSo(11 downto 0), AR);
PCR: reg port map(PCinc, PCld, PCclr, CLK, BUSo, PC);
DRR: reg port map(DRinc, DRld, init, CLK, BUSo, DR);
ACR: reg port map(ACinc, ACld, ACclr, CLK, ACin, AC);
IRR: reg port map('0', IRld, init, CLK, BUSo, IR);
TRR: reg port map('0', TRld, init, CLK, BUSo, TR);
OUTRR: reg generic map(width => 8)
port map('0', OUTRld, init, CLK, BUSo(7 downto 0), OUTR);
ALUM: ALU port map(E, Eo, INPR, AC, DR, ACin,
cAND, cADD, cDR, cINR, cCOM, cSHR, cSHL);
SCT: Timer port map(CLK, SCclr, S, T);
BUSP: busLine port map(AR, PC, DR, AC, IR, TR, MEM, BUSs, BUSo);
DD: Decoder generic map(N => 3)
port map(IR(14 downto 12), '1', D);
G <= D(7) and (not I) and T(3);
P <= D(7) AND I and T(3);
B <= IR(11 downto 0);
N <= ACin(15);
Z <= '1' when ACin = "0000000000000000" else '0';
--MEM
MEMld <= (R and T(1)) or ((D(3) or D(5)) and T(4)) or (D(6) and T(6));
--AR
ARld <= ((T(0) or T(2)) and (not R)) or ((not D(7)) and I and T(3));
ARinc <= D(5) and T(4);
ARclr <= (R and T(0)) or init;
--PC
PCld <= (D(4) and T(4)) or (D(5) and T(5));
PCinc <= ((not R) and T(1)) or (R and T(2)) or (D(6) and T(6) and Z) or
(((B(4) and (not N)) or (B(3) and N) or (B(2) and Z) or (B(1) and (not E))) and G) or
(((B(9) and FGI) or (B(8) and FGO)) and P);
PCclr <= (R and T(1)) or init;
--DR
DRld <= T(4) and (D(0) or D(1) or D(2) or D(6));
DRinc <= T(5) and D(6);
--AC
ACld <= (T(5) and (D(0) or D(1) or D(2))) or (G and B(9)) or (P and B(11));
ACinc <= G and B(5);
ACclr <= (G and B(11)) or init;
--IR
IRld <= T(1) and (not R);
--TR
TRld <= T(0) and R;
--OUTR
OUTRld <= P and B(10);
--SC
SCclr <= (R and T(2)) or (T(5) and (D(0) or D(1) or D(2) or D(5))) or
(T(4) and (D(3) or D(4))) or G or P or init or (not S);
--I
Ij <= (T(2) and (not R)) and IR(15);
Ik <= (T(2) and (not R)) and (not IR(15));
--R
Rj <= IEN and (FGI or FGO) and (not (T(0) or T(1) or T(2)));
Rk <= R and T(2);
--E
Ej <= (((D(1) and T(5)) or (G and (B(7) or B(6)))) and Eo) or (G and B(8) and E);
Ek <= (((D(1) and T(5)) or (G and (B(7) or B(6)))) and (not Eo)) or (G and (B(10) or (B(8) and E)));
--IEN
IENj <= P and B(7);
IENk <= (R and T(2)) or (P and B(6));
--S
Sj <= not B(0);
Sk <= G and B(0);
--FGIO
FGIj <= sFGI;
FGIK <= P and B(11);
FGOj <= sFGO;
FGOK <= P and B(10);
--ALU
cAND <= D(0) and T(5);
cADD <= D(1) and T(5);
cDR <= (D(2) and T(5)) or (D(6) and T(6));
cINR <= P and B(11);
cCOM <= G and B(9);
cSHR <= G and B(7);
cSHL <= G and B(6);
--BUS
rMEM <= (T(1) and (not R)) or (T(3) and I and (not D(7))) or
(T(4) and (D(0) or D(1) or D(2) or D(6)));
rPC <= T(0) or (D(5) and T(4));
rIR <= T(2) and (not R);
rTR <= R and T(1);
rAC <= (D(3) and T(4)) or (P and B(10));
rAR <= (D(4) and T(4)) or (D(5) and T(5));
rDR <= D(6) and T(6);
BUSs(2) <= rMEM or rIR or rTR or rAC;
BUSs(1) <= rPC or rMEM or rTR or rDR;
BUSs(0) <= rMEM or rIR or rAR or rDR;
START: process
begin
init <= '1';
wait until CLK = '0';
wait until CLK'event;
init <= '0';
wait;
end process START;
end Scheme; | gpl-3.0 |
INTI-CMNB-FPGA/fpga_helpers | test/fake-project/lib1/com2_pkg1_lib1.vhdl | 1 | 424 | library IEEE;
use IEEE.std_logic_1164.all;
library LIB1;
use LIB1.pkg1_lib1.all;
entity com2_pkg1_lib1 is
port (
data_i : in std_logic;
data_o : out std_logic
);
end entity com2_pkg1_lib1;
architecture RTL of com2_pkg1_lib1 is
begin
inst: com1_pkg1_lib1
generic map (WITH_GENERIC => FALSE)
port map (
data_i => data_i,
data_o => data_o
);
end architecture RTL;
| gpl-3.0 |
zhangry868/MIPSCPU | PipelineTimeSimulation/simulation/modelsim/gate_work/pipeline_vlg_tst/_primary.vhd | 2 | 92 | library verilog;
use verilog.vl_types.all;
entity pipeline_vlg_tst is
end pipeline_vlg_tst;
| gpl-3.0 |
shibumi/University | VHDL/Aufgabe3.3.vhdl | 2 | 468 | --Gatterschaltung zu Aufgabe 3.3
--Christian Rebischke 30.4.2014
-- x Eingänge, y Ausgang, z "zwischenstationen"
library IEEE;
use IEEE.std_logic_1164.all;
entity Gatterschaltung is
port(x: in STD_LOGIC_VECTOR(4 DOWNTO 1);
y: out STD_LOGIC);
end entity;
architecture test of Gatterschaltung is
signal z: STD_LOGIC;
begin
z <= (x(1) and not x(2)) or (x(2) and x(3)) after 1 ns;
y <= (z and not x(4)) or (x(4) and x(3)) after 1 ns;
end architecture;
| gpl-3.0 |
ARC-Lab-UF/window_gen | template/template.vhd | 1 | 13598 | -- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- This file provides a template for integrating the window generator into
-- a datapath. Note that this is not a functional example and is instead
-- used solely for explaining how to interface an input source with the
-- generator, and how to handle outputs from the generator.
--
-- The code has various TODO markers that should be updated when using a
-- specific application.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.math_custom.all;
use work.window_gen_pkg.all;
entity template is
generic (
IN_RAM_WORDS : positive;
OUT_RAM_WORDS : positive;
IN_DATA_WIDTH : positive;
OUT_DATA_WIDTH : positive;
MAX_WINDOW_ROWS : positive;
MAX_WINDOW_COLS : positive;
MAX_IMAGE_ROWS : positive;
MAX_IMAGE_COLS : positive;
NUM_PIPELINES : positive);
port (
clk : in std_logic;
rst : in std_logic;
go : in std_logic;
window_rows : in std_logic_vector(bitsNeeded(MAX_WINDOW_ROWS)-1 downto 0);
window_cols : in std_logic_vector(bitsNeeded(MAX_WINDOW_COLS)-1 downto 0);
image_cols : in std_logic_vector(bitsNeeded(MAX_IMAGE_COLS)-1 downto 0);
image_rows : in std_logic_vector(bitsNeeded(MAX_IMAGE_ROWS)-1 downto 0)
-- TODO: add application specific I/O
);
end template;
architecture default of template is
constant WINDOW_BITS : positive := MAX_WINDOW_ROWS*MAX_WINDOW_COLS*IN_DATA_WIDTH;
-- 2D array representing a window
type window_t is array(0 to MAX_WINDOW_ROWS-1, 0 to MAX_WINDOW_COLS-1) of std_logic_vector(IN_DATA_WIDTH-1 downto 0);
-- 1D array of 2D windows
type window_array_t is array (0 to NUM_PIPELINES-1) of window_t;
-- a huge vectorized version of all NUM_PIPELINE windows
signal wg_out : std_logic_vector(MAX_WINDOW_ROWS*(MAX_WINDOW_COLS+NUM_PIPELINES-1)*IN_DATA_WIDTH-1 downto 0);
-- all of the windows in 2D format
signal windows : window_array_t;
signal window_valid : std_logic_vector(NUM_PIPELINES-1 downto 0);
signal wg_done : std_logic;
signal wg_empty : std_logic;
signal wg_ready : std_logic;
signal read_windows : std_logic;
signal input_valid : std_logic;
signal pipe_valid_in : std_logic_vector(NUM_PIPELINES-1 downto 0);
signal in_ram_wen : std_logic;
signal in_ram_waddr : std_logic_vector(bitsNeeded(IN_RAM_WORDS)-1 downto 0);
signal in_ram_wdata : std_logic_vector(IN_DATA_WIDTH-1 downto 0);
signal in_ram_raddr : std_logic_vector(bitsNeeded(IN_RAM_WORDS)-1 downto 0);
signal in_ram_rdata : std_logic_vector(IN_DATA_WIDTH-1 downto 0);
signal out_ram_wen : std_logic;
signal out_ram_waddr : std_logic_vector(bitsNeeded(OUT_RAM_WORDS)-1 downto 0);
signal out_ram_wdata : std_logic_vector(OUT_DATA_WIDTH-1 downto 0);
signal out_ram_raddr : std_logic_vector(bitsNeeded(OUT_RAM_WORDS)-1 downto 0);
signal out_ram_rdata : std_logic_vector(OUT_DATA_WIDTH-1 downto 0);
type state_t is (WAIT_FOR_GO, GENERATE_ADDRESS);
signal state : state_t;
-----------------------------------------------------------------------
-- Procedure devectorizeWindow
-- Description: convert a 1D vectorized representation of an output window
-- into a corresponding 2D array for easier processing. Note
-- that this always determines a window of size
-- MAX_WINDOW_ROWS X MAX_WINDOW_COLS. For smaller windows,
-- just ignore the extra rows and columns.
--
-- Parameters:
-- vector : The 1D-vectorized version of the 2D array, stored in row-major
-- order. Index (0,0) starts at the MSB in the vector, with the
-- LSB storing the end of index (total_rows-1, total_cols-1)
-- window : the window as a 2D array (t_window)
-- index : In case multiple windows are specified in the output, index
-- specifies which one to get
--
-- Preconditions: index < PARALLEL_IO, vector must be the
-- appropriate size with data stored as described above.
-----------------------------------------------------------------------
procedure devectorizeWindow(signal vector : std_logic_vector;
window : out window_t;
index : natural) is
begin
for i in 0 to MAX_WINDOW_ROWS-1 loop
for j in index to MAX_WINDOW_COLS+index-1 loop
window(i, j-index) := getVectorElement(vector, i, j, MAX_WINDOW_ROWS, MAX_WINDOW_COLS+NUM_PIPELINES-1, IN_DATA_WIDTH);
end loop;
end loop;
end devectorizeWindow;
begin -- STR
-------------------------------------------------------------------------
-- Input Source
-- Notes: Inputs can be provided to the sliding-window generator from
-- potentially any source. In this example, we instantiate a block RAM with
-- a word width equivalent to the number of replicated pipelines we would
-- like to use. For example, if NUM_PIPELINES is 4, this RAM can provide 4
-- inputs to the window generator every cycle, which will later output up
-- to 4 windows per cycle.
--
-- If using an external RAM as the input source, this RAM would likely be
-- replaced with a FIFO that has a read port width of the same size as this
-- RAM word width. In most cases, that FIFO will have a write port width
-- equivalent to the width of the external memory's data bus. For example,
-- if reading from a memory with a 128-bit data bus into a window generator
-- that reads 64 bits per cycle, you would use a FIFO with a 128-bit write
-- port and 64-bit read port.
--
-- A third possibility for the input source is to connect the window
-- generator directly to the output of another entity. e.g. a chain
-- of filters, where each filter uses a sliding-window generator followed
-- by a pipeline that provides input to the next window generator.
-------------------------------------------------------------------------
U_INPUT_RAM : entity work.RAM(SYNC_READ)
generic map(
num_words => IN_RAM_WORDS,
word_width => IN_DATA_WIDTH*NUM_PIPELINES,
addr_width => bitsNeeded(IN_RAM_WORDS))
port map (
clk => clk,
wen => in_ram_wen,
waddr => in_ram_waddr,
wdata => in_ram_wdata,
raddr => in_ram_raddr,
rdata => in_ram_rdata);
-- example addressing logic for the input RAM
-- The exact logic depends on the type input source, the timing of the
-- input source, etc. This example is simply meant to illustrate the
-- basic concept for generating an input stream for the for the window
-- generator.
process(clk, rst)
begin
if (rst = '1') then
in_ram_raddr <= (others => '0');
input_valid <= '0';
state <= WAIT_FOR_GO;
elsif (rising_edge(clk)) then
case state is
when WAIT_FOR_GO =>
in_ram_raddr <= (others => '0');
input_valid <= '0';
if (go = '1') then
state <= GENERATE_ADDRESS;
end if;
when GENERATE_ADDRESS =>
if (wg_ready = '1') then
in_ram_raddr <= std_logic_vector(unsigned(in_ram_raddr) + 1);
-- TODO: Update timing depending on latency of input source
input_valid <= '1';
end if;
-- TODO: Add completion logic
when others => null;
end case;
end if;
end process;
-------------------------------------------------------------------------
-- Sliding-window generator
-------------------------------------------------------------------------
U_WINDOW_GEN : entity work.window_gen
generic map (
PARALLEL_IO => NUM_PIPELINES,
MAX_WINDOW_ROWS => MAX_WINDOW_ROWS,
MAX_WINDOW_COLS => MAX_WINDOW_COLS,
MAX_IMAGE_ROWS => MAX_IMAGE_ROWS,
MAX_IMAGE_COLS => MAX_IMAGE_COLS,
INPUT0_AT_MSB => false, -- RAM likely stores first input at LSB
DATA_WIDTH => IN_DATA_WIDTH)
port map (
clk => clk,
rst => rst,
go => go,
ready => wg_ready,
read_enable => read_windows,
empty => wg_empty,
image_rows => image_rows,
image_cols => image_cols,
window_rows => window_rows,
window_cols => window_cols,
input => in_ram_rdata, -- input from RAM
input_valid => input_valid, -- TODO: Make sure this logic is timed
-- appropriately.
output => wg_out,
window_valid => window_valid,
done => wg_done
);
-- The output of the window buffer is a huge std_logic_vector that
-- represents all NUM_PIPELINES windows. This code converts the huge vector
-- into an 2D array representation that is easier to work with.
--
-- This would be made much easier by VHDL 2008, where the generator could
-- output this array itself. Once 2008 is more widely supported, we plan to
-- add a 2008 wrapper around the window generator to provide a more
-- convenient interface.
process(wg_out)
variable temp_window : window_t;
begin
for i in 0 to NUM_PIPELINES-1 loop
devectorizeWindow(wg_out, temp_window, i);
windows(i) <= temp_window;
end loop;
end process;
-- read/remove the current windows when the generator isn't empty
-- TODO: add pipeline enable here if necessary (e.g. likely shouldn't read
-- if the pipeline is stalled)
read_windows <= not wg_empty;
-------------------------------------------------------------------------
-- Replicated Pipelines
-- TODO: Add sliding-window function here for each window.
-------------------------------------------------------------------------
U_PIPELINES : for i in 0 to NUM_PIPELINES-1 generate
-- determine the validity of each pipeline input (i.e. window)
-- TODO: add pipeline enable here if necessary (e.g., if the window
-- wasn't read from the generator, you might not want to tell the
-- pipeline the input is valid)
pipe_valid_in(i) <= window_valid(i);
-- TODO: INSTANTIATE SLIDING-WINDOW FUNCTION PIPELINES
-- FOR EACH WIDOW window(i)
end generate;
-------------------------------------------------------------------------
-- Output
-- Notes: Like the input source, the output can potentially be any circuit
-- that can accept a stream of pipeline outputs.
--
-- One additional challenge for storing outputs is that there are cases
-- where the window generator will output less than NUM_PIPELINES windows,
-- in which case some of the pipeline outputs will be invalid while others
-- are valid.
--
-- To deal with this situation, we recommend several possibilities. One
-- simple solution if storing to memory is to also store the invalid
-- outputs and then use softwareto filter out the invalid outputs.
-- A second option is to use a FIFO-like entity that can accept a
-- variable number of inputs (i.e. pipeline outputs) every cycle.
-- In this case, the FIFO will only store the valid outputs,
-- which filters out the invalid outputs. If connecting the pipeline
-- outputs to another downstream entity, it may also be convenient to
-- filter out the invalid outputs there.
-------------------------------------------------------------------------
U_OUTPUT_RAM : entity work.RAM(SYNC_READ)
generic map(
num_words => OUT_RAM_WORDS,
word_width => OUT_DATA_WIDTH,
addr_width => bitsNeeded(OUT_RAM_WORDS))
port map (
clk => clk,
wen => out_ram_wen,
waddr => out_ram_waddr,
wdata => out_ram_wdata,
raddr => out_ram_raddr,
rdata => out_ram_rdata);
end default;
| gpl-3.0 |
JavierReyes945/microelectronics-project | VHDL/enc/polyadder_tb.vhd | 1 | 1994 | -- Company: Fachhochschule Dortmund
-- Engineer: Javier Reyes
--
-- Create Date: 06/16/2017 04:49:58 PM
-- Design Name: Polynomial Adder Testbench for Convolutional Codes example project
-- Module Name: polyadder_tb - Simulation
-- Project Name: Convolutional Codes example project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.conf_pkg.all;
entity polyadder_tb is
-- EMPTY
end polyadder_tb;
architecture Behavioral of polyadder_tb is
-- Signals declaration
-- MSB is input of shift register
signal d_in : std_logic_vector(m-1 downto 0);
signal d_out : std_logic_vector(n-1 downto 0);
-- Components declaration
component polyadder
port (add_in : in std_logic_vector(m-1 downto 0);
add_out : out std_logic_vector(n-1 downto 0));
end component;
begin
-- instantiating the components
POLADD : polyadder port map (d_in, d_out);
-- Bit stream generated (emulate output of shift register)
d_in_process : process
begin
-- Initialized as zero
d_in <= std_logic_vector(to_unsigned(0, m));
wait for 2*clk_period;
-- Insert 1, value 1000 = 8
d_in <= std_logic_vector(to_unsigned(8, m));
wait for clk_period;
-- Insert 0, value 0100 = 4
d_in <= std_logic_vector(to_unsigned(4, m));
wait for clk_period;
-- Insert 1, value 1010 = 12
d_in <= std_logic_vector(to_unsigned(10, m));
wait for clk_period;
-- Insert 1, value 1101 = 13
d_in <= std_logic_vector(to_unsigned(13, m));
wait for clk_period;
-- Insert 0, value 0110 = 6 (trail)
d_in <= std_logic_vector(to_unsigned(6, m));
wait for clk_period;
-- Insert 0, value 0011 = 3 (trail)
d_in <= std_logic_vector(to_unsigned(3, m));
wait for clk_period;
-- Insert 0, value 0001 = 1 (trail)
d_in <= std_logic_vector(to_unsigned(1, m));
wait for clk_period;
-- Insert 0, value 0000 = 0 (trail)
d_in <= std_logic_vector(to_unsigned(0, m));
wait for clk_period;
end process;
end Behavioral;
| gpl-3.0 |
JavierReyes945/microelectronics-project | VHDL/dec/MyTraceBack.vhd | 1 | 4112 | -- Company: Fachhochschule Dortmund
-- Engineer: Mysara Ibrahim
--
-- Create Date: 27/06/2017 10:20:32 AM
-- Design Name: Traceback for Convolutional Codes example project
-- Module Name: MyTraceBack - Behavioral
-- Project Name: Convolutional Codes example project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.conf_pkg.all;
entity MyTraceBack is
port (index : in integer;
surv_path : in integer;
selectionIndex1, selectionIndex2, selectionIndex3, selectionIndex4 : in bit;
selectionIndex5, selectionIndex6, selectionIndex7, selectionIndex8 : in bit;
Decoded_out : out std_logic_vector(6 downto 0) := (others => '0'));
end MyTraceBack;
architecture Behavioral of MyTraceBack is
type selectm is array(7 downto 0, 3 downto 0) of bit;
shared variable sel : selectm := ((others=>(others=> '0' )));
begin
process (index)
begin
if (index>5) then
sel(0,index-6) := selectionIndex1;
sel(1,index-6) := selectionIndex2;
sel(2,index-6) := selectionIndex3;
sel(3,index-6) := selectionIndex4;
sel(4,index-6) := selectionIndex5;
sel(5,index-6) := selectionIndex6;
sel(6,index-6) := selectionIndex7;
sel(7,index-6) := selectionIndex8;
end if;
end process;
process (surv_path)
variable temp : integer :=0;
variable result : std_logic :='0';
variable jlooper : integer := 0;
variable ilooper : integer := 4;
begin
if (surv_path>0)then
if (index > 0) then
ilooper:= 3;
jlooper := 0;
temp:=surv_path;
l1 : while ilooper >= 0 loop
l2 : while jlooper < 8 loop
if (jlooper=temp-1) then
if (sel(jlooper,ilooper)='1') then
case temp is
when 1 => result :='0'; temp:=2; jlooper:=10;
when 2 => result :='0'; temp:=4; jlooper:=10;
when 3 => result :='0'; temp:=6; jlooper:=10;
when 4 => result :='0'; temp:=8; jlooper:=10;
when 5 => result :='1'; temp:=2; jlooper:=10;
when 6 => result :='1'; temp:=4; jlooper:=10;
when 7 => result :='1'; temp:=6; jlooper:=10;
when 8 => result :='1'; temp:=8; jlooper:=10;
when others => result := '0'; jlooper:=10;
end case;
-- end if;
-- if (sel(jlooper,ilooper)='0') then
else
case temp is
when 1 => result :='0'; temp:=1; jlooper:=10;
when 2 => result :='0'; temp:=3; jlooper:=10;
when 3 => result :='0'; temp:=5; jlooper:=10;
when 4 => result :='0'; temp:=7; jlooper:=10;
when 5 => result :='1'; temp:=1; jlooper:=10;
when 6 => result :='1'; temp:=3; jlooper:=10;
when 7 => result :='1'; temp:=5; jlooper:=10;
when 8 => result :='1'; temp:=7; jlooper:=10;
when others => result := '0'; jlooper:=10;
end case;
end if;
end if;
jlooper:=jlooper+1;
end loop l2;
jlooper := 0;
Decoded_out(3+ilooper) <= result;
ilooper:=ilooper-1;
end loop l1;
case temp is
when 1 => Decoded_out(2) <= '0';Decoded_out(1) <= '0';Decoded_out(0) <= '0';
when 2 => Decoded_out(2) <= '0';Decoded_out(1) <= '0';Decoded_out(0) <= '1';
when 3 => Decoded_out(2) <= '0';Decoded_out(1) <= '1';Decoded_out(0) <= '0';
when 4 => Decoded_out(2) <= '0';Decoded_out(1) <= '1';Decoded_out(0) <= '1';
when 5 => Decoded_out(2) <= '1';Decoded_out(1) <= '0';Decoded_out(0) <= '0';
when 6 => Decoded_out(2) <= '1';Decoded_out(1) <= '0';Decoded_out(0) <= '1';
when 7 => Decoded_out(2) <= '1';Decoded_out(1) <= '1';Decoded_out(0) <= '0';
when 8 => Decoded_out(2) <= '1';Decoded_out(1) <= '1';Decoded_out(0) <= '1';
when others => Decoded_out(2) <= '0';Decoded_out(1) <= '0';Decoded_out(0) <= '0';
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 |
JavierReyes945/microelectronics-project | VHDL/dec/TraceBack_tb.vhd | 1 | 3119 | -- Company: Fachhochschule Dortmund
-- Engineer: Mysara Ibrahim
--
-- Create Date: 06/16/2017 03:07:27 PM
-- Design Name: TraceBack testbench for Convolutional Codes example project
-- Module Name: TraceBack_tb - Behavioral
-- Project Name: Convolutional Codes example project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.conf_pkg.all;
entity TraceBack_tb is
-- Port ( );
end TraceBack_tb;
architecture Behavioral of TraceBack_tb is
component MyTraceBack
port (index : in integer;
surv_path : in integer;
selectionIndex1, selectionIndex2, selectionIndex3, selectionIndex4 : in bit;
selectionIndex5, selectionIndex6, selectionIndex7, selectionIndex8 : in bit;
Decoded_out : out std_logic_vector(seq downto 0):=(others => '0'));
end component MyTraceBack;
signal selectx1, selectx2, selectx3, selectx4, selectx5, selectx6, selectx7, selectx8 : bit;
signal surv_sig, index1 : integer range 0 to 8;
signal trac_out : std_logic_vector(seq downto 0):="00000000";
begin
resbts : MyTraceBack port map(index => index1, surv_path => surv_sig,
selectionIndex1 => selectx1, selectionIndex2 => selectx2,
selectionIndex3 => selectx3, selectionIndex4 => selectx4,
selectionIndex5 => selectx5, selectionIndex6 => selectx6,
selectionIndex7 => selectx7, selectionIndex8 => selectx8,
Decoded_out => trac_out);
stim_proc : process
begin
wait for clk_period/2;
index1 <= 0;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '1';selectx5 <= '1';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '1';selectx5 <= '0';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '0';selectx4 <= '1';selectx5 <= '1';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '1';selectx5 <= '1';selectx6 <= '0';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '1';selectx5 <= '1';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '0';selectx5 <= '1';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '1';selectx5 <= '1';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for clk_period;
index1 <= index1+1; surv_sig <= 1;
selectx1 <= '1';selectx2 <= '1';selectx3 <= '1';selectx4 <= '1';selectx5 <= '1';selectx6 <= '1';selectx7 <= '1';selectx8 <= '1';
wait for 3*clk_period/2;
end process;
end Behavioral;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/ahbtest.vhd | 2 | 4012 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.amba.all;
use work.iface.all;
entity ahbtest is
port (
rst : in std_logic;
clk : in clk_type;
-- peripheral bus
-- pbi : in APB_Slv_In_Type; -- peripheral bus in
-- pbo : out APB_Slv_Out_Type; -- peripheral bus out
-- irq : out std_logic; -- interrupt request
-- ahbi1 : in ahb_mst_in_type; -- dma port in
-- ahbo1 : out ahb_mst_out_type; -- dma port out
-- ahbi2 : in ahb_mst_in_type; -- dma port in
-- ahbo2 : out ahb_mst_out_type; -- dma port out
ahbi : in ahb_slv_in_type;
ahbo : out ahb_slv_out_type
);
end;
architecture struct of ahbtest is
type slavestate is (idle, error, split, retry, ws1);
type reg_type is record
haddr : std_logic_vector(31 downto 0); -- address bus
hsel : std_logic;
htrans : std_logic_vector(1 downto 0); -- transfer type
hresp : std_logic_vector(1 downto 0); -- response type
hmaster : std_logic_vector(3 downto 0); -- master
smaster : std_logic_vector(3 downto 0); -- split master
hwrite : std_logic; -- read/write
hready : std_logic; -- ready
splitcnt : natural;
ss : slavestate;
end record;
signal r, rin : reg_type;
begin
comb : process(ahbi, r)
variable v : reg_type;
variable prdata : std_logic_vector(31 downto 0);
variable vsplit : std_logic_vector(15 downto 0);
begin
v := r; v.hready := '0'; vsplit := (others => '0');
if r.splitcnt > 0 then
v.splitcnt := r.splitcnt -1;
if v.splitcnt = 0 then
vsplit(conv_integer(unsigned(r.smaster))) := '1';
end if;
end if;
if (ahbi.hready = '1') then
v.hready := '0'; v.haddr := ahbi.haddr; v.hwrite := ahbi.hwrite;
v.hsel := ahbi.hsel; v.hwrite := ahbi.hwrite;
v.hmaster := ahbi.hmaster;
end if;
if (ahbi.hsel and ahbi.hready) = '1' then
if ((ahbi.htrans = HTRANS_NONSEQ) or (ahbi.htrans = HTRANS_SEQ))
and (r.hresp = HRESP_OKAY)
then
if (ahbi.haddr(5 downto 4) = "01") and ((ahbi.haddr(3) xor ahbi.haddr(2)) = '1')
then v.hresp := HRESP_RETRY; v.ss := retry;
elsif (ahbi.haddr(5 downto 4) = "10") and ((ahbi.haddr(3) xor ahbi.haddr(2)) = '1')
then v.hresp := HRESP_SPLIT; v.ss := split;
elsif (ahbi.haddr(5 downto 4) = "11") and ((ahbi.haddr(3) xor ahbi.haddr(2)) = '1')
then v.hresp := HRESP_ERROR; v.ss := error;
else
v.hresp := HRESP_OKAY;
if (ahbi.haddr(3 downto 2) = "00") then v.ss := ws1;
else v.hready := '1'; end if;
end if;
else
if (r.hresp = HRESP_SPLIT) and (r.splitcnt > 2) then
v.ss := split; v.hresp := HRESP_SPLIT;
else
v.hresp := HRESP_OKAY; v.ss := idle; v.hready := '1';
end if;
end if;
end if;
case r.ss is
when idle =>
when retry =>
v.hresp := HRESP_RETRY; v.ss := idle; v.hready := '1';
when split =>
v.hresp := HRESP_SPLIT; v.ss := idle; v.hready := '1';
v.smaster := r.hmaster;
if r.splitcnt = 0 then v.splitcnt := 15; end if;
when error =>
v.hresp := HRESP_ERROR; v.ss := idle; v.hready := '1';
when ws1 =>
v.hresp := HRESP_OKAY; v.ss := idle; v.hready := '1';
end case;
ahbo.hresp <= r.hresp;
ahbo.hready <= r.hready;
ahbo.hrdata <= r.haddr;
ahbo.hsplit <= vsplit;
if rst = '0' then
v.hready := '1'; v.hsel := '0'; v.hresp := HRESP_OKAY;
v.haddr := (others => '0');
end if;
rin <= v;
end process;
-- ahbo1.haddr <= (others => '0') ;
-- ahbo1.htrans <= HTRANS_IDLE;
-- ahbo1.hbusreq <= '0';
-- ahbo1.hwdata <= (others => '0');
-- ahbo1.hlock <= '0';
-- ahbo1.hwrite <= '0';
-- ahbo1.hsize <= HSIZE_WORD;
-- ahbo1.hburst <= HBURST_SINGLE;
-- ahbo1.hprot <= (others => '0');
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Jidan FPU/branches/avendor/test_bench/tb_fpu.vhd | 2 | 6074 | -------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: test bench for the FPU core
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use std.textio.all;
use work.txt_util.all;
-- fpu operations (fpu_op_i):
-- ========================
-- 000 = add,
-- 001 = substract,
-- 010 = multiply,
-- 011 = divide,
-- 100 = square root
-- 101 = unused
-- 110 = unused
-- 111 = unused
-- Rounding Mode:
-- ==============
-- 00 = round to nearest even(default),
-- 01 = round to zero,
-- 10 = round up,
-- 11 = round down
entity tb_fpu is
end tb_fpu;
architecture rtl of tb_fpu is
component fpu
port (
clk_i : in std_logic;
opa_i : in std_logic_vector(31 downto 0);
opb_i : in std_logic_vector(31 downto 0);
fpu_op_i : in std_logic_vector(2 downto 0);
rmode_i : in std_logic_vector(1 downto 0);
output_o : out std_logic_vector(31 downto 0);
ine_o : out std_logic;
overflow_o : out std_logic;
underflow_o : out std_logic;
div_zero_o : out std_logic;
inf_o : out std_logic;
zero_o : out std_logic;
qnan_o : out std_logic;
snan_o : out std_logic;
start_i : in std_logic;
ready_o : out std_logic
);
end component;
signal clk_i : std_logic:= '0';
signal opa_i, opb_i : std_logic_vector(31 downto 0);
signal fpu_op_i : std_logic_vector(2 downto 0);
signal rmode_i : std_logic_vector(1 downto 0);
signal output_o : std_logic_vector(31 downto 0);
signal start_i, ready_o : std_logic ;
signal ine_o, overflow_o, underflow_o, div_zero_o, inf_o, zero_o, qnan_o, snan_o: std_logic;
signal slv_out : std_logic_vector(31 downto 0);
constant CLK_PERIOD :time := 10 ns; -- period of clk period
begin
-- instantiate fpu
i_fpu: fpu port map (
clk_i => clk_i,
opa_i => opa_i,
opb_i => opb_i,
fpu_op_i => fpu_op_i,
rmode_i => rmode_i,
output_o => output_o,
ine_o => ine_o,
overflow_o => overflow_o,
underflow_o => underflow_o,
div_zero_o => div_zero_o,
inf_o => inf_o,
zero_o => zero_o,
qnan_o => qnan_o,
snan_o => snan_o,
start_i => start_i,
ready_o => ready_o);
---------------------------------------------------------------------------
-- toggle clock
---------------------------------------------------------------------------
clk_i <= not(clk_i) after 5 ns;
verify : process
--The operands and results are in Hex format. The test vectors must be placed in a strict order for the verfication to work.
file testcases_file: TEXT open read_mode is "testcases.txt"; --Name of the file containing the test cases.
variable file_line: line;
variable str_in: string(8 downto 1);
variable str_fpu_op: string(3 downto 1);
variable str_rmode: string(2 downto 1);
begin
---------------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------SoftFloat test vectors (10000 test cases for each operation) --------------------------------------------------------------------
while not endfile(testcases_file) loop
wait for CLK_PERIOD; start_i <= '1';
str_read(testcases_file,str_in);
opa_i <= strhex_to_slv(str_in);
str_read(testcases_file,str_in);
opb_i <= strhex_to_slv(str_in);
str_read(testcases_file,str_fpu_op);
fpu_op_i <= to_std_logic_vector(str_fpu_op);
str_read(testcases_file,str_rmode);
rmode_i <= to_std_logic_vector(str_rmode);
str_read(testcases_file,str_in);
slv_out <= strhex_to_slv(str_in);
wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
assert output_o = slv_out
report "Error!!!"
severity failure;
str_read(testcases_file,str_in);
end loop;
----------------------------------------------------------------------------------------------------------------------------------------------------
assert false
report "Success!!!.......Yahoooooooooooooo"
severity failure;
wait;
end process verify;
end rtl; | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/VFLOAT_2015/General Modules/parameterized modules/parameterized_and_gate.vhd | 1 | 4355 | --======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- RAPID PROTOTYPING LABORATORY --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 29 Sep. 2013 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized OR gate --
----------------------------------------------------------
entity parameterized_and_gate is
generic
(
bits : integer := 0
);
port
(
--inputs
A : in std_logic_vector(bits-1 downto 0);
--outputs
O : out std_logic := '0'
);
end parameterized_and_gate;
----------------------------------------------------------
-- Parameterized OR gate --
----------------------------------------------------------
architecture parameterized_and_gate_arch of parameterized_and_gate is
--SIGNALS
signal im : std_logic_vector(2*ceil2(bits)-2 downto 0) := (others=>'0');
begin
--connect inputs
connect_input : for j in 0 to bits-1 generate
im(j) <= A(j);
end generate;--inputs
blank_inputs : if(ceil2(bits)/=bits) generate
connect_low : for k in bits to ceil2(bits)-1 generate
im(k) <= '1';
end generate;--connect low state
end generate;--zeros on input
--generate tree of gates
or_gates:for g in 0 to ceil2(bits)-2 generate
im(g+ceil2(bits)) <= im(g*2) and im(g*2+1);
end generate; --g
--connect output
O <= im(im'high);
end parameterized_and_gate_arch; -- end of architecture
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.3.7/leon/ddm.vhd | 2 | 14997 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use work.iface.all;
use work.amba.all;
entity ddm is
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ddmi : in ddm_in_type;
ddmo : out ddm_out_type;
irq : out std_logic
);
end;
architecture rtl of ddm is
type ddmregs is record
-- ***********************
-- memory mapped registers
-- bit 0 of 0x80000200
audioenreq : std_logic; -- audio function enabled active
-- bit 1 of 0x80000200
recorden : std_logic; -- audio record '1' or playback '1'
-- bit 2 of 0x80000200
loopen : std_logic; -- enable loop mode;
-- bit 3 of 0x80000200
irqen : std_logic; -- enable interrupt
-- bit 4 of 0x80000200
irq : std_logic; -- irq request
-- 32 bit at 0x80000204
startaddr : std_logic_vector(31 downto 0); -- dma transfer start address
-- 32 bit at 0x80000208
stopaddr : std_logic_vector(31 downto 0); -- dma transfer stop address
-- 14 bit at 0x8000020c
scalerup : std_logic_vector(13 downto 0); -- scaler update register value
-- masterclock / (sampling frequenz * 20*2)
-- lowest 8 bit of 0x80000210
display : std_logic_vector(7 downto 0); -- value to be displayed on the 2
-- digit display
-- bit 9 of 0x80000210
dispen : std_logic; -- enable display on board
-- bit 0-4 of 0x80000214
button0 : std_logic; -- status of the buttons
button1 : std_logic;
button2 : std_logic;
button3 : std_logic;
-- 0x80000218
memoryadr : std_logic_vector(31 downto 0); -- actual dma address /read only
-- memory mapped registers end
-- ***************************
-- internal registers
audioen : std_logic;
dmatransfreq : std_logic;
audiobuffer : std_logic_vector(31 downto 0); -- audio data buffer for
-- memory transfers
shiftcounter : std_logic_vector(4 downto 0); -- counter for 20 bit shiftregister
audioshifter : std_logic_vector(19 downto 0); -- serial shift register for
-- audio a/d and d/a converter
shifttick : std_logic; -- tick from serial 5 bit (from 20 bit shift
-- register) counter
readaudio_clk: std_logic;
shiftstop : std_logic; -- set for the 12 bit not shifted
lrsel : std_logic; -- left/right output selector
masterclk : std_logic;
sclk : std_logic;
audioout : std_logic; -- 1 bit audio output to d/a converter
digit0 : std_logic_vector(6 downto 0);
digit1 : std_logic_vector(6 downto 0);
-- amba status registers
busact : std_logic;
busown : std_logic;
busgrant : std_logic;
busown2cyc : std_logic;
end record;
type timer is record
scaler : std_logic_vector(13 downto 0);
masterclk : std_logic;
sclkscaler : std_logic_vector(1 downto 0); -- shiftclk generator
sclk : std_logic; -- shiftclk output
sclk_old : std_logic; -- old status of shiftclk for signal
-- change recognition
end record;
signal r,rin : ddmregs;
signal timerout,timerin : timer;
begin
ddmtop : process(rst,r, apbi, ahbi, ddmi, timerout)
variable rdata : std_logic_vector(31 downto 0);
variable tmp: ddmregs;
variable regaddr : std_logic_vector(4 downto 0):="10000";
-- amba ahb variables
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_logic; -- read/write
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hbusreq : std_logic; -- bus request
begin
-- init
tmp:=r;
htrans := HTRANS_IDLE; -- do nothing if granted without request
hbusreq := '0';
-- read/write memory mapped registers witch amba apb bus
rdata := (others => '0'); -- init
case apbi.paddr(4 downto 2) is
when "000" =>
rdata(0) := r.audioen or r.audioenreq;
rdata(1) := r.recorden;
rdata(2) := r.loopen;
rdata(3) := r.irqen;
rdata(4) := r.irq;
when "001" =>
rdata := r.startaddr;
when "010" =>
rdata := r.stopaddr;
when "011" =>
rdata(13 downto 0) := r.scalerup;
when "100" =>
rdata(7 downto 0) := r.display;
rdata(8) := r.dispen;
when "101" =>
rdata(0) := r.button0;
rdata(1) := r.button1;
rdata(2) := r.button2;
rdata(3) := r.button3;
when "110" =>
rdata := r.memoryadr;
when others => null;
end case;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
tmp.audioenreq := apbi.pwdata(0);
tmp.recorden := apbi.pwdata(1);
tmp.loopen := apbi.pwdata(2);
tmp.irqen := apbi.pwdata(3);
if apbi.pwdata(4)='0' then -- allow only interrupt reset
tmp.irq := '0';
end if;
if tmp.audioenreq = '1' and r.audioenreq = '0' then -- init audio transaction
tmp.memoryadr := r.startaddr;
if tmp.recorden = '0' then -- load first audio data when play back
tmp.dmatransfreq := '1';
end if;
end if;
when "001" =>
tmp.startaddr := apbi.pwdata;
when "010" =>
tmp.stopaddr := apbi.pwdata;
when "011" =>
tmp.scalerup := apbi.pwdata(13 downto 0);
when "100" =>
tmp.display := apbi.pwdata(7 downto 0);
tmp.dispen := apbi.pwdata(8);
when others => null;
end case;
end if;
-- update buttonreg
tmp.button0 := ddmi.button0;
tmp.button1 := ddmi.button1;
tmp.button2 := ddmi.button2;
tmp.button3 := ddmi.button3;
-- decode display input to digits
case r.display(3 downto 0) is
when "0000" =>
tmp.digit0 := "1110111";
when "0001" =>
tmp.digit0 := "0100100";
when "0010" =>
tmp.digit0 := "1011101";
when "0011" =>
tmp.digit0 := "1101101";
when "0100" =>
tmp.digit0 := "0101110";
when "0101" =>
tmp.digit0 := "1101011";
when "0110" =>
tmp.digit0 := "1111011";
when "0111" =>
tmp.digit0 := "0100111";
when "1000" =>
tmp.digit0 := "1111111";
when "1001" =>
tmp.digit0 := "1101111";
when "1010" =>
tmp.digit0 := "0111111";
when "1011" =>
tmp.digit0 := "1111010";
when "1100" =>
tmp.digit0 := "1010011";
when "1101" =>
tmp.digit0 := "1111100";
when "1110" =>
tmp.digit0 := "1011011";
when "1111" =>
tmp.digit0 := "0011011";
when others => null;
end case;
case r.display(7 downto 4) is
when "0000" =>
tmp.digit1 := "1110111";
when "0001" =>
tmp.digit1 := "0100100";
when "0010" =>
tmp.digit1 := "1011101";
when "0011" =>
tmp.digit1 := "1101101";
when "0100" =>
tmp.digit1 := "0101110";
when "0101" =>
tmp.digit1 := "1101011";
when "0110" =>
tmp.digit1 := "1111011";
when "0111" =>
tmp.digit1 := "0100111";
when "1000" =>
tmp.digit1 := "1111111";
when "1001" =>
tmp.digit1 := "1101111";
when "1010" =>
tmp.digit1 := "0111111";
when "1011" =>
tmp.digit1 := "1111010";
when "1100" =>
tmp.digit1 := "1010011";
when "1101" =>
tmp.digit1 := "1111100";
when "1110" =>
tmp.digit1 := "1011011";
when "1111" =>
tmp.digit1 := "0011011";
when others => null;
end case;
-- audio in/out
tmp.masterclk:=timerout.masterclk;
tmp.sclk :=timerout.sclk;
-- audio shifter out/in
if (timerout.sclk='1') and (timerout.sclk_old='0') then
tmp.shiftcounter := tmp.shiftcounter+1;
tmp.shifttick := r.shiftcounter(4) and not tmp.shiftcounter(4);
if tmp.shiftcounter="10100" then -- stop shifting after 20 bit
tmp.shiftstop :='1';
end if;
-- audio shifregister to buffer update and vice versa
if (tmp.shifttick ='1') and (r.shifttick= '0') then -- all 32 data bits
tmp.lrsel:=not r.lrsel; -- change left/right channel
if tmp.lrsel = '1' then -- only transmit data to or from memory when audio is on for one phase
if r.audioen='1' then
if r.recorden = '1' then -- if record shiftreg to buffer
tmp.audiobuffer(19 downto 0) := tmp.audioshifter; -- save record
-- data from
-- shiftregister
-- in buffer
tmp.dmatransfreq := '1'; -- start dma transfer action for
-- recording
else
tmp.audioshifter := r.audiobuffer(19 downto 0); -- else load new audio data
end if;
end if;
tmp.audioen:=tmp.audioenreq; -- enable audio if requested
if tmp.audioen='1' and tmp.recorden='0' then
tmp.dmatransfreq:='1'; -- load data for playback from memory
end if;
else
tmp.shiftstop:='0'; -- start shifting
end if;
end if;
if r.audioen ='1' then
if r.recorden = '1' then
if tmp.shiftstop='0' then
tmp.readaudio_clk:='1';
else
tmp.audioout := '0';
end if;
else
if tmp.shiftstop='0' then
tmp.audioout := tmp.audioshifter(19);
tmp.audioshifter := tmp.audioshifter(18 downto 0) & '0';
else
tmp.audioout:='0';
end if;
end if;
else
tmp.audioout:='0';
tmp.audioshifter := (others => '0');
end if;
end if;
-- audio data must be read one clk later as mclk is generated
if r.readaudio_clk='1' then
tmp.readaudio_clk:='0';
tmp.audioshifter := tmp.audioshifter(18 downto 0) & ddmi.audioin;
tmp.audioout:=ddmi.audioin;
end if;
-- audio shifregister to buffer update and vice versa
-- dma/amba ahb activity (master)
-- start ahb action
if r.dmatransfreq = '1' then -- request bus for action
hbusreq := '1';
end if;
-- check for bus ownership
tmp.busgrant := ahbi.hgrant;
if tmp.busgrant = '1' and r.dmatransfreq = '1' then
tmp.busact := '1'; -- bus granted and requested
else
tmp.busact := '0'; -- bus granted but not requested
end if;
if (tmp.busact = '1') and (ahbi.hready= '1') then -- bus active
tmp.busown:='1'; -- bus owner at next clock
tmp.dmatransfreq := '0';
end if;
-- control and address cycle of ahb transfer
if r.busown='1' then
haddr := r.memoryadr;
hsize := HSIZE_WORD;
hburst := HBURST_SINGLE;
htrans := HTRANS_NONSEQ;
if r.recorden = '1'then
hwrite := '1';
else
hwrite := '0';
end if;
if ahbi.hready='1' then -- check for data cycle
tmp.busown:='0';
tmp.busown2cyc:='1';
end if;
end if;
-- data cycle of ahb transfer
if r.busown2cyc='1' then
if r.recorden = '1'then
hwdata:=r.audiobuffer;
end if;
if ahbi.hready='1' then
tmp.busown:='0';
tmp.busown2cyc:='0';
tmp.memoryadr := r.memoryadr+4; -- next memory address
if r.recorden='0' then
tmp.audiobuffer := ahbi.hrdata;
end if;
end if;
end if;
-- check for audio action end
if tmp.memoryadr = r.stopaddr then -- stop address reached ?
if r.loopen = '1' then -- if loopmode activated
tmp.memoryadr := r.startaddr; -- loop mode; begin again at start
else
tmp.audioen := '0'; -- audio task finished , in output
-- mode last sample gets lost
tmp.audioenreq := '0';
tmp.audiobuffer:= (others => '0');
end if;
tmp.irq := r.irqen; -- request interrupt when enabled
end if;
-- reset operation of ddm-module
if rst = '0' then
tmp.audiobuffer := (others => '0');
tmp.audioshifter := (others => '0');
tmp.startaddr := (others => '0');
tmp.stopaddr := (others => '0');
tmp.memoryadr := (others => '0');
tmp.scalerup := "00000000000001";
tmp.shiftcounter := (others => '0');
tmp.shiftstop := '0';
tmp.audioen := '0';
tmp.recorden := '0';
tmp.irqen := '0';
tmp.irq := '0';
tmp.display := (others => '0');
tmp.dmatransfreq := '0';
tmp.lrsel := '0';
tmp.dispen := '0';
tmp.busown := '0';
tmp.busown2cyc := '0';
tmp.busact := '0';
tmp.readaudio_clk:='0';
end if;
-- update registers
rin <= tmp;
-- output from ddm to ambabus and outworld
ddmo.digit0 <= r.digit0;
ddmo.digit1 <= r.digit1;
ddmo.audioout <= r.audioout;
ddmo.lr_out <= r.lrsel;
ddmo.shift_clk <= not r.sclk;
ddmo.dispen <= r.dispen;
ddmo.mclk <= r.masterclk;
irq <= r.irq;
apbo.prdata <= rdata;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= hwdata;
ahbo.hlock <= '0';
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hprot <= (others => '0');
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
timerout <= timerin;
end if;
end process;
timerpr : process(timerout, rst)
variable scaler : std_logic_vector(13 downto 0);
variable masterclk : std_logic;
variable tick : std_logic;
variable rscaler : std_logic_vector(1 downto 0);
variable sclk: std_logic;
-- scaler update
begin
if rst = '1' then
sclk:= timerout.sclk;
scaler := timerout.scaler-1;
masterclk := timerout.masterclk;
tick := scaler(13) and not timerout.scaler(13);
rscaler := timerout.sclkscaler;
if tick = '1' then
scaler := r.scalerup;
masterclk := not timerout.masterclk;
rscaler := rscaler+1; -- generating shiftclk
if ((not rscaler(0)) and (not rscaler(1)))='1' then
sclk := not sclk;
end if;
end if;
-- audio shiftclk generation
timerin.sclkscaler <= rscaler;
timerin.sclk_old <= timerout.sclk;
timerin.scaler <= scaler;
timerin.masterclk <= masterclk;
timerin.sclk <= sclk;
else
timerin.sclkscaler <= "00"; --reset
timerin.sclk_old <= '0';
timerin.sclk <= '0';
timerin.scaler <= "00000000000001";
timerin.masterclk <= '0';
end if;
end process;
end;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.3.7/leon/amba.vhd | 2 | 14969 | --============================================================================--
-- Design unit : AMBA (Package declaration)
--
-- File name : amba.vhd
--
-- Purpose : This package declares types to be used with the
-- Advanced Microcontroller Bus Architecture (AMBA).
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
--
-- The document can be retrieved from http://www.arm.com
--
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case n in the name indicates that the signal is
-- active low. A lower case x in the name suffix indicates that
-- the signal is unique to a module. Constant names are in upper
-- case.
--
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Library : AMBA_Lib {recommended}
--
-- Author : European Space Agency (ESA)
-- P.O. Box 299
-- NL-2200 AG Noordwijk ZH
-- The Netherlands
--
-- Contact : mailto:[email protected]
-- http://www.estec.esa.nl/microelectronics
--
-- Copyright (C): European Space Agency (ESA) 2000. This source code may be
-- redistributed provided that the source code and this notice
-- remain intact. This source code may not under any
-- circumstances be resold or redistributed for compensation
-- of any kind without prior written permission.
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit. This information does not
-- necessarily reflect the policy of the European Space Agency.
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.2 ESA 5 Jul 2000 Package created
-- 0.3 ESA 10 Jul 2000 Additional HREADY slave input,
-- Std_ULogic usage for non-array signals,
-- Additional comments on casing and addressing
-- 0.4 ESA 14 Jul 2000 HRESETn removed from AHB Slave input record
-- Additional comments on clocking and reset
-- Additional comments on AHB endianness
-- Additional comments on APB addressing
-- 0.5 ESA 18 Jul 2000 Re-defined vector types for AHB arbiter
-- and APB master
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
package AMBA is
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) Advanced High-performance Bus (AHB)
-----------------------------------------------------------------------------
-- Records are defined for the input and output of an AHB Master, as well as
-- for an AHB Slave. These records are grouped in arrays, for scalability,
-- and new records using these arrays are defined for the input and output of
-- an AHB Arbiter/Decoder.
--
-- The routing of the clock and reset signals defined in the AMBA(TM)
-- Specification is not covered in this package, since being dependent on
-- the clock and reset conventions defined at system level.
--
-- The HCLK and HRESETn signals are routed separately:
-- HCLK: Std_ULogic; -- rising edge
-- HRESETn: Std_ULogic; -- active low reset
--
-- The address bus HADDR contains byte addresses. The relation between the
-- byte address and the n-byte data bus HDATA can either be little-endian or
-- big-endian according to the AMBA(TM) Specification.
--
-- It is recommended that only big-endian modules are implemented using
-- this package.
--
-----------------------------------------------------------------------------
-- Constant definitions for AMBA(TM) AHB
-----------------------------------------------------------------------------
constant HDMAX: Positive range 32 to 1024 := 32; -- data width
constant HAMAX: Positive range 32 to 32 := 32; -- address width
-- constant HMMAX: Positive range 1 to 16 := 16; -- number of masters
-- constant HSMAX: Positive := 16; -- number of slaves
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) AHB Masters
-----------------------------------------------------------------------------
-- AHB master inputs (HCLK and HRESETn routed separately)
type AHB_Mst_In_Type is
record
HGRANT: Std_ULogic; -- bus grant
HREADY: Std_ULogic; -- transfer done
HRESP: Std_Logic_Vector(1 downto 0); -- response type
HRDATA: Std_Logic_Vector(HDMAX-1 downto 0); -- read data bus
HCACHE: Std_ULogic; -- cacheable data
end record;
-- AHB master outputs
type AHB_Mst_Out_Type is
record
HBUSREQ: Std_ULogic; -- bus request
HLOCK: Std_ULogic; -- lock request
HTRANS: Std_Logic_Vector(1 downto 0); -- transfer type
HADDR: Std_Logic_Vector(HAMAX-1 downto 0); -- address bus (byte)
HWRITE: Std_ULogic; -- read/write
HSIZE: Std_Logic_Vector(2 downto 0); -- transfer size
HBURST: Std_Logic_Vector(2 downto 0); -- burst type
HPROT: Std_Logic_Vector(3 downto 0); -- protection control
HWDATA: Std_Logic_Vector(HDMAX-1 downto 0); -- write data bus
end record;
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) AHB Slaves
-----------------------------------------------------------------------------
-- AHB slave inputs (HCLK and HRESETn routed separately)
type AHB_Slv_In_Type is
record
HSEL: Std_ULogic; -- slave select
HADDR: Std_Logic_Vector(HAMAX-1 downto 0); -- address bus (byte)
HWRITE: Std_ULogic; -- read/write
HTRANS: Std_Logic_Vector(1 downto 0); -- transfer type
HSIZE: Std_Logic_Vector(2 downto 0); -- transfer size
HBURST: Std_Logic_Vector(2 downto 0); -- burst type
HWDATA: Std_Logic_Vector(HDMAX-1 downto 0); -- write data bus
HPROT: Std_Logic_Vector(3 downto 0); -- protection control
HREADY: Std_ULogic; -- transfer done
HMASTER: Std_Logic_Vector(3 downto 0); -- current master
HMASTLOCK: Std_ULogic; -- locked access
end record;
-- AHB slave outputs
type AHB_Slv_Out_Type is
record
HREADY: Std_ULogic; -- transfer done
HRESP: Std_Logic_Vector(1 downto 0); -- response type
HRDATA: Std_Logic_Vector(HDMAX-1 downto 0); -- read data bus
HSPLIT: Std_Logic_Vector(15 downto 0); -- split completion
end record;
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) AHB Arbiter/Decoder
-----------------------------------------------------------------------------
-- supporting array types
type AHB_Mst_In_Vector is array (Natural Range <> ) of AHB_Mst_In_Type;
type AHB_Mst_Out_Vector is array (Natural Range <> ) of AHB_Mst_Out_Type;
type AHB_Slv_In_Vector is array (Natural Range <> ) of AHB_Slv_In_Type;
type AHB_Slv_Out_Vector is array (Natural Range <> ) of AHB_Slv_Out_Type;
-- An AHB arbiter could be defined as follows:
-- entity AHBarbiter is
-- generic (
-- masters : integer := 2; -- number of masters
-- slaves : integer := 2; -- number of slaves
-- );
-- port (
-- clk : in std_ulogic;
-- rst : in std_ulogic;
-- msti : out ahb_mst_in_vector(0 to masters-1);
-- msto : in ahb_mst_out_vector(0 to masters-1);
-- slvi : out ahb_slv_in_vector(0 to slaves-1);
-- slvo : in ahb_slv_out_vector(0 to slaves-1)
-- );
-- end;
-----------------------------------------------------------------------------
-- Auxiliary constant definitions for AMBA(TM) AHB
-----------------------------------------------------------------------------
-- constants for HTRANS (transition type, slave output)
constant HTRANS_IDLE: Std_Logic_Vector(1 downto 0) := "00";
constant HTRANS_BUSY: Std_Logic_Vector(1 downto 0) := "01";
constant HTRANS_NONSEQ: Std_Logic_Vector(1 downto 0) := "10";
constant HTRANS_SEQ: Std_Logic_Vector(1 downto 0) := "11";
-- constants for HBURST (burst type, master output)
constant HBURST_SINGLE: Std_Logic_Vector(2 downto 0) := "000";
constant HBURST_INCR: Std_Logic_Vector(2 downto 0) := "001";
constant HBURST_WRAP4: Std_Logic_Vector(2 downto 0) := "010";
constant HBURST_INCR4: Std_Logic_Vector(2 downto 0) := "011";
constant HBURST_WRAP8: Std_Logic_Vector(2 downto 0) := "100";
constant HBURST_INCR8: Std_Logic_Vector(2 downto 0) := "101";
constant HBURST_WRAP16: Std_Logic_Vector(2 downto 0) := "110";
constant HBURST_INCR16: Std_Logic_Vector(2 downto 0) := "111";
-- constants for HSIZE (transfer size, master output)
constant HSIZE_BYTE: Std_Logic_Vector(2 downto 0) := "000";
constant HSIZE_HWORD: Std_Logic_Vector(2 downto 0) := "001";
constant HSIZE_WORD: Std_Logic_Vector(2 downto 0) := "010";
constant HSIZE_DWORD: Std_Logic_Vector(2 downto 0) := "011";
constant HSIZE_4WORD: Std_Logic_Vector(2 downto 0) := "100";
constant HSIZE_8WORD: Std_Logic_Vector(2 downto 0) := "101";
constant HSIZE_16WORD: Std_Logic_Vector(2 downto 0) := "110";
constant HSIZE_32WORD: Std_Logic_Vector(2 downto 0) := "111";
-- constants for HRESP (response, slave output)
constant HRESP_OKAY: Std_Logic_Vector(1 downto 0) := "00";
constant HRESP_ERROR: Std_Logic_Vector(1 downto 0) := "01";
constant HRESP_RETRY: Std_Logic_Vector(1 downto 0) := "10";
constant HRESP_SPLIT: Std_Logic_Vector(1 downto 0) := "11";
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) Advanced Peripheral Bus (APB)
-----------------------------------------------------------------------------
-- Records are defined for the input and output of an APB Slave. These
-- records are grouped in arrays, for scalability, and new records using
-- these arrays are defined for the input and output of an APB Bridge.
--
-- The routing of the clock and reset signals defined in the AMBA(TM)
-- Specification is not covered in this package, since being dependent on
-- the clock and reset conventions defined at system level.
--
-- The PCLK and PRESETn signals are routed separately:
-- PCLK: Std_ULogic; -- rising edge
-- PRESETn: Std_ULogic; -- active low reset
--
-- The characteristics of the address bus PADDR are undefined in the
-- AMBA(TM) Specification.
--
-- When implementing modules with this package, it is recommended that the
-- information on the address bus PADDR is interpreted as byte addresses, but
-- it should only be used for 32-bit word addressing, i.e. the value of
-- address bits 0 and 1 should always be logical 0. For modules not
-- supporting full 32-bit words on the data bus PDATA, e.g. only supporting
-- 16-bit halfwords or 8-bit bytes, the addressing will still be word based.
-- Consequently, one halfword or byte will be accessed for each word address.
-- Modules only supporting byte sized data should exchange data on bit 7 to 0
-- on the PDATA data bus. Modules only supporting halfword sized data should
-- exchange data on bit 15 to 0 on the PDATA data bus. Modules supporting
-- word sized data should exchange data on bit 31 to 0 on the PDATA data bus.
--
-----------------------------------------------------------------------------
-- Constant definitions for AMBA(TM) APB
-----------------------------------------------------------------------------
constant PDMAX: Positive range 8 to 32 := 32; -- data width
constant PAMAX: Positive range 8 to 32 := 32; -- address width
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) APB Slaves
-----------------------------------------------------------------------------
-- APB slave inputs (PCLK and PRESETn routed separately)
type APB_Slv_In_Type is
record
PSEL: Std_ULogic; -- slave select
PENABLE: Std_ULogic; -- strobe
PADDR: Std_Logic_Vector(PAMAX-1 downto 0); -- address bus (byte)
PWRITE: Std_ULogic; -- write
PWDATA: Std_Logic_Vector(PDMAX-1 downto 0); -- write data bus
end record;
-- APB slave outputs
type APB_Slv_Out_Type is
record
PRDATA: Std_Logic_Vector(PDMAX-1 downto 0); -- read data bus
end record;
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) APB Bridge
-----------------------------------------------------------------------------
-- supporting array types
type APB_Slv_In_Vector is array (Natural Range <> ) of APB_Slv_In_Type;
type APB_Slv_Out_Vector is array (Natural Range <> ) of APB_Slv_Out_Type;
-- An AHB/APB bridge could be defined as follows:
-- entity apbmst is
-- generic (slaves : natural := 32);
-- port (
-- clk : in std_ulogic;
-- rst : in std_ulogic;
-- ahbi : in ahb_slv_in_type;
-- ahbo : out ahb_slv_out_type;
-- apbi : in apb_slv_out_vector(0 to slaves-1);
-- apbo : out apb_slv_in_vector(0 to slaves-1)
-- );
-- end;
end AMBA; --==================================================================-- | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/target32.vhd | 1 | 36713 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: target
-- File: target.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: LEON target configuration package
------------------------------------------------------------------------------
-- 29.01.02 Configuration of DDM. LA
-- 13.03.02 MDCT added. APB masters incremented by 1 in AHB configuration, and
-- mdct address added in APB configuration.
library IEEE;
use IEEE.std_logic_1164.all;
package target is
type targettechs is (gen, virtex, atc35, atc25, fs90, umc18);
-- synthesis configuration
type syn_config_type is record
targettech : targettechs;
infer_ram : boolean; -- infer cache ram automatically
infer_regf : boolean; -- infer regfile automatically
infer_rom : boolean; -- infer boot prom automatically
infer_pads : boolean; -- infer pads automatically
infer_mult : boolean; -- infer multiplier automatically
gatedclk : boolean; -- select clocking strategy
rftype : integer; -- regfile implementation option
end record;
-- processor configuration
type multypes is (none, iterative, m32x8, m16x16, m32x16, m32x32);
type divtypes is (none, radix2);
type iu_config_type is record
nwindows : integer; -- # register windows (2 - 32)
multiplier : multypes; -- multiplier type
divider : divtypes; -- divider type
mac : boolean; -- multiply/accumulate
fpuen : integer range 0 to 1; -- FPU enable (integer due to synopsys limitations....sigh!)
cpen : boolean; -- co-processor enable
fastjump : boolean; -- enable fast jump address generation
icchold : boolean; -- enable fast branch logic
lddelay : integer range 1 to 2; -- # load delay cycles (1-2)
fastdecode : boolean; -- optimise instruction decoding (FPGA only)
watchpoints : integer range 0 to 4; -- # hardware watchpoints (0-4)
impl : integer range 0 to 15; -- IU implementation ID
version : integer range 0 to 15; -- IU version ID
end record;
-- FPU configuration
type fputype is (none, meiko, fpc); -- FPU type
type fpu_config_type is record
fpu : fputype; -- FPU type
fregs : integer; -- 32 for internal meiko, 0 for external FPC
version : integer range 0 to 7; -- FPU version ID
end record;
-- co-processor configuration
type cptype is (none, cpc); -- CP type
type cp_config_type is record
cp : cptype; -- Co-processor type
version : integer range 0 to 7; -- CP version ID
-- add your CP-specific configuration options here!!
end record;
-- cache configuration
type cache_config_type is record
icachesize : integer; -- size of I-cache in Kbytes
ilinesize : integer; -- # words per I-cache line
dcachesize : integer; -- size of D-cache in Kbytes
dlinesize : integer; -- # words per D-cache line
end record;
-- memory controller configuration
type mctrl_config_type is record
bus8en : boolean; -- enable 8-bit bus operation
bus16en : boolean; -- enable 16-bit bus operation
rawaddr : boolean; -- enable unlatched address option
end record;
type boottype is (memory, prom, dual);
type boot_config_type is record
boot : boottype; -- select boot source
ramrws : integer range 0 to 3; -- ram read waitstates
ramwws : integer range 0 to 3; -- ram write waitstates
sysclk : integer; -- cpu clock
baud : positive; -- UART baud rate
extbaud : boolean; -- use external baud rate setting
pabits : positive; -- internal boot-prom address bits
end record;
-- PCI configuration
type pcitype is (none, insilicon, esa, ahbtst); -- PCI core type
type pci_config_type is record
pcicore : pcitype; -- PCI core type
ahbmasters : integer; -- number of ahb master interfaces
ahbslaves : integer; -- number of ahb slave interfaces
arbiter : boolean; -- enable PCI arbiter
fixpri : boolean; -- use fixed arbitration priority
prilevels : integer; -- number of priority levels in arbiter
pcimasters : integer; -- number of PCI masters to be handled by arbiter
vendorid : integer; -- PCI vendor ID
deviceid : integer; -- PCI device ID
subsysid : integer; -- PCI subsystem ID
revisionid : integer; -- PCI revision ID
classcode : integer; -- PCI class code
pmepads : boolean; -- enable power down pads
p66pad : boolean; -- enable PCI66 pad
end record;
-- debug configuration
type debug_config_type is record
enable : boolean; -- enable debug port
uart : boolean; -- enable fast uart data to console
iureg : boolean; -- enable tracing of iu register writes
fpureg : boolean; -- enable tracing of fpu register writes
nohalt : boolean; -- dont halt on error
pclow : integer; -- set to 2 for synthesis, 0 for debug
end record;
-- AMBA configuration types
constant AHB_MST_MAX : integer := 5; -- maximum AHB masters
constant AHB_SLV_MAX : integer := 7; -- maximum AHB slaves
constant AHB_SLV_ADDR_MSB : integer := 4; -- MSB address bits to decode slaves
constant AHB_CACHE_MAX : integer := 4; -- maximum cacheability ranges
constant AHB_CACHE_ADDR_MSB : integer := 3; -- MSB address bits to decode cacheability
subtype ahb_range_addr_type is std_logic_vector(AHB_SLV_ADDR_MSB-1 downto 0);
subtype ahb_cache_addr_type is std_logic_vector(AHB_CACHE_ADDR_MSB-1 downto 0);
type ahb_slv_config_type is record
firstaddr : ahb_range_addr_type;
lastaddr : ahb_range_addr_type;
index : integer range 0 to AHB_SLV_MAX-1;
split : boolean;
enable : boolean;
end record;
type ahb_slv_config_vector is array (Natural Range <> ) of ahb_slv_config_type;
constant ahb_slv_config_void : ahb_slv_config_type :=
((others => '0'), (others => '0'), 0, false, false);
type ahb_cache_config_type is record
firstaddr : ahb_cache_addr_type;
lastaddr : ahb_cache_addr_type;
end record;
type ahb_cache_config_vector is array (Natural Range <> ) of ahb_cache_config_type;
constant ahb_cache_config_void : ahb_cache_config_type :=
((others => '0'), (others => '0'));
type ahb_config_type is record
masters : integer range 1 to AHB_MST_MAX;
defmst : integer range 0 to AHB_MST_MAX-1;
split : boolean; -- add support for SPLIT reponse
slvtable : ahb_slv_config_vector(0 to AHB_SLV_MAX-1);
cachetable : ahb_cache_config_vector(0 to AHB_CACHE_MAX-1);
end record;
constant APB_SLV_MAX : integer := 16; -- maximum APB slaves
constant APB_SLV_ADDR_BITS : integer := 10; -- address bits to decode APB slaves
subtype apb_range_addr_type is std_logic_vector(APB_SLV_ADDR_BITS-1 downto 0);
type apb_slv_config_type is record
firstaddr : apb_range_addr_type;
lastaddr : apb_range_addr_type;
index : integer;
enable : boolean;
end record;
type apb_slv_config_vector is array (Natural Range <> ) of apb_slv_config_type;
constant apb_slv_config_void : apb_slv_config_type :=
((others => '0'), (others => '0'), 0, false);
type apb_config_type is record
table : apb_slv_config_vector(0 to APB_SLV_MAX-1);
end record;
type irq_filter_type is (lvl0, lvl1, edge0, edge1);
type irq_filter_vec is array (0 to 31) of irq_filter_type;
type irq2type is record
enable : boolean; -- enable chained interrupt controller
channels : integer; -- number of additional interrupts (1 - 32)
filter : irq_filter_vec; -- irq filter definitions
end record;
type peri_config_type is record
cfgreg : boolean; -- enable LEON configuration register
ahbstat : boolean; -- enable AHB status register
wprot : boolean; -- enable RAM write-protection unit
wdog : boolean; -- enable watchdog
irq2cfg : irq2type; -- chained interrupt controller config
end record;
-- complete configuration record type
type config_type is record
synthesis : syn_config_type;
iu : iu_config_type;
fpu : fpu_config_type;
cp : cp_config_type;
cache : cache_config_type;
ahb : ahb_config_type;
apb : apb_config_type;
mctrl : mctrl_config_type;
boot : boot_config_type;
debug : debug_config_type;
pci : pci_config_type;
peri : peri_config_type;
end record;
----------------------------------------------------------------------------
-- Synthesis configurations
----------------------------------------------------------------------------
constant syn_atc25 : syn_config_type := (
targettech => atc25, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_atc35 : syn_config_type := (
targettech => atc35, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_gen : syn_config_type := (
targettech => gen, infer_pads => true,
infer_ram => true, infer_regf => true, infer_rom => true,
infer_mult => true, gatedclk => false, rftype => 1);
constant syn_virtex : syn_config_type := (
targettech => virtex, infer_pads => true,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => true, gatedclk => false, rftype => 1);
constant syn_virtex_blockprom : syn_config_type := (
targettech => virtex, infer_pads => true,
infer_ram => false, infer_regf => false, infer_rom => false,
infer_mult => true, gatedclk => false, rftype => 1);
constant syn_systel_asic : syn_config_type := (
targettech => atc25, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_fs90 : syn_config_type := (
targettech => fs90, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_umc18 : syn_config_type := (
targettech => umc18, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
-- infer_multgates => false,
infer_mult => false, gatedclk => false, rftype => 1);
----------------------------------------------------------------------------
-- IU configurations
----------------------------------------------------------------------------
constant iu_std : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 0, impl => 0, version => 0);
constant iu_std_mac : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 0, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 0, impl => 0, version => 0);
constant iu_fpu : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 1, cpen => false, fastjump => false, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga : iu_config_type := (
nwindows => 8, multiplier => none, divider => none, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8 : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8_fpu : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 1, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8_mac : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8_small : iu_config_type := (
nwindows => 8, multiplier => iterative, divider => radix2, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_atc25 : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 0, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 2, impl => 0, version => 0);
constant iu_atc25_fpu : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 1, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 2, impl => 0, version => 0);
----------------------------------------------------------------------------
-- FPU configurations
----------------------------------------------------------------------------
constant fpu_none : fpu_config_type := (fpu => none, fregs => 0, version => 0);
constant fpu_meiko: fpu_config_type := (fpu => meiko, fregs => 32, version => 0);
constant fpu_fpc : fpu_config_type := (fpu => fpc, fregs => 0, version => 0);
----------------------------------------------------------------------------
-- CP configurations
----------------------------------------------------------------------------
constant cp_none : cp_config_type := (cp => none, version => 0);
constant cp_cpc : cp_config_type := (cp => cpc, version => 0);
----------------------------------------------------------------------------
-- cache configurations
----------------------------------------------------------------------------
constant cache_1k1k : cache_config_type := (
icachesize => 1, ilinesize => 4, dcachesize => 1, dlinesize => 4);
constant cache_2k1k : cache_config_type := (
icachesize => 2, ilinesize => 4, dcachesize => 1, dlinesize => 4);
constant cache_2k2k : cache_config_type := (
icachesize => 2, ilinesize => 4, dcachesize => 2, dlinesize => 4);
constant cache_2kl8_2kl4 : cache_config_type := (
icachesize => 2, ilinesize => 8, dcachesize => 2, dlinesize => 4);
constant cache_4k2k : cache_config_type := (
icachesize => 4, ilinesize => 8, dcachesize => 2, dlinesize => 4);
constant cache_1k4k : cache_config_type := (
icachesize => 1, ilinesize => 4, dcachesize => 4, dlinesize => 4);
constant cache_4k4k : cache_config_type := (
icachesize => 4, ilinesize => 4, dcachesize => 4, dlinesize => 4);
constant cache_8k8k : cache_config_type := (
icachesize => 8, ilinesize => 8, dcachesize => 8, dlinesize => 4);
----------------------------------------------------------------------------
-- Memory controller configurations
----------------------------------------------------------------------------
constant mctrl_std : mctrl_config_type := (
bus8en => true, bus16en => true, rawaddr => false);
constant mctrl_mem32 : mctrl_config_type := (
bus8en => false, bus16en => false, rawaddr => false);
constant mctrl_mem16 : mctrl_config_type := (
bus8en => false, bus16en => true, rawaddr => false);
----------------------------------------------------------------------------
-- boot configurations
----------------------------------------------------------------------------
constant boot_mem_25M : boot_config_type := (boot => memory, ramrws => 0,
ramwws => 0, sysclk => 24576000, baud => 38400, extbaud => false,
pabits => 8); -- 21.02.02 Booting system with 25 MHZ LA
constant boot_mem_33M : boot_config_type := (boot => memory, ramrws => 0,
ramwws => 0, sysclk => 33333333, baud => 38400, extbaud => false,
pabits => 8); -- 15.02.02 Booting system with 33.3 MHZ LA
constant boot_mem : boot_config_type := (boot => memory, ramrws => 0,
ramwws => 0, sysclk => 1000000, baud => 19200, extbaud => false,
pabits => 8);
constant boot_pmon : boot_config_type := (boot => prom, ramrws => 0,
ramwws => 0, sysclk => 24576000, baud => 38400, extbaud=> false,
pabits => 8);
constant boot_rdbmon : boot_config_type := (boot => prom, ramrws => 0,
ramwws => 0, sysclk => 24576000, baud => 38400, extbaud=> false,
pabits => 11);
constant boot_prom_xess16 : boot_config_type := (boot => prom, ramrws => 0,
ramwws => 0, sysclk => 25000000, baud => 38400, extbaud=> false,
pabits => 8);
----------------------------------------------------------------------------
-- PCI configurations
----------------------------------------------------------------------------
-- NOTE: 0x16E3 is ESA vendor ID - do NOT use without authorisation!!
-- NOTE: 0x1438 is ATMEL vendor ID - do NOT use without authorisation!!
constant pci_none : pci_config_type := (
pcicore => none, ahbmasters => 0, ahbslaves => 0,
arbiter => false, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_test : pci_config_type := (
pcicore => ahbtst, ahbmasters => 2, ahbslaves => 1,
arbiter => false, fixpri => true, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_insilicon : pci_config_type := (
pcicore => insilicon, ahbmasters => 2, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_esaif : pci_config_type := (
pcicore => esa, ahbmasters => 1, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_ahb_test : pci_config_type := (
pcicore => ahbtst, ahbmasters => 0, ahbslaves => 1,
arbiter => false, fixpri => true, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_atc25 : pci_config_type := (
pcicore => ahbtst, ahbmasters => 2, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
-- In-Silicon PCI core in ATMEL configuration
constant pci_atmel : pci_config_type := (
pcicore => insilicon, ahbmasters => 2, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#1438#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
----------------------------------------------------------------------------
-- Peripherals configurations
----------------------------------------------------------------------------
constant irq2none : irq2type := ( enable => false, channels => 32,
filter => (others => lvl0));
constant irq2chan4 : irq2type := ( enable => true, channels => 4,
filter => (lvl0, lvl1, edge0, edge1, others => lvl0));
constant peri_std : peri_config_type := (
cfgreg => true, ahbstat => true, wprot => true, wdog => true,
irq2cfg => irq2none);
constant peri_fpga : peri_config_type := (
cfgreg => true, ahbstat => false, wprot => false, wdog => false,
irq2cfg => irq2none);
constant peri_irq2 : peri_config_type := (
cfgreg => true, ahbstat => false, wprot => false, wdog => false,
irq2cfg => irq2chan4);
----------------------------------------------------------------------------
-- Debug configurations
----------------------------------------------------------------------------
constant debug_none : debug_config_type := ( enable => false, uart => false,
iureg => false, fpureg => false, nohalt => false, pclow => 2);
constant debug_disas : debug_config_type := ( enable => true, uart => false,
iureg => false, fpureg => false, nohalt => false, pclow => 2);
constant debug_msp : debug_config_type := ( enable => true, uart => false,
iureg => false, fpureg => false, nohalt => true, pclow => 2);
constant debug_uart : debug_config_type := ( enable => true, uart => true,
iureg => false, fpureg => false, nohalt => false, pclow => 0);
constant debug_fpu : debug_config_type := ( enable => true, uart => true,
iureg => false, fpureg => true, nohalt => false, pclow => 2);
constant debug_all : debug_config_type := ( enable => true, uart => true,
iureg => true, fpureg => true, nohalt => false, pclow => 0);
----------------------------------------------------------------------------
-- Amba AHB configurations
----------------------------------------------------------------------------
-- standard slave config
constant ahbslvcfg_std : ahb_slv_config_vector(0 to AHB_SLV_MAX-1) := (
-- first last index split enable function HADDR[31:28]
("0000", "0111", 0, false, true), -- memory controller, 0x0- 0x7
("1000", "1000", 1, false, true), -- APB bridge, 256 MB 0x8- 0x8
others => ahb_slv_config_void);
-- AHB test slave config
constant ahbslvcfg_test : ahb_slv_config_vector(0 to AHB_SLV_MAX-1) := (
-- first last index split enable function HADDR[31:28]
("0000", "0111", 0, false, true), -- memory controller, 0x0- 0x7
("1000", "1000", 1, false, true), -- APB bridge, 128 MB 0x8- 0x8
("1010", "1010", 2, true, true), -- AHB test module 0xA- 0xA
("1100", "1111", 3, false, true), -- PCI initiator 0xC- 0xF
others => ahb_slv_config_void);
-- PCI slave config
constant ahbslvcfg_pci : ahb_slv_config_vector(0 to AHB_SLV_MAX-1) := (
-- first last index split enable function HADDR[31:28]
("0000", "0111", 0, false, true), -- memory controller, 0x0- 0x7
("1000", "1000", 1, false, true), -- APB bridge, 128 MB 0x8- 0x8
("1010", "1111", 2, false, true), -- PCI initiator 0xA- 0xF
others => ahb_slv_config_void);
-- standard cacheability config
constant ahbcachecfg_std : ahb_cache_config_vector(0 to AHB_CACHE_MAX-1) := (
-- first last function HADDR[31:29]
("000", "000"), -- PROM area 0x0- 0x0
("010", "011"), -- RAM area 0x2- 0x3
others => ahb_cache_config_void);
-- standard config record
constant ahb_std : ahb_config_type := (
masters => 3, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_std, cachetable => ahbcachecfg_std);
-- FPGA config record
constant ahb_fpga : ahb_config_type := (
masters => 3, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_std, cachetable => ahbcachecfg_std);
-- Phoenix PCI core config record (uses two AHB master instefaces)
constant ahb_insilicon_pci : ahb_config_type := (
masters => 5, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_pci, cachetable => ahbcachecfg_std);
-- ESTEC PCI core config record (uses one AHB master insteface)
constant ahb_esa_pci : ahb_config_type := (
masters => 4, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_pci, cachetable => ahbcachecfg_std);
-- AHB test config
constant ahb_test : ahb_config_type := (
masters => 5, defmst => 0, split => true, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_test, cachetable => ahbcachecfg_std);
----------------------------------------------------------------------------
-- Amba APB configurations
----------------------------------------------------------------------------
-- standard config
constant apbslvcfg_std : apb_slv_config_vector(0 to APB_SLV_MAX-1) := (
-- first last index enable function PADDR[9:0]
( "0000000000", "0000001000", 0, true), -- memory controller, 0x00 - 0x08
( "0000001100", "0000010000", 1, true), -- AHB status reg., 0x0C - 0x10
( "0000010100", "0000011000", 2, true), -- cache controller, 0x14 - 0x18
( "0000011100", "0000100000", 3, true), -- write protection, 0x1C - 0x20
( "0000100100", "0000100100", 4, true), -- config register, 0x24 - 0x24
( "0001000000", "0001101100", 5, true), -- timers, 0x40 - 0x6C
( "0001110000", "0001111100", 6, true), -- uart1, 0x70 - 0x7C
( "0010000000", "0010001100", 7, true), -- uart2, 0x80 - 0x8C
( "0010010000", "0010011100", 8, true), -- interrupt ctrl 0x90 - 0x9C
( "0010100000", "0010101100", 9, true), -- I/O port 0xA0 - 0xAC
( "0100000000", "0111111100", 10, false), -- PCI configuration 0x100 - 0x1FC
( "1000000000", "1000011000", 11, true), -- ddm 0x200 - 0x218
( "1100000000", "1100011000", 12, true), -- mdct 0x300 - 0x318
others => apb_slv_config_void);
-- standard config with secondary interrupt controller
constant apbslvcfg_irq2 : apb_slv_config_vector(0 to APB_SLV_MAX-1) := (
-- first last index enable function PADDR[9:0]
( "0000000000", "0000001000", 0, true), -- memory controller, 0x00 - 0x08
( "0000001100", "0000010000", 1, true), -- AHB status reg., 0x0C - 0x10
( "0000010100", "0000011000", 2, true), -- cache controller, 0x14 - 0x18
( "0000011100", "0000100000", 3, true), -- write protection, 0x1C - 0x20
( "0000100100", "0000100100", 4, true), -- config register, 0x24 - 0x24
( "0001000000", "0001101100", 5, true), -- timers, 0x40 - 0x6C
( "0001110000", "0001111100", 6, true), -- uart1, 0x70 - 0x7C
( "0010000000", "0010001100", 7, true), -- uart2, 0x80 - 0x8C
( "0010010000", "0010011100", 8, true), -- interrupt ctrl 0x90 - 0x9C
( "0010100000", "0010101100", 9, true), -- I/O port 0xA0 - 0xAC
( "0010110000", "0010111100", 10, true), -- 2nd interrupt ctrl 0xB0 - 0xBC
( "1000000000", "1000011000", 11, true), -- ddm 0x200 - 0x218
( "1100000000", "1100011000", 12, true), -- mdct 0x300 - 0x318
others => apb_slv_config_void);
-- PCI config
constant apbslvcfg_pci : apb_slv_config_vector(0 to APB_SLV_MAX-1) := (
-- first last index enable function PADDR[9:0]
( "0000000000", "0000001000", 0, true), -- memory controller, 0x00 - 0x08
( "0000001100", "0000010000", 1, true), -- AHB status reg., 0x0C - 0x10
( "0000010100", "0000011000", 2, true), -- cache controller, 0x14 - 0x18
( "0000011100", "0000100000", 3, true), -- write protection, 0x1C - 0x20
( "0000100100", "0000100100", 4, true), -- config register, 0x24 - 0x24
( "0001000000", "0001101100", 5, true), -- timers, 0x40 - 0x6C
( "0001110000", "0001111100", 6, true), -- uart1, 0x70 - 0x7C
( "0010000000", "0010001100", 7, true), -- uart2, 0x80 - 0x8C
( "0010010000", "0010011100", 8, true), -- interrupt ctrl 0x90 - 0x9C
( "0010100000", "0010101100", 9, true), -- I/O port 0xA0 - 0xAC
( "0100000000", "0111111100", 10, true), -- PCI configuration 0x100- 0x1FC
( "1000000000", "1011111100", 11, true), -- PCI arbiter 0x200- 0x2FC
others => apb_slv_config_void);
constant apb_std : apb_config_type := (table => apbslvcfg_std);
constant apb_irq2 : apb_config_type := (table => apbslvcfg_irq2);
constant apb_pci : apb_config_type := (table => apbslvcfg_pci);
----------------------------------------------------------------------------
-- Pre-defined LEON configurations
----------------------------------------------------------------------------
-- VIRTEX, 2 + 2 Kbyte cache, fpu
constant virtex_2k2k_25M_fpu : config_type := (
synthesis => syn_virtex, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_25M, debug => debug_all, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 4 + 4 Kbyte cache, mul/div, fpu, 25M
constant fpga_4k4k_v8_fpu_33M : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_4k4k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_33M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache 25 MHz
constant fpga_2k2k_25M : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_25M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache 25 MHz
constant fpga_2k2k_fpu_bprom_25M : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_meiko, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache 33.3 MHz
constant fpga_2k2k_33M : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_33M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache
constant fpga_2k2k : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_uart, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, mul/div
constant fpga_2k2k_v8 : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, secondary irq controller (test only)
constant fpga_2k2k_irq2 : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_irq2, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_irq2);
-- Any FPGA, 2 + 2 Kbyte cache, inferred boot-prom
constant fpga_2k2k_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, inferred boot-prom, mul/div
constant fpga_2k2k_v8_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 4 + 4 Kbyte cache, mul/div, fpu
constant fpga_4k4k_v8_fpu : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_4k4k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_25M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 4 + 4 Kbyte cache, inferred boot-prom, mul/div, fpu
constant fpga_4k4k_v8_fpu_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_4k4k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, inferred boot-prom, mul/div, MAC
constant fpga_2k2k_v8_mac_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_mac, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- VIRTEX, 2 + 2 Kbyte cache, hard boot-prom
constant virtex_2k2k_blockprom : config_type := (
synthesis => syn_virtex_blockprom, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- VIRTEX, 2 + 1 Kbyte cache, hard boot-prom with rdbmon
constant virtex_2k1k_rdbmon : config_type := (
synthesis => syn_virtex_blockprom, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k1k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_rdbmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- VIRTEX, 2 + 2 Kbyte cache, hard boot-prom, mul/div
constant virtex_2k2k_v8_fpu_blockprom : config_type := (
synthesis => syn_virtex_blockprom, iu => iu_fpga_v8, fpu => fpu_meiko, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- synthesis targetting ATC25 asic lib
constant gen_atc25 : config_type := (
synthesis => syn_atc25, iu => iu_atc25, fpu => fpu_none, cp => cp_none,
cache => cache_8k8k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting ATC25 asic lib, serial Meiko FPU
constant gen_atc25_meiko : config_type := (
synthesis => syn_atc25, iu => iu_atc25_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_8k8k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting ATC25 asic lib, parallel FPU
constant gen_atc25_fpc : config_type := (
synthesis => syn_atc25, iu => iu_atc25_fpu, fpu => fpu_fpc, cp => cp_none,
cache => cache_8k8k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting ATC25 asic lib + Insilicon PCI core
constant gen_atc25_insilicon_pci : config_type := (
synthesis => syn_atc25, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_4k4k, ahb => ahb_insilicon_pci, apb => apb_pci,
mctrl => mctrl_std, boot => boot_mem, debug => debug_disas, pci => pci_atmel,
peri => peri_std);
-- simulatiom with Insilicon PCI core
constant gen_insilicon_pci : config_type := (
synthesis => syn_gen, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_insilicon_pci, apb => apb_pci,
mctrl => mctrl_std, boot => boot_mem, debug => debug_disas, pci => pci_atmel,
peri => peri_std);
-- synthesis targetting ATC35 asic lib, synopsys
constant gen_atc35 : config_type := (
synthesis => syn_atc35, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_4k4k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- Systel FPGA configuration
constant systel_fpga : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_1k1k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- Systel ASIC configuration
constant systel_asic : config_type := (
synthesis => syn_systel_asic, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_1k1k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting UMC FS90A/B asic lib
constant gen_fs90 : config_type := (
synthesis => syn_fs90, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting UMC18 asic lib, synopsys + AMBIT
constant gen_umc18 : config_type := (
synthesis => syn_umc18, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_4k4k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
end;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Jidan FPU/trunk/comppack.vhd | 3 | 7722 | -------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: component package
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.fpupack.all;
package comppack is
--- Component Declartions ---
--***Add/Substract units***
component pre_norm_addsub is
port(clk_i : in std_logic;
opa_i : in std_logic_vector(31 downto 0);
opb_i : in std_logic_vector(31 downto 0);
fracta_28_o : out std_logic_vector(27 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
fractb_28_o : out std_logic_vector(27 downto 0);
exp_o : out std_logic_vector(7 downto 0));
end component;
component addsub_28 is
port(clk_i : in std_logic;
fpu_op_i : in std_logic;
fracta_i : in std_logic_vector(27 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
fractb_i : in std_logic_vector(27 downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
fract_o : out std_logic_vector(27 downto 0);
sign_o : out std_logic);
end component;
component post_norm_addsub is
port(clk_i : in std_logic;
opa_i : in std_logic_vector(31 downto 0);
opb_i : in std_logic_vector(31 downto 0);
fract_28_i : in std_logic_vector(27 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
exp_i : in std_logic_vector(7 downto 0);
sign_i : in std_logic;
fpu_op_i : in std_logic;
rmode_i : in std_logic_vector(1 downto 0);
output_o : out std_logic_vector(31 downto 0);
ine_o : out std_logic
);
end component;
--***Multiplication units***
component pre_norm_mul is
port(
clk_i : in std_logic;
opa_i : in std_logic_vector(31 downto 0);
opb_i : in std_logic_vector(31 downto 0);
exp_10_o : out std_logic_vector(9 downto 0);
fracta_24_o : out std_logic_vector(23 downto 0); -- hidden(1) & fraction(23)
fractb_24_o : out std_logic_vector(23 downto 0)
);
end component;
component mul_24 is
port(
clk_i : in std_logic;
fracta_i : in std_logic_vector(23 downto 0); -- hidden(1) & fraction(23)
fractb_i : in std_logic_vector(23 downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
start_i : in std_logic;
fract_o : out std_logic_vector(47 downto 0);
sign_o : out std_logic;
ready_o : out std_logic
);
end component;
component serial_mul is
port(
clk_i : in std_logic;
fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
start_i : in std_logic;
fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
sign_o : out std_logic;
ready_o : out std_logic
);
end component;
component post_norm_mul is
port(
clk_i : in std_logic;
opa_i : in std_logic_vector(31 downto 0);
opb_i : in std_logic_vector(31 downto 0);
exp_10_i : in std_logic_vector(9 downto 0);
fract_48_i : in std_logic_vector(47 downto 0); -- hidden(1) & fraction(23)
sign_i : in std_logic;
rmode_i : in std_logic_vector(1 downto 0);
output_o : out std_logic_vector(31 downto 0);
ine_o : out std_logic
);
end component;
--***Division units***
component pre_norm_div is
port(
clk_i : in std_logic;
opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
exp_10_o : out std_logic_vector(EXP_WIDTH+1 downto 0);
dvdnd_50_o : out std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0);
dvsor_27_o : out std_logic_vector(FRAC_WIDTH+3 downto 0)
);
end component;
component serial_div is
port(
clk_i : in std_logic;
dvdnd_i : in std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0); -- hidden(1) & fraction(23)
dvsor_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);
sign_dvd_i : in std_logic;
sign_div_i : in std_logic;
start_i : in std_logic;
ready_o : out std_logic;
qutnt_o : out std_logic_vector(FRAC_WIDTH+3 downto 0);
rmndr_o : out std_logic_vector(FRAC_WIDTH+3 downto 0);
sign_o : out std_logic;
div_zero_o : out std_logic
);
end component;
component post_norm_div is
port(
clk_i : in std_logic;
opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
qutnt_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);
rmndr_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);
exp_10_i : in std_logic_vector(EXP_WIDTH+1 downto 0);
sign_i : in std_logic;
rmode_i : in std_logic_vector(1 downto 0);
output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
ine_o : out std_logic
);
end component;
--***Square units***
component pre_norm_sqrt is
port(
clk_i : in std_logic;
opa_i : in std_logic_vector(31 downto 0);
fracta_52_o : out std_logic_vector(51 downto 0);
exp_o : out std_logic_vector(7 downto 0));
end component;
component sqrt is
generic (RD_WIDTH: integer; SQ_WIDTH: integer); -- SQ_WIDTH = RD_WIDTH/2 (+ 1 if odd)
port(
clk_i : in std_logic;
rad_i : in std_logic_vector(RD_WIDTH-1 downto 0); -- hidden(1) & fraction(23)
start_i : in std_logic;
ready_o : out std_logic;
sqr_o : out std_logic_vector(SQ_WIDTH-1 downto 0);
ine_o : out std_logic);
end component;
component post_norm_sqrt is
port( clk_i : in std_logic;
opa_i : in std_logic_vector(31 downto 0);
fract_26_i : in std_logic_vector(25 downto 0); -- hidden(1) & fraction(11)
exp_i : in std_logic_vector(7 downto 0);
ine_i : in std_logic;
rmode_i : in std_logic_vector(1 downto 0);
output_o : out std_logic_vector(31 downto 0);
ine_o : out std_logic);
end component;
end comppack; | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Jidan FPU/trunk/fpupack.vhd | 3 | 3831 | -------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: FPU package wich contains constants and functions needed in the FPU core
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package fpupack is
-- Data width of floating-point number. Deafult: 32
constant FP_WIDTH : integer := 32;
-- Data width of fraction. Deafult: 23
constant FRAC_WIDTH : integer := 23;
-- Data width of exponent. Deafult: 8
constant EXP_WIDTH : integer := 8;
--Zero vector
constant ZERO_VECTOR: std_logic_vector(30 downto 0) := "0000000000000000000000000000000";
-- Infinty FP format
constant INF : std_logic_vector(30 downto 0) := "1111111100000000000000000000000";
-- QNaN (Quit Not a Number) FP format (without sign bit)
constant QNAN : std_logic_vector(30 downto 0) := "1111111110000000000000000000000";
-- SNaN (Signaling Not a Number) FP format (without sign bit)
constant SNAN : std_logic_vector(30 downto 0) := "1111111100000000000000000000001";
-- count the zeros starting from left
function count_l_zeros (signal s_vector: std_logic_vector) return std_logic_vector;
-- count the zeros starting from right
function count_r_zeros (signal s_vector: std_logic_vector) return std_logic_vector;
end fpupack;
package body fpupack is
-- count the zeros starting from left
function count_l_zeros (signal s_vector: std_logic_vector) return std_logic_vector is
variable v_count : std_logic_vector(5 downto 0);
begin
v_count := "000000";
for i in s_vector'range loop
case s_vector(i) is
when '0' => v_count := v_count + "000001";
when others => exit;
end case;
end loop;
return v_count;
end count_l_zeros;
-- count the zeros starting from right
function count_r_zeros (signal s_vector: std_logic_vector) return std_logic_vector is
variable v_count : std_logic_vector(5 downto 0);
begin
v_count := "000000";
for i in 0 to s_vector'length-1 loop
case s_vector(i) is
when '0' => v_count := v_count + "000001";
when others => exit;
end case;
end loop;
return v_count;
end count_r_zeros;
end fpupack; | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Jidan FPU/tags/arelease/fpupack.vhd | 3 | 3831 | -------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: FPU package wich contains constants and functions needed in the FPU core
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package fpupack is
-- Data width of floating-point number. Deafult: 32
constant FP_WIDTH : integer := 32;
-- Data width of fraction. Deafult: 23
constant FRAC_WIDTH : integer := 23;
-- Data width of exponent. Deafult: 8
constant EXP_WIDTH : integer := 8;
--Zero vector
constant ZERO_VECTOR: std_logic_vector(30 downto 0) := "0000000000000000000000000000000";
-- Infinty FP format
constant INF : std_logic_vector(30 downto 0) := "1111111100000000000000000000000";
-- QNaN (Quit Not a Number) FP format (without sign bit)
constant QNAN : std_logic_vector(30 downto 0) := "1111111110000000000000000000000";
-- SNaN (Signaling Not a Number) FP format (without sign bit)
constant SNAN : std_logic_vector(30 downto 0) := "1111111100000000000000000000001";
-- count the zeros starting from left
function count_l_zeros (signal s_vector: std_logic_vector) return std_logic_vector;
-- count the zeros starting from right
function count_r_zeros (signal s_vector: std_logic_vector) return std_logic_vector;
end fpupack;
package body fpupack is
-- count the zeros starting from left
function count_l_zeros (signal s_vector: std_logic_vector) return std_logic_vector is
variable v_count : std_logic_vector(5 downto 0);
begin
v_count := "000000";
for i in s_vector'range loop
case s_vector(i) is
when '0' => v_count := v_count + "000001";
when others => exit;
end case;
end loop;
return v_count;
end count_l_zeros;
-- count the zeros starting from right
function count_r_zeros (signal s_vector: std_logic_vector) return std_logic_vector is
variable v_count : std_logic_vector(5 downto 0);
begin
v_count := "000000";
for i in 0 to s_vector'length-1 loop
case s_vector(i) is
when '0' => v_count := v_count + "000001";
when others => exit;
end case;
end loop;
return v_count;
end count_r_zeros;
end fpupack; | gpl-3.0 |
Akkadius/EQEmuEOC | modules/commander/ace/build/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon2-1.0.2a/leon/ahbmst.vhd | 1 | 4293 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: ahbmst
-- File: ahbmst.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple AHB master interface
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_arith.conv_unsigned;
use work.amba.all;
use work.iface.all;
use work.macro.all;
entity ahbmst is
generic (incaddr : integer := 0);
port (
rst : in std_logic;
clk : in clk_type;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture rtl of ahbmst is
type reg_type is record
start : std_logic;
retry : std_logic;
grant : std_logic;
active : std_logic;
end record;
signal r, rin : reg_type;
begin
comb : process(ahbi, dmai, rst, r)
variable v : reg_type;
variable ready : std_logic;
variable retry : std_logic;
variable mexc : std_logic;
variable inc : std_logic_vector(3 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(31 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_logic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(9 downto 0); -- next sequential address
variable hbusreq : std_logic; -- bus request
begin
v := r; ready := '0'; mexc := '0'; retry := '0';
haddr := dmai.address; hbusreq := dmai.start; hwdata := dmai.wdata;
newaddr := dmai.address(9 downto 0);
inc := decode(dmai.size);
if incaddr > 0 then
-- pragma translate_off
if not is_x(haddr(9 downto 0)) then
-- pragma translate_on
newaddr := haddr(9 downto 0) + inc(3 downto 1);
-- pragma translate_off
end if;
-- pragma translate_on
end if;
hburst := HBURST_SINGLE;
if dmai.start = '1' then
if (r.active and dmai.burst and not r.retry) = '1' then
htrans := HTRANS_SEQ; hburst := HBURST_INCR;
haddr(9 downto 0) := newaddr;
else htrans := HTRANS_NONSEQ; end if;
else htrans := HTRANS_IDLE; end if;
if r.active = '1' then
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => ready := '1';
when HRESP_RETRY | HRESP_SPLIT=> retry := '1';
when others => ready := '1'; mexc := '1';
end case;
end if;
if ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT)) then
v.retry := not ahbi.hready;
else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
v.start := '0';
if ahbi.hready = '1' then
v.grant := ahbi.hgrant;
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.active := r.grant; v.start := r.grant;
else
v.active := '0';
end if;
end if;
if rst = '0' then v.retry := '0'; v.active := '0'; end if;
rin <= v;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= dmai.wdata;
ahbo.hlock <= '0';
ahbo.hwrite <= dmai.write;
ahbo.hsize <= '0' & dmai.size;
ahbo.hburst <= hburst;
ahbo.hprot <= "0011"; -- non-cached supervisor data
dmao.start <= r.start;
dmao.active <= r.active;
dmao.ready <= ready;
dmao.mexc <= mexc;
dmao.retry <= retry;
dmao.haddr <= newaddr;
dmao.rdata <= ahbi.hrdata;
end process;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon2-1.0.2a/leon/fpu_lth.vhd | 1 | 35187 | -------------------------------------------------------------------------------
-- Copyright (C) 2002 Martin Kasprzyk <[email protected]>
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-------------------------------------------------------------------------------
-- File : fpu.vhd
-- Author : Martin Kasprzyk <[email protected]>
-------------------------------------------------------------------------------
-- Description: A IEEE754 floating point unit for the LEON SPARC processor
-------------------------------------------------------------------------------
-- Modfied by Jiri Gaisler to:
-- * be VHDL-87 compatible
-- * remove ambiguity for std_logic +,-, and > operands.
-- * supress 'X' warnings from std_logic_arith packages
-------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned."-";
use ieee.std_logic_unsigned."+";
use ieee.numeric_std.all;
use work.iface.all;
use work.sparcv8.all;
entity fpu_lth is
port(
ss_clock : in std_logic;
FpInst : in std_logic_vector(9 downto 0);
FpOp : in std_logic;
FpLd : in std_logic;
Reset : in std_logic;
fprf_dout1 : in std_logic_vector(63 downto 0);
fprf_dout2 : in std_logic_vector(63 downto 0);
RoundingMode : in std_logic_vector(1 downto 0);
FpBusy : out std_logic;
FracResult : out std_logic_vector(54 downto 3);
ExpResult : out std_logic_vector(10 downto 0);
SignResult : out std_logic;
SNnotDB : out std_logic; -- Not used
Excep : out std_logic_vector(5 downto 0);
ConditionCodes : out std_logic_vector(1 downto 0);
ss_scan_mode : in std_logic; -- Not used
fp_ctl_scan_in : in std_logic; -- Not used
fp_ctl_scan_out : out std_logic -- Not used
);
end;
architecture rtl of fpu_lth is
constant zero : std_logic_vector(63 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Leading zero counter.
-------------------------------------------------------------------------------
procedure lz_counter (
in_vect : in std_logic_vector(55 downto 0);
leading_zeros : out std_logic_vector(5 downto 0)) is
variable pos_mask : std_logic_vector(55 downto 0);
variable neg_mask : std_logic_vector(55 downto 0);
variable leading_one : std_logic_vector(55 downto 0);
variable nr_zeros : std_logic_vector(5 downto 0);
begin
-- Find leading one e.g. if in_vect = 00101101 then pos_mask = 00111111
-- and neg_mask = "11100000, performing and gives leading_one = 00100000
pos_mask(55) := in_vect(55);
for i in 54 downto 0 loop
pos_mask(i) := pos_mask(i+1) or in_vect(i);
end loop;
neg_mask := "1" & (not pos_mask(55 downto 1));
leading_one := pos_mask and neg_mask;
-- Get number of leading zeros from the leading_one vector
nr_zeros := "000000";
for i in 1 to 55 loop
if (i / 32) /= 0 then
nr_zeros(5) := nr_zeros(5) or leading_one(55-i);
end if;
if ((i mod 32) / 16) /= 0 then
nr_zeros(4) := nr_zeros(4) or leading_one(55-i);
end if;
if (((i mod 32) mod 16) / 8) /= 0 then
nr_zeros(3) := nr_zeros(3) or leading_one(55-i);
end if;
if ((((i mod 32) mod 16) mod 8) / 4) /= 0 then
nr_zeros(2) := nr_zeros(2) or leading_one(55-i);
end if;
if (((((i mod 32) mod 16) mod 8) mod 4) / 2) /= 0 then
nr_zeros(1) := nr_zeros(1) or leading_one(55-i);
end if;
if (i mod 2) /= 0 then
nr_zeros(0) := nr_zeros(0) or leading_one(55-i);
end if;
end loop;
-- Return result
leading_zeros := nr_zeros;
end lz_counter;
-------------------------------------------------------------------------------
-- Variable amount right shifter with sticky bit calculation.
-------------------------------------------------------------------------------
procedure right_shifter_sticky (
in_vect : in std_logic_vector(54 downto 0);
amount : in std_logic_vector(5 downto 0);
out_vect : out std_logic_vector(54 downto 0);
sticky_bit : out std_logic) is
variable after32 : std_logic_vector(54 downto 0);
variable after16 : std_logic_vector(54 downto 0);
variable after8 : std_logic_vector(54 downto 0);
variable after4 : std_logic_vector(54 downto 0);
variable after2 : std_logic_vector(54 downto 0);
variable after1 : std_logic_vector(54 downto 0);
variable sticky32 : std_logic;
variable sticky16 : std_logic;
variable sticky8 : std_logic;
variable sticky4 : std_logic;
variable sticky2 : std_logic;
variable sticky1 : std_logic;
begin
-- If amount(5) = '1' then shift vector 32 positions right
if amount(5) = '1' then
after32 := zero(31 downto 0) & in_vect(54 downto 32);
if in_vect(31 downto 0) /= zero(31 downto 0) then
sticky32 := '1';
else
sticky32 := '0';
end if;
else
after32 := in_vect;
sticky32 := '0';
end if;
-- If amount(4) = '1' then shift vector 16 positions right
if amount(4) = '1' then
after16 := zero(15 downto 0) & after32(54 downto 16);
if after32(15 downto 0) /= zero(15 downto 0) then
sticky16 := '1';
else
sticky16 := '0';
end if;
else
after16 := after32;
sticky16 := '0';
end if;
-- If amount(3) = '1' then shift vector 8 positions right
if amount(3) = '1' then
after8 := zero(7 downto 0) & after16(54 downto 8);
if after16(7 downto 0) /= zero(7 downto 0) then
sticky8 := '1';
else
sticky8 := '0';
end if;
else
after8 := after16;
sticky8 := '0';
end if;
-- If amount(2) = '1' then shift vector 4 positions right
if amount(2) = '1' then
after4 := zero(3 downto 0) & after8(54 downto 4);
if after8(3 downto 0) /= zero(3 downto 0) then
sticky4 := '1';
else
sticky4 := '0';
end if;
else
after4 := after8;
sticky4 := '0';
end if;
-- If amount(1) = '1' then shift vector 2 positions right
if amount(1) = '1' then
after2 := "00" & after4(54 downto 2);
if after4(1 downto 0) /= "00" then
sticky2 := '1';
else
sticky2 := '0';
end if;
else
after2 := after4;
sticky2 := '0';
end if;
-- If amount(0) = '1' then shift vector 1 positions right
if amount(1) = '1' then
after1 := "0" & after2(54 downto 1);
sticky1 := after2(0);
else
after1 := after2;
sticky1 := '0';
end if;
-- Return values
out_vect := after1;
sticky_bit := sticky32 or sticky16 or sticky8 or sticky4 or sticky2 or
sticky1;
end right_shifter_sticky;
-------------------------------------------------------------------------------
-- Variable amount left shifter
-------------------------------------------------------------------------------
procedure left_shifter (
in_vect : in std_logic_vector(56 downto 0);
amount : in std_logic_vector(5 downto 0);
out_vect : out std_logic_vector(56 downto 0)) is
variable after32 : std_logic_vector(56 downto 0);
variable after16 : std_logic_vector(56 downto 0);
variable after8 : std_logic_vector(56 downto 0);
variable after4 : std_logic_vector(56 downto 0);
variable after2 : std_logic_vector(56 downto 0);
variable after1 : std_logic_vector(56 downto 0);
begin
-- If amount(5) = '1' then shift vector 32 positions left
if amount(5) = '1' then
after32 := in_vect(24 downto 0) & zero(31 downto 0);
else
after32 := in_vect;
end if;
-- If amount(4) = '1' then shift vector 16 positions left
if amount(4) = '1' then
after16 := after32(40 downto 0) & zero(15 downto 0);
else
after16 := after32;
end if;
-- If amount(3) = '1' then shift vector 8 positions left
if amount(3) = '1' then
after8 := after16(48 downto 0) & zero(7 downto 0);
else
after8 := after16;
end if;
-- If amount(2) = '1' then shift vector 4 positions left
if amount(2) = '1' then
after4 := after8(52 downto 0) & zero(3 downto 0);
else
after4 := after8;
end if;
-- If amount(1) = '1' then shift vector 2 positions left
if amount(1) = '1' then
after2 := after4(54 downto 0) & "00";
else
after2 := after4;
end if;
-- If amount(0) = '1' then shift vector 1 positions left
if amount(1) = '1' then
after1 := after2(55 downto 0) & "0";
else
after1 := after2;
end if;
-- Return value
out_vect := after1;
end left_shifter;
-------------------------------------------------------------------------------
-- Declaration of record types used to pass signals between pipeline stages.
-------------------------------------------------------------------------------
type op_decode_stage_type is record -- input <-> op_decode
opcode : std_logic_vector(9 downto 0);
end record;
type prenorm_stage_type is record -- op_decode <-> prenorm
sign1 : std_logic;
exp1 : std_logic_vector(10 downto 0);
frac1 : std_logic_vector(51 downto 0);
sign2 : std_logic;
exp2 : std_logic_vector(10 downto 0);
frac2 : std_logic_vector(51 downto 0);
single : std_logic; -- Single precision
comp : std_logic; -- Compare and set cc
gen_ex : std_logic; -- Generate exception if unordered
op1_denorm : std_logic;
op2_denorm : std_logic;
op1_inf : std_logic;
op2_inf : std_logic;
op1_NaN : std_logic;
op2_NaN : std_logic;
op1_SNaN : std_logic;
op2_SNaN : std_logic;
end record;
type addsub_stage_type is record -- prenorm <-> addsub
sign_a : std_logic;
a : std_logic_vector(56 downto 0);
sign_b : std_logic;
b : std_logic_vector(56 downto 0);
exp : std_logic_vector(10 downto 0);
single : std_logic; -- Single precision
comp : std_logic; -- Compare and set cc
gen_ex : std_logic; -- Generate exception if unordered
swaped : std_logic; -- Operands swaped during pre_norm
op1_inf : std_logic;
op2_inf : std_logic;
op1_NaN : std_logic;
op2_NaN : std_logic;
op1_SNaN : std_logic;
op2_SNaN : std_logic;
end record;
type postnorm_stage_type is record -- addsub <-> postnorm
frac : std_logic_vector(56 downto 0);
exp : std_logic_vector(10 downto 0);
sign : std_logic;
single : std_logic; -- Single precision
comp : std_logic; -- Compare and set cc
cc : std_logic_vector(1 downto 0); -- Condition codes
exc : std_logic_vector(4 downto 0); -- Exceptions
res_inf : std_logic;
res_NaN : std_logic;
res_SNaN : std_logic;
res_zero : std_logic;
end record;
type roundnorm_stage_type is record -- postnorm <-> roundnorm
frac : std_logic_vector(56 downto 0);
exp : std_logic_vector(10 downto 0);
sign : std_logic;
single : std_logic; -- Single precision
comp : std_logic; -- Compare and set cc
cc : std_logic_vector(1 downto 0); -- Condition codes
exc : std_logic_vector(4 downto 0); -- Exceptions
res_inf : std_logic;
res_NaN : std_logic;
res_SNaN : std_logic;
end record;
type fpu_result_type is record -- roundnorm <-> out
frac : std_logic_vector(51 downto 0);
exp : std_logic_vector(10 downto 0);
sign : std_logic;
cc : std_logic_vector(1 downto 0);
exc : std_logic_vector(5 downto 0);
end record;
-------------------------------------------------------------------------------
-- Declaration of input and output signal from the different pipeline
-- registers.
-------------------------------------------------------------------------------
signal de, de_in : op_decode_stage_type;
signal pren, pren_in : prenorm_stage_type;
signal as, as_in : addsub_stage_type;
signal posn, posn_in : postnorm_stage_type;
signal rnd, rnd_in : roundnorm_stage_type;
signal rnd_out : fpu_result_type;
-------------------------------------------------------------------------------
-- Type and signals used by generate busy process. In the fututure this process
-- might be integrated into the pipeline but for now a seperat process is used.
-------------------------------------------------------------------------------
type fpu_state is (start, get_operand, pre_norm, add_sub, post_norm,
rnd_norm, hold_val);
signal state, next_state : fpu_state;
signal result_ready : std_logic;
begin -- rtl
de_in.opcode <= FpInst;
-------------------------------------------------------------------------------
-- Opcode decode and unpacking stage
-------------------------------------------------------------------------------
decode_stage: process (de, fprf_dout1, fprf_dout2)
variable single : std_logic;
variable exp1 : std_logic_vector(10 downto 0);
variable exp2 : std_logic_vector(10 downto 0);
variable frac1 : std_logic_vector(51 downto 0);
variable frac2 : std_logic_vector(51 downto 0);
variable frac1_zero : std_logic;
variable frac2_zero : std_logic;
variable exp1_max : std_logic;
variable exp2_max : std_logic;
variable exp1_min : std_logic;
variable exp2_min : std_logic;
begin
-- Get sign bit for op1
pren_in.sign1 <= fprf_dout1(63);
-- Unpack exponent and fraction depending on the precision mode. Note that
-- if single precision is used som bit filling must be done for the
-- exponent and fraction since double precision is used internally.
if de.opcode(1 downto 0) = "01" then -- If single precision
single := '1';
exp1 := "000" & fprf_dout1(62 downto 55);
frac1 := "0" & zero(27 downto 0) & fprf_dout1(54 downto 32);
exp2 := "000" & fprf_dout2(62 downto 55);
frac2 := "0" & zero(27 downto 0) & fprf_dout2(54 downto 32);
else
-- If double precision
single := '0';
exp1 := fprf_dout1(62 downto 52);
frac1 := fprf_dout1(51 downto 0);
exp2 := fprf_dout2(62 downto 52);
frac2 := fprf_dout2(51 downto 0);
end if;
-- Check if fracions zero
if frac1 = zero(51 downto 0) then
frac1_zero := '1';
else
frac1_zero := '0';
end if;
if frac2 = zero(51 downto 0) then
frac2_zero := '1';
else
frac2_zero := '0';
end if;
-- Check if exp is max or min
if (exp1(7 downto 0) = "11111111") and
((single = '1') or (exp1(10 downto 8) = "111")) then
exp1_max := '1';
exp1_min := '0';
elsif exp1 = "00000000000" then
exp1_max := '0';
exp1_min := '1';
else
exp1_max := '0';
exp1_min := '0';
end if;
if (exp2(7 downto 0) = "11111111") and
((single = '1') or (exp2(10 downto 8) = "111")) then
exp2_max := '1';
exp2_min := '0';
elsif exp2 = "00000000000" then
exp2_max := '0';
exp2_min := '1';
else
exp2_max := '0';
exp2_min := '0';
end if;
-- Detect special numbers
pren_in.op1_denorm <= exp1_min;
pren_in.op2_denorm <= exp2_min;
pren_in.op1_inf <= exp1_max and frac1_zero;
pren_in.op2_inf <= exp2_max and frac2_zero;
pren_in.op1_SNaN <= exp1_max and (not frac1_zero) and
not (frac1(51) or (frac1(22) and single));
pren_in.op2_SNaN <= exp2_max and (not frac2_zero) and
not (frac2(51) or (frac2(22) and single));
pren_in.op1_NaN <= exp1_max and (not frac1_zero) and
(frac1(51) or (frac1(22) and single));
pren_in.op2_NaN <= exp2_max and (not frac2_zero) and
(frac2(51) or (frac2(22) and single));
-- Decode instruction. If operation is sub or cmp then negate op2 sign.
-- Unimplemented opcodes will result in addition.
case de.opcode(8 downto 0) is
when FSUBS | FSUBD => pren_in.sign2 <= not fprf_dout2(63);
pren_in.comp <= '0';
pren_in.gen_ex <= '0';
when FCMPS | FCMPD => pren_in.sign2 <= not fprf_dout2(63);
pren_in.comp <= '1';
pren_in.gen_ex <= '0';
when FCMPES | FCMPED => pren_in.sign2 <= not fprf_dout2(63);
pren_in.comp <= '1';
pren_in.gen_ex <= '1';
when others => pren_in.sign2 <= fprf_dout2(63);
pren_in.comp <= '0';
pren_in.gen_ex <= '0';
end case;
pren_in.single <= single;
pren_in.frac1 <= frac1;
pren_in.exp1 <= exp1;
pren_in.frac2 <= frac2;
pren_in.exp2 <= exp2;
end process decode_stage;
-------------------------------------------------------------------------------
-- Prenorm stage
-------------------------------------------------------------------------------
prenorm_stage: process (pren)
variable switch_ops : std_logic;
variable sign_diff : std_logic_vector(11 downto 0);
variable abs_diff : std_logic_vector(11 downto 0);
variable all_zero : std_logic_vector(11 downto 0);
variable shift_amount : std_logic_vector(5 downto 0);
variable adj_op : std_logic_vector(54 downto 0);
variable shifted_op : std_logic_vector(54 downto 0);
variable sticky_bit : std_logic;
begin
all_zero := (others => '0');
-- Calculate differens
-- pragma translate_off
if not is_x(pren.exp1 & pren.exp2) then
-- pragma translate_on
sign_diff := ("0" & pren.exp1) - ("0" & pren.exp2);
-- pragma translate_off
end if;
-- pragma translate_on
switch_ops := sign_diff(11); -- Switch needed
-- If negative get absolute value
if sign_diff(11) = '1' then
-- pragma translate_off
if not is_x(all_zero & sign_diff) then
-- pragma translate_on
abs_diff := all_zero - sign_diff;
-- pragma translate_off
end if;
-- pragma translate_on
else
abs_diff := sign_diff(11 downto 0);
end if;
-- Not needed to shift more then the length of the fraction
-- pragma translate_off
if not is_x(abs_diff) then
-- pragma translate_on
if ieee.std_logic_unsigned.">"(abs_diff, 52) then
shift_amount := "110100";
else
shift_amount := abs_diff(5 downto 0);
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- Do switch of operands if needed. Then retrieve the hidden bit for the
-- larger operand and append overflow, guard, round and sticky bit. For the
-- smaller operand retrive hidden bit and append guard and round bit.
if switch_ops = '1' then
as_in.a <= "0" & (not pren.op2_denorm) & pren.frac2 & "000";
as_in.exp <= pren.exp2;
as_in.sign_a <= pren.sign2;
as_in.sign_b <= pren.sign1;
adj_op := (not pren.op1_denorm) & pren.frac1 & "00";
else
as_in.a <= "0" & (not pren.op1_denorm) & pren.frac1 & "000";
as_in.exp <= pren.exp1;
as_in.sign_a <= pren.sign1;
as_in.sign_b <= pren.sign2;
adj_op := (not pren.op2_denorm) & pren.frac2 & "00";
end if;
-- Shift smaller operand right and get sticky bit.
right_shifter_sticky(adj_op,shift_amount,shifted_op,sticky_bit);
-- Add overflow and sticky bit for shifted smaller operand.
as_in.b <= "0" & shifted_op & sticky_bit;
as_in.swaped <= switch_ops;
as_in.op1_inf <= pren.op1_inf;
as_in.op2_inf <= pren.op2_inf;
as_in.op1_NaN <= pren.op1_NaN;
as_in.op2_NaN <= pren.op2_Nan;
as_in.op1_SNaN <= pren.op1_SNaN;
as_in.op2_SNaN <= pren.op2_SNaN;
as_in.single <= pren.single;
as_in.comp <= pren_in.comp;
as_in.gen_ex <= pren_in.gen_ex;
end process prenorm_stage;
-------------------------------------------------------------------------------
-- Add/Sub stage
-------------------------------------------------------------------------------
addsub_stage: process (as)
variable signs : std_logic_vector(1 downto 0);
variable result : std_logic_vector(56 downto 0);
variable temp : std_logic_vector(56 downto 0);
variable neg_value : std_logic;
variable all_zero : std_logic_vector(56 downto 0);
variable unordered : std_logic;
variable zero_fraction : std_logic;
variable cc_bit0 : std_logic;
variable cc_bit1 : std_logic;
variable SNaN : std_logic;
variable NaN : std_logic;
variable inf : std_logic;
begin
all_zero := (others => '0');
signs := as.sign_a & as.sign_b;
-- Perform operation based on the sign of the operands
case signs is
when "00" =>
-- pragma translate_off
if not is_x(as.a & as.b) then
-- pragma translate_on
result := as.a + as.b;
-- pragma translate_off
end if;
-- pragma translate_on
posn_in.sign <= '0';
neg_value := '0';
when "01" =>
-- pragma translate_off
if not is_x(as.a & as.b) then
-- pragma translate_on
result := as.a - as.b;
-- pragma translate_off
end if;
-- pragma translate_on
posn_in.sign <= result(56);
neg_value := result(56);
when "10" =>
-- pragma translate_off
if not is_x(as.a & as.b) then
-- pragma translate_on
result := as.a - as.b;
-- pragma translate_off
end if;
-- pragma translate_on
posn_in.sign <= not result(56);
neg_value := result(56);
when "11" =>
-- pragma translate_off
if not is_x(as.a & as.b) then
-- pragma translate_on
result := as.a + as.b;
-- pragma translate_off
end if;
-- pragma translate_on
posn_in.sign <= '1';
neg_value := '0';
when others => null;
end case;
-- If result is negative set fraction = -result else set fraction = result
-- pragma translate_off
if not is_x(all_zero & result) then
-- pragma translate_on
temp := all_zero - result;
-- pragma translate_off
end if;
-- pragma translate_on
if neg_value = '1' then
posn_in.frac <= temp(56 downto 0);
else
posn_in.frac <= result(56 downto 0);
end if;
-- Check if result is zero
if result = all_zero then
zero_fraction := '1';
posn_in.exp <= "00000000000";
else
zero_fraction := '0';
posn_in.exp <= as.exp;
end if;
-- Check if unordered operands i.e. any operand is some sort of NaN
unordered := as.op1_NaN or as.op2_NaN or as.op1_SNaN or as.op2_SNaN;
-- Check if result should be a SNaN.
SNaN := as.op1_SNaN or as.op2_SNaN or (unordered and as.gen_ex);
-- Check if result should be a NaN i.e. unordered opearands that don't
-- result in a SNaN or two inf values with different signs.
NaN := (unordered and (not SNaN)) or
(as.op1_inf and as.op2_inf and (signs(1) xor signs(0)));
-- Check if result should be inf.
inf := (as.op1_inf or as.op2_inf) and (not NaN) and (not SNaN);
-- Calculate condition codes.
cc_bit1 := ((not zero_fraction) and (not neg_value) and (not as.swaped)) or
unordered;
cc_bit0 := ((not zero_fraction) and
(as.swaped or (neg_value and (not as.swaped)))) or unordered;
-- Set condition codes if comp signal is 1.
if as.comp = '1' then
posn_in.cc <= cc_bit1 & cc_bit0;
else
posn_in.cc <= (others => '0');
end if;
-- Set exceptions
posn_in.exc <= SNaN & inf & "000";
-- Check if operation results in specal value
posn_in.res_SNaN <= SNaN;
posn_in.res_NaN <= NaN;
posn_in.res_inf <= inf;
posn_in.single <= as.single;
posn_in.res_zero <= zero_fraction;
posn_in.comp <= as.comp;
end process addsub_stage;
-------------------------------------------------------------------------------
-- Postnorm stage
-------------------------------------------------------------------------------
posnorm_stage: process (posn)
variable mask : std_logic_vector(55 downto 0);
variable leading_one : std_logic_vector(55 downto 0);
variable leading_zeros : std_logic_vector(55 downto 0);
variable shifts_needed : std_logic_vector(5 downto 0);
variable shift_amount : std_logic_vector(5 downto 0);
variable exp : std_logic_vector(10 downto 0);
variable frac : std_logic_vector(56 downto 0);
variable overflow : std_logic;
variable underflow : std_logic;
begin
-- If supernormal (overflow bit set) shift left by one step and inc exp
if ((posn.single = '1') and (posn.frac(27) = '1')) or
(posn.frac(56) = '1') then
frac := "0" & posn.frac(56 downto 1);
-- pragma translate_off
if not is_x(posn.exp) then
-- pragma translate_on
exp := posn.exp + 1;
-- pragma translate_off
end if;
-- pragma translate_on
underflow := '0';
else
-- Get number of leading zeros, if single precision is used don't count
-- leading 29 zeroes. (Overflow bit is not counted)
if posn.single = '1' then
lz_counter((posn.frac(26 downto 0) & "0" & zero(27 downto 0)),shifts_needed);
else
lz_counter(posn.frac(55 downto 0),shifts_needed);
end if;
-- If the shift amount needed is larger then the exponent then underflow
-- has occured, check that fraction is not zero.
-- pragma translate_off
if not is_x(shifts_needed & posn.exp) then
-- pragma translate_on
if (ieee.std_logic_unsigned.">"(shifts_needed, posn.exp)) and (posn.res_zero = '0') then
shift_amount := posn.exp(5 downto 0);
exp := (others => '0');
underflow := '1';
else
shift_amount := shifts_needed;
-- pragma translate_off
if not is_x( posn.exp & shift_amount) then
-- pragma translate_on
exp := posn.exp - shift_amount;
-- pragma translate_off
end if;
-- pragma translate_on
underflow := '0';
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- Perform left shift
left_shifter(posn.frac,shift_amount,frac);
end if;
-- Check if overflow has occured, also check that result is not any NaN
if (exp(7 downto 0) = "11111111") and
((posn.single = '1') or (exp(10 downto 8) = "111")) and
(posn.res_SNaN = '0') and (posn.res_NaN = '0') then
overflow := '1';
else
overflow := '0';
end if;
-- If operation is not some sort of compare set overflow/underflow
-- exceptions caused in this pipeline stage
if (posn.comp = '0') then
rnd_in.exc <= posn.exc(4) & overflow & underflow & posn.exc(1 downto 0);
else
rnd_in.exc <= posn.exc(4) & "00" & posn.exc(1 downto 0);
end if;
rnd_in.frac <= frac;
rnd_in.exp <= exp;
rnd_in.cc <= posn.cc;
rnd_in.res_NaN <= posn.res_NaN;
rnd_in.res_SNaN <= posn.res_SNaN;
rnd_in.res_inf <= posn.res_inf or overflow;
rnd_in.single <= posn.single;
rnd_in.comp <= posn.comp;
rnd_in.sign <= posn.sign;
end process posnorm_stage;
-------------------------------------------------------------------------------
-- Round and normalize stage
-------------------------------------------------------------------------------
roundnorm_stage: process (rnd, RoundingMode)
variable rounded_value : std_logic_vector(53 downto 0);
variable rounded_norm_value : std_logic_vector(52 downto 0);
variable exp_norm : std_logic_vector(10 downto 0);
variable exp : std_logic_vector(10 downto 0);
variable fraction : std_logic_vector(51 downto 0);
variable all_zero : std_logic_vector(51 downto 0);
variable overflow : std_logic;
variable inexact : std_logic;
variable NaNs : std_logic;
begin
all_zero := (others => '0');
-- Perform rounding according to selected rounding mode
case RoundingMode is
when "00" => if rnd.frac(2) = '1' and
rnd.frac(3 downto 0) /= "0000" then
-- pragma translate_off
if not is_x(rnd.frac(56 downto 3)) then
-- pragma translate_on
rounded_value := rnd.frac(56 downto 3) + 1;
-- pragma translate_off
end if;
-- pragma translate_on
else
rounded_value := rnd.frac(56 downto 3);
end if;
when "01" => rounded_value := rnd.frac(56 downto 3);
when "10" => if rnd.sign = '0' and rnd.frac(2) = '1' then
-- pragma translate_off
if not is_x(rnd.frac(56 downto 3)) then
-- pragma translate_on
rounded_value := rnd.frac(56 downto 3) + 1;
-- pragma translate_off
end if;
-- pragma translate_on
else
rounded_value := rnd.frac(56 downto 3);
end if;
when "11" => if rnd.sign = '1' and rnd.frac(2) = '1' then
-- pragma translate_off
if not is_x(rnd.frac(56 downto 3)) then
-- pragma translate_on
rounded_value := rnd.frac(56 downto 3) + 1;
-- pragma translate_off
end if;
-- pragma translate_on
else
rounded_value := rnd.frac(56 downto 3);
end if;
when others => null;
end case;
-- Normalize if needed i.e. if overflow bit set shift fraction one step
-- left and inc exp.
if (rnd.single = '1' and rounded_value(24) = '1') or
rounded_value(36) = '1' then
rounded_norm_value := rounded_value(53 downto 1);
-- pragma translate_off
if not is_x(rnd.exp) then
-- pragma translate_on
exp_norm := rnd.exp + 1;
-- pragma translate_off
end if;
-- pragma translate_on
else
rounded_norm_value := rounded_value(52 downto 0);
exp_norm := rnd.exp;
end if;
-- Check if overflow has occured
if (exp_norm(7 downto 0) = "11111111") and
((rnd.single = '1') or (exp_norm(10 downto 8) = "111")) and
(rnd.res_SNaN = '0') and (rnd.res_NaN = '0') then
overflow := '1';
else
overflow := '0';
end if;
-- Check if result is inexact
inexact := (rnd.frac(2) or rnd.frac(1) or rnd.frac(0)) and (not rnd.comp);
-- Check if result is some sort of NaN
NaNs := rnd.res_NaN or rnd.res_SNaN;
-- Set fraction and exponent.
if NaNs = '1' then
fraction := rnd.res_NaN & "1" & all_zero(49 downto 0);
exp := (others => '1');
elsif overflow = '1' or rnd.res_inf = '1' then
fraction := (others => '0');
exp := (others => '1');
else
fraction := rounded_norm_value(51 downto 0);
exp := exp_norm;
end if;
-- Set exception bits. If operaration is some sort of compare then
-- overflow, underflow and inexact interrupt can not occure.
if rnd.comp = '1' then
rnd_out.exc <= "0" & rnd.exc(4) & "0000";
else
rnd_out.exc <= "0" & rnd.exc(4) & (overflow or rnd.exc(3)) &
rnd.exc(2 downto 1) & inexact;
end if;
-- Put out result
if rnd.single = '1' then
rnd_out.frac <= fraction(22 downto 0) & "0" & zero(27 downto 0);
else
rnd_out.frac <= fraction;
end if;
rnd_out.exp <= exp;
rnd_out.sign <= rnd.sign;
rnd_out.cc <= rnd.cc;
end process roundnorm_stage;
-------------------------------------------------------------------------------
-- FPU busy signal generation process
-------------------------------------------------------------------------------
gen_busy: process (state, FpOp, FpLd)
begin
-- Default assignments
FpBusy <= '0';
next_state <= state;
result_ready <= '0';
-- Calculate nextstate and output
case state is
when start => if FpOp = '1' then
next_state <= get_operand;
end if;
when get_operand => FpBusy <= '1';
if FpLd = '1' then
next_state <= pre_norm;
end if;
when pre_norm => FpBusy <= '1';
next_state <= add_sub;
when add_sub => FpBusy <= '1';
next_state <= post_norm;
when post_norm => FpBusy <= '1';
next_state <= rnd_norm;
when rnd_norm => result_ready <= '1';
if FpOp = '1' then
next_state <= get_operand;
else
next_state <= hold_val;
end if;
when hold_val => if FpOp = '1' then
next_state <= get_operand;
end if;
when others => null;
end case;
end process gen_busy;
process (ss_clock, Reset)
begin
if Reset = '1' then
state <= start;
elsif ss_clock = '1' and ss_clock'event then
state <= next_state;
end if;
end process;
-------------------------------------------------------------------------------
-- Pipeline registers
-------------------------------------------------------------------------------
-- Gated ff holding opcode
de_gated : process (ss_clock, FpOp)
begin
if ss_clock = '1' and ss_clock'event then
if FpOp = '1' then
de <= de_in;
end if;
end if;
end process de_gated;
-- Gated ff holding unpacked operands and control signals
pren_gated : process (ss_clock, FpLd)
begin
if ss_clock = '1' and ss_clock'event then
if FpLd = '1' then
pren <= pren_in;
end if;
end if;
end process pren_gated;
-- Normal ff for the other pipeline stages
pipe_regs: process (ss_clock)
begin -- process pipe_regs
if ss_clock = '1' and ss_clock'event then
as <= as_in;
posn <= posn_in;
rnd <= rnd_in;
end if;
end process pipe_regs;
-- Gated ff with asynchronous reset holding the FPU output values
out_gated_reset: process (ss_clock, Reset, result_ready)
begin -- process out_gated_reset
if Reset = '1' then
FracResult <= (others => '0');
ExpResult <= (others => '0');
SignResult <= '0';
Excep <= (others => '0');
ConditionCodes <= (others => '0');
elsif ss_clock = '1' and ss_clock'event then
if result_ready = '1' then
FracResult <= rnd_out.frac;
ExpResult <= rnd_out.exp;
SignResult <= rnd_out.sign;
Excep <= rnd_out.exc;
ConditionCodes <= rnd_out.cc;
end if;
end if;
end process out_gated_reset;
end rtl;
| gpl-3.0 |
mirdej/sk611delay | vhdl/AD_DA.vhd | 1 | 2281 | ---------------------------------------------------------------------------------------------
-- VIDEO DELAY - AD, DA Converter
--
-- Part of the Synkie Project: www.synkie.net
--
-- © 2013 Michael Egger, Licensed under GNU GPLv3
--
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AD_DA is
port (
Clk : in std_logic;
ResetN : in std_logic;
Loopthru : in std_logic;
Data_from_AD : out std_logic_vector (7 downto 0);
Data_to_DA : in std_logic_vector (7 downto 0);
AD_Clk : out std_logic;
AD_Input : in std_logic_vector (7 downto 0);
DA_Clk : out std_logic;
DA_Out : out std_logic_vector (7 downto 0)
);
end entity;
--------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------
architecture AD_DA_Arch of AD_DA is
signal clk_int : std_logic;
signal ad_data, da_data : std_logic_vector (7 downto 0);
begin
--------------------------------------------------------generate slow ad and da clock
-- 156.250 Mhz / 12 = ca. 13 Mhz
process (Clk,ResetN)
variable clk_div : integer range 0 to 6 := 0;
begin
if (ResetN = '0') then
clk_int <= '0';
elsif (clk'EVENT and clk = '1') then
if (clk_div = 6) then
clk_div := 0;
clk_int <= not clk_int;
else
clk_div := clk_div + 1;
end if;
end if;
end process;
--------------------------------------------------------sample/latch AD Converter on falling AD Clock
process (clk_int)
begin
if (clk_int'EVENT and clk_int = '0') then
ad_data <= AD_Input;
end if;
end process;
--------------------------------------------------------prepare Data for DA_Converter on falling DA Clock
process (clk_int)
begin
if (clk_int'EVENT and clk_int = '1') then
DA_Out <= da_data;
end if;
end process;
AD_Clk <= clk_int;
DA_Clk <= not clk_int;
Data_from_AD <= ad_data;
-- da_data <= Data_to_DA;
with Loopthru select
da_data <= ad_data when '1', -- loop through
Data_to_DA when '0',
"11111111" when others;
end AD_DA_Arch; | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/VFLOAT_2015/General Modules/correction/parameterized_mux.vhd | 7 | 4181 | --======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized multiplexer --
----------------------------------------------------------
entity parameterized_mux is
generic
(
bits : integer := 0
);
port
(
--inputs
A : in std_logic_vector(bits-1 downto 0);
B : in std_logic_vector(bits-1 downto 0);
S : in std_logic;
--outputs
O : out std_logic_vector(bits-1 downto 0) := (others=>'0')
);
end parameterized_mux;
----------------------------------------------------------
-- Parameterized multiplexer --
----------------------------------------------------------
architecture parameterized_mux_arch of parameterized_mux is
begin
-- single_bits:for i in 0 to bits-1 generate
-- single_bit : mux2
-- port map
-- (
-- --inputs
-- A => A(i),
-- B => B(i),
-- S => S,
-- --outputs
-- O => O(i)
-- );
-- end generate; --i
O <= A when (S = '1') else B;
end parameterized_mux_arch; -- end of architecture
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon2-1.0.2a/leon/dcom.vhd | 1 | 6037 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: dcom
-- File: dcom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UART for debug support unit
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_arith.conv_unsigned;
use work.macro.all;
use work.amba.all;
use work.ambacomp.all;
use work.iface.all;
entity dcom is
port (
rst : in std_logic;
clk : in clk_type;
dcomi : in dcom_in_type;
dcomo : out dcom_out_type;
dsuo : in dsu_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture struct of dcom is
type dcom_state_type is (idle, addr1, read1, read2, write1, write2);
type reg_type is record
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
len : std_logic_vector(5 downto 0);
write : std_logic;
status : std_logic_vector(1 downto 0);
clen : std_logic_vector(1 downto 0);
state : dcom_state_type;
hresp : std_logic_vector(1 downto 0);
txresp : std_logic;
dmode : std_logic;
dsuact : std_logic;
end record;
signal r, rin : reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal uarti : dcom_uart_in_type;
signal uarto : dcom_uart_out_type;
begin
comb : process(dmao, rst, uarto, dcomi, ahbi, dsuo, r)
variable v : reg_type;
variable enable : std_logic;
variable newlen : std_logic_vector(5 downto 0);
variable vuarti : dcom_uart_in_type;
variable vdmai : ahb_dma_in_type;
variable newaddr : std_logic_vector(31 downto 2);
begin
v := r;
vuarti.rxd := dcomi.dsurx;
vuarti.read := '0'; vuarti.write := '0'; vuarti.data := r.data(31 downto 24);
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := "10";
vdmai.address := r.addr(31 downto 2) & "00"; vdmai.wdata := r.data;
vdmai.write := r.write; v.dsuact := dsuo.dsuact;
-- save hresp
if dmao.ready = '1' then v.hresp := ahbi.hresp; end if;
-- detect entering into debug mode
v.dmode := (r.dmode or (dsuo.dsuact and not r.dsuact)) and dsuo.dresp;
-- address incrementer
-- pragma translate_off
if not is_x(r.len) then
-- pragma translate_on
newlen := r.len - 1;
-- pragma translate_off
end if;
if not is_x(r.addr(31 downto 2)) then
-- pragma translate_on
newaddr := r.addr(31 downto 2) + 1;
-- pragma translate_off
end if;
-- pragma translate_on
case r.state is
when idle => -- idle state
v.clen := "00";
if uarto.dready = '1' then
if uarto.data(7) = '1' then v.state := addr1; end if;
v.write := uarto.data(6); v.len := uarto.data(5 downto 0);
vuarti.read := '1';
end if;
-- send response byte if debug mode was entered
if (r.dmode and dsuo.dresp) = '1' then
v.txresp := '1'; v.dmode := '0';
end if;
when addr1 => -- receive address
if uarto.dready = '1' then
v.addr := r.addr(23 downto 0) & uarto.data;
vuarti.read := '1'; v.clen := r.clen + 1;
end if;
if (r.clen(1) and not v.clen(1)) = '1' then
if r.write = '1' then v.state := write1; else v.state := read1; end if;
end if;
when read1 => -- read AHB
if dmao.active = '1' then
if dmao.ready = '1' then
v.data := dmao.rdata; v.state := read2;
end if;
elsif r.txresp = '0' then vdmai.start := '1'; end if;
v.clen := "00";
when read2 => -- send read-data on uart
if uarto.thempty = '1' then
v.data := r.data(23 downto 0) & uarto.data;
vuarti.write := '1'; v.clen := r.clen + 1;
if (r.clen(1) and not v.clen(1)) = '1' then
v.addr(31 downto 2) := newaddr; v.len := newlen;
if (v.len(5) and not r.len(5)) = '1' then v.state := idle;
else v.state := read1; end if;
if dsuo.lresp = '1' then v.txresp := '1'; end if;
end if;
end if;
when write1 => -- receive write-data
if uarto.dready = '1' then
v.data := r.data(23 downto 0) & uarto.data;
vuarti.read := '1'; v.clen := r.clen + 1;
end if;
if (r.clen(1) and not v.clen(1)) = '1' then v.state := write2; end if;
when write2 => -- write AHB
if dmao.active = '1' then
if dmao.ready = '1' then
v.addr(31 downto 2) := newaddr; v.len := newlen;
if (v.len(5) and not r.len(5)) = '1' then v.state := idle;
else v.state := write1; end if;
if dsuo.lresp = '1' then v.txresp := '1'; end if;
end if;
else vdmai.start := '1'; end if;
v.clen := "00";
end case;
-- send response byte
if r.txresp = '1' then
v.dmode := '0';
if (uarto.lock and uarto.enable and uarto.thempty) = '1' then
vuarti.data := "00000" & dsuo.dsuact & r.hresp; vuarti.write := '1';
v.txresp := '0';
end if;
end if;
vuarti.dsuen := dsuo.dsuen;
if (uarto.lock and rst) = '0' then
v.state := idle; v.write := '0'; v.dmode := '0'; v.txresp := '0';
end if;
rin <= v;
dmai <= vdmai;
uarti <= vuarti;
dcomo.dsutx <= uarto.txd;
end process;
ahbmst0 : ahbmst port map (rst, clk, dmai, dmao, ahbi, ahbo);
dcom_uart0 : dcom_uart port map (rst, clk, apbi, apbo, uarti, uarto);
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/mcoremdct.vhd | 1 | 10444 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mcore
-- File: mcore.vhd
-- Author: Jiri Gaisler - Gaisler Reserch
-- Description: Module containing the processor, caches, memory controller
-- and standard peripherals
------------------------------------------------------------------------------
-- 29.01.02 added signals for DDM
-- 13.03.02 mdct dummy core adddes LA
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
use work.ambacomp.all;
-- pragma translate_off
use work.debug.all;
-- pragma translate_on
entity mcore is
port (
resetn : in std_logic;
clk : in std_logic;
memi : in memory_in_type;
memo : out memory_out_type;
ioi : in io_in_type;
ioo : out io_out_type;
pcii : in pci_in_type;
pcio : out pci_out_type;
ddmi : in ddm_in_type; --LA
ddmo : out ddm_out_type; --LA
test : in std_logic
);
end;
architecture rtl of mcore is
component clkgen
port (
clk : in std_logic;
pciclk : in std_logic;
clki : in clkgen_in_type;
clko : out clkgen_out_type
);
end component;
component rstgen
port (
resetn : in std_logic;
pcirst : in std_logic;
clk : in clk_type;
rst : out rst_type
);
end component;
signal rst : rst_type;
signal clko : clkgen_out_type;
signal clki : clkgen_in_type;
signal iui : iu_in_type;
signal iuo : iu_out_type;
signal ahbsto: ahbstat_out_type;
signal mctrlo: mctrl_out_type;
signal wpo : wprot_out_type;
signal apbi : apb_slv_in_vector(0 to APB_SLV_MAX-1);
signal apbo : apb_slv_out_vector(0 to APB_SLV_MAX-1);
signal ahbmi : ahb_mst_in_vector(0 to AHB_MST_MAX-1);
signal ahbmo : ahb_mst_out_vector(0 to AHB_MST_MAX-1);
signal ahbsi : ahb_slv_in_vector(0 to AHB_SLV_MAX-1);
signal ahbso : ahb_slv_out_vector(0 to AHB_SLV_MAX-1);
signal pciresetn, pciirq : std_logic;
signal irqi : irq_in_type;
signal irqo : irq_out_type;
signal irq2i : irq2_in_type;
signal irq2o : irq2_out_type;
signal timo : timers_out_type;
signal pioo : pio_out_type;
signal uart1i, uart2i : uart_in_type;
signal uart1o, uart2o : uart_out_type;
signal ddmirq : std_logic; -- LA
signal mdctirq : std_logic; -- LA
begin
-- reset generator
reset0 : rstgen port map (resetn, pciresetn, clko.clk, rst);
-- clock generator
clkgen0 : clkgen port map (clk, pcii.pci_clk_in, clki, clko);
----------------------------------------------------------------------
-- AHB bus --
----------------------------------------------------------------------
-- AHB arbiter/decoder
ahb0 : ahbarb
generic map (masters => AHB_MASTERS, defmast => AHB_DEFMST)
port map (rst.syncrst, clko.clk, ahbmi(0 to AHB_MASTERS-1),
ahbmo(0 to AHB_MASTERS-1), ahbsi, ahbso);
-- AHB/APB bridge
apb0 : apbmst
port map (rst.syncrst, clko.clk, ahbsi(1), ahbso(1), apbi, apbo);
-- processor and cache sub-system
proc0 : proc port map (
rst.syncrst, clki, clko, apbi(2), apbo(2), ahbmi(0), ahbmo(0), iui, iuo);
-- memory controller
mctrl0 : mctrl port map (
rst => rst, clk=> clko.clk, memi => memi, memo => memo,
ahbsi => ahbsi(0), ahbso => ahbso(0), apbi => apbi(0), apbo => apbo(0),
pioo => pioo, wpo => wpo, mctrlo => mctrlo);
-- AHB write protection
wp0 : if WPROTEN generate
wpm : wprot port map (
rst => rst, clk => clko.clk, wpo => wpo, ahbsi => ahbsi(0),
apbi => apbi(3), apbo => apbo(3));
end generate;
wp1 : if not WPROTEN generate apbo(3).prdata <= (others => '0'); end generate;
-- AHB status register
as0 : if AHBSTATEN generate
asm : ahbstat port map (
rst => rst, clk => clko.clk, ahbmi => ahbmi(0), ahbsi => ahbsi(0),
apbi => apbi(1), apbo => apbo(1), ahbsto => ahbsto);
end generate;
as1 : if not AHBSTATEN generate
apbo(1).prdata <= (others => '0'); ahbsto.ahberr <= '0';
end generate;
-- AHB test module
ahbt : if PCICORE = ahbtst generate
a0 : ahbtest port map ( rst => rst.syncrst, clk => clko.clk,
ahbi => ahbsi(2), ahbo => ahbso(2)
);
pci0 : pci_is
port map (
rst_n => rst.syncrst, app_clk => clko.clk, pci_clk => clko.pciclk,
pbi => apbi(10), pbo => apbo(10), irq => pciirq,
TargetMasterOut => ahbmo(1), TargetMasterIn => ahbmi(1),
pci_in => pcii, pci_out => pcio,
InitSlaveOut => ahbso(3), InitSlaveIn => ahbsi(3),
InitMasterOut => ahbmo(2), InitMasterIn => ahbmi(2)
);
pciresetn <= '1';
end generate;
-- Optional InSilicon PCI core
pci_is0 : if PCICORE = insilicon generate
pci0 : pci_is
port map (
rst_n => rst.syncrst, app_clk => clko.clk, pci_clk => clko.pciclk,
pbi => apbi(10), pbo => apbo(10), irq => pciirq,
TargetMasterOut => ahbmo(1), TargetMasterIn => ahbmi(1),
pci_in => pcii, pci_out => pcio,
InitSlaveOut => ahbso(2), InitSlaveIn => ahbsi(2),
InitMasterOut => ahbmo(2), InitMasterIn => ahbmi(2)
);
pciresetn <= pcii.pci_rst_in_n;
end generate;
-- Optional ESA PCI core
pci_esa0 : if PCICORE = esa generate
pci0 : pci_esa
port map (
resetn => rst.syncrst, app_clk => clko.clk,
pci_in => pcii, pci_out => pcio,
ahbmasterin => ahbmi(1), ahbmasterout => ahbmo(1),
ahbslavein => ahbsi(2), ahbslaveout => ahbso(2),
apbslavein => apbi(10), apbslaveout => apbo(10), irq => pciirq
);
pciresetn <= pcii.pci_rst_in_n;
end generate;
pr0 : if not PCIEN generate pciirq <= '0'; pciresetn <= '0'; end generate;
-- drive unused part of the AHB bus to stop some stupid synthesis tools
-- from inserting tri-state buffers (!)
ahbdrv : for i in 0 to AHB_SLV_MAX-1 generate
u0 : if not AHB_SLVTABLE(i).enable generate
ahbso(i).hready <= '-'; ahbso(i).hresp <= "--";
ahbso(i).hrdata <= (others => '-');
ahbso(i).hsplit <= (others => '-');
end generate;
end generate;
----------------------------------------------------------------------
-- APB bus --
----------------------------------------------------------------------
pci_arb0 : if PCIARBEN generate
pciarb : pci_arb
port map (
clk => pcii.pci_clk_in, rst_n => rst.syncrst,
req_n => ioi.pci_arb_req_n, frame_n => pcii.pci_frame_in_n,
gnt_n => ioo.pci_arb_gnt_n, pclk => clko.clk,
prst_n => pcii.pci_rst_in_n, pbi => apbi(11), pbo => apbo(11)
);
end generate;
-- LEON configuration register
lc0 : if CFGREG generate
lcm : lconf port map (rst => rst, apbo => apbo(4));
end generate;
-- timers (and watchdog)
timers0 : timers
port map (rst => rst.syncrst, clk => clko.clk, apbi => apbi(5),
apbo => apbo(5), timo => timo);
-- UARTS
-- This stupidity exists because synopsys DC is not capable of
-- handling record elements in port maps. Sad really ...
uart1i.rxd <= pioo.rxd(0); uart1i.ctsn <= pioo.ctsn(0);
uart2i.rxd <= pioo.rxd(1); uart2i.ctsn <= pioo.ctsn(1);
uart1i.scaler <= pioo.io8lsb; uart2i.scaler <= pioo.io8lsb;
uart1 : uart port map (
rst => rst.syncrst, clk => clko.clk, apbi => apbi(6), apbo => apbo(6),
uarti => uart1i, uarto => uart1o);
uart2 : uart port map (
rst => rst.syncrst, clk => clko.clk, apbi => apbi(7), apbo => apbo(7),
uarti => uart2i, uarto => uart2o);
-- interrupt controller
irqctrl0 : irqctrl
port map (rst => rst.syncrst, clk => clko.clk, apbi => apbi(8),
apbo => apbo(8), irqi => irqi, irqo => irqo);
irqi.intack <= iuo.intack; irqi.irl <= iuo.irqvec; iui.irl <= irqo.irl;
-- optional secondary interrupt controller
i2 : if IRQ2EN generate
irqctrl1 : irqctrl2
port map (rst => rst.syncrst, clk => clko.clk, apbi => apbi(10),
apbo => apbo(10), irqi => irq2i, irqo => irq2o);
end generate;
-- parallel I/O port
ioport0 : ioport
port map (rst => rst, clk => clko.clk, apbi => apbi(9), apbo => apbo(9),
uart1o => uart1o, uart2o => uart2o, mctrlo => mctrlo,
ioi => ioi, pioo => pioo);
-- ddm
ddm0 : ddm
port map (rst => rst.syncrst, clk => clk, apbi => apbi(11), apbo => apbo(11),
ahbi => ahbmi(1), ahbo => ahbmo(1), ddmo => ddmo, ddmi => ddmi,
irq => ddmirq ); -- LA
-- mdct
mdct0 : mdct
port map (rst => rst.syncrst, clk => clk, apbi => apbi(12), apbo => apbo(12),
ahbi => ahbmi(2), ahbo => ahbmo(2),irq => mdctirq ); -- LA
-- drive unused part of the APB bus to stop some stupid synthesis tools
-- from inserting tri-state buffers (!)
apbdrv : for i in 0 to APB_SLV_MAX-1 generate
u0 : if not APB_TABLE(i).enable generate
apbo(i).prdata <= (others => '-');
end generate;
end generate;
-- IRQ assignments, add you mapping below
irqi.irq(15) <= '0'; -- unmaskable irq
irqi.irq(14) <= pciirq;
irqi.irq(13) <= ddmirq; -- LA
irqi.irq(12) <= mdctirq; -- LA
irqi.irq(11 downto 10) <= (others => '0'); -- unassigned irqs
-- irqi.irq(10) <= irq2o.irq when IRQ2EN else '0';
irqi.irq(9) <= timo.irq(1); -- timer 2
irqi.irq(8) <= timo.irq(0); -- timer 1
irqi.irq(7 downto 4) <= pioo.irq; -- I/O port interrupts
irqi.irq(3) <= uart1o.irq; -- UART 1
irqi.irq(2) <= uart2o.irq; -- UART 2
irqi.irq(1) <= ahbsto.ahberr; -- AHB error
-- additional 32 interrupts for secondary interrupt controller
irq2i.irq <= (others => '0');
-- drive outputs
ioo.piol <= pioo.piol(15 downto 0);
ioo.piodir <= pioo.piodir(15 downto 0);
ioo.wdog <= timo.wdog;
ioo.errorn <= iuo.error;
-- disassambler
-- pragma translate_off
trace0 : trace(iuo.debug, (test = '1'));
-- pragma translate_on
end ;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/mdctlib.vhd | 1 | 9493 | LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
use work.amba.all;
use work.mdctrom256.all;
package mdctlib is
constant TRIGBITS: integer := 14;
--constant rom_lenght: integer:=14;
constant cPI3_8 :std_logic_vector (31 downto 0) := "00000000000000000001100001111110";
constant cPI2_8 :std_logic_vector (31 downto 0) := "00000000000000000010110101000001";
constant cPI1_8 :std_logic_vector (31 downto 0) := "00000000000000000011101100100001";
constant zero32 : std_logic_vector (31 downto 0):= "00000000000000000000000000000000";
type btf8_data is array(0 to 7) of std_logic_vector (31 downto 0);
type btf16_data is array(0 to 1) of btf8_data;
type btf32_data is array(0 to 1) of btf16_data;
type block4_data is array(0 to 3) of std_logic_vector (31 downto 0);
type block8_data is array(0 to 7) of std_logic_vector (31 downto 0);
type block16_data is array(0 to 15) of std_logic_vector (31 downto 0);
type block32_data is array(0 to 31) of std_logic_vector (31 downto 0);
--type rom_table is array (0 to rom_lenght-1) of std_logic_vector (31 downto 0);
type in_multadd is record
op1_m1: std_logic_vector (31 downto 0);
op2_m1: std_logic_vector (31 downto 0);
op1_m2: std_logic_vector (31 downto 0);
op2_m2: std_logic_vector (31 downto 0);
add_fun: std_logic;
end record;
type out_multadd is record
r_m1: std_logic_vector (31 downto 0);
r_m2: std_logic_vector (31 downto 0);
r_mult: std_logic_vector (31 downto 0);
end record;
type in_addbank is record
op1_a1 : std_logic_vector(31 downto 0);
op2_a1 : std_logic_vector(31 downto 0);
op1_a2 : std_logic_vector(31 downto 0);
op2_a2 : std_logic_vector(31 downto 0);
op1_a3 : std_logic_vector(31 downto 0);
op2_a3 : std_logic_vector(31 downto 0);
op1_s1 : std_logic_vector(31 downto 0);
op2_s1 : std_logic_vector(31 downto 0);
op1_s2 : std_logic_vector(31 downto 0);
op2_s2 : std_logic_vector(31 downto 0);
op1_s3 : std_logic_vector(31 downto 0);
op2_s3 : std_logic_vector(31 downto 0);
end record;
type out_addbank is record
r_a1: std_logic_vector(31 downto 0);
r_a2: std_logic_vector(31 downto 0);
r_a3: std_logic_vector(31 downto 0);
r_s1: std_logic_vector(31 downto 0);
r_s2: std_logic_vector(31 downto 0);
r_s3: std_logic_vector(31 downto 0);
end record;
type ctrlregs is record
-- registers and signals used to communicate mdctctrl with amba wrapper
ntoprocess : std_logic_vector(5 downto 0); -- number of resting elements to be processed
memwr : std_logic; -- '1' for write, '0' for read
startadr: std_logic_vector(31 downto 0); -- start address of current block
incr : std_logic; -- Bytes increment for blocks ('0'=>4 '1'=>8)
pos : std_logic_vector(1 downto 0);
-- Pointer to read/store from buffer
-- (00,01,10,11)=>(0,4,8,12)
finish : std_logic; -- '1' if whole mdct is finished
end record;
type mdctregs is record
-- ***********************
-- memory mapped registers
-- Control register
-- bit 0 of 0x80000300
mdctenreq : std_logic; -- mdct function enabled
-- bit 1 of 0x80000300
irqen : std_logic; -- enable interrupt
-- bit 2 of 0x80000300
irq : std_logic; -- irq request
-- 10 bit at 0x80000304
size : std_logic; -- number of points of mdct '0'=>256 '1'=>2048
-- 32 bit at 0x80000308
rdstartaddr : std_logic_vector(31 downto 0); -- read dma transfer start address
-- 32 bit at 0x800030c
wrstartaddr : std_logic_vector(31 downto 0); -- write dma transfer start address
-- Status register
-- bit 0 of 0x80000310
ready : std_logic; -- '1' if function done, '0' if busy / read only
-- bit 1 of 0x80000310
memwr : std_logic; -- '1' if writting, '0' if reading data from memory /read only
-- 32 bit at 0x80000314
memoryadr : std_logic_vector(31 downto 0); -- actual dma address /read only
-- memory mapped registers end
-- ***************************
-- internal registers
mdcten : std_logic;
dmatransfreq : std_logic;
ntoprocess : std_logic_vector(5 downto 0); -- number of resting elements to be processed
inputdata : block32_data; -- original data from memory
result : block32_data; -- result after mdct to store in memory
-- amba status registers
busact : std_logic;
busown : std_logic;
busgrant : std_logic;
busown2cyc : std_logic;
end record;
component mdct
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
irq : out std_logic
);
end component;
component butterfly_8
port (
rst : in std_logic;
clk : in std_logic;
datain : in btf8_data;
dataout : out btf8_data;
enabled : in std_logic
);
end component;
component butterfly_16
port (
rst : in std_logic;
clk : in std_logic;
datain : in btf16_data;
dataout : out btf16_data;
enabled : in std_logic
);
end component;
component butterfly_32
port (
rst : in std_logic;
clk : in std_logic;
datain : in btf32_data;
dataout : out btf32_data;
enabled : in std_logic;
ready : out std_logic
);
end component;
function MULT_NORM(w :std_logic_vector (63 downto 0))
return std_logic_vector;
function HALVE(w :std_logic_vector (31 downto 0))
return std_logic_vector;
function BT32_to_BLOCK32(bt: btf32_data )
return block32_data;
function BLOCK32_to_BT32(b: block32_data )
return btf32_data;
function BLOCK8_to_BLOCK16(b1: block8_data; b2: block8_data)
return block16_data;
function BLOCK16_to_BLOCK8(b: block16_data; x: integer range 0 to 1)
return block8_data;
function BLOCK32_to_BLOCK4(b: block32_data)
return block4_data;
function BLOCK4_to_BLOCK32(b: block4_data)
return block32_data;
function ROM_to_BLOCK4(t: rom_table; start:integer)
return block4_data;end;
package body mdctlib is
function MULT_NORM(w :std_logic_vector (63 downto 0))
return std_logic_vector is
variable result: std_logic_vector (31 downto 0);
variable rshift: bit_vector (63 downto 0);
begin
rshift := TO_BITVECTOR (w); -- convert to bitvector in order to prepare shift
rshift := rshift sra TRIGBITS; -- shift arithmetic right
result := TO_STDLOGICVECTOR(rshift(31 downto 0));-- convert to std_logic_vector again
return result;
end MULT_NORM;
function HALVE(w :std_logic_vector (31 downto 0))
return std_logic_vector is
variable result: std_logic_vector (31 downto 0);
variable rshift: bit_vector (31 downto 0);
begin
rshift := TO_BITVECTOR (w); -- convert to bitvector in order to prepare shift
rshift := rshift sra 1; -- shift arithmetic right
result := TO_STDLOGICVECTOR(rshift);-- convert to std_logic_vector again
return result;
end HALVE;
function BT32_to_BLOCK32(bt: btf32_data )
return block32_data is
variable result: block32_data;
begin
for i in 0 to 1 loop
for j in 0 to 1 loop
for k in 0 to 7 loop
result (8*i + 8*(j+i) + k) := bt (i)(j)(k);
end loop;
end loop;
end loop;
return result;
end BT32_to_BLOCK32;
function BLOCK32_to_BT32(b: block32_data )
return btf32_data is
variable result: btf32_data;
begin
for i in 0 to 1 loop
for j in 0 to 1 loop
for k in 0 to 7 loop
result (i)(j)(k) := b (8*i + 8*(j+i) + k) ;
end loop;
end loop;
end loop;
return result;
end BLOCK32_to_BT32;
function BLOCK8_to_BLOCK16(b1: block8_data; b2: block8_data)
return block16_data is
variable result: block16_data;
begin
for i in 0 to 7 loop
result(i) := b1(i);
end loop;
for i in 8 to 15 loop
result(i) := b2(i-8);
end loop;
return result;
end BLOCK8_to_BLOCK16;
function BLOCK16_to_BLOCK8(b: block16_data; x: integer range 0 to 1)
return block8_data is
variable result: block8_data;
begin
for i in 0 to 7 loop
result(i) := b(i + x*8);
end loop;
return result;
end BLOCK16_to_BLOCK8;
function BLOCK32_to_BLOCK4(b: block32_data)
return block4_data is
variable result: block4_data;
begin
for i in 0 to 3 loop
result(i) := b(i);
end loop;
return result;
end BLOCK32_to_BLOCK4;
function BLOCK4_to_BLOCK32(b: block4_data)
return block32_data is
variable result: block32_data;
begin
for i in 0 to 3 loop
result(i) := b(i);
end loop;
return result;
end BLOCK4_to_BLOCK32;
function ROM_to_BLOCK4(t: rom_table; start:integer)
return block4_data is
variable result: block4_data;
begin
for i in 0 to 3 loop
result(i) := t(i+start);
end loop;
return result;
end ROM_to_BLOCK4;
end; -- end mdct lib
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon2-1.0.2a/leon/dcache.vhd | 1 | 22716 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: dcache
-- File: dcache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned.conv_integer;
use work.amba.all;
use work.target.all;
use work.config.all;
use work.sparcv8.all; -- ASI declarations
use work.iface.all;
use work.macro.all; -- xorv()
entity dcache is
port (
rst : in std_logic;
clk : in clk_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_logic
);
end;
architecture rtl of dcache is
constant TAG_HIGH : integer := DTAG_HIGH;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH: integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LINE_ZERO : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');
type rdatatype is (dtag, ddata, icache, memory); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_logic;
lock : std_logic;
end record;
type dcache_control_type is record -- all registers
read : std_logic; -- access direction
signed : std_logic; -- signed/unsigned read
size : std_logic_vector(1 downto 0); -- access size
req, burst, holdn, nomds, stpend : std_logic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
valid : std_logic_vector(DLINE_SIZE - 1 downto 0); -- registered valid bits
dstate : std_logic_vector(2 downto 0); -- FSM vector
hit : std_logic;
flush : std_logic; -- flush in progress
mexc : std_logic; -- latched mexc
wb : write_buffer_type; -- write buffer
asi : std_logic_vector(3 downto 0);
icenable : std_logic; -- icache diag access
end record;
type snoop_reg_type is record -- snoop control registers
snoop : std_logic; -- snoop access to tags
writebp : std_logic; -- snoop write bypass
addr : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag
end record;
type snoop_hit_reg_type is record
hit : std_logic_vector(2**DOFFSET_BITS-1 downto 0);-- snoop hit bits
taddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);-- saved tag address
end record;
signal r, c : dcache_control_type; -- r is registers, c is combinational
signal rs, cs : snoop_reg_type; -- rs is registers, cs is combinational
signal rh, ch : snoop_hit_reg_type; -- rs is registers, cs is combinational
begin
dctrl : process(rst, r, rs, rh, dci, mcdo, ico, dcramo, ahbsi, fpuholdn)
variable dcramov : dcram_out_type;
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_logic;
variable twrite, tdiagwrite, ddiagwrite, dwrite : std_logic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : std_logic_vector(31 downto 0);
variable wdata : std_logic_vector(31 downto 0);
variable vmaskraw, vmask : std_logic_vector((DLINE_SIZE -1) downto 0);
variable vmaskdbl : std_logic_vector((DLINE_SIZE/2 -1) downto 0);
variable enable : std_logic;
variable mds : std_logic;
variable mexc : std_logic;
variable hit, valid, validraw, forcemiss : std_logic;
variable signed : std_logic;
variable flush : std_logic;
variable iflush : std_logic;
variable v : dcache_control_type;
variable eholdn : std_logic; -- external hold
variable tparerr : std_logic;
variable dparerr : std_logic;
variable snoopwe : std_logic;
variable hcache : std_logic;
variable snoopaddr: std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable vs : snoop_reg_type;
variable vh : snoop_hit_reg_type;
variable dsudata : std_logic_vector(31 downto 0);
begin
-- init local variables
v := r; vs := rs; vh := rh; dcramov := dcramo;
mds := '1'; dwrite := '0'; twrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn;
tparerr := '0'; dparerr := '0';
vs.snoop := '0'; vs.writebp := '0'; snoopwe := '0';
snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);
hcache := '0';
enable := '1';
rdatasel := ddata; -- read data from cache as default
-- AHB snoop handling
if DSNOOP then
-- snoop only in cacheable areas
for i in PROC_CACHETABLE'range loop --'
if (ahbsi.haddr(31 downto 32-PROC_CACHE_ADDR_MSB) >= PROC_CACHETABLE(i).firstaddr) and
(ahbsi.haddr(31 downto 32-PROC_CACHE_ADDR_MSB) <= PROC_CACHETABLE(i).lastaddr)
then hcache := '1'; end if;
end loop;
-- save snoop tag
vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);
-- snoop on NONSEQ or SEQ and first word in cache line
-- do not snoop during own transfers or during cache flush
if (ahbsi.hready and ahbsi.hwrite and not mcdo.bg) = '1' and
((ahbsi.htrans = HTRANS_NONSEQ) or
((ahbsi.htrans = HTRANS_SEQ) and
(ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))
then
vs.snoop := mcdo.dsnoop and hcache;
end if;
-- clear valid bits on snoop hit (or set hit bits)
if ((rs.snoop and (not mcdo.ba) and not r.flush) = '1')
and (dcramov.dtramoutsn.tag = rs.addr(TAG_HIGH downto TAG_LOW))
then
if DSNOOP_FAST then
-- pragma translate_off
if not is_x(rs.addr(OFFSET_HIGH downto OFFSET_LOW)) then
-- pragma translate_on
vh.hit(conv_integer(rs.addr(OFFSET_HIGH downto OFFSET_LOW))) := '1';
-- pragma translate_off
end if;
-- pragma translate_on
else
snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW); snoopwe := '1';
end if;
end if;
-- bypass tag data on read/write contention
if (not DSNOOP_FAST) and (rs.writebp = '1') then
dcramov.dtramout.tag := (others => '0');
dcramov.dtramout.valid := (others => '0');
end if;
end if;
-- generate access parameters during pipeline stall
if ((r.holdn) = '0') or (DEBUG_UNIT and (dci.dsuen = '1')) then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0); signed := r.signed;
read := r.read; size := r.size; edata := dci.maddress;
else
maddress := dci.maddress(31 downto 0); signed := dci.signed;
read := dci.read; size := dci.size; edata := dci.edata;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
-- generate cache hit and valid bits
forcemiss := not dci.asi(3);
if (dcramov.dtramout.tag = dci.maddress(TAG_HIGH downto TAG_LOW)) then
hit := (not r.flush) and not tparerr;
else
hit := '0';
end if;
-- force miss on snoop hit
if DSNOOP and DSNOOP_FAST then
-- pragma translate_off
if not is_x(rh.taddr) then
-- pragma translate_on
hit := hit and not rh.hit(conv_integer(rh.taddr));
-- pragma translate_off
end if;
-- pragma translate_on
end if;
validraw := genmux(dci.maddress(LINE_HIGH downto LINE_LOW),
dcramov.dtramout.valid);
valid := validraw and not dparerr;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = "000") then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(3 downto 0);
v.signed := dci.signed;
end if;
-- Store buffer
wdata := r.wb.data1;
if mcdo.ready = '1' then
v.wb.addr(2) := r.wb.addr(2) or (r.wb.size(0) and r.wb.size(1));
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
-- main Dcache state machine
case r.dstate is
when "000" => -- Idle state
v.nomds := r.nomds and not eholdn; v.valid := dcramov.dtramout.valid;
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock;
v.wb.asi := dci.asi(3 downto 0);
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
if dci.asi(3 downto 0) = ASI_DTAG then rdatasel := dtag; end if;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(3 downto 0) is
when ASI_ITAG | ASI_IDATA => -- Read/write Icache tags
if ico.flush = '1' then mexc := '1';
else v.dstate := "101"; v.holdn := '0'; end if;
when ASI_IFLUSH => -- flush instruction cache
if dci.read = '0' then iflush := '1'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when others =>
if dci.read = '1' then -- read access
if (not ((mcdo.dcs(0) = '1')
and ((hit and valid and not forcemiss) = '1')))
then -- read miss
v.holdn := '0'; v.dstate := "001";
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1'))
then -- wait for store queue
v.req := '1';
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
end if;
end if;
else -- write access
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := "100"; end if; -- double store
else -- wait for store queue
v.dstate := "110"; v.holdn := '0';
end if;
if (mcdo.dcs(0) = '1') and ((hit and (dci.size(1) or validraw)) = '1')
then -- write hit
twrite := '1'; dwrite := '1';
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
end case;
end if;
when "001" => -- read miss, wait for memory data
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
if r.stpend = '0' then
if mcdo.ready = '1' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
if (mcdo.dcs = "01") then
v.hit := mcdo.cache and r.hit; twrite := v.hit;
elsif (mcdo.dcs(1) = '1') then
v.hit := mcdo.cache and (r.hit or not r.asi(2)); twrite := v.hit;
end if;
dwrite := twrite; rdatasel := memory;
mexc := mcdo.mexc;
if r.req = '0' then
if (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (mcdo.dcs(0) = '1') then
v.dstate := "011"; v.holdn := '0';
else v.dstate := "000"; end if;
else v.nomds := '1'; end if;
end if;
v.mexc := mcdo.mexc; v.wb.data2 := mcdo.data;
else
if ((mcdo.ready and not r.req) = '1') then -- wait for store queue
v.burst := r.size(1) and r.size(0) and not r.xaddress(2);
v.wb.addr := r.xaddress; v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi;
end if;
end if;
when "011" => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
v.dstate := "000";
when "100" => -- second part of double store cycle
v.dstate := "000"; v.wb.data2 := dci.edata;
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (mcdo.dcs(0) = '1') and (r.hit = '1') then dwrite := '1'; end if;
when "101" => -- icache diag access
rdatasel := icache; v.icenable := '1'; v.holdn := '0';
if ico.diagrdy = '1' then
v.dstate := "011"; v.icenable := '0'; mds := not r.read;
end if;
when "110" => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if ((mcdo.ready and not r.req) = '1') then -- store queue emptied
if (mcdo.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := '1';
end if;
v.dstate := "000";
v.req := '1'; v.burst := r.size(1) and r.size(0); v.stpend := '1';
v.wb.addr := r.xaddress; v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi;
if r.size = "11" then v.wb.addr(2) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when others => v.dstate := "000";
end case;
dsudata := (others => '0');
if DEBUG_UNIT and dci.dsuen = '1' then
case dci.asi(3 downto 0) is
when ASI_ITAG | ASI_IDATA => -- Read/write Icache tags
v.icenable := not ico.diagrdy;
dsudata := ico.diagdata;
when ASI_DTAG =>
if dci.write = '1' then
twrite := not dci.eenaddr; tdiagwrite := '1';
end if;
dsudata(TAG_HIGH downto TAG_LOW) := dcramov.dtramout.tag;
dsudata(DLINE_SIZE -1 downto 0) := dcramov.dtramout.valid;
when ASI_DDATA =>
if dci.write = '1' then dwrite := '1'; ddiagwrite := '1'; end if;
dsudata := dcramov.ddramout.data;
when others =>
end case;
end if;
-- select data to return on read access
-- align if byte/half word read from cache or memory.
rdata := (others => '0');
align_data := (others => '0');
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when dtag =>
rdata(TAG_HIGH downto TAG_LOW) := dcramov.dtramout.tag;
rdata(DLINE_SIZE -1 downto 0) := dcramov.dtramout.valid;
when icache => rdata := ico.diagdata;
when ddata | memory =>
if rdatasel = ddata then align_data := dcramov.ddramout.data;
else align_data := mcdo.data; end if;
case size is
when "00" => -- byte read
case maddrlow is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if maddress(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
end case;
-- select which data to update the data cache with
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatain := edata(7 downto 0) & dcramov.ddramout.data(23 downto 0);
when "01" =>
ddatain := dcramov.ddramout.data(31 downto 24) & edata(7 downto 0) &
dcramov.ddramout.data(15 downto 0);
when "10" =>
ddatain := dcramov.ddramout.data(31 downto 16) & edata(7 downto 0) &
dcramov.ddramout.data(7 downto 0);
when others =>
ddatain := dcramov.ddramout.data(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatain := edata(15 downto 0) & dcramov.ddramout.data(15 downto 0);
else
ddatain := dcramov.ddramout.data(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatain := edata;
end case;
-- handle double load with pipeline hold
if (r.dstate = "000") and (r.nomds = '1') then
rdata := r.wb.data2; mexc := r.mexc;
end if;
-- Handle AHB retry. Re-generate bus request and burst
if mcdo.retry = '1' then
v.req := '1';
v.burst := r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2);
end if;
-- Generate new valid bits
vmaskdbl := decode(maddress(LINE_HIGH downto LINE_LOW+1));
if (size = "11") and (read = '0') then
for i in 0 to (DLINE_SIZE - 1) loop vmaskraw(i) := vmaskdbl(i/2); end loop;
else
vmaskraw := decode(maddress(LINE_HIGH downto LINE_LOW));
end if;
vmask := vmaskraw;
if r.hit = '1' then vmask := r.valid or vmaskraw; end if;
if r.dstate = "000" then
vmask := dcramov.dtramout.valid or vmaskraw;
end if;
if (mcdo.mexc or r.flush) = '1' then twrite := '0'; dwrite := '0'; end if;
if twrite = '1' then v.valid := vmask; end if;
if tdiagwrite = '1' then -- diagnostic tag write
if DEBUG_UNIT and (dci.dsuen = '1') then
vmask := dci.maddress(DLINE_SIZE - 1 downto 0);
else
vmask := dci.edata(DLINE_SIZE - 1 downto 0);
end if;
end if;
-- cache flush
if (dci.flush or flush or mcdo.dflush) = '1' then
v.flush := '1'; v.faddr := (others => '0');
end if;
if r.flush = '1' then
twrite := '1'; vmask := (others => '0'); v.faddr := r.faddr +1;
newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
if (r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) = '1' then
v.flush := '0';
end if;
end if;
-- AHB snoop handling (2), bypass write data on read/write contention
if DSNOOP then
if DSNOOP_FAST then
vh.taddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
if twrite = '1' then
-- pragma translate_off
if not is_x(taddr(OFFSET_HIGH downto OFFSET_LOW)) then
-- pragma translate_on
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW))) := '0';
-- pragma translate_off
end if;
-- pragma translate_on
end if;
else
if rs.addr(OFFSET_HIGH downto OFFSET_LOW) =
r.xaddress(OFFSET_HIGH downto OFFSET_LOW)
then
if twrite = '0' then
if snoopwe = '1' then vs.writebp := '1'; end if;
else
if snoopwe = '1' then twrite := '0'; end if; -- avoid write/write contention
end if;
end if;
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then ddatain := mcdo.data; end if;
-- reset
if rst = '0' then
v.dstate := "000"; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0';
end if;
-- Drive signals
c <= v; cs <= vs; ch <= vh; -- register inputs
-- tag ram inputs
dcrami.dtramin.valid <= vmask;
dcrami.dtramin.tag <= newtag(TAG_HIGH downto TAG_LOW);
dcrami.dtramin.enable <= enable;
dcrami.dtramin.write <= twrite;
dcrami.dtraminsn.enable <= vs.snoop or snoopwe;
dcrami.dtraminsn.write <= snoopwe;
dcrami.dtraminsn.address<= snoopaddr;
-- data ram inputs
dcrami.ddramin.enable <= enable;
dcrami.ddramin.address <= taddr;
dcrami.ddramin.data <= ddatain;
dcrami.ddramin.write <= dwrite;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.asi <= r.wb.asi;
mcdi.lock <= r.wb.lock or dci.lock;
mcdi.req <= r.req;
mcdi.flush <= r.flush;
-- diagnostic instruction cache access
dco.icdiag.flush <= iflush or mcdo.iflush;
dco.icdiag.read <= read;
dco.icdiag.tag <= not r.asi(0);
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
dco.dsudata <= dsudata; -- debug unit
-- IU data cache inputs
dco.data <= rdata;
dco.mexc <= mexc;
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
end process;
-- Local registers
reg1 : process(clk)
begin if rising_edge(clk) then r <= c; end if; end process;
sn2 : if DSNOOP generate
reg2 : process(clk)
begin if rising_edge(clk) then rs <= cs; end if; end process;
end generate;
sn3 : if DSNOOP_FAST generate
reg3 : process(clk)
begin if rising_edge(clk) then rh <= ch; end if; end process;
end generate;
end ;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon2-1.0.2a/leon/proc.vhd | 1 | 5944 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: proc
-- File: proc.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: This unit contains the integer unit, cache memory,
-- clock/reset generation and (optinally) FPU.
------------------------------------------------------------------------------
-- Version control:
-- 11-9-1998: First implemetation
-- 26-9-1999: Release 1.0
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
use work.fpulib.all;
use work.tech_map.all;
entity proc is
port (
rst : in std_logic;
clki : out clkgen_in_type;
clko : in clkgen_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
iui : in iu_in_type;
iuo : out iu_out_type
);
end;
architecture rtl of proc is
component iu
port (
rst : std_logic;
rclk : in clk_type;
rclkn : in clk_type;
clk : in clk_type;
iclk : in clk_type;
dclk : in clk_type;
holdn : in std_logic;
ici : out icache_in_type; -- icache input
ico : in icache_out_type; -- icache output
dci : out dcache_in_type; -- dcache input
dco : in dcache_out_type; -- dcache output
fpui : out fpu_in_type; -- FPU input
fpuo : in fpu_out_type; -- FPU output
iui : in iu_in_type; -- system input
iuo : out iu_out_type; -- system output
rfi : out rf_in_type; -- register-file input
rfo : in rf_out_type; -- register-file output
cpi : out cp_in_type; -- CP input
cpo : in cp_out_type; -- CP output
fpi : out cp_in_type; -- FP input
fpo : in cp_out_type -- FP output
);
end component;
component cache
port (
rst : in std_logic;
clk : in clk_type;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
iuo : in iu_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_logic
);
end component;
component cp
port (
rst : in std_logic; -- Reset
clk : in clk_type; -- main clock
iuclk : in clk_type; -- gated IU clock
holdn : in std_logic; -- pipeline hold
cpi : in cp_in_type;
cpo : out cp_out_type
);
end component;
component fp
port (
rst : in std_logic; -- Reset
clk : in clk_type; -- main clock
iuclk : in clk_type; -- gated IU clock
holdn : in std_logic; -- pipeline hold
xholdn : in std_logic; -- pipeline hold
cpi : in cp_in_type;
cpo : out cp_out_type
);
end component;
component fp1eu
port (
rst : in std_logic; -- Reset
clk : in clkgen_out_type;
xholdn : in std_logic; -- Reset
cpi : in cp_in_type;
cpo : out cp_out_type
);
end component;
component cachemem
port (
clk : in clk_type;
crami : in cram_in_type;
cramo : out cram_out_type
);
end component;
signal ici : icache_in_type;
signal ico : icache_out_type;
signal dci : dcache_in_type;
signal dco : dcache_out_type;
signal fpui : fpu_in_type;
signal fpuo : fpu_out_type;
signal cpi, fpi : cp_in_type;
signal cpo, fpo : cp_out_type;
signal pholdn, xholdn : std_logic;
signal iuol : iu_out_type;
signal rfi : rf_in_type; -- register-file input
signal rfo : rf_out_type; -- register-file output
signal crami : cram_in_type;
signal cramo : cram_out_type;
begin
clki.iholdn <= ico.hold;
clki.imdsn <= ico.mds;
clki.dholdn <= dco.hold;
clki.dmdsn <= dco.mds;
clki.fpuholdn <= fpui.fpuholdn and cpo.holdn and fpo.holdn;
pholdn <= fpui.fpuholdn and cpo.holdn and fpo.holdn;
xholdn <= cpo.holdn and dco.hold and ico.hold;
iuo <= iuol;
-- integer unit and register file
iu0 : iu port map (rst, clko.clk, clko.clkn, clko.iuclk, clko.iclk,
clko.dclk, clko.holdn, ici, ico, dci, dco, fpui, fpuo, iui, iuol,
rfi, rfo, cpi, cpo, fpi, fpo);
rf0 : regfile_iu generic map (RFIMPTYPE, RABITS, RDBITS, IREGNUM)
port map (rst, clko.clk, clko.clkn, rfi, rfo);
-- cache controller and memories
c0 : cache port map (rst, clko.clk, ici, ico, dci, dco, iuol,
apbi, apbo, ahbi, ahbo, ahbsi, crami, cramo, pholdn);
cmem0 : cachemem port map (clko.clk, crami, cramo);
-- serial floating-point co-processor (optional)
fpopt : if (FPIFTYPE = serial) generate
fpu0 : fpu_core port map (clko.clk, fpui, fpuo);
end generate;
-- parallel floating-point co-processor (optional)
fpcopt : if (FPIFTYPE = parallel) generate
fp0 : fp1eu port map (rst, clko, xholdn, fpi, fpo);
end generate;
nofpc : if (FPIFTYPE /= parallel) generate
fpo.holdn <= '1';
fpo.ldlock <= '0';
fpo.ccv <= '1';
end generate;
-- co-processor (optional)
cpopt : if CPEN generate
cp0 : fp1eu port map (rst, clko, xholdn, cpi, cpo);
end generate;
nocp : if not CPEN generate
cpo.holdn <= '1';
cpo.ldlock <= '0';
end generate;
end ;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Jidan FPU/trunk/fpu.vhd | 1 | 14210 | -------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: top entity
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library work;
use work.comppack.all;
use work.fpupack.all;
entity fpu is
port (
clk_i : in std_logic;
-- Input Operands A & B
opa_i : in std_logic_vector(FP_WIDTH-1 downto 0); -- Default: FP_WIDTH=32
opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
-- fpu operations (fpu_op_i):
-- ========================
-- 000 = add,
-- 001 = substract,
-- 010 = multiply,
-- 011 = divide,
-- 100 = square root
-- 101 = unused
-- 110 = unused
-- 111 = unused
fpu_op_i : in std_logic_vector(2 downto 0);
-- Rounding Mode:
-- ==============
-- 00 = round to nearest even(default),
-- 01 = round to zero,
-- 10 = round up,
-- 11 = round down
rmode_i : in std_logic_vector(1 downto 0);
-- Output port
output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
-- Control signals
start_i : in std_logic; -- is also restart signal
ready_o : out std_logic;
-- Exceptions
ine_o : out std_logic; -- inexact
overflow_o : out std_logic; -- overflow
underflow_o : out std_logic; -- underflow
div_zero_o : out std_logic; -- divide by zero
inf_o : out std_logic; -- infinity
zero_o : out std_logic; -- zero
qnan_o : out std_logic; -- queit Not-a-Number
snan_o : out std_logic -- signaling Not-a-Number
);
end fpu;
architecture rtl of fpu is
constant MUL_SERIAL: integer range 0 to 1 := 0; -- 0 for parallel multiplier, 1 for serial
constant MUL_COUNT: integer:= 11; --11 for parallel multiplier, 34 for serial
-- Input/output registers
signal s_opa_i, s_opb_i : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_fpu_op_i : std_logic_vector(2 downto 0);
signal s_rmode_i : std_logic_vector(1 downto 0);
signal s_output_o : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_ine_o, s_overflow_o, s_underflow_o, s_div_zero_o, s_inf_o, s_zero_o, s_qnan_o, s_snan_o : std_logic;
type t_state is (waiting,busy);
signal s_state : t_state;
signal s_start_i : std_logic;
signal s_count : integer;
signal s_output1 : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_infa, s_infb : std_logic;
-- ***Add/Substract units signals***
signal prenorm_addsub_fracta_28_o, prenorm_addsub_fractb_28_o : std_logic_vector(27 downto 0);
signal prenorm_addsub_exp_o : std_logic_vector(7 downto 0);
signal addsub_fract_o : std_logic_vector(27 downto 0);
signal addsub_sign_o : std_logic;
signal postnorm_addsub_output_o : std_logic_vector(31 downto 0);
signal postnorm_addsub_ine_o : std_logic;
-- ***Multiply units signals***
signal pre_norm_mul_exp_10 : std_logic_vector(9 downto 0);
signal pre_norm_mul_fracta_24 : std_logic_vector(23 downto 0);
signal pre_norm_mul_fractb_24 : std_logic_vector(23 downto 0);
signal mul_24_fract_48 : std_logic_vector(47 downto 0);
signal mul_24_sign : std_logic;
signal serial_mul_fract_48 : std_logic_vector(47 downto 0);
signal serial_mul_sign : std_logic;
signal mul_fract_48: std_logic_vector(47 downto 0);
signal mul_sign: std_logic;
signal post_norm_mul_output : std_logic_vector(31 downto 0);
signal post_norm_mul_ine : std_logic;
-- ***Division units signals***
signal pre_norm_div_dvdnd : std_logic_vector(49 downto 0);
signal pre_norm_div_dvsor : std_logic_vector(26 downto 0);
signal pre_norm_div_exp : std_logic_vector(EXP_WIDTH+1 downto 0);
signal serial_div_qutnt : std_logic_vector(26 downto 0);
signal serial_div_rmndr : std_logic_vector(26 downto 0);
signal serial_div_sign : std_logic;
signal serial_div_div_zero : std_logic;
signal post_norm_div_output : std_logic_vector(31 downto 0);
signal post_norm_div_ine : std_logic;
-- ***Square units***
signal pre_norm_sqrt_fracta_o : std_logic_vector(51 downto 0);
signal pre_norm_sqrt_exp_o : std_logic_vector(7 downto 0);
signal sqrt_sqr_o : std_logic_vector(25 downto 0);
signal sqrt_ine_o : std_logic;
signal post_norm_sqrt_output : std_logic_vector(31 downto 0);
signal post_norm_sqrt_ine_o : std_logic;
begin
--***Add/Substract units***
i_prenorm_addsub: pre_norm_addsub
port map (
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
fracta_28_o => prenorm_addsub_fracta_28_o,
fractb_28_o => prenorm_addsub_fractb_28_o,
exp_o=> prenorm_addsub_exp_o);
i_addsub: addsub_28
port map(
clk_i => clk_i,
fpu_op_i => s_fpu_op_i(0),
fracta_i => prenorm_addsub_fracta_28_o,
fractb_i => prenorm_addsub_fractb_28_o,
signa_i => s_opa_i(31),
signb_i => s_opb_i(31),
fract_o => addsub_fract_o,
sign_o => addsub_sign_o);
i_postnorm_addsub: post_norm_addsub
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
fract_28_i => addsub_fract_o,
exp_i => prenorm_addsub_exp_o,
sign_i => addsub_sign_o,
fpu_op_i => s_fpu_op_i(0),
rmode_i => s_rmode_i,
output_o => postnorm_addsub_output_o,
ine_o => postnorm_addsub_ine_o
);
--***Multiply units***
i_pre_norm_mul: pre_norm_mul
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
exp_10_o => pre_norm_mul_exp_10,
fracta_24_o => pre_norm_mul_fracta_24,
fractb_24_o => pre_norm_mul_fractb_24);
i_mul_24 : mul_24
port map(
clk_i => clk_i,
fracta_i => pre_norm_mul_fracta_24,
fractb_i => pre_norm_mul_fractb_24,
signa_i => s_opa_i(31),
signb_i => s_opb_i(31),
start_i => start_i,
fract_o => mul_24_fract_48,
sign_o => mul_24_sign,
ready_o => open);
i_serial_mul : serial_mul
port map(
clk_i => clk_i,
fracta_i => pre_norm_mul_fracta_24,
fractb_i => pre_norm_mul_fractb_24,
signa_i => s_opa_i(31),
signb_i => s_opb_i(31),
start_i => s_start_i,
fract_o => serial_mul_fract_48,
sign_o => serial_mul_sign,
ready_o => open);
-- serial or parallel multiplier will be choosed depending on constant MUL_SERIAL
mul_fract_48 <= mul_24_fract_48 when MUL_SERIAL=0 else serial_mul_fract_48;
mul_sign <= mul_24_sign when MUL_SERIAL=0 else serial_mul_sign;
i_post_norm_mul : post_norm_mul
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
exp_10_i => pre_norm_mul_exp_10,
fract_48_i => mul_fract_48,
sign_i => mul_sign,
rmode_i => s_rmode_i,
output_o => post_norm_mul_output,
ine_o => post_norm_mul_ine
);
--***Division units***
i_pre_norm_div : pre_norm_div
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
exp_10_o => pre_norm_div_exp,
dvdnd_50_o => pre_norm_div_dvdnd,
dvsor_27_o => pre_norm_div_dvsor);
i_serial_div : serial_div
port map(
clk_i=> clk_i,
dvdnd_i => pre_norm_div_dvdnd,
dvsor_i => pre_norm_div_dvsor,
sign_dvd_i => s_opa_i(31),
sign_div_i => s_opb_i(31),
start_i => s_start_i,
ready_o => open,
qutnt_o => serial_div_qutnt,
rmndr_o => serial_div_rmndr,
sign_o => serial_div_sign,
div_zero_o => serial_div_div_zero);
i_post_norm_div : post_norm_div
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
qutnt_i => serial_div_qutnt,
rmndr_i => serial_div_rmndr,
exp_10_i => pre_norm_div_exp,
sign_i => serial_div_sign,
rmode_i => s_rmode_i,
output_o => post_norm_div_output,
ine_o => post_norm_div_ine);
--***Square units***
i_pre_norm_sqrt : pre_norm_sqrt
port map(
clk_i => clk_i,
opa_i => s_opa_i,
fracta_52_o => pre_norm_sqrt_fracta_o,
exp_o => pre_norm_sqrt_exp_o);
i_sqrt: sqrt
generic map(RD_WIDTH=>52, SQ_WIDTH=>26)
port map(
clk_i => clk_i,
rad_i => pre_norm_sqrt_fracta_o,
start_i => s_start_i,
ready_o => open,
sqr_o => sqrt_sqr_o,
ine_o => sqrt_ine_o);
i_post_norm_sqrt : post_norm_sqrt
port map(
clk_i => clk_i,
opa_i => s_opa_i,
fract_26_i => sqrt_sqr_o,
exp_i => pre_norm_sqrt_exp_o,
ine_i => sqrt_ine_o,
rmode_i => s_rmode_i,
output_o => post_norm_sqrt_output,
ine_o => post_norm_sqrt_ine_o);
-----------------------------------------------------------------
-- Input Register
process(clk_i)
begin
if rising_edge(clk_i) then
s_opa_i <= opa_i;
s_opb_i <= opb_i;
s_fpu_op_i <= fpu_op_i;
s_rmode_i <= rmode_i;
s_start_i <= start_i;
end if;
end process;
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
output_o <= s_output_o;
ine_o <= s_ine_o;
overflow_o <= s_overflow_o;
underflow_o <= s_underflow_o;
div_zero_o <= s_div_zero_o;
inf_o <= s_inf_o;
zero_o <= s_zero_o;
qnan_o <= s_qnan_o;
snan_o <= s_snan_o;
end if;
end process;
-- FSM
process(clk_i)
begin
if rising_edge(clk_i) then
if s_start_i ='1' then
s_state <= busy;
s_count <= 0;
elsif s_count=6 and ((fpu_op_i="000") or (fpu_op_i="001")) then
s_state <= waiting;
ready_o <= '1';
s_count <=0;
elsif s_count=MUL_COUNT and fpu_op_i="010" then
s_state <= waiting;
ready_o <= '1';
s_count <=0;
elsif s_count=33 and fpu_op_i="011" then
s_state <= waiting;
ready_o <= '1';
s_count <=0;
elsif s_count=33 and fpu_op_i="100" then
s_state <= waiting;
ready_o <= '1';
s_count <=0;
elsif s_state=busy then
s_count <= s_count + 1;
else
s_state <= waiting;
ready_o <= '0';
end if;
end if;
end process;
-- Output Multiplexer
process(clk_i)
begin
if rising_edge(clk_i) then
if fpu_op_i="000" or fpu_op_i="001" then
s_output1 <= postnorm_addsub_output_o;
s_ine_o <= postnorm_addsub_ine_o;
elsif fpu_op_i="010" then
s_output1 <= post_norm_mul_output;
s_ine_o <= post_norm_mul_ine;
elsif fpu_op_i="011" then
s_output1 <= post_norm_div_output;
s_ine_o <= post_norm_div_ine;
elsif fpu_op_i="100" then
s_output1 <= post_norm_sqrt_output;
s_ine_o <= post_norm_sqrt_ine_o;
else
s_output1 <= (others => '0');
s_ine_o <= '0';
end if;
end if;
end process;
s_infa <= '1' when s_opa_i(30 downto 23)="11111111" else '0';
s_infb <= '1' when s_opb_i(30 downto 23)="11111111" else '0';
--In round down: the subtraction of two equal numbers other than zero are always -0!!!
process(s_output1, s_rmode_i, s_div_zero_o, s_infa, s_infb, s_qnan_o, s_snan_o, s_zero_o, s_fpu_op_i, s_opa_i, s_opb_i )
begin
if s_rmode_i="00" or (s_div_zero_o or (s_infa or s_infb) or s_qnan_o or s_snan_o)='1' then --round-to-nearest-even
s_output_o <= s_output1;
elsif s_rmode_i="01" and s_output1(30 downto 23)="11111111" then
--In round-to-zero: the sum of two non-infinity operands is never infinity,even if an overflow occures
s_output_o <= s_output1(31) & "1111111011111111111111111111111";
elsif s_rmode_i="10" and s_output1(31 downto 23)="111111111" then
--In round-up: the sum of two non-infinity operands is never negative infinity,even if an overflow occures
s_output_o <= "11111111011111111111111111111111";
elsif s_rmode_i="11" then
--In round-down: a-a= -0
if (s_fpu_op_i="000" or s_fpu_op_i="001") and s_zero_o='1' and (s_opa_i(31) or (s_fpu_op_i(0) xor s_opb_i(31)))='1' then
s_output_o <= "1" & s_output1(30 downto 0);
--In round-down: the sum of two non-infinity operands is never postive infinity,even if an overflow occures
elsif s_output1(31 downto 23)="011111111" then
s_output_o <= "01111111011111111111111111111111";
else
s_output_o <= s_output1;
end if;
else
s_output_o <= s_output1;
end if;
end process;
-- Generate Exceptions
s_underflow_o <= '1' when s_output1(30 downto 23)="00000000" and s_ine_o='1' else '0';
s_overflow_o <= '1' when s_output1(30 downto 23)="11111111" and s_ine_o='1' else '0';
s_div_zero_o <= serial_div_div_zero when fpu_op_i="011" else '0';
s_inf_o <= '1' when s_output1(30 downto 23)="11111111" and (s_qnan_o or s_snan_o)='0' else '0';
s_zero_o <= '1' when or_reduce(s_output1(30 downto 0))='0' else '0';
s_qnan_o <= '1' when s_output1(30 downto 0)=QNAN else '0';
s_snan_o <= '1' when s_opa_i(30 downto 0)=SNAN or s_opb_i(30 downto 0)=SNAN else '0';
end rtl; | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/VFLOAT_2015/General Modules/swap/parameterized_subtractor.vhd | 3 | 3962 | --======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized subtractor --
----------------------------------------------------------
entity parameterized_subtractor is
generic
(
bits : integer := 0
);
port
(
--inputs
A : in std_logic_vector(bits-1 downto 0);
B : in std_logic_vector(bits-1 downto 0);
--outputs
O : out std_logic_vector(bits-1 downto 0) := (others=>'0')
);
end parameterized_subtractor;
----------------------------------------------------------
-- Parameterized subtractor --
----------------------------------------------------------
architecture parameterized_subtractor_arch of parameterized_subtractor is
begin
--subtraction
O <= A - B;
end parameterized_subtractor_arch; -- end of architecture
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/ooac_leon_files/iface-ooac.vhd | 2 | 24747 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: iface
-- File: iface.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Package with type declarations for module interconnections
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
package iface is
subtype clk_type is std_logic;
------------------------------------------------------------------------------
-- Add I/Os for custom peripherals in the records below
------------------------------------------------------------------------------
-- peripheral inputs
type io_in_type is record
piol : std_logic_vector(15 downto 0); -- I/O port inputs
pci_arb_req_n : std_logic_vector(0 to 3);
end record;
-- peripheral outputs
type io_out_type is record
piol : std_logic_vector(15 downto 0); -- I/O port outputs
piodir : std_logic_vector(15 downto 0); -- I/O port direction
errorn : std_logic; -- CPU in error mode
wdog : std_logic; -- watchdog output
pci_arb_gnt_n : std_logic_vector(0 to 3);
end record;
------------------------------------------------------------------------------
-- IU register file signals
type rf_in_type is record
rd1addr : std_logic_vector(RABITS-1 downto 0); -- read address 1
rd2addr : std_logic_vector(RABITS-1 downto 0); -- read address 2
wraddr : std_logic_vector(RABITS-1 downto 0); -- write address
wrdata : std_logic_vector(RDBITS-1 downto 0); -- write data
ren1 : std_logic; -- read 1 enable
ren2 : std_logic; -- read 2 enable
wren : std_logic; -- write enable
end record;
type rf_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
-- co-processor register file signals
type rf_cp_in_type is record
rd1addr : std_logic_vector(3 downto 0); -- read address 1
rd2addr : std_logic_vector(3 downto 0); -- read address 2
wraddr : std_logic_vector(3 downto 0); -- write address
wrdata : std_logic_vector(RDBITS-1 downto 0); -- write data
ren1 : std_logic; -- read 1 enable
ren2 : std_logic; -- read 2 enable
wren : std_logic; -- write enable
end record;
type rf_cp_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
-- instruction cache diagnostic access inputs
type icdiag_in_type is record
addr : std_logic_vector(31 downto 0); -- memory stage address
enable : std_logic;
read : std_logic;
tag : std_logic;
flush : std_logic;
end record;
-- data cache controller inputs
type dcache_in_type is record
asi : std_logic_vector(7 downto 0); -- ASI for load/store
maddress : std_logic_vector(31 downto 0); -- memory stage address
eaddress : std_logic_vector(31 downto 0); -- execute stage address
edata : std_logic_vector(31 downto 0); -- execute stage data
size : std_logic_vector(1 downto 0);
signed : std_logic;
enaddr : std_logic;
eenaddr : std_logic;
nullify : std_logic;
lock : std_logic;
read : std_logic;
write : std_logic;
flush : std_logic;
dsuen : std_logic;
end record;
-- data cache controller outputs
type dcache_out_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
mexc : std_logic; -- memory exception
hold : std_logic;
mds : std_logic;
werr : std_logic; -- memory write error
icdiag : icdiag_in_type;
dsudata : std_logic_vector(31 downto 0);
end record;
type icache_in_type is record
rpc : std_logic_vector(31 downto PCLOW); -- raw address (npc)
fpc : std_logic_vector(31 downto PCLOW); -- latched address (fpc)
dpc : std_logic_vector(31 downto PCLOW); -- latched address (dpc)
rbranch : std_logic; -- Instruction branch
fbranch : std_logic; -- Instruction branch
nullify : std_logic; -- instruction nullify
su : std_logic; -- super-user
flush : std_logic; -- flush icache
end record;
type icache_out_type is record
data : std_logic_vector(31 downto 0);
exception : std_logic;
hold : std_logic;
flush : std_logic; -- flush in progress
diagrdy : std_logic; -- diagnostic access ready
diagdata : std_logic_vector(31 downto 0); -- diagnostic data
mds : std_logic; -- memory data strobe
end record;
type memory_ic_in_type is record
address : std_logic_vector(31 downto 0); -- memory address
burst : std_logic; -- burst request
req : std_logic; -- memory cycle request
su : std_logic; -- supervisor address space
flush : std_logic; -- flush in progress
end record;
type memory_ic_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
grant : std_logic; --
retry : std_logic; --
mexc : std_logic; -- memory exception
burst : std_logic; -- memory burst enable
ics : std_logic_vector(1 downto 0); -- icache state (from CCR)
cache : std_logic; -- cacheable data
end record;
type memory_dc_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
asi : std_logic_vector(3 downto 0); -- ASI for load/store
size : std_logic_vector(1 downto 0);
burst : std_logic;
read : std_logic;
req : std_logic;
flush : std_logic; -- flush in progress
lock : std_logic;
su : std_logic;
end record;
type memory_dc_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
grant : std_logic; --
retry : std_logic; --
mexc : std_logic; -- memory exception
werr : std_logic; -- memory write error
dcs : std_logic_vector(1 downto 0);
iflush : std_logic; -- flush icache (from CCR)
dflush : std_logic; -- flush dcache (from CCR)
cache : std_logic; -- cacheable data
dsnoop : std_logic; -- snoop enable
ba : std_logic; -- bus active (used for snooping)
bg : std_logic; -- bus grant (used for snooping)
end record;
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
end record;
type memory_out_type is record
address : std_logic_vector(27 downto 0);
data : std_logic_vector(31 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
iosn : std_logic;
romsn : std_logic_vector(1 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
read : std_logic;
end record;
type pio_in_type is record
piol : std_logic_vector(15 downto 0);
pioh : std_logic_vector(15 downto 0);
end record;
type pio_out_type is record
irq : std_logic_vector(3 downto 0);
piol : std_logic_vector(31 downto 0);
piodir : std_logic_vector(17 downto 0);
io8lsb : std_logic_vector(7 downto 0);
rxd : std_logic_vector(1 downto 0);
ctsn : std_logic_vector(1 downto 0);
wrio : std_logic;
end record;
type wprot_out_type is record
wprothit : std_logic;
end record;
type ahbstat_out_type is record
ahberr : std_logic;
end record;
type mctrl_out_type is record
pioh : std_logic_vector(15 downto 0);
end record;
type itram_in_type is record
tag : std_logic_vector(ITAG_BITS - ILINE_SIZE - 1 downto 0);
valid : std_logic_vector(ILINE_SIZE -1 downto 0);
enable : std_logic;
write : std_logic;
end record;
type itram_out_type is record
tag : std_logic_vector(ITAG_BITS - ILINE_SIZE -1 downto 0);
valid : std_logic_vector(ILINE_SIZE -1 downto 0);
end record;
type idram_in_type is record
address : std_logic_vector((IOFFSET_BITS + ILINE_BITS -1) downto 0);
data : std_logic_vector(31 downto 0);
enable : std_logic;
write : std_logic;
end record;
type idram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type dtram_in_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE - 1 downto 0);
valid : std_logic_vector(DLINE_SIZE -1 downto 0);
enable : std_logic;
write : std_logic;
end record;
type dtram_out_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE -1 downto 0);
valid : std_logic_vector(DLINE_SIZE -1 downto 0);
end record;
type dtramsn_in_type is record
enable : std_logic;
write : std_logic;
address : std_logic_vector((DOFFSET_BITS-1) downto 0);
end record;
type dtramsn_out_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE -1 downto 0);
end record;
type ddram_in_type is record
address : std_logic_vector((DOFFSET_BITS + DLINE_BITS -1) downto 0);
data : std_logic_vector(31 downto 0);
enable : std_logic;
write : std_logic;
end record;
type ddram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type icram_in_type is record
itramin : itram_in_type;
idramin : idram_in_type;
end record;
type icram_out_type is record
itramout : itram_out_type;
idramout : idram_out_type;
end record;
type dcram_in_type is record
dtramin : dtram_in_type;
ddramin : ddram_in_type;
dtraminsn : dtramsn_in_type;
end record;
type dcram_out_type is record
dtramout : dtram_out_type;
ddramout : ddram_out_type;
dtramoutsn : dtramsn_out_type;
end record;
type cram_in_type is record
icramin : icram_in_type;
dcramin : dcram_in_type;
end record;
type cram_out_type is record
icramout : icram_out_type;
dcramout : dcram_out_type;
end record;
type irq_in_type is record
irq : std_logic_vector(15 downto 1);
intack : std_logic;
irl : std_logic_vector(3 downto 0);
end record;
type irq_out_type is record
irl : std_logic_vector(3 downto 0);
end record;
type irq2_in_type is record
irq : std_logic_vector(31 downto 0);
end record;
type irq2_out_type is record
irq : std_logic;
end record;
type timers_out_type is record
irq : std_logic_vector(1 downto 0);
tick : std_logic;
wdog : std_logic;
end record;
type uart_in_type is record
rxd : std_logic;
ctsn : std_logic;
scaler : std_logic_vector(7 downto 0);
end record;
type uart_out_type is record
rxen : std_logic;
txen : std_logic;
flow : std_logic;
irq : std_logic;
rtsn : std_logic;
txd : std_logic;
end record;
type clkgen_in_type is record
iholdn : std_logic; -- Instruction hold
imdsn : std_logic; -- Instruction memory data strobe
dholdn : std_logic; -- Data hold
dmdsn : std_logic; -- Data memory data strobe
fpuholdn : std_logic; -- FPU/CP busy
end record;
type clkgen_out_type is record
clk : clk_type; -- Common clock
clkn : clk_type; -- inverted clock
iuclk : clk_type; -- Processor clock
dclk : clk_type; -- Data latch clock
iclk : clk_type; -- Instruction latch clock
pciclk : clk_type; -- PCI config-block clock
holdn : std_logic; -- Instruction latch clock
end record;
-- iu pipeline control type (defined here to be visible to debug and coprocessor)
type pipeline_control_type is record
inst : std_logic_vector(31 downto 0); -- instruction word
pc : std_logic_vector(31 downto PCLOW); -- program counter
annul : std_logic; -- instruction annul
cnt : std_logic_vector(1 downto 0); -- cycle number (multi-cycle inst)
ld : std_logic; -- load cycle
pv : std_logic; -- PC valid
rett : std_logic; -- RETT indicator
trap : std_logic; -- trap pending flag
tt : std_logic_vector(5 downto 0); -- trap type
rd : std_logic_vector(RABITS-1 downto 0); -- destination register address
end record;
-- Stucture for FPU/CP control
type cp_in_type is record
flush : std_logic; -- pipeline flush
exack : std_logic; -- CP exception acknowledge
dannul : std_logic; -- decode stage annul
dtrap : std_logic; -- decode stage trap
dcnt : std_logic_vector(1 downto 0); -- decode stage cycle counter
dinst : std_logic_vector(31 downto 0); -- decode stage instruction
ex : pipeline_control_type; -- iu pipeline ctrl (ex)
me : pipeline_control_type; -- iu pipeline ctrl (me)
wr : pipeline_control_type; -- iu pipeline ctrl (wr)
lddata : std_logic_vector(31 downto 0); -- load data
end record;
type cp_out_type is record
data : std_logic_vector(31 downto 0); -- store data
exc : std_logic; -- CP exception
cc : std_logic_vector(1 downto 0); -- CP condition codes
ccv : std_logic; -- CP condition codes valid
holdn : std_logic; -- CP pipeline hold
ldlock : std_logic; -- CP load/store interlock
end record;
-- iu debug port
type iu_debug_in_type is record
dsuen : std_logic; -- DSU enable
dbreak : std_logic; -- debug break-in
btrapa : std_logic; -- break on IU trap
btrape : std_logic; -- break on IU trap
berror : std_logic; -- break on IU error mode
bwatch : std_logic; -- break on IU watchpoint
bsoft : std_logic; -- break on software breakpoint (TA 1)
rerror : std_logic; -- reset processor error mode
step : std_logic; -- single step
denable : std_logic; -- diagnostic register access enable
dwrite : std_logic; -- read/write
daddr : std_logic_vector(20 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
end record;
type iu_debug_out_type is record
clk : std_logic;
rst : std_logic;
holdn : std_logic;
ex : pipeline_control_type;
me : pipeline_control_type;
wr : pipeline_control_type;
write_reg : std_logic;
mresult : std_logic_vector(31 downto 0);
result : std_logic_vector(31 downto 0);
trap : std_logic;
error : std_logic;
dmode : std_logic;
dmode2 : std_logic;
vdmode : std_logic;
dbreak : std_logic;
tt : std_logic_vector(7 downto 0);
psrtt : std_logic_vector(7 downto 0);
psrpil : std_logic_vector(3 downto 0);
diagrdy : std_logic;
ddata : std_logic_vector(31 downto 0); -- diagnostic data
end record;
type iu_in_type is record
irl : std_logic_vector(3 downto 0); -- interrupt request level
debug : iu_debug_in_type;
end record;
type iu_out_type is record
error : std_logic;
intack : std_logic;
irqvec : std_logic_vector(3 downto 0);
ipend : std_logic;
debug : iu_debug_out_type;
end record;
-- Meiko FPU interface
type fpu_in_type is record
FpInst : std_logic_vector(9 downto 0);
FpOp : std_logic;
FpLd : std_logic;
Reset : std_logic;
fprf_dout1 : std_logic_vector(63 downto 0);
fprf_dout2 : std_logic_vector(63 downto 0);
RoundingMode : std_logic_vector(1 downto 0);
ss_scan_mode : std_logic;
fp_ctl_scan_in : std_logic;
fpuholdn : std_logic;
end record;
type fpu_out_type is record
FpBusy : std_logic;
FracResult : std_logic_vector(54 downto 3);
ExpResult : std_logic_vector(10 downto 0);
SignResult : std_logic;
SNnotDB : std_logic;
Excep : std_logic_vector(5 downto 0);
ConditionCodes : std_logic_vector(1 downto 0);
fp_ctl_scan_out : std_logic;
end record;
type cp_unit_in_type is record -- coprocessor execution unit input
op1 : std_logic_vector (63 downto 0); -- operand 1
op2 : std_logic_vector (63 downto 0); -- operand 2
opcode : std_logic_vector (9 downto 0); -- opcode
start : std_logic; -- start
load : std_logic; -- load operands
flush : std_logic; -- cancel operation
end record;
type cp_unit_out_type is record -- coprocessor execution unit output
res : std_logic_vector (63 downto 0); -- result
cc : std_logic_vector (1 downto 0); -- condition codes
exc : std_logic_vector (5 downto 0); -- exception
busy : std_logic; -- eu busy
end record;
type rst_type is record
syncrst : std_logic; -- synchronous reset
rawrst : std_logic; -- asynchronous reset
end record;
-- pci_[in|out]_type groups all EXTERNAL pci ports in unidirectional form
-- as well as the required enable signals for the pads
type pci_in_type is record
pci_rst_in_n : std_logic;
pci_clk_in : std_logic;
pci_gnt_in_n : std_logic;
pci_idsel_in : std_logic;
pci_adin : std_logic_vector(31 downto 0);
pci_cbein_n : std_logic_vector(3 downto 0);
pci_frame_in_n : std_logic;
pci_irdy_in_n : std_logic;
pci_trdy_in_n : std_logic;
pci_devsel_in_n : std_logic;
pci_stop_in_n : std_logic;
pci_lock_in_n : std_logic;
pci_perr_in_n : std_logic;
pci_serr_in_n : std_logic;
pci_par_in : std_logic;
pci_host : std_logic;
pci_66 : std_logic;
pme_status : std_logic;
end record;
type pci_out_type is record
pci_aden_n : std_logic_vector(31 downto 0);
pci_cbe0_en_n : std_logic;
pci_cbe1_en_n : std_logic;
pci_cbe2_en_n : std_logic;
pci_cbe3_en_n : std_logic;
pci_frame_en_n : std_logic;
pci_irdy_en_n : std_logic;
pci_ctrl_en_n : std_logic;
pci_perr_en_n : std_logic;
pci_par_en_n : std_logic;
pci_req_en_n : std_logic;
pci_lock_en_n : std_logic;
pci_serr_en_n : std_logic;
pci_int_en_n : std_logic;
pci_req_out_n : std_logic;
pci_adout : std_logic_vector(31 downto 0);
pci_cbeout_n : std_logic_vector(3 downto 0);
pci_frame_out_n : std_logic;
pci_irdy_out_n : std_logic;
pci_trdy_out_n : std_logic;
pci_devsel_out_n : std_logic;
pci_stop_out_n : std_logic;
pci_perr_out_n : std_logic;
pci_serr_out_n : std_logic;
pci_par_out : std_logic;
pci_lock_out_n : std_logic;
power_state : std_logic_vector(1 downto 0);
pme_enable : std_logic;
pme_clear : std_logic;
pci_int_out_n : std_logic;
end record;
type div_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
y : std_logic_vector(32 downto 0); -- Y (MSB divident)
flush : std_logic;
signed : std_logic;
start : std_logic;
end record;
type div_out_type is record
ready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(31 downto 0); -- div result
end record;
type mul_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
y : std_logic_vector(7 downto 0); -- Y (MSB MAC register)
asr18 : std_logic_vector(31 downto 0); -- LSB MAC register
end record;
type mul_out_type is record
ready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(63 downto 0); -- mul result
end record;
type ahb_dma_in_type is record
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(31 downto 0);
start : std_logic;
burst : std_logic;
write : std_logic;
size : std_logic_vector(1 downto 0);
end record;
type ahb_dma_out_type is record
start : std_logic;
active : std_logic;
ready : std_logic;
retry : std_logic;
mexc : std_logic;
haddr : std_logic_vector(9 downto 0);
rdata : std_logic_vector(31 downto 0);
end record;
type actpci_be_in_type is record
mem_ad_int : std_logic_vector(31 downto 0);
mem_data : std_logic_vector(31 downto 0);
dp_done : std_logic;
dp_start : std_logic;
rd_be_now : std_logic;
rd_cyc : std_logic;
wr_be_now : std_logic_vector(3 downto 0);
wr_cyc : std_logic;
bar0_mem_cyc : std_logic;
busy : std_logic_vector(3 downto 0);
master_active : std_logic;
be_gnt : std_logic;
end record;
type actpci_be_out_type is record
rd_be_rdy : std_logic;
wr_be_rdy : std_logic;
error : std_logic;
busy : std_logic;
mem_data : std_logic_vector(31 downto 0);
cs_controln : std_logic;
rd_controln : std_logic;
wr_controln : std_logic;
control_add : std_logic_vector(1 downto 0);
ext_intn : std_logic;
be_req : std_logic;
end record;
type dsu_in_type is record
dsuen : std_logic;
dsubre : std_logic;
end record;
type dsu_out_type is record
dsuact : std_logic;
ntrace : std_logic;
freezetime : std_logic;
lresp : std_logic;
dresp : std_logic;
dsuen : std_logic;
dsubre : std_logic;
end record;
type dcom_in_type is record
dsurx : std_logic;
end record;
type dcom_out_type is record
dsutx : std_logic;
end record;
type dsuif_in_type is record
dsui : dsu_in_type;
dcomi : dcom_in_type;
end record;
type dsuif_out_type is record
dsuo : dsu_out_type;
dcomo : dcom_out_type;
end record;
type dcom_uart_in_type is record
rxd : std_logic;
read : std_logic;
write : std_logic;
data : std_logic_vector(7 downto 0);
dsuen : std_logic;
end record;
type dcom_uart_out_type is record
txd : std_logic;
dready : std_logic;
tsempty : std_logic;
thempty : std_logic;
lock : std_logic;
enable : std_logic;
data : std_logic_vector(7 downto 0);
end record;
type tracebuf_in_type is record
addr : std_logic_vector(TBUFABITS downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
type dsumem_in_type is record
pbufi : tracebuf_in_type;
abufi : tracebuf_in_type;
end record;
type dsumem_out_type is record
pbufo : tracebuf_out_type;
abufo : tracebuf_out_type;
end record;
-- -----------------------------------------------
type ddm_in_type is record -- added for DDM
button0 : std_logic;
button1 : std_logic;
button2 : std_logic;
button3 : std_logic;
audioin : std_logic;
end record;
type ddm_out_type is record
digit0 : std_logic_vector(6 downto 0);
digit1 : std_logic_vector(6 downto 0);
audioout : std_logic;
lr_out : std_logic;
shift_clk : std_logic;
mclk : std_logic;
dispen : std_logic;
end record;
-- -----------------------------------------------
end;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.3.7/leon/cachemem.vhd | 2 | 4499 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: cachemem
-- File: cachemem.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Contains ram cells for both instruction and data caches
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.macro.all;
use work.tech_map.all;
entity cachemem is
port (
clk : in clk_type;
crami : in cram_in_type;
cramo : out cram_out_type
);
end;
architecture rtl of cachemem is
constant ITDEPTH : natural := 2**IOFFSET_BITS;
constant DTDEPTH : natural := 2**DOFFSET_BITS;
constant ITWIDTH : natural := ITAG_BITS;
constant DTWIDTH : natural := DTAG_BITS;
signal itaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
signal idaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
signal itdatain : std_logic_vector(ITAG_BITS -1 downto 0);
signal itdataout : std_logic_vector(ITAG_BITS -1 downto 0);
signal iddatain : std_logic_vector(32 -1 downto 0);
signal iddataout : std_logic_vector(32 -1 downto 0);
signal itenable : std_logic;
signal idenable : std_logic;
signal itwrite : std_logic;
signal idwrite : std_logic;
signal dtaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal ddaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
signal dtdatain : std_logic_vector(DTAG_BITS -1 downto 0);
signal dtdataout : std_logic_vector(DTAG_BITS -1 downto 0);
signal dddatain : std_logic_vector(32 -1 downto 0);
signal dddataout : std_logic_vector(32 -1 downto 0);
signal dtenable : std_logic;
signal ddenable : std_logic;
signal dtwrite : std_logic;
signal ddwrite : std_logic;
signal vcc, gnd : std_logic;
begin
vcc <= '1'; gnd <= '0';
itaddr <= crami.icramin.idramin.address(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
idaddr <= crami.icramin.idramin.address;
itinsel : process(crami)
begin
itdatain(ITAG_BITS - 1 downto 0) <= crami.icramin.itramin.tag &
crami.icramin.itramin.valid;
iddatain(31 downto 0) <= crami.icramin.idramin.data;
dtdatain(DTAG_BITS - 1 downto 0) <= crami.dcramin.dtramin.tag &
crami.dcramin.dtramin.valid;
dddatain(32 - 1 downto 0) <= crami.dcramin.ddramin.data;
end process;
itwrite <= crami.icramin.itramin.write;
idwrite <= crami.icramin.idramin.write;
itenable <= crami.icramin.itramin.enable;
idenable <= crami.icramin.idramin.enable;
dtaddr <= crami.dcramin.ddramin.address(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
ddaddr <= crami.dcramin.ddramin.address;
dtwrite <= crami.dcramin.dtramin.write;
ddwrite <= crami.dcramin.ddramin.write;
dtenable <= crami.dcramin.dtramin.enable;
ddenable <= crami.dcramin.ddramin.enable;
itags0 : syncram
generic map ( dbits => ITAG_BITS, abits => IOFFSET_BITS)
port map ( itaddr, clk, itdatain, itdataout, itenable, itwrite);
dtags0 : syncram
generic map ( dbits => DTAG_BITS, abits => DOFFSET_BITS)
port map ( dtaddr, clk, dtdatain, dtdataout, dtenable, dtwrite);
idata0 : syncram
generic map ( dbits => 32, abits => IOFFSET_BITS+ILINE_BITS)
port map ( idaddr, clk, iddatain, iddataout, idenable, idwrite);
ddata0 : syncram
generic map ( dbits => 32, abits => DOFFSET_BITS+DLINE_BITS)
port map ( ddaddr, clk, dddatain, dddataout, ddenable, ddwrite);
cramo.icramout.itramout.valid <= itdataout(ILINE_SIZE -1 downto 0);
cramo.icramout.itramout.tag <= itdataout(ITAG_BITS-1 downto ILINE_SIZE);
cramo.icramout.idramout.data <= iddataout(31 downto 0);
cramo.dcramout.dtramout.valid <= dtdataout(DLINE_SIZE -1 downto 0);
cramo.dcramout.dtramout.tag <= dtdataout(DTAG_BITS-1 downto DLINE_SIZE);
cramo.dcramout.ddramout.data <= dddataout(31 downto 0);
end ;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.3.7/leon/tech_map.vhd | 2 | 22979 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Package: tech_map
-- File: tech_map.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Technology mapping of cache-rams, regfiles, pads and multiplier
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
package tech_map is
-- IU three-port regfile
component regfile_iu
generic (
rftype : integer := 1;
abits : integer := 8; dbits : integer := 32; words : integer := 128
);
port (
rst : in std_logic;
clk : in clk_type;
clkn : in clk_type;
rfi : in rf_in_type;
rfo : out rf_out_type);
end component;
-- CP three-port
component regfile_cp
generic (
abits : integer := 4; dbits : integer := 32; words : integer := 16
);
port (
rst : in std_logic;
clk : in clk_type;
rfi : in rf_cp_in_type;
rfo : out rf_cp_out_type);
end component;
-- single-port sync ram
component syncram
generic ( abits : integer := 10; dbits : integer := 8);
port (
address : in std_logic_vector((abits -1) downto 0);
clk : in clk_type;
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_logic;
write : in std_logic
);
end component;
-- sync prom (used for boot-prom option)
component bprom
port (
clk : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(31 downto 0);
data : out std_logic_vector(31 downto 0)
);
end component;
-- signed multipler
component hw_smult
generic ( abits : integer := 10; bbits : integer := 8 );
port (
a : in std_logic_vector(abits-1 downto 0);
b : in std_logic_vector(bbits-1 downto 0);
c : out std_logic_vector(abits+bbits-1 downto 0)
);
end component;
-- pads
component inpad port (pad : in std_logic; q : out std_logic); end component;
component smpad port (pad : in std_logic; q : out std_logic); end component;
component outpad
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end component;
component toutpadu
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end component;
component odpad
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end component;
component iodpad
generic (drive : integer := 1);
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component iopad
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component smiopad
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component pcioutpad port (d : in std_logic; pad : out std_logic); end component;
component pcitoutpad port (d, en : in std_logic; pad : out std_logic); end component;
component pciiopad
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component pciiodpad
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
end tech_map;
-- syncronous ram
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_fs90.all;
use work.tech_umc18.all;
use work.tech_generic.all;
use work.tech_virtex.all;
entity syncram is
generic ( abits : integer := 8; dbits : integer := 32);
port (
address : in std_logic_vector (abits -1 downto 0);
clk : in clk_type;
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_logic;
write : in std_logic
);
end;
architecture behav of syncram is
begin
inf : if INFER_RAM generate
u0 : generic_syncram generic map (abits => abits, dbits => dbits)
port map (address, clk, datain, dataout, enable, write);
end generate;
hb : if (not INFER_RAM) generate
at2 : if TARGET_TECH = atc25 generate
u0 : atc25_syncram generic map (abits => abits, dbits => dbits)
port map (address, clk, datain, dataout, enable, write);
end generate;
at3 : if TARGET_TECH = atc35 generate
u0 : atc35_syncram generic map (abits => abits, dbits => dbits)
port map (address, clk, datain, dataout, enable, write);
end generate;
fs9 : if TARGET_TECH = fs90 generate
u0 : fs90_syncram generic map (abits => abits, dbits => dbits)
port map (address, clk, datain, dataout, enable, write);
end generate;
umc1 : if TARGET_TECH = umc18 generate
u0 : umc18_syncram generic map (abits => abits, dbits => dbits)
port map (address, clk, datain, dataout, enable, write);
end generate;
xcv : if TARGET_TECH = virtex generate
u0 : virtex_syncram generic map (abits => abits, dbits => dbits)
port map (address, clk, datain, dataout, enable, write);
end generate;
sim : if TARGET_TECH = gen generate
u0 : generic_syncram generic map (abits => abits, dbits => dbits)
port map (address, clk, datain, dataout, enable, write);
end generate;
end generate;
end;
-- IU regfile
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_fs90.all;
use work.tech_umc18.all;
use work.tech_generic.all;
use work.tech_virtex.all;
entity regfile_iu is
generic (
rftype : integer := 1;
abits : integer := 8; dbits : integer := 32; words : integer := 128
);
port (
rst : in std_logic;
clk : in clk_type;
clkn : in clk_type;
rfi : in rf_in_type;
rfo : out rf_out_type);
end;
architecture rtl of regfile_iu is
signal vcc : std_logic;
begin
vcc <= '1';
inf : if INFER_REGF generate
u0 : generic_regfile_iu generic map (rftype, abits, dbits, words)
port map (rst, clk, clkn, rfi, rfo);
end generate;
ninf : if not INFER_REGF generate
atm0 : if TARGET_TECH = atc25 generate
u0 : atc25_regfile_iu generic map (abits, dbits, words)
port map (rst, clk, clkn, rfi, rfo);
end generate;
atm1 : if TARGET_TECH = atc35 generate
u0 : atc35_regfile generic map (abits, dbits, words)
port map (rst, clk, clkn, rfi, rfo);
end generate;
umc0 : if TARGET_TECH = fs90 generate
u0 : fs90_regfile generic map (abits, dbits, words)
port map (rst, clk, clkn, rfi, rfo);
end generate;
umc1 : if TARGET_TECH = umc18 generate
u0 : umc18_regfile generic map (abits, dbits, words)
port map (rst, clk, clkn, rfi, rfo);
end generate;
xcv : if TARGET_TECH = virtex generate
u0 : virtex_regfile generic map (abits, dbits, words)
port map (rst, clk, clkn, rfi, rfo);
end generate;
sim : if TARGET_TECH = gen generate
u0 : generic_regfile_iu generic map (rftype, abits, dbits, words)
port map (rst, clk, clkn, rfi, rfo);
end generate;
end generate;
end;
-- Parallel FPU/CP regfile
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_fs90.all;
use work.tech_umc18.all;
use work.tech_generic.all;
use work.tech_virtex.all;
entity regfile_cp is
generic (
abits : integer := 4; dbits : integer := 32; words : integer := 16
);
port (
rst : in std_logic;
clk : in clk_type;
rfi : in rf_cp_in_type;
rfo : out rf_cp_out_type);
end;
architecture rtl of regfile_cp is
signal vcc : std_logic;
begin
vcc <= '1';
inf : if INFER_REGF generate
u0 : generic_regfile_cp generic map (abits, dbits, words)
port map (rst, clk, rfi, rfo);
end generate;
ninf : if not INFER_REGF generate
atm0 : if TARGET_TECH = atc25 generate
u0 : atc25_regfile_cp generic map (abits, dbits, words)
port map (rst, clk, rfi, rfo);
end generate;
atm1 : if TARGET_TECH = atc35 generate
u0 : atc35_regfile_cp generic map (abits, dbits, words)
port map (rst, clk, rfi, rfo);
end generate;
-- umc0 : if TARGET_TECH = fs90 generate
-- u0 : fs90_regfile_cp generic map (abits, dbits, words)
-- port map (rst, clk, rfi, rfo);
-- end generate;
-- umc1 : if TARGET_TECH = umc18 generate
-- u0 : umc18_regfile_cp generic map (abits, dbits, words)
-- port map (rst, clk, rfi, rfo);
-- end generate;
xcv : if TARGET_TECH = virtex generate
u0 : virtex_regfile_cp generic map (abits, dbits, words)
port map (rst, clk, rfi, rfo);
end generate;
sim : if TARGET_TECH = gen generate
u0 : generic_regfile_cp generic map (abits, dbits, words)
port map (rst, clk, rfi, rfo);
end generate;
end generate;
end;
-- boot-prom
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.tech_atc35.all;
use work.tech_generic.all;
use work.tech_virtex.all;
entity bprom is
port (
clk : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(31 downto 0);
data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of bprom is
component gen_bprom
port (
clk : in std_logic;
csn : in std_logic;
addr : in std_logic_vector (29 downto 0);
data : out std_logic_vector (31 downto 0));
end component;
begin
b0: if INFER_ROM generate
u0 : gen_bprom port map (clk, cs, addr(31 downto 2), data);
end generate;
b1: if (not INFER_ROM) and (TARGET_TECH = virtex) generate
u0 : virtex_bprom port map (clk, addr(31 downto 2), data);
end generate;
end;
-- multiplier
library ieee;
use ieee.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.multlib.all;
use work.tech_generic.all;
entity hw_smult is
generic ( abits : integer := 10; bbits : integer := 8 );
port (
a : in std_logic_vector(abits-1 downto 0);
b : in std_logic_vector(bbits-1 downto 0);
c : out std_logic_vector(abits+bbits-1 downto 0)
);
end;
architecture rtl of hw_smult is
begin
inf : if INFER_MULT generate
u0 : generic_smult
generic map (abits => abits, bbits => bbits)
port map (a, b, c);
end generate;
mg : if not INFER_MULT generate
m1717 : if (abits = 17) and (bbits = 17) generate
u0 : mul_17_17 port map (a, b, c);
end generate;
m339 : if (abits = 33) and (bbits = 9) generate
u0 : mul_33_9 port map (a, b, c);
end generate;
m3317 : if (abits = 33) and (bbits = 17) generate
u0 : mul_33_17 port map (a, b, c);
end generate;
m3333 : if (abits = 33) and (bbits = 33) generate
u0 : mul_33_33 port map (a, b, c);
end generate;
end generate;
end;
-- input pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_fs90.all;
use work.tech_umc18.all;
use work.tech_generic.all;
entity inpad is port (pad : in std_logic; q : out std_logic); end;
architecture rtl of inpad is
begin
inf : if INFER_PADS generate
ginpad0 : geninpad port map (q => q, pad => pad);
end generate;
ninf : if not INFER_PADS generate
ip1 : if TARGET_TECH = atc25 generate
ipx : atc25_inpad port map (q => q, pad => pad);
end generate;
ip2 : if TARGET_TECH = atc35 generate
ipx : atc35_inpad port map (q => q, pad => pad);
end generate;
ip3 : if TARGET_TECH = fs90 generate
ipx : fs90_inpad port map (q => q, pad => pad);
end generate;
ip4 : if TARGET_TECH = umc18 generate
ipx : umc18_inpad port map (q => q, pad => pad);
end generate;
end generate;
end;
-- input schmitt pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_fs90.all;
use work.tech_umc18.all;
use work.tech_generic.all;
entity smpad is port (pad : in std_logic; q : out std_logic); end;
architecture rtl of smpad is
begin
inf : if INFER_PADS generate
gsmpad0 : gensmpad port map (pad => pad, q => q);
end generate;
ninf : if not INFER_PADS generate
sm1 : if TARGET_TECH = atc25 generate
smx : atc25_smpad port map (q => q, pad => pad);
end generate;
sm2 : if TARGET_TECH = atc35 generate
smx : atc35_smpad port map (q => q, pad => pad);
end generate;
sm3 : if TARGET_TECH = fs90 generate
smx : fs90_smpad port map (q => q, pad => pad);
end generate;
sm4 : if TARGET_TECH = umc18 generate
smx : umc18_smpad port map (q => q, pad => pad);
end generate;
end generate;
end;
-- output pads
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_fs90.all;
use work.tech_umc18.all;
use work.tech_generic.all;
entity outpad is
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end;
architecture rtl of outpad is
begin
inf : if INFER_PADS generate
goutpad0 : genoutpad port map (d => d, pad => pad);
end generate;
ninf : if not INFER_PADS generate
op1 : if TARGET_TECH = atc25 generate
opx : atc25_outpad generic map (drive) port map (d => d, pad => pad);
end generate;
op2 : if TARGET_TECH = atc35 generate
opx : atc35_outpad generic map (drive) port map (d => d, pad => pad);
end generate;
op3 : if TARGET_TECH = fs90 generate
opx : fs90_outpad generic map (drive) port map (d => d, pad => pad);
end generate;
op4 : if TARGET_TECH = umc18 generate
opx : umc18_outpad generic map (drive) port map (d => d, pad => pad);
end generate;
end generate;
end;
-- tri-state output pads with pull-up
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_fs90.all;
use work.tech_umc18.all;
use work.tech_generic.all;
entity toutpadu is
generic (drive : integer := 1);
port (d, en : in std_logic; pad : out std_logic);
end;
architecture rtl of toutpadu is
begin
inf : if INFER_PADS generate
giop0 : gentoutpadu port map (d => d, en => en, pad => pad);
end generate;
ninf : if not INFER_PADS generate
atc25t : if TARGET_TECH = atc25 generate
p0 : atc25_toutpadu generic map (drive) port map (d => d, en => en, pad => pad);
end generate;
atc35t : if TARGET_TECH = atc35 generate
p0 : atc35_toutpadu generic map (drive) port map (d => d, en => en, pad => pad);
end generate;
fs90t : if TARGET_TECH = fs90 generate
p0 : fs90_toutpadu generic map (drive) port map (d => d, en => en, pad => pad);
end generate;
umc18t : if TARGET_TECH = umc18 generate
p0 : umc18_toutpadu generic map (drive) port map (d => d, en => en, pad => pad);
end generate;
end generate;
end;
-- bidirectional pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_fs90.all;
use work.tech_umc18.all;
use work.tech_generic.all;
entity iopad is
generic (drive : integer := 1);
port (
d : in std_logic;
en : in std_logic;
q : out std_logic;
pad : inout std_logic
);
end;
architecture rtl of iopad is
begin
inf : if INFER_PADS generate
giop0 : geniopad port map (d => d, en => en, q => q, pad => pad);
end generate;
ninf : if not INFER_PADS generate
atc25t : if TARGET_TECH = atc25 generate
p0 : atc25_iopad generic map (drive) port map (d => d, en => en, q => q, pad => pad);
end generate;
atc35t : if TARGET_TECH = atc35 generate
po : atc35_iopad generic map (drive) port map (d => d, en => en, q => q, pad => pad);
end generate;
fs90t : if TARGET_TECH = fs90 generate
po : fs90_iopad generic map (drive) port map (d => d, en => en, q => q, pad => pad);
end generate;
umc18t : if TARGET_TECH = umc18 generate
po : umc18_iopad generic map (drive) port map (d => d, en => en, q => q, pad => pad);
end generate;
end generate;
end;
-- bidirectional pad with schmitt trigger for I/O ports
-- (if available)
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_fs90.all;
use work.tech_umc18.all;
use work.tech_generic.all;
entity smiopad is
generic (drive : integer := 1);
port (
d : in std_logic;
en : in std_logic;
q : out std_logic;
pad : inout std_logic
);
end;
architecture rtl of smiopad is
begin
inf : if INFER_PADS generate
giop0 : geniopad port map (d => d, en => en, q => q, pad => pad);
end generate;
ninf : if not INFER_PADS generate
smiop1 : if TARGET_TECH = atc25 generate
p0 : atc25_iopad generic map (drive) port map (d => d, en => en, q => q, pad => pad);
end generate;
smiop2 : if TARGET_TECH = atc35 generate
p0 : atc35_iopad generic map (drive) port map (d => d, en => en, q => q, pad => pad);
end generate;
smiop3 : if TARGET_TECH = fs90 generate
p0 : fs90_smiopad generic map (drive) port map (d => d, en => en, q => q, pad => pad);
end generate;
smiop4 : if TARGET_TECH = umc18 generate
p0 : umc18_smiopad generic map (drive) port map (d => d, en => en, q => q, pad => pad);
end generate;
end generate;
end;
-- open-drain pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_fs90.all;
use work.tech_umc18.all;
use work.tech_generic.all;
entity odpad is
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end;
architecture rtl of odpad is
begin
inf : if INFER_PADS generate
godpad0 : genodpad port map (d => d, pad => pad);
end generate;
ninf : if not INFER_PADS generate
odp1 : if TARGET_TECH = atc25 generate
p0 : atc25_odpad generic map (drive) port map (d => d, pad => pad);
end generate;
odp2 : if TARGET_TECH = atc35 generate
p0 : atc35_odpad generic map (drive) port map (d => d, pad => pad);
end generate;
odp3 : if TARGET_TECH = fs90 generate
p0 : fs90_odpad generic map (drive) port map (d => d, pad => pad);
end generate;
odp4 : if TARGET_TECH = umc18 generate
p0 : umc18_odpad generic map (drive) port map (d => d, pad => pad);
end generate;
end generate;
end;
-- bi-directional open-drain
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_fs90.all;
use work.tech_umc18.all;
use work.tech_generic.all;
entity iodpad is
generic (drive : integer := 1);
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture rtl of iodpad is
begin
inf : if INFER_PADS generate
giodp0 : geniodpad port map (d => d, q => q, pad => pad);
end generate;
ninf : if not INFER_PADS generate
iodp1 : if TARGET_TECH = atc25 generate
p0 : atc25_iodpad generic map (drive) port map (d => d, q => q, pad => pad);
end generate;
iodp2 : if TARGET_TECH = atc35 generate
p0 : atc35_iodpad generic map (drive) port map (d => d, q => q, pad => pad);
end generate;
iodp3 : if TARGET_TECH = fs90 generate
p0 : fs90_iodpad generic map (drive) port map (d => d, q => q, pad => pad);
end generate;
iodp4 : if TARGET_TECH = umc18 generate
p0 : umc18_iodpad generic map (drive) port map (d => d, q => q, pad => pad);
end generate;
end generate;
end;
-- PCI output pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_generic.all;
entity pcioutpad is port (d : in std_logic; pad : out std_logic); end;
architecture rtl of pcioutpad is
begin
inf : if INFER_PADS generate
goutpad0 : genoutpad port map (d => d, pad => pad);
end generate;
ninf : if not INFER_PADS generate
op1 : if TARGET_TECH = atc25 generate
opx : atc25_pcioutpad port map (d => d, pad => pad);
end generate;
end generate;
end;
-- PCI tristate output pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_generic.all;
entity pcitoutpad is port (d, en : in std_logic; pad : out std_logic); end;
architecture rtl of pcitoutpad is
begin
inf : if INFER_PADS generate
giop0 : gentoutpadu port map (d => d, en => en, pad => pad);
end generate;
ninf : if not INFER_PADS generate
atc25t : if TARGET_TECH = atc25 generate
p0 : atc25_pcitoutpad port map (d => d, en => en, pad => pad);
end generate;
end generate;
end;
-- bidirectional pad
-- PCI bidir pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_generic.all;
entity pciiopad is
port (
d : in std_logic;
en : in std_logic;
q : out std_logic;
pad : inout std_logic
);
end;
architecture rtl of pciiopad is
begin
inf : if INFER_PADS generate
giop0 : geniopad port map (d => d, en => en, q => q, pad => pad);
end generate;
ninf : if not INFER_PADS generate
iop1 : if TARGET_TECH = atc25 generate
p0 : atc25_pciiopad port map (d => d, en => en, q => q, pad => pad);
end generate;
end generate;
end;
-- PCI bi-directional open-drain
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.tech_atc25.all;
use work.tech_atc35.all;
use work.tech_generic.all;
entity pciiodpad is
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture rtl of pciiodpad is
begin
inf : if INFER_PADS generate
giodp0 : geniodpad port map (d => d, q => q, pad => pad);
end generate;
ninf : if not INFER_PADS generate
iodp1 : if TARGET_TECH = atc25 generate
p0 : atc25_pciiodpad port map (d => d, q => q, pad => pad);
end generate;
end generate;
end;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/targetmdct.vhd | 1 | 36383 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: target
-- File: target.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: LEON target configuration package
------------------------------------------------------------------------------
-- 29.01.02 Configuration of DDM. LA
-- 13.03.02 MDCT added. APB masters incremented by 1 in AHB configuration, and
-- mdct address added in APB configuration.
library IEEE;
use IEEE.std_logic_1164.all;
package target is
type targettechs is (gen, virtex, atc35, atc25, fs90, umc18);
-- synthesis configuration
type syn_config_type is record
targettech : targettechs;
infer_ram : boolean; -- infer cache ram automatically
infer_regf : boolean; -- infer regfile automatically
infer_rom : boolean; -- infer boot prom automatically
infer_pads : boolean; -- infer pads automatically
infer_mult : boolean; -- infer multiplier automatically
gatedclk : boolean; -- select clocking strategy
rftype : integer; -- regfile implementation option
end record;
-- processor configuration
type multypes is (none, iterative, m32x8, m16x16, m32x16, m32x32);
type divtypes is (none, radix2);
type iu_config_type is record
nwindows : integer; -- # register windows (2 - 32)
multiplier : multypes; -- multiplier type
divider : divtypes; -- divider type
mac : boolean; -- multiply/accumulate
fpuen : integer range 0 to 1; -- FPU enable (integer due to synopsys limitations....sigh!)
cpen : boolean; -- co-processor enable
fastjump : boolean; -- enable fast jump address generation
icchold : boolean; -- enable fast branch logic
lddelay : integer range 1 to 2; -- # load delay cycles (1-2)
fastdecode : boolean; -- optimise instruction decoding (FPGA only)
watchpoints : integer range 0 to 4; -- # hardware watchpoints (0-4)
impl : integer range 0 to 15; -- IU implementation ID
version : integer range 0 to 15; -- IU version ID
end record;
-- FPU configuration
type fputype is (none, meiko, fpc); -- FPU type
type fpu_config_type is record
fpu : fputype; -- FPU type
fregs : integer; -- 32 for internal meiko, 0 for external FPC
version : integer range 0 to 7; -- FPU version ID
end record;
-- co-processor configuration
type cptype is (none, cpc); -- CP type
type cp_config_type is record
cp : cptype; -- Co-processor type
version : integer range 0 to 7; -- CP version ID
-- add your CP-specific configuration options here!!
end record;
-- cache configuration
type cache_config_type is record
icachesize : integer; -- size of I-cache in Kbytes
ilinesize : integer; -- # words per I-cache line
dcachesize : integer; -- size of D-cache in Kbytes
dlinesize : integer; -- # words per D-cache line
end record;
-- memory controller configuration
type mctrl_config_type is record
bus8en : boolean; -- enable 8-bit bus operation
bus16en : boolean; -- enable 16-bit bus operation
rawaddr : boolean; -- enable unlatched address option
end record;
type boottype is (memory, prom, dual);
type boot_config_type is record
boot : boottype; -- select boot source
ramrws : integer range 0 to 3; -- ram read waitstates
ramwws : integer range 0 to 3; -- ram write waitstates
sysclk : integer; -- cpu clock
baud : positive; -- UART baud rate
extbaud : boolean; -- use external baud rate setting
pabits : positive; -- internal boot-prom address bits
end record;
-- PCI configuration
type pcitype is (none, insilicon, esa, ahbtst); -- PCI core type
type pci_config_type is record
pcicore : pcitype; -- PCI core type
ahbmasters : integer; -- number of ahb master interfaces
ahbslaves : integer; -- number of ahb slave interfaces
arbiter : boolean; -- enable PCI arbiter
fixpri : boolean; -- use fixed arbitration priority
prilevels : integer; -- number of priority levels in arbiter
pcimasters : integer; -- number of PCI masters to be handled by arbiter
vendorid : integer; -- PCI vendor ID
deviceid : integer; -- PCI device ID
subsysid : integer; -- PCI subsystem ID
revisionid : integer; -- PCI revision ID
classcode : integer; -- PCI class code
pmepads : boolean; -- enable power down pads
p66pad : boolean; -- enable PCI66 pad
end record;
-- debug configuration
type debug_config_type is record
enable : boolean; -- enable debug port
uart : boolean; -- enable fast uart data to console
iureg : boolean; -- enable tracing of iu register writes
fpureg : boolean; -- enable tracing of fpu register writes
nohalt : boolean; -- dont halt on error
pclow : integer; -- set to 2 for synthesis, 0 for debug
end record;
-- AMBA configuration types
constant AHB_MST_MAX : integer := 4; -- maximum AHB masters
constant AHB_SLV_MAX : integer := 7; -- maximum AHB slaves
constant AHB_SLV_ADDR_MSB : integer := 4; -- MSB address bits to decode slaves
constant AHB_CACHE_MAX : integer := 4; -- maximum cacheability ranges
constant AHB_CACHE_ADDR_MSB : integer := 3; -- MSB address bits to decode cacheability
subtype ahb_range_addr_type is std_logic_vector(AHB_SLV_ADDR_MSB-1 downto 0);
subtype ahb_cache_addr_type is std_logic_vector(AHB_CACHE_ADDR_MSB-1 downto 0);
type ahb_slv_config_type is record
firstaddr : ahb_range_addr_type;
lastaddr : ahb_range_addr_type;
index : integer range 0 to AHB_SLV_MAX-1;
split : boolean;
enable : boolean;
end record;
type ahb_slv_config_vector is array (Natural Range <> ) of ahb_slv_config_type;
constant ahb_slv_config_void : ahb_slv_config_type :=
((others => '0'), (others => '0'), 0, false, false);
type ahb_cache_config_type is record
firstaddr : ahb_cache_addr_type;
lastaddr : ahb_cache_addr_type;
end record;
type ahb_cache_config_vector is array (Natural Range <> ) of ahb_cache_config_type;
constant ahb_cache_config_void : ahb_cache_config_type :=
((others => '0'), (others => '0'));
type ahb_config_type is record
masters : integer range 1 to AHB_MST_MAX;
defmst : integer range 0 to AHB_MST_MAX-1;
split : boolean; -- add support for SPLIT reponse
slvtable : ahb_slv_config_vector(0 to AHB_SLV_MAX-1);
cachetable : ahb_cache_config_vector(0 to AHB_CACHE_MAX-1);
end record;
constant APB_SLV_MAX : integer := 16; -- maximum APB slaves
constant APB_SLV_ADDR_BITS : integer := 10; -- address bits to decode APB slaves
subtype apb_range_addr_type is std_logic_vector(APB_SLV_ADDR_BITS-1 downto 0);
type apb_slv_config_type is record
firstaddr : apb_range_addr_type;
lastaddr : apb_range_addr_type;
index : integer;
enable : boolean;
end record;
type apb_slv_config_vector is array (Natural Range <> ) of apb_slv_config_type;
constant apb_slv_config_void : apb_slv_config_type :=
((others => '0'), (others => '0'), 0, false);
type apb_config_type is record
table : apb_slv_config_vector(0 to APB_SLV_MAX-1);
end record;
type irq_filter_type is (lvl0, lvl1, edge0, edge1);
type irq_filter_vec is array (0 to 31) of irq_filter_type;
type irq2type is record
enable : boolean; -- enable chained interrupt controller
channels : integer; -- number of additional interrupts (1 - 32)
filter : irq_filter_vec; -- irq filter definitions
end record;
type peri_config_type is record
cfgreg : boolean; -- enable LEON configuration register
ahbstat : boolean; -- enable AHB status register
wprot : boolean; -- enable RAM write-protection unit
wdog : boolean; -- enable watchdog
irq2cfg : irq2type; -- chained interrupt controller config
end record;
-- complete configuration record type
type config_type is record
synthesis : syn_config_type;
iu : iu_config_type;
fpu : fpu_config_type;
cp : cp_config_type;
cache : cache_config_type;
ahb : ahb_config_type;
apb : apb_config_type;
mctrl : mctrl_config_type;
boot : boot_config_type;
debug : debug_config_type;
pci : pci_config_type;
peri : peri_config_type;
end record;
----------------------------------------------------------------------------
-- Synthesis configurations
----------------------------------------------------------------------------
constant syn_atc25 : syn_config_type := (
targettech => atc25, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_atc35 : syn_config_type := (
targettech => atc35, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_gen : syn_config_type := (
targettech => gen, infer_pads => true,
infer_ram => true, infer_regf => true, infer_rom => true,
infer_mult => true, gatedclk => false, rftype => 1);
constant syn_virtex : syn_config_type := (
targettech => virtex, infer_pads => true,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => true, gatedclk => false, rftype => 1);
constant syn_virtex_blockprom : syn_config_type := (
targettech => virtex, infer_pads => true,
infer_ram => false, infer_regf => false, infer_rom => false,
infer_mult => true, gatedclk => false, rftype => 1);
constant syn_systel_asic : syn_config_type := (
targettech => atc25, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_fs90 : syn_config_type := (
targettech => fs90, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, gatedclk => false, rftype => 1);
constant syn_umc18 : syn_config_type := (
targettech => umc18, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
-- infer_multgates => false,
infer_mult => false, gatedclk => false, rftype => 1);
----------------------------------------------------------------------------
-- IU configurations
----------------------------------------------------------------------------
constant iu_std : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 0, impl => 0, version => 0);
constant iu_std_mac : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 0, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 0, impl => 0, version => 0);
constant iu_fpu : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 1, cpen => false, fastjump => false, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga : iu_config_type := (
nwindows => 8, multiplier => none, divider => none, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8 : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8_fpu : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => false,
fpuen => 1, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8_mac : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_fpga_v8_small : iu_config_type := (
nwindows => 8, multiplier => iterative, divider => radix2, mac => false,
fpuen => 0, cpen => false, fastjump => true, icchold => true, lddelay => 1,
fastdecode => true, watchpoints => 0, impl => 0, version => 0);
constant iu_atc25 : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 0, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 2, impl => 0, version => 0);
constant iu_atc25_fpu : iu_config_type := (
nwindows => 8, multiplier => m16x16, divider => radix2, mac => true,
fpuen => 1, cpen => false, fastjump => true, icchold => false, lddelay => 1,
fastdecode => false, watchpoints => 2, impl => 0, version => 0);
----------------------------------------------------------------------------
-- FPU configurations
----------------------------------------------------------------------------
constant fpu_none : fpu_config_type := (fpu => none, fregs => 0, version => 0);
constant fpu_meiko: fpu_config_type := (fpu => meiko, fregs => 32, version => 0);
constant fpu_fpc : fpu_config_type := (fpu => fpc, fregs => 0, version => 0);
----------------------------------------------------------------------------
-- CP configurations
----------------------------------------------------------------------------
constant cp_none : cp_config_type := (cp => none, version => 0);
constant cp_cpc : cp_config_type := (cp => cpc, version => 0);
----------------------------------------------------------------------------
-- cache configurations
----------------------------------------------------------------------------
constant cache_1k1k : cache_config_type := (
icachesize => 1, ilinesize => 4, dcachesize => 1, dlinesize => 4);
constant cache_2k1k : cache_config_type := (
icachesize => 2, ilinesize => 4, dcachesize => 1, dlinesize => 4);
constant cache_2k2k : cache_config_type := (
icachesize => 2, ilinesize => 4, dcachesize => 2, dlinesize => 4);
constant cache_2kl8_2kl4 : cache_config_type := (
icachesize => 2, ilinesize => 8, dcachesize => 2, dlinesize => 4);
constant cache_4k2k : cache_config_type := (
icachesize => 4, ilinesize => 8, dcachesize => 2, dlinesize => 4);
constant cache_1k4k : cache_config_type := (
icachesize => 1, ilinesize => 4, dcachesize => 4, dlinesize => 4);
constant cache_4k4k : cache_config_type := (
icachesize => 4, ilinesize => 4, dcachesize => 4, dlinesize => 4);
constant cache_8k8k : cache_config_type := (
icachesize => 8, ilinesize => 8, dcachesize => 8, dlinesize => 4);
----------------------------------------------------------------------------
-- Memory controller configurations
----------------------------------------------------------------------------
constant mctrl_std : mctrl_config_type := (
bus8en => true, bus16en => true, rawaddr => false);
constant mctrl_mem32 : mctrl_config_type := (
bus8en => false, bus16en => false, rawaddr => false);
constant mctrl_mem16 : mctrl_config_type := (
bus8en => false, bus16en => true, rawaddr => false);
----------------------------------------------------------------------------
-- boot configurations
----------------------------------------------------------------------------
constant boot_mem_25M : boot_config_type := (boot => memory, ramrws => 0,
ramwws => 0, sysclk => 24576000, baud => 38400, extbaud => false,
pabits => 8); -- 21.02.02 Booting system with 25 MHZ LA
constant boot_mem_33M : boot_config_type := (boot => memory, ramrws => 0,
ramwws => 0, sysclk => 33333333, baud => 38400, extbaud => false,
pabits => 8); -- 15.02.02 Booting system with 33.3 MHZ LA
constant boot_mem : boot_config_type := (boot => memory, ramrws => 0,
ramwws => 0, sysclk => 1000000, baud => 19200, extbaud => false,
pabits => 8);
constant boot_pmon : boot_config_type := (boot => prom, ramrws => 0,
ramwws => 0, sysclk => 24576000, baud => 38400, extbaud=> false,
pabits => 8);
constant boot_rdbmon : boot_config_type := (boot => prom, ramrws => 0,
ramwws => 0, sysclk => 24576000, baud => 38400, extbaud=> false,
pabits => 11);
constant boot_prom_xess16 : boot_config_type := (boot => prom, ramrws => 0,
ramwws => 0, sysclk => 25000000, baud => 38400, extbaud=> false,
pabits => 8);
----------------------------------------------------------------------------
-- PCI configurations
----------------------------------------------------------------------------
-- NOTE: 0x16E3 is ESA vendor ID - do NOT use without authorisation!!
-- NOTE: 0x1438 is ATMEL vendor ID - do NOT use without authorisation!!
constant pci_none : pci_config_type := (
pcicore => none, ahbmasters => 0, ahbslaves => 0,
arbiter => false, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_test : pci_config_type := (
pcicore => ahbtst, ahbmasters => 2, ahbslaves => 1,
arbiter => false, fixpri => true, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_insilicon : pci_config_type := (
pcicore => insilicon, ahbmasters => 2, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_esaif : pci_config_type := (
pcicore => esa, ahbmasters => 1, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_ahb_test : pci_config_type := (
pcicore => ahbtst, ahbmasters => 0, ahbslaves => 1,
arbiter => false, fixpri => true, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
constant pci_atc25 : pci_config_type := (
pcicore => ahbtst, ahbmasters => 2, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#16E3#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
-- In-Silicon PCI core in ATMEL configuration
constant pci_atmel : pci_config_type := (
pcicore => insilicon, ahbmasters => 2, ahbslaves => 1,
arbiter => true, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#1438#, deviceid => 16#0BAD#, subsysid => 16#0ACE#,
revisionid => 16#01#, classcode =>16#00000B#, pmepads => false,
p66pad => false);
----------------------------------------------------------------------------
-- Peripherals configurations
----------------------------------------------------------------------------
constant irq2none : irq2type := ( enable => false, channels => 32,
filter => (others => lvl0));
constant irq2chan4 : irq2type := ( enable => true, channels => 4,
filter => (lvl0, lvl1, edge0, edge1, others => lvl0));
constant peri_std : peri_config_type := (
cfgreg => true, ahbstat => true, wprot => true, wdog => true,
irq2cfg => irq2none);
constant peri_fpga : peri_config_type := (
cfgreg => true, ahbstat => false, wprot => false, wdog => false,
irq2cfg => irq2none);
constant peri_irq2 : peri_config_type := (
cfgreg => true, ahbstat => false, wprot => false, wdog => false,
irq2cfg => irq2chan4);
----------------------------------------------------------------------------
-- Debug configurations
----------------------------------------------------------------------------
constant debug_none : debug_config_type := ( enable => false, uart => false,
iureg => false, fpureg => false, nohalt => false, pclow => 2);
constant debug_disas : debug_config_type := ( enable => true, uart => false,
iureg => false, fpureg => false, nohalt => false, pclow => 2);
constant debug_msp : debug_config_type := ( enable => true, uart => false,
iureg => false, fpureg => false, nohalt => true, pclow => 2);
constant debug_uart : debug_config_type := ( enable => true, uart => true,
iureg => false, fpureg => false, nohalt => false, pclow => 0);
constant debug_fpu : debug_config_type := ( enable => true, uart => true,
iureg => false, fpureg => true, nohalt => false, pclow => 2);
constant debug_all : debug_config_type := ( enable => true, uart => true,
iureg => true, fpureg => true, nohalt => false, pclow => 0);
----------------------------------------------------------------------------
-- Amba AHB configurations
----------------------------------------------------------------------------
-- standard slave config
constant ahbslvcfg_std : ahb_slv_config_vector(0 to AHB_SLV_MAX-1) := (
-- first last index split enable function HADDR[31:28]
("0000", "0111", 0, false, true), -- memory controller, 0x0- 0x7
("1000", "1000", 1, false, true), -- APB bridge, 256 MB 0x8- 0x8
others => ahb_slv_config_void);
-- AHB test slave config
constant ahbslvcfg_test : ahb_slv_config_vector(0 to AHB_SLV_MAX-1) := (
-- first last index split enable function HADDR[31:28]
("0000", "0111", 0, false, true), -- memory controller, 0x0- 0x7
("1000", "1000", 1, false, true), -- APB bridge, 128 MB 0x8- 0x8
("1010", "1010", 2, true, true), -- AHB test module 0xA- 0xA
("1100", "1111", 3, false, true), -- PCI initiator 0xC- 0xF
others => ahb_slv_config_void);
-- PCI slave config
constant ahbslvcfg_pci : ahb_slv_config_vector(0 to AHB_SLV_MAX-1) := (
-- first last index split enable function HADDR[31:28]
("0000", "0111", 0, false, true), -- memory controller, 0x0- 0x7
("1000", "1000", 1, false, true), -- APB bridge, 128 MB 0x8- 0x8
("1010", "1111", 2, false, true), -- PCI initiator 0xA- 0xF
others => ahb_slv_config_void);
-- standard cacheability config
constant ahbcachecfg_std : ahb_cache_config_vector(0 to AHB_CACHE_MAX-1) := (
-- first last function HADDR[31:29]
("000", "000"), -- PROM area 0x0- 0x0
("010", "011"), -- RAM area 0x2- 0x3
others => ahb_cache_config_void);
-- standard config record
constant ahb_std : ahb_config_type := (
masters => 3, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_std, cachetable => ahbcachecfg_std);
-- FPGA config record
constant ahb_fpga : ahb_config_type := (
masters => 3, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_std, cachetable => ahbcachecfg_std);
-- Phoenix PCI core config record (uses two AHB master instefaces)
constant ahb_insilicon_pci : ahb_config_type := (
masters => 5, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_pci, cachetable => ahbcachecfg_std);
-- ESTEC PCI core config record (uses one AHB master insteface)
constant ahb_esa_pci : ahb_config_type := (
masters => 4, defmst => 0, split => false, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_pci, cachetable => ahbcachecfg_std);
-- AHB test config
constant ahb_test : ahb_config_type := (
masters => 5, defmst => 0, split => true, -- masters increased by 2 for DDM & mdct. LA
slvtable => ahbslvcfg_test, cachetable => ahbcachecfg_std);
----------------------------------------------------------------------------
-- Amba APB configurations
----------------------------------------------------------------------------
-- standard config
constant apbslvcfg_std : apb_slv_config_vector(0 to APB_SLV_MAX-1) := (
-- first last index enable function PADDR[9:0]
( "0000000000", "0000001000", 0, true), -- memory controller, 0x00 - 0x08
( "0000001100", "0000010000", 1, true), -- AHB status reg., 0x0C - 0x10
( "0000010100", "0000011000", 2, true), -- cache controller, 0x14 - 0x18
( "0000011100", "0000100000", 3, true), -- write protection, 0x1C - 0x20
( "0000100100", "0000100100", 4, true), -- config register, 0x24 - 0x24
( "0001000000", "0001101100", 5, true), -- timers, 0x40 - 0x6C
( "0001110000", "0001111100", 6, true), -- uart1, 0x70 - 0x7C
( "0010000000", "0010001100", 7, true), -- uart2, 0x80 - 0x8C
( "0010010000", "0010011100", 8, true), -- interrupt ctrl 0x90 - 0x9C
( "0010100000", "0010101100", 9, true), -- I/O port 0xA0 - 0xAC
( "0100000000", "0111111100", 10, false), -- PCI configuration 0x100 - 0x1FC
( "1000000000", "1000011000", 11, true), -- ddm 0x200 - 0x218
( "1100000000", "1100011000", 12, true), -- mdct 0x300 - 0x318
others => apb_slv_config_void);
-- standard config with secondary interrupt controller
constant apbslvcfg_irq2 : apb_slv_config_vector(0 to APB_SLV_MAX-1) := (
-- first last index enable function PADDR[9:0]
( "0000000000", "0000001000", 0, true), -- memory controller, 0x00 - 0x08
( "0000001100", "0000010000", 1, true), -- AHB status reg., 0x0C - 0x10
( "0000010100", "0000011000", 2, true), -- cache controller, 0x14 - 0x18
( "0000011100", "0000100000", 3, true), -- write protection, 0x1C - 0x20
( "0000100100", "0000100100", 4, true), -- config register, 0x24 - 0x24
( "0001000000", "0001101100", 5, true), -- timers, 0x40 - 0x6C
( "0001110000", "0001111100", 6, true), -- uart1, 0x70 - 0x7C
( "0010000000", "0010001100", 7, true), -- uart2, 0x80 - 0x8C
( "0010010000", "0010011100", 8, true), -- interrupt ctrl 0x90 - 0x9C
( "0010100000", "0010101100", 9, true), -- I/O port 0xA0 - 0xAC
( "0010110000", "0010111100", 10, true), -- 2nd interrupt ctrl 0xB0 - 0xBC
( "1000000000", "1000011000", 11, true), -- ddm 0x200 - 0x218
( "1100000000", "1100011000", 12, true), -- mdct 0x300 - 0x318
others => apb_slv_config_void);
-- PCI config
constant apbslvcfg_pci : apb_slv_config_vector(0 to APB_SLV_MAX-1) := (
-- first last index enable function PADDR[9:0]
( "0000000000", "0000001000", 0, true), -- memory controller, 0x00 - 0x08
( "0000001100", "0000010000", 1, true), -- AHB status reg., 0x0C - 0x10
( "0000010100", "0000011000", 2, true), -- cache controller, 0x14 - 0x18
( "0000011100", "0000100000", 3, true), -- write protection, 0x1C - 0x20
( "0000100100", "0000100100", 4, true), -- config register, 0x24 - 0x24
( "0001000000", "0001101100", 5, true), -- timers, 0x40 - 0x6C
( "0001110000", "0001111100", 6, true), -- uart1, 0x70 - 0x7C
( "0010000000", "0010001100", 7, true), -- uart2, 0x80 - 0x8C
( "0010010000", "0010011100", 8, true), -- interrupt ctrl 0x90 - 0x9C
( "0010100000", "0010101100", 9, true), -- I/O port 0xA0 - 0xAC
( "0100000000", "0111111100", 10, true), -- PCI configuration 0x100- 0x1FC
( "1000000000", "1011111100", 11, true), -- PCI arbiter 0x200- 0x2FC
others => apb_slv_config_void);
constant apb_std : apb_config_type := (table => apbslvcfg_std);
constant apb_irq2 : apb_config_type := (table => apbslvcfg_irq2);
constant apb_pci : apb_config_type := (table => apbslvcfg_pci);
----------------------------------------------------------------------------
-- Pre-defined LEON configurations
----------------------------------------------------------------------------
-- VIRTEX, 2 + 2 Kbyte cache, fpu
constant virtex_2k2k_25M_fpu : config_type := (
synthesis => syn_virtex, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_25M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 4 + 4 Kbyte cache, mul/div, fpu, 25M
constant fpga_4k4k_v8_fpu_33M : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_4k4k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_33M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache 25 MHz
constant fpga_2k2k_25M : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_25M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache 33.3 MHz
constant fpga_2k2k_33M : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_33M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache
constant fpga_2k2k : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, mul/div
constant fpga_2k2k_v8 : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, secondary irq controller (test only)
constant fpga_2k2k_irq2 : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_irq2, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_irq2);
-- Any FPGA, 2 + 2 Kbyte cache, inferred boot-prom
constant fpga_2k2k_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, inferred boot-prom, mul/div
constant fpga_2k2k_v8_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 4 + 4 Kbyte cache, mul/div, fpu
constant fpga_4k4k_v8_fpu : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_4k4k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem_25M, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 4 + 4 Kbyte cache, inferred boot-prom, mul/div, fpu
constant fpga_4k4k_v8_fpu_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_4k4k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- Any FPGA, 2 + 2 Kbyte cache, inferred boot-prom, mul/div, MAC
constant fpga_2k2k_v8_mac_softprom : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8_mac, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- VIRTEX, 2 + 2 Kbyte cache, hard boot-prom
constant virtex_2k2k_blockprom : config_type := (
synthesis => syn_virtex_blockprom, iu => iu_fpga_v8_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- VIRTEX, 2 + 1 Kbyte cache, hard boot-prom with rdbmon
constant virtex_2k1k_rdbmon : config_type := (
synthesis => syn_virtex_blockprom, iu => iu_fpga, fpu => fpu_none, cp => cp_none,
cache => cache_2k1k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_rdbmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- VIRTEX, 2 + 2 Kbyte cache, hard boot-prom, mul/div
constant virtex_2k2k_v8_blockprom : config_type := (
synthesis => syn_virtex_blockprom, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_fpga, apb => apb_std, mctrl => mctrl_std,
boot => boot_pmon, debug => debug_disas, pci => pci_none,
peri => peri_fpga);
-- synthesis targetting ATC25 asic lib
constant gen_atc25 : config_type := (
synthesis => syn_atc25, iu => iu_atc25, fpu => fpu_none, cp => cp_none,
cache => cache_8k8k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting ATC25 asic lib, serial Meiko FPU
constant gen_atc25_meiko : config_type := (
synthesis => syn_atc25, iu => iu_atc25_fpu, fpu => fpu_meiko, cp => cp_none,
cache => cache_8k8k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting ATC25 asic lib, parallel FPU
constant gen_atc25_fpc : config_type := (
synthesis => syn_atc25, iu => iu_atc25_fpu, fpu => fpu_fpc, cp => cp_none,
cache => cache_8k8k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting ATC25 asic lib + Insilicon PCI core
constant gen_atc25_insilicon_pci : config_type := (
synthesis => syn_atc25, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_4k4k, ahb => ahb_insilicon_pci, apb => apb_pci,
mctrl => mctrl_std, boot => boot_mem, debug => debug_disas, pci => pci_atmel,
peri => peri_std);
-- simulatiom with Insilicon PCI core
constant gen_insilicon_pci : config_type := (
synthesis => syn_gen, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_insilicon_pci, apb => apb_pci,
mctrl => mctrl_std, boot => boot_mem, debug => debug_disas, pci => pci_atmel,
peri => peri_std);
-- synthesis targetting ATC35 asic lib, synopsys
constant gen_atc35 : config_type := (
synthesis => syn_atc35, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_4k4k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- Systel FPGA configuration
constant systel_fpga : config_type := (
synthesis => syn_gen, iu => iu_fpga_v8, fpu => fpu_none, cp => cp_none,
cache => cache_1k1k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- Systel ASIC configuration
constant systel_asic : config_type := (
synthesis => syn_systel_asic, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_1k1k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting UMC FS90A/B asic lib
constant gen_fs90 : config_type := (
synthesis => syn_fs90, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_2k2k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
-- synthesis targetting UMC18 asic lib, synopsys + AMBIT
constant gen_umc18 : config_type := (
synthesis => syn_umc18, iu => iu_std, fpu => fpu_none, cp => cp_none,
cache => cache_4k4k, ahb => ahb_std, apb => apb_std, mctrl => mctrl_std,
boot => boot_mem, debug => debug_disas, pci => pci_none,
peri => peri_std);
end;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/VFLOAT_2015/General Modules/parameterized modules/parameterized_shifter/parameterized_shifter.vhd | 2 | 5074 | --======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized variable shifter --
----------------------------------------------------------
entity parameterized_shifter is
generic
(
bits : integer := 12;
shift_bits : integer := 8;
direction : std_logic := '0' --0=right,1=left
);
port
(
--inputs
I : in std_logic_vector(bits-1 downto 0);
S : in std_logic_vector(shift_bits-1 downto 0);
FILL : in std_logic;
--outputs
O : out std_logic_vector(bits-1 downto 0)
);
end parameterized_shifter;
----------------------------------------------------------
-- Parameterized variable shifter --
----------------------------------------------------------
architecture parameterized_shifter_arch of parameterized_shifter is
--CONSTANTS
constant rows : integer := ceil_log2(bits);
--TYPE
type pipe is array (0 to rows) of std_logic_vector(bits-1 downto 0);
--SIGNALS
signal zeros : std_logic_vector(bits-1 downto 0) := (others => '0');
signal truncate : std_logic_vector(rows-1 downto 0) := (others => '0');
signal shift : integer := 0;
signal tmp : integer := bits;
signal im : pipe; --intermediate signals
begin
shift <= conv_integer(S);
-- need_shift: if(shift < tmp) generate
truncate <= conv_std_logic_vector(shift, rows);
im(0) <= I;
over_rows : for x in 0 to rows-1 generate --iterate over rows
row : parameterized_variable_shifter_row
generic map
(
bits => bits,
row_number => x,
direction => direction
)
port map
(
--inputs
I => im(x),
S => truncate(x),
FILL => fill,
--outputs
O => im(x+1)
);
end generate;--rows
-- O <= im(rows);
-- end generate;
O <= (others => '0') when (shift >= tmp) else im(rows);
-- all_zeros: if(shift >= tmp) generate
-- O(bits-1 downto 0) <= (others => '0');
-- end generate;
end parameterized_shifter_arch; -- end of architecture
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.3.7/leon/fp.vhd | 3 | 32126 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: fp
-- File: fp.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Parallel floating-point co-processor interface
-- The interface allows any number of parallel execution unit
-- As an example, two Meiko FPUs and two FMOVE units have been attached
------------------------------------------------------------------------------
-- FPU support unit - performs FMOVS, FNEGS, FABSS
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.conv_integer;
use work.iface.all;
entity fpaux is
port (
rst : in std_logic; -- Reset
clk : in std_logic; -- clock
eui : in cp_unit_in_type; -- inputs
euo : out cp_unit_out_type -- outputs
);
end;
architecture rtl of fpaux is
type reg_type is record
op : std_logic_vector (31 downto 0); -- operand
ins : std_logic_vector (1 downto 0); -- operand
end record;
signal r, rin : reg_type;
begin
comb: process(rst, eui, r)
variable rv : reg_type;
variable ready : std_logic;
variable sign : std_logic;
begin
rv := r;
if eui.start = '1' then rv.ins := eui.opcode(3 downto 2); end if;
if eui.load = '1' then rv.op := eui.op2(63 downto 32); end if;
case r.ins is
when "00" => sign := r.op(31); -- fmovs
when "01" => sign := not r.op(31); -- fnegs
when others => sign := '0'; -- fabss
end case;
euo.res(63 downto 29) <= sign & "000" & r.op(30 downto 0);
euo.res(28 downto 0) <= (others => '0');
euo.busy <= '0';
euo.exc <= (others => '0');
euo.cc <= (others => '0');
rin <= rv;
end process;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.conv_integer;
use work.config.all;
use work.iface.all;
use work.sparcv8.all;
use work.ramlib.all;
use work.fpulib.all;
-- pragma translate_off
library MMS;
use MMS.stdioimp.all;
use STD.TEXTIO.all;
use work.debug.all;
-- pragma translate_on
entity fp is
port (
rst : in std_logic; -- Reset
clk : in clk_type; -- main clock
iuclk : in clk_type; -- gated IU clock
holdn : in std_logic; -- pipeline hold
xholdn : in std_logic; -- pipeline hold
cpi : in cp_in_type;
cpo : out cp_out_type
);
end;
architecture rtl of fp is
constant EUTYPES : integer := 1; -- number of execution unit types
--constant EUTYPES : integer := 1; -- number of execution unit types
constant EU1NUM : integer := 2; -- number of execution unit 1 types
constant EU2NUM : integer := 1; -- number of execution unit 2 types
constant EUMAX : integer := 2; -- maximum number of any execution unit
--constant EUTOT : integer := 2; -- total number of execution units
constant EUTOT : integer := 2; -- total number of execution units
subtype euindex is integer range 0 to EUMAX-1;
subtype eumindex is integer range 0 to EUTOT-1;
subtype eutindex is integer range 0 to EUTYPES-1;
-- array to define how many execution units of each type
type euconf_arr is array (0 to 2) of euindex; -- one more than necessay to avoid modeltech bug
constant euconf : euconf_arr := (EU1NUM-1, EU2NUM-1,0);
--constant euconf : euconf_arr := (EU1NUM,1);
type eu_fifo_arr is array (0 to EUTOT-1) of eutindex;
type eu_fifo_type is record
first : eumindex;
last : eumindex;
fifo : eu_fifo_arr;
end record;
type euq_type is record
first : euindex;
last : euindex;
end record;
type euq_arr is array (0 to EUTYPES-1) of euq_type;
type rfi_type is record
raddr1 : std_logic_vector (3 downto 0);
raddr2 : std_logic_vector (3 downto 0);
waddr : std_logic_vector (3 downto 0);
wdata : std_logic_vector (63 downto 0);
wren : std_logic_vector(1 downto 0);
end record;
type rfo_type is record
rdata1 : std_logic_vector (63 downto 0);
rdata2 : std_logic_vector (63 downto 0);
end record;
type cpins_type is (none, cpop, load, store);
type pl_ctrl is record -- pipeline control record
cpins : cpins_type; -- CP instruction
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wrcc : std_logic; -- write CP condition codes
acsr : std_logic; -- access CP control register
first : euindex;
end record;
type unit_status_type is (exception, free, started, ready);
type unit_ctrl is record -- execution unit control record
status : unit_status_type; -- unit status
rs1 : std_logic_vector (4 downto 0); -- destination register
rs2 : std_logic_vector (4 downto 0); -- destination register
rd : std_logic_vector (4 downto 0); -- destination register
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- will write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wb : std_logic; -- result being written back
wrcc : std_logic; -- will write CP condition codes
rst : std_logic; -- reset register
pc : std_logic_vector (31 downto PCLOW); -- program counter
inst : std_logic_vector (31 downto 0); -- instruction
end record;
type csr_type is record -- CP status register
cc : std_logic_vector (1 downto 0); -- condition codes
aexc : std_logic_vector (4 downto 0); -- exception codes
cexc : std_logic_vector (4 downto 0); -- exception codes
tem : std_logic_vector (4 downto 0); -- trap enable mask
rd : std_logic_vector (1 downto 0); -- rounding mode
tt : std_logic_vector (2 downto 0); -- trap type
end record;
type execstate is (nominal, excpend, exception);
type reg_type is record -- registers clocked with pipeline
eufirst : euindex;
eulast : euindex;
sdep : std_logic; -- data dependency ex/me/wr
eut : integer range 0 to EUTYPES-1; -- type EU to start
eui : integer range 0 to EUMAX-1; -- index EU to start
start : std_logic; -- start EU
weut : integer range 0 to EUTYPES-1; -- write stage eut
weui : integer range 0 to EUMAX-1; -- write stage eui
end record;
type regx_type is record -- registers clocked continuously
res : std_logic_vector (63 downto 0); -- write stage result
waddr : std_logic_vector (3 downto 0); -- write stage dest
wren : std_logic_vector (1 downto 0); -- write stage regfile write enable
csr : csr_type; -- co-processor status register
start : std_logic; -- start EU
starty : std_logic; -- start EU
startx : std_logic; -- start EU
holdn : std_logic;
state : execstate; -- using rs1
end record;
type unit_ctrl_arr is array (0 to EUMAX-1) of unit_ctrl;
type unit_ctrl_arr_arr is array (0 to EUTYPES-1) of unit_ctrl_arr;
type eui_arr is array (0 to EUMAX-1) of cp_unit_in_type;
type euo_arr is array (0 to EUMAX-1) of cp_unit_out_type;
type eui_arr_arr is array (0 to EUTYPES) of eui_arr;
type euo_arr_arr is array (0 to EUTYPES) of euo_arr;
signal vcc, gnd : std_logic;
signal rfi : rfi_type;
signal rfo : rfo_type;
signal ex, exin, me, mein, wr, wrin : pl_ctrl;
signal r, rin : reg_type;
signal rx, rxin : regx_type;
signal eui : eui_arr_arr;
signal euo : euo_arr_arr;
signal eu, euin : unit_ctrl_arr_arr;
signal euq, euqin : euq_arr;
signal euf, eufin : eu_fifo_type;
component fpaux
port (
rst : in std_logic; -- Reset
clk : in std_logic; -- clock
eui : in cp_unit_in_type; -- inputs
euo : out cp_unit_out_type -- outputs
);
end component;
function ldcheck (rdin : std_logic_vector; ldd : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) or
((eu.rreg1 = '1') and (rd = eu.rs1)) or
((eu.rreg2 = '1') and (rd = eu.rs2))
then lock := '1'; end if;
if (ldd = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd)) or
((eu.rreg1 = '1') and ((rd(4 downto 1) & '1') = eu.rs1)) or
((eu.rreg2 = '1') and ((rd(4 downto 1) & '1') = eu.rs2))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function stcheck (rdin : std_logic_vector; std : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) then lock := '1'; end if;
if (std = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function srccheck (rsin : std_logic_vector; dbl : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rs : std_logic_vector(4 downto 0);
begin
lock := '0'; rs := rsin;
if (eu.wreg = '1') and (rs(4 downto 1) = eu.rd(4 downto 1)) then
if ((dbl or eu.rdd) = '1') or (rs(0) = eu.rd(0)) then lock := '1'; end if;
end if;
return(lock);
end;
function ddepcheck (rs1, rs2 : std_logic_vector;
rreg1, rreg2, rs1d, rs2d : std_logic; eu : unit_ctrl_arr_arr;
euo : euo_arr_arr) return std_logic is
variable ddep : std_logic;
variable r1, r2 : std_logic_vector(4 downto 0);
begin
ddep := '0'; r1 := rs1; r2 := rs2;
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
if (eu(i)(j).status = started) or (eu(i)(j).status = ready) then
if rreg1 = '1' then ddep := ddep or srccheck(r1, rs1d, eu(i)(j)); end if;
if rreg2 = '1' then ddep := ddep or srccheck(r2, rs2d, eu(i)(j)); end if;
end if;
end loop;
end loop;
return(ddep);
end;
begin
vcc <= '1'; gnd <= '1';
-- instruction decoding
pipeline : process(cpi, ex, me, wr, eu, euin, r, rx, rfi, rfo, holdn, xholdn,
euo, euf, euq, rst)
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opc : std_logic_vector(8 downto 0);
variable stdata : std_logic_vector(31 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable ctrl : pl_ctrl;
variable ldlock : std_logic;
variable wren : std_logic_vector(1 downto 0);
variable waddr : std_logic_vector(3 downto 0);
variable rtaddr : std_logic_vector(3 downto 0);
variable wrdata : std_logic_vector(63 downto 0);
variable rtdata : std_logic_vector(63 downto 0);
variable rv : reg_type;
variable rxv : regx_type;
variable euv : unit_ctrl_arr_arr;
variable euqv : euq_arr;
variable euiv : eui_arr_arr;
variable eufv : eu_fifo_type;
variable euti : eumindex;
variable euqi : euindex;
variable ddep : std_logic;
variable cpexc : std_logic;
variable fpill : std_logic;
variable ccv : std_logic;
variable qne : std_logic;
variable op1 : std_logic_vector (63 downto 0); -- operand1
variable op2 : std_logic_vector (63 downto 0); -- operand2
variable opcode : std_logic_vector (9 downto 0); -- FP opcode
begin
-------------------------------------------------------------
-- decode stage
-------------------------------------------------------------
op := cpi.dinst(31 downto 30);
op3 := cpi.dinst(24 downto 19);
opc := cpi.dinst(13 downto 5);
rs1 := cpi.dinst(18 downto 14);
rs2 := cpi.dinst(4 downto 0);
rd := cpi.dinst(29 downto 25);
rv := r; rxv := rx; ctrl.first := ex.first;
ctrl.cpins := none; ctrl.wreg := '0'; ctrl.rdd := '0';
ctrl.wrcc := '0'; ctrl.acsr := '0'; ldlock := '0';
ctrl.rreg1 := '0'; ctrl.rreg2 := '0';
ctrl.rs1d := '0'; ctrl.rs2d := '0'; fpill := '0';
stdata := (others => '-'); wren := "00"; cpexc := '0';
ccv := '0'; rv.start := '0';
rv.weut := r.eut; rv.weui := r.eui;
rxv.start := '0'; rv.eut := 0; rv.eui := 0; rv.sdep := '0';
euv := eu; euqv := euq; eufv := euf;
euti := euf.fifo(euf.last); euqi := euq(euti).last;
if (euf.last /= euf.first) or (eu(euti)(euqi).status = exception)
then qne := '1'; else qne := '0'; end if;
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
euiv(i)(j).opcode := cpi.ex.inst(19) & cpi.ex.inst(13 downto 5);
euiv(i)(j).start := '0'; euiv(i)(j).load := '0';
euiv(i)(j).flush := eu(i)(j).rst or euin(i)(j).rst;
euv(i)(j).wb := '0';
euv(i)(j).rst := not rst;
if (eu(i)(j).status = started) and (euo(i)(j).busy = '0') then
euv(i)(j).status := ready;
end if;
if (eu(i)(j).status > free) then
ccv := ccv or eu(i)(j).wrcc;
end if;
end loop;
end loop;
-- decode CP instructions
case op is
when FMT3 =>
case op3 is
when FPOP1 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wreg := '1';
case opc is
when FMOVS | FABSS | FNEGS => ctrl.rreg2 := '1';
when FITOS | FSTOI => ctrl.rreg2 := '1';
when FITOD | FSTOD => ctrl.rreg2 := '1'; ctrl.rdd := '1';
when FDTOI | FDTOS => ctrl.rreg2 := '1'; ctrl.rs2d := '1';
when FSQRTS => ctrl.rreg2 := '1';
when FSQRTD => ctrl.rreg2 := '1'; ctrl.rs2d := '1'; ctrl.rdd := '1';
when FADDS | FSUBS | FMULS | FDIVS =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
when FADDD | FSUBD | FMULD | FDIVD =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1'; ctrl.rs1d := '1';
ctrl.rs2d := '1'; ctrl.rdd := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when FPOP2 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wrcc := '1';
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
case opc is
when FCMPD | FCMPED =>
ctrl.rs1d := '1'; ctrl.rs2d := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when others => null;
end case;
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(ex.wreg = '1')
then
if (ctrl.rreg1 = '1') and
(rs1(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs1d or ex.rdd) = '1') or (rs1(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
if (ctrl.rreg2 = '1') and
(rs2(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs2d or ex.rdd) = '1') or (rs2(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
end if;
when LDST =>
case op3 is
when LDF | LDDF =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.rdd := op3(1) and op3(0);
ctrl.cpins := load; ctrl.wreg := '1';
for i in 0 to EUTYPES-1 loop -- dst interlock
for j in 0 to euconf(i) loop
ldlock := ldlock or ldcheck(rd, ctrl.rdd, euin(i)(j));
end loop;
end loop;
end if;
when STF | STDF =>
-- check for CP register dependencies
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and
((rd = cpi.ex.inst(29 downto 25)) or
((rd(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(ex.rdd = '1')))
then ldlock := '1'; end if;
if rx.state = nominal then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
ldlock := ldlock or stcheck(rd, (op3(1) and op3(0)), euin(i)(j));
end loop;
end loop;
end if;
if (ldlock = '0') then ctrl.cpins := store; end if;
when STFSR | LDFSR =>
if (rx.state = exception) and (op3 = LDFSR) then
rxv.state := excpend; rxv.csr.tt := "100";
else
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and (op3 = STFSR) and (ex.acsr = '1')
then ldlock := '1'; end if;
if (rx.state = nominal) then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
if eu(i)(j).status > free then ldlock := '1'; end if;
end loop;
end loop;
end if;
end if;
-- FIX ME - add check for not yet commited cpins in pipeline
if (ldlock = '0') then
ctrl.acsr := '1';
if op3 = STFSR then ctrl.cpins := store;
else ctrl.cpins := load; end if;
end if;
when STDFQ =>
if (rx.state = nominal) then
rxv.state := excpend; rxv.csr.tt := "100";
else ctrl.cpins := store; end if;
when others => null;
end case;
when others => null;
end case;
if ((cpi.flush or cpi.dtrap or cpi.dannul) = '1') then
ctrl.cpins := none;
rxv.state := rx.state; rxv.csr.tt := rx.csr.tt;
end if;
-------------------------------------------------------------
-- execute stage
-------------------------------------------------------------
-- generate regfile addresses
if holdn = '0' then
op := cpi.me.inst(31 downto 30);
rd := cpi.me.inst(29 downto 25);
op3 := cpi.me.inst(24 downto 19);
rs1 := cpi.me.inst(18 downto 14);
rs2 := cpi.me.inst(4 downto 0);
else
op := cpi.ex.inst(31 downto 30);
rd := cpi.ex.inst(29 downto 25);
op3 := cpi.ex.inst(24 downto 19);
rs1 := cpi.ex.inst(18 downto 14);
rs2 := cpi.ex.inst(4 downto 0);
end if;
if (op = LDST) and (op3(2) = '1') then rs1 := rd; end if;
rfi.raddr1 <= rs1(4 downto 1); rfi.raddr2 <= rs2(4 downto 1);
cpo.ldlock <= ldlock;
op1 := rfo.rdata1; op2 := rfo.rdata2;
-- generate store data
if (cpi.ex.inst(20 downto 19) = "10") then -- STDFQ
if (cpi.ex.cnt /= "10") then stdata := eu(euti)(euqi).pc;
else stdata := eu(euti)(euqi).inst; end if;
elsif ((cpi.ex.inst(25) = '0') and (cpi.ex.cnt /= "10")) then -- STF/STDF
stdata := op1(63 downto 32);
else stdata := op1(31 downto 0); end if;
if (ex.cpins = store) and (ex.acsr = '1') then -- STFSR
stdata := rx.csr.rd & "00" & rx.csr.tem & "000" & FPUVER &
rx.csr.tt & qne & '0' & rx.csr.cc & rx.csr.aexc & rx.csr.cexc;
end if;
cpo.data <= stdata;
-- check for source operand dependency with scheduled instructions
if (ex.cpins = cpop) then
rv.sdep := ddepcheck(cpi.ex.inst(18 downto 14), cpi.ex.inst(4 downto 0),
ex.rreg1, ex.rreg2, ex.rs1d, ex.rs2d, eu, euo);
end if;
-- select execution unit type
if (cpi.ex.inst(12 downto 9) = "0000") and (EUTYPES > 1) then
rv.eut := EUTYPES-1; -- use exection unit 1
else
rv.eut := 0; -- use exection unit 0
end if;
-- check if an execution unit is available
if (ex.cpins = cpop) and (holdn = '1') and (cpi.flush = '0') then
rv.eui := euq(rv.eut).first;
ccv := ccv or ex.wrcc;
if (rv.sdep = '0') and (eu(rv.eut)(euq(rv.eut).first).status = free)
then
rxv.start := '1';
euiv(rv.eut)(rv.eui).start := '1';
euv(rv.eut)(rv.eui).status := started;
euv(rv.eut)(rv.eui).rd := cpi.ex.inst(29 downto 25);
euv(rv.eut)(rv.eui).rs1 := cpi.ex.inst(18 downto 14);
euv(rv.eut)(rv.eui).rs2 := cpi.ex.inst(4 downto 0);
euv(rv.eut)(rv.eui).wreg := ex.wreg;
euv(rv.eut)(rv.eui).rreg1 := ex.rreg1;
euv(rv.eut)(rv.eui).rreg2 := ex.rreg2;
euv(rv.eut)(rv.eui).rs1d := ex.rs1d;
euv(rv.eut)(rv.eui).rs2d := ex.rs2d;
euv(rv.eut)(rv.eui).rdd := ex.rdd;
euv(rv.eut)(rv.eui).wrcc := ex.wrcc;
else rxv.holdn := '0'; rv.start := '1'; end if;
ctrl.first := euf.first;
eufv.fifo(euf.first) := rv.eut;
if euq(rv.eut).first = euconf(rv.eut) then euqv(rv.eut).first := 0;
else euqv(rv.eut).first := euqv(rv.eut).first + 1; end if;
if euf.first = (EUTOT-1) then eufv.first := 0;
else eufv.first := eufv.first + 1; end if;
end if;
-------------------------------------------------------------
-- memory stage
-------------------------------------------------------------
ddep := ddepcheck(cpi.me.inst(18 downto 14), cpi.me.inst(4 downto 0),
me.rreg1, me.rreg2, me.rs1d, me.rs2d, eu, euo);
euiv(r.eut)(r.eui).load := rx.start or rx.starty;
if (rx.holdn = '0') and (xholdn = '1') and (cpi.flush = '0') and
((r.sdep and ddep) = '0') and (euo(r.eut)(euq(r.eut).first).busy = '0')
then
euiv(r.eut)(r.eui).start := not rx.startx;
euiv(r.eut)(r.eui).opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
end if;
if (rx.holdn = '0') and (cpi.flush = '0') and
(not ((r.sdep = '1') and (ddep = '1'))) and
((eu(r.eut)(r.eui).status <= free) or
(euin(r.eut)(r.eui).wb = '1'))
then
euiv(r.eut)(r.eui).load := rx.starty;
euiv(r.eut)(r.eui).start := not (rx.starty or rx.startx);
if eu(r.eut)(r.eui).status /= exception then
euv(r.eut)(r.eui).status := started;
end if;
euv(r.eut)(r.eui).rs1 := cpi.me.inst(18 downto 14);
euv(r.eut)(r.eui).rs2 := cpi.me.inst(4 downto 0);
euv(r.eut)(r.eui).rd := cpi.me.inst(29 downto 25);
euv(r.eut)(r.eui).wreg := me.wreg;
euv(r.eut)(r.eui).rreg1 := me.rreg1;
euv(r.eut)(r.eui).rreg2 := me.rreg2;
euv(r.eut)(r.eui).rs1d := me.rs1d;
euv(r.eut)(r.eui).rs2d := me.rs2d;
euv(r.eut)(r.eui).rdd := me.rdd;
euv(r.eut)(r.eui).wrcc := me.wrcc;
euiv(r.eut)(r.eui).opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
rxv.holdn := '1';
end if;
rxv.starty := euiv(r.eut)(r.eui).start;
rxv.startx := (rx.startx or euiv(r.eut)(r.eui).start) and not holdn;
ccv := ccv or me.wrcc;
if cpi.flush = '1' then rxv.holdn := '1'; end if;
-- regfile bypass
if (rx.waddr = cpi.me.inst(18 downto 15)) then
if (rx.wren(0) = '1') then op1(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op1(31 downto 0) := rx.res(31 downto 0); end if;
end if;
if (rx.waddr = cpi.me.inst(4 downto 1)) then
if (rx.wren(0) = '1') then op2(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op2(31 downto 0) := rx.res(31 downto 0); end if;
end if;
-- optionally forward data from write stage
if rfi.wren(0) = '1' then
if cpi.me.inst(18 downto 15) = rfi.waddr then
op1(63 downto 32) := rfi.wdata(63 downto 32);
end if;
if cpi.me.inst(4 downto 1) = rfi.waddr then
op2(63 downto 32) := rfi.wdata(63 downto 32);
end if;
end if;
if rfi.wren(1) = '1' then
if cpi.me.inst(18 downto 15) = rfi.waddr then
op1(31 downto 0) := rfi.wdata(31 downto 0);
end if;
if cpi.me.inst(4 downto 1) = rfi.waddr then
op2(31 downto 0) := rfi.wdata(31 downto 0);
end if;
end if;
-- align single operands
if me.rs1d = '0' then
if cpi.me.inst(14) = '0' then op1 := op1(63 downto 32) & op1(63 downto 32);
else op1 := op1(31 downto 0) & op1(31 downto 0); end if;
end if;
if me.rs2d = '0' then
if cpi.me.inst(0) = '0' then op2 := op2(63 downto 32) & op2(63 downto 32);
else op2 := op2(31 downto 0) & op2(31 downto 0); end if;
end if;
-- drive EU operand inputs
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
euiv(i)(j).op1 := op1; euiv(i)(j).op2 := op2;
end loop;
end loop;
cpo.holdn <= rx.holdn;
-------------------------------------------------------------
-- write stage
-------------------------------------------------------------
wrdata := cpi.lddata & cpi.lddata;
if cpi.flush = '0' then
case wr.cpins is
when load =>
if (wr.wreg = '1') then
if cpi.wr.cnt = "00" then
wren(0) := not cpi.wr.inst(25);
wren(1) := cpi.wr.inst(25);
else wren(1) := '1'; end if;
end if;
if (wr.acsr and holdn) = '1' then
rxv.csr.cexc := cpi.lddata(4 downto 0);
rxv.csr.aexc := cpi.lddata(9 downto 5);
rxv.csr.cc := cpi.lddata(11 downto 10);
rxv.csr.tem := cpi.lddata(27 downto 23);
rxv.csr.rd := cpi.lddata(31 downto 30);
end if;
when store =>
if wr.acsr = '1' then rxv.csr.tt := (others => '0'); end if;
if (cpi.wr.inst(20 downto 19) = "10") then -- STDFQ
if qne = '1'then
euv(euti)(euqi).status := free;
euv(euti)(euqi).rst := '1';
if euq(euti).last = euconf(euti) then euqv(euti).last := 0;
else euqv(euti).last := euqv(euti).last + 1; end if;
if (euf.last /= euf.first) then
if euf.last = (EUTOT-1) then eufv.last := 0;
else eufv.last := eufv.last + 1; end if;
end if;
else
rxv.state := nominal;
end if;
end if;
when cpop =>
-- dont assign PC and inst until here in case previous cpop trapped
euv(r.weut)(r.weui).inst := cpi.wr.inst;
euv(r.weut)(r.weui).pc := cpi.wr.pc;
when others => null;
end case;
end if;
-- flush EU if trap was taken
if ((holdn and cpi.flush) = '1') and (EUTOT > 1) then
case wr.cpins is
when cpop =>
if eu(r.weut)(r.weui).status /= exception then
euv(r.weut)(r.weui).rst := '1';
euv(r.weut)(r.weui).status := free;
end if;
eufv.first := wr.first;
euqv(r.eut).first := r.eut;
euqv(r.weut).first := r.weut;
when others => null;
end case;
end if;
waddr := cpi.wr.inst(29 downto 26);
-------------------------------------------------------------
-- retire stage
-------------------------------------------------------------
rtaddr := eu(euti)(euqi).rd(4 downto 1);
if eu(euti)(euqi).rdd = '1' then rtdata := euo(euti)(euqi).res;
else
rtdata(63 downto 32) := euo(euti)(euqi).res(63) &
euo(euti)(euqi).res(59 downto 29);
rtdata(31 downto 0) := rtdata(63 downto 32);
end if;
wren := wren and (holdn & holdn);
if ((euo(euti)(euqi).exc(4 downto 0) and rx.csr.tem) /= "00000") or
(euo(euti)(euqi).exc(5) = '1')
then
cpexc := '1';
end if;
if (wren = "00") and (eu(euti)(euqi).status = ready) and
(rx.state = nominal)
then
waddr := rtaddr; wrdata := rtdata;
if cpexc = '0' then
if (eu(euti)(euqi).wreg) = '1' then
if (eu(euti)(euqi).rdd) = '1' then wren := "11";
else
wren(0) := not eu(euti)(euqi).rd(0);
wren(1) := eu(euti)(euqi).rd(0);
end if;
end if;
if eu(euti)(euqi).wrcc = '1' then
rxv.csr.cc := euo(euti)(euqi).cc;
end if;
rxv.csr.aexc := rx.csr.aexc or euo(euti)(euqi).exc(4 downto 0);
if euv(euti)(euqi).status = ready then
euv(euti)(euqi).status := free;
end if;
euv(euti)(euqi).wb := '1';
rxv.csr.cexc := euo(euti)(euqi).exc(4 downto 0);
if euq(euti).last = euconf(euti) then euqv(euti).last := 0;
else euqv(euti).last := euqv(euti).last + 1; end if;
if euf.last = (EUTOT-1) then eufv.last := 0;
else eufv.last := eufv.last + 1; end if;
else
euv(euti)(euqi).status := exception;
rxv.state := excpend;
if (euo(euti)(euqi).exc(5) = '1') then rxv.csr.tt := "011";
else rxv.csr.tt := "001"; end if;
end if;
end if;
if cpi.exack = '1' then rxv.state := exception; end if;
if rxv.state = excpend then cpo.exc <= '1'; else cpo.exc <= '0'; end if;
cpo.ccv <= not ccv;
cpo.cc <= rx.csr.cc;
rxv.res := wrdata;
rxv.waddr := waddr;
rxv.wren := wren;
rfi.waddr <= waddr;
rfi.wren <= wren;
rfi.wdata <= wrdata;
-- reset
if rst = '0' then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop euv(i)(j).status := free; end loop;
euqv(i).first := 0; euqv(i).last := 0;
end loop;
eufv.first := 0; eufv.last := 0; rxv.holdn := '1'; rv.start := '0';
rxv.state := nominal; rxv.csr.tt := (others => '0');
rxv.startx := '0';
ctrl.first := 0;
end if;
euin <= euv;
eui <= euiv;
eufin <= eufv;
euqin <= euqv;
exin <= ctrl;
rin <= rv;
rxin <= rxv;
end process;
-- registers
regs : process(clk)
variable pc : std_logic_vector(31 downto 0);
begin
if rising_edge(clk(0)) then
if holdn = '1' then
ex <= exin; me <= ex; wr <= me; r <= rin;
end if;
euq <= euqin; euf <= eufin;
rx <= rxin; eu <= euin;
-- pragma translate_off
if DEBUGFPU then
if euin(euf.fifo(euf.last))(euq(euf.fifo(euf.last)).last).wb = '1' then
pc := eu(euf.fifo(euf.last))(euq(euf.fifo(euf.last)).last).pc;
else pc := cpi.wr.pc; end if;
if (rfi.wren(0) = '1') then
print(tost(pc) & ": %f" & tost("000" & rfi.waddr & '0') &
" = " & tost(rfi.wdata(63 downto 32)));
end if;
if (rfi.wren(1) = '1') then
print(tost(pc) & ": %f" & tost("000" & rfi.waddr & '1') &
" = " & tost(rfi.wdata(31 downto 0)));
end if;
end if;
-- pragma translate_on
end if;
end process;
-- simple 3-port register file made up of 4 parallel dprams
dp00: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(63 downto 32), rfi.raddr1, rfi.waddr, vcc, rfi.wren(0),
clk(0), vcc, rfo.rdata1(63 downto 32));
dp01: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(31 downto 0), rfi.raddr1, rfi.waddr, vcc, rfi.wren(1),
clk(0), vcc, rfo.rdata1(31 downto 0));
dp10: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(63 downto 32), rfi.raddr2, rfi.waddr, vcc, rfi.wren(0),
clk(0), vcc, rfo.rdata2(63 downto 32));
dp11: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(31 downto 0), rfi.raddr2, rfi.waddr, vcc, rfi.wren(1),
clk(0), vcc, rfo.rdata2(31 downto 0));
gl0 : for i in 0 to euconf(0) generate
fpu0 : fpu port map (
ss_clock => clk(0),
FpInst => eui(0)(i).opcode,
FpOp => eui(0)(i).start,
FpLd => eui(0)(i).load,
Reset => eui(0)(i).flush,
fprf_dout1 => eui(0)(i).op1,
fprf_dout2 => eui(0)(i).op2,
RoundingMode => rx.csr.rd,
FpBusy => euo(0)(i).busy,
FracResult => euo(0)(i).res(51 downto 0),
ExpResult => euo(0)(i).res(62 downto 52),
SignResult => euo(0)(i).res(63),
SNnotDB => open,
Excep => euo(0)(i).exc,
ConditionCodes => euo(0)(i).cc,
ss_scan_mode => gnd,
fp_ctl_scan_in => gnd,
fp_ctl_scan_out => open);
end generate;
fpauxgen : if EUTYPES > 1 generate
gl1 : for i in 0 to euconf(1) generate
eu1 : fpaux port map (rst, clk(0), eui(1)(i), euo(1)(i));
end generate;
end generate;
end;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/ahbstat.vhd | 2 | 3175 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: ahbstat
-- File: ahbstat.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: AHB status register. Latches the address and bus
-- parameters when an error is signalled on the AHB bus.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
entity ahbstat is
port (
rst : in rst_type;
clk : in clk_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsto : out ahbstat_out_type
);
end;
architecture rtl of ahbstat is
type memstattype is record
hsize : std_logic_vector(2 downto 0);
hmaster : std_logic_vector(3 downto 0);
address : std_logic_vector(31 downto 0); -- failed address
read : std_logic;
newerr : std_logic;
ahberr : std_logic;
hresp : std_logic_vector(1 downto 0);
end record;
signal r, rin : memstattype;
signal ecorr, ecorrin : std_logic;
begin
ctrl : process(rst, ahbmi, ahbsi, apbi, r, ecorr)
variable v : memstattype;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
begin
v := r; regsd := (others => '0');
case apbi.paddr(2 downto 2) is
when "1" => regsd := r.address;
when "0" =>
regsd := "00000000000000000000000" & r.newerr & r.read &
r.hmaster & r.hsize ;
when others => regsd := (others => '-');
end case;
apbo.prdata <= regsd;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(2 downto 2) is
when "1" => v.address := apbi.pwdata;
when "0" =>
v.newerr := apbi.pwdata(8);
v.read := apbi.pwdata(7);
v.hmaster := apbi.pwdata(6 downto 3);
v.hsize := apbi.pwdata(2 downto 0);
when others => null;
end case;
end if;
v.hresp := ahbmi.hresp;
if (ahbsi.hready = '1') then
if (r.newerr = '0') then
if (r.hresp = HRESP_ERROR) then v.newerr := '1';
else
v.hmaster := ahbsi.hmaster; v.address := ahbsi.haddr;
v.read := not ahbsi.hwrite; v.hsize := ahbsi.hsize;
end if;
end if;
v.hresp := HRESP_OKAY;
end if;
if rst.syncrst = '0' then
v.newerr := '0'; v.hresp := HRESP_OKAY;
end if;
v.ahberr := v.newerr and not r.newerr;
rin <= v;
ahbsto.ahberr <= r.ahberr;
end process;
memstatregs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/meiko.vhd | 3 | 1823 |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: meiko
-- File: meiko.vhd
-- Description: Dummy version of Meiko FPU
------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use work.iface.all;
entity fpu is
port(
ss_clock : in clk_type;
FpInst : in std_logic_vector(9 downto 0);
FpOp : in std_logic;
FpLd : in std_logic;
Reset : in std_logic;
fprf_dout1 : in std_logic_vector(63 downto 0);
fprf_dout2 : in std_logic_vector(63 downto 0);
RoundingMode : in std_logic_vector(1 downto 0);
FpBusy : out std_logic;
FracResult : out std_logic_vector(54 downto 3);
ExpResult : out std_logic_vector(10 downto 0);
SignResult : out std_logic;
SNnotDB : out std_logic;
Excep : out std_logic_vector(5 downto 0);
ConditionCodes : out std_logic_vector(1 downto 0);
ss_scan_mode : in std_logic;
fp_ctl_scan_in : in std_logic;
fp_ctl_scan_out : out std_logic
);
end;
architecture rtl of fpu is
begin
FpBusy <= '1';
FracResult <= (others => '0');
ExpResult <= (others => '0');
Excep <= (others => '0');
ConditionCodes <= (others => '0');
SignResult <= '0';
SNnotDB <= '0';
end;
| gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/pci_is.vhd | 2 | 3242 | -------------------------------------------------------------------------------
-- Title : PCI interface for LEON processor
-- Project : pci4leon
-------------------------------------------------------------------------------
-- File : pci.vhd
-- Author : Roland Weigand <[email protected]>
-- Created : 2000/02/29
-- Last modified : 2000/02/29
-------------------------------------------------------------------------------
-- Description :
-- This Unit is the top level of the PCI interface. It is connected
-- to the peripheral bus of LEON and the DMA port.
-- PCI ports must be connected to the top level pads.
-- It includes the Phoenix/In-Silicon PCI core
-------------------------------------------------------------------------------
-- THIS IS JUST A DUMMY VERSION TO TEST THE LEON/AHB INTERFACE
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.amba.all;
use work.iface.all;
entity pci_is is
port (
rst_n : in std_logic;
app_clk : in clk_type;
pci_clk : in clk_type; -- switched clock for PCI config regs
-- peripheral bus
pbi : in APB_Slv_In_Type; -- peripheral bus in
pbo : out APB_Slv_Out_Type; -- peripheral bus out
irq : out std_logic; -- interrupt request
-- PCI-Target DMA-Port = AHB master
TargetMasterOut : out ahb_mst_out_type; -- dma port out
TargetMasterIn : in ahb_mst_in_type; -- dma port in
-- TargetAsi : out std_logic_vector(3 downto 0); -- 1 ASI
-- PCI PORTS for top level
pci_in : in pci_in_type; -- PCI bus inputs
pci_out : out pci_out_type; -- PCI bus outputs
-- PCI-Initiator Word-Interface = AHB slave
InitSlaveOut : out ahb_slv_out_type; -- Direct initiator I/F
InitSlaveIn : in ahb_slv_in_type; -- Direct initiator I/F
-- PCI-Intitiator DMA-Port = AHB master
InitMasterOut : out ahb_mst_out_type; -- dma port out
InitMasterIn : in ahb_mst_in_type -- dma port in
-- InitAsi : out std_logic_vector(3 downto 0); -- 1 ASI
);
end;
architecture struct of pci_is is
begin
InitMasterOut.haddr <= (others => '0') ;
InitMasterOut.htrans <= HTRANS_IDLE;
InitMasterOut.hbusreq <= '0';
InitMasterOut.hwdata <= (others => '0');
InitMasterOut.hlock <= '0';
InitMasterOut.hwrite <= '0';
InitMasterOut.hsize <= HSIZE_WORD;
InitMasterOut.hburst <= HBURST_SINGLE;
InitMasterOut.hprot <= (others => '0');
TargetMasterOut.haddr <= (others => '0') ;
TargetMasterOut.htrans <= HTRANS_IDLE;
TargetMasterOut.hbusreq <= '0';
TargetMasterOut.hwdata <= (others => '0');
TargetMasterOut.hlock <= '0';
TargetMasterOut.hwrite <= '0';
TargetMasterOut.hsize <= HSIZE_WORD;
TargetMasterOut.hburst <= HBURST_SINGLE;
TargetMasterOut.hprot <= (others => '0');
InitSlaveOut.hrdata <= (others => '0');
InitSlaveOut.hready <= '1';
InitSlaveOut.hresp <= HRESP_OKAY;
irq <= '0';
end;
| gpl-3.0 |
johnmurrayvi/vhdl-projects | CPU/Control.vhd | 1 | 9948 | library IEEE;
use IEEE.std_logic_1164.all;
use work.cpu_lib.all;
entity control is
port( clock : in std_logic;
reset : in std_logic;
instrReg : in bit16;
compout : in std_logic;
ready : in std_logic;
progCntrWr : out std_logic;
progCntrRd : out std_logic;
addrRegWr : out std_logic;
addrRegRd : out std_logic;
outRegWr : out std_logic;
outRegRd : out std_logic;
shiftSel : out t_shift;
aluSel : out t_alu;
compSel : out t_comp;
opRegRd : out std_logic;
opRegWr : out std_logic;
instrWr : out std_logic;
regSel : out t_reg;
regRd : out std_logic;
regWr : out std_logic;
rw : out std_logic;
vma : out std_logic
);
end control;
architecture rtl of control is
signal current_state, next_state : state;
begin
nxtstateproc: process( current_state, instrReg, compout, ready)
begin
progCntrWr <= '0';
progCntrRd <= '0';
addrRegWr <= '0';
outRegWr <= '0';
outRegRd <= '0';
shiftSel <= shftpass;
aluSel <= alupass;
compSel <= eq;
opRegRd <= '0';
opRegWr <= '0';
instrWr <= '0';
regSel <= "000";
regRd <= '0';
regWr <= '0';
rw <= '0';
vma <= '0';
case current_state is
when reset1 =>
aluSel <= zero after 1 ns;
shiftSel <= shftpass;
next_state <= reset2;
when reset2 =>
aluSel <= zero;
shiftSel <= shftpass;
outRegWr <= '1';
next_state <= reset3;
when reset3 =>
outRegRd <= '1';
next_state <= reset4;
when reset4 =>
outRegRd <= '1';
progCntrWr <= '1';
addrRegWr <= '1';
next_state <= reset5;
when reset5 =>
vma <= '1';
rw <= '0';
next_state <= reset6;
when reset6 =>
vma <= '1';
rw <= '0';
if ready = '1' then
instrWr <= '1';
next_state <= execute;
else
next_state <= reset6;
end if;
when execute =>
case instrReg(15 downto 11) is
when "00000" => --- nop
next_state <= incPc;
when "00001" => --- load
regSel <= instrReg(5 downto 3);
regRd <= '1';
next_state <= load2;
when "00010" => --- store
regSel <= instrReg(2 downto 0);
regRd <= '1';
next_state <= store2;
when "00011" => ----- move
regSel <= instrReg(5 downto 3);
regRd <= '1';
aluSel <= alupass;
shiftSel <= shftpass;
next_state <= move2;
when "00100" => ---- loadI
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
next_state <= loadI2;
when "00101" => ---- BranchImm
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
next_state <= braI2;
when "00110" => ---- BranchGTImm
regSel <= instrReg(5 downto 3);
regRd <= '1';
next_state <= bgtI2;
when "00111" => ------- inc
regSel <= instrReg(2 downto 0);
regRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
next_state <= inc2;
when others =>
next_state <= incPc;
end case;
when load2 =>
regSel <= instrReg(5 downto 3);
regRd <= '1';
addrregWr <= '1';
next_state <= load3;
when load3 =>
vma <= '1';
rw <= '0';
next_state <= load4;
when load4 =>
vma <= '1';
rw <= '0';
regSel <= instrReg(2 downto 0);
regWr <= '1';
next_state <= incPc;
when store2 =>
regSel <= instrReg(2 downto 0);
regRd <= '1';
addrregWr <= '1';
next_state <= store3;
when store3 =>
regSel <= instrReg(5 downto 3);
regRd <= '1';
next_state <= store4;
when store4 =>
regSel <= instrReg(5 downto 3);
regRd <= '1';
vma <= '1';
rw <= '1';
next_state <= incPc;
when move2 =>
regSel <= instrReg(5 downto 3);
regRd <= '1';
aluSel <= alupass;
shiftsel <= shftpass;
outRegWr <= '1';
next_state <= move3;
when move3 =>
outRegRd <= '1';
next_state <= move4;
when move4 =>
outRegRd <= '1';
regSel <= instrReg(2 downto 0);
regWr <= '1';
next_state <= incPc;
when loadI2 =>
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
outregWr <= '1';
next_state <= loadI3;
when loadI3 =>
outregRd <= '1';
next_state <= loadI4;
when loadI4 =>
outregRd <= '1';
progcntrWr <= '1';
addrregWr <= '1';
next_state <= loadI5;
when loadI5 =>
vma <= '1';
rw <= '0';
next_state <= loadI6;
when loadI6 =>
vma <= '1';
rw <= '0';
if ready = '1' then
regSel <= instrReg(2 downto 0);
regWr <= '1';
next_state <= incPc;
else
next_state <= loadI6;
end if;
when braI2 =>
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
outregWr <= '1';
next_state <= braI3;
when braI3 =>
outregRd <= '1';
next_state <= braI4;
when braI4 =>
outregRd <= '1';
progcntrWr <= '1';
addrregWr <= '1';
next_state <= braI5;
when braI5 =>
vma <= '1';
rw <= '0';
next_state <= braI6;
when braI6 =>
vma <= '1';
rw <= '0';
if ready = '1' then
progcntrWr <= '1';
next_state <= loadPc;
else
next_state <= braI6;
end if;
when bgtI2 =>
regSel <= instrReg(5 downto 3);
regRd <= '1';
opRegWr <= '1';
next_state <= bgtI3;
when bgtI3 =>
opRegRd <= '1';
regSel <= instrReg(2 downto 0);
regRd <= '1';
compsel <= gt;
next_state <= bgtI4;
when bgtI4 =>
opRegRd <= '1' after 1 ns;
regSel <= instrReg(2 downto 0);
regRd <= '1';
compsel <= gt;
if compout = '1' then
next_state <= bgtI5;
else
next_state <= incPc;
end if;
when bgtI5 =>
progcntrRd <= '1';
alusel <= inc;
shiftSel <= shftpass;
next_state <= bgtI6;
when bgtI6 =>
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
outregWr <= '1';
next_state <= bgtI7;
when bgtI7 =>
outregRd <= '1';
next_state <= bgtI8;
when bgtI8 =>
outregRd <= '1';
progcntrWr <= '1';
addrregWr <= '1';
next_state <= bgtI9;
when bgtI9 =>
vma <= '1';
rw <= '0';
next_state <= bgtI10;
when bgtI10 =>
vma <= '1';
rw <= '0';
if ready = '1' then
progcntrWr <= '1';
next_state <= loadPc;
else
next_state <= bgtI10;
end if;
when inc2 =>
regSel <= instrReg(2 downto 0);
regRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
outregWr <= '1';
next_state <= inc3;
when inc3 =>
outregRd <= '1';
next_state <= inc4;
when inc4 =>
outregRd <= '1';
regsel <= instrReg(2 downto 0);
regWr <= '1';
next_state <= incPc;
when loadPc =>
progcntrRd <= '1';
next_state <= loadPc2;
when loadPc2 =>
progcntrRd <= '1';
addrRegWr <= '1';
next_state <= loadPc3;
when loadPc3 =>
vma <= '1';
rw <= '0';
next_state <= loadPc4;
when loadPc4 =>
vma <= '1';
rw <= '0';
if ready = '1' then
instrWr <= '1';
next_state <= execute;
else
next_state <= loadPc4;
end if;
when incPc =>
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
next_state <= incPc2;
when incPc2 =>
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
outregWr <= '1';
next_state <= incPc3;
when incPc3 =>
outregRd <= '1';
next_state <= incPc4;
when incPc4 =>
outregRd <= '1';
progcntrWr <= '1';
addrregWr <= '1';
next_state <= incPc5;
when incPc5 =>
vma <= '1';
rw <= '0';
next_state <= incPc6;
when incPc6 =>
vma <= '1';
rw <= '0';
if ready = '1' then
instrWr <= '1';
next_state <= execute;
else
next_state <= incPc6;
end if;
when others =>
next_state <= incPc;
end case;
end process;
controlffProc: process(clock, reset)
begin
if reset = '1' then
current_state <= reset1 after 1 ns;
elsif clock'event and clock = '1' then
current_state <= next_state after 1 ns;
end if;
end process;
end rtl;
| gpl-3.0 |
tejainece/VHDLExperiments | GoldschmidtDivider/GoldschmidtDivider.vhd | 1 | 4524 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:47:26 01/19/2014
-- Design Name:
-- Module Name: GoldschmidtDiv - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY GoldschmidtDivider IS
GENERIC (m: natural := 20);
PORT (
N: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
D: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Q: OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clk, reset, start: IN STD_LOGIC;
done: OUT STD_LOGIC);
END GoldschmidtDivider;
architecture Behavioral of GoldschmidtDivider is
COMPONENT Multiply16Booth4 is
PORT (
a: IN STD_LOGIC_VECTOR(15 downto 0);
b: IN STD_LOGIC_VECTOR(15 downto 0);
o: OUT STD_LOGIC_VECTOR(15 downto 0));
END COMPONENT;
TYPE state_type IS (STATE_IDLE, STATE_LOAD, STATE_UPDATE, STATE_DONE);
SIGNAL cur_state : state_type;
SIGNAL load, update: STD_LOGIC;
SIGNAL step: NATURAL RANGE 0 TO m-1;
SIGNAL Ni: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL Nim1: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL Di: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL Dim1: STD_LOGIC_VECTOR(15 DOWNTO 0);
--SIGNAL F: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL Fi: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL Fim1: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL tDi: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL tNi: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL tDone: STD_LOGIC;
constant TWO16: signed := "0000001000000000";
begin
--intial reciprocal approximation
--it flips all bits above decimal points
--F(15 downto 8) <= (OTHERS => '0');
--F(7 downto 0) <= N(15 downto 8);
--multipliers
--tDi <= STD_LOGIC_VECTOR(signed(Dim1) * signed(Fim1));
--tNi <= STD_LOGIC_VECTOR(signed(Nim1) * signed(Fim1));
dmul: Multiply16Booth4 PORT MAP (
a => Dim1,
b => Fim1,
o => tDi(23 downto 8)
);
nmul: Multiply16Booth4 PORT MAP (
a => Nim1,
b => Fim1,
o => tNi(23 downto 8)
);
--Fi calculation
Fi <= STD_LOGIC_VECTOR(TWO16 - signed(Di));
--internal mux
Dim1 <= D when load='1' else Di;
Nim1 <= N when load='1' else Ni;
--Fim1 <= "00000000" & D(15 downto 8) when load='1' else Fi;
Fgen: FOR i IN 0 TO 15 GENERATE
if8to15:IF i >= 8 AND i <= 15 GENERATE
Fim1(i) <= '0' when load = '1' else Fi(i);
END GENERATE;
if0to7:IF i >= 0 AND i <= 7 GENERATE
Fim1(i) <= D(i+8) when load = '1' else Fi(i);
END GENERATE;
END GENERATE;
--quotient & output mux
Q <= Ni when tDone = '1' else (OTHERS => '0');
done <= tDone;
--di register & rounding
dregister: PROCESS(clk)
BEGIN
IF clk'EVENT and clk = '1' THEN
IF reset = '1' THEN
Di <= (OTHERS => '0');
ELSIF load = '1' OR update = '1' THEN
Di <= tDi(23 downto 8);
END IF;
END IF;
END PROCESS;
--ni register & rounding
nregister: PROCESS(clk)
BEGIN
IF clk'EVENT and clk = '1' THEN
IF reset = '1' THEN
Ni <= (OTHERS => '0');
ELSIF load = '1' OR update = '1' THEN
Ni <= tNi(23 downto 8);
END IF;
END IF;
END PROCESS;
counter: PROCESS(clk)
BEGIN
IF clk'EVENT and clk = '1' THEN
IF load = '1' THEN step <= 0;
ELSIF update = '1' THEN step <= (step+1) MOD m;
END IF;
END IF;
END PROCESS;
--Controller
NEXT_STATE_DECODE: PROCESS(clk, reset)
BEGIN
IF reset = '1' THEN cur_state <= STATE_IDLE;
ELSIF clk'EVENT AND clk = '1' THEN
CASE cur_state IS
WHEN STATE_IDLE => IF start = '1' THEN cur_state <= STATE_LOAD; END IF;
WHEN STATE_LOAD => cur_state <= STATE_UPDATE;
WHEN STATE_UPDATE => IF step = m-1 THEN cur_state <= STATE_DONE; END IF;
WHEN STATE_DONE => cur_state <= STATE_IDLE;
END CASE;
END IF;
END PROCESS;
OUTPUT_DECODE: PROCESS(cur_state)
BEGIN
CASE cur_state IS
WHEN STATE_IDLE => load <= '0'; update <= '0'; tDone <= '0';
WHEN STATE_LOAD => load <= '1'; update <= '0'; tDone <= '0';
WHEN STATE_UPDATE => load <= '0'; update <= '1'; tDone <= '0';
WHEN STATE_DONE => load <= '0'; update <= '0'; tDone <= '1';
END CASE;
END PROCESS;
end Behavioral;
| gpl-3.0 |
tejainece/VHDLExperiments | FloatingPointMul23/Selector.vhd | 1 | 1809 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:29 11/20/2013
-- Design Name:
-- Module Name: Selector - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.MyTypes.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Selector is
generic (
num_sum: integer := 0;
num_buffer: integer := 0
);
Port ( cIn : in PairT;
cSel : in PairT;
cOut : out PairT;
sumIn : in PairArr(num_sum downto 0);
sumOut : out PairArr(num_sum downto 0);
bufferIn: in PairArr(num_buffer downto 0);
bufferOut:out PairArr(num_buffer downto 0));
end Selector;
architecture Behavioral of Selector is
begin
process (cIn, cSel, sumIn)
begin
if (cSel(0) = cSel(1)) then
if (cSel(0) = '0') then
for index in 0 to num_sum loop
sumOut(index) <= (1 downto 0 => sumIn(index)(0));
end loop;
cOut <= (1 downto 0 => cIn(0));
else
for index in 0 to num_sum loop
sumOut(index) <= (1 downto 0 => sumIn(index)(1));
end loop;
cOut <= (1 downto 0 => cIn(1));
end if;
else
for index in 0 to num_sum loop
sumOut <= sumIn;
end loop;
cOut <= cIn;
end if;
end process;
bufferOut <= bufferIn;
end Behavioral; | gpl-3.0 |
marc0l92/RadioFM_FPGA | RadioFM_project/ps7_stub.vhd | 1 | 36385 | ----------------------------------------------------------------------------
-- ps7_stub.vhd
-- ZedBoard simple VHDL example
-- Version 1.0
--
-- Copyright (C) 2013 H.Poetzl
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation, either version
-- 2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.VCOMPONENTS.all;
entity ps7_stub is
port (
i2c_sda_i : in std_ulogic;
i2c_sda_o : out std_ulogic;
i2c_sda_tn : out std_ulogic;
--
i2c_scl_i : in std_ulogic;
i2c_scl_o : out std_ulogic;
i2c_scl_tn : out std_ulogic
);
end entity ps7_stub;
architecture RTL of ps7_stub is
begin
PS7_inst : PS7
port map (
DMA0DATYPE => open, -- out std_logic_vector(1 downto 0);
DMA0DAVALID => open, -- out std_ulogic;
DMA0DRREADY => open, -- out std_ulogic;
DMA0RSTN => open, -- out std_ulogic;
DMA1DATYPE => open, -- out std_logic_vector(1 downto 0);
DMA1DAVALID => open, -- out std_ulogic;
DMA1DRREADY => open, -- out std_ulogic;
DMA1RSTN => open, -- out std_ulogic;
DMA2DATYPE => open, -- out std_logic_vector(1 downto 0);
DMA2DAVALID => open, -- out std_ulogic;
DMA2DRREADY => open, -- out std_ulogic;
DMA2RSTN => open, -- out std_ulogic;
DMA3DATYPE => open, -- out std_logic_vector(1 downto 0);
DMA3DAVALID => open, -- out std_ulogic;
DMA3DRREADY => open, -- out std_ulogic;
DMA3RSTN => open, -- out std_ulogic;
EMIOCAN0PHYTX => open, -- out std_ulogic;
EMIOCAN1PHYTX => open, -- out std_ulogic;
EMIOENET0GMIITXD => open, -- out std_logic_vector(7 downto 0);
EMIOENET0GMIITXEN => open, -- out std_ulogic;
EMIOENET0GMIITXER => open, -- out std_ulogic;
EMIOENET0MDIOMDC => open, -- out std_ulogic;
EMIOENET0MDIOO => open, -- out std_ulogic;
EMIOENET0MDIOTN => open, -- out std_ulogic;
EMIOENET0PTPDELAYREQRX => open, -- out std_ulogic;
EMIOENET0PTPDELAYREQTX => open, -- out std_ulogic;
EMIOENET0PTPPDELAYREQRX => open, -- out std_ulogic;
EMIOENET0PTPPDELAYREQTX => open, -- out std_ulogic;
EMIOENET0PTPPDELAYRESPRX => open, -- out std_ulogic;
EMIOENET0PTPPDELAYRESPTX => open, -- out std_ulogic;
EMIOENET0PTPSYNCFRAMERX => open, -- out std_ulogic;
EMIOENET0PTPSYNCFRAMETX => open, -- out std_ulogic;
EMIOENET0SOFRX => open, -- out std_ulogic;
EMIOENET0SOFTX => open, -- out std_ulogic;
EMIOENET1GMIITXD => open, -- out std_logic_vector(7 downto 0);
EMIOENET1GMIITXEN => open, -- out std_ulogic;
EMIOENET1GMIITXER => open, -- out std_ulogic;
EMIOENET1MDIOMDC => open, -- out std_ulogic;
EMIOENET1MDIOO => open, -- out std_ulogic;
EMIOENET1MDIOTN => open, -- out std_ulogic;
EMIOENET1PTPDELAYREQRX => open, -- out std_ulogic;
EMIOENET1PTPDELAYREQTX => open, -- out std_ulogic;
EMIOENET1PTPPDELAYREQRX => open, -- out std_ulogic;
EMIOENET1PTPPDELAYREQTX => open, -- out std_ulogic;
EMIOENET1PTPPDELAYRESPRX => open, -- out std_ulogic;
EMIOENET1PTPPDELAYRESPTX => open, -- out std_ulogic;
EMIOENET1PTPSYNCFRAMERX => open, -- out std_ulogic;
EMIOENET1PTPSYNCFRAMETX => open, -- out std_ulogic;
EMIOENET1SOFRX => open, -- out std_ulogic;
EMIOENET1SOFTX => open, -- out std_ulogic;
EMIOGPIOO => open, -- out std_logic_vector(63 downto 0);
EMIOGPIOTN => open, -- out std_logic_vector(63 downto 0);
EMIOI2C0SCLO => i2c_scl_o, -- out std_ulogic;
EMIOI2C0SCLTN => i2c_scl_tn, -- out std_ulogic;
EMIOI2C0SDAO => i2c_sda_o, -- out std_ulogic;
EMIOI2C0SDATN => i2c_sda_tn, -- out std_ulogic;
EMIOI2C1SCLO => open, -- out std_ulogic;
EMIOI2C1SCLTN => open, -- out std_ulogic;
EMIOI2C1SDAO => open, -- out std_ulogic;
EMIOI2C1SDATN => open, -- out std_ulogic;
EMIOPJTAGTDO => open, -- out std_ulogic;
EMIOPJTAGTDTN => open, -- out std_ulogic;
EMIOSDIO0BUSPOW => open, -- out std_ulogic;
EMIOSDIO0BUSVOLT => open, -- out std_logic_vector(2 downto 0);
EMIOSDIO0CLK => open, -- out std_ulogic;
EMIOSDIO0CMDO => open, -- out std_ulogic;
EMIOSDIO0CMDTN => open, -- out std_ulogic;
EMIOSDIO0DATAO => open, -- out std_logic_vector(3 downto 0);
EMIOSDIO0DATATN => open, -- out std_logic_vector(3 downto 0);
EMIOSDIO0LED => open, -- out std_ulogic;
EMIOSDIO1BUSPOW => open, -- out std_ulogic;
EMIOSDIO1BUSVOLT => open, -- out std_logic_vector(2 downto 0);
EMIOSDIO1CLK => open, -- out std_ulogic;
EMIOSDIO1CMDO => open, -- out std_ulogic;
EMIOSDIO1CMDTN => open, -- out std_ulogic;
EMIOSDIO1DATAO => open, -- out std_logic_vector(3 downto 0);
EMIOSDIO1DATATN => open, -- out std_logic_vector(3 downto 0);
EMIOSDIO1LED => open, -- out std_ulogic;
EMIOSPI0MO => open, -- out std_ulogic;
EMIOSPI0MOTN => open, -- out std_ulogic;
EMIOSPI0SCLKO => open, -- out std_ulogic;
EMIOSPI0SCLKTN => open, -- out std_ulogic;
EMIOSPI0SO => open, -- out std_ulogic;
EMIOSPI0SSNTN => open, -- out std_ulogic;
EMIOSPI0SSON => open, -- out std_logic_vector(2 downto 0);
EMIOSPI0STN => open, -- out std_ulogic;
EMIOSPI1MO => open, -- out std_ulogic;
EMIOSPI1MOTN => open, -- out std_ulogic;
EMIOSPI1SCLKO => open, -- out std_ulogic;
EMIOSPI1SCLKTN => open, -- out std_ulogic;
EMIOSPI1SO => open, -- out std_ulogic;
EMIOSPI1SSNTN => open, -- out std_ulogic;
EMIOSPI1SSON => open, -- out std_logic_vector(2 downto 0);
EMIOSPI1STN => open, -- out std_ulogic;
EMIOTRACECTL => open, -- out std_ulogic;
EMIOTRACEDATA => open, -- out std_logic_vector(31 downto 0);
EMIOTTC0WAVEO => open, -- out std_logic_vector(2 downto 0);
EMIOTTC1WAVEO => open, -- out std_logic_vector(2 downto 0);
EMIOUART0DTRN => open, -- out std_ulogic;
EMIOUART0RTSN => open, -- out std_ulogic;
EMIOUART0TX => open, -- out std_ulogic;
EMIOUART1DTRN => open, -- out std_ulogic;
EMIOUART1RTSN => open, -- out std_ulogic;
EMIOUART1TX => open, -- out std_ulogic;
EMIOUSB0PORTINDCTL => open, -- out std_logic_vector(1 downto 0);
EMIOUSB0VBUSPWRSELECT => open, -- out std_ulogic;
EMIOUSB1PORTINDCTL => open, -- out std_logic_vector(1 downto 0);
EMIOUSB1VBUSPWRSELECT => open, -- out std_ulogic;
EMIOWDTRSTO => open, -- out std_ulogic;
EVENTEVENTO => open, -- out std_ulogic;
EVENTSTANDBYWFE => open, -- out std_logic_vector(1 downto 0);
EVENTSTANDBYWFI => open, -- out std_logic_vector(1 downto 0);
FCLKCLK => open, -- out std_logic_vector(3 downto 0);
FCLKRESETN => open, -- out std_logic_vector(3 downto 0);
FTMTF2PTRIGACK => open, -- out std_logic_vector(3 downto 0);
FTMTP2FDEBUG => open, -- out std_logic_vector(31 downto 0);
FTMTP2FTRIG => open, -- out std_logic_vector(3 downto 0);
IRQP2F => open, -- out std_logic_vector(28 downto 0);
MAXIGP0ARADDR => open, -- out std_logic_vector(31 downto 0);
MAXIGP0ARBURST => open, -- out std_logic_vector(1 downto 0);
MAXIGP0ARCACHE => open, -- out std_logic_vector(3 downto 0);
MAXIGP0ARESETN => open, -- out std_ulogic;
MAXIGP0ARID => open, -- out std_logic_vector(11 downto 0);
MAXIGP0ARLEN => open, -- out std_logic_vector(3 downto 0);
MAXIGP0ARLOCK => open, -- out std_logic_vector(1 downto 0);
MAXIGP0ARPROT => open, -- out std_logic_vector(2 downto 0);
MAXIGP0ARQOS => open, -- out std_logic_vector(3 downto 0);
MAXIGP0ARSIZE => open, -- out std_logic_vector(1 downto 0);
MAXIGP0ARVALID => open, -- out std_ulogic;
MAXIGP0AWADDR => open, -- out std_logic_vector(31 downto 0);
MAXIGP0AWBURST => open, -- out std_logic_vector(1 downto 0);
MAXIGP0AWCACHE => open, -- out std_logic_vector(3 downto 0);
MAXIGP0AWID => open, -- out std_logic_vector(11 downto 0);
MAXIGP0AWLEN => open, -- out std_logic_vector(3 downto 0);
MAXIGP0AWLOCK => open, -- out std_logic_vector(1 downto 0);
MAXIGP0AWPROT => open, -- out std_logic_vector(2 downto 0);
MAXIGP0AWQOS => open, -- out std_logic_vector(3 downto 0);
MAXIGP0AWSIZE => open, -- out std_logic_vector(1 downto 0);
MAXIGP0AWVALID => open, -- out std_ulogic;
MAXIGP0BREADY => open, -- out std_ulogic;
MAXIGP0RREADY => open, -- out std_ulogic;
MAXIGP0WDATA => open, -- out std_logic_vector(31 downto 0);
MAXIGP0WID => open, -- out std_logic_vector(11 downto 0);
MAXIGP0WLAST => open, -- out std_ulogic;
MAXIGP0WSTRB => open, -- out std_logic_vector(3 downto 0);
MAXIGP0WVALID => open, -- out std_ulogic;
MAXIGP1ARADDR => open, -- out std_logic_vector(31 downto 0);
MAXIGP1ARBURST => open, -- out std_logic_vector(1 downto 0);
MAXIGP1ARCACHE => open, -- out std_logic_vector(3 downto 0);
MAXIGP1ARESETN => open, -- out std_ulogic;
MAXIGP1ARID => open, -- out std_logic_vector(11 downto 0);
MAXIGP1ARLEN => open, -- out std_logic_vector(3 downto 0);
MAXIGP1ARLOCK => open, -- out std_logic_vector(1 downto 0);
MAXIGP1ARPROT => open, -- out std_logic_vector(2 downto 0);
MAXIGP1ARQOS => open, -- out std_logic_vector(3 downto 0);
MAXIGP1ARSIZE => open, -- out std_logic_vector(1 downto 0);
MAXIGP1ARVALID => open, -- out std_ulogic;
MAXIGP1AWADDR => open, -- out std_logic_vector(31 downto 0);
MAXIGP1AWBURST => open, -- out std_logic_vector(1 downto 0);
MAXIGP1AWCACHE => open, -- out std_logic_vector(3 downto 0);
MAXIGP1AWID => open, -- out std_logic_vector(11 downto 0);
MAXIGP1AWLEN => open, -- out std_logic_vector(3 downto 0);
MAXIGP1AWLOCK => open, -- out std_logic_vector(1 downto 0);
MAXIGP1AWPROT => open, -- out std_logic_vector(2 downto 0);
MAXIGP1AWQOS => open, -- out std_logic_vector(3 downto 0);
MAXIGP1AWSIZE => open, -- out std_logic_vector(1 downto 0);
MAXIGP1AWVALID => open, -- out std_ulogic;
MAXIGP1BREADY => open, -- out std_ulogic;
MAXIGP1RREADY => open, -- out std_ulogic;
MAXIGP1WDATA => open, -- out std_logic_vector(31 downto 0);
MAXIGP1WID => open, -- out std_logic_vector(11 downto 0);
MAXIGP1WLAST => open, -- out std_ulogic;
MAXIGP1WSTRB => open, -- out std_logic_vector(3 downto 0);
MAXIGP1WVALID => open, -- out std_ulogic;
SAXIACPARESETN => open, -- out std_ulogic;
SAXIACPARREADY => open, -- out std_ulogic;
SAXIACPAWREADY => open, -- out std_ulogic;
SAXIACPBID => open, -- out std_logic_vector(2 downto 0);
SAXIACPBRESP => open, -- out std_logic_vector(1 downto 0);
SAXIACPBVALID => open, -- out std_ulogic;
SAXIACPRDATA => open, -- out std_logic_vector(63 downto 0);
SAXIACPRID => open, -- out std_logic_vector(2 downto 0);
SAXIACPRLAST => open, -- out std_ulogic;
SAXIACPRRESP => open, -- out std_logic_vector(1 downto 0);
SAXIACPRVALID => open, -- out std_ulogic;
SAXIACPWREADY => open, -- out std_ulogic;
SAXIGP0ARESETN => open, -- out std_ulogic;
SAXIGP0ARREADY => open, -- out std_ulogic;
SAXIGP0AWREADY => open, -- out std_ulogic;
SAXIGP0BID => open, -- out std_logic_vector(5 downto 0);
SAXIGP0BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIGP0BVALID => open, -- out std_ulogic;
SAXIGP0RDATA => open, -- out std_logic_vector(31 downto 0);
SAXIGP0RID => open, -- out std_logic_vector(5 downto 0);
SAXIGP0RLAST => open, -- out std_ulogic;
SAXIGP0RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIGP0RVALID => open, -- out std_ulogic;
SAXIGP0WREADY => open, -- out std_ulogic;
SAXIGP1ARESETN => open, -- out std_ulogic;
SAXIGP1ARREADY => open, -- out std_ulogic;
SAXIGP1AWREADY => open, -- out std_ulogic;
SAXIGP1BID => open, -- out std_logic_vector(5 downto 0);
SAXIGP1BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIGP1BVALID => open, -- out std_ulogic;
SAXIGP1RDATA => open, -- out std_logic_vector(31 downto 0);
SAXIGP1RID => open, -- out std_logic_vector(5 downto 0);
SAXIGP1RLAST => open, -- out std_ulogic;
SAXIGP1RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIGP1RVALID => open, -- out std_ulogic;
SAXIGP1WREADY => open, -- out std_ulogic;
SAXIHP0ARESETN => open, -- out std_ulogic;
SAXIHP0ARREADY => open, -- out std_ulogic;
SAXIHP0AWREADY => open, -- out std_ulogic;
SAXIHP0BID => open, -- out std_logic_vector(5 downto 0);
SAXIHP0BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP0BVALID => open, -- out std_ulogic;
SAXIHP0RACOUNT => open, -- out std_logic_vector(2 downto 0);
SAXIHP0RCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP0RDATA => open, -- out std_logic_vector(63 downto 0);
SAXIHP0RID => open, -- out std_logic_vector(5 downto 0);
SAXIHP0RLAST => open, -- out std_ulogic;
SAXIHP0RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP0RVALID => open, -- out std_ulogic;
SAXIHP0WACOUNT => open, -- out std_logic_vector(5 downto 0);
SAXIHP0WCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP0WREADY => open, -- out std_ulogic;
SAXIHP1ARESETN => open, -- out std_ulogic;
SAXIHP1ARREADY => open, -- out std_ulogic;
SAXIHP1AWREADY => open, -- out std_ulogic;
SAXIHP1BID => open, -- out std_logic_vector(5 downto 0);
SAXIHP1BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP1BVALID => open, -- out std_ulogic;
SAXIHP1RACOUNT => open, -- out std_logic_vector(2 downto 0);
SAXIHP1RCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP1RDATA => open, -- out std_logic_vector(63 downto 0);
SAXIHP1RID => open, -- out std_logic_vector(5 downto 0);
SAXIHP1RLAST => open, -- out std_ulogic;
SAXIHP1RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP1RVALID => open, -- out std_ulogic;
SAXIHP1WACOUNT => open, -- out std_logic_vector(5 downto 0);
SAXIHP1WCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP1WREADY => open, -- out std_ulogic;
SAXIHP2ARESETN => open, -- out std_ulogic;
SAXIHP2ARREADY => open, -- out std_ulogic;
SAXIHP2AWREADY => open, -- out std_ulogic;
SAXIHP2BID => open, -- out std_logic_vector(5 downto 0);
SAXIHP2BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP2BVALID => open, -- out std_ulogic;
SAXIHP2RACOUNT => open, -- out std_logic_vector(2 downto 0);
SAXIHP2RCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP2RDATA => open, -- out std_logic_vector(63 downto 0);
SAXIHP2RID => open, -- out std_logic_vector(5 downto 0);
SAXIHP2RLAST => open, -- out std_ulogic;
SAXIHP2RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP2RVALID => open, -- out std_ulogic;
SAXIHP2WACOUNT => open, -- out std_logic_vector(5 downto 0);
SAXIHP2WCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP2WREADY => open, -- out std_ulogic;
SAXIHP3ARESETN => open, -- out std_ulogic;
SAXIHP3ARREADY => open, -- out std_ulogic;
SAXIHP3AWREADY => open, -- out std_ulogic;
SAXIHP3BID => open, -- out std_logic_vector(5 downto 0);
SAXIHP3BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP3BVALID => open, -- out std_ulogic;
SAXIHP3RACOUNT => open, -- out std_logic_vector(2 downto 0);
SAXIHP3RCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP3RDATA => open, -- out std_logic_vector(63 downto 0);
SAXIHP3RID => open, -- out std_logic_vector(5 downto 0);
SAXIHP3RLAST => open, -- out std_ulogic;
SAXIHP3RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP3RVALID => open, -- out std_ulogic;
SAXIHP3WACOUNT => open, -- out std_logic_vector(5 downto 0);
SAXIHP3WCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP3WREADY => open, -- out std_ulogic;
DDRA => open, -- inout std_logic_vector(14 downto 0);
DDRBA => open, -- inout std_logic_vector(2 downto 0);
DDRCASB => open, -- inout std_ulogic;
DDRCKE => open, -- inout std_ulogic;
DDRCKN => open, -- inout std_ulogic;
DDRCKP => open, -- inout std_ulogic;
DDRCSB => open, -- inout std_ulogic;
DDRDM => open, -- inout std_logic_vector(3 downto 0);
DDRDQ => open, -- inout std_logic_vector(31 downto 0);
DDRDQSN => open, -- inout std_logic_vector(3 downto 0);
DDRDQSP => open, -- inout std_logic_vector(3 downto 0);
DDRDRSTB => open, -- inout std_ulogic;
DDRODT => open, -- inout std_ulogic;
DDRRASB => open, -- inout std_ulogic;
DDRVRN => open, -- inout std_ulogic;
DDRVRP => open, -- inout std_ulogic;
DDRWEB => open, -- inout std_ulogic;
MIO => open, -- inout std_logic_vector(53 downto 0);
PSCLK => open, -- inout std_ulogic;
PSPORB => open, -- inout std_ulogic;
PSSRSTB => open, -- inout std_ulogic;
DDRARB => (others => '0'), -- in std_logic_vector(3 downto 0);
DMA0ACLK => '0', -- in std_ulogic;
DMA0DAREADY => '0', -- in std_ulogic;
DMA0DRLAST => '0', -- in std_ulogic;
DMA0DRTYPE => (others => '0'), -- in std_logic_vector(1 downto 0);
DMA0DRVALID => '0', -- in std_ulogic;
DMA1ACLK => '0', -- in std_ulogic;
DMA1DAREADY => '0', -- in std_ulogic;
DMA1DRLAST => '0', -- in std_ulogic;
DMA1DRTYPE => (others => '0'), -- in std_logic_vector(1 downto 0);
DMA1DRVALID => '0', -- in std_ulogic;
DMA2ACLK => '0', -- in std_ulogic;
DMA2DAREADY => '0', -- in std_ulogic;
DMA2DRLAST => '0', -- in std_ulogic;
DMA2DRTYPE => (others => '0'), -- in std_logic_vector(1 downto 0);
DMA2DRVALID => '0', -- in std_ulogic;
DMA3ACLK => '0', -- in std_ulogic;
DMA3DAREADY => '0', -- in std_ulogic;
DMA3DRLAST => '0', -- in std_ulogic;
DMA3DRTYPE => (others => '0'), -- in std_logic_vector(1 downto 0);
DMA3DRVALID => '0', -- in std_ulogic;
EMIOCAN0PHYRX => '0', -- in std_ulogic;
EMIOCAN1PHYRX => '0', -- in std_ulogic;
EMIOENET0EXTINTIN => '0', -- in std_ulogic;
EMIOENET0GMIICOL => '0', -- in std_ulogic;
EMIOENET0GMIICRS => '0', -- in std_ulogic;
EMIOENET0GMIIRXCLK => '0', -- in std_ulogic;
EMIOENET0GMIIRXD => (others => '0'), -- in std_logic_vector(7 downto 0);
EMIOENET0GMIIRXDV => '0', -- in std_ulogic;
EMIOENET0GMIIRXER => '0', -- in std_ulogic;
EMIOENET0GMIITXCLK => '0', -- in std_ulogic;
EMIOENET0MDIOI => '0', -- in std_ulogic;
EMIOENET1EXTINTIN => '0', -- in std_ulogic;
EMIOENET1GMIICOL => '0', -- in std_ulogic;
EMIOENET1GMIICRS => '0', -- in std_ulogic;
EMIOENET1GMIIRXCLK => '0', -- in std_ulogic;
EMIOENET1GMIIRXD => (others => '0'), -- in std_logic_vector(7 downto 0);
EMIOENET1GMIIRXDV => '0', -- in std_ulogic;
EMIOENET1GMIIRXER => '0', -- in std_ulogic;
EMIOENET1GMIITXCLK => '0', -- in std_ulogic;
EMIOENET1MDIOI => '0', -- in std_ulogic;
EMIOGPIOI => (others => '0'), -- in std_logic_vector(63 downto 0);
EMIOI2C0SCLI => i2c_scl_i, -- in std_ulogic;
EMIOI2C0SDAI => i2c_sda_i, -- in std_ulogic;
EMIOI2C1SCLI => '0', -- in std_ulogic;
EMIOI2C1SDAI => '0', -- in std_ulogic;
EMIOPJTAGTCK => '0', -- in std_ulogic;
EMIOPJTAGTDI => '0', -- in std_ulogic;
EMIOPJTAGTMS => '0', -- in std_ulogic;
EMIOSDIO0CDN => '0', -- in std_ulogic;
EMIOSDIO0CLKFB => '0', -- in std_ulogic;
EMIOSDIO0CMDI => '0', -- in std_ulogic;
EMIOSDIO0DATAI => (others => '0'), -- in std_logic_vector(3 downto 0);
EMIOSDIO0WP => '0', -- in std_ulogic;
EMIOSDIO1CDN => '0', -- in std_ulogic;
EMIOSDIO1CLKFB => '0', -- in std_ulogic;
EMIOSDIO1CMDI => '0', -- in std_ulogic;
EMIOSDIO1DATAI => (others => '0'), -- in std_logic_vector(3 downto 0);
EMIOSDIO1WP => '0', -- in std_ulogic;
EMIOSPI0MI => '0', -- in std_ulogic;
EMIOSPI0SCLKI => '0', -- in std_ulogic;
EMIOSPI0SI => '0', -- in std_ulogic;
EMIOSPI0SSIN => '0', -- in std_ulogic;
EMIOSPI1MI => '0', -- in std_ulogic;
EMIOSPI1SCLKI => '0', -- in std_ulogic;
EMIOSPI1SI => '0', -- in std_ulogic;
EMIOSPI1SSIN => '0', -- in std_ulogic;
EMIOSRAMINTIN => '0', -- in std_ulogic;
EMIOTRACECLK => '0', -- in std_ulogic;
EMIOTTC0CLKI => (others => '0'), -- in std_logic_vector(2 downto 0);
EMIOTTC1CLKI => (others => '0'), -- in std_logic_vector(2 downto 0);
EMIOUART0CTSN => '0', -- in std_ulogic;
EMIOUART0DCDN => '0', -- in std_ulogic;
EMIOUART0DSRN => '0', -- in std_ulogic;
EMIOUART0RIN => '0', -- in std_ulogic;
EMIOUART0RX => '0', -- in std_ulogic;
EMIOUART1CTSN => '0', -- in std_ulogic;
EMIOUART1DCDN => '0', -- in std_ulogic;
EMIOUART1DSRN => '0', -- in std_ulogic;
EMIOUART1RIN => '0', -- in std_ulogic;
EMIOUART1RX => '0', -- in std_ulogic;
EMIOUSB0VBUSPWRFAULT => '0', -- in std_ulogic;
EMIOUSB1VBUSPWRFAULT => '0', -- in std_ulogic;
EMIOWDTCLKI => '0', -- in std_ulogic;
EVENTEVENTI => '0', -- in std_ulogic;
FCLKCLKTRIGN => (others => '0'), -- in std_logic_vector(3 downto 0);
FPGAIDLEN => '0', -- in std_ulogic;
FTMDTRACEINATID => (others => '0'), -- in std_logic_vector(3 downto 0);
FTMDTRACEINCLOCK => '0', -- in std_ulogic;
FTMDTRACEINDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
FTMDTRACEINVALID => '0', -- in std_ulogic;
FTMTF2PDEBUG => (others => '0'), -- in std_logic_vector(31 downto 0);
FTMTF2PTRIG => (others => '0'), -- in std_logic_vector(3 downto 0);
FTMTP2FTRIGACK => (others => '0'), -- in std_logic_vector(3 downto 0);
IRQF2P => (others => '0'), -- in std_logic_vector(19 downto 0);
MAXIGP0ACLK => '0', -- in std_ulogic;
MAXIGP0ARREADY => '0', -- in std_ulogic;
MAXIGP0AWREADY => '0', -- in std_ulogic;
MAXIGP0BID => (others => '0'), -- in std_logic_vector(11 downto 0);
MAXIGP0BRESP => (others => '0'), -- in std_logic_vector(1 downto 0);
MAXIGP0BVALID => '0', -- in std_ulogic;
MAXIGP0RDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
MAXIGP0RID => (others => '0'), -- in std_logic_vector(11 downto 0);
MAXIGP0RLAST => '0', -- in std_ulogic;
MAXIGP0RRESP => (others => '0'), -- in std_logic_vector(1 downto 0);
MAXIGP0RVALID => '0', -- in std_ulogic;
MAXIGP0WREADY => '0', -- in std_ulogic;
MAXIGP1ACLK => '0', -- in std_ulogic;
MAXIGP1ARREADY => '0', -- in std_ulogic;
MAXIGP1AWREADY => '0', -- in std_ulogic;
MAXIGP1BID => (others => '0'), -- in std_logic_vector(11 downto 0);
MAXIGP1BRESP => (others => '0'), -- in std_logic_vector(1 downto 0);
MAXIGP1BVALID => '0', -- in std_ulogic;
MAXIGP1RDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
MAXIGP1RID => (others => '0'), -- in std_logic_vector(11 downto 0);
MAXIGP1RLAST => '0', -- in std_ulogic;
MAXIGP1RRESP => (others => '0'), -- in std_logic_vector(1 downto 0);
MAXIGP1RVALID => '0', -- in std_ulogic;
MAXIGP1WREADY => '0', -- in std_ulogic;
SAXIACPACLK => '0', -- in std_ulogic;
SAXIACPARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIACPARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPARID => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPARUSER => (others => '0'), -- in std_logic_vector(4 downto 0);
SAXIACPARVALID => '0', -- in std_ulogic;
SAXIACPAWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIACPAWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPAWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPAWID => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPAWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPAWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPAWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPAWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPAWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPAWUSER => (others => '0'), -- in std_logic_vector(4 downto 0);
SAXIACPAWVALID => '0', -- in std_ulogic;
SAXIACPBREADY => '0', -- in std_ulogic;
SAXIACPRREADY => '0', -- in std_ulogic;
SAXIACPWDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIACPWID => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPWLAST => '0', -- in std_ulogic;
SAXIACPWSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIACPWVALID => '0', -- in std_ulogic;
SAXIGP0ACLK => '0', -- in std_ulogic;
SAXIGP0ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP0ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP0ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIGP0ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0ARVALID => '0', -- in std_ulogic;
SAXIGP0AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP0AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP0AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIGP0AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0AWVALID => '0', -- in std_ulogic;
SAXIGP0BREADY => '0', -- in std_ulogic;
SAXIGP0RREADY => '0', -- in std_ulogic;
SAXIGP0WDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP0WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP0WLAST => '0', -- in std_ulogic;
SAXIGP0WSTRB => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0WVALID => '0', -- in std_ulogic;
SAXIGP1ACLK => '0', -- in std_ulogic;
SAXIGP1ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP1ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP1ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIGP1ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1ARVALID => '0', -- in std_ulogic;
SAXIGP1AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP1AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP1AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIGP1AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1AWVALID => '0', -- in std_ulogic;
SAXIGP1BREADY => '0', -- in std_ulogic;
SAXIGP1RREADY => '0', -- in std_ulogic;
SAXIGP1WDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP1WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP1WLAST => '0', -- in std_ulogic;
SAXIGP1WSTRB => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1WVALID => '0', -- in std_ulogic;
SAXIHP0ACLK => '0', -- in std_ulogic;
SAXIHP0ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP0ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP0ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP0ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0ARVALID => '0', -- in std_ulogic;
SAXIHP0AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP0AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP0AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP0AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0AWVALID => '0', -- in std_ulogic;
SAXIHP0BREADY => '0', -- in std_ulogic;
SAXIHP0RDISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP0RREADY => '0', -- in std_ulogic;
SAXIHP0WDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIHP0WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP0WLAST => '0', -- in std_ulogic;
SAXIHP0WRISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP0WSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIHP0WVALID => '0', -- in std_ulogic;
SAXIHP1ACLK => '0', -- in std_ulogic;
SAXIHP1ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP1ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP1ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP1ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1ARVALID => '0', -- in std_ulogic;
SAXIHP1AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP1AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP1AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP1AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1AWVALID => '0', -- in std_ulogic;
SAXIHP1BREADY => '0', -- in std_ulogic;
SAXIHP1RDISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP1RREADY => '0', -- in std_ulogic;
SAXIHP1WDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIHP1WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP1WLAST => '0', -- in std_ulogic;
SAXIHP1WRISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP1WSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIHP1WVALID => '0', -- in std_ulogic;
SAXIHP2ACLK => '0', -- in std_ulogic;
SAXIHP2ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP2ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP2ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP2ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2ARVALID => '0', -- in std_ulogic;
SAXIHP2AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP2AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP2AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP2AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2AWVALID => '0', -- in std_ulogic;
SAXIHP2BREADY => '0', -- in std_ulogic;
SAXIHP2RDISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP2RREADY => '0', -- in std_ulogic;
SAXIHP2WDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIHP2WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP2WLAST => '0', -- in std_ulogic;
SAXIHP2WRISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP2WSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIHP2WVALID => '0', -- in std_ulogic;
SAXIHP3ACLK => '0', -- in std_ulogic;
SAXIHP3ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP3ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP3ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP3ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3ARVALID => '0', -- in std_ulogic;
SAXIHP3AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP3AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP3AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP3AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3AWVALID => '0', -- in std_ulogic;
SAXIHP3BREADY => '0', -- in std_ulogic;
SAXIHP3RDISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP3RREADY => '0', -- in std_ulogic;
SAXIHP3WDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIHP3WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP3WLAST => '0', -- in std_ulogic;
SAXIHP3WRISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP3WSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIHP3WVALID => '0' -- in std_ulogic
);
end RTL; | gpl-3.0 |
johnmurrayvi/vhdl-projects | Hex2SSeg_Controller/Part2-Separate/Part2-A/Hex4Digs2SSeg.vhd | 1 | 1995 | ------------------------------------------------
-- Module Name: Hex4Digs2SSeg - behavioral --
------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Hex4Dig2SSeg_Package.all;
entity Hex4Digs2SSeg is
port (
clock : in std_logic; -- Input clock
incr : in std_logic_vector (3 downto 0); -- Increment digits
anodes : out std_logic_vector (3 downto 0); -- Anodes for display
cathodes : out std_logic_vector (7 downto 0) -- Cathodes for segments
);
end Hex4Digs2SSeg;
architecture behavioral of Hex4Digs2SSeg is
signal dsel : std_logic_vector (1 downto 0) := "00"; -- Display select
signal hx0, hx1, hx2, hx3 : std_logic_vector (3 downto 0) := "0000"; -- Hex digits
signal sg0, sg1, sg2, sg3 : std_logic_vector (7 downto 0) := "11111111"; -- Segments
begin
-- Get 4 Hex digits and assign their segments
dig0: HexD2SSeg port map (hx0, sg0);
dig1: HexD2SSeg port map (hx1, sg1);
dig2: HexD2SSeg port map (hx2, sg2);
dig3: HexD2SSeg port map (hx3, sg3);
hx0 <= hx0 + 1 when incr(0) = '1' else hx0;
hx1 <= hx1 + 1 when incr(1) = '1' else hx1;
hx2 <= hx2 + 1 when incr(2) = '1' else hx2;
hx3 <= hx3 + 1 when incr(3) = '1' else hx3;
process (clock) -- choose output display with dsel
begin
if (clock'event and clock = '1') then
case dsel is
when "00" =>
cathodes <= sg0;
anodes <= "0111";
when "01" =>
cathodes <= sg1;
anodes <= "1011";
when "10" =>
cathodes <= sg2;
anodes <= "1101";
when others =>
cathodes <= sg3;
anodes <= "1110";
end case;
dsel <= dsel - 1;
end if;
end process;
end behavioral;
| gpl-3.0 |
johnmurrayvi/vhdl-projects | Hex2SSeg_Controller/Part1/Hex2SSegDecoder.vhd | 3 | 1299 | ---------------------------------------
-- Module Name: Hex2SSeg - decode --
---------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Hex2SSeg is
port (
-- 4 bit number to represent one hex digit
HexChar : in std_logic_vector (3 downto 0);
-- 8 bit signal output corresponding to the hex digit
Segments : out std_logic_vector (7 downto 0)
);
end Hex2SSeg;
architecture decode of Hex2SSeg is
begin
with HexChar select
Segments <= "11000000" when "0000", -- 0
"11111001" when "0001", -- 1
"10100100" when "0010", -- 2
"10110000" when "0011", -- 3
"10011001" when "0100", -- 4
"10010010" when "0101", -- 5
"10000010" when "0110", -- 6
"11111000" when "0111", -- 7
"10000000" when "1000", -- 8
"10010000" when "1001", -- 9
"10001000" when "1010", -- A
"10000011" when "1011", -- b
"11000110" when "1100", -- C
"10100001" when "1101", -- d
"10000110" when "1110", -- E
"10001110" when others; -- F
end decode;
| gpl-3.0 |
johnmurrayvi/vhdl-projects | Hex2SSeg_Controller/Part2-Separate/Part2-B/Hex4Digs_2_SSEG_Package.vhd | 1 | 1582 | ----------------------------------------------
-- Package Name: Hex4Digs_2_SSEG_Package --
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package Hex4Digs_2_SSEG_Package is
-- 4 hex digits on SSeg displays
component Hex4Digs_2_SSeg is
port ( clock : in std_logic; -- Input clock
sw0 : in std_logic; -- Switch to control clock
incr : in std_logic_vector (3 downto 0); -- Buttons to increment digits
anodes : out std_logic_vector (3 downto 0); -- Anodes for display
cathodes : out std_logic_vector (7 downto 0)); -- Cathodes for segments
end component;
-- Use debounce pulses from buttons
component HexBtns is
port ( clk : in std_logic;
btns : in std_logic_vector (3 downto 0);
pulse : out std_logic_vector (3 downto 0));
end component;
-- Control clock with switch, either 1KHz or 5Hz
component ClockController is
port ( clock : in std_logic;
sw0 : in std_logic;
clk : out std_logic);
end component;
-- Hex to SSeg decoder
component Hex2SSeg is
port ( HexChar : in std_logic_vector (3 downto 0);
Segments : out std_logic_vector (7 downto 0));
end component;
-- Clock Divider with TC input
component CDiv is
port ( Cin : in std_logic;
TCvl : in integer;
Cout : out std_logic);
end component;
end Hex4Digs_2_SSEG_Package;
| gpl-3.0 |
johnmurrayvi/vhdl-projects | Hex2SSeg_Controller/Part2/HexDigSSegCntrl.vhd | 1 | 2821 | -----------------------------------------------
-- Module Name: HexDigSSegCntrl - control --
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity HexDigSSegCntrl is
port ( clock : in std_logic;
sws : in std_logic_vector (2 downto 0);
anodes : out std_logic_vector (3 downto 0);
cathodes : out std_logic_vector (7 downto 0));
end HexDigSSegCntrl;
architecture control of HexDigSSegCntrl is
signal cntr : std_logic_vector (3 downto 0);
signal sw0 : std_logic;
signal csws : std_logic_vector (1 downto 0);
signal en : std_logic;
signal clk : std_logic;
constant TC5Hz : integer := 56; -- TC for 5 Hz clock
constant TC16Hz : integer := 42; -- TC for 16 Hz clock
constant TC30Hz : integer := 36; -- TC for 30 Hz clock
constant TC312Hz : integer := 20; -- TC for 312 Hz clock
signal clk5Hz : std_logic := '0'; -- 5Hz clock
signal clk16Hz : std_logic := '0'; -- 16Hz clock
signal clk30Hz : std_logic := '0'; -- 30Hz clock
signal clk312Hz : std_logic := '0'; -- 312Hz clock
signal c0, c1, c2, c3 : integer range 0 to 15;
begin
sw0 <= sws(0);
csws(0) <= sws(1);
csws(1) <= sws(2);
c5Hz: CDiv port map (clock, TC5Hz, clk5Hz);
c16Hz: CDiv port map (clock, TC16Hz, clk16Hz);
c30Hz: CDiv port map (clock, TC30Hz, clk30Hz);
c312Hz: CDiv port map (clock, TC312Hz, clk312Hz);
HexDs: Hex4Digs_2_SSeg port map (clock, clk, sw0, cntr, anodes, cathodes);
process (csws, clk5Hz, clk16Hz, clk30Hz, clk312Hz) -- control clocks
begin
case csws is
when "00" =>
clk <= clk5Hz;
when "01" =>
clk <= clk16Hz;
when "10" =>
clk <= clk30Hz;
when others =>
clk <= clk312Hz;
end case;
end process;
process (clk)
begin
if rising_edge(clk) then
en <= not en;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if en = '1' then
c0 <= c0 + 1;
cntr(0) <= '1';
if (c0 = 15) then
c1 <= c1 + 1;
cntr(1) <= '1';
if (c1 = 15) then
c2 <= c2 + 1;
cntr(2) <= '1';
if (c2 = 15) then
c3 <= c3 + 1;
cntr(3) <= '1';
end if;
end if;
end if;
else
cntr <= "0000";
end if;
end if;
end process;
end control;
| gpl-3.0 |
johnmurrayvi/vhdl-projects | Hex2SSeg_Controller/Part2-Separate/Part2-A/debounce.vhd | 1 | 896 | --------------------------------------------
-- Module Name: debounce - clean_pulse --
--------------------------------------------
-- Button debounce circuit;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity debounce is
port (
clk : in std_logic; -- make it low frequency
key : in std_logic; -- active low input
pulse : out std_logic
);
end debounce;
architecture clean_pulse of debounce is
signal cnt : std_logic_vector (1 downto 0);
begin
process (clk,key)
begin
if key = '1' then
cnt <= "00";
elsif (clk'event and clk = '1') then
if (cnt /= "11") then cnt <= cnt + 1; end if;
end if;
if (cnt = "10") and (key = '0') then
pulse <= '1';
else
pulse <= '0';
end if;
end process;
end clean_pulse;
| gpl-3.0 |
tejainece/VHDLExperiments | FloatingPointMul23/HalfAdder.vhd | 1 | 1061 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:08:15 11/19/2013
-- Design Name:
-- Module Name: HalfAdder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.MyTypes.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity HalfAdder is
port( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
end HalfAdder;
architecture Behavioral of HalfAdder is
begin
s <= a xor b;
c <= a and b;
end Behavioral;
| gpl-3.0 |
marc0l92/RadioFM_FPGA | RadioFM_project/top_radio.vhd | 1 | 3213 | --Simple FM Transmitter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fm_xmit is
Port ( clk_in : in STD_LOGIC;
antenna, led : out STD_LOGIC);
end fm_xmit;
architecture Behavioral of fm_xmit is
component clk_wiz_v3_6 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
signal clk320 : std_logic;
signal rst_in : std_logic;
signal locked_int : std_logic;
signal shift_ctr : unsigned (1 downto 0) := (others => '0');
signal phase_accumulator : unsigned (31 downto 0) := (others => '0');
signal beep_counter : unsigned (23 downto 0):= (others => '0'); -- gives a 305Hz beep signal
-- signal message : std_logic_vector(33 downto 0) := "1111100011101110111000111110000000";
signal code : unsigned (4 downto 0) := (others => '0');
signal message_id : unsigned (1 downto 0) := (others => '0');
-- signal message : std_logic_vector(33 downto 0) := "0000000000000000000000000000000000";
-- signal message : std_logic_vector(33 downto 0) := "0101010101010101010101010101010101";
-- signal message : std_logic_vector(135 downto 0):= "0101010101010101010101010101010101110011001100110011001100110011001111110000111100001111000011110000001010111010101110101011101010111010";
-- 1100110011001100110011001100110011
-- 1111000011110000111100001111000000
-- 1010111010101110101011101010111010
signal message : std_logic_vector(135 downto 0):= "0101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101011111";
begin
led<='1'; --led 0 acceso
antenna <= std_logic(phase_accumulator(31));
clknetwork : clk_wiz_v3_6
port map
(-- Clock in ports
CLK_IN1 => clk_in,
-- Clock out ports
CLK_OUT1 => clk320,
-- Status and control signals
RESET => rst_in,
LOCKED => locked_int);
process(clk320)
begin
if rising_edge(clk320) then
if beep_counter = x"FFFFFF" then
if shift_ctr = "00" then
message <= message(0) & message(135 downto 1);
end if;
shift_ctr <= shift_ctr + 1;
end if;
-- The constants are calculated as (desired freq)/320Mhz*2^32
if message(0) = '1' then
if (beep_counter(17) = '1') and (beep_counter(18) = '1')and (beep_counter(19) = '1') then
phase_accumulator <= phase_accumulator + 1222387958; -- gives a 91075kHz signal
else
phase_accumulator <= phase_accumulator + 1220374692; -- gives 90925kHz signal
end if;
else
phase_accumulator <= phase_accumulator + 1221381325; -- gives 91000kHz signal
end if;
beep_counter <= beep_counter+1;
end if;
end process;
end Behavioral;
| gpl-3.0 |
johnmurrayvi/vhdl-projects | PS2_Mouse/MouseRefComp.vhd | 1 | 3619 | ----------------------------------------------------------------------------------
-- Company: Digilent RO
-- Engineer: Mircea Dabacan
--
-- Create Date: 12:57:12 03/01/2008
-- Design Name:
-- Module Name: MouseRefComp - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is the structural VHDL code of the
-- Digilent Mouse Reference Component.
-- It instantiates three components:
-- - ps2interface
-- - mouse_controller
-- - resolution_mouse_informer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.mouse_ref_pkg.all;
entity MouseRefComp is
port (
clk : in std_logic;
resolution : in std_logic;
rst : in std_logic;
switch : in std_logic;
left : out std_logic;
middle : out std_logic;
new_event : out std_logic;
right : out std_logic;
busy : out std_logic;
xpos : out std_logic_vector(9 downto 0);
ypos : out std_logic_vector(9 downto 0);
zpos : out std_logic_vector(3 downto 0);
ps2_clk : inout std_logic;
ps2_data : inout std_logic
);
end MouseRefComp;
architecture Structural of MouseRefComp is
signal TX_DATA : std_logic_vector(7 downto 0);
signal bitSetMaxX : std_logic;
signal vecValue : std_logic_vector(9 downto 0);
signal bitRead : std_logic;
signal bitWrite : std_logic;
signal bitErr : std_logic;
signal bitSetX : std_logic;
signal bitSetY : std_logic;
signal bitSetMaxY : std_logic;
signal vecRxData : std_logic_vector(7 downto 0);
begin
MouseCtrlInst : mouse_controller
port map (
clk => clk,
rst => rst,
read => bitRead,
write => bitWrite,
err => bitErr,
setmax_x => bitSetMaxX,
setmax_y => bitSetMaxY,
setx => bitSetX,
sety => bitSetY,
value(9 downto 0) => vecValue(9 downto 0),
rx_data(7 downto 0) => vecRxData(7 downto 0),
tx_data(7 downto 0) => TX_DATA(7 downto 0),
left => left,
middle => middle,
right => right,
xpos(9 downto 0) => xpos(9 downto 0),
ypos(9 downto 0) => ypos(9 downto 0),
zpos(3 downto 0) => zpos(3 downto 0),
new_event => new_event
);
ResMouseInfInst : resolution_mouse_informer
port map (
clk => clk,
resolution => resolution,
rst => rst,
switch => switch,
setmax_x => bitSetMaxX,
setmax_y => bitSetMaxY,
setx => bitSetX,
sety => bitSetY,
value(9 downto 0) => vecValue(9 downto 0)
);
Pss2Inst : ps2interface
port map (
clk => clk,
rst => rst,
tx_data(7 downto 0) => TX_DATA(7 downto 0),
read => bitRead,
write => bitWrite,
busy => busy,
err => bitErr,
rx_data(7 downto 0) => vecRxData(7 downto 0),
ps2_clk => ps2_clk,
ps2_data => ps2_data
);
end Structural;
| gpl-3.0 |
amof/fpga-pong | VGA.vhd | 1 | 1708 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY VGA IS
-----SYNC PARAMETERS FOR 640x480 VGA DISPLAY (25MHz clock)-----
GENERIC(
Ha: INTEGER:=96; -- Hpulse
Hb: INTEGER:=143; -- Hpulse+Hbp
Hc: INTEGER:=783; -- Hpulse+Hbp+Hactive
Hd: INTEGER:=800; -- Hpulse+Hbp+Hactive+Hfp
Va: INTEGER:=2; -- Vpulse
Vb: INTEGER:=35; -- Vpulse+Vbp
Vc: INTEGER:=515; -- Vpulse+Vbp+Vactive
Vd: INTEGER:=525); -- Vpulse+Vbp+Vactive+Vfp
PORT(
CLK_VGA : IN STD_LOGIC;
Hsync,Vsync : BUFFER STD_LOGIC;
BLANK,SYNC : BUFFER STD_LOGIC;
Xcnt, Ycnt : OUT INTEGER
);
END VGA;
ARCHITECTURE MAIN OF VGA IS
SIGNAL Hactive, Vactive: STD_LOGIC;
BEGIN
---------------------------------
-- CONTROL GENERATOR --
---------------------------------
-- Static signals for DACs:
BLANK <= Hactive AND Vactive;
SYNC <= '0';
-- Horizontal signal generation
PROCESS(CLK_VGA)
VARIABLE Hcnt: INTEGER RANGE 0 TO Hd;
BEGIN
IF RISING_EDGE(CLK_VGA) THEN
Hcnt:=Hcnt+1;
IF (Hcnt=Ha)THEN
Hsync<='1';
ELSIF(Hcnt=Hb) THEN
Hactive<='1';
ELSIF(Hcnt=Hc) THEN
Hactive<='0';
ELSIF(Hcnt=Hd) THEN
Hsync<='0';
Hcnt:=0;
END IF;
IF (Hcnt>=Hb AND Hcnt<Hc) THEN
Xcnt<=Hcnt-Hb; -- Xcnt 0 --> 639
ELSE
Xcnt<=0;
END IF;
END IF;
END PROCESS;
-- Vertical signal generation
PROCESS(Hsync)
VARIABLE Vcnt: INTEGER RANGE 0 TO Vd;
BEGIN
IF FALLING_EDGE(Hsync) THEN
Vcnt:=Vcnt+1;
IF (Vcnt=Va)THEN
Vsync<='1';
ELSIF(Vcnt=Vb) THEN
Vactive<='1';
ELSIF(Vcnt=Vc) THEN
Vactive<='0';
ELSIF(Vcnt=Vd) THEN
Vsync<='0';
Vcnt:=0;
END IF;
IF (Vcnt>=Vb AND Vcnt<Vc) THEN
Ycnt<=Vcnt-Vb; -- Ycnt 0 --> 479
ELSE
Ycnt<=0;
END IF;
END IF;
END PROCESS;
END MAIN; | gpl-3.0 |
amof/fpga-pong | BUTTONS.vhd | 1 | 1487 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ENTITY BUTTONS IS PORT
(
BOUTONS : IN unsigned(3 downto 0);
UP, DOWN : OUT STD_LOGIC;
UPd, DOWNd : OUT STD_LOGIC;
--------SYSTEMS signals
RST_N : IN STD_LOGIC;
MCLK : IN STD_LOGIC
);
END BUTTONS;
ARCHITECTURE ARCH of BUTTONS IS
SIGNAL PREC_BOUTON0 : STD_LOGIC;
SIGNAL PREC_BOUTON1 : STD_LOGIC;
SIGNAL PREC_BOUTON2 : STD_LOGIC;
SIGNAL PREC_BOUTON3 : STD_LOGIC;
begin
PROCESS (MCLK, RST_N)
VARIABLE timeCount : integer;
BEGIN
IF RST_N='0' THEN
UP<='0';
DOWN<='0';
UPd<='0';
DOWNd<='0';
timeCount := 0;
PREC_BOUTON0<='0';
PREC_BOUTON1<='0';
PREC_BOUTON2<='0';
PREC_BOUTON3<='0';
ELSE
IF rising_edge(MCLK) THEN
timeCount := timeCount+1;
IF timeCount = 999999 THEN
timeCount:=0;
PREC_BOUTON0 <= BOUTONS(0);
PREC_BOUTON1 <= BOUTONS(1);
PREC_BOUTON2 <= BOUTONS(2);
PREC_BOUTON3 <= BOUTONS(3);
IF BOUTONS(0)='0' AND (PREC_BOUTON0 = '0' or PREC_BOUTON0 = '1') THEN
UPd<='1';
END IF;
IF (BOUTONS(1)='0') AND (PREC_BOUTON1 = '0' or PREC_BOUTON1 = '1') THEN
DOWNd<='1';
END IF;
IF BOUTONS(2)='0' AND (PREC_BOUTON2 = '0' or PREC_BOUTON2 = '1') THEN
UP<='1';
END IF;
IF (BOUTONS(3)='0') AND (PREC_BOUTON3 = '0' or PREC_BOUTON3 = '1') THEN
DOWN<='1';
END IF;
ELSE
UP<='0';
DOWN<='0';
UPd<='0';
DOWNd<='0';
END IF;
END IF;
END IF;
END PROCESS;
END ARCH; | gpl-3.0 |
zpekic/tinycomputer | bcdadder.vhd | 1 | 1477 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:52:18 11/16/2016
-- Design Name:
-- Module Name: bcdadder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bcdadder is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end bcdadder;
architecture Behavioral of bcdadder is
signal raw_sum, adjusted_sum: std_logic_vector(5 downto 0);
begin
raw_sum <= std_logic_vector(unsigned('0' & a & cin) + unsigned('0' & b & cin));
adjusted_sum <= raw_sum when (raw_sum < "010100") else std_logic_vector(unsigned(raw_sum) + "001100");
sum <= adjusted_sum(4 downto 1);
cout <= adjusted_sum(5);
end Behavioral;
| gpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemWinner/dist_mem_gen_v8_0/hdl/dist_mem_gen_v8_0_vh_rfs.vhd | 5 | 40066 | `protect begin_protected
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ozkapLlzFuEloLVBobAI9SQyggmQnBgNSW3jK8RPIqkM9KZKcHmbZ0TpgpMH2hQ=
`protect end_protected
| gpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/imports/VHDL/Initialize.vhd | 1 | 16385 | ---A bulky Synchronous Fsm that scans the whole map and places the numbers around the mines
--- its divided in 9 state chains based on the position type of the tile.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Initialize is
port( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Random_Done : in Std_Logic;
Data_in : in STD_LOGIC_VECTOR (4 downto 0);
Request_Set : out STD_LOGIC;
X_out : out STD_LOGIC_VECTOR (4 downto 0);
Y_out : out STD_LOGIC_VECTOR (4 downto 0);
Data_out : out STD_LOGIC_VECTOR (4 downto 0);
Done : out STD_LOGIC);
end Initialize;
architecture Behavioral of Initialize is
signal x_temp: unsigned (4 downto 0):="00001";
signal y_temp: unsigned (4 downto 0):="00001";
signal set_temp: STD_LOGIC:='0';
signal sum_temp: unsigned(3 downto 0):="0000";
signal done_sig: STD_LOGIC:='0';
---------------------------------------------------------------------------STATES
Type State_type is
(Zero_st,First_st,Idle1_st,A_st,B_st,C_St,Idle2_st,Done_st,Evaluate_st,Evaluate_st2,--10
UL_st1,UL_st2,UL_st3,UL_st4,UL_st5,
UR_st1,UR_st2,UR_st3,UR_st4,UR_st5,--20
U_st1,U_st2,U_st3,U_st4,U_st5,U_st6,U_st7,
BL_st1,BL_st2,BL_st3,BL_st4,BL_st5,
BR_st1,BR_st2,BR_st3,BR_st4,BR_st5,--37
B_st1,B_st2,B_st3,B_st4,B_st5,B_st6,B_st7,--44
L_st1,L_st2,L_st3,L_st4,L_st5,L_st6,L_st7,--51
R_st1,R_st2,R_st3,R_st4,R_st5,R_st6,R_st7,--58
C_st1,C_st2,C_st3,C_st4,C_st5,C_st6,C_st7,C_st8,C_st9,C_st10);--68 STATES !
Signal state: State_type:=(Zero_st);
begin
Done <= done_sig;
process
begin
WAIT UNTIL Clk'event AND Clk='1';
If Reset='1' then
----REQUEST SET
set_temp<='0';
done_sig<='0';
sum_temp<="0000";
x_temp<="00001";
y_temp<="00001";
state<=Zero_st;
else
Case state is
When Zero_st=>
if (Random_Done='1') then
state<=First_st;
else
state<=Zero_st;
end if;
When First_st=>
x_temp<="00001";
y_temp<="00001";
-------------------------save coordinates
state<=Idle1_st;
When Idle1_st =>
sum_temp<="0000";
----REQUEST SET
set_temp<='0';
x_temp<= x_temp;
y_temp<=y_temp;
state<=A_st;
When A_st=>
state<=B_st;
When B_st=>
state<= C_st;
When C_st=>
If (Data_in="01111") then--if there is bomb do nothing. change tile and go to Idle state again
If(y_temp=20)then
if(x_temp=20)then
done_sig<='1';
state<=Done_st;
else
x_temp<=x_temp+1;
y_temp<="00001";
state<=Idle1_st;
end if;
else
y_temp<=y_temp+1;
state<=Idle1_st;
end if;
else
state<=Idle2_st;------- if no bomb then empty cell. evaluate and go to idle 2
end if;
When Idle2_st=>
x_temp<=x_temp;
y_temp<=y_temp;
If (x_temp="00001") then -------------1st row
If(y_temp="00001")then------------1st column
state<=UL_st1;--(1,1)
elsif (y_temp=20) then------------last col
state<=UR_st1;--(1,20)
else
state<=U_st1;--(1,whatever)
end if;
elsif (x_temp=20) then------------last row
If(y_temp="00001")then
state<=BL_st1;--(20,1)
elsif (y_temp=20) then
state<=BR_st1;--(20,20)
else
state<=B_st1;--(20,whatever)
end if;
else
If(y_temp="00001")then
state<=L_st1;
elsif (y_temp=20) then
state<=R_st1;
else
state<=C_st1;
end if;
end if;
When UL_st1=>--------------------------------------------------------------------------------------------------------------UPPER LEFT
x_temp<=x_temp;
y_temp<=y_temp+1;
state<=UL_st2;
When UL_st2=>
y_temp<=y_temp;
x_temp<=x_temp+1;
state<= UL_st3;
When UL_st3=>
x_temp<=x_temp;
y_temp<=y_temp-1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= UL_st4;
When UL_st4=>
y_temp<=y_temp;
x_temp<=x_temp-1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<=UL_st5;
When UL_st5=>
y_temp<=y_temp;
x_temp<=x_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<=Evaluate_st;
When Evaluate_st=>-----------------------------------------------------------------------------------------------------EVALUATE
----REQUEST SET
sum_temp<=sum_temp;
set_temp<='1';
state<=Evaluate_st2;
When Evaluate_st2=>
----REQUEST SET
set_temp<='0';
If(y_temp=20)then
if(x_temp=20)then
done_sig<='1';
state<=Done_st;
else
x_temp<=x_temp+1;
y_temp<="00001";
state<=Idle1_st;
end if;
else
y_temp<=y_temp+1;
state<=Idle1_st;
end if;
When U_st1=>----------------------------------------------------------------------------------------------UPPER
y_temp<=y_temp+1;
x_temp<=x_temp;
state<=U_st2;
When U_st2=>
y_temp<=y_temp;
x_temp<=x_temp+1;
state<= U_st3;
When U_st3=>
y_temp<=y_temp-1;
x_temp<=x_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= U_st4;
When U_st4=>
y_temp<=y_temp-1;
x_temp<=x_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= U_st5;
When U_st5=>
x_temp<=x_temp-1;
y_temp<=y_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= U_st6;
When U_st6=>
x_temp<=x_temp;
y_temp<=y_temp+1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= U_st7;
When U_st7=>
x_temp<=x_temp;
y_temp<=y_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= Evaluate_st;
When UR_st1=>--------------------------------------------------------------------------------------------------------------UPPER RIGHT
x_temp<=x_temp+1;
y_temp<=y_temp;
state<=UR_st2;
When UR_st2=>
y_temp<=y_temp-1;
x_temp<=x_temp;
state<= UR_st3;
When UR_st3=>
x_temp<=x_temp-1;
y_temp<=y_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= UR_st4;
When UR_st4=>
y_temp<=y_temp+1;
x_temp<=x_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<=UR_st5;
When UR_st5=>
y_temp<=y_temp;
x_temp<=x_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<=Evaluate_st;
When L_st1=>----------------------------------------------------------------------------------------------LEFT
y_temp<=y_temp;
x_temp<=x_temp-1;
state<=L_st2;
When L_st2=>
y_temp<=y_temp+1;
x_temp<=x_temp;
state<= L_st3;
When L_st3=>
y_temp<=y_temp;
x_temp<=x_temp+1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= L_st4;
When L_st4=>
y_temp<=y_temp;
x_temp<=x_temp+1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= L_st5;
When L_st5=>
x_temp<=x_temp;
y_temp<=y_temp-1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= L_st6;
When L_st6=>
x_temp<=x_temp-1;
y_temp<=y_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= L_st7;
When L_st7=>
x_temp<=x_temp;
y_temp<=y_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= Evaluate_st;
When C_st1=>----------------------------------------------------------------------------------------------CENTRE
y_temp<=y_temp+1;
x_temp<=x_temp;
state<=C_st2;
When C_st2=>
y_temp<=y_temp;
x_temp<=x_temp+1;
state<= C_st3;
When C_st3=>
y_temp<=y_temp-1;
x_temp<=x_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= C_st4;
When C_st4=>
y_temp<=y_temp-1;
x_temp<=x_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= C_st5;
When C_st5=>
x_temp<=x_temp-1;
y_temp<=y_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= C_st6;
When C_st6=>
x_temp<=x_temp-1;
y_temp<=y_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= C_st7;
When C_st7=>
x_temp<=x_temp;
y_temp<=y_temp+1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<=C_st8;
When C_st8=>
x_temp<=x_temp;
y_temp<=y_temp+1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<=C_st9;
When C_st9=>
x_temp<=x_temp+1;
y_temp<=y_temp-1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<=C_st10;
When C_st10=>
x_temp<=x_temp;
y_temp<=y_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= Evaluate_st;
When R_st1=>----------------------------------------------------------------------------------------------RIGHT
y_temp<=y_temp;
x_temp<=x_temp+1;
state<=R_st2;
When R_st2=>
y_temp<=y_temp-1;
x_temp<=x_temp;
state<= R_st3;
When R_st3=>
y_temp<=y_temp;
x_temp<=x_temp-1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= R_st4;
When R_st4=>
y_temp<=y_temp;
x_temp<=x_temp-1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= R_st5;
When R_st5=>
x_temp<=x_temp;
y_temp<=y_temp+1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= R_st6;
When R_st6=>
x_temp<=x_temp+1;
y_temp<=y_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= R_st7;
When R_st7=>
x_temp<=x_temp;
y_temp<=y_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= Evaluate_st;
When BL_st1=>--------------------------------------------------------------------------------------------------------------BOTTOM LEFT
x_temp<=x_temp-1;
y_temp<=y_temp;
state<=BL_st2;
When BL_st2=>
y_temp<=y_temp+1;
x_temp<=x_temp;
state<= BL_st3;
When BL_st3=>
x_temp<=x_temp+1;
y_temp<=y_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= BL_st4;
When BL_st4=>
y_temp<=y_temp-1;
x_temp<=x_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<=BL_st5;
When BL_st5=>
y_temp<=y_temp;
x_temp<=x_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<=Evaluate_st;
When B_st1=>----------------------------------------------------------------------------------------------BOTTOM
y_temp<=y_temp-1;
x_temp<=x_temp;
state<=B_st2;
When B_st2=>
y_temp<=y_temp;
x_temp<=x_temp-1;
state<= B_st3;
When B_st3=>
y_temp<=y_temp+1;
x_temp<=x_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= B_st4;
When B_st4=>
y_temp<=y_temp+1;
x_temp<=x_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= B_st5;
When B_st5=>
x_temp<=x_temp+1;
y_temp<=y_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= B_st6;
When B_st6=>
x_temp<=x_temp;
y_temp<=y_temp-1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= B_st7;
When B_st7=>
x_temp<=x_temp;
y_temp<=y_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= Evaluate_st;
When BR_st1=>--------------------------------------------------------------------------------------------------------------BOTTOM RIGHT
x_temp<=x_temp;
y_temp<=y_temp-1;
state<=BR_st2;
When BR_st2=>
y_temp<=y_temp;
x_temp<=x_temp-1;
state<= BR_st3;
When BR_st3=>
x_temp<=x_temp;
y_temp<=y_temp+1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<= BR_st4;
When BR_st4=>
y_temp<=y_temp;
x_temp<=x_temp+1;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<=BR_st5;
When BR_st5=>
y_temp<=y_temp;
x_temp<=x_temp;
If (Data_in="01111") then
sum_temp<=sum_temp+1;
else
sum_temp<=sum_temp;
end if;
state<=Evaluate_st;
When Done_st=>------------------------------------------------------------------------------------------------DONE
----REQUEST SET
set_temp<='0';
done_sig<='1';
state<=Done_st;
when others=>NULL;
end case;
end if;
end process;
-----------------
Request_set<=set_temp;
Data_out<="0"&STD_LOGIC_VECTOR(sum_temp);--- set everything into unexplored whatever
X_out<=STD_LOGIC_VECTOR(x_temp);
Y_out<=STD_LOGIC_VECTOR(y_temp);
end Behavioral; | gpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/imports/VHDL/ToPixelScore.vhd | 1 | 1112 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ToPixelScore is
Port (
DataIn : in STD_LOGIC_VECTOR (11 downto 0);
Column : in STD_LOGIC_VECTOR (4 downto 0);
PixelOut : out STD_LOGIC
);
end ToPixelScore;
architecture Behavioral of ToPixelScore is
begin
---- Select pixel data in accordance to column
process(DataIn,Column)
begin
if Column = "00001" then
PixelOut <= DataIn(11);
elsif
Column = "00010" then
PixelOut <= DataIn(10);
elsif
Column = "00011" then
PixelOut <= DataIn(9);
elsif
Column = "00100" then
PixelOut <= DataIn(8);
elsif
Column = "00101" then
PixelOut <= DataIn(7);
elsif
Column = "00110" then
PixelOut <= DataIn(6);
elsif
Column = "00111" then
PixelOut <= DataIn(5);
elsif
Column = "01000" then
PixelOut <= DataIn(4);
elsif
Column = "01001" then
PixelOut <= DataIn(3);
elsif
Column = "01010" then
PixelOut <= DataIn(2);
elsif
Column = "01011" then
PixelOut <= DataIn(1);
elsif
Column = "01100" then
PixelOut <= DataIn(0);
end if;
end process;
end Behavioral;
| gpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/imports/VHDL/Reset_Mode.vhd | 1 | 1718 | ---------------Reset the contents of the Map to border and empty unexplored cell encoding
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Reset_Module is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Request_Set : out STD_LOGIC;
X_out : out STD_LOGIC_VECTOR (4 downto 0);
Y_out : out STD_LOGIC_VECTOR (4 downto 0);
Data_out : out STD_LOGIC_VECTOR (4 downto 0)
);
end Reset_Module;
architecture Behavioral of Reset_Module is
------
signal x_temp: unsigned (4 downto 0):="00000";
signal y_temp: unsigned (4 downto 0):="00000";
signal set_temp: STD_LOGIC:='0';
Type State_type is
(Fill,Move);
signal state:State_type:=(Fill);
begin
process
begin
Wait until Clk'event AND Clk='1';
If Reset='0' then-----------------------EINAI TO ANAPODO. KATALAVATE ?
x_temp<="00000";
y_temp<="00000";
set_temp<='0';
state<=Fill;
else
Case state is
When Fill=>
set_temp<='1';
If (x_temp=0) then
Data_out<="11011";
elsif (x_temp=21) then
Data_out<="11011";
else
If (y_temp=0) then
Data_out<="11011";
elsif (y_temp=21) then
Data_out<="11011";
else
Data_out<="00000";
end if;
end if;
state<=Move;
When Move =>
set_temp<='0';
If (y_temp=21) then
if (x_temp=21) then
x_temp<="00000";
y_temp<="00000";
else
x_temp<=x_temp+1;
y_temp<="00000";
end if;
else
y_temp<=y_temp+1;
end if;
state<=Fill;
When others=> NULL;
end case;
end if;
end process;
X_out<=STD_LOGIC_VECTOR(x_temp);
Y_out<=STD_LOGIC_VECTOR(y_temp);
Request_set<=set_temp;
end Behavioral;
| gpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/imports/VHDL/BlockRamGrid.vhd | 1 | 1892 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BlockRamGrid is
Port (
Clock : in STD_LOGIC;
Set : in STD_LOGIC;
X_Control : in STD_LOGIC_VECTOR (4 downto 0);
Y_Control : in STD_LOGIC_VECTOR (4 downto 0);
DataIn : in STD_LOGIC_VECTOR (4 downto 0);
X_Graphics : in STD_LOGIC_VECTOR (4 downto 0);
Y_Graphics : in STD_LOGIC_VECTOR (4 downto 0);
DataOutControl : out STD_LOGIC_VECTOR (4 downto 0);
DataOutGraphics : out STD_LOGIC_VECTOR (4 downto 0)
);
end BlockRamGrid;
architecture Behavioral of BlockRamGrid is
component CoordToAddr
Port (
X : in STD_LOGIC_VECTOR (4 downto 0);
Y : in STD_LOGIC_VECTOR (4 downto 0);
Output : out STD_LOGIC_VECTOR (8 downto 0)
);
end component;
component Mem
PORT (
a : IN STD_LOGIC_VECTOR(8 DOWNTO 0); --Address from Control
d : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --DataIn
dpra : IN STD_LOGIC_VECTOR(8 DOWNTO 0); --Address from Graphics
clk : IN STD_LOGIC;
we : IN STD_LOGIC; --Set
spo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --DataOutControl
dpo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) --DataOutGraphics
);
END component;
signal OutputControl_signal : std_logic_vector(8 downto 0);
signal OutputGraphics_signal : std_logic_vector(8 downto 0);
signal RegOut_signal : std_logic_vector(4 downto 0);
begin
CoordToAddr_Control: CoordToAddr port map(
X => X_Control,
Y => Y_Control,
Output => OutputControl_signal
);
CoordToAddr_Graphics:CoordToAddr port map(
X => X_Graphics,
Y => Y_Graphics,
Output => OutputGraphics_signal
);
CORE:Mem port map(
a => OutputControl_signal,
d => DataIn,
dpra => OutputGraphics_signal,
clk => Clock,
we => Set,
spo => DataOutControl,
dpo => DataOutGraphics
);
end Behavioral;
| gpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Pointer/Pointer_funcsim.vhdl | 1 | 46110 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
-- Date : Tue Jun 30 15:35:47 2015
-- Host : Vangelis-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Pointer/Pointer_funcsim.vhdl
-- Design : Pointer
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Pointer_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 27 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Pointer_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end Pointer_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of Pointer_blk_mem_gen_prim_wrapper_init is
signal \n_0_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_16_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_24_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_32_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_33_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_34_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_35_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_8_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"7F7F00007F7C00007F7000007F4000007E0000007C0000007000000040000000",
INIT_01 => X"7F7F7F7E7F7F7F7E7F7F7F787F7F7F607F7F7F007F7F7E007F7F78007F7F6000",
INIT_02 => X"7F7C00007F7F00007F7F60007F7F78007F7F7E007F7F7F407F7F7F607F7F7F78",
INIT_03 => X"000000000000000040000000700000007C0000007F0000007F4000007F700000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13) => '0',
ADDRARDADDR(12) => '0',
ADDRARDADDR(11) => '0',
ADDRARDADDR(10) => '0',
ADDRARDADDR(9 downto 5) => addra(4 downto 0),
ADDRARDADDR(4) => '0',
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9 downto 5) => addra(4 downto 0),
ADDRBWRADDR(4) => '1',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15) => \n_0_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
DOADO(14 downto 8) => douta(13 downto 7),
DOADO(7) => \n_8_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
DOADO(6 downto 0) => douta(6 downto 0),
DOBDO(15) => \n_16_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
DOBDO(14 downto 8) => douta(27 downto 21),
DOBDO(7) => \n_24_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
DOBDO(6 downto 0) => douta(20 downto 14),
DOPADOP(1) => \n_32_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
DOPADOP(0) => \n_33_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
DOPBDOP(1) => \n_34_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
DOPBDOP(0) => \n_35_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\,
ENARDEN => '1',
ENBWREN => '1',
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Pointer_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 27 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Pointer_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end Pointer_blk_mem_gen_prim_width;
architecture STRUCTURE of Pointer_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.Pointer_blk_mem_gen_prim_wrapper_init
port map (
addra(4 downto 0) => addra(4 downto 0),
clka => clka,
douta(27 downto 0) => douta(27 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Pointer_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 27 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Pointer_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end Pointer_blk_mem_gen_generic_cstr;
architecture STRUCTURE of Pointer_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.Pointer_blk_mem_gen_prim_width
port map (
addra(4 downto 0) => addra(4 downto 0),
clka => clka,
douta(27 downto 0) => douta(27 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Pointer_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 27 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Pointer_blk_mem_gen_top : entity is "blk_mem_gen_top";
end Pointer_blk_mem_gen_top;
architecture STRUCTURE of Pointer_blk_mem_gen_top is
begin
\valid.cstr\: entity work.Pointer_blk_mem_gen_generic_cstr
port map (
addra(4 downto 0) => addra(4 downto 0),
clka => clka,
douta(27 downto 0) => douta(27 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Pointer_blk_mem_gen_v8_2_synth is
port (
douta : out STD_LOGIC_VECTOR ( 27 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Pointer_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end Pointer_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of Pointer_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.Pointer_blk_mem_gen_top
port map (
addra(4 downto 0) => addra(4 downto 0),
clka => clka,
douta(27 downto 0) => douta(27 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Pointer_blk_mem_gen_v8_2__parameterized0\ is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
dina : in STD_LOGIC_VECTOR ( 27 downto 0 );
douta : out STD_LOGIC_VECTOR ( 27 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 27 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 27 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 4 downto 0 );
sleep : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
attribute C_FAMILY : string;
attribute C_FAMILY of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "artix7";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "artix7";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "./";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 4;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 3;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "Pointer.mif";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "Pointer.mem";
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 28;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 28;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 30;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 30;
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 5;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 28;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 28;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 30;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 30;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 5;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "1";
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 3.2088 mW";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \Pointer_blk_mem_gen_v8_2__parameterized0\ : entity is "yes";
end \Pointer_blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \Pointer_blk_mem_gen_v8_2__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(27) <= \<const0>\;
doutb(26) <= \<const0>\;
doutb(25) <= \<const0>\;
doutb(24) <= \<const0>\;
doutb(23) <= \<const0>\;
doutb(22) <= \<const0>\;
doutb(21) <= \<const0>\;
doutb(20) <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.Pointer_blk_mem_gen_v8_2_synth
port map (
addra(4 downto 0) => addra(4 downto 0),
clka => clka,
douta(27 downto 0) => douta(27 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Pointer is
port (
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
douta : out STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of Pointer : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of Pointer : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of Pointer : entity is "blk_mem_gen_v8_2,Vivado 2014.4";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of Pointer : entity is "Pointer,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of Pointer : entity is "Pointer,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=Pointer.mif,C_INIT_FILE=Pointer.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=28,C_READ_WIDTH_A=28,C_WRITE_DEPTH_A=30,C_READ_DEPTH_A=30,C_ADDRA_WIDTH=5,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=28,C_READ_WIDTH_B=28,C_WRITE_DEPTH_B=30,C_READ_DEPTH_B=30,C_ADDRB_WIDTH=5,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.2088 mW}";
end Pointer;
architecture STRUCTURE of Pointer is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 27 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 27 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 5;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 5;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.2088 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "Pointer.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "Pointer.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 3;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 30;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 30;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 28;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 28;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 30;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 30;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 28;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 28;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\Pointer_blk_mem_gen_v8_2__parameterized0\
port map (
addra(4 downto 0) => addra(4 downto 0),
addrb(4) => '0',
addrb(3) => '0',
addrb(2) => '0',
addrb(1) => '0',
addrb(0) => '0',
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
dina(27) => '0',
dina(26) => '0',
dina(25) => '0',
dina(24) => '0',
dina(23) => '0',
dina(22) => '0',
dina(21) => '0',
dina(20) => '0',
dina(19) => '0',
dina(18) => '0',
dina(17) => '0',
dina(16) => '0',
dina(15) => '0',
dina(14) => '0',
dina(13) => '0',
dina(12) => '0',
dina(11) => '0',
dina(10) => '0',
dina(9) => '0',
dina(8) => '0',
dina(7) => '0',
dina(6) => '0',
dina(5) => '0',
dina(4) => '0',
dina(3) => '0',
dina(2) => '0',
dina(1) => '0',
dina(0) => '0',
dinb(27) => '0',
dinb(26) => '0',
dinb(25) => '0',
dinb(24) => '0',
dinb(23) => '0',
dinb(22) => '0',
dinb(21) => '0',
dinb(20) => '0',
dinb(19) => '0',
dinb(18) => '0',
dinb(17) => '0',
dinb(16) => '0',
dinb(15) => '0',
dinb(14) => '0',
dinb(13) => '0',
dinb(12) => '0',
dinb(11) => '0',
dinb(10) => '0',
dinb(9) => '0',
dinb(8) => '0',
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(27 downto 0) => douta(27 downto 0),
doutb(27 downto 0) => NLW_U0_doutb_UNCONNECTED(27 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(4 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(4 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(4 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(4 downto 0),
s_axi_rdata(27 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(27 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
wea(0) => '0',
web(0) => '0'
);
end STRUCTURE;
| gpl-3.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/alt_vipvfr131_common_pulling_width_adapter.vhd | 2 | 5362 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_pulling_width_adapter is
generic (
-- all cusp function units have these
NAME : string := "";
OPTIMIZED : integer := OPTIMIZED_ON;
FAMILY : integer := FAMILY_STRATIX;
-- configuring the input and output widths
IN_WIDTH : integer := 16;
OUT_WIDTH : integer := 16
);
port (
-- cusp system clock, reset
clock : in std_logic;
reset : in std_logic;
-- interface to cusp
ena : in std_logic := '1';
-- input side
input_data : in std_logic_vector(IN_WIDTH - 1 downto 0) := (others => '0');
need_input : out std_logic;
-- output port
output_data : out std_logic_vector(OUT_WIDTH - 1 downto 0) := (others => '0');
pull : in std_logic;
pull_en : in std_logic;
discard : in std_logic;
discard_en : in std_logic
);
end entity;
architecture rtl of alt_vipvfr131_common_pulling_width_adapter is
-- the number of output words which will fit (wholly) into an input word
constant N : integer := IN_WIDTH / OUT_WIDTH;
-- enough buffers to store N output words
type buffers_type is array(integer range <>) of std_logic_vector(OUT_WIDTH - 1 downto 0);
signal buffers : buffers_type(N - 1 downto 0);
-- a counter counts how many output words we can serve without pulling from the input
signal outputs_waiting : std_logic_vector(N - 1 downto 0);
signal perform_pull : std_logic;
signal perform_pull_delay0 : std_logic;
signal perform_pull_delay1 : std_logic;
signal perform_discard : std_logic;
signal perform_discard_delay0 : std_logic;
signal perform_discard_delay1 : std_logic;
signal outputs_waiting_delay0 : std_logic;
signal outputs_waiting_delay1 : std_logic;
begin
-- check validity of inputs
assert OUT_WIDTH <= IN_WIDTH
report "Currently only narrowing output adapters are supported"
severity ERROR;
-- always output buffer zero
output_data <= buffers(0);
-- input_en is derived combinationally, but only very simply
need_input <= pull and pull_en and outputs_waiting(0);
perform_pull <= pull and pull_en;
perform_discard <= discard and discard_en;
-- every time pull is triggered the counter rotates round and:
-- if there are no words stored, input is pulled and captured
-- if there are words stored, the stored words are shifted
-- either way there should be a new word in buffers(0) on the next cycle
-- discard en just causes any outputs waiting to be discarded
respond_triggers : process (clock, reset)
begin
if reset = '1' then
buffers <= (others => (others => '0'));
outputs_waiting(0) <= '1';
outputs_waiting(N - 1 downto 1) <= (others => '0');
perform_pull_delay0 <= '0';
perform_pull_delay1 <= '0';
perform_discard_delay0 <= '0';
perform_discard_delay1 <= '0';
outputs_waiting_delay0 <= '0';
outputs_waiting_delay1 <= '0';
elsif clock'EVENT and clock = '1' then
if ena = '1' then
if perform_pull = '1' then
-- either way, rotate outputs waiting around to decrease the number of
-- outputs waiting, or replace 0 with MAX
outputs_waiting <= outputs_waiting(0) & outputs_waiting(N - 1 downto 1);
elsif perform_discard = '1' then
-- discard causes what is effectively a reset
outputs_waiting(0) <= '1';
outputs_waiting(N - 1 downto 1) <= (others => '0');
end if;
-- delay the control signals by the latency of the read (2 cycles)
perform_pull_delay0 <= perform_pull;
perform_pull_delay1 <= perform_pull_delay0;
perform_discard_delay0 <= perform_discard;
perform_discard_delay1 <= perform_discard_delay0;
outputs_waiting_delay0 <= outputs_waiting(0);
outputs_waiting_delay1 <= outputs_waiting_delay0;
if perform_pull_delay1 = '1' then
if outputs_waiting_delay1 = '1' then
-- currently no outputs waiting, so this output request will
-- have to be serviced by passing a request for a whole new
-- input word to the input port
-- driving need_input high is dealt with combinationally, so
-- all that needs to be done here is capture the resulting
-- output
-- THE ASSUMPTION IS THAT WHATEVER IS DRIVING THE INPUT HAS
-- A TRIGGER TO DATA DELAY OF ZERO
for i in 0 to N - 1 loop
buffers(i) <= input_data((i + 1) * OUT_WIDTH - 1 downto i * OUT_WIDTH);
end loop;
else
-- currently have outputs waiting, so just shift the buffers
-- around to prepare output for the next clock cycle
for i in 0 to N - 2 loop
buffers(i) <= buffers(i + 1);
end loop;
end if;
elsif perform_discard_delay1 = '1' then
-- discard causes what is effectively a reset
buffers <= (others => (others => '0'));
end if;
end if;
end if;
end process;
end architecture rtl;
| gpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/imports/VHDL/Cursor.vhd | 1 | 2769 | ---Cursor Control
---Responsible for keeping the cursor "within limits"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Cursor is
Port ( Clk : in STD_LOGIC;
Reset :in STD_LOGIC;
Up : in STD_LOGIC;
Down : in STD_LOGIC;
Left : in STD_LOGIC;
Right : in STD_LOGIC;
-- Confirm : in STD_LOGIC;
Move1 : in STD_LOGIC_vector(0 downto 0);
Move2 : in STD_LOGIC_vector(0 downto 0);
Move4 : in STD_LOGIC_vector(0 downto 0);
Move8 : in STD_LOGIC_vector(0 downto 0);
IniDone : in STD_LOGIC;
X_co : out std_logic_vector (4 downto 0);
Y_co : out std_logic_vector (4 downto 0));
end Cursor;
architecture Behavioral of Cursor is
signal x_tmp:unsigned (4 downto 0):=("00001");
signal y_tmp:unsigned (4 downto 0):=("00001");
signal Move:unsigned(3 downto 0);
signal Moves0:unsigned(0 downto 0);
signal Moves1:unsigned(0 downto 0);
signal Moves2:unsigned(0 downto 0);
signal Moves3:unsigned(0 downto 0);
begin
Moves0<=unsigned(Move1);
Moves1<=unsigned(Move2);
Moves2<=unsigned(Move4);
Moves3<=unsigned(Move8);
Move<=Moves3&Moves2&Moves1&Moves0;
process
begin
WAIT UNTIL Clk'event AND Clk='1';
If (Reset='1') then
x_tmp<="00001";
y_tmp<="00001";
elsif IniDone = '1' then
If (Up='1') then
if (x_tmp-(1+Move)>20) then ------------------------ -11 if limits are exceeded
x_tmp<=x_tmp-(1+Move)-11;---------x_tmp-
elsif(x_tmp-(1+Move)=0) then
x_tmp<="10100";
else
x_tmp<= x_tmp-(1+Move);
end if;
y_tmp<=y_tmp; ------------coord y stays the same
elsif(Down='1') then
if (x_tmp+(1+Move)>20) then ---------------------------- -20 if limits are exceeded
x_tmp<=x_tmp+(1+Move)-20;
elsif(x_tmp+(1+Move)=0) then
x_tmp<="00001";
else
x_tmp<= x_tmp+(1+Move);
end if;
y_tmp<=y_tmp; ------------coord y stays the same
elsif(Left='1') then
if (y_tmp-(1+Move)>20) then ------------------------ -11 if limits are exceeded
y_tmp<=y_tmp-(1+Move)-11;
elsif(y_tmp-(1+Move)=0) then
y_tmp<="10100";
else
y_tmp<= y_tmp-(1+Move);
end if;
x_tmp<=x_tmp;------------coord x stays the same
elsif(Right='1')then
if (y_tmp+(1+Move)>20) then ---------------------------- -20 if limits are exceeded
y_tmp<=y_tmp+(1+Move)-20;
elsif(y_tmp+(1+Move)=0) then
y_tmp<="00001";
else
y_tmp<= y_tmp+(1+Move);
end if;
x_tmp<=x_tmp;------------coord x stays the same
else
y_tmp<=y_tmp; -----------registering the signals
x_tmp<=x_tmp; -----------register 5 used to be a component
end if;
else
NULL;
end if;
end process;
X_co<=std_logic_vector(x_tmp);
Y_co<=std_logic_vector(y_tmp);
end Behavioral;
| gpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Mem/synth/Mem.vhd | 1 | 6816 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0;
USE dist_mem_gen_v8_0.dist_mem_gen_v8_0;
ENTITY Mem IS
PORT (
a : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END Mem;
ARCHITECTURE Mem_arch OF Mem IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Mem_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Mem_arch: ARCHITECTURE IS "dist_mem_gen_v8_0,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Mem_arch : ARCHITECTURE IS "Mem,dist_mem_gen_v8_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Mem_arch: ARCHITECTURE IS "Mem,dist_mem_gen_v8_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_ADDR_WIDTH=9,C_DEFAULT_DATA=0,C_DEPTH=512,C_HAS_CLK=1,C_HAS_D=1,C_HAS_DPO=1,C_HAS_DPRA=1,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=1,C_MEM_INIT_FILE=Mem.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=2,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=5,C_PARSER_TYPE=1}";
BEGIN
U0 : dist_mem_gen_v8_0
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 9,
C_DEFAULT_DATA => "0",
C_DEPTH => 512,
C_HAS_CLK => 1,
C_HAS_D => 1,
C_HAS_DPO => 1,
C_HAS_DPRA => 1,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 1,
C_MEM_INIT_FILE => "Mem.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 2,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 5,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => d,
dpra => dpra,
clk => clk,
we => we,
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo,
dpo => dpo
);
END Mem_arch;
| gpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemTextures/synth/MemTextures.vhd | 1 | 6825 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0;
USE dist_mem_gen_v8_0.dist_mem_gen_v8_0;
ENTITY MemTextures IS
PORT (
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clk : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(91 DOWNTO 0)
);
END MemTextures;
ARCHITECTURE MemTextures_arch OF MemTextures IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF MemTextures_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(91 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(91 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(91 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(91 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(91 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF MemTextures_arch: ARCHITECTURE IS "dist_mem_gen_v8_0,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF MemTextures_arch : ARCHITECTURE IS "MemTextures,dist_mem_gen_v8_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF MemTextures_arch: ARCHITECTURE IS "MemTextures,dist_mem_gen_v8_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_ADDR_WIDTH=8,C_DEFAULT_DATA=0,C_DEPTH=256,C_HAS_CLK=1,C_HAS_D=0,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=0,C_MEM_INIT_FILE=MemTextures.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=0,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=1,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=92,C_PARSER_TYPE=1}";
BEGIN
U0 : dist_mem_gen_v8_0
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 8,
C_DEFAULT_DATA => "0",
C_DEPTH => 256,
C_HAS_CLK => 1,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "MemTextures.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 1,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 92,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 92)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
clk => clk,
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END MemTextures_arch;
| gpl-3.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/alt_vipvfr131_common_fifo_usedw_calculator.vhd | 2 | 13582 | -- Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_fifo_usedw_calculator is
generic
(
WIDTH : integer := 8;
DEPTH : integer := 9;
READ_TO_WRITE_DELAY : integer := 3;
WRITE_TO_READ_DELAY : integer := 3;
CLOCKS_ARE_SAME : boolean := TRUE
);
port
(
-- clocks, enables and reset
rdclock : in std_logic;
rdena : in std_logic;
wrclock : in std_logic;
wrena : in std_logic;
reset : in std_logic;
-- triggers
wrreq : in std_logic;
rdreq : in std_logic;
-- information signals calculated (write side)
wrusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
full : out std_logic;
almost_full : out std_logic;
-- information signals calculated (read side)
rdusedw : out std_logic_vector(wide_enough_for(DEPTH) - 1 downto 0);
empty : out std_logic;
almost_empty : out std_logic
);
end entity;
architecture rtl of alt_vipvfr131_common_fifo_usedw_calculator is
-- internal registers for the fullness/emptiness monitoring output ports
signal rdusedw_reg : unsigned(WIDTH - 1 downto 0);
signal wrusedw_reg : unsigned(WIDTH - 1 downto 0);
signal full_reg : std_logic;
signal almost_full_reg : std_logic;
signal empty_reg : std_logic;
signal almost_empty_reg : std_logic;
begin
-- check generics
assert WIDTH > 0
report "Generic WIDTH must greater than zero"
severity ERROR;
assert READ_TO_WRITE_DELAY >= 0
report "Generic READ_TO_WRITE_DELAY must greater than or equal to zero"
severity ERROR;
assert WRITE_TO_READ_DELAY >= 0
report "Generic WRITE_TO_READ_DELAY must greater than or equal to zero"
severity ERROR;
-- in single clock mode, just delay the signals using shift registers and
-- update rdusedw and wrusedw accordingly
-- if both delays are zero, rdusedw and wrusedw will be the same, however
-- we need do nothing about this because any synthesis tool will fold such
-- obvious bits of identical logic together
single_clock_gen :
if CLOCKS_ARE_SAME generate
-- delayed (possibly by zero cycles!) versions of rdreq and wrreq
signal rdreq_delay, wrreq_delay : std_logic;
signal wrreq_to_delayer : std_logic;
begin
-- delaying unit for read
rdreq_delayer : alt_vipvfr131_common_one_bit_delay
generic map
(
DELAY => READ_TO_WRITE_DELAY
)
port map
(
clock => rdclock,
ena => rdena,
reset => reset,
data => rdreq,
q => rdreq_delay
);
-- delaying unit for write
-- note that this is enabled on the rdena, because the rdena stalls all of the interesting
-- logic of the fifo, whereas the wrena just stalls a little bit of write logic
wrreq_delayer : alt_vipvfr131_common_one_bit_delay
generic map
(
DELAY => WRITE_TO_READ_DELAY
)
port map
(
clock => rdclock,
ena => '1',
reset => reset,
data => wrreq_to_delayer,
q => wrreq_delay
);
wrreq_to_delayer <= wrreq and wrena;
-- this process updates the wrusedw and full signals
update_write_fullness_signals : process (wrclock, reset)
begin
if reset = '1' then
-- start empty
full_reg <= '0';
almost_full_reg <= '0';
wrusedw_reg <= (others => '0');
elsif wrclock'EVENT and wrclock = '1' then
-- update based on (possibly) delayed rdreq and up to date wrreq values
if (rdreq_delay = '1' and rdena = '1') and (wrreq = '0' or wrena = '0') then
-- reading and not writing decreases the used words in a fifo
full_reg <= '0';
if wrusedw_reg = to_unsigned(DEPTH - 1, WIDTH) then
almost_full_reg <= '0';
end if;
wrusedw_reg <= wrusedw_reg - 1;
elsif (rdreq_delay = '0' or rdena = '0') and (wrreq = '1' and wrena = '1') then
-- writing and not reading increases the used words in a fifo
if wrusedw_reg = to_unsigned(DEPTH - 1, WIDTH) then
full_reg <= '1';
end if;
if wrusedw_reg = to_unsigned(maximum(DEPTH - 2, 0), WIDTH) then
almost_full_reg <= '1';
end if;
wrusedw_reg <= wrusedw_reg + 1;
end if;
end if;
end process;
-- drive output lines from registers
wrusedw <= std_logic_vector(wrusedw_reg);
full <= full_reg;
almost_full <= almost_full_reg when DEPTH > 1 else '1';
-- this process updates the read side rdusedw and empty signals
update_read_emptiness_signals : process (rdclock, reset)
begin
if reset = '1' then
-- start empty
empty_reg <= '1';
almost_empty_reg <= '1';
rdusedw_reg <= (others => '0');
elsif rdclock'EVENT and rdclock = '1' then
-- update based on up to date rdreq and (possibly) delayed wrreq values
-- update based on up to date rdreq and (possibly) delayed wrreq values
if (rdreq = '1' and rdena = '1') and wrreq_delay = '0' then
-- reading and not writing decreases the used words in the fifo
if rdusedw_reg = to_unsigned(1, WIDTH) then
empty_reg <= '1';
end if;
if rdusedw_reg = to_unsigned(2, WIDTH) then
almost_empty_reg <= '1';
end if;
rdusedw_reg <= rdusedw_reg - 1;
elsif (rdreq = '0' or rdena = '0') and wrreq_delay = '1' then
-- writing and not reading increases the used words in the fifo
empty_reg <= '0';
if rdusedw_reg = to_unsigned(1, WIDTH) then
almost_empty_reg <= '0';
end if;
rdusedw_reg <= rdusedw_reg + 1;
end if;
end if;
end process;
-- drive output lines from registers
rdusedw <= std_logic_vector(rdusedw_reg);
empty <= empty_reg;
almost_empty <= almost_empty_reg when DEPTH > 1 else '1';
end generate;
-- in dual clock mode, need to maintain separate counters which only increment
-- cross clock domains by converting to gray, avoiding metastability with shift
-- registers and converting back
dual_clock_gen :
if CLOCKS_ARE_SAME = FALSE generate
-- these counters are incremented when rdreqs and wrreqs happen
-- they are then propagated across the clock domains and positive
-- deltas in their values are looked for at the other side
signal wrcounter, rdcounter : unsigned(WIDTH - 1 downto 0);
-- the counters in their destination once they've crossed the clock domains
signal clock_crossed_wrcounter, clock_crossed_rdcounter : std_logic_vector(WIDTH - 1 downto 0);
-- monitoring how much the counters have changed
signal clock_crossed_wrcounter_prev, clock_crossed_rdcounter_prev : std_logic_vector(WIDTH - 1 downto 0);
signal writes_this_read_cycle, reads_this_write_cycle : std_logic_vector(WIDTH - 1 downto 0);
-- sometimes extra delay is required after the clock crossing delay
signal writes_this_read_cycle_delay, reads_this_write_cycle_delay : std_logic_vector(WIDTH - 1 downto 0);
begin
-- update the rdcounter in response to rdreq on the rdclock
update_rdcounter : process (rdclock, reset)
begin
if reset = '1' then
rdcounter <= (others => '0');
elsif rdclock'EVENT and rdclock = '1' then
if rdena = '1' then
if rdreq = '1' then
rdcounter <= rdcounter + 1;
end if;
end if;
end if;
end process;
-- update the wrcounter in response to wrreq on the wrclock
update_wrcounter : process (wrclock, reset)
begin
if reset = '1' then
wrcounter <= (others => '0');
elsif wrclock'EVENT and wrclock = '1' then
if wrena = '1' then
if wrreq = '1' then
wrcounter <= wrcounter + 1;
end if;
end if;
end if;
end process;
-- propagate the wrcounter across to the read clock domain and monitor
-- how much it advances each cycle
wrcounter_to_rdclock : alt_vipvfr131_common_gray_clock_crosser
generic map
(
WIDTH => WIDTH
)
port map
(
inclock => wrclock,
outclock => rdclock,
inena => wrena,
outena => '1',
reset => reset,
data => std_logic_vector(wrcounter),
q => clock_crossed_wrcounter
);
-- track the previous value of clock_crossed_wrcounter
update_clock_crossed_wrcounter_prev : process (rdclock, reset)
begin
if reset = '1' then
clock_crossed_wrcounter_prev <= (others => '0');
elsif rdclock'EVENT and rdclock = '1' then
clock_crossed_wrcounter_prev <= clock_crossed_wrcounter;
end if;
end process;
-- combinationally update the wrcounter delta this read cycle
writes_this_read_cycle <= std_logic_vector(unsigned(clock_crossed_wrcounter) - unsigned(clock_crossed_wrcounter_prev));
-- propagate the rdcounter across to the write clock domain and monitor
-- how much it advances each cycle
rdcounter_to_wrclock : alt_vipvfr131_common_gray_clock_crosser
generic map
(
WIDTH => WIDTH
)
port map
(
inclock => rdclock,
outclock => wrclock,
inena => rdena,
outena => '1',
reset => reset,
data => std_logic_vector(rdcounter),
q => clock_crossed_rdcounter
);
-- track the previous value of clock_crossed_rdcounter
update_clock_crossed_rdcounter_prev : process (wrclock, reset)
begin
if reset = '1' then
clock_crossed_rdcounter_prev <= (others => '0');
elsif wrclock'EVENT and wrclock = '1' then
clock_crossed_rdcounter_prev <= clock_crossed_rdcounter;
end if;
end process;
-- combinationally update the rdcounter delta this read cycle
reads_this_write_cycle <= std_logic_vector(unsigned(clock_crossed_rdcounter) - unsigned(clock_crossed_rdcounter_prev));
-- delay writes_this_read_cycle as requested
writes_this_read_cycle_delayer : alt_vipvfr131_common_std_logic_vector_delay
generic map
(
WIDTH => WIDTH,
DELAY => WRITE_TO_READ_DELAY
)
port map
(
clock => rdclock,
ena => '1',
reset => reset,
data => writes_this_read_cycle,
q => writes_this_read_cycle_delay
);
-- delay reads_this_write_cycle as requested
reads_this_write_cycle_delayer : alt_vipvfr131_common_std_logic_vector_delay
generic map
(
WIDTH => WIDTH,
DELAY => READ_TO_WRITE_DELAY
)
port map
(
clock => wrclock,
ena => '1',
reset => reset,
data => reads_this_write_cycle,
q => reads_this_write_cycle_delay
);
-- this process updates the wrusedw and full signals
update_write_fullness_signals : process (wrclock, reset)
variable new_wrusedw : unsigned(WIDTH - 1 downto 0);
begin
if reset = '1' then
-- start empty
full_reg <= '0';
almost_full_reg <= '0';
wrusedw_reg <= (others => '0');
elsif wrclock'EVENT and wrclock = '1' then
-- update based on wrreq and the number of reads which we've been told about
-- this write cycle
new_wrusedw := wrusedw_reg;
if wrreq = '1' and wrena = '1' then
new_wrusedw := new_wrusedw + 1;
end if;
new_wrusedw := new_wrusedw - unsigned(reads_this_write_cycle_delay); -- should not be possible for this to make it go negative
-- update full
if new_wrusedw = to_unsigned(DEPTH, WIDTH) then
full_reg <= '1';
else
full_reg <= '0';
end if;
-- update almost full
if new_wrusedw >= to_unsigned(DEPTH - 1, WIDTH) then
almost_full_reg <= '1';
else
almost_full_reg <= '0';
end if;
-- update wrusedw_reg itself
wrusedw_reg <= new_wrusedw;
end if;
end process;
-- drive output lines from registers
wrusedw <= std_logic_vector(wrusedw_reg);
full <= full_reg;
almost_full <= almost_full_reg when DEPTH > 1 else '1';
-- this process updates the rdusedw and empty signals
update_read_emptiness_signals : process (rdclock, reset)
variable new_rdusedw : unsigned(WIDTH - 1 downto 0);
begin
if reset = '1' then
-- start empty
empty_reg <= '1';
almost_empty_reg <= '1';
rdusedw_reg <= (others => '0');
elsif rdclock'EVENT and rdclock = '1' then
-- update based on wrreq and the number of reads which we've been told about
-- this write cycle
new_rdusedw := rdusedw_reg;
if rdreq = '1' and rdena = '1' then
new_rdusedw := new_rdusedw - 1;
end if;
new_rdusedw := new_rdusedw + unsigned(writes_this_read_cycle_delay); -- should not be possible for this to make it wrap
-- update empty
if new_rdusedw = to_unsigned(0, WIDTH) then
empty_reg <= '1';
else
empty_reg <= '0';
end if;
-- update almost empty
if new_rdusedw <= to_unsigned(1, WIDTH) then
almost_empty_reg <= '1';
else
almost_empty_reg <= '0';
end if;
-- update rdusedw_reg itself
rdusedw_reg <= new_rdusedw;
end if;
end process;
-- drive output lines from registers
rdusedw <= std_logic_vector(rdusedw_reg);
empty <= empty_reg;
almost_empty <= almost_empty_reg when DEPTH > 1 else '1';
end generate;
end;
| gpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemFaces/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 24 | 19921 | `protect begin_protected
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
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`protect end_protected
| gpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/imports/VHDL/ScoreAndRowToAddr.vhd | 1 | 529 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
use Ieee.std_logic_unsigned.all;
entity ScoreAndRowToAddr is
Port (
Texture : in STD_LOGIC_VECTOR (3 downto 0);
Row : in STD_LOGIC_VECTOR (4 downto 0);
AddressOut : out STD_LOGIC_VECTOR (7 downto 0)
);
end ScoreAndRowToAddr;
architecture Behavioral of ScoreAndRowToAddr is
begin
AddressOut <= conv_std_logic_vector(conv_integer((Texture))*17+conv_integer(Row)-1,8);
end Behavioral;
| gpl-3.0 |
pravintavagad/Project2 | src/ram.vhd | 1 | 883 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:16:12 03/17/2014
-- Design Name:
-- Module Name: ram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ram is
end ram;
architecture Behavioral of ram is
begin
end Behavioral;
| gpl-3.0 |
simoesusp/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/MUX1.vhd | 4 | 6693 | -- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: MUX1.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY MUX1 IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END MUX1;
ARCHITECTURE SYN OF mux1 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 15 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
sub_wire5 <= data0x(15 DOWNTO 0);
sub_wire4 <= data1x(15 DOWNTO 0);
sub_wire3 <= data2x(15 DOWNTO 0);
result <= sub_wire0(15 DOWNTO 0);
sub_wire1 <= data3x(15 DOWNTO 0);
sub_wire2(3, 0) <= sub_wire1(0);
sub_wire2(3, 1) <= sub_wire1(1);
sub_wire2(3, 2) <= sub_wire1(2);
sub_wire2(3, 3) <= sub_wire1(3);
sub_wire2(3, 4) <= sub_wire1(4);
sub_wire2(3, 5) <= sub_wire1(5);
sub_wire2(3, 6) <= sub_wire1(6);
sub_wire2(3, 7) <= sub_wire1(7);
sub_wire2(3, 8) <= sub_wire1(8);
sub_wire2(3, 9) <= sub_wire1(9);
sub_wire2(3, 10) <= sub_wire1(10);
sub_wire2(3, 11) <= sub_wire1(11);
sub_wire2(3, 12) <= sub_wire1(12);
sub_wire2(3, 13) <= sub_wire1(13);
sub_wire2(3, 14) <= sub_wire1(14);
sub_wire2(3, 15) <= sub_wire1(15);
sub_wire2(2, 0) <= sub_wire3(0);
sub_wire2(2, 1) <= sub_wire3(1);
sub_wire2(2, 2) <= sub_wire3(2);
sub_wire2(2, 3) <= sub_wire3(3);
sub_wire2(2, 4) <= sub_wire3(4);
sub_wire2(2, 5) <= sub_wire3(5);
sub_wire2(2, 6) <= sub_wire3(6);
sub_wire2(2, 7) <= sub_wire3(7);
sub_wire2(2, 8) <= sub_wire3(8);
sub_wire2(2, 9) <= sub_wire3(9);
sub_wire2(2, 10) <= sub_wire3(10);
sub_wire2(2, 11) <= sub_wire3(11);
sub_wire2(2, 12) <= sub_wire3(12);
sub_wire2(2, 13) <= sub_wire3(13);
sub_wire2(2, 14) <= sub_wire3(14);
sub_wire2(2, 15) <= sub_wire3(15);
sub_wire2(1, 0) <= sub_wire4(0);
sub_wire2(1, 1) <= sub_wire4(1);
sub_wire2(1, 2) <= sub_wire4(2);
sub_wire2(1, 3) <= sub_wire4(3);
sub_wire2(1, 4) <= sub_wire4(4);
sub_wire2(1, 5) <= sub_wire4(5);
sub_wire2(1, 6) <= sub_wire4(6);
sub_wire2(1, 7) <= sub_wire4(7);
sub_wire2(1, 8) <= sub_wire4(8);
sub_wire2(1, 9) <= sub_wire4(9);
sub_wire2(1, 10) <= sub_wire4(10);
sub_wire2(1, 11) <= sub_wire4(11);
sub_wire2(1, 12) <= sub_wire4(12);
sub_wire2(1, 13) <= sub_wire4(13);
sub_wire2(1, 14) <= sub_wire4(14);
sub_wire2(1, 15) <= sub_wire4(15);
sub_wire2(0, 0) <= sub_wire5(0);
sub_wire2(0, 1) <= sub_wire5(1);
sub_wire2(0, 2) <= sub_wire5(2);
sub_wire2(0, 3) <= sub_wire5(3);
sub_wire2(0, 4) <= sub_wire5(4);
sub_wire2(0, 5) <= sub_wire5(5);
sub_wire2(0, 6) <= sub_wire5(6);
sub_wire2(0, 7) <= sub_wire5(7);
sub_wire2(0, 8) <= sub_wire5(8);
sub_wire2(0, 9) <= sub_wire5(9);
sub_wire2(0, 10) <= sub_wire5(10);
sub_wire2(0, 11) <= sub_wire5(11);
sub_wire2(0, 12) <= sub_wire5(12);
sub_wire2(0, 13) <= sub_wire5(13);
sub_wire2(0, 14) <= sub_wire5(14);
sub_wire2(0, 15) <= sub_wire5(15);
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_size => 4,
lpm_type => "LPM_MUX",
lpm_width => 16,
lpm_widths => 2
)
PORT MAP (
data => sub_wire2,
sel => sel,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL "data0x[15..0]"
-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL "data1x[15..0]"
-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL "data2x[15..0]"
-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL "data3x[15..0]"
-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-3.0 |
simoesusp/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE115/MUX1.vhd | 4 | 6693 | -- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: MUX1.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY MUX1 IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END MUX1;
ARCHITECTURE SYN OF mux1 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 15 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
sub_wire5 <= data0x(15 DOWNTO 0);
sub_wire4 <= data1x(15 DOWNTO 0);
sub_wire3 <= data2x(15 DOWNTO 0);
result <= sub_wire0(15 DOWNTO 0);
sub_wire1 <= data3x(15 DOWNTO 0);
sub_wire2(3, 0) <= sub_wire1(0);
sub_wire2(3, 1) <= sub_wire1(1);
sub_wire2(3, 2) <= sub_wire1(2);
sub_wire2(3, 3) <= sub_wire1(3);
sub_wire2(3, 4) <= sub_wire1(4);
sub_wire2(3, 5) <= sub_wire1(5);
sub_wire2(3, 6) <= sub_wire1(6);
sub_wire2(3, 7) <= sub_wire1(7);
sub_wire2(3, 8) <= sub_wire1(8);
sub_wire2(3, 9) <= sub_wire1(9);
sub_wire2(3, 10) <= sub_wire1(10);
sub_wire2(3, 11) <= sub_wire1(11);
sub_wire2(3, 12) <= sub_wire1(12);
sub_wire2(3, 13) <= sub_wire1(13);
sub_wire2(3, 14) <= sub_wire1(14);
sub_wire2(3, 15) <= sub_wire1(15);
sub_wire2(2, 0) <= sub_wire3(0);
sub_wire2(2, 1) <= sub_wire3(1);
sub_wire2(2, 2) <= sub_wire3(2);
sub_wire2(2, 3) <= sub_wire3(3);
sub_wire2(2, 4) <= sub_wire3(4);
sub_wire2(2, 5) <= sub_wire3(5);
sub_wire2(2, 6) <= sub_wire3(6);
sub_wire2(2, 7) <= sub_wire3(7);
sub_wire2(2, 8) <= sub_wire3(8);
sub_wire2(2, 9) <= sub_wire3(9);
sub_wire2(2, 10) <= sub_wire3(10);
sub_wire2(2, 11) <= sub_wire3(11);
sub_wire2(2, 12) <= sub_wire3(12);
sub_wire2(2, 13) <= sub_wire3(13);
sub_wire2(2, 14) <= sub_wire3(14);
sub_wire2(2, 15) <= sub_wire3(15);
sub_wire2(1, 0) <= sub_wire4(0);
sub_wire2(1, 1) <= sub_wire4(1);
sub_wire2(1, 2) <= sub_wire4(2);
sub_wire2(1, 3) <= sub_wire4(3);
sub_wire2(1, 4) <= sub_wire4(4);
sub_wire2(1, 5) <= sub_wire4(5);
sub_wire2(1, 6) <= sub_wire4(6);
sub_wire2(1, 7) <= sub_wire4(7);
sub_wire2(1, 8) <= sub_wire4(8);
sub_wire2(1, 9) <= sub_wire4(9);
sub_wire2(1, 10) <= sub_wire4(10);
sub_wire2(1, 11) <= sub_wire4(11);
sub_wire2(1, 12) <= sub_wire4(12);
sub_wire2(1, 13) <= sub_wire4(13);
sub_wire2(1, 14) <= sub_wire4(14);
sub_wire2(1, 15) <= sub_wire4(15);
sub_wire2(0, 0) <= sub_wire5(0);
sub_wire2(0, 1) <= sub_wire5(1);
sub_wire2(0, 2) <= sub_wire5(2);
sub_wire2(0, 3) <= sub_wire5(3);
sub_wire2(0, 4) <= sub_wire5(4);
sub_wire2(0, 5) <= sub_wire5(5);
sub_wire2(0, 6) <= sub_wire5(6);
sub_wire2(0, 7) <= sub_wire5(7);
sub_wire2(0, 8) <= sub_wire5(8);
sub_wire2(0, 9) <= sub_wire5(9);
sub_wire2(0, 10) <= sub_wire5(10);
sub_wire2(0, 11) <= sub_wire5(11);
sub_wire2(0, 12) <= sub_wire5(12);
sub_wire2(0, 13) <= sub_wire5(13);
sub_wire2(0, 14) <= sub_wire5(14);
sub_wire2(0, 15) <= sub_wire5(15);
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_size => 4,
lpm_type => "LPM_MUX",
lpm_width => 16,
lpm_widths => 2
)
PORT MAP (
data => sub_wire2,
sel => sel,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL "data0x[15..0]"
-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL "data1x[15..0]"
-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL "data2x[15..0]"
-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL "data3x[15..0]"
-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/LBDR_packet_drop_with_checkers/LBDR_packet_drop_routing_part_pseudo_checkers.vhd | 3 | 15472 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end LBDR_packet_drop_routing_part_pseudo_checkers;
architecture behavior of LBDR_packet_drop_routing_part_pseudo_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
signal grant_signals: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then
err_tail_empty_Requests_FF_Requests_in <= '1';
else
err_tail_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1';
else
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or
grant_signals = "01000" or grant_signals = "10000") and grants = '0') then
err_grants_onehot <= '1';
else
err_grants_onehot <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( grant_signals = "00000" and grants = '1') then
err_grants_mismatch <= '1';
else
err_grants_mismatch <= '0';
end if;
end process;
-- Checked !
process (flit_type, Requests_FF, Requests_FF, Requests_in)
begin
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
else
err_header_tail_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
else
err_dst_addr_cur_addr_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
else
err_dst_addr_cur_addr_not_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
else
err_dst_addr_cur_addr_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
else
err_dst_addr_cur_addr_not_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
else
err_dst_addr_cur_addr_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
else
err_dst_addr_cur_addr_not_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
else
err_dst_addr_cur_addr_S1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
else
err_dst_addr_cur_addr_not_S1 <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr = cur_addr and Req_L_in = '0') then
err_dst_addr_cur_addr_Req_L_in <= '1';
else
err_dst_addr_cur_addr_Req_L_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr /= cur_addr and Req_L_in = '1') then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
else
err_dst_addr_cur_addr_not_Req_L_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in = '0') then
err_header_not_empty_faulty_drop_packet_in <= '1';
else
err_header_not_empty_faulty_drop_packet_in <= '0';
end if;
end process;
-- Added (according to new design)!
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in, packet_drop)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '0' and not (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in /= packet_drop) then
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '1';
else
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '0';
end if;
end process;
-- Added (according to new design)!
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, Requests_in)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and Requests_in /= "00000") then
err_header_not_empty_faulty_Req_in_all_zero <= '1';
else
err_header_not_empty_faulty_Req_in_all_zero <= '0';
end if;
end process;
-- Added (according to new design)!
--process (flit_type, empty, Req_L_in, N1_out, E1_out, W1_out, S1_out)
--begin
-- if ( flit_type = "001" and empty = '0' and Req_L_in /= (not N1_out and not E1_out and not W1_out and not S1_out) ) then
-- err_header_not_empty_Req_L_in <= '1';
-- else
-- err_header_not_empty_Req_L_in <= '0';
-- end if;
--end process;
-- Updated !
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_N_in /= ( ((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0) ) ) then
err_header_not_empty_Req_N_in <= '1';
else
err_header_not_empty_Req_N_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_E_in /= ( ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1) ) ) then
err_header_not_empty_Req_E_in <= '1';
else
err_header_not_empty_Req_E_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_W_in /= ( ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2) ) ) then
err_header_not_empty_Req_W_in <= '1';
else
err_header_not_empty_Req_W_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_S_in /= (((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) ) then
err_header_not_empty_Req_S_in <= '1';
else
err_header_not_empty_Req_S_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if (flit_type = "001" and empty = '1' and packet_drop_in /= packet_drop ) then
err_header_empty_packet_drop_in_packet_drop_equal <= '1';
else
err_header_empty_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '1' and packet_drop_in /= '0' ) then
err_tail_not_empty_packet_drop_not_packet_drop_in <= '1';
else
err_tail_not_empty_packet_drop_not_packet_drop_in <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '0' and packet_drop_in /= packet_drop ) then
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '1';
else
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if ( ((flit_type /= "001" and flit_type /= "100") or empty = '1') and packet_drop_in /= packet_drop ) then
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '1';
else
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (packet_drop_order, packet_drop)
begin
if (packet_drop_order /= packet_drop) then
err_packet_drop_order <= '1';
else
err_packet_drop_order <= '0';
end if;
end process;
-- Added !
end behavior; | gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/Checkers/Control_Part_Checkers/Allocator_checkers/Allocator_logic_checkers/allocator_logic_pseudo_with_checkers_top.vhd | 3 | 31450 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_logic_pseudo_with_checkers_top is
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
grant_N_out, grant_E_out, grant_W_out, grant_S_out, grant_L_out : out std_logic;
-- Checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N,
err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W,
err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S,
err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match : out std_logic
);
end allocator_logic_pseudo_with_checkers_top;
architecture behavior of allocator_logic_pseudo_with_checkers_top is
component allocator_logic_pseudo is
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
grant_N_out, grant_E_out, grant_W_out, grant_S_out, grant_L_out : out std_logic
);
end component;
component allocator_logic_pseudo_checkers is
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : in std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: in std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: in std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: in std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: in std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L : in std_logic;
-- Checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N,
err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W,
err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S,
err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match : out std_logic
);
end component;
-- Signal(s) definition(s) for checkers
signal valid_N_sig, valid_E_sig, valid_W_sig, valid_S_sig, valid_L_sig : std_logic;
signal grant_N_N_signal, grant_N_E_signal, grant_N_W_signal, grant_N_S_signal, grant_N_L_signal: std_logic;
signal grant_E_N_signal, grant_E_E_signal, grant_E_W_signal, grant_E_S_signal, grant_E_L_signal: std_logic;
signal grant_W_N_signal, grant_W_E_signal, grant_W_W_signal, grant_W_S_signal, grant_W_L_signal: std_logic;
signal grant_S_N_signal, grant_S_E_signal, grant_S_W_signal, grant_S_S_signal, grant_S_L_signal: std_logic;
signal grant_L_N_signal, grant_L_E_signal, grant_L_W_signal, grant_L_S_signal, grant_L_L_signal: std_logic;
signal grant_N_out_sig, grant_E_out_sig, grant_W_out_sig, grant_S_out_sig, grant_L_out_sig : std_logic;
begin
-- We did this because of the checkers
valid_N <= valid_N_sig;
valid_E <= valid_E_sig;
valid_W <= valid_W_sig;
valid_S <= valid_S_sig;
valid_L <= valid_L_sig;
grant_N_out <= grant_N_out_sig;
grant_E_out <= grant_E_out_sig;
grant_W_out <= grant_W_out_sig;
grant_S_out <= grant_S_out_sig;
grant_L_out <= grant_L_out_sig;
grant_N_N <= grant_N_N_signal;
grant_N_E <= grant_N_E_signal;
grant_N_W <= grant_N_W_signal;
grant_N_S <= grant_N_S_signal;
grant_N_L <= grant_N_L_signal;
grant_E_N <= grant_E_N_signal;
grant_E_E <= grant_E_E_signal;
grant_E_W <= grant_E_W_signal;
grant_E_S <= grant_E_S_signal;
grant_E_L <= grant_E_L_signal;
grant_W_N <= grant_W_N_signal;
grant_W_E <= grant_W_E_signal;
grant_W_W <= grant_W_W_signal;
grant_W_S <= grant_W_S_signal;
grant_W_L <= grant_W_L_signal;
grant_S_N <= grant_S_N_signal;
grant_S_E <= grant_S_E_signal;
grant_S_W <= grant_S_W_signal;
grant_S_S <= grant_S_S_signal;
grant_S_L <= grant_S_L_signal;
grant_L_N <= grant_L_N_signal;
grant_L_E <= grant_L_E_signal;
grant_L_W <= grant_L_W_signal;
grant_L_S <= grant_L_S_signal;
grant_L_L <= grant_L_L_signal;
-- Allocator logic (pseudo-combinational) module instantiation
ALLOCATOR_LOGIC_PSEUDO0: allocator_logic_pseudo
PORT MAP (
empty_N => empty_N,
empty_E => empty_E,
empty_W => empty_W,
empty_S => empty_S,
empty_L => empty_L,
grant_N_N_sig => grant_N_N_sig, grant_N_E_sig => grant_N_E_sig, grant_N_W_sig => grant_N_W_sig, grant_N_S_sig => grant_N_S_sig, grant_N_L_sig => grant_N_L_sig,
grant_E_N_sig => grant_E_N_sig, grant_E_E_sig => grant_E_E_sig, grant_E_W_sig => grant_E_W_sig, grant_E_S_sig => grant_E_S_sig, grant_E_L_sig => grant_E_L_sig,
grant_W_N_sig => grant_W_N_sig, grant_W_E_sig => grant_W_E_sig, grant_W_W_sig => grant_W_W_sig, grant_W_S_sig => grant_W_S_sig, grant_W_L_sig => grant_W_L_sig,
grant_S_N_sig => grant_S_N_sig, grant_S_E_sig => grant_S_E_sig, grant_S_W_sig => grant_S_W_sig, grant_S_S_sig => grant_S_S_sig, grant_S_L_sig => grant_S_L_sig,
grant_L_N_sig => grant_L_N_sig, grant_L_E_sig => grant_L_E_sig, grant_L_W_sig => grant_L_W_sig, grant_L_S_sig => grant_L_S_sig, grant_L_L_sig => grant_L_L_sig,
valid_N => valid_N_sig,
valid_E => valid_E_sig,
valid_W => valid_W_sig,
valid_S => valid_S_sig,
valid_L => valid_L_sig,
grant_N_N => grant_N_N_signal,
grant_N_E => grant_N_E_signal,
grant_N_W => grant_N_W_signal,
grant_N_S => grant_N_S_signal,
grant_N_L => grant_N_L_signal,
grant_E_N => grant_E_N_signal,
grant_E_E => grant_E_E_signal,
grant_E_W => grant_E_W_signal,
grant_E_S => grant_E_S_signal,
grant_E_L => grant_E_L_signal,
grant_W_N => grant_W_N_signal,
grant_W_E => grant_W_E_signal,
grant_W_W => grant_W_W_signal,
grant_W_S => grant_W_S_signal,
grant_W_L => grant_W_L_signal,
grant_S_N => grant_S_N_signal,
grant_S_E => grant_S_E_signal,
grant_S_W => grant_S_W_signal,
grant_S_S => grant_S_S_signal,
grant_S_L => grant_S_L_signal,
grant_L_N => grant_L_N_signal,
grant_L_E => grant_L_E_signal,
grant_L_W => grant_L_W_signal,
grant_L_S => grant_L_S_signal,
grant_L_L => grant_L_L_signal,
grant_N_out => grant_N_out_sig,
grant_E_out => grant_E_out_sig,
grant_W_out => grant_W_out_sig,
grant_S_out => grant_S_out_sig,
grant_L_out => grant_L_out_sig
);
-- Allocator logic (pseudo-combinational) checkers instantiation
CHECKERS: allocator_logic_pseudo_checkers PORT MAP (
empty_N => empty_N,
empty_E => empty_E,
empty_W => empty_W,
empty_S => empty_S,
empty_L => empty_L,
grant_N_N_sig => grant_N_N_sig, grant_N_E_sig => grant_N_E_sig, grant_N_W_sig => grant_N_W_sig, grant_N_S_sig => grant_N_S_sig, grant_N_L_sig => grant_N_L_sig,
grant_E_N_sig => grant_E_N_sig, grant_E_E_sig => grant_E_E_sig, grant_E_W_sig => grant_E_W_sig, grant_E_S_sig => grant_E_S_sig, grant_E_L_sig => grant_E_L_sig,
grant_W_N_sig => grant_W_N_sig, grant_W_E_sig => grant_W_E_sig, grant_W_W_sig => grant_W_W_sig, grant_W_S_sig => grant_W_S_sig, grant_W_L_sig => grant_W_L_sig,
grant_S_N_sig => grant_S_N_sig, grant_S_E_sig => grant_S_E_sig, grant_S_W_sig => grant_S_W_sig, grant_S_S_sig => grant_S_S_sig, grant_S_L_sig => grant_S_L_sig,
grant_L_N_sig => grant_L_N_sig, grant_L_E_sig => grant_L_E_sig, grant_L_W_sig => grant_L_W_sig, grant_L_S_sig => grant_L_S_sig, grant_L_L_sig => grant_L_L_sig,
valid_N => valid_N_sig,
valid_E => valid_E_sig,
valid_W => valid_W_sig,
valid_S => valid_S_sig,
valid_L => valid_L_sig,
grant_N_N => grant_N_N_signal,
grant_N_E => grant_N_E_signal,
grant_N_W => grant_N_W_signal,
grant_N_S => grant_N_S_signal,
grant_N_L => grant_N_L_signal,
grant_E_N => grant_E_N_signal,
grant_E_E => grant_E_E_signal,
grant_E_W => grant_E_W_signal,
grant_E_S => grant_E_S_signal,
grant_E_L => grant_E_L_signal,
grant_W_N => grant_W_N_signal,
grant_W_E => grant_W_E_signal,
grant_W_W => grant_W_W_signal,
grant_W_S => grant_W_S_signal,
grant_W_L => grant_W_L_signal,
grant_S_N => grant_S_N_signal,
grant_S_E => grant_S_E_signal,
grant_S_W => grant_S_W_signal,
grant_S_S => grant_S_S_signal,
grant_S_L => grant_S_L_signal,
grant_L_N => grant_L_N_signal,
grant_L_E => grant_L_E_signal,
grant_L_W => grant_L_W_signal,
grant_L_S => grant_L_S_signal,
grant_L_L => grant_L_L_signal,
grant_N => grant_N_out_sig,
grant_E => grant_E_out_sig,
grant_W => grant_W_out_sig,
grant_S => grant_S_out_sig,
grant_L => grant_L_out_sig,
-- Checker Outputs
err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N ,
err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N ,
err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E ,
err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E ,
err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W ,
err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W ,
err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S ,
err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S ,
err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L ,
err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L ,
err_grants_valid_not_match => err_grants_valid_not_match
);
END;
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/ram_wrapper.vhd | 3 | 6136 | ---------------------------------------------------------------------
-- TITLE: RAM wrapper
-- AUTHOR: Siavoosh Payandeh Azad
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
component TS1N40LPB4096X32M4S is
--generic (cdeFileInit : string);
port (
PD : in std_logic; --Power down mode
CLK : in std_logic; --CLK input
CEB : in std_logic; --Chip enable, active low for SRAM operation; active high for fuse data setting
WEB : in std_logic; --Write enable, active low
CEBM : in std_logic; --Chip enable for BIST, active low for SRAM operation; active high for fuse data setting
WEBM : in std_logic; --Write enable for BIST, active low
AWT : in std_logic; --Asynchronous write through
A: in std_logic_vector(11 downto 0); --Address input
D: in std_logic_vector(31 downto 0); --Data input
BWEB: in std_logic_vector(31 downto 0); --Bit write enable, active low
AM: in std_logic_vector(9 downto 0); --Address input for BIST
DM: in std_logic_vector(31 downto 0); --Data input for BIST
BWEBM: in std_logic_vector(31 downto 0); --Bit write enable, active low
BIST: in std_logic; --BIST enable
RTSEL:in std_logic_vector(1 downto 0); --Read margin setting pins
WTSEL:in std_logic_vector(1 downto 0); --Write margin setting pins
Q: out std_logic_vector(31 downto 0) --Data output
);
end component;
signal Mem_clk : std_logic;
signal Mem_reset : std_logic;
signal Mem_enable : std_logic;
signal Mem_write_byte_enable : std_logic_vector(3 downto 0);
signal Mem_address : std_logic_vector(31 downto 2);
signal Mem_data_write : std_logic_vector(31 downto 0);
signal Mem_data_read : std_logic_vector(31 downto 0);
signal write_enable: std_logic;
signal write_BWEB: std_logic_vector(31 downto 0);
signal not_clock: std_logic;
signal delayed_data_out, Q: std_logic_vector(31 downto 0);
begin
process(IJTAG_select, clk, reset, enable, write_byte_enable, address,
data_write, Mem_data_read, IJTAG_clk, IJTAG_reset, IJTAG_enable,
IJTAG_write_byte_enable, IJTAG_address, IJTAG_data_write)
begin
case( IJTAG_select) is
when '0' =>
Mem_clk <= clk;
Mem_reset <= reset;
Mem_enable <= enable;
Mem_write_byte_enable <= write_byte_enable;
Mem_address <= address;
Mem_data_write <= data_write;
data_read <= Mem_data_read;
when others =>
Mem_clk <= IJTAG_clk;
Mem_reset <= IJTAG_reset;
Mem_enable <= IJTAG_enable;
Mem_write_byte_enable <= IJTAG_write_byte_enable;
Mem_address <= IJTAG_address;
Mem_data_write <= IJTAG_data_write;
IJTAG_data_read <= Mem_data_read;
end case;
end process;
write_enable <= not(Mem_write_byte_enable(0) or Mem_write_byte_enable(1) or Mem_write_byte_enable(2) or Mem_write_byte_enable(3));
not_clock <= not Mem_clk;
-- the following process is not actually tested!
process(Mem_write_byte_enable)
begin
write_BWEB <= (others => '1');
if Mem_write_byte_enable(0) = '1' then
write_BWEB(7 downto 0) <= "00000000";
end if;
if Mem_write_byte_enable(1) = '1' then
write_BWEB(15 downto 8) <= "00000000";
end if;
if Mem_write_byte_enable(2) = '1' then
write_BWEB(23 downto 16) <= "00000000";
end if;
if Mem_write_byte_enable(3) = '1' then
write_BWEB(31 downto 24) <= "00000000";
end if;
end process;
-- Plasma wants the data in the next clock cycle!
process(Mem_clk, Mem_reset)begin
if Mem_reset = '1' then
delayed_data_out <= (others=> '0');
elsif rising_edge(Mem_clk) then
delayed_data_out <= Q;
end if;
end process;
RAM_unit: TS1N40LPB4096X32M4S
generic map (cdeFileInit => stim_file)
port map(
PD => '0',
CLK => not_clock, -- this is the part that we changed. there was some serious timing issues with setup and hold times!
CEB => '0',
WEB => write_enable,
CEBM => '0',
WEBM => '1',
AWT => '0',
A => Mem_address(13 downto 2),
D => Mem_data_write,
BWEB => write_BWEB,
AM => (others =>'0'),
DM => (others =>'0'),
BWEBM => (others =>'1'),
BIST => '0',
RTSEL => "01", -- they said and i qoute: "Please use this setting"
WTSEL => "01", -- they said and i qoute: "Please use this setting"
Q => Q
);
Mem_data_read <= delayed_data_out;
end; --architecture logic
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/xilinx_image.vhd | 3 | 181451 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafafafafafafafaf2308000c241400ac273c243c243c273c",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
INIT_04 => X"8c343c00af03af270003278f0300ac008f34af0000000014008f8fafaf03af27",
INIT_05 => X"008f000c2400142480008f0010af03afaf270003278f0300ac008f3c00103000",
INIT_06 => X"008f8f0010af24af03afaf270003278f8f030000140080008f000c000080af24",
INIT_07 => X"03000004008faf24008f000c0024008f0010000c0024008f00102c008faf3000",
INIT_08 => X"0c000080af24008f0010af27000c8f008f002727afafaf03afaf270003278f8f",
INIT_09 => X"3c03af270003278f8f030000140080008fa0248faf24008f0014248024008f00",
INIT_0A => X"0000000003278f8f030000008c3c0010000c0003afaf270003278f0330008c34",
INIT_0B => X"243c000c343c243c24000c343c243c24000c243c000c243c000c243c03afaf27",
INIT_0C => X"24243c243c243caf243caf24000c24243c243c243caf243caf24000c243c000c",
INIT_0D => X"000c343c243c243c243caf243caf24000c343c243c243c243caf243caf24000c",
INIT_0E => X"243c000c000c243c000c243c000c000c243c000c243c000c000c243c000c243c",
INIT_0F => X"3c000c243c0010000c243c0014008c3c000c243c000c243c000c000c243c000c",
INIT_10 => X"af240010af24afaf03afaf270003278f8f0300000c24000c0024008c3c000c24",
INIT_11 => X"0c8f24000010008f001400008f8faf24008f0010af001400000014008f8f0010",
INIT_12 => X"24008faf240010008f8c002400008f3c000c0024008c002400008f3c000c2400",
INIT_13 => X"0c243c0010ac3c24008c3c000c243c0014248f001428008faf24008f000c24af",
INIT_14 => X"0087000c24000c8faf00008f870010a7afafafaf03afaf270003278f8f030000",
INIT_15 => X"0087a730240097af240010008f8c00008f000087000c24000c00008c00008f00",
INIT_16 => X"000c243c0010ac3c24008c3c000c243c0014248f000c8f2400000c243c001428",
INIT_17 => X"87000c24000c8faf0000008f870010a7afafafafaf03afaf270003278f8f0300",
INIT_18 => X"87a730240097af240010008f8c00008f000087000c24000c00008c00008f0000",
INIT_19 => X"008c00008f000087000c24000c8faf0000008f2400870010a7000c2400142800",
INIT_1A => X"000c240014280087a730240097af240010008f8c00008f000087000c24000c00",
INIT_1B => X"000c00008c00008f0000343c87000c24000c8faf0000000014008f870010a724",
INIT_1C => X"24000c240014280087a730240097af240010008f8c00008f0000343c87000c24",
INIT_1D => X"0c24000c00008c00008f0000343c87000c24000c8faf00000014008f870010a7",
INIT_1E => X"2400000c243c0014280087a730240097af240010008f8c00008f0000343c8700",
INIT_1F => X"af270003278f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c8f",
INIT_20 => X"0c24000c00008c002400008f3c000c24000c8faf00008f8f0010afafaf2403af",
INIT_21 => X"008f8f0010af000c24001428008faf24008faf240010008f8c002400008f3c00",
INIT_22 => X"10008f8c002400008f3c000c24000c00008c002400008f3c000c24000c8faf00",
INIT_23 => X"0010ac3c24008c3c000c243c0014248f000c243c001428008faf24008faf2400",
INIT_24 => X"8f0000008fa000278f0000008f0010afaf03afaf270003278f8f0300000c243c",
INIT_25 => X"00af008000278f0010af001428008faf24008fac008f002700008fa400270000",
INIT_26 => X"10008f8c002400008f3c000c24000c0024008c002400008f3c000c24000c8f24",
INIT_27 => X"24000c0024008c002400008f3c000c24000c8f2400af0084002700008faf2400",
INIT_28 => X"3c000c24000c8f2400af008c002700008faf240010008f8c002400008f3c000c",
INIT_29 => X"8faf24008faf240010008f8c002400008f3c000c24000c0024008c002400008f",
INIT_2A => X"8f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c243c00142800",
INIT_2B => X"000c24000c00008c3c000c24000c8faf00008f8fafaf24af2403afaf27000327",
INIT_2C => X"8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f8c3c",
INIT_2D => X"008f8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f",
INIT_2E => X"240010008f8c243c000c24000c00008c243c000c24000c8faf00008faf240010",
INIT_2F => X"008faf240010008f8c243c000c24000c00008c243c000c24000c8faf24008faf",
INIT_30 => X"0014248f000c243caf240010008f8c243c000c00008c243c000c24000c8faf24",
INIT_31 => X"28008c3caf03af27000003278f8f0300000c243c0010ac3c24008c3c000c243c",
INIT_32 => X"a324af03af270003278f0324001000ac3c24008c3cac008f0024003c8c3c0010",
INIT_33 => X"14003c8c340010240010248c3c00100083a4248fa3001000102400100094008f",
INIT_34 => X"af270003278f0324a4008fa30010ac3cac243cac3cac008c3c240018008c3c00",
INIT_35 => X"0010240010248c3c00100083a4248fa3001000102400100094008fa324afaf03",
INIT_36 => X"3cac0024003c8c248c3c001028008c3c0004008f0010008faf008c34af008c34",
INIT_37 => X"af008fafaf03af270003278f0324a4008fa30010ac243cac3cac3cac3c24008c",
INIT_38 => X"10afafafafaf03afaf270003278f038f00140080a00080af24008faf24008f00",
INIT_39 => X"8f8faf240010af240010248f0004008fa3001428008faf24008fa02400278f00",
INIT_3A => X"008f001028008faf0000000014008f8faf00000014008f8f0010af24af000000",
INIT_3B => X"1000008c008f00008f240014008fa000278f0000302430008f00100000302430",
INIT_3C => X"8f0010008c008fa02400278faf24008f0014248f0000100004008faf24008f00",
INIT_3D => X"2700248c008f0010ac008f00008f24000c8f0000008f2700100000008f248c00",
INIT_3E => X"af03af270003278f0300ac343c343cafaf03af270003278f8f0300000c8f0000",
INIT_3F => X"008fafaf03af270003278f038f0014008faf00008f24008faf302c008f0010af"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
INIT_04 => X"42420200c4a0bebd00e0bdbec0004300c302c2000007624000c2c3c5c4a0bebd",
INIT_05 => X"00c20000040062024300c20000c4a0bebfbd00e0bdbec0004300c30200404200",
INIT_06 => X"00c2c30000c202c4a0bebfbd00e0bdbebfc0000040004200c20000400042c343",
INIT_07 => X"c000004100c2c24200c20000404200c200000000404200c200404200c2c24243",
INIT_08 => X"00400042c34300c20000c2c20000c440c660c2c3c6c5c4a0bebfbd00e0bdbebf",
INIT_09 => X"02a0bebd00e0bdbebfc0000040004200c24303c2c24200c2006202434200c200",
INIT_0A => X"00000000e0bdbebfc002020042020040000000a0bebfbd00e0bdbec042004242",
INIT_0B => X"44020000440245020600004402450206000044020000440200004402a0bebfbd",
INIT_0C => X"04450246024702a24202a202000004450246024702a24202a202000044020000",
INIT_0D => X"00004402450246024702a24202a20200004402450246024702a24202a2020000",
INIT_0E => X"4402000000004402000044020000000044020000440200000000440200004402",
INIT_0F => X"0200004402000000004402004000420200004402000044020000000044020000",
INIT_10 => X"c2020000c202c0c0a0bebfbd00e0bdbebfc00000000400004005004202000044",
INIT_11 => X"00c40500004000c200406200c2c3c24200c20000c000400007624000c2c30000",
INIT_12 => X"4200c2c202006200c24362420300c30200004005004262420300c30200000400",
INIT_13 => X"004402000043024300420200004402006202c300404200c2c24200c2000004c2",
INIT_14 => X"00c20000040000c4c24300c3c20000c0c0c6c5c4a0bebfbd00e0bdbebfc00000",
INIT_15 => X"00c2c2424200c2c202006200c2436200c30200c200000400004000426200c302",
INIT_16 => X"00004402000043024300420200004402006202c30000c4050000004402004042",
INIT_17 => X"c20000040000c4c2006200c2c30000c0c0c7c6c5c4a0bebfbd00e0bdbebfc000",
INIT_18 => X"c2c2424200c2c202006200c2436200c30200c200000400004000426200c30200",
INIT_19 => X"00426200c30200c20000040000c4c2006200c24300c20000c000000400404200",
INIT_1A => X"00000400404200c2c2424200c2c202006200c2436200c30200c2000004000040",
INIT_1B => X"00004000426200c302624202c30000040000c4c2000007624000c3c20000c202",
INIT_1C => X"0200000400404200c2c2424200c2c202006200c2436200c302624202c3000004",
INIT_1D => X"000400004000426200c302624202c30000040000c4c20007624000c3c20000c2",
INIT_1E => X"05000000440200404200c2c2424200c2c202006200c2436200c302624202c300",
INIT_1F => X"bfbd00e0bdbebfc00000004402000043024300420200004402006202c30000c4",
INIT_20 => X"0004000040004262420300c3020000040000c4c26200c2c30000c0c0c202a0be",
INIT_21 => X"00c2c30000c000000400404200c2c24200c2c202006200c24362420300c30200",
INIT_22 => X"6200c24362420300c302000004000040004262420300c3020000040000c4c262",
INIT_23 => X"000043024300420200004402006202c30000440200404200c2c24200c2c20200",
INIT_24 => X"c2030200c24382c4c2030200c20000c0c0a0bebfbd00e0bdbebfc00000004402",
INIT_25 => X"00c2004262c3c20000c000404200c2c24200c24300c362c30200c24382c40200",
INIT_26 => X"6200c24362420300c30200000400004005004262420300c3020000040000c405",
INIT_27 => X"0400004005004262420300c3020000040000c40500c2004262c30200c2c20200",
INIT_28 => X"020000040000c40500c2004262c30200c2c202006200c24362420300c3020000",
INIT_29 => X"c2c24200c2c202006200c24362420300c30200000400004005004262420300c3",
INIT_2A => X"bebfc00000004402000043024300420200004402006202c30000440200404200",
INIT_2B => X"0000040000400042020000040000c4c26200c2c3c0c202c202a0bebfbd00e0bd",
INIT_2C => X"434202000004000040004242020000040000c4c26200c2c3c202006200c24302",
INIT_2D => X"00c2434202000004000040004242020000040000c4c26200c2c3c202006200c2",
INIT_2E => X"02006200c2434202000004000040004242020000040000c4c20200c2c2020062",
INIT_2F => X"00c2c202006200c2434202000004000040004242020000040000c4c24200c2c2",
INIT_30 => X"006202c300004402c202006200c2434202000040004242020000040000c4c242",
INIT_31 => X"42004202c4a0bebd0000e0bdbebfc00000004402000043024300420200004402",
INIT_32 => X"c202c4a0bebd00e0bdbec0020000004302430042024300c36242030243020040",
INIT_33 => X"40620243020000020062024302004000c24303c2c000000043030040004200c2",
INIT_34 => X"bebd00e0bdbec0024000c2c00000400243030240024300630302004000420200",
INIT_35 => X"0000020062024302004000c24303c2c000000043030040004200c2c202c0c4a0",
INIT_36 => X"02438242040243024402004042004202004000c2004000c2c2004202c2004202",
INIT_37 => X"c200c2c5c4a0bebd00e0bdbec0024000c2c00000430302400240024302430042",
INIT_38 => X"00c0c7c6c5c4a0bebfbd00e0bdbec0c200400042430063c46400c3c34300c200",
INIT_39 => X"c2c3c2020000c202006202c3004100c2c000404200c2c24200c2430362c3c200",
INIT_3A => X"00c200404200c2c2000007624000c3c2c20007624000c3c20000c202c2006200",
INIT_3B => X"4062004200c26200c203004000c26283c4c3020242424200c200000202424242",
INIT_3C => X"c20040004200c2430362c3c2c24200c2006202c3000000004100c2c24200c200",
INIT_3D => X"c362034200c200004300c26200c2030000c4406200c2c30040628200c2044300",
INIT_3E => X"c4a0bebd00e0bdbec0004363034202c5c4a0bebd00e0bdbebfc0000000c44062",
INIT_3F => X"00c2c5c4a0bebd00e0bdbec0c2004000c2c26200c34200c2c2424200c20000c0"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000000000000000ff00000800ff1800350035003300b200",
INIT_01 => X"000000000000000000000000000000000000072000002000d800d800ff700000",
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000200000f000ff00000000e800000000800010100000000000000000f000ff",
INIT_05 => X"0000000000000000000000000000f00000ff00000000e8000000002000ff0000",
INIT_06 => X"0000000000000000f00000ff0000000000e80000ff0000000000002000000000",
INIT_07 => X"e80000ff000000ff000000002000000000000000200000000000000000000010",
INIT_08 => X"0020000000000000000000000007002800380000000000f00000ff0000000000",
INIT_09 => X"20f000ff0000000000e80000ff0000000000000000ff000000000000ff000000",
INIT_0A => X"0000000000000000e8161600002000ff000100f00000ff00000000e800000000",
INIT_0B => X"2a00000256922700000002561227000000002a0000002a0000002a00f00000ff",
INIT_0C => X"032800280028000028000000000200280028002800002800000000002a000000",
INIT_0D => X"0002230029002900290000290000000002430028002900290000290000000002",
INIT_0E => X"2a00000400002a0000002a00000500002a0000002a00000300002a0000002a00",
INIT_0F => X"0000002b00000000002b00000000330000002b0000002b00000200002a000000",
INIT_10 => X"0000000000000000f00000ff0000000000e8000000000001200030330000002b",
INIT_11 => X"010000300000000000ff10000000000000000000000000100000000000000000",
INIT_12 => X"0000000000000000000010241800000000012000300010241800000000000000",
INIT_13 => X"002b00000033000000330000002b000000000000ff0300000000000000000000",
INIT_14 => X"0000000000000000001000000000000000000000f00000ff0000000000e80000",
INIT_15 => X"000000ff00000000000000000000100000100000000000000020000010000010",
INIT_16 => X"00002b00000033000000330000002b0000000000000100003000002b0000ff00",
INIT_17 => X"000000000000000010000000000000000000000000f00000ff0000000000e800",
INIT_18 => X"0000ff0000000000000000000010000010000000000000002000001000001000",
INIT_19 => X"0000100000100000000000000000001000000001000000000000000000ff0000",
INIT_1A => X"00000000ff00000000ff00000000000000000000100000100000000000000020",
INIT_1B => X"00002000001000001010ff3f0000000000000000101000000000000000000000",
INIT_1C => X"0000000000ff00000000ff000000000000000000001000001010ff3f00000000",
INIT_1D => X"000000002000001000001010ff3f000000000000000010000000000000000000",
INIT_1E => X"003000002b0000ff00000000ff000000000000000000001000001010ff3f0000",
INIT_1F => X"00ff0000000000e80000002b00000033000000330000002b0000000000000100",
INIT_20 => X"000000002000001029180000000000000000000010000000000000000012f000",
INIT_21 => X"00000000000000000000ff000000000000000000000000000010291800000000",
INIT_22 => X"00000000102a180000000000000000200000102a180000000000000000000010",
INIT_23 => X"000033000000330000002b000000000000002c0000ff00000000000000000000",
INIT_24 => X"001c1c0000001000001e1e000000000000f00000ff0000000000e80000002b00",
INIT_25 => X"3000000010000000000000ff0000000000000000000010001000000010001000",
INIT_26 => X"00000000102c18000000000000000120003000102c1800000000000000010000",
INIT_27 => X"00000120003000102c1800000000000000010000300000001000100000000000",
INIT_28 => X"000000000001000030000000100010000000000000000000102c180000000000",
INIT_29 => X"000000000000000000000000102c18000000000000000120003000102c180000",
INIT_2A => X"0000e80000002b00000033000000330000002b000000000000002c0000ff0000",
INIT_2B => X"000000000020002c0000000000000000100000000000430012f00000ff000000",
INIT_2C => X"002c0000000000002000002c0000000000000000100000000000000000002c00",
INIT_2D => X"0000002c0000000000002000002c000000000000000010000000000000000000",
INIT_2E => X"0000000000002c0000000000002000002c000000000000000010000000000000",
INIT_2F => X"0000000000000000002c0000000000002000002c000000000000000000000000",
INIT_30 => X"0000000000002c00000000000000002c0000002000002c0000000000000000ff",
INIT_31 => X"0000330000f000ff000000000000e80000002b00000033000000330000002b00",
INIT_32 => X"000000f000ff00000000e8ff0000103300000033000000001035180033000000",
INIT_33 => X"0010400080000000000000320000000000000000000000000000000000000000",
INIT_34 => X"00ff00000000e8000000000000ff33003300003200000035007f000000330000",
INIT_35 => X"00000000000033000000000000000000000000000000000000000000000000f0",
INIT_36 => X"000010352000007f330000000000330000000000000000000000008000000080",
INIT_37 => X"0000000000f000ff00000000e8000000000000ff330000330032003300000033",
INIT_38 => X"000000000000f00000ff00000000e80000ff0000000000000000000000000000",
INIT_39 => X"000000ff0000000000000000000000000000ff00000000000000000010000000",
INIT_3A => X"0000000000000000101000000000000000100000000000000000000000100000",
INIT_3B => X"0010000000001800000000000000001800001616000000000000001616000000",
INIT_3C => X"00000000000000000010000000ff00000000ff0000000000ff000000ff000000",
INIT_3D => X"0010000000000000000000180000000006002810000000000010100000000000",
INIT_3E => X"00f000ff00000000e80000fc0000200000f000ff0000000000e8000006002810",
INIT_3F => X"00000000f000ff00000000e80000ff000000100000ff00000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"4c4844403c3834302c2824201c181410980e00ac04fd2a001800b0000000f001",
INIT_01 => X"504c4844403c3834302c2824201c18141000cc2410200060125c1058fc005450",
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
INIT_04 => X"00200000082504f80008100c2500000000100012100d1b020014101410250cf0",
INIT_05 => X"001800980d00040a000018001318251014e80008080425000000080000fa0200",
INIT_06 => X"001020001e101c2025181ce00008181014250000e90000001800982500001801",
INIT_07 => X"250000e0001010fc0010009825570014000700982530001400090a0014140f06",
INIT_08 => X"9825000010010010001810140016a025a42514a8a8a4a025989c60000820181c",
INIT_09 => X"002504f80008a0989c250000e400000010000d1010ff001000080a00ff001000",
INIT_0A => X"000000000818101425030000000000fd003c00251014e8000808042501000020",
INIT_0B => X"8000008878348c0002008878340c000100ae680000ae540000ae3c0025181ce0",
INIT_0C => X"2184009c00b40010d800140200e7070c0024003c00106000140100ae680000ae",
INIT_0D => X"00e7450174008c00a40010c800140400e72105fc0014002c00105000140300e7",
INIT_0E => X"f800008b00ae680000aee000006300ae680000aec80000fe00ae680000aea800",
INIT_0F => X"0000ae5000001300ae4800000700100000ae380000ae2800001400ae680000ae",
INIT_10 => X"1403004b10031c18252024d8000820181c250000980a0005250a25100000ae5c",
INIT_11 => X"05100a250026001400eb2a00101414020014000b140004100d1a020014100011",
INIT_12 => X"0100181c0100030010002170800018000005250a250021708000180000983a00",
INIT_13 => X"ae9c00000510000100100000ae7400000d011c00b2e800101002001000982018",
INIT_14 => X"001000983a00d4181807002810002c1014302c28252024d80008282024250000",
INIT_15 => X"001010ff0100101401000300180021002c80001000982000d425000021002c80",
INIT_16 => X"00aee400000510000100100000aed800000d01140005300a2500aec40000d120",
INIT_17 => X"1000983a00d418181218002810002d101434302c28252024d800082820242500",
INIT_18 => X"1010ff0100101401000300180021002c80001000982000d425000021002c8000",
INIT_19 => X"000021003080001000983a00d4181812180028230010002f1000980a00d00600",
INIT_1A => X"00980a00ce06001010ff0100101401000300180021003080001000982000d425",
INIT_1B => X"00d42500002100348021ffff1000983a00d4181812100d1a0200281000341001",
INIT_1C => X"0100980a00c90a001010ff010010140100030018002100348021ffff10009820",
INIT_1D => X"982000d42500002100388021ffff1000983a00d41818100d1a02002810003310",
INIT_1E => X"0a2500aef00000ca0a001010ff010010140100030018002100388021ffff1000",
INIT_1F => X"24d80008282024250000aee400000510000100100000aed800000d011400053c",
INIT_20 => X"982000d425000021ec8000100000983a00d41c1c21001018002b101418342520",
INIT_21 => X"001018002b1000980a00d20a00101001001014010003001c0021ec8000100000",
INIT_22 => X"03001c0021148000100000982000d425000021148000100000983a00d41c1c23",
INIT_23 => X"000510000100100000aed800000d011400ae140000d20a001010010010140100",
INIT_24 => X"10030000100c21101003000010001f1014259094680008282024250000aee400",
INIT_25 => X"2518000c21101000871000de0a0010100100103c001021108000101c21104000",
INIT_26 => X"030018002158800010000098200005250a250021588000100000983a0005180a",
INIT_27 => X"200005250a250021588000100000983a0005180a2518001c2110400010140100",
INIT_28 => X"0000983a0005180a2518003c2110800010140100030018002158800010000098",
INIT_29 => X"10100100101401000300180021588000100000980a0005250a25002158800010",
INIT_2A => X"9094250000aee400000510000100100000aed800000d011400ae300000760a00",
INIT_2B => X"00982000d42500800000983a00d41c1c240018141018211434252024d8000898",
INIT_2C => X"04800000982000d4250004800000983a00d41c1c2500181410010003001c8000",
INIT_2D => X"001c08800000982000d4250008800000983a00d41c1c2600181410010003001c",
INIT_2E => X"010003001c0c800000982000d425000c800000983a00d41c1c27001410010003",
INIT_2F => X"001410010003001c10800000982000d4250010800000983a00d41c1c12001410",
INIT_30 => X"000d011000ae400010010003001c14800000d4250014800000983a00d41c1cee",
INIT_31 => X"0f002400082504f8000008282024250000aee400000510000100100000aed800",
INIT_32 => X"000110250cf00008080425ff0002252400010024000000082130800024000013",
INIT_33 => X"0b24000000001f01000401f0000006000000321000002a000732000600000010",
INIT_34 => X"14e80008100c25030000100000d82c00280100f00000003000fc000600240000",
INIT_35 => X"003401000401280000060000005d1800003f00075d0006000000180001041825",
INIT_36 => X"00002170800000fc200000100f00200000160008001a00040800000004000004",
INIT_37 => X"0000101410250cf00008181425030000180000c32c01002800f0002000010020",
INIT_38 => X"0a104c48444025383cc00008100c250000f20000000000140100141001001000",
INIT_39 => X"184018ff0003180100050a48000500402f00f30f001010010010102021101000",
INIT_3A => X"0010000a0a00101c12100d1b02001c4810100d1b02001c48003e140e1c121800",
INIT_3B => X"0b2a0000004c2300140f000c001c102110140300ff57ff001000080300ff30ff",
INIT_3C => X"4c000b0000004c102d21101414ff0014000aff1800000200c0001414ff001400",
INIT_3D => X"20230f00004c000c00004c2300140f00f844252100142000122a2300140f0000",
INIT_3E => X"10250cf000080804250000180360000c082504f8000840383c250000f8442521",
INIT_3F => X"00080c082504f80008100c250000f1001010240010ff001000ff010000000d00"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"00008f8faf000c8faf0000008f00008fafaf03afaf270003278f030000008f00",
INIT_01 => X"8f0000003c8fac008fac008fac008f30008fafafafafaf03af270003278f8f03",
INIT_02 => X"0010248f001428008faf24008faf00008f0030003000008f8c008f0010afac00",
INIT_03 => X"10240014008f8f001024001000008f8c008f001024001000008f8c008f001024",
INIT_04 => X"03af270003278f0300008faf03af270003278f0300001024001028008c008f00",
INIT_05 => X"3c000c243c000c343c343caf24afaf03afafaf27000003278f030000343c8faf",
INIT_06 => X"0004008c340010ac24ac343c24ae000c242424000c243cac008f343caf008c34",
INIT_07 => X"8fae000c242424000c24000c0024008f000c243c0014248faf000c8faf008c24",
INIT_08 => X"000000000003278f8f8f0300000c00142c008fac008f24af000c8f0010af2400",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000102040912000000",
INIT_0F => X"fffffffffffffffffffffffffffffffffffffffffffffefcf9f2e4c992000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000606060606050000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000010101010101000000",
INIT_14 => X"3d3d3d3d3d3d676620740a0a747320650a000000000000000000000000000000",
INIT_15 => X"694c7363726d69546e616f6269546f6175206467730a00696920746c6c67730a",
INIT_16 => X"4e490a007420696c54004546455000454d500a6469540030617261736d657061",
INIT_17 => X"544c4c0a0a53200a4c2000454e490a0044414f4c41454e490a0044414f4c4145",
INIT_18 => X"0000000000000000000054204945540a54204d0a542043422f440a2054494920",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000102040912000000000000000000000000000000",
INIT_1F => X"fffffffffffffffffffffefcf9f2e4c992000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000606060606050000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000010101010101000000000000000000000000000000",
INIT_24 => X"7566542055000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000072756570695300736e61756369670a0a727475526e2068616e",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"6200c2c3c20000c4c2430300c30200c2c5c4a0bebfbd00e0bdbec0620200c202",
INIT_01 => X"c240026202c34000c24000c24300c24300c2c0c7c6c5c4a0bebd00e0bdbebfc0",
INIT_02 => X"006202c300404200c2c24200c2c24300c2404202424300c24300c20000c04300",
INIT_03 => X"0002006200c2c300000200404300c24300c200000200404300c24300c2000002",
INIT_04 => X"a0bebd00e0bdbec00200c2c4a0bebd00e0bdbec000000002004042004200c200",
INIT_05 => X"0200004402000044024502c202c5c4a0b0bebfbd0000e0bdbec002624202c3c4",
INIT_06 => X"00400042020000400243630302020000040510000044024300c34202c2004242",
INIT_07 => X"c20200000405100000040000400500c200004402006202c3c20000c4c2004202",
INIT_08 => X"0000000000e0bdb0bebfc000000000404200c24300c302c20000c40000c24200",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"00000000000000000000000000000000010204091224489123468d1a34000000",
INIT_0F => X"fffffffffffffffffffffffffffffefcf9f2e4c99224489123468d1a34000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000003030303030300000000000000",
INIT_12 => X"02010000000000000000000000000000010101020515100b0500fb1a150f0a05",
INIT_13 => X"0000000000000000000000000000000000000000000001504f4e4d4c4b050403",
INIT_14 => X"0a3d3d3d3d3d0a747369540a656d707247000000000000000000000000000000",
INIT_15 => X"6e69736379656e65737470696e656e63622f6920740a006f762f69697420740a",
INIT_16 => X"554d0a0073746c206f00444144410053414c0a6f6e6500306e206c206220726c",
INIT_17 => X"4949540a0a45500a4546005347460a0021534e414c52554d0a0021494e414c52",
INIT_18 => X"0000000000000000000020544f52200a20544f0a2054545420450a00454f562f",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"00000000010204091224489123468d1a34000000000000000000000000000000",
INIT_1F => X"fffffefcf9f2e4c99224489123468d1a34000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000003030303030300000000000000000000000000000000000000",
INIT_22 => X"00000000010101020515100b0500fb1a150f0a05000000000000000000000000",
INIT_23 => X"0000000000000000000001504f4e4d4c4b050403020100000000000000000000",
INIT_24 => X"20203a5441000000000000000000000000000000000000000000000000000000",
INIT_25 => X"00000000000000206d74616e65007420746e6f6e690a006b2074542074696420",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"100000000000070000101f00001000000000f00000ff00000000e8101400001f",
INIT_01 => X"001814100f000000000000000000000000000000000000f000ff0000000000e8",
INIT_02 => X"0000000000ff0000000000000000100000180010001000000000000000000000",
INIT_03 => X"0000000000000000000000001000000000000000000000100000000000000000",
INIT_04 => X"f000ff00000000e817000000f000ff00000000e8100000000000000000000000",
INIT_05 => X"200000320000007801c20000000000f0000000ff0000000000e81010ff1f0000",
INIT_06 => X"00000000800000007f00ff0f7f00000700007f00003200000000002000000000",
INIT_07 => X"0000000700007f0000000001200030000000320000000000000008000000007f",
INIT_08 => X"00000000000000000000e810000100ff0300000000007f000008000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0101010101010101010101010101010000000000000000000000000000000000",
INIT_0B => X"0202020201010101010101010101010101010101010101010101010101010101",
INIT_0C => X"0202020202020202020202020202020202020202020202020202020202020202",
INIT_0D => X"0303030303030303030303030303030303030303030303030303030303030202",
INIT_0E => X"0000000000000000010204091224489123468d1a3468d1a2458a152b56030303",
INIT_0F => X"fffffffffffffefcf9f2e4c99224489123468d1a3468d1a2458a152b56000000",
INIT_10 => X"0000000000000000000000000000000000080808080707000000000000ffffff",
INIT_11 => X"000000000000000000000000000000000101039e9b9794918e0f0c0906030000",
INIT_12 => X"46230000000000000000000095a8c0e00d50c1a1439e5b17d4914e4f0cc98643",
INIT_13 => X"1212121212000000000000000000202429303a48619123c7a4815d3a17b08d69",
INIT_14 => X"003d3d3d3d3d0069686e650073616c6165121212121212121212121212121212",
INIT_15 => X"67730a65206d67730a69657467730a7474206e616954006e69206f63696d6954",
INIT_16 => X"4d4550003a65656674002149215300542041006e6773003020746c73656e696c",
INIT_17 => X"4f43494d0044410044410054205453000a53205443204d4550000a4c20544320",
INIT_18 => X"0000000000000000000000454e414f420045524d00454f5253524100534e4920",
INIT_19 => X"00000000000000000000000000000000000000000000000000001212ed515302",
INIT_1A => X"0101010000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0101010101010101010101010101010101010101010101010101010101010101",
INIT_1C => X"0202020202020202020202020202020202020202020202020101010101010101",
INIT_1D => X"0303030303030303030303030303030303030202020202020202020202020202",
INIT_1E => X"1224489123468d1a3468d1a2458a152b56030303030303030303030303030303",
INIT_1F => X"9224489123468d1a3468d1a2458a152b56000000000000000000000001020409",
INIT_20 => X"0000000000080808080707000000000000fffffffffffffffffffefcf9f2e4c9",
INIT_21 => X"000000000101039e9b9794918e0f0c0906030000000000000000000000000000",
INIT_22 => X"95a8c0e00d50c1a1439e5b17d4914e4f0cc98643000000000000000000000000",
INIT_23 => X"0000202429303a48619123c7a4815d3a17b08d69462300000000000000000000",
INIT_24 => X"6379204552121212121212121212121212121212121212121200000000000000",
INIT_25 => X"0000000000000000622063676e000a7469696d676e4200737770205568732072",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"250014101400dc101025400020400024242025181ce000080804252500000c00",
INIT_01 => X"20250224ff1000001c000018000014ff0010041c181410250cf0000820181c25",
INIT_02 => X"0004010400ea080000000100000421000425ff2b010700000000140013000000",
INIT_03 => X"0c04000400181c00140300042a002400001c001f0200042a0024000018002a01",
INIT_04 => X"2504f80008080425420008082504f80008100c25250002050004020000002000",
INIT_05 => X"0000ae6c000080407d000110013c38252c3034c80000080804254224feff0808",
INIT_06 => X"002e000000003300fc00fffffc0000f90103fc00aea800000014300014000050",
INIT_07 => X"100000f90103fc00980a0005250a251000aecc00001a011c1c009118180000fc",
INIT_08 => X"0b0705030008382c30342525006000cae90010000020fc20009d180009100100",
INIT_09 => X"9d97958b89837f716d6b67656159534f4947433d3b352f2b29251f1d1713110d",
INIT_0A => X"5b514b3d393733251b19150f0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a3",
INIT_0B => X"231d0b09fdf7f3ebe7dfd3cfcdc9c1bbb7b1afa5a399918d857f7b756f67615d",
INIT_0C => X"efe7e3ddd7cfc5bdb3aba5a195938d878381776b69655f5957514b413b39332d",
INIT_0D => X"d1cbc7b9b3ada9a1978f8b7773716d5f5b5955473d3b37352b291d130501f9f5",
INIT_0E => X"010204091224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78e5dfd7",
INIT_0F => X"f9f2e4c99224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78000000",
INIT_10 => X"070001020301010000000101010102030718110a03fcf5231c150e0700fffefc",
INIT_11 => X"0000010303010100010059647285a0c80b90212807e6c5a483a5846342210007",
INIT_12 => X"8a4500030103030001000100ae6472856dc80b90212807e6c5a483a584634221",
INIT_13 => X"38373635340005010300010001005d689c8b41d117a245c8833ef9b46f5914cf",
INIT_14 => X"003d3d3d3d3d006e696773007420616c6e2b2c2d2e2f30313233343d3c3b3a39",
INIT_15 => X"20740073616f2074006f722020740069727367646e65000a73646e6170756e65",
INIT_16 => X"422052002073646161000a4c00530020545300652074000a3168656d72756d20",
INIT_17 => X"4e4150550021530021490020544948000a4550495543422052000a4546495543",
INIT_18 => X"0908070605040302010000535354504900535945005352415520440054205344",
INIT_19 => X"6159534f4947433d3b352f2b29251f1d1713110d0b07050300002246cb153520",
INIT_1A => X"0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a39d97958b89837f716d6b6765",
INIT_1B => X"cdc9c1bbb7b1afa5a399918d857f7b756f67615d5b514b3d393733251b19150f",
INIT_1C => X"95938d878381776b69655f5957514b413b39332d231d0b09fdf7f3ebe7dfd3cf",
INIT_1D => X"73716d5f5b5955473d3b37352b291d130501f9f5efe7e3ddd7cfc5bdb3aba5a1",
INIT_1E => X"3468d1a2458a152b56ac59b367cf9e3c78e5dfd7d1cbc7b9b3ada9a1978f8b77",
INIT_1F => X"3468d1a2458a152b56ac59b367cf9e3c78000000010204091224489123468d1a",
INIT_20 => X"010102030718110a03fcf5231c150e0700fffefcf9f2e4c99224489123468d1a",
INIT_21 => X"7285a0c80b90212807e6c5a483a5846342210007070001020301010000000101",
INIT_22 => X"ae6472856dc80b90212807e6c5a483a584634221000001030301010001005964",
INIT_23 => X"01005d689c8b41d117a245c8833ef9b46f5914cf8a4500030103030001000100",
INIT_24 => X"616f4953542b2c2d2e2f30313233343d3c3b3a39383736353400050103000100",
INIT_25 => X"0000000100000000656e6b2064000a656f636d206e6500216f756f41652c7465",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Processor_NI/control.vhd | 9 | 16953 | ---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+4+2+4+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * EPC register have been changed! It used to be R0, now it is R26
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity control is
port(opcode : in std_logic_vector(31 downto 0); -- not opcode, but the whole instruction !!! (opcode is the first 6 most significant bits of the instruction.)
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end; --entity control
architecture logic of control is
begin
control_proc: process(opcode, intr_signal)
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
variable is_syscall : std_logic;
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rtx := opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
is_syscall := '0';
case op is
when "000000" => --SPECIAL
case func is
when "000000" => --SLL r[rd]=r[rt]<<re;
-- This is overlapping with NOP instruction in which all bits are zero, so opcode is zero and the last 6 bits (funct) are also zero,
-- does this mean that NOP acts as SLL ???
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000010" => --SRL r[rd]=u[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_shift;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000011" => --SRA r[rd]=r[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "000100" => --SLLV r[rd]=r[rt]<<r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000110" => --SRLV r[rd]=u[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000111" => --SRAV r[rd]=r[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "001000" => --JR s->pc_next=r[rs];
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
when "001001" => --JALR r[rd]=s->pc_next; s->pc_next=r[rs];
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--when "001010" => --MOVZ if(!r[rt]) r[rd]=r[rs]; /*IV*/
--when "001011" => --MOVN if(r[rt]) r[rd]=r[rs]; /*IV*/
when "001100" => --SYSCALL
is_syscall := '1';
when "001101" => --BREAK s->wakeup=1;
is_syscall := '1';
--when "001111" => --SYNC s->wakeup=1;
when "010000" => --MFHI r[rd]=s->hi;
c_source := C_FROM_MULT;
mult_function := MULT_READ_HI;
when "010001" => --MTHI s->hi=r[rs];
mult_function := MULT_WRITE_HI;
when "010010" => --MFLO r[rd]=s->lo;
c_source := C_FROM_MULT;
mult_function := MULT_READ_LO;
when "010011" => --MTLO s->lo=r[rs];
mult_function := MULT_WRITE_LO;
when "011000" => --MULT s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_SIGNED_MULT;
when "011001" => --MULTU s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_MULT;
when "011010" => --DIV s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_SIGNED_DIVIDE;
when "011011" => --DIVU s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_DIVIDE;
when "100000" => --ADD r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100001" => --ADDU r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100010" => --SUB r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100011" => --SUBU r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100100" => --AND r[rd]=r[rs]&r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_AND;
when "100101" => --OR r[rd]=r[rs]|r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_OR;
when "100110" => --XOR r[rd]=r[rs]^r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_XOR;
when "100111" => --NOR r[rd]=~(r[rs]|r[rt]);
c_source := C_FROM_ALU;
alu_function := ALU_NOR;
when "101010" => --SLT r[rd]=r[rs]<r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN_SIGNED;
when "101011" => --SLTU r[rd]=u[rs]<u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN;
when "101101" => --DADDU r[rd]=r[rs]+u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--when "110001" => --TGEU
--when "110010" => --TLT
--when "110011" => --TLTU
--when "110100" => --TEQ
--when "110110" => --TNE
when others =>
end case;
when "000001" => --REGIMM
rt := "000000";
rd := "011111";
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--if(test) pc=pc+imm*4
case rtx is
when "10000" => --BLTZAL r[31]=s->pc_next; branch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_LTZ;
when "00000" => --BLTZ branch=r[rs]<0;
branch_function := BRANCH_LTZ;
when "10001" => --BGEZAL r[31]=s->pc_next; branch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_GEZ;
when "00001" => --BGEZ branch=r[rs]>=0;
branch_function := BRANCH_GEZ;
--when "10010" => --BLTZALL r[31]=s->pc_next; lbranch=r[rs]<0;
--when "00010" => --BLTZL lbranch=r[rs]<0;
--when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
--when "00011" => --BGEZL lbranch=r[rs]>=0;
when others =>
end case;
when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
c_source := C_FROM_PC_PLUS4;
rd := "011111";
pc_source := FROM_OPCODE25_0;
when "000010" => --J s->pc_next=(s->pc&0xf0000000)|target;
pc_source := FROM_OPCODE25_0;
when "000100" => --BEQ branch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_EQ;
when "000101" => --BNE branch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_NE;
when "000110" => --BLEZ branch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := b_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_LEZ;
when "000111" => --BGTZ branch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
when "001000" => --ADDI r[rt]=r[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001001" => --ADDIU u[rt]=u[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001010" => --SLTI r[rt]=r[rs]<(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN_SIGNED;
when "001011" => --SLTIU u[rt]=u[rs]<(unsigned long)(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN;
when "001100" => --ANDI r[rt]=r[rs]&imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_AND;
when "001101" => --ORI r[rt]=r[rs]|imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_OR;
when "001110" => --XORI r[rt]=r[rs]^imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_XOR;
when "001111" => --LUI r[rt]=(imm<<16);
c_source := C_FROM_IMM_SHIFT16;
rd := rt;
when "010000" => --COP0
alu_function := ALU_OR;
c_source := C_FROM_ALU;
if opcode(23) = '0' then --move from CP0
rs := '1' & opcode(15 downto 11);
rt := "000000";
rd := '0' & opcode(20 downto 16);
else --move to CP0
rs := "000000";
rd(5) := '1';
pc_source := FROM_BRANCH; --delay possible interrupt
branch_function := BRANCH_NO;
end if;
--when "010001" => --COP1
--when "010010" => --COP2
--when "010011" => --COP3
--when "010100" => --BEQL lbranch=r[rs]==r[rt];
--when "010101" => --BNEL lbranch=r[rs]!=r[rt];
--when "010110" => --BLEZL lbranch=r[rs]<=0;
--when "010111" => --BGTZL lbranch=r[rs]>0;
when "011010" => -- SUBI r[rt]=r[rs]-(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_SUBTRACT;
when "100000" => --LB r[rt]=*(signed char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8S; --address=(short)imm+r[rs];
when "100001" => --LH r[rt]=*(signed short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16S; --address=(short)imm+r[rs];
when "100010" => --LWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100011" => --LW r[rt]=*(long*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100100" => --LBU r[rt]=*(unsigned char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8; --address=(short)imm+r[rs];
when "100101" => --LHU r[rt]=*(unsigned short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16; --address=(short)imm+r[rs];
--when "100110" => --LWR //Not Implemented
when "101000" => --SB *(char*)ptr=(char)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE8; --address=(short)imm+r[rs];
when "101001" => --SH *(short*)ptr=(short)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE16;
when "101010" => --SWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
when "101011" => --SW *(long*)ptr=r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--when "101110" => --SWR //Not Implemented
--when "101111" => --CACHE
--when "110000" => --LL r[rt]=*(long*)ptr;
--when "110001" => --LWC1
--when "110010" => --LWC2
--when "110011" => --LWC3
--when "110101" => --LDC1
--when "110110" => --LDC2
--when "110111" => --LDC3
--when "111000" => --SC *(long*)ptr=r[rt]; r[rt]=1;
--when "111001" => --SWC1
--when "111010" => --SWC2
--when "111011" => --SWC3
--when "111101" => --SDC1
--when "111110" => --SDC2
--when "111111" => --SDC3
when others =>
end case;
if c_source = C_FROM_NULL then
rd := "000000";
end if;
if intr_signal = '1' or is_syscall = '1' then
rs := "111111"; --interrupt vector
rt := "000000";
rd := "101110"; --save PC in EPC
alu_function := ALU_OR;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
branch_function := BRANCH_YES;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_PC;
pc_source := FROM_LBRANCH; -- "11"
mem_source := MEM_FETCH;
exception_out <= '1';
else
exception_out <= '0';
end if;
rs_index <= rs;
rt_index <= rt;
rd_index <= rd;
imm_out <= imm;
alu_func <= alu_function;
shift_func <= shift_function;
mult_func <= mult_function;
branch_func <= branch_function;
a_source_out <= a_source;
b_source_out <= b_source;
c_source_out <= c_source;
pc_source_out <= pc_source;
mem_source_out <= mem_source;
end process;
end; --logic
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/NI_Test/arbiter_in.vhd | 12 | 3876 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
-- Is this like the old arbiter in the router with handshaking FC ??
entity arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L:in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L:out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_in is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L)
begin
X_N <= '0';
X_E <= '0';
X_W <= '0';
X_S <= '0';
X_L <= '0';
case state is
when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S)
-- Here it seems N has the higest priority, is it fine ?
if req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
else
state_in <= state;
end if;
when North =>
if req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
else
state_in <= state;
end if;
when East =>
if req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
else
state_in <= state;
end if;
when West =>
if req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
else
state_in <= state;
end if;
when South =>
if req_X_S = '1' then
state_in <= South;
X_S <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
else
state_in <= state;
end if;
when others =>
if req_X_L = '1' then
state_in <= Local;
X_L <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S <= '1';
else
state_in <= state;
end if;
end case;
end process;
end;
| gpl-3.0 |
domagalski/pocketcorr | fpga/roach/fft_core_v5.vhd | 1 | 622 | library IEEE;
use IEEE.std_logic_1164.all;
entity fft_core_v5 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
pol0: in std_logic_vector(17 downto 0);
pol1: in std_logic_vector(17 downto 0);
pol2: in std_logic_vector(17 downto 0);
pol3: in std_logic_vector(17 downto 0);
shift: in std_logic_vector(15 downto 0);
sync: in std_logic;
oflow: out std_logic;
pol02_out: out std_logic_vector(35 downto 0);
pol13_out: out std_logic_vector(35 downto 0);
sync_out: out std_logic
);
end fft_core_v5;
architecture structural of fft_core_v5 is
begin
end structural;
| gpl-3.0 |
simoesusp/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/AP9_cpu.vhd | 2 | 31168 | ---------------------------------------------------
--apx-arch ap9 micro-processor---------------------
--16-bits width bus--------------------------------
--external clock-----------------------------------
--builded by microenix, cOPyright (r) 2011---------
--for detailed description about this--------------
--architechture, please refer to the ap9 reference--
--manual.------------------------------------------
---------------------------------------------------
libraRY ieee;
use ieee.std_LOGIC_1164.all;
use ieee.std_LOGIC_ARITH.all;
use ieee.std_LOGIC_unsigned.all;
entity AP9_cpu is
port( clk : in std_LOGIC;
reset : in std_LOGIC;
Mem : in STD_LOGIC_VECTOR(15 downto 0);
M5 : out STD_LOGIC_VECTOR(15 downto 0);
M1 : out STD_LOGIC_VECTOR(15 downto 0);
RW : out std_LOGIC;
key : in STD_LOGIC_VECTOR(7 downto 0);
videoflag : out std_LOGIC;
vga_pos : out STD_LOGIC_VECTOR(15 downto 0);
vga_char : out STD_LOGIC_VECTOR(15 downto 0);
Ponto : out STD_LOGIC_VECTOR(2 downto 0);
halt_ack : out std_LOGIC;
halt_req : in std_LOGIC;
PC_data : out STD_LOGIC_VECTOR(15 downto 0)
);
end AP9_cpu;
ARCHITECTURE main of AP9_cpu is
TYPE STATES is (fetch, decode, exec, halted); -- Estados da Maquina de Controle do Processador
TYPE Registers is array(0 to 7) of STD_LOGIC_VECTOR(15 downto 0); -- Banco de Registradores
TYPE LoadRegisters is array(0 to 7) of std_LOGIC; -- Sinais de LOAD dos Registradores do Banco
-- INSTRUCTION SET: 29 INSTRUCTIONS
-- Data Manipulation Instructions: -- Usage -- Action -- Format
CONSTANT LOAD : STD_LOGIC_VECTOR(5 downto 0) := "110000"; -- LOAD RX END -- RX <- M[END] Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END
CONSTANT STORE : STD_LOGIC_VECTOR(5 downto 0) := "110001"; -- STORE END RX -- M[END] <- RX Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END
CONSTANT LOADIMED : STD_LOGIC_VECTOR(5 downto 0) := "111000"; -- LOADN RX Nr -- RX <- Nr Format: < inst(6) | RX(3) | xxxxxxb0 > + 16bit Numero
CONSTANT LOADINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111100"; -- LOADI RX RY -- RX <- M[RY] Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT STOREINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111101"; -- STOREI RX RY -- M[RX] <- RY Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT MOV : STD_LOGIC_VECTOR(5 downto 0) := "110011"; -- MOV RX RY -- RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 >
-- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 >
-- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 >
-- I/O Instructions:
CONSTANT OUTCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110010"; -- OUTCHAR RX RY -- Video[RY] <- Char(RX) Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT INCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110101"; -- INCHAR RX -- RX[5..0] <- KeyPressed RX[15..6] <- 0's Format: < inst(6) | RX(3) | xxxxxxx >
-- Se nao pressionar nenhuma tecla, RX recebe 00FF
CONSTANT ARITH : STD_LOGIC_VECTOR(1 downto 0) := "10";
-- Aritmethic Instructions(All should begin wiht "10"):
CONSTANT ADD : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- ADD RX RY RZ / ADDC RX RY RZ -- RX <- RY + RZ / RX <- RY + RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT SUB : STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- SUB RX RY RZ / SUBC RX RY RZ -- RX <- RY - RZ / RX <- RY - RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT MULT : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- MUL RX RY RZ / MUL RX RY RZ -- RX <- RY * RZ / RX <- RY * RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT DIV : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- DIV RX RY RZ -- RX <- RY / RZ / RX <- RY / RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT INC : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- INC RX / DEC RX -- RX <- RX + 1 / RX <- RX - 1 -- b6= INC/DEC : 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
CONSTANT LMOD : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- MOD RX RY RZ -- RX <- RY MOD RZ Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LOGIC : STD_LOGIC_VECTOR(1 downto 0) := "01";
-- LOGIC Instructions (All should begin wiht "01"):
CONSTANT LAND : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- AND RX RY RZ -- RZ <- RX AND RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LOR : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- OR RX RY RZ -- RZ <- RX OR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LXOR : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- XOR RX RY RZ -- RZ <- RX XOR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LNOT : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- NOT RX RY -- RX <- NOT(RY) Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT SHIFT : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- SHIFTL0 RX,n / SHIFTL1 RX,n / SHIFTR0 RX,n / SHIFTR1 RX,n / ROTL RX,n / ROTR RX,n
-- SHIFT/Rotate RX -- b6=shif/rotate: 0/1 b5=left/right: 0/1; b4=fill;
-- Format: < inst(6) | RX(3) | b6 b5 b4 | nnnn >
CONSTANT CMP : STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- CMP RX RY -- Compare RX and RY and set FR : Format: < inst(6) | RX(3) | RY(3) | xxxx > Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
-- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED)
-- FLOW CONTROL Instructions:
CONSTANT JMP : STD_LOGIC_VECTOR(5 downto 0) := "000010"; -- JMP END -- PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END
CONSTANT CALL : STD_LOGIC_VECTOR(5 downto 0) := "000011"; -- CALL END -- M[SP] <- PC | SP-- | PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END
CONSTANT RTS : STD_LOGIC_VECTOR(5 downto 0) := "000100"; -- RTS -- SP++ | PC <- M[SP] | b6=RX/FR: 1/0 Format: < inst(6) | xxxxxxxxxx >
CONSTANT PUSH : STD_LOGIC_VECTOR(5 downto 0) := "000101"; -- PUSH RX / PUSH FR -- M[SP] <- RX / M[SP] <- FR | SP-- : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
CONSTANT POP : STD_LOGIC_VECTOR(5 downto 0) := "000110"; -- POP RX / POP FR -- SP++ | RX <- M[SP] / FR <- M[SP] : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
-- Control Instructions:
CONSTANT NOP : STD_LOGIC_VECTOR(5 downto 0) := "000000"; -- NOP -- Do Nothing Format: < inst(6) | xxxxxxxxxx >
CONSTANT HALT : STD_LOGIC_VECTOR(5 downto 0) := "001111"; -- HALT -- StOP Here Format: < inst(6) | xxxxxxxxxx >
CONSTANT SETC : STD_LOGIC_VECTOR(5 downto 0) := "001000"; -- CLEARC / SETC -- Set/Clear CarRY: b9 = 1-set; 0-clear Format: < inst(6) | b9 | xxxxxxxxx >
CONSTANT BREAKP : STD_LOGIC_VECTOR(5 downto 0) := "001110"; -- BREAK POINT -- Switch to manual clock Format: < inst(6) | xxxxxxxxxx >
-- CONSTANTes para controle do Mux2
CONSTANT sULA : STD_LOGIC_VECTOR (2 downto 0) := "000";
CONSTANT sMem : STD_LOGIC_VECTOR (2 downto 0) := "001";
CONSTANT sM4 : STD_LOGIC_VECTOR (2 downto 0) := "010";
CONSTANT skey : STD_LOGIC_VECTOR (2 downto 0) := "011";
--CONSTANT sTECLADO : STD_LOGIC_VECTOR (2 downto 0) := "011";
CONSTANT sSP : STD_LOGIC_VECTOR (2 downto 0) := "100";
-- CONSTANTes para controle do Mux2
-- CONSTANT sULA : STD_LOGIC_VECTOR(1 downto 0) := "00";
-- CONSTANT sMem : STD_LOGIC_VECTOR(1 downto 0) := "01";
-- CONSTANT sM4 : STD_LOGIC_VECTOR(1 downto 0) := "10";
-- CONSTANT skey : STD_LOGIC_VECTOR(1 downto 0) := "11";
-- Sinais para o Processo da ULA
signal OP : STD_LOGIC_VECTOR(6 downto 0); -- OP(6) deve ser setado para OPeracoes com carRY
signal x, y, result : STD_LOGIC_VECTOR(15 downto 0);
signal FR : STD_LOGIC_VECTOR(15 downto 0); -- Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
signal auxFR : STD_LOGIC_VECTOR(15 downto 0); -- Representa um barramento conectando a ULA ao Mux6 para escrever no FR
begin
-- Maquina de Controle
process(clk, reset)
--Register Declaration:
variable PC : STD_LOGIC_VECTOR(15 downto 0); -- Program Counter
variable IR : STD_LOGIC_VECTOR(15 downto 0); -- Instruction Register
variable SP : STD_LOGIC_VECTOR(15 downto 0); -- Stack Pointer
variable MAR : STD_LOGIC_VECTOR(15 downto 0); -- Memory address Register
--VARIABLE TECLADO :STD_LOGIC_VECTOR(15 downto 0); -- Registrador para receber dados do teclado
variable reg : Registers;
-- Mux dos barramentos de dados internos
VARIABLE M2 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos barramentos de dados internos para os Registradores
VARIABLE M3, M4 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos Registradores para as entradas da ULA
-- Novos Sinais da V2
variable LoadReg : LoadRegisters;
variable LoadIR : std_LOGIC;
variable LoadMAR : std_LOGIC;
variable LoadPC : std_LOGIC;
variable IncPC : std_LOGIC;
VARIABLE LoadSP : STD_LOGIC;
variable IncSP : std_LOGIC;
variable DecSP : std_LOGIC;
variable selM2 : STD_LOGIC_VECTOR(2 downto 0); -- VARIABLE selM2 :STD_LOGIC_VECTOR (2 downto 0);
variable selM6 : STD_LOGIC_VECTOR(2 downto 0); -- VARIABLE selM6 :STD_LOGIC_VECTOR (2 downto 0);
VARIABLE BreakFlag : STD_LOGIC;
variable state : STATES;
variable RX : integer;
variable RY : integer;
variable RZ : integer;
begin
if(reset = '1') then
state := fetch;
M1(15 downto 0) <= x"0000";
videoflag <= '0';
RX := 0;
RY := 0;
RZ := 0;
RW <= '0';
LoadIR := '0';
LoadMAR := '0';
LoadPC := '0';
IncPC := '0';
IncSP := '0';
DecSP := '0';
selM2 := sMem;
selM6 := sULA;
LoadReg(0) := '0';
LoadReg(1) := '0';
LoadReg(2) := '0';
LoadReg(3) := '0';
LoadReg(4) := '0';
LoadReg(5) := '0';
LoadReg(6) := '0';
LoadReg(7) := '0';
REG(0) := x"0000";
REG(1) := x"0000";
REG(2) := x"0000";
REG(3) := x"0000";
REG(4) := x"0000";
REG(5) := x"0000";
REG(6) := x"0000";
REG(7) := x"0000";
PC := x"0000";
SP := x"3ffc"; -- 7ffc
IR := x"0000";
MAR := x"0000";
-- TECLADO := x"0000";
BreakFlag:= '0'; -- Break Point Flag
--BREAK <= '0'; -- Break Point output to switch to manual clock
-- nao tinha
HALT_ack <= '0';
elsif(clk'event and clk = '1') then
if(LoadIR = '1') then IR := Mem; end if;
if(LoadPC = '1') then PC := Mem; end if;
if(IncPC = '1') then PC := PC + x"0001"; end if;
if(LoadMAR = '1') then MAR := Mem; end if;
if(LoadSP = '1') then SP := M3; end if;
if(IncSP = '1') then SP := SP + x"0001"; end if;
if(DecSP = '1') then SP := SP - x"0001"; end if;
-- Selecao do Mux6
if (selM6 = sULA) THEN FR <= auxFR; -- Sempre recebe flags da ULA
ELSIF (selM6 = sMem) THEN FR <= Mem; END IF; -- A menos que seja POP FR, quando recebe da Memoria
-- Atualiza o nome dos registradores!!!
RX := conv_integer(IR(9 downto 7));
RY := conv_integer(IR(6 downto 4));
RZ := conv_integer(IR(3 downto 1));
-- Selecao do Mux2
if (selM2 = sULA) THEN M2 := RESULT;
ELSIF (selM2 = sMem) THEN M2 := Mem;
ELSIF (selM2 = sM4) THEN M2 := M4;
ELSIF (selM2 = skey) THEN M2(15 downto 8) := x"00";
M2(7 downto 0) := key;
ELSIF (selM2 = sSP) THEN M2 := SP;
END IF;
-- if (LoadReg(RX) = '1') then REG(RX) := M2; end if;
if(LoadReg(RX) = '1') then reg(RX) := m2; end if;
-- Reseta os sinais de controle APOS usa-los acima
-- Zera todos os sinais de controle, para depois ligar um por um a medida que for necessario: a ultima atribuicao e' a que vale no processo!!!
LoadIR := '0';
LoadMAR := '0';
LoadPC := '0';
IncPC := '0';
IncSP := '0';
DecSP := '0';
LoadSP := '0';
selM6 := sULA; -- Sempre atualiza o FR da ULA, a nao ser que a instrucao seja POP FR
LoadReg(0) := '0';
LoadReg(1) := '0';
LoadReg(2) := '0';
LoadReg(3) := '0';
LoadReg(4) := '0';
LoadReg(5) := '0';
LoadReg(6) := '0';
LoadReg(7) := '0';
videoflag <= '0';
RW <= '0';
-- nao tinha
if(halt_req = '1') then state := halted; end if;
PC_data <= PC;
case state is
--************************************************************************
-- FETCH STATE
--************************************************************************
when fetch =>
PONTO <= "001";
-- Inicio das acoes do ciclo de Busca !!
M1 <= PC;
RW <= '0';
LoadIR := '1';
IncPC := '1';
STATE := decode;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- DECODE STATE
--************************************************************************
when decode =>
PONTO <= "010";
--========================================================================
-- INCHAR RX[5..0] <- KeyPressed RX[15..6] <- 0
--========================================================================
IF(IR(15 DOWNTO 10) = INCHAR) THEN
selM2 := skey;
LoadReg(RX) := '1';
state := fetch;
END IF;
--========================================================================
-- OUTCHAR Video[RY] <- Char(RX)
--========================================================================
IF(IR(15 DOWNTO 10) = OUTCHAR) THEN
M3 := Reg(Rx); -- M3 <- Rx
M4 := Reg(Ry); -- M4 <- Ry
vga_char <= M3;
vga_pos <= M4;
videoflag <= '1';
state := fetch;
END IF;
--========================================================================
-- MOV RX/SP <- RY/SP
-- MOV RX RY RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 >
-- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 >
-- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 >
--========================================================================
IF(IR(15 DOWNTO 10) = MOV) THEN
IF(IR(0) = '0') THEN
M4 := REG(RY);
selM2 := sM4;
LoadReg(RX) := '1';
ELSE
IF(IR(1) = '0') THEN
selM2 := sSP;
LoadReg(RX) := '1';
ELSE
M3 := REG(RX);
LoadSP := '1';
END IF;
END IF;
state := fetch;
END IF;
--========================================================================
-- STORE DIReto M[END] <- RX
--========================================================================
IF(IR(15 DOWNTO 10) = STORE) THEN -- Busca o endereco
M1 <= PC;
RW <= '0';
LoadMAR := '1';
IncPC := '1';
state := exec;
END IF;
--========================================================================
-- STORE indexado por registrador M[RX] <- RY
--========================================================================
IF(IR(15 DOWNTO 10) = STOREINDEX) THEN
M4 := Reg(Rx); -- M4 <- Rx
M1 <= M4; -- M1 <- M4
M3 := Reg(Ry); -- M3 <- Ry
M5 <= M3;
Rw <= '1'; -- Rw <- 1
state := fetch;
END IF;
--========================================================================
-- LOAD Direto RX <- M[End]
--========================================================================
IF(IR(15 DOWNTO 10) = LOAD) THEN -- Busca o endereco
M1 <= PC; -- M1 <- PC
Rw <= '0'; -- Rw <- 0
LoadMAR := '1';-- LMAR <- 1
IncPC := '1';
state := exec;
END IF;
--========================================================================
-- LOAD Imediato RX <- Nr
--========================================================================
IF(IR(15 DOWNTO 10) = LOADIMED) THEN
M1 <= PC; -- M1 <- PC
Rw <= '0'; -- Rw <= '0'
selM2 := sMeM; -- LRx <- 1
LoadReg(RX) := '1'; -- IncPC <- 1
IncPC := '1'; -- M2 <- MEM
state := fetch;
END IF;
--========================================================================
-- LOAD Indexado por registrador RX <- M(RY)
--========================================================================
IF(IR(15 DOWNTO 10) = LOADINDEX) THEN
M4 := Reg(Ry); -- M4 <- Ry
M1 <= M4; -- M1 <- M4
Rw <= '0'; -- Rw <- 0
selM2 := sMEM; -- M2 <- MEM
LoadReg(Rx) := '1'; -- LRx <- 1
state := fetch;
END IF;
--========================================================================
-- LOGIC OPERATION ('SHIFT', 'CMP' AND 'NOT' NOT INCLUDED) RX <- RY (?) RZ
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) /= SHIFT AND IR(13 DOWNTO 10) /= LNOT AND IR(13 DOWNTO 10) /= CMP) THEN
M3 := Reg(Ry);
M4 := Reg(Rz);
X <= M3;
Y <= M4;
OP(5 downto 0 ) <= IR(15 downto 10);
selM2 := sULA;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- NOT RX, RY RX <- NOT(RY)
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) = LNOT) THEN
M3 := REG(RX);
M4 := REG(RY);
X <= M3;
Y <= M4;
OP(5 downto 0) <= IR(15 downto 10);
selM2 := sULA;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- CMP RX, RY
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) = CMP) THEN
M3 := Reg(Rx);
M4 := Reg(Ry);
X <= M3;
Y <= M4;
OP(5 downto 0 ) <= IR(15 downto 10);
state := fetch;
END IF;
--========================================================================
-- SHIFT RX, RY RX <- SHIFT[ RY] ROTATE INCluded !
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC and (IR(13 DOWNTO 10) = SHIFT)) THEN
if(IR(6 DOWNTO 4) = "000") then -- SHIFT LEFT 0
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))sll conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 4) = "001") then -- SHIFT LEFT 1
Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))sll conv_integer(IR(3 DOWNTO 0))));
elsif(IR(6 DOWNTO 4) = "010") then -- SHIFT RIGHT 0
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))srl conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 4) = "011") then -- SHIFT RIGHT 0
Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))srl conv_integer(IR(3 DOWNTO 0))));
elsif(IR(6 DOWNTO 5) = "11") then -- ROTATE RIGHT
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))ror conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 5) = "10") then -- ROTATE LEFT
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))rol conv_integer(IR(3 DOWNTO 0)));
end if;
state := fetch;
end if;
--========================================================================
-- JMP END PC <- 16bit END : b9-b6 = COND
-- Flag Register: <...|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
--========================================================================
IF(IR(15 DOWNTO 10) = JMP) THEN
if((IR(9 downto 6) = "0000") or -- NO COND
(IR(9 downto 6) = "0111" and FR(0) = '1') or -- GREATER
(IR(9 downto 6) = "1001" and FR(2 downto 0) = "101") or -- greater equal
(IR(9 downto 6) = "1000" and FR(1) = '1') or -- lesser
(IR(9 downto 6) = "1010" and FR(2 downto 0) = "110") or -- lesser equal
(IR(9 downto 6) = "0001" and FR(2) = '1') or -- equal
(IR(9 downto 6) = "0010" and FR(2) = '0') or -- not equal
(IR(9 downto 6) = "0011" and FR(3) = '1') or -- zero
(IR(9 downto 6) = "0100" and FR(3) = '0') or -- not zero
(IR(9 downto 6) = "0101" and FR(4) = '1') or -- carry
(IR(9 downto 6) = "0110" and FR(4) = '0') or -- not carry
(IR(9 downto 6) = "1011" and FR(5) = '1') or -- overflow
(IR(9 downto 6) = "1100" and FR(5) = '0') or -- not overflow
(IR(9 downto 6) = "1101" and FR(6) = '1') or -- DIV0
(IR(9 downto 6) = "1110" and FR(9) = '1')) then -- result negative
M1 <= PC;
RW <= '0';
LoadPC := '1';
else
IncPC := '1';
end if;
state := fetch;
END IF;
--========================================================================
-- PUSH RX
--========================================================================
IF(IR(15 DOWNTO 10) = PUSH) THEN
M1 <= SP; -- M1 <- SP
Rw <= '1'; -- R/W <- 1
if(IR(6) = '0') then
M3 := Reg(Rx); -- M3 <- Rx
elsif(IR(6) = '1') then
M3 := FR;
end if;
M5 <= M3; -- M5 <- M3
DecSP := '1'; -- DecSP <- 1
state := fetch;
END IF;
--========================================================================
-- POP RX
--========================================================================
IF(IR(15 DOWNTO 10) = POP) THEN
IncSP := '1';
state := exec;
END IF;
--========================================================================
-- CALL END PC <- 16bit END : b9-b6 = COND PUSH(PC)
-- Flag Register: <...|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
--========================================================================
IF(IR(15 DOWNTO 10) = CALL) THEN
if((IR(9 downto 6) = "0000") or -- NO COND
(IR(9 downto 6) = "0111" and FR(0) = '1') or -- GREATER
(IR(9 downto 6) = "1001" and FR(2 downto 0) = "101") or -- greater equal
(IR(9 downto 6) = "1000" and FR(1) = '1') or -- lesser
(IR(9 downto 6) = "1010" and FR(2 downto 0) = "110") or -- lesser equal
(IR(9 downto 6) = "0001" and FR(2) = '1') or -- equal
(IR(9 downto 6) = "0010" and FR(2) = '0') or -- not equal
(IR(9 downto 6) = "0011" and FR(3) = '1') or -- zero
(IR(9 downto 6) = "0100" and FR(3) = '0') or -- not zero
(IR(9 downto 6) = "0101" and FR(4) = '1') or -- carry
(IR(9 downto 6) = "0110" and FR(4) = '0') or -- not carry
(IR(9 downto 6) = "1011" and FR(5) = '1') or -- overflow
(IR(9 downto 6) = "1100" and FR(5) = '0') or -- not overflow
(IR(9 downto 6) = "1101" and FR(6) = '1') or -- DIV0
(IR(9 downto 6) = "1110" and FR(9) = '1')) then -- result negative
RW <= '1'; -- Escreve PC na Pilha (M[SP] <- PC)
M5 <= PC;
M1 <= SP;
DecSP := '1';
state := exec;
ELSE
IncPC := '1';
state := fetch;
END IF;
END IF;
--========================================================================
-- RTS PC <- Mem[SP]
--========================================================================
IF(IR(15 DOWNTO 10) = RTS) THEN
IncSP := '1';
state := exec;
END IF;
--========================================================================
-- ARITH OPERATION ('INC' NOT INCLUDED) RX <- RY (?) RZ
--========================================================================
IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) /= INC) THEN
M3 := Reg(Ry);
M4 := Reg(RZ);
X <= M3;
Y <= M4;
OP(5 downto 0 ) <= IR(15 downto 10);
OP(6) <= IR(0);
selM2 := sULA;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- INC RX <- RX (+ or -) 1
--========================================================================
IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) = INC) THEN
M3 := Reg(Rx);
M4 := x"0001";
X <= M3;
Y <= M4;
OP(5 downto 4) <= ARITH;
IF(IR(6) = '0') THEN
OP(3 downto 0) <= ADD;
ELSE
OP(3 downto 0) <= SUB;
END IF;
selM2 := sULA;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- NOP
--========================================================================
IF( IR(15 DOWNTO 10) = NOP) THEN
state := fetch;
end if;
--========================================================================
-- HALT
--========================================================================
IF( IR(15 DOWNTO 10) = HALT) THEN
state := halted;
END IF;
--========================================================================
-- SETC/CLEARC
--========================================================================
IF( IR(15 DOWNTO 10) = SETC) THEN
FR(4) <= IR(9);
state := fetch;
end if;
--========================================================================
-- BREAKP
--========================================================================
IF( IR(15 DOWNTO 10) = BREAKP) THEN
BreakFlag := not(BreakFlag);
--BREAK <= BreakFlag;
state := fetch;
PONTO <= "101";
END IF;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- EXECUTE STATE
--************************************************************************
when exec =>
PONTO <= "100";
--========================================================================
-- EXEC STORE DIReto M[END] <- RX
--========================================================================
IF(IR(15 DOWNTO 10) = STORE) THEN
M1 <= MAR;
Rw <= '1';
M3 := Reg(Rx);
M5 <= M3;
state := fetch;
END IF;
--========================================================================
-- EXEC LOAD DIReto RX <- M[END]
--========================================================================
IF(IR(15 DOWNTO 10) = LOAD) THEN
M1 <= Mar;
Rw <= '0';
selM2 := sMem;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- EXEC POP RX
--========================================================================
IF(IR(15 DOWNTO 10) = POP) THEN
M1 <= SP; -- M1 <- SP
Rw <= '0'; -- R/W <- 0
if(IR(6) = '0') then
selM2 := sMem; -- M2 <- MEM
LoadReg(Rx) := '1'; -- LRx <- 1
elsif(IR(6) = '1') then
selM6 := sMem;
end if;
state := fetch;
END IF;
--========================================================================
-- EXEC CALL Pilha <- PC e PC <- 16bit END :
--========================================================================
IF(IR(15 DOWNTO 10) = CALL) THEN
M1 <= PC; -- M1 <- PC
Rw <= '0'; -- R/W <- 0
LoadPC := '1'; -- LPC <- 1
state := fetch;
END IF;
--========================================================================
-- EXEC RTS PC <- Mem[SP]
--========================================================================
IF(IR(15 DOWNTO 10) = RTS) THEN
M1 <= SP;
Rw <= '0';
LoadPC := '1';
IncPC := '1'; -- fazer em outro estado pq INCrementar e LOAD sao na SUBida de clock
state := fetch;
END IF;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- HALT STATE
--************************************************************************
WHEN halted =>
PONTO <= "111";
state := halted;
halt_ack <= '1';
WHEN OTHERS =>
state := fetch;
videoflag <= '0';
PONTO <= "000";
END CASE;
end if;
end process;
--************************************************************************
-- ULA ---> 3456 (3042)
--************************************************************************
PROCESS (OP, X, Y, reset)
VARIABLE AUX : STD_LOGIC_VECTOR(15 downto 0);
VARIABLE RESULT32 : STD_LOGIC_VECTOR(31 downto 0);
BEGIN
IF (reset = '1') THEN
auxFR <= x"0000";
RESULT <= x"0000";
else
auxFR <= FR;
--========================================================================
-- ARITH
--========================================================================
IF (OP (5 downto 4) = ARITH) THEN
CASE OP (3 downto 0) IS
WHEN ADD =>
IF (OP(6) = '1') THEN --Soma com carRY
AUX := X + Y + FR(4);
RESULT32 := (x"00000000" + X + Y + FR(4));
ELSE --Soma sem carRY
AUX := X + Y;
RESULT32 := (x"00000000" + X + Y);
end if;
if(RESULT32 > "01111111111111111") THEN -- CarRY
auxFR(4) <= '1';
ELSE
auxFR(4) <= '0';
end if;
WHEN SUB =>
AUX := X - Y;
WHEN MULT =>
RESULT32 := X * Y;
AUX := RESULT32(15 downto 0);
if(RESULT32 > x"0000FFFF") THEN -- ARITHmetic Overflow
auxFR(5) <= '1';
ELSE
auxFR(5) <= '0';
end if;
WHEN DIV =>
IF(Y = x"0000") THEN
AUX := x"0000";
auxFR(6) <= '1'; -- DIV by Zero
ELSE
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X)/CONV_INTEGER(Y), 16);
auxFR(6) <= '0';
END IF;
WHEN LMOD =>
IF(Y = x"0000") THEN
AUX := x"0000";
auxFR(6) <= '1'; -- DIV by Zero
ELSE
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X) mod CONV_INTEGER(Y), 16);
auxFR(6) <= '0';
END IF;
WHEN others => -- invalid operation, defaults to nothing
AUX := X;
END CASE;
if(AUX = x"0000") THEN
auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater>
ELSE
auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater>
end if;
if(AUX < x"0000") THEN -- NEGATIVO
auxFR(9) <= '1';
ELSE
auxFR(9) <= '0';
end if;
RESULT <= AUX;
ELSIF (OP (5 downto 4) = LOGIC) THEN
IF (OP (3 downto 0) = CMP) THEN
result <= x;
IF (x > y) THEN
auxFR(2 downto 0) <= "001"; -- FR = <...|zero|equal|lesser|greater>
ELSIF (x < y) THEN
auxFR(2 downto 0) <= "010"; -- FR = <...|zero|equal|lesser|greater>
ELSIF (x = y) THEN
auxFR(2 downto 0) <= "100"; -- FR = <...|zero|equal|lesser|greater>
END IF;
ELSE
CASE OP (3 downto 0) IS
WHEN LAND => result <= x and y;
WHEN LXOR => result <= x xor y;
WHEN LOR => result <= x or y;
WHEN LNOT => result <= not y;
WHEN others => -- invalid operation, defaults to nothing
RESULT <= X;
END CASE;
if(result = x"0000") THEN
auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater>
ELSE
auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater>
end if;
END IF;
END IF;
END IF; -- Reset
END PROCESS;
end main;
| gpl-3.0 |
domagalski/pocketcorr | fpga/roach2/pfb_core_v6.vhd | 1 | 367 | library IEEE;
use IEEE.std_logic_1164.all;
entity pfb_core_v6 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
pol1_in1: in std_logic_vector(15 downto 0);
sync: in std_logic;
pol1_out1: out std_logic_vector(35 downto 0);
sync_out: out std_logic
);
end pfb_core_v6;
architecture structural of pfb_core_v6 is
begin
end structural;
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/Router_32_bit_credit_based_packet_drop_classifier_SHMU_will_full_set_of_checkers.vhd | 3 | 499404 | --Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
use work.component_pack.all;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI (Outputs for classified fault information)
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
---- fault injector shift register with serial input signals
--TCK: in std_logic;
--SE: in std_logic; -- shift enable
--UE: in std_logic; -- update enable
--SI: in std_logic; -- serial Input
--SO: out std_logic; -- serial output
---- Outputs for non-classified fault information
--link_faults_async: out std_logic_vector(4 downto 0);
--turn_faults_async: out std_logic_vector(19 downto 0)
);
end router_credit_based_PD_C_SHMU;
architecture behavior of router_credit_based_PD_C_SHMU is
-------------------------------
-- Added because of Checkers --
-------------------------------
--signal combined_error_signals: std_logic_vector(19 downto 0); -- Shall we only consider this for the 20 bits showing the turn faults or individual checkers ?!
--signal shift_parallel_data: std_logic_vector(19 downto 0);
-------------------------------
-------------------------------
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal LBDR_Fault_N, LBDR_Fault_E, LBDR_Fault_W, LBDR_Fault_S, LBDR_Fault_L: std_logic;
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
-- Signals related to link fault classification modules
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
-- Signals related to Control part checkers fault classification modules
signal Healthy_N2E_turn_fault, intermittent_N2E_turn_fault, faulty_N2E_turn_fault: std_logic;
signal Healthy_N2W_turn_fault, intermittent_N2W_turn_fault, faulty_N2W_turn_fault: std_logic;
signal Healthy_E2N_turn_fault, intermittent_E2N_turn_fault, faulty_E2N_turn_fault: std_logic;
signal Healthy_E2S_turn_fault, intermittent_E2S_turn_fault, faulty_E2S_turn_fault: std_logic;
signal Healthy_W2N_turn_fault, intermittent_W2N_turn_fault, faulty_W2N_turn_fault: std_logic;
signal Healthy_W2S_turn_fault, intermittent_W2S_turn_fault, faulty_W2S_turn_fault: std_logic;
signal Healthy_S2E_turn_fault, intermittent_S2E_turn_fault, faulty_S2E_turn_fault: std_logic;
signal Healthy_S2W_turn_fault, intermittent_S2W_turn_fault, faulty_S2W_turn_fault: std_logic;
signal Healthy_N2S_path_fault, intermittent_N2S_path_fault, faulty_N2S_path_fault: std_logic;
signal Healthy_S2N_path_fault, intermittent_S2N_path_fault, faulty_S2N_path_fault: std_logic;
signal Healthy_E2W_path_fault, intermittent_E2W_path_fault, faulty_E2W_path_fault: std_logic;
signal Healthy_W2E_path_fault, intermittent_W2E_path_fault, faulty_W2E_path_fault: std_logic;
signal Healthy_L2N_fault, intermittent_L2N_fault, faulty_L2N_fault: std_logic;
signal Healthy_L2E_fault, intermittent_L2E_fault, faulty_L2E_fault: std_logic;
signal Healthy_L2W_fault, intermittent_L2W_fault, faulty_L2W_fault: std_logic;
signal Healthy_L2S_fault, intermittent_L2S_fault, faulty_L2S_fault: std_logic;
signal Healthy_N2L_fault, intermittent_N2L_fault, faulty_N2L_fault: std_logic;
signal Healthy_E2L_fault, intermittent_E2L_fault, faulty_E2L_fault: std_logic;
signal Healthy_W2L_fault, intermittent_W2L_fault, faulty_W2L_fault: std_logic;
signal Healthy_S2L_fault, intermittent_S2L_fault, faulty_S2L_fault: std_logic;
-- Signals needed for control part checkers
-- Signals needed for LBDR packet drop checkers
-- North
signal N_err_header_empty_Requests_FF_Requests_in,
N_err_tail_Requests_in_all_zero,
N_err_tail_empty_Requests_FF_Requests_in,
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
N_err_grants_onehot,
N_err_grants_mismatch,
N_err_header_tail_Requests_FF_Requests_in,
N_err_dst_addr_cur_addr_N1,
N_err_dst_addr_cur_addr_not_N1,
N_err_dst_addr_cur_addr_E1,
N_err_dst_addr_cur_addr_not_E1,
N_err_dst_addr_cur_addr_W1,
N_err_dst_addr_cur_addr_not_W1,
N_err_dst_addr_cur_addr_S1,
N_err_dst_addr_cur_addr_not_S1,
N_err_dst_addr_cur_addr_Req_L_in,
N_err_dst_addr_cur_addr_not_Req_L_in,
N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--N_err_header_not_empty_Req_L_in, -- added according to new design
N_err_header_not_empty_Req_N_in,
N_err_header_not_empty_Req_E_in,
N_err_header_not_empty_Req_W_in,
N_err_header_not_empty_Req_S_in,
N_err_header_empty_packet_drop_in_packet_drop_equal,
N_err_tail_not_empty_packet_drop_not_packet_drop_in,
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
N_err_packet_drop_order,
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- East
E_err_header_empty_Requests_FF_Requests_in,
E_err_tail_Requests_in_all_zero,
E_err_tail_empty_Requests_FF_Requests_in,
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
E_err_grants_onehot,
E_err_grants_mismatch,
E_err_header_tail_Requests_FF_Requests_in,
E_err_dst_addr_cur_addr_N1,
E_err_dst_addr_cur_addr_not_N1,
E_err_dst_addr_cur_addr_E1,
E_err_dst_addr_cur_addr_not_E1,
E_err_dst_addr_cur_addr_W1,
E_err_dst_addr_cur_addr_not_W1,
E_err_dst_addr_cur_addr_S1,
E_err_dst_addr_cur_addr_not_S1,
E_err_dst_addr_cur_addr_Req_L_in,
E_err_dst_addr_cur_addr_not_Req_L_in,
E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--E_err_header_not_empty_Req_L_in, -- added according to new design
E_err_header_not_empty_Req_N_in,
E_err_header_not_empty_Req_E_in,
E_err_header_not_empty_Req_W_in,
E_err_header_not_empty_Req_S_in,
E_err_header_empty_packet_drop_in_packet_drop_equal,
E_err_tail_not_empty_packet_drop_not_packet_drop_in,
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
E_err_packet_drop_order,
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- West
W_err_header_empty_Requests_FF_Requests_in,
W_err_tail_Requests_in_all_zero,
W_err_tail_empty_Requests_FF_Requests_in,
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
W_err_grants_onehot,
W_err_grants_mismatch,
W_err_header_tail_Requests_FF_Requests_in,
W_err_dst_addr_cur_addr_N1,
W_err_dst_addr_cur_addr_not_N1,
W_err_dst_addr_cur_addr_E1,
W_err_dst_addr_cur_addr_not_E1,
W_err_dst_addr_cur_addr_W1,
W_err_dst_addr_cur_addr_not_W1,
W_err_dst_addr_cur_addr_S1,
W_err_dst_addr_cur_addr_not_S1,
W_err_dst_addr_cur_addr_Req_L_in,
W_err_dst_addr_cur_addr_not_Req_L_in,
W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--W_err_header_not_empty_Req_L_in, -- added according to new design
W_err_header_not_empty_Req_N_in,
W_err_header_not_empty_Req_E_in,
W_err_header_not_empty_Req_W_in,
W_err_header_not_empty_Req_S_in,
W_err_header_empty_packet_drop_in_packet_drop_equal,
W_err_tail_not_empty_packet_drop_not_packet_drop_in,
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
W_err_packet_drop_order,
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- South
S_err_header_empty_Requests_FF_Requests_in,
S_err_tail_Requests_in_all_zero,
S_err_tail_empty_Requests_FF_Requests_in,
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
S_err_grants_onehot,
S_err_grants_mismatch,
S_err_header_tail_Requests_FF_Requests_in,
S_err_dst_addr_cur_addr_N1,
S_err_dst_addr_cur_addr_not_N1,
S_err_dst_addr_cur_addr_E1,
S_err_dst_addr_cur_addr_not_E1,
S_err_dst_addr_cur_addr_W1,
S_err_dst_addr_cur_addr_not_W1,
S_err_dst_addr_cur_addr_S1,
S_err_dst_addr_cur_addr_not_S1,
S_err_dst_addr_cur_addr_Req_L_in,
S_err_dst_addr_cur_addr_not_Req_L_in,
S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--S_err_header_not_empty_Req_L_in, -- added according to new design
S_err_header_not_empty_Req_N_in,
S_err_header_not_empty_Req_E_in,
S_err_header_not_empty_Req_W_in,
S_err_header_not_empty_Req_S_in,
S_err_header_empty_packet_drop_in_packet_drop_equal,
S_err_tail_not_empty_packet_drop_not_packet_drop_in,
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
S_err_packet_drop_order,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- Local
L_err_header_empty_Requests_FF_Requests_in,
L_err_tail_Requests_in_all_zero,
L_err_tail_empty_Requests_FF_Requests_in,
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
L_err_grants_onehot,
L_err_grants_mismatch,
L_err_header_tail_Requests_FF_Requests_in,
L_err_dst_addr_cur_addr_N1,
L_err_dst_addr_cur_addr_not_N1,
L_err_dst_addr_cur_addr_E1,
L_err_dst_addr_cur_addr_not_E1,
L_err_dst_addr_cur_addr_W1,
L_err_dst_addr_cur_addr_not_W1,
L_err_dst_addr_cur_addr_S1,
L_err_dst_addr_cur_addr_not_S1,
L_err_dst_addr_cur_addr_Req_L_in,
L_err_dst_addr_cur_addr_not_Req_L_in,
L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--L_err_header_not_empty_Req_L_in, -- added according to new design
L_err_header_not_empty_Req_N_in,
L_err_header_not_empty_Req_E_in,
L_err_header_not_empty_Req_W_in,
L_err_header_not_empty_Req_S_in,
L_err_header_empty_packet_drop_in_packet_drop_equal,
L_err_tail_not_empty_packet_drop_not_packet_drop_in,
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
L_err_packet_drop_order,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal: std_logic;
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-- Signals needed for FIFO packet drop with fault classifier support checkers
-- North
-- Functional checkers
signal N_err_empty_full, N_err_empty_read_en, N_err_full_write_en, N_err_state_in_onehot, N_err_read_pointer_in_onehot, N_err_write_pointer_in_onehot,
-- Structural checkers
N_err_write_en_write_pointer, N_err_not_write_en_write_pointer, N_err_read_pointer_write_pointer_not_empty, N_err_read_pointer_write_pointer_empty,
N_err_read_pointer_write_pointer_not_full, N_err_read_pointer_write_pointer_full, N_err_read_pointer_increment, N_err_read_pointer_not_increment,
N_err_write_en, N_err_not_write_en, N_err_not_write_en1, N_err_not_write_en2, N_err_read_en_mismatch, N_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
N_err_fake_credit_read_en_fake_credit_counter_in_increment,
N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
N_err_fake_credit_read_en_credit_out,
N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
N_err_state_out_Idle_not_fault_out_not_fake_credit,
N_err_state_out_Idle_not_fault_out_not_fault_info_in,
N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
N_err_state_out_Idle_fault_out_fake_credit,
N_err_state_out_Idle_fault_out_state_in_Packet_drop,
N_err_state_out_Idle_fault_out_fault_info_in,
N_err_state_out_Idle_fault_out_faulty_packet_in,
N_err_state_out_Idle_not_health_info,
N_err_state_out_Idle_not_write_fake_flit,
N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
N_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
N_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
N_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
N_err_state_out_Body_flit_valid_in_not_health_info,
N_err_state_out_Body_flit_not_fake_credit,
N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
N_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
N_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
N_err_state_out_Tail_flit_not_write_fake_flit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
N_err_fault_info_fault_info_out_equal,
N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- East
-- Functional checkers
E_err_empty_full, E_err_empty_read_en, E_err_full_write_en, E_err_state_in_onehot, E_err_read_pointer_in_onehot, E_err_write_pointer_in_onehot,
-- Structural checkers
E_err_write_en_write_pointer, E_err_not_write_en_write_pointer, E_err_read_pointer_write_pointer_not_empty, E_err_read_pointer_write_pointer_empty,
E_err_read_pointer_write_pointer_not_full, E_err_read_pointer_write_pointer_full, E_err_read_pointer_increment, E_err_read_pointer_not_increment,
E_err_write_en, E_err_not_write_en, E_err_not_write_en1, E_err_not_write_en2, E_err_read_en_mismatch, E_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
E_err_fake_credit_read_en_fake_credit_counter_in_increment,
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
E_err_fake_credit_read_en_credit_out,
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
E_err_state_out_Idle_not_fault_out_not_fake_credit,
E_err_state_out_Idle_not_fault_out_not_fault_info_in,
E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
E_err_state_out_Idle_fault_out_fake_credit,
E_err_state_out_Idle_fault_out_state_in_Packet_drop,
E_err_state_out_Idle_fault_out_fault_info_in,
E_err_state_out_Idle_fault_out_faulty_packet_in,
E_err_state_out_Idle_not_health_info,
E_err_state_out_Idle_not_write_fake_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
E_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
E_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
E_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
E_err_state_out_Body_flit_valid_in_not_health_info,
E_err_state_out_Body_flit_not_fake_credit,
E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
E_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
E_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
E_err_state_out_Tail_flit_not_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
E_err_fault_info_fault_info_out_equal,
E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- West
-- Functional checkers
W_err_empty_full, W_err_empty_read_en, W_err_full_write_en, W_err_state_in_onehot, W_err_read_pointer_in_onehot, W_err_write_pointer_in_onehot,
-- Structural checkers
W_err_write_en_write_pointer, W_err_not_write_en_write_pointer, W_err_read_pointer_write_pointer_not_empty, W_err_read_pointer_write_pointer_empty,
W_err_read_pointer_write_pointer_not_full, W_err_read_pointer_write_pointer_full, W_err_read_pointer_increment, W_err_read_pointer_not_increment,
W_err_write_en, W_err_not_write_en, W_err_not_write_en1, W_err_not_write_en2, W_err_read_en_mismatch, W_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
W_err_fake_credit_read_en_fake_credit_counter_in_increment,
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
W_err_fake_credit_read_en_credit_out,
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
W_err_state_out_Idle_not_fault_out_not_fake_credit,
W_err_state_out_Idle_not_fault_out_not_fault_info_in,
W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
W_err_state_out_Idle_fault_out_fake_credit,
W_err_state_out_Idle_fault_out_state_in_Packet_drop,
W_err_state_out_Idle_fault_out_fault_info_in,
W_err_state_out_Idle_fault_out_faulty_packet_in,
W_err_state_out_Idle_not_health_info,
W_err_state_out_Idle_not_write_fake_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
W_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
W_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
W_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
W_err_state_out_Body_flit_valid_in_not_health_info,
W_err_state_out_Body_flit_not_fake_credit,
W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
W_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
W_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
W_err_state_out_Tail_flit_not_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
W_err_fault_info_fault_info_out_equal,
W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- South
-- Functional checkers
S_err_empty_full, S_err_empty_read_en, S_err_full_write_en, S_err_state_in_onehot, S_err_read_pointer_in_onehot, S_err_write_pointer_in_onehot,
-- Structural checkers
S_err_write_en_write_pointer, S_err_not_write_en_write_pointer, S_err_read_pointer_write_pointer_not_empty, S_err_read_pointer_write_pointer_empty,
S_err_read_pointer_write_pointer_not_full, S_err_read_pointer_write_pointer_full, S_err_read_pointer_increment, S_err_read_pointer_not_increment,
S_err_write_en, S_err_not_write_en, S_err_not_write_en1, S_err_not_write_en2, S_err_read_en_mismatch, S_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
S_err_fake_credit_read_en_fake_credit_counter_in_increment,
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
S_err_fake_credit_read_en_credit_out,
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
S_err_state_out_Idle_not_fault_out_not_fake_credit,
S_err_state_out_Idle_not_fault_out_not_fault_info_in,
S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
S_err_state_out_Idle_fault_out_fake_credit,
S_err_state_out_Idle_fault_out_state_in_Packet_drop,
S_err_state_out_Idle_fault_out_fault_info_in,
S_err_state_out_Idle_fault_out_faulty_packet_in,
S_err_state_out_Idle_not_health_info,
S_err_state_out_Idle_not_write_fake_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
S_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
S_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
S_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
S_err_state_out_Body_flit_valid_in_not_health_info,
S_err_state_out_Body_flit_not_fake_credit,
S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
S_err_state_out_Tail_flit_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
S_err_fault_info_fault_info_out_equal,
S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- Local
-- Functional checkers
L_err_empty_full, L_err_empty_read_en, L_err_full_write_en, L_err_state_in_onehot, L_err_read_pointer_in_onehot, L_err_write_pointer_in_onehot,
-- Structural checkers
L_err_write_en_write_pointer, L_err_not_write_en_write_pointer, L_err_read_pointer_write_pointer_not_empty,
L_err_read_pointer_write_pointer_empty, L_err_read_pointer_write_pointer_not_full, L_err_read_pointer_write_pointer_full,
L_err_read_pointer_increment, L_err_read_pointer_not_increment, L_err_write_en, L_err_not_write_en, L_err_not_write_en1,
L_err_not_write_en2, L_err_read_en_mismatch, L_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
L_err_fake_credit_read_en_fake_credit_counter_in_increment,
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
L_err_fake_credit_read_en_credit_out,
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
L_err_state_out_Idle_not_fault_out_not_fake_credit,
L_err_state_out_Idle_not_fault_out_not_fault_info_in,
L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
L_err_state_out_Idle_fault_out_fake_credit,
L_err_state_out_Idle_fault_out_state_in_Packet_drop,
L_err_state_out_Idle_fault_out_fault_info_in,
L_err_state_out_Idle_fault_out_faulty_packet_in,
L_err_state_out_Idle_not_health_info,
L_err_state_out_Idle_not_write_fake_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
L_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
L_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
L_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
L_err_state_out_Body_flit_valid_in_not_health_info,
L_err_state_out_Body_flit_not_fake_credit,
L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
L_err_state_out_Tail_flit_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
L_err_fault_info_fault_info_out_equal,
L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in: std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Signals needed for Allocator unit
-- Allocator logic checker outputs
signal err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match: std_logic;
-- Allocator credit_counter logic checker outputs
signal err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter_in Checker signals (part of allocator unit)
-- North Arbiter_in checker outputs
signal N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N, N_err_IDLE_grant_N,N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E, N_err_West_Req_W,
N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L,
N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W, N_err_West_Req_S,
N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N,
N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S, N_err_West_Req_L,
N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E,
N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L, N_err_West_Req_N,
N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W,
N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N, N_err_West_Req_E,
N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S,
N_err_arbiter_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants,
N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L,
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E, E_err_West_Req_W,
E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L,
E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W, E_err_West_Req_S,
E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N,
E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S, E_err_West_Req_L,
E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E,
E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L, E_err_West_Req_N,
E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W,
E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N, E_err_West_Req_E,
E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S,
E_err_arbiter_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants,
E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L,
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E, W_err_West_Req_W,
W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L,
W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W, W_err_West_Req_S,
W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N,
W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S, W_err_West_Req_L,
W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E,
W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L, W_err_West_Req_N,
W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W,
W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N, W_err_West_Req_E,
W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S,
W_err_arbiter_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants,
W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L,
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N, S_err_IDLE_grant_N,S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E, S_err_West_Req_W,
S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L,
S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W, S_err_West_Req_S,
S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N,
S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S, S_err_West_Req_L,
S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E,
S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L, S_err_West_Req_N,
S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W,
S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N, S_err_West_Req_E,
S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S,
S_err_arbiter_state_in_onehot, S_err_no_request_grants, S_err_request_no_grants,
S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L,
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N, L_err_IDLE_grant_N,L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E,
L_err_East_grant_E, L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S,L_err_South_grant_S,
L_err_Local_Req_L, L_err_Local_grant_L,
L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W,
L_err_East_grant_W, L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L,
L_err_Local_Req_N, L_err_Local_grant_N,
L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S,
L_err_East_grant_S, L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N,
L_err_Local_Req_E, L_err_Local_grant_E,
L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L,
L_err_East_grant_L, L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E,
L_err_Local_Req_W, L_err_Local_grant_W,
L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N,
L_err_East_grant_N, L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W,
L_err_Local_Req_S, L_err_Local_grant_S,
L_err_arbiter_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants,
L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S,
L_err_no_Req_L_grant_L : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter_out Checker signals (part of allocator unit)
-- North Arbiter_out checker outputs
signal N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N,
N_err_North_req_X_N,
N_err_North_credit_not_zero_req_X_N_grant_N,
N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E,
N_err_East_credit_not_zero_req_X_E_grant_E,
N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W,
N_err_West_credit_not_zero_req_X_W_grant_W,
N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S,
N_err_South_credit_not_zero_req_X_S_grant_S,
N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L,
N_err_Local_credit_not_zero_req_X_L_grant_L,
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S,
N_err_South_req_X_L, N_err_Local_req_X_N,
N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L,
N_err_South_req_X_N, N_err_Local_req_X_E,
N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N,
N_err_South_req_X_E, N_err_Local_req_X_W,
N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E,
N_err_South_req_X_W, N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot,
N_arbiter_out_err_no_request_grants,
N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant,
N_err_state_West_Invalid_Grant, N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant,
N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N,
E_err_North_req_X_N,
E_err_North_credit_not_zero_req_X_N_grant_N,
E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E,
E_err_East_credit_not_zero_req_X_E_grant_E,
E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W,
E_err_West_credit_not_zero_req_X_W_grant_W,
E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S,
E_err_South_credit_not_zero_req_X_S_grant_S,
E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L,
E_err_Local_credit_not_zero_req_X_L_grant_L,
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N,
E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E,
E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W,
E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot,
E_arbiter_out_err_no_request_grants,
E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant, E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N,
W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S,
W_err_South_req_X_L, W_err_Local_req_X_N,
W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L,
W_err_South_req_X_N, W_err_Local_req_X_E,
W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N,
W_err_South_req_X_E, W_err_Local_req_X_W,
W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E,
W_err_South_req_X_W, W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot,
W_arbiter_out_err_no_request_grants,
W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant,W_err_state_East_Invalid_Grant,
W_err_state_West_Invalid_Grant, W_err_state_South_Invalid_Grant,W_err_state_Local_Invalid_Grant,
W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N,
S_err_North_credit_zero_or_not_req_X_N_not_grant_N, S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E,
S_err_East_credit_zero_or_not_req_X_E_not_grant_E, S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W,
S_err_West_credit_zero_or_not_req_X_W_not_grant_W, S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S,
S_err_South_credit_zero_or_not_req_X_S_not_grant_S, S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L,
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N,
S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E,
S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W,
S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N,
L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E,
L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
L_err_West_req_X_W, L_err_West_credit_not_zero_req_X_W_grant_W,
L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S,
L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L,
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N,
L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E,
L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W,
L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot,
L_arbiter_out_err_no_request_grants,
L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant,L_err_state_East_Invalid_Grant,
L_err_state_West_Invalid_Grant, L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant,
L_err_Grants_onehot_or_all_zero : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Signals needed for grouping checkers to model turn/path faults
signal N_FIFO_checkers_ORed, E_FIFO_checkers_ORed, W_FIFO_checkers_ORed, S_FIFO_checkers_ORed, L_FIFO_checkers_ORed : std_logic;
signal N2E_turn_fault, N2W_turn_fault, E2N_turn_fault, E2S_turn_fault, W2N_turn_fault, W2S_turn_fault, S2E_turn_fault, S2W_turn_fault : std_logic;
signal not_N2E_turn_fault, not_N2W_turn_fault, not_E2N_turn_fault, not_E2S_turn_fault, not_W2N_turn_fault, not_W2S_turn_fault, not_S2E_turn_fault, not_S2W_turn_fault : std_logic;
signal N2S_path_fault, S2N_path_fault, E2W_path_fault, W2E_path_fault : std_logic;
signal not_N2S_path_fault, not_S2N_path_fault, not_E2W_path_fault, not_W2E_path_fault : std_logic;
signal L2N_fault, L2E_fault, L2W_fault, L2S_fault, N2L_fault, E2L_fault, W2L_fault, S2L_fault : std_logic;
signal not_L2N_fault, not_L2E_fault, not_L2W_fault, not_L2S_fault, not_N2L_fault, not_E2L_fault, not_W2L_fault, not_S2L_fault : std_logic;
-- Just used temporarily for debugging purposes!
signal N_LBDR_checkers_ORed, E_LBDR_checkers_ORed, W_LBDR_checkers_ORed, S_LBDR_checkers_ORed, L_LBDR_checkers_ORed : std_logic;
signal Allocator_checkers_ORed : std_logic;
--signal turn_faults_sig : std_logic_vector(19 downto 0);
-------------------------------------------------------------------------------------------------
-- Added because of the chain we make for sending faulty values ---------------------------------
-- The chain is : L, N, E, W and S FIFO, then L, N, E, W and S LBDR, ----------------------------
-- then L, N, E, W and S Arbiter_in, --------------------
-- then L, N, E, W and S Arbiter_out and then Allocator's interlal logic ??!! --
-------------------------------------------------------------------------------------------------
signal fault_DO_serial_L_FIFO_to_N_FIFO, fault_DO_serial_N_FIFO_to_E_FIFO, fault_DO_serial_E_FIFO_to_W_FIFO, fault_DO_serial_W_FIFO_to_S_FIFO: std_logic;
signal fault_DO_serial_S_FIFO_to_L_LBDR, fault_DO_serial_L_LBDR_to_N_LBDR, fault_DO_serial_N_LBDR_to_E_LBDR, fault_DO_serial_E_LBDR_to_W_LBDR: std_logic;
signal fault_DO_serial_W_LBDR_to_S_LBDR, fault_DO_serial_S_LBDR_to_Allocator: std_logic;
------------------------------------------------------------------
------------------------------------------------------------------
begin
not_N2E_turn_fault <= not N2E_turn_fault;
not_N2W_turn_fault <= not N2W_turn_fault;
not_E2N_turn_fault <= not E2N_turn_fault;
not_E2S_turn_fault <= not E2S_turn_fault;
not_W2N_turn_fault <= not W2N_turn_fault;
not_W2S_turn_fault <= not W2S_turn_fault;
not_S2E_turn_fault <= not S2E_turn_fault;
not_S2W_turn_fault <= not W2S_turn_fault;
not_N2S_path_fault <= not N2S_path_fault;
not_S2N_path_fault <= not S2N_path_fault;
not_E2W_path_fault <= not E2W_path_fault;
not_W2E_path_fault <= not W2E_path_fault;
not_L2N_fault <= not L2N_fault;
not_L2E_fault <= not L2E_fault;
not_L2W_fault <= not L2W_fault;
not_L2S_fault <= not L2S_fault;
not_N2L_fault <= not N2L_fault;
not_E2L_fault <= not E2L_fault;
not_W2L_fault <= not W2L_fault;
not_S2L_fault <= not S2L_fault;
-- FIFO contributes to all turns and paths, therefore, for each turn or path (for the input direction), all the outputs of FIFO checkers
-- corresponding to that input are ORed together.
-- North
N_FIFO_checkers_ORed <= N_err_empty_full or
N_err_empty_read_en or
N_err_full_write_en or
N_err_state_in_onehot or
N_err_read_pointer_in_onehot or
N_err_write_pointer_in_onehot or
N_err_write_en_write_pointer or
N_err_not_write_en_write_pointer or
N_err_read_pointer_write_pointer_not_empty or
N_err_read_pointer_write_pointer_empty or
N_err_read_pointer_write_pointer_not_full or
N_err_read_pointer_write_pointer_full or
N_err_read_pointer_increment or
N_err_read_pointer_not_increment or
N_err_write_en or
N_err_not_write_en or
N_err_not_write_en1 or
N_err_not_write_en2 or
N_err_read_en_mismatch or
N_err_read_en_mismatch1 or
N_err_fake_credit_read_en_fake_credit_counter_in_increment or
N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
N_err_fake_credit_read_en_credit_out or
N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
N_err_state_out_Idle_not_fault_out_not_fake_credit or
N_err_state_out_Idle_not_fault_out_not_fault_info_in or
N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
N_err_state_out_Idle_fault_out_fake_credit or
N_err_state_out_Idle_fault_out_state_in_Packet_drop or
N_err_state_out_Idle_fault_out_fault_info_in or
N_err_state_out_Idle_fault_out_faulty_packet_in or
N_err_state_out_Idle_not_health_info or
N_err_state_out_Idle_not_write_fake_flit or
N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
N_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
N_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
N_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
N_err_state_out_Body_flit_valid_in_not_health_info or
N_err_state_out_Body_flit_not_fake_credit or
N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
N_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
N_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
N_err_state_out_Tail_flit_not_write_fake_flit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
N_err_fault_info_fault_info_out_equal or
N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- East
E_FIFO_checkers_ORed <= E_err_empty_full or
E_err_empty_read_en or
E_err_full_write_en or
E_err_state_in_onehot or
E_err_read_pointer_in_onehot or
E_err_write_pointer_in_onehot or
E_err_write_en_write_pointer or
E_err_not_write_en_write_pointer or
E_err_read_pointer_write_pointer_not_empty or
E_err_read_pointer_write_pointer_empty or
E_err_read_pointer_write_pointer_not_full or
E_err_read_pointer_write_pointer_full or
E_err_read_pointer_increment or
E_err_read_pointer_not_increment or
E_err_write_en or
E_err_not_write_en or
E_err_not_write_en1 or
E_err_not_write_en2 or
E_err_read_en_mismatch or
E_err_read_en_mismatch1 or
E_err_fake_credit_read_en_fake_credit_counter_in_increment or
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
E_err_fake_credit_read_en_credit_out or
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
E_err_state_out_Idle_not_fault_out_not_fake_credit or
E_err_state_out_Idle_not_fault_out_not_fault_info_in or
E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
E_err_state_out_Idle_fault_out_fake_credit or
E_err_state_out_Idle_fault_out_state_in_Packet_drop or
E_err_state_out_Idle_fault_out_fault_info_in or
E_err_state_out_Idle_fault_out_faulty_packet_in or
E_err_state_out_Idle_not_health_info or
E_err_state_out_Idle_not_write_fake_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
E_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
E_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
E_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
E_err_state_out_Body_flit_valid_in_not_health_info or
E_err_state_out_Body_flit_not_fake_credit or
E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
E_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
E_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
E_err_state_out_Tail_flit_not_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
E_err_fault_info_fault_info_out_equal or
E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- West
W_FIFO_checkers_ORed <= W_err_empty_full or W_err_empty_read_en or W_err_full_write_en or W_err_state_in_onehot or
W_err_read_pointer_in_onehot or W_err_write_pointer_in_onehot or
W_err_write_en_write_pointer or W_err_not_write_en_write_pointer or W_err_read_pointer_write_pointer_not_empty or
W_err_read_pointer_write_pointer_empty or W_err_read_pointer_write_pointer_not_full or
W_err_read_pointer_write_pointer_full or W_err_read_pointer_increment or W_err_read_pointer_not_increment or
W_err_write_en or W_err_not_write_en or W_err_not_write_en1 or W_err_not_write_en2 or W_err_read_en_mismatch or
W_err_read_en_mismatch1 or
W_err_fake_credit_read_en_fake_credit_counter_in_increment or
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
W_err_fake_credit_read_en_credit_out or
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
W_err_state_out_Idle_not_fault_out_not_fake_credit or
W_err_state_out_Idle_not_fault_out_not_fault_info_in or
W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
W_err_state_out_Idle_fault_out_fake_credit or
W_err_state_out_Idle_fault_out_state_in_Packet_drop or
W_err_state_out_Idle_fault_out_fault_info_in or
W_err_state_out_Idle_fault_out_faulty_packet_in or
W_err_state_out_Idle_not_health_info or
W_err_state_out_Idle_not_write_fake_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
W_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
W_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
W_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
W_err_state_out_Body_flit_valid_in_not_health_info or
W_err_state_out_Body_flit_not_fake_credit or
W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
W_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
W_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
W_err_state_out_Tail_flit_not_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
W_err_fault_info_fault_info_out_equal or
W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- South
S_FIFO_checkers_ORed <= S_err_empty_full or S_err_empty_read_en or S_err_full_write_en or S_err_state_in_onehot or
S_err_read_pointer_in_onehot or S_err_write_pointer_in_onehot or
S_err_write_en_write_pointer or S_err_not_write_en_write_pointer or
S_err_read_pointer_write_pointer_not_empty or S_err_read_pointer_write_pointer_empty or
S_err_read_pointer_write_pointer_not_full or S_err_read_pointer_write_pointer_full or
S_err_read_pointer_increment or S_err_read_pointer_not_increment or S_err_write_en or
S_err_not_write_en or S_err_not_write_en1 or S_err_not_write_en2 or S_err_read_en_mismatch or
S_err_read_en_mismatch1 or
S_err_fake_credit_read_en_fake_credit_counter_in_increment or
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
S_err_fake_credit_read_en_credit_out or
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
S_err_state_out_Idle_not_fault_out_not_fake_credit or
S_err_state_out_Idle_not_fault_out_not_fault_info_in or
S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
S_err_state_out_Idle_fault_out_fake_credit or
S_err_state_out_Idle_fault_out_state_in_Packet_drop or
S_err_state_out_Idle_fault_out_fault_info_in or
S_err_state_out_Idle_fault_out_faulty_packet_in or
S_err_state_out_Idle_not_health_info or
S_err_state_out_Idle_not_write_fake_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
S_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
S_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
S_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
S_err_state_out_Body_flit_valid_in_not_health_info or
S_err_state_out_Body_flit_not_fake_credit or
S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
S_err_state_out_Tail_flit_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
S_err_fault_info_fault_info_out_equal or
S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- Local
L_FIFO_checkers_ORed <= L_err_empty_full or L_err_empty_read_en or L_err_full_write_en or L_err_state_in_onehot or
L_err_read_pointer_in_onehot or L_err_write_pointer_in_onehot or
L_err_write_en_write_pointer or
L_err_not_write_en_write_pointer or
L_err_read_pointer_write_pointer_not_empty or
L_err_read_pointer_write_pointer_empty or
L_err_read_pointer_write_pointer_not_full or
L_err_read_pointer_write_pointer_full or
L_err_read_pointer_increment or
L_err_read_pointer_not_increment or
L_err_write_en or L_err_not_write_en or L_err_not_write_en1 or L_err_not_write_en2 or
L_err_read_en_mismatch or L_err_read_en_mismatch1 or
L_err_fake_credit_read_en_fake_credit_counter_in_increment or
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
L_err_fake_credit_read_en_credit_out or
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
L_err_state_out_Idle_not_fault_out_not_fake_credit or
L_err_state_out_Idle_not_fault_out_not_fault_info_in or
L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
L_err_state_out_Idle_fault_out_fake_credit or
L_err_state_out_Idle_fault_out_state_in_Packet_drop or
L_err_state_out_Idle_fault_out_fault_info_in or
L_err_state_out_Idle_fault_out_faulty_packet_in or
L_err_state_out_Idle_not_health_info or
L_err_state_out_Idle_not_write_fake_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
L_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
L_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
L_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
L_err_state_out_Body_flit_valid_in_not_health_info or
L_err_state_out_Body_flit_not_fake_credit or
L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
L_err_state_out_Tail_flit_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
L_err_fault_info_fault_info_out_equal or
L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
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-- Just for debugging purposes of the checkers!
-- LBDR checker outputs ORed
-- North
-- Routing part checkers
N_LBDR_checkers_ORed <= N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_N1 or
N_err_dst_addr_cur_addr_not_N1 or
N_err_dst_addr_cur_addr_E1 or
N_err_dst_addr_cur_addr_not_E1 or
N_err_dst_addr_cur_addr_W1 or
N_err_dst_addr_cur_addr_not_W1 or
N_err_dst_addr_cur_addr_S1 or
N_err_dst_addr_cur_addr_not_S1 or
N_err_dst_addr_cur_addr_Req_L_in or
N_err_dst_addr_cur_addr_not_Req_L_in or
N_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
N_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--N_err_header_not_empty_Req_L_in or -- added according to new design
N_err_header_not_empty_Req_N_in or
N_err_header_not_empty_Req_E_in or
N_err_header_not_empty_Req_W_in or
N_err_header_not_empty_Req_S_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
-- Cx_Reconf checkers
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- East
-- Routing part checkers
E_LBDR_checkers_ORed <= E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_N1 or
E_err_dst_addr_cur_addr_not_N1 or
E_err_dst_addr_cur_addr_E1 or
E_err_dst_addr_cur_addr_not_E1 or
E_err_dst_addr_cur_addr_W1 or
E_err_dst_addr_cur_addr_not_W1 or
E_err_dst_addr_cur_addr_S1 or
E_err_dst_addr_cur_addr_not_S1 or
E_err_dst_addr_cur_addr_Req_L_in or
E_err_dst_addr_cur_addr_not_Req_L_in or
E_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
E_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--E_err_header_not_empty_Req_L_in or -- added according to new design
E_err_header_not_empty_Req_N_in or
E_err_header_not_empty_Req_E_in or
E_err_header_not_empty_Req_W_in or
E_err_header_not_empty_Req_S_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
-- Cx_Reconf checkers
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- West
-- Routing part checkers
W_LBDR_checkers_ORed <= W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
W_err_grants_onehot or
W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_N1 or
W_err_dst_addr_cur_addr_not_N1 or
W_err_dst_addr_cur_addr_E1 or
W_err_dst_addr_cur_addr_not_E1 or
W_err_dst_addr_cur_addr_W1 or
W_err_dst_addr_cur_addr_not_W1 or
W_err_dst_addr_cur_addr_S1 or
W_err_dst_addr_cur_addr_not_S1 or
W_err_dst_addr_cur_addr_Req_L_in or
W_err_dst_addr_cur_addr_not_Req_L_in or
W_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
W_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--W_err_header_not_empty_Req_L_in or -- added according to new design
W_err_header_not_empty_Req_N_in or
W_err_header_not_empty_Req_E_in or
W_err_header_not_empty_Req_W_in or
W_err_header_not_empty_Req_S_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or
W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
-- Cx_Reconf checkers
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- South
-- Routing part checkers
S_LBDR_checkers_ORed <= S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_N1 or
S_err_dst_addr_cur_addr_not_N1 or
S_err_dst_addr_cur_addr_E1 or
S_err_dst_addr_cur_addr_not_E1 or
S_err_dst_addr_cur_addr_W1 or
S_err_dst_addr_cur_addr_not_W1 or
S_err_dst_addr_cur_addr_S1 or
S_err_dst_addr_cur_addr_not_S1 or
S_err_dst_addr_cur_addr_Req_L_in or
S_err_dst_addr_cur_addr_not_Req_L_in or
S_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
S_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--S_err_header_not_empty_Req_L_in or -- added according to new design
S_err_header_not_empty_Req_N_in or
S_err_header_not_empty_Req_E_in or
S_err_header_not_empty_Req_W_in or
S_err_header_not_empty_Req_S_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
-- Cx_Reconf checkers
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- Local
-- Routing part checkers
L_LBDR_checkers_ORed <= L_err_header_empty_Requests_FF_Requests_in or
L_err_tail_Requests_in_all_zero or
L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
L_err_grants_onehot or
L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or
L_err_dst_addr_cur_addr_N1 or
L_err_dst_addr_cur_addr_not_N1 or
L_err_dst_addr_cur_addr_E1 or
L_err_dst_addr_cur_addr_not_E1 or
L_err_dst_addr_cur_addr_W1 or
L_err_dst_addr_cur_addr_not_W1 or
L_err_dst_addr_cur_addr_S1 or
L_err_dst_addr_cur_addr_not_S1 or
L_err_dst_addr_cur_addr_Req_L_in or
L_err_dst_addr_cur_addr_not_Req_L_in or
L_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
L_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--L_err_header_not_empty_Req_L_in or -- added according to new design
L_err_header_not_empty_Req_N_in or
L_err_header_not_empty_Req_E_in or
L_err_header_not_empty_Req_W_in or
L_err_header_not_empty_Req_S_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
-- Cx_Reconf checkers
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
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-- Allocator checker outputs ORed !
-- Allocator logic checker outputs
Allocator_checkers_ORed <= err_grant_N_N_sig_not_empty_N_grant_N_N or err_not_grant_N_N_sig_or_empty_N_not_grant_N_N or
err_grant_N_E_sig_not_empty_E_grant_N_E or err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or
err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or
err_grant_N_S_sig_not_empty_S_grant_N_S or err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or
err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or
err_grant_E_N_sig_not_empty_N_grant_E_N or err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or
err_grant_E_E_sig_not_empty_E_grant_E_E or err_not_grant_E_E_sig_or_empty_E_not_grant_E_E or
err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or
err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or
err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or
err_grant_W_N_sig_not_empty_N_grant_W_N or err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or
err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or
err_grant_W_W_sig_not_empty_W_grant_W_W or err_not_grant_W_W_sig_or_empty_W_not_grant_W_W or
err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or
err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or
err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or
err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or
err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or
err_grant_S_S_sig_not_empty_S_grant_S_S or err_not_grant_S_S_sig_or_empty_S_not_grant_S_S or
err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or
err_grant_L_N_sig_not_empty_N_grant_L_N or err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or
err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or
err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or
err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or
err_grant_L_L_sig_not_empty_L_grant_L_L or err_not_grant_L_L_sig_or_empty_L_not_grant_L_L or
err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or
err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or
err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or
err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or
err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or
err_grants_valid_not_match or
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or
err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or
err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or
err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or
err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
-- Arbiter_in checker outputs
-- North Arbiter_in checker outputs
N_err_Requests_state_in_state_not_equal or
N_err_IDLE_Req_N or N_err_IDLE_grant_N or N_err_North_Req_N or N_err_North_grant_N or
N_err_East_Req_E or N_err_East_grant_E or N_err_West_Req_W or N_err_West_grant_W or
N_err_South_Req_S or N_err_South_grant_S or N_err_Local_Req_L or N_err_Local_grant_L or
N_err_IDLE_Req_E or N_err_IDLE_grant_E or N_err_North_Req_E or N_err_North_grant_E or
N_err_East_Req_W or N_err_East_grant_W or N_err_West_Req_S or N_err_West_grant_S or
N_err_South_Req_L or N_err_South_grant_L or N_err_Local_Req_N or N_err_Local_grant_N or
N_err_IDLE_Req_W or N_err_IDLE_grant_W or N_err_North_Req_W or N_err_North_grant_W or
N_err_East_Req_S or N_err_East_grant_S or N_err_West_Req_L or N_err_West_grant_L or
N_err_South_Req_N or N_err_South_grant_N or N_err_Local_Req_E or N_err_Local_grant_E or
N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or
N_err_East_Req_L or N_err_East_grant_L or N_err_West_Req_N or N_err_West_grant_N or
N_err_South_Req_E or N_err_South_grant_E or N_err_Local_Req_W or N_err_Local_grant_W or
N_err_IDLE_Req_L or N_err_IDLE_grant_L or N_err_North_Req_L or N_err_North_grant_L or
N_err_East_Req_N or N_err_East_grant_N or N_err_West_Req_E or N_err_West_grant_E or
N_err_South_Req_W or N_err_South_grant_W or N_err_Local_Req_S or N_err_Local_grant_S or
N_err_arbiter_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or
N_err_no_Req_N_grant_N or N_err_no_Req_E_grant_E or N_err_no_Req_W_grant_W or
N_err_no_Req_S_grant_S or N_err_no_Req_L_grant_L or
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal or
E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or E_err_North_grant_N or
E_err_East_Req_E or E_err_East_grant_E or E_err_West_Req_W or E_err_West_grant_W or
E_err_South_Req_S or E_err_South_grant_S or E_err_Local_Req_L or E_err_Local_grant_L or
E_err_IDLE_Req_E or E_err_IDLE_grant_E or E_err_North_Req_E or E_err_North_grant_E or
E_err_East_Req_W or E_err_East_grant_W or E_err_West_Req_S or E_err_West_grant_S or
E_err_South_Req_L or E_err_South_grant_L or E_err_Local_Req_N or E_err_Local_grant_N or
E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or
E_err_East_Req_S or E_err_East_grant_S or E_err_West_Req_L or E_err_West_grant_L or
E_err_South_Req_N or E_err_South_grant_N or E_err_Local_Req_E or E_err_Local_grant_E or
E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or
E_err_East_Req_L or E_err_East_grant_L or E_err_West_Req_N or E_err_West_grant_N or
E_err_South_Req_E or E_err_South_grant_E or E_err_Local_Req_W or E_err_Local_grant_W or
E_err_IDLE_Req_L or E_err_IDLE_grant_L or E_err_North_Req_L or E_err_North_grant_L or
E_err_East_Req_N or E_err_East_grant_N or E_err_West_Req_E or E_err_West_grant_E or
E_err_South_Req_W or E_err_South_grant_W or E_err_Local_Req_S or E_err_Local_grant_S or
E_err_arbiter_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or
E_err_no_Req_N_grant_N or E_err_no_Req_E_grant_E or E_err_no_Req_W_grant_W or
E_err_no_Req_S_grant_S or E_err_no_Req_L_grant_L or
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal or
W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or
W_err_East_Req_E or W_err_East_grant_E or W_err_West_Req_W or W_err_West_grant_W or
W_err_South_Req_S or W_err_South_grant_S or W_err_Local_Req_L or W_err_Local_grant_L or
W_err_IDLE_Req_E or W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or
W_err_East_Req_W or W_err_East_grant_W or W_err_West_Req_S or W_err_West_grant_S or
W_err_South_Req_L or W_err_South_grant_L or W_err_Local_Req_N or W_err_Local_grant_N or
W_err_IDLE_Req_W or W_err_IDLE_grant_W or W_err_North_Req_W or W_err_North_grant_W or
W_err_East_Req_S or W_err_East_grant_S or W_err_West_Req_L or W_err_West_grant_L or
W_err_South_Req_N or W_err_South_grant_N or W_err_Local_Req_E or W_err_Local_grant_E or
W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or
W_err_East_Req_L or W_err_East_grant_L or W_err_West_Req_N or W_err_West_grant_N or
W_err_South_Req_E or W_err_South_grant_E or W_err_Local_Req_W or W_err_Local_grant_W or
W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or
W_err_East_Req_N or W_err_East_grant_N or W_err_West_Req_E or W_err_West_grant_E or
W_err_South_Req_W or W_err_South_grant_W or W_err_Local_Req_S or W_err_Local_grant_S or
W_err_arbiter_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or
W_err_no_Req_N_grant_N or W_err_no_Req_E_grant_E or W_err_no_Req_W_grant_W or
W_err_no_Req_S_grant_S or W_err_no_Req_L_grant_L or
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal or
S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or
S_err_East_Req_E or S_err_East_grant_E or S_err_West_Req_W or S_err_West_grant_W or
S_err_South_Req_S or S_err_South_grant_S or S_err_Local_Req_L or S_err_Local_grant_L or
S_err_IDLE_Req_E or S_err_IDLE_grant_E or S_err_North_Req_E or S_err_North_grant_E or
S_err_East_Req_W or S_err_East_grant_W or S_err_West_Req_S or S_err_West_grant_S or
S_err_South_Req_L or S_err_South_grant_L or S_err_Local_Req_N or S_err_Local_grant_N or
S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or
S_err_East_Req_S or S_err_East_grant_S or S_err_West_Req_L or S_err_West_grant_L or
S_err_South_Req_N or S_err_South_grant_N or S_err_Local_Req_E or S_err_Local_grant_E or
S_err_IDLE_Req_S or S_err_IDLE_grant_S or S_err_North_Req_S or S_err_North_grant_S or
S_err_East_Req_L or S_err_East_grant_L or S_err_West_Req_N or S_err_West_grant_N or
S_err_South_Req_E or S_err_South_grant_E or S_err_Local_Req_W or S_err_Local_grant_W or
S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or
S_err_East_Req_N or S_err_East_grant_N or S_err_West_Req_E or S_err_West_grant_E or
S_err_South_Req_W or S_err_South_grant_W or S_err_Local_Req_S or S_err_Local_grant_S or
S_err_arbiter_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or
S_err_no_Req_N_grant_N or S_err_no_Req_E_grant_E or S_err_no_Req_W_grant_W or
S_err_no_Req_S_grant_S or S_err_no_Req_L_grant_L or
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal or
L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or
L_err_East_Req_E or L_err_East_grant_E or L_err_West_Req_W or L_err_West_grant_W or
L_err_South_Req_S or L_err_South_grant_S or L_err_Local_Req_L or L_err_Local_grant_L or
L_err_IDLE_Req_E or L_err_IDLE_grant_E or L_err_North_Req_E or L_err_North_grant_E or
L_err_East_Req_W or L_err_East_grant_W or L_err_West_Req_S or L_err_West_grant_S or
L_err_South_Req_L or L_err_South_grant_L or L_err_Local_Req_N or L_err_Local_grant_N or
L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or
L_err_East_Req_S or L_err_East_grant_S or L_err_West_Req_L or L_err_West_grant_L or
L_err_South_Req_N or L_err_South_grant_N or L_err_Local_Req_E or L_err_Local_grant_E or
L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or
L_err_East_Req_L or L_err_East_grant_L or L_err_West_Req_N or L_err_West_grant_N or
L_err_South_Req_E or L_err_South_grant_E or L_err_Local_Req_W or L_err_Local_grant_W or
L_err_IDLE_Req_L or L_err_IDLE_grant_L or L_err_North_Req_L or L_err_North_grant_L or
L_err_East_Req_N or L_err_East_grant_N or L_err_West_Req_E or L_err_West_grant_E or
L_err_South_Req_W or L_err_South_grant_W or L_err_Local_Req_S or L_err_Local_grant_S or
L_err_arbiter_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_N_grant_N or L_err_no_Req_E_grant_E or L_err_no_Req_W_grant_W or
L_err_no_Req_S_grant_S or L_err_no_Req_L_grant_L or
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal or
N_err_IDLE_req_X_N or
N_err_North_req_X_N or
N_err_North_credit_not_zero_req_X_N_grant_N or
N_err_North_credit_zero_or_not_req_X_N_not_grant_N or
N_err_East_req_X_E or
N_err_East_credit_not_zero_req_X_E_grant_E or
N_err_East_credit_zero_or_not_req_X_E_not_grant_E or
N_err_West_req_X_W or
N_err_West_credit_not_zero_req_X_W_grant_W or
N_err_West_credit_zero_or_not_req_X_W_not_grant_W or
N_err_South_req_X_S or
N_err_South_credit_not_zero_req_X_S_grant_S or
N_err_South_credit_zero_or_not_req_X_S_not_grant_S or
N_err_Local_req_X_L or
N_err_Local_credit_not_zero_req_X_L_grant_L or
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
N_err_IDLE_req_X_E or
N_err_North_req_X_E or
N_err_East_req_X_W or
N_err_West_req_X_S or
N_err_South_req_X_L or
N_err_Local_req_X_N or
N_err_IDLE_req_X_W or
N_err_North_req_X_W or
N_err_East_req_X_S or
N_err_West_req_X_L or
N_err_South_req_X_N or
N_err_Local_req_X_E or
N_err_IDLE_req_X_S or
N_err_North_req_X_S or
N_err_East_req_X_L or
N_err_West_req_X_N or
N_err_South_req_X_E or
N_err_Local_req_X_W or
N_err_IDLE_req_X_L or
N_err_North_req_X_L or
N_err_East_req_X_N or
N_err_West_req_X_E or
N_err_South_req_X_W or
N_err_Local_req_X_S or
N_arbiter_out_err_state_in_onehot or
N_arbiter_out_err_no_request_grants or
N_err_request_IDLE_state or
N_err_request_IDLE_not_Grants or
N_err_state_North_Invalid_Grant or
N_err_state_East_Invalid_Grant or
N_err_state_West_Invalid_Grant or
N_err_state_South_Invalid_Grant or
N_err_state_Local_Invalid_Grant or
N_err_Grants_onehot_or_all_zero or
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal or
E_err_IDLE_req_X_N or
E_err_North_req_X_N or
E_err_North_credit_not_zero_req_X_N_grant_N or
E_err_North_credit_zero_or_not_req_X_N_not_grant_N or
E_err_East_req_X_E or
E_err_East_credit_not_zero_req_X_E_grant_E or
E_err_East_credit_zero_or_not_req_X_E_not_grant_E or
E_err_West_req_X_W or
E_err_West_credit_not_zero_req_X_W_grant_W or
E_err_West_credit_zero_or_not_req_X_W_not_grant_W or
E_err_South_req_X_S or
E_err_South_credit_not_zero_req_X_S_grant_S or
E_err_South_credit_zero_or_not_req_X_S_not_grant_S or
E_err_Local_req_X_L or
E_err_Local_credit_not_zero_req_X_L_grant_L or
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
E_err_IDLE_req_X_E or E_err_North_req_X_E or E_err_East_req_X_W or E_err_West_req_X_S or E_err_South_req_X_L or
E_err_Local_req_X_N or
E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_East_req_X_S or E_err_West_req_X_L or E_err_South_req_X_N or
E_err_Local_req_X_E or
E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_East_req_X_L or E_err_West_req_X_N or E_err_South_req_X_E or
E_err_Local_req_X_W or
E_err_IDLE_req_X_L or E_err_North_req_X_L or E_err_East_req_X_N or E_err_West_req_X_E or E_err_South_req_X_W or
E_err_Local_req_X_S or
E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or
E_err_request_IDLE_state or
E_err_request_IDLE_not_Grants or E_err_state_North_Invalid_Grant or E_err_state_East_Invalid_Grant or
E_err_state_West_Invalid_Grant or E_err_state_South_Invalid_Grant or E_err_state_Local_Invalid_Grant or
E_err_Grants_onehot_or_all_zero or
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal or
W_err_IDLE_req_X_N or
W_err_North_req_X_N or
W_err_North_credit_not_zero_req_X_N_grant_N or
W_err_North_credit_zero_or_not_req_X_N_not_grant_N or
W_err_East_req_X_E or
W_err_East_credit_not_zero_req_X_E_grant_E or
W_err_East_credit_zero_or_not_req_X_E_not_grant_E or
W_err_West_req_X_W or
W_err_West_credit_not_zero_req_X_W_grant_W or
W_err_West_credit_zero_or_not_req_X_W_not_grant_W or
W_err_South_req_X_S or
W_err_South_credit_not_zero_req_X_S_grant_S or
W_err_South_credit_zero_or_not_req_X_S_not_grant_S or
W_err_Local_req_X_L or
W_err_Local_credit_not_zero_req_X_L_grant_L or
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
W_err_IDLE_req_X_E or W_err_North_req_X_E or W_err_East_req_X_W or W_err_West_req_X_S or W_err_South_req_X_L or
W_err_Local_req_X_N or
W_err_IDLE_req_X_W or W_err_North_req_X_W or W_err_East_req_X_S or W_err_West_req_X_L or W_err_South_req_X_N or
W_err_Local_req_X_E or
W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_East_req_X_L or W_err_West_req_X_N or W_err_South_req_X_E or
W_err_Local_req_X_W or
W_err_IDLE_req_X_L or W_err_North_req_X_L or W_err_East_req_X_N or W_err_West_req_X_E or W_err_South_req_X_W or
W_err_Local_req_X_S or
W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or
W_err_request_IDLE_state or
W_err_request_IDLE_not_Grants or W_err_state_North_Invalid_Grant or W_err_state_East_Invalid_Grant or
W_err_state_West_Invalid_Grant or W_err_state_South_Invalid_Grant or W_err_state_Local_Invalid_Grant or
W_err_Grants_onehot_or_all_zero or
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal or
S_err_IDLE_req_X_N or
S_err_North_req_X_N or
S_err_North_credit_not_zero_req_X_N_grant_N or
S_err_North_credit_zero_or_not_req_X_N_not_grant_N or
S_err_East_req_X_E or
S_err_East_credit_not_zero_req_X_E_grant_E or
S_err_East_credit_zero_or_not_req_X_E_not_grant_E or
S_err_West_req_X_W or
S_err_West_credit_not_zero_req_X_W_grant_W or
S_err_West_credit_zero_or_not_req_X_W_not_grant_W or
S_err_South_req_X_S or
S_err_South_credit_not_zero_req_X_S_grant_S or
S_err_South_credit_zero_or_not_req_X_S_not_grant_S or
S_err_Local_req_X_L or
S_err_Local_credit_not_zero_req_X_L_grant_L or
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
S_err_IDLE_req_X_E or S_err_North_req_X_E or S_err_East_req_X_W or
S_err_West_req_X_S or S_err_South_req_X_L or S_err_Local_req_X_N or
S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_East_req_X_S or
S_err_West_req_X_L or S_err_South_req_X_N or S_err_Local_req_X_E or
S_err_IDLE_req_X_S or S_err_North_req_X_S or S_err_East_req_X_L or
S_err_West_req_X_N or S_err_South_req_X_E or S_err_Local_req_X_W or
S_err_IDLE_req_X_L or S_err_North_req_X_L or S_err_East_req_X_N or
S_err_West_req_X_E or S_err_South_req_X_W or S_err_Local_req_X_S or
S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or
S_err_request_IDLE_not_Grants or S_err_state_North_Invalid_Grant or S_err_state_East_Invalid_Grant or
S_err_state_West_Invalid_Grant or S_err_state_South_Invalid_Grant or S_err_state_Local_Invalid_Grant or
S_err_Grants_onehot_or_all_zero or
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal or
L_err_IDLE_req_X_N or
L_err_North_req_X_N or
L_err_North_credit_not_zero_req_X_N_grant_N or
L_err_North_credit_zero_or_not_req_X_N_not_grant_N or
L_err_East_req_X_E or
L_err_East_credit_not_zero_req_X_E_grant_E or
L_err_East_credit_zero_or_not_req_X_E_not_grant_E or
L_err_West_req_X_W or
L_err_West_credit_not_zero_req_X_W_grant_W or
L_err_West_credit_zero_or_not_req_X_W_not_grant_W or
L_err_South_req_X_S or
L_err_South_credit_not_zero_req_X_S_grant_S or
L_err_South_credit_zero_or_not_req_X_S_not_grant_S or
L_err_Local_req_X_L or
L_err_Local_credit_not_zero_req_X_L_grant_L or
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
L_err_IDLE_req_X_E or L_err_North_req_X_E or L_err_East_req_X_W or L_err_West_req_X_S or L_err_South_req_X_L or
L_err_Local_req_X_N or
L_err_IDLE_req_X_W or L_err_North_req_X_W or L_err_East_req_X_S or L_err_West_req_X_L or L_err_South_req_X_N or
L_err_Local_req_X_E or
L_err_IDLE_req_X_S or L_err_North_req_X_S or L_err_East_req_X_L or L_err_West_req_X_N or L_err_South_req_X_E or
L_err_Local_req_X_W or
L_err_IDLE_req_X_L or L_err_North_req_X_L or L_err_East_req_X_N or L_err_West_req_X_E or L_err_South_req_X_W or
L_err_Local_req_X_S or
L_arbiter_out_err_state_in_onehot or
L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or
L_err_request_IDLE_not_Grants or L_err_state_North_Invalid_Grant or L_err_state_East_Invalid_Grant or
L_err_state_West_Invalid_Grant or L_err_state_South_Invalid_Grant or L_err_state_Local_Invalid_Grant or
L_err_Grants_onehot_or_all_zero;
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- Turn fault checkers
-- FIFO
N2E_turn_fault <= N_FIFO_checkers_ORed or
-- LBDR
N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_E1 or
N_err_dst_addr_cur_addr_not_E1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
N_err_header_not_empty_Req_E_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
N_err_Requests_state_in_state_not_equal or N_err_East_Req_E or N_err_East_grant_E or N_err_IDLE_Req_E or N_err_IDLE_grant_E or
N_err_North_Req_E or N_err_North_grant_E or N_err_Local_Req_E or N_err_Local_grant_E or N_err_South_Req_E or N_err_South_grant_E or
N_err_West_Req_E or N_err_West_grant_E or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or
N_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_IDLE_req_X_N or E_err_North_req_X_N or
E_err_North_credit_not_zero_req_X_N_grant_N or E_err_North_credit_zero_or_not_req_X_N_not_grant_N or E_err_Local_req_X_N or
E_err_South_req_X_N or E_err_West_req_X_N or E_err_East_req_X_N or E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or
W_err_South_req_X_N or W_err_West_req_X_N or W_err_East_req_X_N or err_grant_E_N_sig_not_empty_N_grant_E_N or
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- FIFO
N2W_turn_fault <= N_FIFO_checkers_ORed or
-- LBDR
N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_W1 or
N_err_dst_addr_cur_addr_not_W1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
N_err_header_not_empty_Req_W_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
N_err_Requests_state_in_state_not_equal or
N_err_West_Req_W or
N_err_West_grant_W or
N_err_East_Req_W or
N_err_East_grant_W or
N_err_IDLE_Req_W or
N_err_IDLE_grant_W or
N_err_North_Req_W or
N_err_North_grant_W or
N_err_Local_Req_W or
N_err_Local_grant_W or
N_err_South_Req_W or
N_err_South_grant_W or
N_err_state_in_onehot or
N_err_no_request_grants or
N_err_request_no_grants or
N_err_no_Req_W_grant_W or
W_arbiter_out_err_Requests_state_in_state_not_equal or
W_err_IDLE_req_X_N or
W_err_North_req_X_N or
W_err_North_credit_not_zero_req_X_N_grant_N or
W_err_North_credit_zero_or_not_req_X_N_not_grant_N or
W_err_Local_req_X_N or
W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or
W_err_request_IDLE_state or
W_err_request_IDLE_not_Grants or
W_err_Grants_onehot_or_all_zero or
err_grant_W_N_sig_not_empty_N_grant_W_N or
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or
err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or
err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
E2N_turn_fault <= E_FIFO_checkers_ORed or -- FIFO
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_N1 or
E_err_dst_addr_cur_addr_not_N1 or
E_err_header_not_empty_faulty_drop_packet_in or
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
E_err_header_not_empty_faulty_Req_in_all_zero or
E_err_header_not_empty_Req_N_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or
E_err_North_grant_N or E_err_Local_Req_N or E_err_Local_grant_N or E_err_South_Req_N or E_err_South_grant_N or
E_err_West_Req_N or E_err_West_grant_N or E_err_East_Req_N or E_err_East_grant_N or E_err_state_in_onehot or
E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_N_grant_N or
N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_East_req_X_E or
N_err_East_credit_not_zero_req_X_E_grant_E or N_err_East_credit_zero_or_not_req_X_E_not_grant_E or
N_err_IDLE_req_X_E or N_err_North_req_X_E or N_err_Local_req_X_E or N_err_South_req_X_E or N_err_West_req_X_E or
N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or
N_err_Grants_onehot_or_all_zero or err_grant_N_E_sig_not_empty_E_grant_N_E or
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or err_grant_signals_not_empty_grant_N or
err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or
err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal;
E2S_turn_fault <= E_FIFO_checkers_ORed or -- FIFO
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_S1 or
E_err_dst_addr_cur_addr_not_S1 or
E_err_header_not_empty_faulty_drop_packet_in or
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
E_err_header_not_empty_faulty_Req_in_all_zero or
E_err_header_not_empty_Req_S_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or E_err_South_Req_S or E_err_South_grant_S or E_err_West_Req_S or E_err_West_grant_S or
E_err_East_Req_S or E_err_East_grant_S or E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or
E_err_Local_Req_S or E_err_Local_grant_S or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or
E_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_East_req_X_E or
S_err_East_credit_not_zero_req_X_E_grant_E or S_err_East_credit_zero_or_not_req_X_E_not_grant_E or S_err_IDLE_req_X_E or
S_err_North_req_X_E or S_err_Local_req_X_E or S_err_South_req_X_E or S_err_West_req_X_E or S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or
err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
W2N_turn_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
W_err_grants_onehot or
W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_N1 or
W_err_dst_addr_cur_addr_not_N1 or
W_err_header_not_empty_faulty_drop_packet_in or
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
W_err_header_not_empty_faulty_Req_in_all_zero or
W_err_header_not_empty_Req_N_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or
W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or
W_err_Local_Req_N or W_err_Local_grant_N or W_err_South_Req_N or W_err_South_grant_N or W_err_West_Req_N or W_err_West_grant_N or
W_err_East_Req_N or W_err_East_grant_N or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or
W_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_West_req_X_W or
N_err_West_credit_not_zero_req_X_W_grant_W or N_err_West_credit_zero_or_not_req_X_W_not_grant_W or N_err_East_req_X_W or
N_err_IDLE_req_X_W or N_err_North_req_X_W or N_err_Local_req_X_W or N_err_South_req_X_W or N_arbiter_out_err_state_in_onehot or
N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or
err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or err_grant_signals_not_empty_grant_N or
err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal;
-- FIFO
W2S_turn_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_S1 or W_err_dst_addr_cur_addr_not_S1 or
W_err_header_not_empty_faulty_drop_packet_in or W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
W_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_S_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or W_err_South_Req_S or W_err_South_grant_S or W_err_West_Req_S or W_err_West_grant_S or
W_err_East_Req_S or W_err_East_grant_S or W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or
W_err_Local_Req_S or W_err_Local_grant_S or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or
W_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_West_req_X_W or
S_err_West_credit_not_zero_req_X_W_grant_W or S_err_West_credit_zero_or_not_req_X_W_not_grant_W or S_err_East_req_X_W or
S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_Local_req_X_W or S_err_South_req_X_W or S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or
err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
S2E_turn_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_E1 or S_err_dst_addr_cur_addr_not_E1 or
S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
S_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_E_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or S_err_East_Req_E or S_err_East_grant_E or S_err_IDLE_Req_E or S_err_IDLE_grant_E or
S_err_North_Req_E or S_err_North_grant_E or S_err_Local_Req_E or S_err_Local_grant_E or S_err_South_Req_E or S_err_South_grant_E or
S_err_West_Req_E or S_err_West_grant_E or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or
S_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_South_req_X_S or
E_err_South_credit_not_zero_req_X_S_grant_S or E_err_South_credit_zero_or_not_req_X_S_not_grant_S or E_err_West_req_X_S or
E_err_East_req_X_S or E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_Local_req_X_S or E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or
err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or err_grant_signals_not_empty_grant_E or
err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or
err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- FIFO
S2W_turn_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_W1 or
S_err_dst_addr_cur_addr_not_W1 or
S_err_header_not_empty_faulty_drop_packet_in or
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
S_err_header_not_empty_faulty_Req_in_all_zero or
S_err_header_not_empty_Req_W_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or S_err_West_Req_W or S_err_West_grant_W or S_err_East_Req_W or S_err_East_grant_W or
S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or S_err_Local_Req_W or S_err_Local_grant_W or
S_err_South_Req_W or S_err_South_grant_W or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or
S_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_South_req_X_S or
W_err_South_credit_not_zero_req_X_S_grant_S or W_err_South_credit_zero_or_not_req_X_S_not_grant_S or W_err_West_req_X_S or
W_err_East_req_X_S or W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_Local_req_X_S or W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or
err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
-- Path fault checkers
-- FIFO
N2S_path_fault <= N_FIFO_checkers_ORed or
-- LBDR
N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_S1 or
N_err_dst_addr_cur_addr_not_S1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
N_err_header_not_empty_Req_S_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
N_err_Requests_state_in_state_not_equal or N_err_South_Req_S or N_err_South_grant_S or N_err_West_Req_S or N_err_West_grant_S or
N_err_East_Req_S or N_err_East_grant_S or N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or
N_err_Local_Req_S or N_err_Local_grant_S or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or
N_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_IDLE_req_X_N or S_err_North_req_X_N or
S_err_North_credit_not_zero_req_X_N_grant_N or S_err_North_credit_zero_or_not_req_X_N_not_grant_N or S_err_Local_req_X_N or
S_err_South_req_X_N or S_err_West_req_X_N or S_err_East_req_X_N or S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or
err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
S2N_path_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_N1 or S_err_dst_addr_cur_addr_not_N1 or
S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
S_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_N_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or
S_err_Local_Req_N or S_err_Local_grant_N or S_err_South_Req_N or S_err_South_grant_N or S_err_West_Req_N or S_err_West_grant_N or
S_err_East_Req_N or S_err_East_grant_N or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or
S_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_South_req_X_S or
N_err_South_credit_not_zero_req_X_S_grant_S or N_err_South_credit_zero_or_not_req_X_S_not_grant_S or
N_err_West_req_X_S or N_err_East_req_X_S or N_err_IDLE_req_X_S or N_err_North_req_X_S or N_err_Local_req_X_S or
N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or
N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_S_sig_not_empty_S_grant_N_S or
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or
err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or
err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal;
-- FIFO
E2W_path_fault <= E_FIFO_checkers_ORed or
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_W1 or E_err_dst_addr_cur_addr_not_W1 or
E_err_header_not_empty_faulty_drop_packet_in or E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
E_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_W_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or E_err_West_Req_W or E_err_West_grant_W or E_err_East_Req_W or E_err_East_grant_W or
E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or E_err_Local_Req_W or E_err_Local_grant_W or
E_err_South_Req_W or E_err_South_grant_W or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or
E_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_East_req_X_E or
W_err_East_credit_not_zero_req_X_E_grant_E or W_err_East_credit_zero_or_not_req_X_E_not_grant_E or W_err_IDLE_req_X_E or
W_err_North_req_X_E or W_err_Local_req_X_E or W_err_South_req_X_E or W_err_West_req_X_E or W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or
err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
-- FIFO
W2E_path_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_E1 or W_err_dst_addr_cur_addr_not_E1 or
W_err_header_not_empty_faulty_drop_packet_in or W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
W_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_E_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or W_err_East_Req_E or W_err_East_grant_E or W_err_IDLE_Req_E or
W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or W_err_Local_Req_E or W_err_Local_grant_E or
W_err_South_Req_E or W_err_South_grant_E or W_err_West_Req_E or W_err_West_grant_E or W_err_state_in_onehot or
W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or
W_err_West_req_X_W or E_err_West_credit_not_zero_req_X_W_grant_W or E_err_West_credit_zero_or_not_req_X_W_not_grant_W or
E_err_East_req_X_W or E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_Local_req_X_W or E_err_South_req_X_W or
E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or
E_err_Grants_onehot_or_all_zero or err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or
err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- Checkers for Paths/turns from/to Local port
-- FIFO
L2N_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_N1 or L_err_dst_addr_cur_addr_not_N1 or
L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_N_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or
L_err_Local_Req_N or L_err_Local_grant_N or L_err_South_Req_N or L_err_South_grant_N or L_err_West_Req_N or L_err_West_grant_N or
L_err_East_Req_N or L_err_East_grant_N or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_Local_req_X_L or
N_err_Local_credit_not_zero_req_X_L_grant_L or N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or N_err_South_req_X_L or
N_err_West_req_X_L or N_err_East_req_X_L or N_err_IDLE_req_X_L or N_err_North_req_X_L or N_arbiter_out_err_state_in_onehot or
N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or
err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or err_grant_signals_not_empty_grant_N or
err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal;
-- FIFO
L2E_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_E1 or L_err_dst_addr_cur_addr_not_E1 or
L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_E_in or L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or L_err_East_Req_E or L_err_East_grant_E or L_err_IDLE_Req_E or L_err_IDLE_grant_E or
L_err_North_Req_E or L_err_North_grant_E or L_err_Local_Req_E or L_err_Local_grant_E or L_err_South_Req_E or L_err_South_grant_E or
L_err_West_Req_E or L_err_West_grant_E or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_Local_req_X_L or
E_err_Local_credit_not_zero_req_X_L_grant_L or E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or E_err_South_req_X_L or
E_err_West_req_X_L or E_err_East_req_X_L or E_err_IDLE_req_X_L or E_err_North_req_X_L or E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or
err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or err_grant_signals_not_empty_grant_E or
err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- FIFO
L2W_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_W1 or L_err_dst_addr_cur_addr_not_W1 or
L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_W_in or L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or L_err_West_Req_W or L_err_West_grant_W or L_err_East_Req_W or L_err_East_grant_W or
L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or L_err_Local_Req_W or L_err_Local_grant_W or
L_err_South_Req_W or L_err_South_grant_W or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_Local_req_X_L or
W_err_Local_credit_not_zero_req_X_L_grant_L or W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or W_err_South_req_X_L or
W_err_West_req_X_L or W_err_East_req_X_L or W_err_IDLE_req_X_L or W_err_North_req_X_L or W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or
err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
-- FIFO
L2S_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or
L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_S_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or L_err_South_Req_S or L_err_South_grant_S or L_err_West_Req_S or L_err_West_grant_S or
L_err_East_Req_S or L_err_East_grant_S or L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or
L_err_Local_Req_S or L_err_Local_grant_S or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_Local_req_X_L or
S_err_Local_credit_not_zero_req_X_L_grant_L or S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or S_err_South_req_X_L or
S_err_West_req_X_L or S_err_East_req_X_L or S_err_IDLE_req_X_L or S_err_North_req_X_L or S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or
err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
N2L_fault <= N_FIFO_checkers_ORed or
-- LBDR
N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_Req_L_in or
N_err_dst_addr_cur_addr_not_Req_L_in or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
--N_err_header_not_empty_Req_L_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
N_err_Requests_state_in_state_not_equal or N_err_Local_Req_L or N_err_Local_grant_L or N_err_South_Req_L or N_err_South_grant_L or
N_err_West_Req_L or N_err_West_grant_L or N_err_East_Req_L or N_err_East_grant_L or N_err_IDLE_Req_L or N_err_IDLE_grant_L or
N_err_North_Req_L or N_err_North_grant_L or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or
N_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_IDLE_req_X_N or L_err_North_req_X_N or
L_err_North_credit_not_zero_req_X_N_grant_N or L_err_North_credit_zero_or_not_req_X_N_not_grant_N or L_err_Local_req_X_N or
L_err_South_req_X_N or L_err_West_req_X_N or L_err_East_req_X_N or L_arbiter_out_err_state_in_onehot or
L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or
L_err_request_IDLE_not_Grants or
L_err_Grants_onehot_or_all_zero or
err_grant_L_N_sig_not_empty_N_grant_L_N or
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or
err_grant_signals_not_empty_grant_L or
err_not_grant_signals_empty_not_grant_L or
err_grants_valid_not_match or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
-- FIFO
E2L_fault <= E_FIFO_checkers_ORed or
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_Req_L_in or
E_err_dst_addr_cur_addr_not_Req_L_in or
E_err_header_not_empty_faulty_drop_packet_in or
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
E_err_header_not_empty_faulty_Req_in_all_zero or
--E_err_header_not_empty_Req_L_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or E_err_Local_Req_L or E_err_Local_grant_L or E_err_South_Req_L or E_err_South_grant_L or
E_err_West_Req_L or E_err_West_grant_L or E_err_East_Req_L or E_err_East_grant_L or E_err_IDLE_Req_L or E_err_IDLE_grant_L or
E_err_North_Req_L or E_err_North_grant_L or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or
E_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_East_req_X_E or
L_err_East_credit_not_zero_req_X_E_grant_E or L_err_East_credit_zero_or_not_req_X_E_not_grant_E or L_err_IDLE_req_X_E or
L_err_North_req_X_E or L_err_Local_req_X_E or L_err_South_req_X_E or L_err_West_req_X_E or L_arbiter_out_err_state_in_onehot or
L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or
err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or err_grant_signals_not_empty_grant_L or
err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
-- FIFO
W2L_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
W_err_grants_onehot or
W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_Req_L_in or
W_err_dst_addr_cur_addr_not_Req_L_in or
W_err_header_not_empty_faulty_drop_packet_in or
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
W_err_header_not_empty_faulty_Req_in_all_zero or
--W_err_header_not_empty_Req_L_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or
W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or W_err_Local_Req_L or W_err_Local_grant_L or W_err_South_Req_L or
W_err_South_grant_L or W_err_West_Req_L or W_err_West_grant_L or W_err_East_Req_L or W_err_East_grant_L or
W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or W_err_state_in_onehot or
W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_L_grant_L or
L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_West_req_X_W or L_err_West_credit_not_zero_req_X_W_grant_W or
L_err_West_credit_zero_or_not_req_X_W_not_grant_W or L_err_East_req_X_W or L_err_IDLE_req_X_W or L_err_North_req_X_W or
L_err_Local_req_X_W or L_err_South_req_X_W or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or
err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
-- FIFO
S2L_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_Req_L_in or
S_err_dst_addr_cur_addr_not_Req_L_in or
S_err_header_not_empty_faulty_drop_packet_in or
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
S_err_header_not_empty_faulty_Req_in_all_zero or
--S_err_header_not_empty_Req_L_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or S_err_Local_Req_L or S_err_Local_grant_L or S_err_South_Req_L or
S_err_South_grant_L or S_err_West_Req_L or S_err_West_grant_L or S_err_East_Req_L or S_err_East_grant_L or
S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or S_err_state_in_onehot or
S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_L_grant_L or
L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_South_req_X_S or L_err_South_credit_not_zero_req_X_S_grant_S or
L_err_South_credit_zero_or_not_req_X_S_not_grant_S or L_err_West_req_X_S or L_err_East_req_X_S or L_err_IDLE_req_X_S or
L_err_North_req_X_S or L_err_Local_req_X_S or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or
err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or err_grant_signals_not_empty_grant_L or
err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- Link faults and turn faults
-- The order of the turns/paths from left to right (MSB to LSB) -> 20 bits
-- N2E, N2W, E2N, E2S,
-- W2N, W2S, S2E, S2W,
-- N2S, S2N, E2W, W2E,
-- L2N, L2E, L2W, L2S,
-- N2L, E2L, W2L, S2L
------------------------------------------------------------------------------------------------------------------------------
-- Taking classified fault information to output
------------------------------------------------------------------------------------------------------------------------------
turn_faults <= faulty_N2E_turn_fault & faulty_N2W_turn_fault & faulty_E2N_turn_fault & faulty_E2S_turn_fault &
faulty_W2N_turn_fault & faulty_W2S_turn_fault & faulty_S2E_turn_fault & faulty_S2W_turn_fault &
faulty_N2S_path_fault & faulty_S2N_path_fault & faulty_E2W_path_fault & faulty_W2E_path_fault &
faulty_L2N_fault & faulty_L2E_fault & faulty_L2W_fault & faulty_L2S_fault &
faulty_N2L_fault & faulty_E2L_fault & faulty_W2L_fault & faulty_S2L_fault; -- 20 bits because of turn/path faults
link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L;
------------------------------------------------------------------------------------------------------------------------------
-- Taking non-classified fault information to output
------------------------------------------------------------------------------------------------------------------------------
--turn_faults_async <= N2E_turn_fault & N2W_turn_fault & E2N_turn_fault & E2S_turn_fault &
-- W2N_turn_fault & W2S_turn_fault & S2E_turn_fault & S2W_turn_fault &
-- N2S_path_fault & S2N_path_fault & E2W_path_fault & W2E_path_fault &
-- L2N_fault & L2E_fault & L2W_fault & L2S_fault &
-- N2L_fault & E2L_fault & W2L_fault & S2L_fault; -- 20 bits because of turn/path faults
--link_faults_async <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L;
------------------------------------------------------------------------------------------------------------------------------
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Checker Counter Threshold modules
-- Turn faults
CHK_CT_N2E_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => N2E_turn_fault, Healthy_packet => not_N2E_turn_fault,
Intermittent => intermittent_N2E_turn_fault, Faulty => faulty_N2E_turn_fault);
CHK_CT_N2W_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => N2W_turn_fault, Healthy_packet => not_N2W_turn_fault,
Intermittent => intermittent_N2W_turn_fault, Faulty => faulty_N2W_turn_fault);
CHK_CT_E2N_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => E2N_turn_fault, Healthy_packet => not_E2N_turn_fault,
Intermittent => intermittent_E2N_turn_fault, Faulty => faulty_E2N_turn_fault);
CHK_CT_E2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => E2S_turn_fault, Healthy_packet => not_E2S_turn_fault,
Intermittent => intermittent_E2S_turn_fault, Faulty => faulty_E2S_turn_fault);
CHK_CT_W2N_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => W2N_turn_fault, Healthy_packet => not_W2N_turn_fault,
Intermittent => intermittent_W2N_turn_fault, Faulty => faulty_W2N_turn_fault);
CHK_CT_W2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => W2S_turn_fault, Healthy_packet => not_W2S_turn_fault,
Intermittent => intermittent_W2S_turn_fault, Faulty => faulty_W2S_turn_fault);
CHK_CT_S2E_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => S2E_turn_fault, Healthy_packet => not_S2E_turn_fault,
Intermittent => intermittent_S2E_turn_fault, Faulty => faulty_S2E_turn_fault);
CHK_CT_S2W_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => S2W_turn_fault, Healthy_packet => not_S2W_turn_fault,
Intermittent => intermittent_S2W_turn_fault, Faulty => faulty_S2W_turn_fault);
--Path faults
CHK_CT_N2S_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => N2S_path_fault, Healthy_packet => not_N2S_path_fault,
Intermittent => intermittent_N2S_path_fault, Faulty => faulty_N2S_path_fault);
CHK_CT_S2N_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => S2N_path_fault, Healthy_packet => not_S2N_path_fault,
Intermittent => intermittent_S2N_path_fault, Faulty => faulty_S2N_path_fault);
CHK_CT_E2W_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => E2W_path_fault, Healthy_packet => not_E2W_path_fault,
Intermittent => intermittent_E2W_path_fault, Faulty => faulty_E2W_path_fault);
CHK_CT_W2E_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => W2E_path_fault, Healthy_packet => not_W2E_path_fault,
Intermittent => intermittent_W2E_path_fault, Faulty => faulty_W2E_path_fault);
-- Local port related faults (to/from local port)
CHK_CT_L2N_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => L2N_fault, Healthy_packet => not_L2N_fault,
Intermittent => intermittent_L2N_fault, Faulty => faulty_L2N_fault);
CHK_CT_L2E_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => L2E_fault, Healthy_packet => not_L2E_fault,
Intermittent => intermittent_L2E_fault, Faulty => faulty_L2E_fault);
CHK_CT_L2W_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => L2W_fault, Healthy_packet => not_L2W_fault,
Intermittent => intermittent_L2W_fault, Faulty => faulty_L2W_fault);
CHK_CT_L2S_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => L2S_fault, Healthy_packet => not_L2S_fault,
Intermittent => intermittent_L2S_fault, Faulty => faulty_L2S_fault);
CHK_CT_N2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => N2L_fault, Healthy_packet => not_N2L_fault,
Intermittent => intermittent_N2L_fault, Faulty => faulty_N2L_fault);
CHK_CT_E2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => E2L_fault, Healthy_packet => not_E2L_fault,
Intermittent => intermittent_E2L_fault, Faulty => faulty_E2L_fault);
CHK_CT_W2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => W2L_fault, Healthy_packet => not_W2L_fault,
Intermittent => intermittent_W2L_fault, Faulty => faulty_W2L_fault);
CHK_CT_S2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => S2L_fault, Healthy_packet => not_S2L_fault,
Intermittent => intermittent_S2L_fault, Faulty => faulty_S2L_fault);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- All the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_FIFO_to_N_FIFO, SO=> fault_DO_serial_N_FIFO_to_E_FIFO,
-- Checker outputs
-- Functional checkers
err_empty_full => N_err_empty_full, err_empty_read_en => N_err_empty_read_en, err_full_write_en => N_err_full_write_en,
err_state_in_onehot => N_err_state_in_onehot, err_read_pointer_in_onehot => N_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => N_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => N_err_write_en_write_pointer,
err_not_write_en_write_pointer => N_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full,
err_read_pointer_increment => N_err_read_pointer_increment,
err_read_pointer_not_increment => N_err_read_pointer_not_increment,
err_write_en => N_err_write_en,
err_not_write_en => N_err_not_write_en,
err_not_write_en1 => N_err_not_write_en1,
err_not_write_en2 => N_err_not_write_en2,
err_read_en_mismatch => N_err_read_en_mismatch,
err_read_en_mismatch1 => N_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => N_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => N_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => N_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => N_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => N_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => N_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => N_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => N_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => N_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => N_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => N_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => N_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => N_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => N_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => N_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => N_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => N_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => N_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => N_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => N_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_FIFO_to_E_FIFO, SO=> fault_DO_serial_E_FIFO_to_W_FIFO,
-- Checker outputs
-- Functional checkers
err_empty_full => E_err_empty_full, err_empty_read_en => E_err_empty_read_en, err_full_write_en => E_err_full_write_en,
err_state_in_onehot => E_err_state_in_onehot, err_read_pointer_in_onehot => E_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => E_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => E_err_write_en_write_pointer,
err_not_write_en_write_pointer => E_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full,
err_read_pointer_increment => E_err_read_pointer_increment,
err_read_pointer_not_increment => E_err_read_pointer_not_increment,
err_write_en => E_err_write_en,
err_not_write_en => E_err_not_write_en,
err_not_write_en1 => E_err_not_write_en1,
err_not_write_en2 => E_err_not_write_en2,
err_read_en_mismatch => E_err_read_en_mismatch,
err_read_en_mismatch1 => E_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => E_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => E_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => E_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => E_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => E_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => E_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => E_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => E_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => E_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => E_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => E_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => E_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => E_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => E_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => E_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => E_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => E_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => E_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => E_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => E_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_FIFO_to_W_FIFO, SO=> fault_DO_serial_W_FIFO_to_S_FIFO,
-- Checker outputs
-- Functional checkers
err_empty_full => W_err_empty_full, err_empty_read_en => W_err_empty_read_en, err_full_write_en => W_err_full_write_en,
err_state_in_onehot => W_err_state_in_onehot, err_read_pointer_in_onehot => W_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => W_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => W_err_write_en_write_pointer,
err_not_write_en_write_pointer => W_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full,
err_read_pointer_increment => W_err_read_pointer_increment,
err_read_pointer_not_increment => W_err_read_pointer_not_increment,
err_write_en => W_err_write_en,
err_not_write_en => W_err_not_write_en,
err_not_write_en1 => W_err_not_write_en1,
err_not_write_en2 => W_err_not_write_en2,
err_read_en_mismatch => W_err_read_en_mismatch,
err_read_en_mismatch1 => W_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => W_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => W_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => W_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => W_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => W_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => W_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => W_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => W_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => W_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => W_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => W_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => W_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => W_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => W_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => W_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => W_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => W_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => W_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => W_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => W_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_FIFO_to_S_FIFO, SO=> fault_DO_serial_S_FIFO_to_L_LBDR,
-- Checker outputs
-- Functional checkers
err_empty_full => S_err_empty_full,
err_empty_read_en => S_err_empty_read_en,
err_full_write_en => S_err_full_write_en,
err_state_in_onehot => S_err_state_in_onehot,
err_read_pointer_in_onehot => S_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => S_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => S_err_write_en_write_pointer,
err_not_write_en_write_pointer => S_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full,
err_read_pointer_increment => S_err_read_pointer_increment,
err_read_pointer_not_increment => S_err_read_pointer_not_increment,
err_write_en => S_err_write_en,
err_not_write_en => S_err_not_write_en,
err_not_write_en1 => S_err_not_write_en1,
err_not_write_en2 => S_err_not_write_en2,
err_read_en_mismatch => S_err_read_en_mismatch,
err_read_en_mismatch1 => S_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => S_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => S_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => S_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => S_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => S_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => S_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => S_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => S_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => S_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => S_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => S_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => S_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => S_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => S_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => S_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => S_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => S_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => S_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => S_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => S_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> SI, SO=> fault_DO_serial_L_FIFO_to_N_FIFO,
-- Checker outputs
-- Functional checkers
err_empty_full => L_err_empty_full, err_empty_read_en => L_err_empty_read_en, err_full_write_en => L_err_full_write_en,
err_state_in_onehot => L_err_state_in_onehot, err_read_pointer_in_onehot => L_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => L_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => L_err_write_en_write_pointer,
err_not_write_en_write_pointer => L_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full,
err_read_pointer_increment => L_err_read_pointer_increment,
err_read_pointer_not_increment => L_err_read_pointer_not_increment,
err_write_en => L_err_write_en,
err_not_write_en => L_err_not_write_en,
err_not_write_en1 => L_err_not_write_en1,
err_not_write_en2 => L_err_not_write_en2,
err_read_en_mismatch => L_err_read_en_mismatch,
err_read_en_mismatch1 => L_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => L_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => L_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => L_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => L_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => L_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => L_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => L_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => L_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => L_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => L_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => L_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => L_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => L_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => L_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => L_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => L_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => L_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => L_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => L_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => L_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
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parity_LBDR_N: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_N, empty_N, LBDR_Fault_N);
parity_LBDR_E: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_E, empty_E, LBDR_Fault_E);
parity_LBDR_W: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_W, empty_W, LBDR_Fault_W);
parity_LBDR_S: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_S, empty_S, LBDR_Fault_S);
parity_LBDR_L: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_L, empty_L, LBDR_Fault_L);
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--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_N, packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_LBDR_to_N_LBDR, SO=> fault_DO_serial_N_LBDR_to_E_LBDR,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => N_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => N_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => N_err_grants_onehot,
err_grants_mismatch => N_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => N_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => N_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => N_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => N_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_E, packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_LBDR_to_E_LBDR, SO=> fault_DO_serial_E_LBDR_to_W_LBDR,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => E_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => E_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => E_err_grants_onehot,
err_grants_mismatch => E_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => E_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => E_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => E_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => E_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_W, packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_LBDR_to_W_LBDR, SO=> fault_DO_serial_W_LBDR_to_S_LBDR,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => W_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => W_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => W_err_grants_onehot,
err_grants_mismatch => W_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => W_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => W_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => W_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => W_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_S, packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_LBDR_to_S_LBDR, SO=> fault_DO_serial_S_LBDR_to_Allocator,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => S_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => S_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => S_err_grants_onehot,
err_grants_mismatch => S_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => S_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => S_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => S_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => S_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_L, packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_FIFO_to_L_LBDR, SO=> fault_DO_serial_L_LBDR_to_N_LBDR,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => L_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => L_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => L_err_grants_onehot,
err_grants_mismatch => L_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => L_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => L_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => L_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => L_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
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-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL,
--TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_LBDR_to_Allocator, SO=> SO,
-- Checker outputs
-- Allocator logic checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N ,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N ,
err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E ,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E ,
err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W ,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W ,
err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S ,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S ,
err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L ,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L ,
err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N ,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N ,
err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E ,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E ,
err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W ,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W ,
err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S ,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S ,
err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L ,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L ,
err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N ,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N ,
err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E ,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E ,
err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W ,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W ,
err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S ,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S ,
err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L ,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L ,
err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N ,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N ,
err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E ,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E ,
err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W ,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W ,
err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S ,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S ,
err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L ,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L ,
err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N ,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N ,
err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E ,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E ,
err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W ,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W ,
err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S ,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S ,
err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L ,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L ,
err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N ,
err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N ,
err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E ,
err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E ,
err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W ,
err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W ,
err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S ,
err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S ,
err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L ,
err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L ,
err_grants_valid_not_match => err_grants_valid_not_match ,
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal ,
err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment ,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change ,
err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement ,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change ,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal ,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal ,
err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment ,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change ,
err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement ,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change ,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal ,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal ,
err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment ,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change ,
err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement ,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change ,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal ,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal ,
err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment ,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change ,
err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement ,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change ,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal ,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal ,
err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment ,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change ,
err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement ,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change ,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal ,
-- North Arbiter_in Checker outputs
N_err_Requests_state_in_state_not_equal => N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N => N_err_IDLE_Req_N, N_err_IDLE_grant_N => N_err_IDLE_grant_N, N_err_North_Req_N => N_err_North_Req_N,
N_err_North_grant_N => N_err_North_grant_N, N_err_East_Req_E => N_err_East_Req_E, N_err_East_grant_E => N_err_East_grant_E,
N_err_West_Req_W => N_err_West_Req_W, N_err_West_grant_W => N_err_West_grant_W, N_err_South_Req_S => N_err_South_Req_S,
N_err_South_grant_S => N_err_South_grant_S, N_err_Local_Req_L => N_err_Local_Req_L, N_err_Local_grant_L => N_err_Local_grant_L,
N_err_IDLE_Req_E => N_err_IDLE_Req_E, N_err_IDLE_grant_E => N_err_IDLE_grant_E, N_err_North_Req_E => N_err_North_Req_E,
N_err_North_grant_E => N_err_North_grant_E, N_err_East_Req_W => N_err_East_Req_W, N_err_East_grant_W => N_err_East_grant_W,
N_err_West_Req_S => N_err_West_Req_S, N_err_West_grant_S => N_err_West_grant_S, N_err_South_Req_L => N_err_South_Req_L,
N_err_South_grant_L => N_err_South_grant_L, N_err_Local_Req_N => N_err_Local_Req_N, N_err_Local_grant_N => N_err_Local_grant_N,
N_err_IDLE_Req_W => N_err_IDLE_Req_W, N_err_IDLE_grant_W => N_err_IDLE_grant_W, N_err_North_Req_W => N_err_North_Req_W,
N_err_North_grant_W => N_err_North_grant_W, N_err_East_Req_S => N_err_East_Req_S, N_err_East_grant_S => N_err_East_grant_S,
N_err_West_Req_L => N_err_West_Req_L, N_err_West_grant_L => N_err_West_grant_L, N_err_South_Req_N => N_err_South_Req_N,
N_err_South_grant_N => N_err_South_grant_N, N_err_Local_Req_E => N_err_Local_Req_E, N_err_Local_grant_E => N_err_Local_grant_E,
N_err_IDLE_Req_S => N_err_IDLE_Req_S, N_err_IDLE_grant_S => N_err_IDLE_grant_S, N_err_North_Req_S => N_err_North_Req_S,
N_err_North_grant_S => N_err_North_grant_S, N_err_East_Req_L => N_err_East_Req_L, N_err_East_grant_L => N_err_East_grant_L,
N_err_West_Req_N => N_err_West_Req_N, N_err_West_grant_N => N_err_West_grant_N, N_err_South_Req_E => N_err_South_Req_E,
N_err_South_grant_E => N_err_South_grant_E, N_err_Local_Req_W => N_err_Local_Req_W, N_err_Local_grant_W => N_err_Local_grant_W,
N_err_IDLE_Req_L => N_err_IDLE_Req_L, N_err_IDLE_grant_L => N_err_IDLE_grant_L, N_err_North_Req_L => N_err_North_Req_L,
N_err_North_grant_L => N_err_North_grant_L, N_err_East_Req_N => N_err_East_Req_N, N_err_East_grant_N => N_err_East_grant_N,
N_err_West_Req_E => N_err_West_Req_E, N_err_West_grant_E => N_err_West_grant_E, N_err_South_Req_W => N_err_South_Req_W,
N_err_South_grant_W => N_err_South_grant_W, N_err_Local_Req_S => N_err_Local_Req_S, N_err_Local_grant_S => N_err_Local_grant_S,
N_err_state_in_onehot => N_err_arbiter_state_in_onehot, N_err_no_request_grants => N_err_no_request_grants,
N_err_request_no_grants => N_err_request_no_grants,
N_err_no_Req_N_grant_N => N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E => N_err_no_Req_E_grant_E,
N_err_no_Req_W_grant_W => N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S => N_err_no_Req_S_grant_S,
N_err_no_Req_L_grant_L => N_err_no_Req_L_grant_L,
-- East Arbiter_in Checker outputs
E_err_Requests_state_in_state_not_equal => E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N => E_err_IDLE_Req_N, E_err_IDLE_grant_N => E_err_IDLE_grant_N, E_err_North_Req_N => E_err_North_Req_N,
E_err_North_grant_N => E_err_North_grant_N, E_err_East_Req_E => E_err_East_Req_E, E_err_East_grant_E => E_err_East_grant_E,
E_err_West_Req_W => E_err_West_Req_W, E_err_West_grant_W => E_err_West_grant_W, E_err_South_Req_S => E_err_South_Req_S,
E_err_South_grant_S => E_err_South_grant_S, E_err_Local_Req_L => E_err_Local_Req_L, E_err_Local_grant_L => E_err_Local_grant_L,
E_err_IDLE_Req_E => E_err_IDLE_Req_E, E_err_IDLE_grant_E => E_err_IDLE_grant_E, E_err_North_Req_E => E_err_North_Req_E,
E_err_North_grant_E => E_err_North_grant_E, E_err_East_Req_W => E_err_East_Req_W, E_err_East_grant_W => E_err_East_grant_W,
E_err_West_Req_S => E_err_West_Req_S, E_err_West_grant_S => E_err_West_grant_S, E_err_South_Req_L => E_err_South_Req_L,
E_err_South_grant_L => E_err_South_grant_L, E_err_Local_Req_N => E_err_Local_Req_N, E_err_Local_grant_N => E_err_Local_grant_N,
E_err_IDLE_Req_W => E_err_IDLE_Req_W, E_err_IDLE_grant_W => E_err_IDLE_grant_W, E_err_North_Req_W => E_err_North_Req_W,
E_err_North_grant_W => E_err_North_grant_W, E_err_East_Req_S => E_err_East_Req_S, E_err_East_grant_S => E_err_East_grant_S,
E_err_West_Req_L => E_err_West_Req_L, E_err_West_grant_L => E_err_West_grant_L, E_err_South_Req_N => E_err_South_Req_N,
E_err_South_grant_N => E_err_South_grant_N, E_err_Local_Req_E => E_err_Local_Req_E, E_err_Local_grant_E => E_err_Local_grant_E,
E_err_IDLE_Req_S => E_err_IDLE_Req_S, E_err_IDLE_grant_S => E_err_IDLE_grant_S, E_err_North_Req_S => E_err_North_Req_S,
E_err_North_grant_S => E_err_North_grant_S, E_err_East_Req_L => E_err_East_Req_L, E_err_East_grant_L => E_err_East_grant_L,
E_err_West_Req_N => E_err_West_Req_N, E_err_West_grant_N => E_err_West_grant_N, E_err_South_Req_E => E_err_South_Req_E,
E_err_South_grant_E => E_err_South_grant_E, E_err_Local_Req_W => E_err_Local_Req_W, E_err_Local_grant_W => E_err_Local_grant_W,
E_err_IDLE_Req_L => E_err_IDLE_Req_L, E_err_IDLE_grant_L => E_err_IDLE_grant_L, E_err_North_Req_L => E_err_North_Req_L,
E_err_North_grant_L => E_err_North_grant_L, E_err_East_Req_N => E_err_East_Req_N, E_err_East_grant_N => E_err_East_grant_N,
E_err_West_Req_E => E_err_West_Req_E, E_err_West_grant_E => E_err_West_grant_E, E_err_South_Req_W => E_err_South_Req_W,
E_err_South_grant_W => E_err_South_grant_W, E_err_Local_Req_S => E_err_Local_Req_S, E_err_Local_grant_S => E_err_Local_grant_S,
E_err_state_in_onehot => E_err_arbiter_state_in_onehot,
E_err_no_request_grants => E_err_no_request_grants,
E_err_request_no_grants => E_err_request_no_grants,
E_err_no_Req_N_grant_N => E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E => E_err_no_Req_E_grant_E,
E_err_no_Req_W_grant_W => E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S => E_err_no_Req_S_grant_S,
E_err_no_Req_L_grant_L => E_err_no_Req_L_grant_L,
-- West Arbiter_in Checker outputs
W_err_Requests_state_in_state_not_equal => W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N => W_err_IDLE_Req_N, W_err_IDLE_grant_N => W_err_IDLE_grant_N, W_err_North_Req_N => W_err_North_Req_N,
W_err_North_grant_N => W_err_North_grant_N, W_err_East_Req_E => W_err_East_Req_E, W_err_East_grant_E => W_err_East_grant_E,
W_err_West_Req_W => W_err_West_Req_W, W_err_West_grant_W => W_err_West_grant_W, W_err_South_Req_S => W_err_South_Req_S,
W_err_South_grant_S => W_err_South_grant_S, W_err_Local_Req_L => W_err_Local_Req_L, W_err_Local_grant_L => W_err_Local_grant_L,
W_err_IDLE_Req_E => W_err_IDLE_Req_E, W_err_IDLE_grant_E => W_err_IDLE_grant_E, W_err_North_Req_E => W_err_North_Req_E,
W_err_North_grant_E => W_err_North_grant_E, W_err_East_Req_W => W_err_East_Req_W, W_err_East_grant_W => W_err_East_grant_W,
W_err_West_Req_S => W_err_West_Req_S, W_err_West_grant_S => W_err_West_grant_S, W_err_South_Req_L => W_err_South_Req_L,
W_err_South_grant_L => W_err_South_grant_L, W_err_Local_Req_N => W_err_Local_Req_N, W_err_Local_grant_N => W_err_Local_grant_N,
W_err_IDLE_Req_W => W_err_IDLE_Req_W, W_err_IDLE_grant_W => W_err_IDLE_grant_W, W_err_North_Req_W => W_err_North_Req_W,
W_err_North_grant_W => W_err_North_grant_W, W_err_East_Req_S => W_err_East_Req_S, W_err_East_grant_S => W_err_East_grant_S,
W_err_West_Req_L => W_err_West_Req_L, W_err_West_grant_L => W_err_West_grant_L, W_err_South_Req_N => W_err_South_Req_N,
W_err_South_grant_N => W_err_South_grant_N, W_err_Local_Req_E => W_err_Local_Req_E, W_err_Local_grant_E => W_err_Local_grant_E,
W_err_IDLE_Req_S => W_err_IDLE_Req_S, W_err_IDLE_grant_S => W_err_IDLE_grant_S, W_err_North_Req_S => W_err_North_Req_S,
W_err_North_grant_S => W_err_North_grant_S, W_err_East_Req_L => W_err_East_Req_L, W_err_East_grant_L => W_err_East_grant_L,
W_err_West_Req_N => W_err_West_Req_N, W_err_West_grant_N => W_err_West_grant_N, W_err_South_Req_E => W_err_South_Req_E,
W_err_South_grant_E => W_err_South_grant_E, W_err_Local_Req_W => W_err_Local_Req_W, W_err_Local_grant_W => W_err_Local_grant_W,
W_err_IDLE_Req_L => W_err_IDLE_Req_L, W_err_IDLE_grant_L => W_err_IDLE_grant_L, W_err_North_Req_L => W_err_North_Req_L,
W_err_North_grant_L => W_err_North_grant_L, W_err_East_Req_N => W_err_East_Req_N, W_err_East_grant_N => W_err_East_grant_N,
W_err_West_Req_E => W_err_West_Req_E, W_err_West_grant_E => W_err_West_grant_E, W_err_South_Req_W => W_err_South_Req_W,
W_err_South_grant_W => W_err_South_grant_W, W_err_Local_Req_S => W_err_Local_Req_S, W_err_Local_grant_S => W_err_Local_grant_S,
W_err_state_in_onehot => W_err_arbiter_state_in_onehot,
W_err_no_request_grants => W_err_no_request_grants,
W_err_request_no_grants => W_err_request_no_grants,
W_err_no_Req_N_grant_N => W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E => W_err_no_Req_E_grant_E,
W_err_no_Req_W_grant_W => W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S => W_err_no_Req_S_grant_S,
W_err_no_Req_L_grant_L => W_err_no_Req_L_grant_L,
-- South Arbiter_in Checker outputs
S_err_Requests_state_in_state_not_equal => S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N => S_err_IDLE_Req_N, S_err_IDLE_grant_N => S_err_IDLE_grant_N, S_err_North_Req_N => S_err_North_Req_N,
S_err_North_grant_N => S_err_North_grant_N, S_err_East_Req_E => S_err_East_Req_E, S_err_East_grant_E => S_err_East_grant_E,
S_err_West_Req_W => S_err_West_Req_W, S_err_West_grant_W => S_err_West_grant_W, S_err_South_Req_S => S_err_South_Req_S,
S_err_South_grant_S => S_err_South_grant_S, S_err_Local_Req_L => S_err_Local_Req_L, S_err_Local_grant_L => S_err_Local_grant_L,
S_err_IDLE_Req_E => S_err_IDLE_Req_E, S_err_IDLE_grant_E => S_err_IDLE_grant_E, S_err_North_Req_E => S_err_North_Req_E,
S_err_North_grant_E => S_err_North_grant_E, S_err_East_Req_W => S_err_East_Req_W, S_err_East_grant_W => S_err_East_grant_W,
S_err_West_Req_S => S_err_West_Req_S, S_err_West_grant_S => S_err_West_grant_S, S_err_South_Req_L => S_err_South_Req_L,
S_err_South_grant_L => S_err_South_grant_L, S_err_Local_Req_N => S_err_Local_Req_N, S_err_Local_grant_N => S_err_Local_grant_N,
S_err_IDLE_Req_W => S_err_IDLE_Req_W, S_err_IDLE_grant_W => S_err_IDLE_grant_W, S_err_North_Req_W => S_err_North_Req_W,
S_err_North_grant_W => S_err_North_grant_W, S_err_East_Req_S => S_err_East_Req_S, S_err_East_grant_S => S_err_East_grant_S,
S_err_West_Req_L => S_err_West_Req_L, S_err_West_grant_L => S_err_West_grant_L, S_err_South_Req_N => S_err_South_Req_N,
S_err_South_grant_N => S_err_South_grant_N, S_err_Local_Req_E => S_err_Local_Req_E, S_err_Local_grant_E => S_err_Local_grant_E,
S_err_IDLE_Req_S => S_err_IDLE_Req_S, S_err_IDLE_grant_S => S_err_IDLE_grant_S, S_err_North_Req_S => S_err_North_Req_S,
S_err_North_grant_S => S_err_North_grant_S, S_err_East_Req_L => S_err_East_Req_L, S_err_East_grant_L => S_err_East_grant_L,
S_err_West_Req_N => S_err_West_Req_N, S_err_West_grant_N => S_err_West_grant_N, S_err_South_Req_E => S_err_South_Req_E,
S_err_South_grant_E => S_err_South_grant_E, S_err_Local_Req_W => S_err_Local_Req_W, S_err_Local_grant_W => S_err_Local_grant_W,
S_err_IDLE_Req_L => S_err_IDLE_Req_L, S_err_IDLE_grant_L => S_err_IDLE_grant_L, S_err_North_Req_L => S_err_North_Req_L,
S_err_North_grant_L => S_err_North_grant_L, S_err_East_Req_N => S_err_East_Req_N, S_err_East_grant_N => S_err_East_grant_N,
S_err_West_Req_E => S_err_West_Req_E, S_err_West_grant_E => S_err_West_grant_E, S_err_South_Req_W => S_err_South_Req_W,
S_err_South_grant_W => S_err_South_grant_W, S_err_Local_Req_S => S_err_Local_Req_S, S_err_Local_grant_S => S_err_Local_grant_S,
S_err_state_in_onehot => S_err_arbiter_state_in_onehot,
S_err_no_request_grants => S_err_no_request_grants,
S_err_request_no_grants => S_err_request_no_grants,
S_err_no_Req_N_grant_N => S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E => S_err_no_Req_E_grant_E,
S_err_no_Req_W_grant_W => S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S => S_err_no_Req_S_grant_S,
S_err_no_Req_L_grant_L => S_err_no_Req_L_grant_L,
-- Local Arbiter_in Checker outputs
L_err_Requests_state_in_state_not_equal => L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N => L_err_IDLE_Req_N, L_err_IDLE_grant_N => L_err_IDLE_grant_N, L_err_North_Req_N => L_err_North_Req_N,
L_err_North_grant_N => L_err_North_grant_N, L_err_East_Req_E => L_err_East_Req_E, L_err_East_grant_E => L_err_East_grant_E,
L_err_West_Req_W => L_err_West_Req_W, L_err_West_grant_W => L_err_West_grant_W, L_err_South_Req_S => L_err_South_Req_S,
L_err_South_grant_S => L_err_South_grant_S, L_err_Local_Req_L => L_err_Local_Req_L, L_err_Local_grant_L => L_err_Local_grant_L,
L_err_IDLE_Req_E => L_err_IDLE_Req_E, L_err_IDLE_grant_E => L_err_IDLE_grant_E, L_err_North_Req_E => L_err_North_Req_E,
L_err_North_grant_E => L_err_North_grant_E, L_err_East_Req_W => L_err_East_Req_W, L_err_East_grant_W => L_err_East_grant_W,
L_err_West_Req_S => L_err_West_Req_S, L_err_West_grant_S => L_err_West_grant_S, L_err_South_Req_L => L_err_South_Req_L,
L_err_South_grant_L => L_err_South_grant_L, L_err_Local_Req_N => L_err_Local_Req_N, L_err_Local_grant_N => L_err_Local_grant_N,
L_err_IDLE_Req_W => L_err_IDLE_Req_W, L_err_IDLE_grant_W => L_err_IDLE_grant_W, L_err_North_Req_W => L_err_North_Req_W,
L_err_North_grant_W => L_err_North_grant_W, L_err_East_Req_S => L_err_East_Req_S, L_err_East_grant_S => L_err_East_grant_S,
L_err_West_Req_L => L_err_West_Req_L, L_err_West_grant_L => L_err_West_grant_L, L_err_South_Req_N => L_err_South_Req_N,
L_err_South_grant_N => L_err_South_grant_N, L_err_Local_Req_E => L_err_Local_Req_E, L_err_Local_grant_E => L_err_Local_grant_E,
L_err_IDLE_Req_S => L_err_IDLE_Req_S, L_err_IDLE_grant_S => L_err_IDLE_grant_S, L_err_North_Req_S => L_err_North_Req_S,
L_err_North_grant_S => L_err_North_grant_S, L_err_East_Req_L => L_err_East_Req_L, L_err_East_grant_L => L_err_East_grant_L,
L_err_West_Req_N => L_err_West_Req_N, L_err_West_grant_N => L_err_West_grant_N, L_err_South_Req_E => L_err_South_Req_E,
L_err_South_grant_E => L_err_South_grant_E, L_err_Local_Req_W => L_err_Local_Req_W, L_err_Local_grant_W => L_err_Local_grant_W,
L_err_IDLE_Req_L => L_err_IDLE_Req_L, L_err_IDLE_grant_L => L_err_IDLE_grant_L, L_err_North_Req_L => L_err_North_Req_L,
L_err_North_grant_L => L_err_North_grant_L, L_err_East_Req_N => L_err_East_Req_N, L_err_East_grant_N => L_err_East_grant_N,
L_err_West_Req_E => L_err_West_Req_E, L_err_West_grant_E => L_err_West_grant_E, L_err_South_Req_W => L_err_South_Req_W,
L_err_South_grant_W => L_err_South_grant_W, L_err_Local_Req_S => L_err_Local_Req_S, L_err_Local_grant_S => L_err_Local_grant_S,
L_err_state_in_onehot => L_err_arbiter_state_in_onehot,
L_err_no_request_grants => L_err_no_request_grants,
L_err_request_no_grants => L_err_request_no_grants,
L_err_no_Req_N_grant_N => L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E => L_err_no_Req_E_grant_E,
L_err_no_Req_W_grant_W => L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S => L_err_no_Req_S_grant_S,
L_err_no_Req_L_grant_L => L_err_no_Req_L_grant_L,
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal => N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N => N_err_IDLE_req_X_N,
N_err_North_req_X_N => N_err_North_req_X_N,
N_err_North_credit_not_zero_req_X_N_grant_N => N_err_North_credit_not_zero_req_X_N_grant_N,
N_err_North_credit_zero_or_not_req_X_N_not_grant_N => N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E => N_err_East_req_X_E,
N_err_East_credit_not_zero_req_X_E_grant_E => N_err_East_credit_not_zero_req_X_E_grant_E,
N_err_East_credit_zero_or_not_req_X_E_not_grant_E => N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W => N_err_West_req_X_W,
N_err_West_credit_not_zero_req_X_W_grant_W => N_err_West_credit_not_zero_req_X_W_grant_W,
N_err_West_credit_zero_or_not_req_X_W_not_grant_W => N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S => N_err_South_req_X_S,
N_err_South_credit_not_zero_req_X_S_grant_S => N_err_South_credit_not_zero_req_X_S_grant_S,
N_err_South_credit_zero_or_not_req_X_S_not_grant_S => N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L => N_err_Local_req_X_L,
N_err_Local_credit_not_zero_req_X_L_grant_L => N_err_Local_credit_not_zero_req_X_L_grant_L,
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L => N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E => N_err_IDLE_req_X_E, N_err_North_req_X_E => N_err_North_req_X_E, N_err_East_req_X_W => N_err_East_req_X_W,
N_err_West_req_X_S => N_err_West_req_X_S, N_err_South_req_X_L => N_err_South_req_X_L, N_err_Local_req_X_N => N_err_Local_req_X_N,
N_err_IDLE_req_X_W => N_err_IDLE_req_X_W, N_err_North_req_X_W => N_err_North_req_X_W, N_err_East_req_X_S => N_err_East_req_X_S,
N_err_West_req_X_L => N_err_West_req_X_L, N_err_South_req_X_N => N_err_South_req_X_N, N_err_Local_req_X_E => N_err_Local_req_X_E,
N_err_IDLE_req_X_S => N_err_IDLE_req_X_S, N_err_North_req_X_S => N_err_North_req_X_S, N_err_East_req_X_L => N_err_East_req_X_L,
N_err_West_req_X_N => N_err_West_req_X_N, N_err_South_req_X_E => N_err_South_req_X_E, N_err_Local_req_X_W => N_err_Local_req_X_W,
N_err_IDLE_req_X_L => N_err_IDLE_req_X_L, N_err_North_req_X_L => N_err_North_req_X_L, N_err_East_req_X_N => N_err_East_req_X_N,
N_err_West_req_X_E => N_err_West_req_X_E, N_err_South_req_X_W => N_err_South_req_X_W, N_err_Local_req_X_S => N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot => N_arbiter_out_err_state_in_onehot,
N_arbiter_out_err_no_request_grants => N_arbiter_out_err_no_request_grants,
N_err_request_IDLE_state => N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants => N_err_request_IDLE_not_Grants,
N_err_state_North_Invalid_Grant => N_err_state_North_Invalid_Grant,
N_err_state_East_Invalid_Grant => N_err_state_East_Invalid_Grant,
N_err_state_West_Invalid_Grant => N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant => N_err_state_South_Invalid_Grant,
N_err_state_Local_Invalid_Grant => N_err_state_Local_Invalid_Grant,
N_err_Grants_onehot_or_all_zero => N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal => E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N => E_err_IDLE_req_X_N,
E_err_North_req_X_N => E_err_North_req_X_N,
E_err_North_credit_not_zero_req_X_N_grant_N => E_err_North_credit_not_zero_req_X_N_grant_N,
E_err_North_credit_zero_or_not_req_X_N_not_grant_N => E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E => E_err_East_req_X_E,
E_err_East_credit_not_zero_req_X_E_grant_E => E_err_East_credit_not_zero_req_X_E_grant_E,
E_err_East_credit_zero_or_not_req_X_E_not_grant_E => E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W => E_err_West_req_X_W,
E_err_West_credit_not_zero_req_X_W_grant_W => E_err_West_credit_not_zero_req_X_W_grant_W,
E_err_West_credit_zero_or_not_req_X_W_not_grant_W => E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S => E_err_South_req_X_S,
E_err_South_credit_not_zero_req_X_S_grant_S => E_err_South_credit_not_zero_req_X_S_grant_S,
E_err_South_credit_zero_or_not_req_X_S_not_grant_S => E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L => E_err_Local_req_X_L,
E_err_Local_credit_not_zero_req_X_L_grant_L => E_err_Local_credit_not_zero_req_X_L_grant_L,
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L => E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E => E_err_IDLE_req_X_E, E_err_North_req_X_E => E_err_North_req_X_E, E_err_East_req_X_W => E_err_East_req_X_W,
E_err_West_req_X_S => E_err_West_req_X_S, E_err_South_req_X_L => E_err_South_req_X_L, E_err_Local_req_X_N => E_err_Local_req_X_N,
E_err_IDLE_req_X_W => E_err_IDLE_req_X_W, E_err_North_req_X_W => E_err_North_req_X_W, E_err_East_req_X_S => E_err_East_req_X_S,
E_err_West_req_X_L => E_err_West_req_X_L, E_err_South_req_X_N => E_err_South_req_X_N, E_err_Local_req_X_E => E_err_Local_req_X_E,
E_err_IDLE_req_X_S => E_err_IDLE_req_X_S, E_err_North_req_X_S => E_err_North_req_X_S, E_err_East_req_X_L => E_err_East_req_X_L,
E_err_West_req_X_N => E_err_West_req_X_N, E_err_South_req_X_E => E_err_South_req_X_E, E_err_Local_req_X_W => E_err_Local_req_X_W,
E_err_IDLE_req_X_L => E_err_IDLE_req_X_L, E_err_North_req_X_L => E_err_North_req_X_L, E_err_East_req_X_N => E_err_East_req_X_N,
E_err_West_req_X_E => E_err_West_req_X_E, E_err_South_req_X_W => E_err_South_req_X_W, E_err_Local_req_X_S => E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot => E_arbiter_out_err_state_in_onehot,
E_arbiter_out_err_no_request_grants => E_arbiter_out_err_no_request_grants,
E_err_request_IDLE_state => E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants => E_err_request_IDLE_not_Grants,
E_err_state_North_Invalid_Grant => E_err_state_North_Invalid_Grant,
E_err_state_East_Invalid_Grant => E_err_state_East_Invalid_Grant,
E_err_state_West_Invalid_Grant => E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant => E_err_state_South_Invalid_Grant,
E_err_state_Local_Invalid_Grant => E_err_state_Local_Invalid_Grant,
E_err_Grants_onehot_or_all_zero => E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal => W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N => W_err_IDLE_req_X_N,
W_err_North_req_X_N => W_err_North_req_X_N,
W_err_North_credit_not_zero_req_X_N_grant_N => W_err_North_credit_not_zero_req_X_N_grant_N,
W_err_North_credit_zero_or_not_req_X_N_not_grant_N => W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E => W_err_East_req_X_E,
W_err_East_credit_not_zero_req_X_E_grant_E => W_err_East_credit_not_zero_req_X_E_grant_E,
W_err_East_credit_zero_or_not_req_X_E_not_grant_E => W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W => W_err_West_req_X_W,
W_err_West_credit_not_zero_req_X_W_grant_W => W_err_West_credit_not_zero_req_X_W_grant_W,
W_err_West_credit_zero_or_not_req_X_W_not_grant_W => W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S => W_err_South_req_X_S,
W_err_South_credit_not_zero_req_X_S_grant_S => W_err_South_credit_not_zero_req_X_S_grant_S,
W_err_South_credit_zero_or_not_req_X_S_not_grant_S => W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L => W_err_Local_req_X_L,
W_err_Local_credit_not_zero_req_X_L_grant_L => W_err_Local_credit_not_zero_req_X_L_grant_L,
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L => W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E => W_err_IDLE_req_X_E, W_err_North_req_X_E => W_err_North_req_X_E, W_err_East_req_X_W => W_err_East_req_X_W,
W_err_West_req_X_S => W_err_West_req_X_S, W_err_South_req_X_L => W_err_South_req_X_L, W_err_Local_req_X_N => W_err_Local_req_X_N,
W_err_IDLE_req_X_W => W_err_IDLE_req_X_W, W_err_North_req_X_W => W_err_North_req_X_W, W_err_East_req_X_S => W_err_East_req_X_S,
W_err_West_req_X_L => W_err_West_req_X_L, W_err_South_req_X_N => W_err_South_req_X_N, W_err_Local_req_X_E => W_err_Local_req_X_E,
W_err_IDLE_req_X_S => W_err_IDLE_req_X_S, W_err_North_req_X_S => W_err_North_req_X_S, W_err_East_req_X_L => W_err_East_req_X_L,
W_err_West_req_X_N => W_err_West_req_X_N, W_err_South_req_X_E => W_err_South_req_X_E, W_err_Local_req_X_W => W_err_Local_req_X_W,
W_err_IDLE_req_X_L => W_err_IDLE_req_X_L, W_err_North_req_X_L => W_err_North_req_X_L, W_err_East_req_X_N => W_err_East_req_X_N,
W_err_West_req_X_E => W_err_West_req_X_E, W_err_South_req_X_W => W_err_South_req_X_W, W_err_Local_req_X_S => W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot => W_arbiter_out_err_state_in_onehot,
W_arbiter_out_err_no_request_grants => W_arbiter_out_err_no_request_grants,
W_err_request_IDLE_state => W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants => W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant => W_err_state_North_Invalid_Grant,
W_err_state_East_Invalid_Grant => W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant => W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant => W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant => W_err_state_Local_Invalid_Grant,
W_err_Grants_onehot_or_all_zero => W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal => S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N => S_err_IDLE_req_X_N,
S_err_North_req_X_N => S_err_North_req_X_N,
S_err_North_credit_not_zero_req_X_N_grant_N => S_err_North_credit_not_zero_req_X_N_grant_N,
S_err_North_credit_zero_or_not_req_X_N_not_grant_N => S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E => S_err_East_req_X_E,
S_err_East_credit_not_zero_req_X_E_grant_E => S_err_East_credit_not_zero_req_X_E_grant_E,
S_err_East_credit_zero_or_not_req_X_E_not_grant_E => S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W => S_err_West_req_X_W,
S_err_West_credit_not_zero_req_X_W_grant_W => S_err_West_credit_not_zero_req_X_W_grant_W,
S_err_West_credit_zero_or_not_req_X_W_not_grant_W => S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S => S_err_South_req_X_S,
S_err_South_credit_not_zero_req_X_S_grant_S => S_err_South_credit_not_zero_req_X_S_grant_S,
S_err_South_credit_zero_or_not_req_X_S_not_grant_S => S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L => S_err_Local_req_X_L,
S_err_Local_credit_not_zero_req_X_L_grant_L => S_err_Local_credit_not_zero_req_X_L_grant_L,
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L => S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E => S_err_IDLE_req_X_E, S_err_North_req_X_E => S_err_North_req_X_E, S_err_East_req_X_W => S_err_East_req_X_W,
S_err_West_req_X_S => S_err_West_req_X_S, S_err_South_req_X_L => S_err_South_req_X_L, S_err_Local_req_X_N => S_err_Local_req_X_N,
S_err_IDLE_req_X_W => S_err_IDLE_req_X_W, S_err_North_req_X_W => S_err_North_req_X_W, S_err_East_req_X_S => S_err_East_req_X_S,
S_err_West_req_X_L => S_err_West_req_X_L, S_err_South_req_X_N => S_err_South_req_X_N, S_err_Local_req_X_E => S_err_Local_req_X_E,
S_err_IDLE_req_X_S => S_err_IDLE_req_X_S, S_err_North_req_X_S => S_err_North_req_X_S, S_err_East_req_X_L => S_err_East_req_X_L,
S_err_West_req_X_N => S_err_West_req_X_N, S_err_South_req_X_E => S_err_South_req_X_E, S_err_Local_req_X_W => S_err_Local_req_X_W,
S_err_IDLE_req_X_L => S_err_IDLE_req_X_L, S_err_North_req_X_L => S_err_North_req_X_L, S_err_East_req_X_N => S_err_East_req_X_N,
S_err_West_req_X_E => S_err_West_req_X_E, S_err_South_req_X_W => S_err_South_req_X_W, S_err_Local_req_X_S => S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot => S_arbiter_out_err_state_in_onehot,
S_arbiter_out_err_no_request_grants => S_arbiter_out_err_no_request_grants,
S_err_request_IDLE_state => S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants => S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant => S_err_state_North_Invalid_Grant,
S_err_state_East_Invalid_Grant => S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant => S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant => S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant => S_err_state_Local_Invalid_Grant,
S_err_Grants_onehot_or_all_zero => S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal => L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N => L_err_IDLE_req_X_N,
L_err_North_req_X_N => L_err_North_req_X_N,
L_err_North_credit_not_zero_req_X_N_grant_N => L_err_North_credit_not_zero_req_X_N_grant_N,
L_err_North_credit_zero_or_not_req_X_N_not_grant_N => L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E => L_err_East_req_X_E,
L_err_East_credit_not_zero_req_X_E_grant_E => L_err_East_credit_not_zero_req_X_E_grant_E,
L_err_East_credit_zero_or_not_req_X_E_not_grant_E => L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
L_err_West_req_X_W => L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W => L_err_West_credit_not_zero_req_X_W_grant_W,
L_err_West_credit_zero_or_not_req_X_W_not_grant_W => L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S => L_err_South_req_X_S,
L_err_South_credit_not_zero_req_X_S_grant_S => L_err_South_credit_not_zero_req_X_S_grant_S,
L_err_South_credit_zero_or_not_req_X_S_not_grant_S => L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L => L_err_Local_req_X_L,
L_err_Local_credit_not_zero_req_X_L_grant_L => L_err_Local_credit_not_zero_req_X_L_grant_L,
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L => L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E => L_err_IDLE_req_X_E, L_err_North_req_X_E => L_err_North_req_X_E, L_err_East_req_X_W => L_err_East_req_X_W,
L_err_West_req_X_S => L_err_West_req_X_S, L_err_South_req_X_L => L_err_South_req_X_L, L_err_Local_req_X_N => L_err_Local_req_X_N,
L_err_IDLE_req_X_W => L_err_IDLE_req_X_W, L_err_North_req_X_W => L_err_North_req_X_W, L_err_East_req_X_S => L_err_East_req_X_S,
L_err_West_req_X_L => L_err_West_req_X_L, L_err_South_req_X_N => L_err_South_req_X_N, L_err_Local_req_X_E => L_err_Local_req_X_E,
L_err_IDLE_req_X_S => L_err_IDLE_req_X_S, L_err_North_req_X_S => L_err_North_req_X_S, L_err_East_req_X_L => L_err_East_req_X_L,
L_err_West_req_X_N => L_err_West_req_X_N, L_err_South_req_X_E => L_err_South_req_X_E, L_err_Local_req_X_W => L_err_Local_req_X_W,
L_err_IDLE_req_X_L => L_err_IDLE_req_X_L, L_err_North_req_X_L => L_err_North_req_X_L, L_err_East_req_X_N => L_err_East_req_X_N,
L_err_West_req_X_E => L_err_West_req_X_E, L_err_South_req_X_W => L_err_South_req_X_W, L_err_Local_req_X_S => L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot => L_arbiter_out_err_state_in_onehot,
L_arbiter_out_err_no_request_grants => L_arbiter_out_err_no_request_grants,
L_err_request_IDLE_state => L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants => L_err_request_IDLE_not_Grants,
L_err_state_North_Invalid_Grant => L_err_state_North_Invalid_Grant,
L_err_state_East_Invalid_Grant => L_err_state_East_Invalid_Grant,
L_err_state_West_Invalid_Grant => L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant => L_err_state_South_Invalid_Grant,
L_err_state_Local_Invalid_Grant => L_err_state_Local_Invalid_Grant,
L_err_Grants_onehot_or_all_zero => L_err_Grants_onehot_or_all_zero
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
end; | gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/eth_dma.vhd | 12 | 6966 | ---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/NI_Test/flit_tracker.vhd | 14 | 2969 | --Copyright (C) 2016 Siavoosh Payandeh Azad
--
-- This module Monitors the links status along side with the valid data value
-- in case there is a valid flit on the link, the module produces a log entery
-- in the tracker_file location.
--
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_misc.all;
entity flit_tracker is
generic (
DATA_WIDTH: integer := 32;
tracker_file: string :="track.txt"
);
port (
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
valid_in : in std_logic
);
end;
architecture behavior of flit_tracker is
begin
process(clk)
variable source_id, destination_id, Packet_length, packet_id: integer;
variable xor_check : std_logic;
-- file handeling
file trace_file : text is out tracker_file;
variable LINEVARIABLE : line;
begin
Packet_length := 0;
destination_id := 0;
source_id := 0;
packet_id := 0;
if clk'event and clk = '1' then -- checks the link status on the rising edge of the clock!
if unsigned(RX) /= to_unsigned(0, RX'length) and valid_in = '1' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
Packet_length := to_integer(unsigned(RX(28 downto 17)));
destination_id := to_integer(unsigned(RX(16 downto 13)));
source_id := to_integer(unsigned(RX(12 downto 9)));
packet_id := to_integer(unsigned(RX(8 downto 1)));
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then -- the flit is healthy
write(LINEVARIABLE, "H flit at " & time'image(now) & " From " & integer'image(source_id) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(packet_id));
else
write(LINEVARIABLE, "H flit at " & time'image(now) & " From " & integer'image(source_id) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(packet_id) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then -- the flit is healthy
write(LINEVARIABLE, "B flit at " & time'image(now));
else
write(LINEVARIABLE, "B flit at " & time'image(now) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then -- the flit is healthy
write(LINEVARIABLE, "T flit at " & time'image(now));
else
write(LINEVARIABLE, "T flit at " & time'image(now) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
end if;
end if;
end if;
end process;
end; | gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/flit_tracker.vhd | 14 | 2969 | --Copyright (C) 2016 Siavoosh Payandeh Azad
--
-- This module Monitors the links status along side with the valid data value
-- in case there is a valid flit on the link, the module produces a log entery
-- in the tracker_file location.
--
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_misc.all;
entity flit_tracker is
generic (
DATA_WIDTH: integer := 32;
tracker_file: string :="track.txt"
);
port (
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
valid_in : in std_logic
);
end;
architecture behavior of flit_tracker is
begin
process(clk)
variable source_id, destination_id, Packet_length, packet_id: integer;
variable xor_check : std_logic;
-- file handeling
file trace_file : text is out tracker_file;
variable LINEVARIABLE : line;
begin
Packet_length := 0;
destination_id := 0;
source_id := 0;
packet_id := 0;
if clk'event and clk = '1' then -- checks the link status on the rising edge of the clock!
if unsigned(RX) /= to_unsigned(0, RX'length) and valid_in = '1' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
Packet_length := to_integer(unsigned(RX(28 downto 17)));
destination_id := to_integer(unsigned(RX(16 downto 13)));
source_id := to_integer(unsigned(RX(12 downto 9)));
packet_id := to_integer(unsigned(RX(8 downto 1)));
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then -- the flit is healthy
write(LINEVARIABLE, "H flit at " & time'image(now) & " From " & integer'image(source_id) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(packet_id));
else
write(LINEVARIABLE, "H flit at " & time'image(now) & " From " & integer'image(source_id) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(packet_id) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then -- the flit is healthy
write(LINEVARIABLE, "B flit at " & time'image(now));
else
write(LINEVARIABLE, "B flit at " & time'image(now) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
xor_check := XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
if xor_check = RX(0) then -- the flit is healthy
write(LINEVARIABLE, "T flit at " & time'image(now));
else
write(LINEVARIABLE, "T flit at " & time'image(now) & " FAULTY ");
end if;
writeline(trace_file, LINEVARIABLE);
end if;
end if;
end if;
end process;
end; | gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/Checkers/Control_Part_Checkers/LBDR_packet_drop_checkers/LBDR_routing_part/RTL/LBDR_packet_drop_routing_part_pseudo_checkers.vhd | 12 | 13914 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
--err_header_not_empty_Requests_in_onehot,
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end LBDR_packet_drop_routing_part_pseudo_checkers;
architecture behavior of LBDR_packet_drop_routing_part_pseudo_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
signal grant_signals: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
--process (flit_type, empty, Requests_in)
--begin
-- if (flit_type = "001" and empty = '0' and Requests_in /= "00001" and Requests_in /= "00010" and
-- Requests_in /= "00100" and Requests_in /= "01000" and Requests_in /= "10000") then
-- err_header_not_empty_Requests_in_onehot <= '1';
-- else
-- err_header_not_empty_Requests_in_onehot <= '0';
-- end if;
--end process;
-- Checked !
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then
err_tail_empty_Requests_FF_Requests_in <= '1';
else
err_tail_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1';
else
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or
grant_signals = "01000" or grant_signals = "10000") and grants = '0') then
err_grants_onehot <= '1';
else
err_grants_onehot <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( grant_signals = "00000" and grants = '1') then
err_grants_mismatch <= '1';
else
err_grants_mismatch <= '0';
end if;
end process;
-- Checked !
process (flit_type, Requests_FF, Requests_FF, Requests_in)
begin
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
else
err_header_tail_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
else
err_dst_addr_cur_addr_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
else
err_dst_addr_cur_addr_not_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
else
err_dst_addr_cur_addr_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
else
err_dst_addr_cur_addr_not_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
else
err_dst_addr_cur_addr_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
else
err_dst_addr_cur_addr_not_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
else
err_dst_addr_cur_addr_S1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
else
err_dst_addr_cur_addr_not_S1 <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr = cur_addr and Req_L_in = '0') then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
else
err_dst_addr_cur_addr_not_Req_L_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, cur_addr, dst_addr, Req_L_in, Req_L_FF)
begin
if ( flit_type = "001" and empty = '0' and cur_addr /= dst_addr and Req_L_in /= Req_L_FF) then
err_dst_addr_cur_addr_Req_L_in <= '1';
else
err_dst_addr_cur_addr_Req_L_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_N_in /= ( ((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0) ) ) then
err_header_not_empty_Req_N_in <= '1';
else
err_header_not_empty_Req_N_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_E_in /= ( ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1) ) ) then
err_header_not_empty_Req_E_in <= '1';
else
err_header_not_empty_Req_E_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_W_in /= ( ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2) ) ) then
err_header_not_empty_Req_W_in <= '1';
else
err_header_not_empty_Req_W_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_S_in /= (((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) ) then
err_header_not_empty_Req_S_in <= '1';
else
err_header_not_empty_Req_S_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in)
begin
if (flit_type = "001" and empty = '0' and ( ((((N1_out and not E1_out and not W1_out) or
(N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) or
(((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or
(E1_out and S1_out and Rxy(3))) and Cx(1)) or (((W1_out and not N1_out and not S1_out) or
(W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) or
(((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or
(S1_out and W1_out and Rxy(7))) and Cx(3))) ='0' ) and dst_addr /= cur_addr and packet_drop_in <= '0' ) then
err_header_not_empty_packet_drop_in <= '1';
else
err_header_not_empty_packet_drop_in <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in, packet_drop)
begin
if (flit_type = "001" and empty = '0' and ( ( ((((N1_out and not E1_out and not W1_out) or
(N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) or
(((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or
(E1_out and S1_out and Rxy(3))) and Cx(1)) or (((W1_out and not N1_out and not S1_out) or
(W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) or
(((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or
(S1_out and W1_out and Rxy(7))) and Cx(3))) ='1' ) or (dst_addr = cur_addr) ) and packet_drop_in /= packet_drop ) then
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal <= '1';
else
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if (flit_type = "001" and empty = '1' and packet_drop_in /= packet_drop ) then
err_header_empty_packet_drop_in_packet_drop_equal <= '1';
else
err_header_empty_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '1' and packet_drop_in /= '0' ) then
err_tail_not_empty_packet_drop_not_packet_drop_in <= '1';
else
err_tail_not_empty_packet_drop_not_packet_drop_in <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '0' and packet_drop_in /= packet_drop ) then
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '1';
else
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if ( ((flit_type /= "001" and flit_type /= "100") or empty = '1') and packet_drop_in /= packet_drop ) then
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '1';
else
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (packet_drop_order, packet_drop)
begin
if (packet_drop_order /= packet_drop) then
err_packet_drop_order <= '1';
else
err_packet_drop_order <= '0';
end if;
end process;
-- Added !
end behavior; | gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/Checkers/Control_Part_Checkers/LBDR_packet_drop_checkers/LBDR_routing_part/RTL/LBDR_packet_drop_routing_part_pseudo.vhd | 3 | 4772 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port ( empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
packet_drop_order: out std_logic;
packet_drop_in: out std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: out std_logic;
N1_out, E1_out, W1_out, S1_out: out std_logic;
grants_out: out std_logic
);
end LBDR_packet_drop_routing_part_pseudo;
architecture behavior of LBDR_packet_drop_routing_part_pseudo is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic;
signal grants: std_logic;
--signal packet_drop, packet_drop_in: std_logic;
--signal ReConf_FF_in, ReConf_FF_out: std_logic;
begin
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
grants_out <= grants;
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
-- Taking X1 signals to the output interface for checking with checkers
N1_out <= N1;
E1_out <= E1;
W1_out <= W1;
S1_out <= S1;
--process(clk, reset)
--begin
--if reset = '0' then
-- Rxy <= Rxy_reconf;
-- Req_N_FF <= '0';
-- Req_E_FF <= '0';
-- Req_W_FF <= '0';
-- Req_S_FF <= '0';
-- Req_L_FF <= '0';
-- Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
-- Temp_Cx <= (others => '0');
-- ReConf_FF_out <= '0';
-- reconfig_cx <= '0';
-- packet_drop <= '0';
--elsif clk'event and clk = '1' then
-- Rxy <= Rxy_in;
-- Req_N_FF <= Req_N_in;
-- Req_E_FF <= Req_E_in;
-- Req_W_FF <= Req_W_in;
-- Req_S_FF <= Req_S_in;
-- Req_L_FF <= Req_L_in;
-- ReConf_FF_out <= ReConf_FF_in;
-- Cx <= Cx_in;
-- reconfig_cx <= reconfig_cx_in;
-- Temp_Cx <= Temp_Cx_in;
-- packet_drop <= packet_drop_in;
--end if;
--end process;
-- The combionational part
process(N1, E1, W1, S1, Rxy, Cx, flit_type, dst_addr, cur_addr, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop) begin
packet_drop_in <= packet_drop;
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
if dst_addr = cur_addr then
Req_L_in <= '1';
else
Req_L_in <= Req_L_FF;
end if;
if ((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) or
(((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) or
(((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) or
(((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3))) ='0' and
(dst_addr /= cur_addr) then
packet_drop_in <= '1';
end if;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
if flit_type = "100" and empty = '0' then
if packet_drop = '1' then
packet_drop_in <= '0';
end if;
end if;
end process;
packet_drop_order <= packet_drop;
END; | gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/alu.vhd | 13 | 2633 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity alu is
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end; --alu
architecture logic of alu is
signal do_add : std_logic;
signal sum : std_logic_vector(32 downto 0);
signal less_than : std_logic;
begin
do_add <= '1' when alu_function = ALU_ADD else '0';
sum <= bv_adder(a_in, b_in, do_add);
less_than <= sum(32) when a_in(31) = b_in(31) or alu_function = ALU_LESS_THAN
else a_in(31);
GENERIC_ALU: if alu_type = "DEFAULT" generate
c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or
alu_function=ALU_SUBTRACT else
ZERO(31 downto 1) & less_than when alu_function=ALU_LESS_THAN or
alu_function=ALU_LESS_THAN_SIGNED else
a_in or b_in when alu_function=ALU_OR else
a_in and b_in when alu_function=ALU_AND else
a_in xor b_in when alu_function=ALU_XOR else
a_in nor b_in when alu_function=ALU_NOR else
ZERO;
end generate;
AREA_OPTIMIZED_ALU: if alu_type /= "DEFAULT" generate
c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or
alu_function=ALU_SUBTRACT else (others => 'Z');
c_alu <= ZERO(31 downto 1) & less_than when alu_function=ALU_LESS_THAN or
alu_function=ALU_LESS_THAN_SIGNED else
(others => 'Z');
c_alu <= a_in or b_in when alu_function=ALU_OR else (others => 'Z');
c_alu <= a_in and b_in when alu_function=ALU_AND else (others => 'Z');
c_alu <= a_in xor b_in when alu_function=ALU_XOR else (others => 'Z');
c_alu <= a_in nor b_in when alu_function=ALU_NOR else (others => 'Z');
c_alu <= ZERO when alu_function=ALU_NOTHING else (others => 'Z');
end generate;
end; --architecture logic
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Processor_NI/ram.vhd | 6 | 3151 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the RAM, reads the executable from either "code.txt",
-- or for Altera "code[0-3].hex".
-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ADDRESS_WIDTH : natural := 15;
subtype word is std_logic_vector(data_write'length-1 downto 0);
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH)/4 - 1) of word;
signal storage : storage_array;
begin
ram_proc: process(clk, enable, write_byte_enable,
address, data_write) --mem_write, mem_sel
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
file load_file : text open read_mode is stim_file;
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
--The following two lines had to be commented out for synthesis
readline(load_file, hex_file_line);
hread(hex_file_line, data);
storage(index) <= data;
index := index + 1;
end loop;
end if;
if rising_edge(clk) then
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if enable = '1' then
if write_byte_enable(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
end if;
if write_byte_enable /= "0000" then
storage(index) <= data;
end if;
end if;
data_read <= data;
end process;
end; --architecture logic
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/Checkers/Control_Part_Checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_checkers/RTL/FIFO_one_hot_credit_based_packet_drop_classifier_support_checkers.vhd | 3 | 54694 | --Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
--err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out,
--err_valid_in_state_out_state_in_not_change,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
--err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
--err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
--err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change : out std_logic
--err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change
--err_state_out_invalid_state_in_state_out_not_change,
--err_state_out_invalid_not_fault_info,
--err_state_out_invalid_not_health_info,
--err_state_out_invalid_not_fake_credit,
--err_state_out_invalid_not_write_fake_flit,
--err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change: out std_logic
);
end FIFO_credit_based_control_part_checkers;
architecture behavior of FIFO_credit_based_control_part_checkers is
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
--signal read_en_signal: std_logic;
begin
--read_en_signal <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty_out;
-- Functional Checkers (Might cover or be covered by some of the structural checkers)
-- Empty and full cannot be high at the same time!
process (empty_out, full_out)
begin
if (empty_out = '1' and full_out = '1') then
err_empty_full <= '1';
else
err_empty_full <= '0';
end if;
end process;
-- Reading from an empty FIFO is not possible!
process (empty_out, read_en_out)
begin
if (empty_out = '1' and read_en_out = '1') then
err_empty_read_en <= '1';
else
err_empty_read_en <= '0';
end if;
end process;
-- Writing to a full FIFO is not possible!
process (full_out, write_en_out)
begin
if (full_out = '1' and write_en_out = '1') then
err_full_write_en <= '1';
else
err_full_write_en <= '0';
end if;
end process;
-- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)!
process (state_in)
begin
if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
-- Read pointer must always be one-hot!
process (read_pointer_in)
begin
if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then
err_read_pointer_in_onehot <= '1';
else
err_read_pointer_in_onehot <= '0';
end if;
end process;
-- Write pointer must always be one-hot!
process (write_pointer_in)
begin
if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then
err_write_pointer_in_onehot <= '1';
else
err_write_pointer_in_onehot <= '0';
end if;
end process;
---------------------------------------------------------------------------------------------------------
-- Structural Checkers
-- Write pointer and Read pointer checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
else
err_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
else
err_not_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
else
err_read_pointer_write_pointer_not_empty <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
else
err_read_pointer_write_pointer_empty <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
else
err_read_pointer_write_pointer_not_full <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
else
err_read_pointer_write_pointer_full <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
else
err_read_pointer_increment <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
else
err_read_pointer_not_increment <= '0';
end if;
end process;
-- Checked !
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then
err_write_en <= '1';
else
err_write_en <= '0';
end if;
end process;
-- Updated !
process (valid_in, write_en_out)
begin
if (valid_in = '0' and write_en_out = '1') then
err_not_write_en <= '1';
else
err_not_write_en <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then
err_not_write_en1 <= '1';
else
err_not_write_en1 <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then
err_not_write_en2 <= '1';
else
err_not_write_en2 <= '0';
end if;
end process;
-- Updated !
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then
err_read_en_mismatch <= '1';
else
err_read_en_mismatch <= '0';
end if;
end process;
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then
err_read_en_mismatch1 <= '1';
else
err_read_en_mismatch1 <= '0';
end if;
end process;
-- Newly added checkers for FIFO with packet drop and fault classifier support!
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then
err_fake_credit_read_en_fake_credit_counter_in_increment <= '1';
else
err_fake_credit_read_en_fake_credit_counter_in_increment <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1';
else
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, credit_out)
begin
if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then
err_fake_credit_read_en_credit_out <= '1';
else
err_fake_credit_read_en_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0';
end if;
end process;
--process (fake_credit, read_en_out, credit_out)
--begin
-- if (fake_credit = '1' and read_en_out = '1' and credit_out = '1') then
-- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '1';
-- else
-- err_fake_credit_read_en_fake_credit_counter_zero_not_credit_out <= '0';
-- end if;
--end process;
-- Checkers for Packet Dropping FSM of FIFO
--process (valid_in, state_out, state_in)
--begin
-- if (valid_in = '0' and (state_out = Idle or state_out = Header_flit or state_out = Body_flit or state_out = Packet_drop) and state_in /= state_out) then
-- err_valid_in_state_out_state_in_not_change <= '1';
-- else
-- err_valid_in_state_out_state_in_not_change <= '0';
-- end if;
--end process;
-- Idle state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, valid_in, state_in)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, fault_out, valid_in, state_in, state_out)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0';
end if;
end process;
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '0' and fake_credit = '1') then
err_state_out_Idle_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Idle_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, fault_info)
begin
if (state_out = Idle and fault_out = '0' and fault_info = '1') then
err_state_out_Idle_not_fault_out_not_fault_info <= '1';
else
err_state_out_Idle_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '1' and fake_credit = '0') then
err_state_out_Idle_fault_out_fake_credit <= '1';
else
err_state_out_Idle_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, state_in)
begin
if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Idle_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Idle_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, fault_out, fault_info)
begin
if (state_out = Idle and fault_out = '1' and fault_info = '0') then
err_state_out_Idle_fault_out_fault_info <= '1';
else
err_state_out_Idle_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in)
begin
if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Idle_fault_out_faulty_packet_in <= '1';
else
err_state_out_Idle_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Idle and write_fake_flit = '1') then
err_state_out_Idle_not_write_fake_flit <= '1';
else
err_state_out_Idle_not_write_fake_flit <= '0';
end if;
end process;
-- Other properties for Idle state
--------------------------------------------------------------------------------------------------
process (state_out, health_info)
begin
if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then
err_state_out_Idle_not_health_info <= '1';
else
err_state_out_Idle_not_health_info <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Header_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then
-- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Header_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Header_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in, state_out)
begin
if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Header_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Header_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Header_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1';
else
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Body_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, health_info)
begin
if (state_out = Body_flit and valid_in = '0' and health_info = '1') then
err_state_out_Body_flit_valid_in_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_health_info <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "010" and flit_type /= "100" and state_in /= state_out) then
-- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Body_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Body_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Body_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Body_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Body_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if (state_out = Body_flit and fake_credit = '1') then
err_state_out_Body_flit_not_fake_credit <= '1';
else
err_state_out_Body_flit_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Tail_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0';
end if;
end process;
--process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
--begin
-- if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then
-- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info = '0') then
err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1';
else
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1';
else
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info)
begin
if (state_out = Tail_flit and valid_in = '0' and fault_info = '1') then
err_state_out_Tail_flit_not_valid_in_not_fault_info <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fault_info <= '0';
end if;
end process;
process (state_out, valid_in, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Tail_flit and write_fake_flit = '1') then
err_state_out_Tail_flit_not_write_fake_flit <= '1';
else
err_state_out_Tail_flit_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Packet_drop state
-- faulty_packet_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0';
end if;
end process;
-- faulty_packet_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, fault_info)
begin
if (state_out = Packet_drop and fault_info = '1') then
err_state_out_Packet_drop_not_fault_info <= '1';
else
err_state_out_Packet_drop_not_fault_info <= '0';
end if;
end process;
process (state_out, faulty_packet_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0';
end if;
end process;
--process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
--begin
-- if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
-- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_and_tail_or_fault_out_state_in_state_out_not_change <= '0';
-- end if;
--end process;
-- Invalid state
--process (state_out, state_in)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and state_in /= state_out) then
-- err_state_out_invalid_state_in_state_out_not_change <= '1';
-- else
-- err_state_out_invalid_state_in_state_out_not_change <= '0';
-- end if;
--end process;
--process (state_out, fault_info)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fault_info = '1') then
-- err_state_out_invalid_not_fault_info <= '1';
-- else
-- err_state_out_invalid_not_fault_info <= '0';
-- end if;
--end process;
--process (state_out, health_info)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and health_info = '1') then
-- err_state_out_invalid_not_health_info <= '1';
-- else
-- err_state_out_invalid_not_health_info <= '0';
-- end if;
--end process;
--process (state_out, fake_credit)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and fake_credit = '1') then
-- err_state_out_invalid_not_fake_credit <= '1';
-- else
-- err_state_out_invalid_not_fake_credit <= '0';
-- end if;
--end process;
--process (state_out, write_fake_flit)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and write_fake_flit = '1') then
-- err_state_out_invalid_not_write_fake_flit <= '1';
-- else
-- err_state_out_invalid_not_write_fake_flit <= '0';
-- end if;
--end process;
--process (state_out, faulty_packet_in, faulty_packet_out)
--begin
-- if (state_out /= Idle and state_out /= Header_flit and state_out /= Body_flit and state_out /= Tail_flit and state_out /= Packet_drop and faulty_packet_in /= faulty_packet_out) then
-- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '1';
-- else
-- err_state_out_invalid_faulty_packet_in_faulty_packet_out_not_change <= '0';
-- end if;
--end process;
end behavior; | gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/AsyncDataRegisterAdapter.vhd | 3 | 3159 | --Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AsyncDataRegisterAdapter is
Generic ( Size : positive := 8);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
-- Data interface
DI : in STD_LOGIC_VECTOR (Size-1 downto 0);
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)
);
end AsyncDataRegisterAdapter;
architecture AsyncDataRegisterAdapter_arch of AsyncDataRegisterAdapter is
signal DI_sync_first, DI_sync: STD_LOGIC_VECTOR (Size-1 downto 0);
signal sreg_do: STD_LOGIC_VECTOR (Size-1 downto 0);
signal sreg_so: STD_LOGIC;
signal sticky_flags, sticky_flags_mux: STD_LOGIC_VECTOR (Size-1 downto 0);
signal flag_mask_strobe: STD_LOGIC;
component SReg is
Generic ( Size : positive := 7);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end component;
begin
sticky_flags_mux <= (sticky_flags or DI_sync) and not sreg_do when flag_mask_strobe = '1' else sticky_flags or DI_sync;
synchronizer_di : process(TCK,RST)
begin
if RST = '1' then
DI_sync_first <= (others => '0');
DI_sync <= (others => '0');
elsif TCK'event and TCK = '1' then
DI_sync_first <= DI;
DI_sync <= DI_sync_first;
end if ;
end process ; -- synchronizer
sticky_flag_update : process(TCK,RST)
begin
if RST = '1' then
sticky_flags <= (others => '0');
elsif TCK'event and TCK = '1' then
sticky_flags <= sticky_flags_mux;
end if ;
end process ;
sticky_flag_update_strobe : process(TCK)
begin
if TCK'event and TCK = '1' then
flag_mask_strobe <= SEL and UE;
end if;
end process;
SO <= sreg_so;
DO <= sreg_do;
shiftreg : SReg
Generic map ( Size => Size)
Port map ( -- Scan Interface scan_client ----------
SI => SI, -- Input Port SI = SI
SO => sreg_so,
SEL => SEL,
----------------------------------------
SE => SE,
CE => CE,
UE => UE,
RST => RST,
TCK => TCK,
DI => sticky_flags,
DO => sreg_do);
end AsyncDataRegisterAdapter_arch; | gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/New_SHMU_on_Node/network_2x2_NI_FI_packet_drop_SHMU_credit_based_with_checkers_tb.vhd | 3 | 10824 | --Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TB_Package.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
-- Declaring network component
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0);
--fault injector signals
FI_Add_2_0, FI_Add_0_2: in std_logic_vector(4 downto 0);
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: in std_logic;
FI_Add_3_1, FI_Add_1_3: in std_logic_vector(4 downto 0);
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: in std_logic;
FI_Add_1_0, FI_Add_0_1: in std_logic_vector(4 downto 0);
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: in std_logic;
FI_Add_3_2, FI_Add_2_3: in std_logic_vector(4 downto 0);
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: in std_logic;
--------------
link_faults_0: out std_logic_vector(4 downto 0);
turn_faults_0: out std_logic_vector(7 downto 0);
Rxy_reconf_PE_0: in std_logic_vector(7 downto 0);
Cx_reconf_PE_0: in std_logic_vector(3 downto 0);
Reconfig_command_0 : in std_logic;
--------------
link_faults_1: out std_logic_vector(4 downto 0);
turn_faults_1: out std_logic_vector(7 downto 0);
Rxy_reconf_PE_1: in std_logic_vector(7 downto 0);
Cx_reconf_PE_1: in std_logic_vector(3 downto 0);
Reconfig_command_1 : in std_logic;
--------------
link_faults_2: out std_logic_vector(4 downto 0);
turn_faults_2: out std_logic_vector(7 downto 0);
Rxy_reconf_PE_2: in std_logic_vector(7 downto 0);
Cx_reconf_PE_2: in std_logic_vector(3 downto 0);
Reconfig_command_2 : in std_logic;
--------------
link_faults_3: out std_logic_vector(4 downto 0);
turn_faults_3: out std_logic_vector(7 downto 0);
Rxy_reconf_PE_3: in std_logic_vector(7 downto 0);
Cx_reconf_PE_3: in std_logic_vector(3 downto 0);
Reconfig_command_3 : in std_logic
);
end component;
component NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
log_file : string := "output.txt");
port( reset : in std_logic;
clk : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(7 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end component; --component NoC_Node
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
--fault injector signals
signal FI_Add_2_0, FI_Add_0_2: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0) := (others=>'0');
signal sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0: std_logic :='0';
signal FI_Add_3_1, FI_Add_1_3: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0) := (others=>'0');
signal sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1: std_logic :='0';
signal FI_Add_1_0, FI_Add_0_1: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0):= (others=>'0');
signal sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0: std_logic :='0';
signal FI_Add_3_2, FI_Add_2_3: std_logic_vector(integer(ceil(log2(real(31))))-1 downto 0):= (others=>'0');
signal sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2: std_logic :='0';
signal link_faults_0 : std_logic_vector(4 downto 0);
signal turn_faults_0 : std_logic_vector(7 downto 0);
signal Rxy_reconf_PE_0 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_0 : std_logic_vector(3 downto 0);
signal Reconfig_command_0 : std_logic;
signal link_faults_1 : std_logic_vector(4 downto 0);
signal turn_faults_1 : std_logic_vector(7 downto 0);
signal Rxy_reconf_PE_1 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_1 : std_logic_vector(3 downto 0);
signal Reconfig_command_1 : std_logic;
signal link_faults_2 : std_logic_vector(4 downto 0);
signal turn_faults_2 : std_logic_vector(7 downto 0);
signal Rxy_reconf_PE_2 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_2 : std_logic_vector(3 downto 0);
signal Reconfig_command_2 : std_logic;
signal link_faults_3 : std_logic_vector(4 downto 0);
signal turn_faults_3 : std_logic_vector(7 downto 0);
signal Rxy_reconf_PE_3 : std_logic_vector(7 downto 0);
signal Cx_reconf_PE_3 : std_logic_vector(3 downto 0);
signal Reconfig_command_3 : std_logic;
--------------
constant clk_period : time := 1 ns;
signal reset, not_reset, clk: std_logic :='0';
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after 1 ns;
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3,
--fault injector signals
--FI vertical signals
FI_Add_2_0, FI_Add_0_2,
sta0_0_2, sta1_0_2, sta0_2_0, sta1_2_0,
FI_Add_3_1, FI_Add_1_3,
sta0_1_3, sta1_1_3, sta0_3_1, sta1_3_1,
--FI horizontal signals
FI_Add_1_0, FI_Add_0_1,
sta0_0_1, sta1_0_1, sta0_1_0, sta1_1_0,
FI_Add_3_2, FI_Add_2_3,
sta0_2_3, sta1_2_3, sta0_3_2, sta1_3_2,
-- should be connected to NI
link_faults_0, turn_faults_0, Rxy_reconf_PE_0, Cx_reconf_PE_0, Reconfig_command_0,
link_faults_1, turn_faults_1, Rxy_reconf_PE_1, Cx_reconf_PE_1, Reconfig_command_1,
link_faults_2, turn_faults_2, Rxy_reconf_PE_2, Cx_reconf_PE_2, Reconfig_command_2,
link_faults_3, turn_faults_3, Rxy_reconf_PE_3, Cx_reconf_PE_3, Reconfig_command_3
);
not_reset <= not reset;
-- connecting the PEs
PE_0: NoC_Node
generic map( current_address => 0,
stim_file => "code_0.txt",
log_file => "output_0.txt")
port map( not_reset, clk,
credit_in => credit_out_L_0,
valid_out => valid_in_L_0,
TX => RX_L_0,
credit_out => credit_in_L_0,
valid_in => valid_out_L_0,
RX => TX_L_0,
link_faults => link_faults_0,
turn_faults => turn_faults_0,
Rxy_reconf_PE => Rxy_reconf_PE_0,
Cx_reconf_PE => Cx_reconf_PE_0,
Reconfig_command => Reconfig_command_0
);
PE_1: NoC_Node
generic map( current_address => 1,
stim_file => "code_1.txt",
log_file => "output_1.txt")
port map( not_reset, clk,
credit_in => credit_out_L_1,
valid_out => valid_in_L_1,
TX => RX_L_1,
credit_out => credit_in_L_1,
valid_in => valid_out_L_1,
RX => TX_L_1,
link_faults => link_faults_1,
turn_faults => turn_faults_1,
Rxy_reconf_PE => Rxy_reconf_PE_1,
Cx_reconf_PE => Cx_reconf_PE_1,
Reconfig_command => Reconfig_command_1
);
PE_2: NoC_Node
generic map( current_address => 2,
stim_file => "code_2.txt",
log_file => "output_2.txt")
port map( not_reset, clk,
credit_in => credit_out_L_2,
valid_out => valid_in_L_2,
TX => RX_L_2,
credit_out => credit_in_L_2,
valid_in => valid_out_L_2,
RX => TX_L_2,
link_faults => link_faults_2,
turn_faults => turn_faults_2,
Rxy_reconf_PE => Rxy_reconf_PE_2,
Cx_reconf_PE => Cx_reconf_PE_2,
Reconfig_command => Reconfig_command_2
);
PE_3: NoC_Node
generic map( current_address => 3,
stim_file => "code_3.txt",
log_file => "output_3.txt")
port map( not_reset, clk,
credit_in => credit_out_L_3,
valid_out => valid_in_L_3,
TX => RX_L_3,
credit_out => credit_in_L_3,
valid_in => valid_out_L_3,
RX => TX_L_3,
link_faults => link_faults_3,
turn_faults => turn_faults_3,
Rxy_reconf_PE => Rxy_reconf_PE_3,
Cx_reconf_PE => Cx_reconf_PE_3,
Reconfig_command => Reconfig_command_3
);
-- connecting the fault generators
gen_fault(sta0_1_0, sta1_1_0, FI_Add_1_0, 63,442052708,1828205602);
gen_fault(sta0_0_1, sta1_0_1, FI_Add_0_1, 53,1295222520,931907344);
gen_fault(sta0_2_0, sta1_2_0, FI_Add_2_0, 70,384023008,1549010334);
gen_fault(sta0_0_2, sta1_0_2, FI_Add_0_2, 61,460224063,1900282825);
gen_fault(sta0_3_1, sta1_3_1, FI_Add_3_1, 51,1175811338,1371195782);
gen_fault(sta0_1_3, sta1_1_3, FI_Add_1_3, 48,2134559509,1884522909);
gen_fault(sta0_3_2, sta1_3_2, FI_Add_3_2, 52,69484405,203739638);
gen_fault(sta0_2_3, sta1_2_3, FI_Add_2_3, 48,1017472312,722198941);
end;
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/ddr_ctrl.vhd | 12 | 13365 | ---------------------------------------------------------------------
-- TITLE: DDR SDRAM Interface
-- AUTHORS: Steve Rhoads ([email protected])
-- DATE CREATED: 7/26/07
-- FILENAME: ddr_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Double Data Rate Sychronous Dynamic Random Access Memory Interface
--
-- For: 64 MB = MT46V32M16, 512Mb, 32Mb x 16 (default)
-- ROW = address(25 downto 13)
-- BANK = address(12 downto 11)
-- COL = address(10 downto 2)
--
-- Changes are needed for 32 MB = MT46V16M16, 256Mb, 16Mb x 16
-- ROW = address(24 downto 12) -- 25 ignored
-- BANK = address(11 downto 10)
-- COL = address(9 downto 2) --also change ddr_init.c
--
-- Changes are needed for 128 MB = MT46V64M16, 1Gb, 64Mb x 16
-- ROW = address(26 downto 14)
-- BANK = address(13 downto 12)
-- COL = address(11 downto 2) --also change ddr_init.c
--
-- Requires CAS latency=2; burst size=2.
-- Requires clk changes on rising_edge(clk_2x).
-- Requires active, address, byte_we, data_w stable throughout transfer.
-- DLL mode requires 77MHz. Non-DLL mode runs at 25 MHz.
--
-- cycle_cnt 777777770000111122223333444455556666777777777777
-- clk_2x --__--__--__--__--__--__--__--__--__--__--__--__
-- clk ____----____----____----____----____----____----
-- SD_CLK ----____----____----____----____----____----____
-- cmd ____write+++WRITE+++____________________________
-- SD_DQ ~~~~~~~~~~~~~~uuuullllUUUULLLL~~~~~~~~~~~~~~~~~~
--
-- cycle_cnt 777777770000111122223333444455556666777777777777
-- clk_2x --__--__--__--__--__--__--__--__--__--__--__--__
-- clk ____----____----____----____----____----____----
-- SD_CLK ----____----____----____----____----____----____
-- cmd ____read++++________________________read++++____
-- SD_DQ ~~~~~~~~~~~~~~~~~~~~~~~~uuuullll~~~~~~~~~~~~~~~~
-- SD_DQnDLL ~~~~~~~~~~~~~~~~~~~~~~~~~~uuuullll~~~~~~~~~~~~~~
-- pause ____------------------------________------------
--
-- Must run DdrInit() to initialize DDR chip.
-- Read Micron DDR SDRAM MT46V32M16 data sheet for more details.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity ddr_ctrl is
port(
clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end; --entity ddr
architecture logic of ddr_ctrl is
--Commands for bits RAS & CAS & WE
subtype command_type is std_logic_vector(2 downto 0);
constant COMMAND_LMR : command_type := "000";
constant COMMAND_AUTO_REFRESH : command_type := "001";
constant COMMAND_PRECHARGE : command_type := "010";
constant COMMAND_ACTIVE : command_type := "011";
constant COMMAND_WRITE : command_type := "100";
constant COMMAND_READ : command_type := "101";
constant COMMAND_TERMINATE : command_type := "110";
constant COMMAND_NOP : command_type := "111";
subtype ddr_state_type is std_logic_vector(3 downto 0);
constant STATE_POWER_ON : ddr_state_type := "0000";
constant STATE_IDLE : ddr_state_type := "0001";
constant STATE_ROW_ACTIVATE : ddr_state_type := "0010";
constant STATE_ROW_ACTIVE : ddr_state_type := "0011";
constant STATE_READ : ddr_state_type := "0100";
constant STATE_READ2 : ddr_state_type := "0101";
constant STATE_READ3 : ddr_state_type := "0110";
constant STATE_PRECHARGE : ddr_state_type := "0111";
constant STATE_PRECHARGE2 : ddr_state_type := "1000";
signal state_prev : ddr_state_type;
signal refresh_cnt : std_logic_vector(7 downto 0);
signal data_write2 : std_logic_vector(47 downto 0); --write pipeline
signal byte_we_reg2 : std_logic_vector(5 downto 0); --write pipeline
signal write_active : std_logic;
signal write_prev : std_logic;
signal cycle_count : std_logic_vector(2 downto 0); --half clocks since op
signal cycle_count2 : std_logic_vector(2 downto 0); --delayed by quarter clock
signal cke_reg : std_logic;
signal clk_p : std_logic;
signal bank_open : std_logic_vector(3 downto 0);
signal data_read : std_logic_vector(31 downto 0);
begin
ddr_proc: process(clk, clk_p, clk_2x, reset_in,
address, byte_we, data_w, active, no_start, no_stop,
SD_DQ, SD_UDQS, SD_LDQS,
state_prev, refresh_cnt,
byte_we_reg2, data_write2,
cycle_count, cycle_count2, write_prev,
write_active, cke_reg, bank_open,
data_read)
type address_array_type is array(3 downto 0) of std_logic_vector(12 downto 0);
variable address_row : address_array_type;
variable command : std_logic_vector(2 downto 0); --RAS & CAS & WE
variable bank_index : integer;
variable state_current : ddr_state_type;
begin
command := COMMAND_NOP;
bank_index := conv_integer(address(12 downto 11));
state_current := state_prev;
--DDR state machine to determine state_current and command
case state_prev is
when STATE_POWER_ON =>
if active = '1' then
if byte_we /= "0000" then
command := address(6 downto 4); --LMR="000"
else
state_current := STATE_IDLE; --read transistions to STATE_IDLE
end if;
end if;
when STATE_IDLE =>
if refresh_cnt(7) = '1' then
state_current := STATE_PRECHARGE;
command := COMMAND_AUTO_REFRESH;
elsif active = '1' and no_start = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
end if;
when STATE_ROW_ACTIVATE =>
state_current := STATE_ROW_ACTIVE;
when STATE_ROW_ACTIVE =>
if refresh_cnt(7) = '1' then
if write_prev = '0' then
state_current := STATE_PRECHARGE;
command := COMMAND_PRECHARGE;
end if;
elsif active = '1' and no_start = '0' then
if bank_open(bank_index) = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
elsif address(25 downto 13) /= address_row(bank_index) then
if write_prev = '0' then
state_current := STATE_PRECHARGE;
command := COMMAND_PRECHARGE;
end if;
else
if byte_we /= "0000" then
command := COMMAND_WRITE;
elsif write_prev = '0' then
state_current := STATE_READ;
command := COMMAND_READ;
end if;
end if;
end if;
when STATE_READ =>
state_current := STATE_READ2;
when STATE_READ2 =>
state_current := STATE_READ3;
when STATE_READ3 =>
if no_stop = '0' then
state_current := STATE_ROW_ACTIVE;
end if;
when STATE_PRECHARGE =>
state_current := STATE_PRECHARGE2;
when STATE_PRECHARGE2 =>
state_current := STATE_IDLE;
when others =>
state_current := STATE_IDLE;
end case; --state_prev
--rising_edge(clk) domain registers
if reset_in = '1' then
state_prev <= STATE_POWER_ON;
cke_reg <= '0';
refresh_cnt <= ZERO(7 downto 0);
write_prev <= '0';
write_active <= '0';
bank_open <= "0000";
elsif rising_edge(clk) then
if active = '1' then
cke_reg <= '1';
end if;
if command = COMMAND_WRITE then
write_prev <= '1';
elsif cycle_count2(2 downto 1) = "11" then
write_prev <= '0';
end if;
if command = COMMAND_WRITE then
write_active <= '1';
elsif cycle_count2 = "100" then
write_active <= '0';
end if;
if command = COMMAND_ACTIVE then
bank_open(bank_index) <= '1';
address_row(bank_index) := address(25 downto 13);
end if;
if command = COMMAND_PRECHARGE then
bank_open <= "0000";
end if;
if command = COMMAND_AUTO_REFRESH then
refresh_cnt <= ZERO(7 downto 0);
else
refresh_cnt <= refresh_cnt + 1;
end if;
state_prev <= state_current;
end if; --rising_edge(clk)
--rising_edge(clk_2x) domain registers
if reset_in = '1' then
cycle_count <= "000";
elsif rising_edge(clk_2x) then
--Cycle_count
if (command = COMMAND_READ or command = COMMAND_WRITE) and clk = '1' then
cycle_count <= "000";
elsif cycle_count /= "111" then
cycle_count <= cycle_count + 1;
end if;
clk_p <= clk; --earlier version of not clk
--Read data (DLL disabled)
if cycle_count = "100" then
data_read(31 downto 16) <= SD_DQ; --data
elsif cycle_count = "101" then
data_read(15 downto 0) <= SD_DQ;
end if;
end if;
--falling_edge(clk_2x) domain registers
if reset_in = '1' then
cycle_count2 <= "000";
data_write2 <= ZERO(15 downto 0) & ZERO;
byte_we_reg2 <= "000000";
elsif falling_edge(clk_2x) then
cycle_count2 <= cycle_count;
--Write pipeline
if clk = '0' then
data_write2 <= data_write2(31 downto 16) & data_w;
byte_we_reg2 <= byte_we_reg2(3 downto 2) & byte_we;
else
data_write2(47 downto 16) <= data_write2(31 downto 0);
byte_we_reg2(5 downto 2) <= byte_we_reg2(3 downto 0);
end if;
--Read data (DLL enabled)
--if cycle_count = "100" then
-- data_read(31 downto 16) <= SD_DQ; --data
--elsif cycle_count = "101" then
-- data_read(15 downto 0) <= SD_DQ;
--end if;
end if;
data_r <= data_read;
--Write data
if write_active = '1' then
SD_UDQS <= clk_p; --upper_data_strobe
SD_LDQS <= clk_p; --low_data_strobe
SD_DQ <= data_write2(47 downto 32); --data
SD_UDM <= not byte_we_reg2(5); --upper_byte_enable
SD_LDM <= not byte_we_reg2(4); --low_byte_enable
else
SD_UDQS <= 'Z'; --upper_data_strobe
SD_LDQS <= 'Z'; --low_data_strobe
SD_DQ <= "ZZZZZZZZZZZZZZZZ"; --data
SD_UDM <= 'Z';
SD_LDM <= 'Z';
end if;
--DDR control signals
SD_CK_P <= clk_p; --clock_positive
SD_CK_N <= not clk_p; --clock_negative
SD_CKE <= cke_reg; --clock_enable
SD_BA <= address(12 downto 11); --bank_address
if command = COMMAND_ACTIVE or state_current = STATE_POWER_ON then
SD_A <= address(25 downto 13); --address row
elsif command = COMMAND_READ or command = COMMAND_WRITE then
SD_A <= "000" & address(10 downto 2) & "0"; --address col
else
SD_A <= "0010000000000"; --PERCHARGE all banks
end if;
SD_CS <= not cke_reg; --chip_select
SD_RAS <= command(2); --row_address_strobe
SD_CAS <= command(1); --column_address_strobe
SD_WE <= command(0); --write_enable
if active = '1' and state_current /= STATE_POWER_ON and
command /= COMMAND_WRITE and state_prev /= STATE_READ3 then
pause <= '1';
else
pause <= '0';
end if;
end process; --ddr_proc
end; --architecture logic
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/Arbiter_in_one_hot_with_checkers/Arbiter_in_one_hot_with_checkers.vhd | 12 | 12952 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
-- Is this like the old arbiter in the router with handshaking FC ??
entity Arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in;
architecture behavior of Arbiter_in is
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in : STATE_TYPE := IDLE;
SIGNAL X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic; -- needed for connecting output ports
-- of Arbiter_in to checker inputs
component Arbiter_in_one_hot_checkers is
port (
req_X_N :in std_logic;
req_X_E :in std_logic;
req_X_W :in std_logic;
req_X_S :in std_logic;
req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N :in std_logic;
X_E :in std_logic;
X_W :in std_logic;
X_S :in std_logic;
X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end component;
begin
-- Becuase of checkers we did this
X_N <= X_N_sig;
X_E <= X_E_sig;
X_W <= X_W_sig;
X_S <= X_S_sig;
X_L <= X_L_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
-- Arbiter_in Checkers module instantiation
ARBITER_IN_CHECKERS: Arbiter_in_one_hot_checkers port map (
req_X_N => req_X_N, -- _sig not needed, because it is an input port
req_X_E => req_X_E, -- _sig not needed, because it is an input port
req_X_W => req_X_W, -- _sig not needed, because it is an input port
req_X_S => req_X_S, -- _sig not needed, because it is an input port
req_X_L => req_X_L, -- _sig not needed, because it is an input port
state => state, -- _sig not needed, because it is an input port
state_in => state_in, -- _sig not needed, because it is an internal signal
X_N => X_N_sig,
X_E => X_E_sig,
X_W => X_W_sig,
X_S => X_S_sig,
X_L => X_L_sig,
-- Checker outputs
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => err_IDLE_Req_N,
err_IDLE_grant_N => err_IDLE_grant_N,
err_North_Req_N => err_North_Req_N,
err_North_grant_N => err_North_grant_N,
err_East_Req_E => err_East_Req_E,
err_East_grant_E => err_East_grant_E,
err_West_Req_W => err_West_Req_W,
err_West_grant_W => err_West_grant_W,
err_South_Req_S => err_South_Req_S,
err_South_grant_S => err_South_grant_S,
err_Local_Req_L => err_Local_Req_L,
err_Local_grant_L => err_Local_grant_L,
err_IDLE_Req_E => err_IDLE_Req_E,
err_IDLE_grant_E => err_IDLE_grant_E,
err_North_Req_E => err_North_Req_E,
err_North_grant_E => err_North_grant_E,
err_East_Req_W => err_East_Req_W,
err_East_grant_W => err_East_grant_W,
err_West_Req_S => err_West_Req_S,
err_West_grant_S => err_West_grant_S,
err_South_Req_L => err_South_Req_L,
err_South_grant_L => err_South_grant_L,
err_Local_Req_N => err_Local_Req_N,
err_Local_grant_N => err_Local_grant_N,
err_IDLE_Req_W => err_IDLE_Req_W,
err_IDLE_grant_W => err_IDLE_grant_W,
err_North_Req_W => err_North_Req_W,
err_North_grant_W => err_North_grant_W,
err_East_Req_S => err_East_Req_S,
err_East_grant_S => err_East_grant_S,
err_West_Req_L => err_West_Req_L,
err_West_grant_L => err_West_grant_L,
err_South_Req_N => err_South_Req_N,
err_South_grant_N => err_South_grant_N,
err_Local_Req_E => err_Local_Req_E,
err_Local_grant_E => err_Local_grant_E,
err_IDLE_Req_S => err_IDLE_Req_S,
err_IDLE_grant_S => err_IDLE_grant_S,
err_North_Req_S => err_North_Req_S,
err_North_grant_S => err_North_grant_S,
err_East_Req_L => err_East_Req_L,
err_East_grant_L => err_East_grant_L,
err_West_Req_N => err_West_Req_N,
err_West_grant_N => err_West_grant_N,
err_South_Req_E => err_South_Req_E,
err_South_grant_E => err_South_grant_E,
err_Local_Req_W => err_Local_Req_W,
err_Local_grant_W => err_Local_grant_W,
err_IDLE_Req_L => err_IDLE_Req_L,
err_IDLE_grant_L => err_IDLE_grant_L,
err_North_Req_L => err_North_Req_L,
err_North_grant_L => err_North_grant_L,
err_East_Req_N => err_East_Req_N,
err_East_grant_N => err_East_grant_N,
err_West_Req_E => err_West_Req_E,
err_West_grant_E => err_West_grant_E,
err_South_Req_W => err_South_Req_W,
err_South_grant_W => err_South_grant_W,
err_Local_Req_S => err_Local_Req_S,
err_Local_grant_S => err_Local_grant_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_no_grants => err_request_no_grants,
err_no_Req_N_grant_N => err_no_Req_N_grant_N,
err_no_Req_E_grant_E => err_no_Req_E_grant_E,
err_no_Req_W_grant_W => err_no_Req_W_grant_W,
err_no_Req_S_grant_S => err_no_Req_S_grant_S,
err_no_Req_L_grant_L => err_no_Req_L_grant_L
);
-- Main Logic of Arbiter_in
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L)
begin
X_N_sig <= '0';
X_E_sig <= '0';
X_W_sig <= '0';
X_S_sig <= '0';
X_L_sig <= '0';
case state is
when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S)
-- Here it seems N has the higest priority, is it fine ?
if req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
else
state_in <= state;
end if;
when North =>
if req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
else
state_in <= state;
end if;
when East =>
if req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
else
state_in <= state;
end if;
when West =>
if req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
else
state_in <= state;
end if;
when South =>
if req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
else
state_in <= state;
end if;
when others =>
if req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
else
state_in <= state;
end if;
end case;
end process;
end;
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/Router_32_bit_credit_based_packet_drop_classifier.vhd | 3 | 19736 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic
);
end router_credit_based_PD_C;
architecture behavior of router_credit_based_PD_C is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end COMPONENT;
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty:out std_logic
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 0;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
begin
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
| gpl-3.0 |
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