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siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/plasma.vhd | 3 | 15291 | ---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
-- 0x10000000 - 0x100fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been instantiated!
-- * some changes has been applied to the ports of the CPU to facilitate the new NI!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 0;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address, ram_address_late : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r, ram_data_r_ni : std_logic_vector(31 downto 0);
signal NI_irq_out : std_logic;
--signal NI_read_flag : std_logic;
--signal NI_write_flag : std_logic;
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
constant reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
constant reserved_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant reserved_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, ram_address_late, ram_data_r_ni,
data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w)
begin
case cpu_address(30 downto 28) is
when "000" => --internal RAM
if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address)
or (ram_address_late = reserved_counter_address)) then
cpu_data_r <= ram_data_r_ni;
else
cpu_data_r <= ram_data_r;
end if;
when "001" => --external RAM
if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address)
or (ram_address_late = reserved_counter_address)) then
cpu_data_r <= ram_data_r_ni;
else
cpu_data_r <= ram_data_r; --cache
end if;
else
cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others =>
cpu_data_r <= gpioA_in;
end case;
when "011" => --flash
cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO;
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
counter_reg <= bv_inc(counter_reg);
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
elsif cpu_address(6 downto 4) = "110" then
counter_reg <= cpu_data_w;
end if;
end if;
end if;
end if;
end process;
process(ram_address, reset, clk)begin
if reset = '1' then
ram_address_late <= (others => '0');
elsif clk'event and clk = '1' then
ram_address_late <= ram_address;
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w, data_read)
begin
if cache_access = '1' then --Check if cache hit or write through
ram_enable <= '1';
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & address_next(11 downto 2);
ram_data_w <= cpu_data_w;
elsif cache_miss = '1' then --Update cache after cache miss
ram_enable <= '1';
ram_byte_we <= "1111";
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & cpu_address(11 downto 2);
ram_data_w <= data_read;
else --Normal non-cache access
if address_next(30 downto 28) = "000" then
ram_enable <= '1';
else
ram_enable <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
u2_ram: ram
generic map (memory_type => memory_type, stim_file => stim_file)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r);
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail);
dma_gen: if ethernet = '0' generate
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
dma_gen2: if ethernet = '1' generate
u4_eth: eth_dma
port map(
clk => clk,
reset => reset,
enable_eth => gpio0_reg(24),
select_eth => enable_eth,
rec_isr => irq_eth_rec,
send_isr => irq_eth_send,
address => address, --to DDR
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => eth_pause_in,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
E_RX_CLK => gpioA_in(20),
E_RX_DV => gpioA_in(19),
E_RXD => gpioA_in(18 downto 15),
E_TX_CLK => gpioA_in(14),
E_TX_EN => gpio0_out(28),
E_TXD => gpio0_out(27 downto 24));
end generate;
u4_ni: NI
generic map(current_address => current_address, SHMU_address => 0)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r_ni,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
irq_out => NI_irq_out,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX,
link_faults => link_faults,
turn_faults => turn_faults,
Rxy_reconf_PE => Rxy_reconf_PE,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command
);
end; --architecture logic
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/New_SHMU_on_Node/LBDR_packet_drop_checkers/LBDR_packet_drop_with_checkers.vhd | 6 | 27011 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic;
-- Checker outputs
-- Routing part checkers
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order,
-- Cx_Reconf checkers
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
-- Rxy_Reconf checkers
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end LBDR_packet_drop;
architecture behavior of LBDR_packet_drop is
signal Cx, Cx_in: std_logic_vector(3 downto 0);
signal Temp_Cx, Temp_Cx_in: std_logic_vector(3 downto 0);
signal reconfig_cx, reconfig_cx_in: std_logic;
signal ReConf_FF_in, ReConf_FF_out: std_logic;
signal Rxy, Rxy_in: std_logic_vector(7 downto 0);
signal Rxy_tmp, Rxy_tmp_in: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
signal grants: std_logic;
signal packet_drop, packet_drop_in: std_logic;
-- Signal(s) required for checker(s)
signal packet_drop_order_sig: std_logic;
component LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end component;
component Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end component;
component Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Rxy_tmp: in std_logic_vector(7 downto 0);
Reconfig_command : in std_logic;
flit_type: in std_logic_vector(2 downto 0);
grants: in std_logic;
empty: in std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_tmp_in: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end component;
begin
packet_drop_order <= packet_drop_order_sig;
-- LBDR packet drop routing part checkers instantiation
LBDR_packet_drop_routing_part_checkers: LBDR_packet_drop_routing_part_pseudo_checkers
generic map (cur_addr_rst => cur_addr_rst, NoC_size => NoC_size)
port map (
empty => empty,
flit_type => flit_type,
Req_N_FF => Req_N_FF,
Req_E_FF => Req_E_FF,
Req_W_FF => Req_W_FF,
Req_S_FF => Req_S_FF,
Req_L_FF => Req_L_FF,
grant_N => grant_N,
grant_E => grant_E,
grant_W => grant_W,
grant_S => grant_S,
grant_L => grant_L,
dst_addr => dst_addr,
Cx => Cx,
Rxy => Rxy,
packet_drop => packet_drop,
N1_out => N1,
E1_out => E1,
W1_out => W1,
S1_out => S1,
Req_N_in => Req_N_in,
Req_E_in => Req_E_in,
Req_W_in => Req_W_in,
Req_S_in => Req_S_in,
Req_L_in => Req_L_in,
grants => grants,
packet_drop_order => packet_drop_order_sig,
packet_drop_in => packet_drop_in,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => err_grants_onehot,
err_grants_mismatch => err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in => err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal => err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal => err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => err_packet_drop_order
);
-- LBDR packet drop Cx Reconfiguration module checkers instantiation
Cx_Reconf_checkers: Cx_Reconf_pseudo_checkers port map (
reconfig_cx => reconfig_cx,
flit_type => flit_type,
empty => empty,
grants => grants,
Cx_in => Cx_in,
Temp_Cx => Temp_Cx,
reconfig_cx_in => reconfig_cx_in,
Cx => Cx,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command,
Faulty_C_N => Faulty_C_N,
Faulty_C_E => Faulty_C_E,
Faulty_C_W => Faulty_C_W,
Faulty_C_S => Faulty_C_S,
Temp_Cx_in => Temp_Cx_in,
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal
);
-- LBDR packet drop Rxy Reconfiguration checkers instantiation
Rxy_Reconf_checkers : Rxy_Reconf_pseudo_checkers
port map (
ReConf_FF_out => ReConf_FF_out,
Rxy => Rxy,
Rxy_tmp => Rxy_tmp,
Reconfig_command => Reconfig_command,
flit_type => flit_type,
grants => grants,
empty => empty,
Rxy_reconf_PE => Rxy_reconf_PE,
Rxy_in => Rxy_in,
Rxy_tmp_in => Rxy_tmp_in,
ReConf_FF_in => ReConf_FF_in,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
process(clk, reset)
begin
if reset = '0' then
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
Rxy_tmp <= (others => '0');
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Temp_Cx <= (others => '0');
ReConf_FF_out <= '0';
reconfig_cx <= '0';
packet_drop <= '0';
elsif clk'event and clk = '1' then
Rxy <= Rxy_in;
Rxy_tmp <= Rxy_tmp_in;
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
ReConf_FF_out <= ReConf_FF_in;
Cx <= Cx_in;
reconfig_cx <= reconfig_cx_in;
Temp_Cx <= Temp_Cx_in;
packet_drop <= packet_drop_in;
end if;
end process;
-- The combionational part
process(Reconfig_command, Rxy_reconf_PE, Rxy_tmp, ReConf_FF_out, Rxy, flit_type, grants, empty)begin
Rxy_tmp_in <= Rxy_tmp;
if ReConf_FF_out= '1' and flit_type = "100" and empty = '0' and grants = '1' then
Rxy_in <= Rxy_tmp;
ReConf_FF_in <= '0';
else
Rxy_in <= Rxy;
if Reconfig_command = '1'then
Rxy_tmp_in <= Rxy_reconf_PE;
ReConf_FF_in <= '1';
else
Rxy_tmp_in <= Rxy_tmp;
ReConf_FF_in <= ReConf_FF_out;
end if;
end if;
end process;
process(Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Cx, Temp_Cx, flit_type, reconfig_cx, empty, grants, Cx_reconf_PE, Reconfig_command) begin
Temp_Cx_in <= Temp_Cx;
if reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' then
Cx_in <= Temp_Cx;
reconfig_cx_in <= '0';
else
Cx_in <= Cx;
if (Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1' then
reconfig_cx_in <= '1';
Temp_Cx_in <= not(Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N) and Cx;
elsif Reconfig_command = '1' then
reconfig_cx_in <= '1';
Temp_Cx_in <= Cx_reconf_PE;
else
reconfig_cx_in <= reconfig_cx;
end if;
end if;
end process;
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop, dst_addr, cur_addr) begin
packet_drop_in <= packet_drop;
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
if dst_addr = cur_addr then
Req_L_in <= '1';
else
Req_L_in <= Req_L_FF; -- Added to remove latch possibility. Correct ??
end if;
if ((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) or
(((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) or
(((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) or
(((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3))) ='0' and dst_addr /= cur_addr then
packet_drop_in <= '1';
end if;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
if flit_type = "100" and empty = '0' then
if packet_drop = '1' then
packet_drop_in <= '0';
end if;
end if;
end process;
packet_drop_order_sig <= packet_drop;
END; | gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/LBDR_packet_drop_with_checkers.vhd | 6 | 27011 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop is
generic (
cur_addr_rst: integer := 5;
Rxy_rst: integer := 60;
Cx_rst: integer := 15;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic;
-- Checker outputs
-- Routing part checkers
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order,
-- Cx_Reconf checkers
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
-- Rxy_Reconf checkers
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end LBDR_packet_drop;
architecture behavior of LBDR_packet_drop is
signal Cx, Cx_in: std_logic_vector(3 downto 0);
signal Temp_Cx, Temp_Cx_in: std_logic_vector(3 downto 0);
signal reconfig_cx, reconfig_cx_in: std_logic;
signal ReConf_FF_in, ReConf_FF_out: std_logic;
signal Rxy, Rxy_in: std_logic_vector(7 downto 0);
signal Rxy_tmp, Rxy_tmp_in: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
signal grants: std_logic;
signal packet_drop, packet_drop_in: std_logic;
-- Signal(s) required for checker(s)
signal packet_drop_order_sig: std_logic;
component LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end component;
component Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end component;
component Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Rxy_tmp: in std_logic_vector(7 downto 0);
Reconfig_command : in std_logic;
flit_type: in std_logic_vector(2 downto 0);
grants: in std_logic;
empty: in std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_tmp_in: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end component;
begin
packet_drop_order <= packet_drop_order_sig;
-- LBDR packet drop routing part checkers instantiation
LBDR_packet_drop_routing_part_checkers: LBDR_packet_drop_routing_part_pseudo_checkers
generic map (cur_addr_rst => cur_addr_rst, NoC_size => NoC_size)
port map (
empty => empty,
flit_type => flit_type,
Req_N_FF => Req_N_FF,
Req_E_FF => Req_E_FF,
Req_W_FF => Req_W_FF,
Req_S_FF => Req_S_FF,
Req_L_FF => Req_L_FF,
grant_N => grant_N,
grant_E => grant_E,
grant_W => grant_W,
grant_S => grant_S,
grant_L => grant_L,
dst_addr => dst_addr,
Cx => Cx,
Rxy => Rxy,
packet_drop => packet_drop,
N1_out => N1,
E1_out => E1,
W1_out => W1,
S1_out => S1,
Req_N_in => Req_N_in,
Req_E_in => Req_E_in,
Req_W_in => Req_W_in,
Req_S_in => Req_S_in,
Req_L_in => Req_L_in,
grants => grants,
packet_drop_order => packet_drop_order_sig,
packet_drop_in => packet_drop_in,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => err_grants_onehot,
err_grants_mismatch => err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in,
err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in,
err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in,
err_header_not_empty_packet_drop_in => err_header_not_empty_packet_drop_in,
err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal => err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal,
err_header_empty_packet_drop_in_packet_drop_equal => err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => err_packet_drop_order
);
-- LBDR packet drop Cx Reconfiguration module checkers instantiation
Cx_Reconf_checkers: Cx_Reconf_pseudo_checkers port map (
reconfig_cx => reconfig_cx,
flit_type => flit_type,
empty => empty,
grants => grants,
Cx_in => Cx_in,
Temp_Cx => Temp_Cx,
reconfig_cx_in => reconfig_cx_in,
Cx => Cx,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command,
Faulty_C_N => Faulty_C_N,
Faulty_C_E => Faulty_C_E,
Faulty_C_W => Faulty_C_W,
Faulty_C_S => Faulty_C_S,
Temp_Cx_in => Temp_Cx_in,
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal
);
-- LBDR packet drop Rxy Reconfiguration checkers instantiation
Rxy_Reconf_checkers : Rxy_Reconf_pseudo_checkers
port map (
ReConf_FF_out => ReConf_FF_out,
Rxy => Rxy,
Rxy_tmp => Rxy_tmp,
Reconfig_command => Reconfig_command,
flit_type => flit_type,
grants => grants,
empty => empty,
Rxy_reconf_PE => Rxy_reconf_PE,
Rxy_in => Rxy_in,
Rxy_tmp_in => Rxy_tmp_in,
ReConf_FF_in => ReConf_FF_in,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
process(clk, reset)
begin
if reset = '0' then
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
Rxy_tmp <= (others => '0');
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Temp_Cx <= (others => '0');
ReConf_FF_out <= '0';
reconfig_cx <= '0';
packet_drop <= '0';
elsif clk'event and clk = '1' then
Rxy <= Rxy_in;
Rxy_tmp <= Rxy_tmp_in;
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
ReConf_FF_out <= ReConf_FF_in;
Cx <= Cx_in;
reconfig_cx <= reconfig_cx_in;
Temp_Cx <= Temp_Cx_in;
packet_drop <= packet_drop_in;
end if;
end process;
-- The combionational part
process(Reconfig_command, Rxy_reconf_PE, Rxy_tmp, ReConf_FF_out, Rxy, flit_type, grants, empty)begin
Rxy_tmp_in <= Rxy_tmp;
if ReConf_FF_out= '1' and flit_type = "100" and empty = '0' and grants = '1' then
Rxy_in <= Rxy_tmp;
ReConf_FF_in <= '0';
else
Rxy_in <= Rxy;
if Reconfig_command = '1'then
Rxy_tmp_in <= Rxy_reconf_PE;
ReConf_FF_in <= '1';
else
Rxy_tmp_in <= Rxy_tmp;
ReConf_FF_in <= ReConf_FF_out;
end if;
end if;
end process;
process(Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Cx, Temp_Cx, flit_type, reconfig_cx, empty, grants, Cx_reconf_PE, Reconfig_command) begin
Temp_Cx_in <= Temp_Cx;
if reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' then
Cx_in <= Temp_Cx;
reconfig_cx_in <= '0';
else
Cx_in <= Cx;
if (Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1' then
reconfig_cx_in <= '1';
Temp_Cx_in <= not(Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N) and Cx;
elsif Reconfig_command = '1' then
reconfig_cx_in <= '1';
Temp_Cx_in <= Cx_reconf_PE;
else
reconfig_cx_in <= reconfig_cx;
end if;
end if;
end process;
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop, dst_addr, cur_addr) begin
packet_drop_in <= packet_drop;
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
if dst_addr = cur_addr then
Req_L_in <= '1';
else
Req_L_in <= Req_L_FF; -- Added to remove latch possibility. Correct ??
end if;
if ((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) or
(((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) or
(((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) or
(((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3))) ='0' and dst_addr /= cur_addr then
packet_drop_in <= '1';
end if;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
if flit_type = "100" and empty = '0' then
if packet_drop = '1' then
packet_drop_in <= '0';
end if;
end if;
end process;
packet_drop_order_sig <= packet_drop;
END; | gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/shifter.vhd | 16 | 3063 | ---------------------------------------------------------------------
-- TITLE: Shifter Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- Matthias Gruenewald
-- DATE CREATED: 2/2/01
-- FILENAME: shifter.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the 32-bit shifter unit.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity shifter is
generic(shifter_type : string := "DEFAULT");
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end; --entity shifter
architecture logic of shifter is
-- type shift_function_type is (
-- shift_nothing, shift_left_unsigned,
-- shift_right_signed, shift_right_unsigned);
signal shift1L, shift2L, shift4L, shift8L, shift16L : std_logic_vector(31 downto 0);
signal shift1R, shift2R, shift4R, shift8R, shift16R : std_logic_vector(31 downto 0);
signal fills : std_logic_vector(31 downto 16);
begin
fills <= "1111111111111111" when shift_func = SHIFT_RIGHT_SIGNED
and value(31) = '1'
else "0000000000000000";
shift1L <= value(30 downto 0) & '0' when shift_amount(0) = '1' else value;
shift2L <= shift1L(29 downto 0) & "00" when shift_amount(1) = '1' else shift1L;
shift4L <= shift2L(27 downto 0) & "0000" when shift_amount(2) = '1' else shift2L;
shift8L <= shift4L(23 downto 0) & "00000000" when shift_amount(3) = '1' else shift4L;
shift16L <= shift8L(15 downto 0) & ZERO(15 downto 0) when shift_amount(4) = '1' else shift8L;
shift1R <= fills(31) & value(31 downto 1) when shift_amount(0) = '1' else value;
shift2R <= fills(31 downto 30) & shift1R(31 downto 2) when shift_amount(1) = '1' else shift1R;
shift4R <= fills(31 downto 28) & shift2R(31 downto 4) when shift_amount(2) = '1' else shift2R;
shift8R <= fills(31 downto 24) & shift4R(31 downto 8) when shift_amount(3) = '1' else shift4R;
shift16R <= fills(31 downto 16) & shift8R(31 downto 16) when shift_amount(4) = '1' else shift8R;
GENERIC_SHIFTER: if shifter_type = "DEFAULT" generate
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else
shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
shift_func = SHIFT_RIGHT_SIGNED else
ZERO;
end generate;
AREA_OPTIMIZED_SHIFTER: if shifter_type /= "DEFAULT" generate
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else (others => 'Z');
c_shift <= shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
shift_func = SHIFT_RIGHT_SIGNED else (others => 'Z');
c_shift <= ZERO when shift_func = SHIFT_NOTHING else (others => 'Z');
end generate;
end; --architecture logic
| gpl-3.0 |
siavooshpayandehazad/NoC_Router | RTL/Processor_NI/shifter.vhd | 16 | 3063 | ---------------------------------------------------------------------
-- TITLE: Shifter Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- Matthias Gruenewald
-- DATE CREATED: 2/2/01
-- FILENAME: shifter.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the 32-bit shifter unit.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity shifter is
generic(shifter_type : string := "DEFAULT");
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end; --entity shifter
architecture logic of shifter is
-- type shift_function_type is (
-- shift_nothing, shift_left_unsigned,
-- shift_right_signed, shift_right_unsigned);
signal shift1L, shift2L, shift4L, shift8L, shift16L : std_logic_vector(31 downto 0);
signal shift1R, shift2R, shift4R, shift8R, shift16R : std_logic_vector(31 downto 0);
signal fills : std_logic_vector(31 downto 16);
begin
fills <= "1111111111111111" when shift_func = SHIFT_RIGHT_SIGNED
and value(31) = '1'
else "0000000000000000";
shift1L <= value(30 downto 0) & '0' when shift_amount(0) = '1' else value;
shift2L <= shift1L(29 downto 0) & "00" when shift_amount(1) = '1' else shift1L;
shift4L <= shift2L(27 downto 0) & "0000" when shift_amount(2) = '1' else shift2L;
shift8L <= shift4L(23 downto 0) & "00000000" when shift_amount(3) = '1' else shift4L;
shift16L <= shift8L(15 downto 0) & ZERO(15 downto 0) when shift_amount(4) = '1' else shift8L;
shift1R <= fills(31) & value(31 downto 1) when shift_amount(0) = '1' else value;
shift2R <= fills(31 downto 30) & shift1R(31 downto 2) when shift_amount(1) = '1' else shift1R;
shift4R <= fills(31 downto 28) & shift2R(31 downto 4) when shift_amount(2) = '1' else shift2R;
shift8R <= fills(31 downto 24) & shift4R(31 downto 8) when shift_amount(3) = '1' else shift4R;
shift16R <= fills(31 downto 16) & shift8R(31 downto 16) when shift_amount(4) = '1' else shift8R;
GENERIC_SHIFTER: if shifter_type = "DEFAULT" generate
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else
shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
shift_func = SHIFT_RIGHT_SIGNED else
ZERO;
end generate;
AREA_OPTIMIZED_SHIFTER: if shifter_type /= "DEFAULT" generate
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else (others => 'Z');
c_shift <= shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
shift_func = SHIFT_RIGHT_SIGNED else (others => 'Z');
c_shift <= ZERO when shift_func = SHIFT_NOTHING else (others => 'Z');
end generate;
end; --architecture logic
| gpl-3.0 |
LemurPwned/classic-fpga | memory/dram.vhdl | 1 | 614 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dram is
port (
clk : in std_logic;
I : in std_logic;
addr : in std_logic_vector(3 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end entity;
architecture dram of dram is
type ram_tye is array(15 downto 0) of std_logic_vector(7 dowonto 0);
signal RAM: ram_type;
begin
process(clk)
begin
if rising_edge(clk) then
if I='1' then
RAM(conv_integer(ADDR)) <= di;
end if;
end if;
end process;
do<=RAM(conv_integer(ADDR));
end architecture;
| gpl-3.0 |
LemurPwned/classic-fpga | multiplexers_registers/barrel.vhdl | 1 | 926 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity barrel is
port (
clk : in std_logic;
se : in std_logic_vector(1 downto 0);
I : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0);
Q2 : out std_logic_vector(3 downto 0)
);
end entity;
architecture arch of barrel is
signal Qt, Qt2 : std_logic_vector(3 downto 0):="0000";
begin
process(clk, se)
begin
if rising_edge(clk) then
if (se(0)='0' and se(1)='0') then
Qt<=I;
Qt2<=I;
elsif (se(0)='1' and se(1)='0') then
Qt<=I(3 downto 1)&"0";
Qt2<=I(3)&I(3 downto 1);
elsif (se(0)='0' and se(1)='1') then
Qt<=I(3 downto 2)&"00";
Qt2<=I(3)&I(3)&I(3 downto 2);
else
Qt<=I(3)&"000";
Qt2<=(others =>I(3));
end if;
end if;
end process;
Q<=Qt;
Q2<=Qt2;
end architecture;
| gpl-3.0 |
LemurPwned/classic-fpga | multiplexers_registers/multiplex_1_tb.vhdl | 1 | 1330 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplex_1_tb is
end entity;
architecture behav of multiplex_1_tb is
component multiplex_1
port (
smi : in std_logic_vector(6 downto 0);
smo : out std_logic;
se : in std_logic_vector(2 downto 0)
);
end component;
for multiplex_1_0 : multiplex_1 use entity work.multiplex_1;
signal smi : std_logic_vector (6 downto 0);
signal se : std_logic_vector (2 downto 0);
signal smo : std_logic;
begin
multiplex_1_0: multiplex_1 port map (smi=>smi, smo=>smo, se=>se);
process
begin
smi <= "1111011";
se <= "000";
wait for 5 ns;
se <= "001";
wait for 5 ns;
se <= "010";
wait for 5 ns;
se <= "011";
wait for 5 ns;
se <= "100";
wait for 5 ns;
smi <= "1110111";
se <= "000";
wait for 5 ns;
se <= "001";
wait for 5 ns;
se <= "010";
wait for 5 ns;
se <= "011";
wait for 5 ns;
se <= "100";
wait for 5 ns;
se <= "101";
wait for 5 ns;
se <= "110";
wait for 5 ns;
se <= "111";
wait for 5 ns;
smi <= "1011111";
se <= "000";
wait for 5 ns;
se <= "110";
wait for 5 ns;
se <= "010";
wait for 5 ns;
se <= "111";
wait for 5 ns;
se <= "101";
wait for 5 ns;
wait;
end process;
end architecture;
| gpl-3.0 |
LemurPwned/classic-fpga | dff.vhdl | 1 | 412 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dff is
port (
clk : in std_logic;
r : in std_logic;
D : in std_logic;
Q : out std_logic
);
end entity;
architecture behavior of dff is
begin
process(clk, r)
begin
if r = '1' then
Q <= '0';
elsif rising_edge(clk) then
Q <= D;
end if;
end process;
end architecture;
| gpl-3.0 |
jimmystelzer/8086compipelineemvhdl | processor/src/processor.vhd | 1 | 13653 | ------------------------------------------------------------------
-- Processador Intel 8086 arquiteturado em pipeline e simplificado
------------------------------------------------------------------
-- Desenvolvedores: Jimmy Pinto Stelzer, Bruno Goulart e Bruno Paes
-- Baseado no exemplo de implementação do MIPS dos professores Fernando Moraes e Ney Calazans.
------------------------------------------------------------------
------------------------
-- Definições Gerais
------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package p_intel_8086 is
type instructions is
(JMP,CMP,JZ,LOOPNZ,HLT,ADD,MOVRR,MOVRI,MOVRM,NOP);
type microinstruction is record
op: instructions; -- meneumonicos
rsCode: STD_LOGIC_VECTOR (2 downto 0);
rdCode: STD_LOGIC_VECTOR (2 downto 0);
param: STD_LOGIC_VECTOR (31 downto 0);
modc: STD_LOGIC_VECTOR (1 downto 0);
w: std_logic;
ex: std_logic;
mem: std_logic;
wb: std_logic;
end record;
end p_intel_8086;
-------------------------------------
-- Registrador do pipeline
-------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_intel_8086.all;
entity regpl is
generic( INIT_VALUE : STD_LOGIC_VECTOR(83 downto 0) := (others=>'0') );
port( clock, reset, enable : in std_logic;
D : in STD_LOGIC_VECTOR (83 downto 0);
I : in instructions;
O : out instructions;
Q : out STD_LOGIC_VECTOR (83 downto 0)
);
end regpl;
architecture regpl of regpl is
begin
process(clock, reset)
begin
if reset = '1' then
Q <= INIT_VALUE(83 downto 0);
O <= NOP;
elsif clock'event and clock = '0' then
if enable = '1' then
Q <= D;
O <= I;
end if;
end if;
end process;
end regpl;
-------------------------------------
-- Registrador de 16bits para AX, BX, CX, DX, SP, BP, SI, DI, ES, DS, SS e ES.
-------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity reg16 is
generic( INIT_VALUE : STD_LOGIC_VECTOR(15 downto 0) := (others=>'0') );
port( clock, reset, enable : in std_logic;
D : in STD_LOGIC_VECTOR (15 downto 0);
Q : out STD_LOGIC_VECTOR (15 downto 0)
);
end reg16;
architecture reg16 of reg16 is
begin
process(clock, reset)
begin
if reset = '1' then
Q <= INIT_VALUE(15 downto 0);
elsif clock'event and clock = '0' then
if enable = '1' then
Q <= D;
end if;
end if;
end process;
end reg16;
-------------------------------------
-- Banco de Registradores
-------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.p_intel_8086.all;
entity reg_bank is
port( clock, reset, enable : in std_logic;
w : in std_logic;
RsCode, RdCode : in std_logic_vector( 2 downto 0);
RD : in std_logic_vector(15 downto 0);
R1, R2: out std_logic_vector(15 downto 0));
end reg_bank;
architecture reg_bank of reg_bank is
type bank is array(0 to 7) of std_logic_vector(15 downto 0);
signal reg : bank;
begin
g1: for i in 0 to 7 generate
rx: entity work.reg16 port map(clock=>clock, reset=>reset, enable=>'1', D=>RD, Q=>reg(i));
end generate g1;
R1 <= reg(CONV_INTEGER(RsCode)) when w='1' else --AX CX DX BX SP BP SI DI
"00000000" & reg(0)(7 downto 0) when CONV_INTEGER(RsCode)=0 and w='0' else --AL
"00000000" & reg(1)(7 downto 0) when CONV_INTEGER(RsCode)=0 and w='0' else --CL
"00000000" & reg(2)(7 downto 0) when CONV_INTEGER(RsCode)=0 and w='0' else --DL
"00000000" & reg(3)(7 downto 0) when CONV_INTEGER(RsCode)=0 and w='0' else --BL
"00000000" & reg(4)(15 downto 8) when CONV_INTEGER(RsCode)=0 and w='0' else --AH
"00000000" & reg(5)(15 downto 8) when CONV_INTEGER(RsCode)=0 and w='0' else --CH
"00000000" & reg(6)(15 downto 8) when CONV_INTEGER(RsCode)=0 and w='0' else --DH
"00000000" & reg(7)(15 downto 8) when CONV_INTEGER(RsCode)=0 and w='0'; --BH
R2 <= reg(CONV_INTEGER(RdCode)) when w='1' else --AX CX DX BX SP BP SI DI
"00000000" & reg(0)(7 downto 0) when CONV_INTEGER(RdCode)=0 and w='0' else --AL
"00000000" & reg(1)(7 downto 0) when CONV_INTEGER(RdCode)=0 and w='0' else --CL
"00000000" & reg(2)(7 downto 0) when CONV_INTEGER(RdCode)=0 and w='0' else --DL
"00000000" & reg(3)(7 downto 0) when CONV_INTEGER(RdCode)=0 and w='0' else --BL
"00000000" & reg(4)(15 downto 8) when CONV_INTEGER(RdCode)=0 and w='0' else --AH
"00000000" & reg(5)(15 downto 8) when CONV_INTEGER(RdCode)=0 and w='0' else --CH
"00000000" & reg(6)(15 downto 8) when CONV_INTEGER(RdCode)=0 and w='0' else --DH
"00000000" & reg(7)(15 downto 8) when CONV_INTEGER(RdCode)=0 and w='0'; --BH
end reg_bank;
-------------------------------------
-- ULA
-------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.p_intel_8086.all;
entity alu is
port( op1, op2 : in std_logic_vector(15 downto 0);
param : in std_logic_vector(31 downto 0);
dest : out std_logic_vector(15 downto 0);
opalu : in instructions;
w : in std_logic
);
end alu;
architecture alu of alu is
signal flags : std_logic_vector(15 downto 0) := (others=>'0');
signal soma : std_logic_vector(15 downto 0) := (others=>'0');
begin
-- FLAGS
soma <= (op1+op2);
-- ZF
flags(6) <= '1' when (op2-op1)=0 and (opalu=ADD or opalu=CMP or opalu=LOOPNZ) else
'0' when (op2-op1)/=0 and (opalu=ADD or opalu=CMP or opalu=LOOPNZ);
-- SF
flags(7) <= '1' when soma<0 and opalu=ADD else
'0' when soma>0 and opalu=ADD;
-- CF
flags(0) <= '1' when soma>255 and w='0' and opalu=ADD else
'0' when soma<255 and w='0' and opalu=ADD;
-- OF
flags(11) <= '1' when (soma<-128 or (op1+op2)>127) and w='0' and opalu=ADD else
'0' when (soma>-128 and (op1+op2)<127) and w='0' and opalu=ADD;
-- AF
flags(4) <= '1' when soma>65535 and w='1' and opalu=ADD else
'0' when soma<65535 and w='1' and opalu=ADD;
-- PF
flags(2) <= '1' when CONV_INTEGER(soma) mod 2=0 and w='0' and opalu=ADD else
'0' when CONV_INTEGER(soma) mod 2/=0 and w='0' and opalu=ADD;
--(JMP,CMP,JZ,LOOPNZ,HLT,ADD,MOVRR,MOVRI,MOVRM,NOP)
dest <=
op1 + op2 when opalu=ADD else
op2 when opalu=MOVRR else
param(31 downto 16) when opalu=MOVRI else
op1 - 2 when opalu=LOOPNZ else -- CX--
(others=>'1') when opalu=JZ and flags(6)='1' else -- seta dest
(others=>'0'); --nop, hlt, cmp, movrm, jmp,
end alu;
-----------------------------------------
-- Control
-----------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use work.p_intel_8086.all;
entity control_unit is
port(clock, reset : in std_logic;
uins : out microinstruction;
ir : in std_logic_vector(39 downto 0)
);
end control_unit;
architecture control_unit of control_unit is
signal i : instructions;
signal di : std_logic;
begin
i <= MOVRI when ir(39 downto 36)="1011" else
MOVRR when ir(39 downto 34)="100010" else
ADD when ir(39 downto 34)="000000" else
CMP when ir(39 downto 34)="100000" else
MOVRM when ir(39 downto 33)="0110011" else
HLT when ir(39 downto 32)="11110100" else
LOOPNZ when ir(39 downto 32)="11100000" else
JZ when ir(39 downto 32)="01110100" else
JMP when ir(39 downto 32)="11101001" else
NOP;
uins.op <= i;
-- execution
uins.ex <= '1' when i/=NOP and i/=JMP else
'0';
-- write back
uins.wb <= '0' when i=NOP or i=HLT or i=JZ or i=CMP or i=JMP else
'1';
-- memory
uins.mem <= '1' when i=MOVRM else
'0';
-- w
uins.w <= ir(35) when i=MOVRI else
ir(32) when i=MOVRM or i=CMP or i=ADD or i=MOVRR else
--'1' when i=LOOPNZ else --?
'X'; --Unknown
-- mod
uins.modc <= ir(31 downto 30) when i=MOVRM or i=CMP or i=ADD or i=MOVRR else
"XX"; -- Unknown
-- di
di <= ir(33) when i=CMP or i=ADD or i=MOVRR else
'X';
-- rdCode
uins.rdCode <= ir(34 downto 32) when i=MOVRI else
ir(26 downto 24) when i=MOVRM or (di='1' and (i=CMP or i=ADD or i=MOVRR)) else
ir(29 downto 27) when di='0' and (i=CMP or i=ADD or i=MOVRR) else
"001" when i=LOOPNZ else
(others=>'X');
-- rsCode
uins.rsCode <= ir(26 downto 24) when i=MOVRM or (di='0' and (i=CMP or i=ADD or i=MOVRR)) else
ir(29 downto 27) when di='1' and (i=CMP or i=ADD or i=MOVRR) else
(others=>'X');
-- param -- usado para carregar as informações como offset(-low|-high), seg(-low|-high), data(-low|-high), addr(-low|-high), disp
uins.param <= "00000000" & "00000000" & "00000000" & ir(31 downto 24) when (i=JZ or i=LOOPNZ) and ir(31)='0' else
"11111111" & "11111111" & "11111111" & ir(31 downto 24) when (i=JZ or i=LOOPNZ) and ir(31)='1' else
"00000000" & "00000000" & "00000000" & ir(23 downto 16) when i=CMP and ir(23)='0' else
"11111111" & "11111111" & "11111111" & ir(23 downto 16) when i=CMP and ir(23)='1' else
"00000000" & ir(7 downto 0) & ir(15 downto 8) & ir(23 downto 16) when i=MOVRM and ir(23)='0' else
"11111111" & ir(7 downto 0) & ir(15 downto 8) & ir(23 downto 16) when i=MOVRM and ir(23)='1' else
ir(7 downto 0) & ir(15 downto 8) & ir(23 downto 16) & ir(31 downto 24) when i=MOVRI else
(others=>'X');
--39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24
--1 0 1 1 w d d d MOVRI Param(7-0 & 15-8 & 23-16 & 31-24) se w = 1 else Param(31-24)
--0 1 1 0 0 1 1 w m m s s s d d d MOVRM Param(7-0 & 15-8 & 23-16)
--1 0 0 0 0 0 di w m m s s s d d d CMP Param(23-16) se di = 0 inverte sss e ddd
--0 0 0 0 0 0 di w m m s s s d d d ADD Param() se di = 0 inverte sss e ddd
--1 0 0 0 1 0 di w m m s s s d d d MOVRR Param() se di = 0 inverte sss e ddd
--1 1 1 1 0 1 0 0 HLT
--1 1 1 0 0 0 0 0 LOOPNZ Param(31-24) | w = 1 | rd = 001
--0 1 1 1 0 1 0 0 JZ Param(31-24) | w=0
--1 1 1 0 1 0 0 1 JMP Param(7-0 & 15-8 & 23-16 & 31-24)
-- NOP
end control_unit;
---------------------------
-- BIU - Bus Interface Unit (simplificada)
---------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity biu is
port( addr : in std_logic_vector(19 downto 0); -- endereço
clock : in std_logic;
reset : in std_logic;
mode : in std_logic; -- modo -> 0 = leitura; 1 = escrita
mtype : in std_logic; -- tipo -> 0 = instruções; 1 = dados;
memc : inout std_logic_vector(0 to 1023); -- 1024bits -> 128bytes -- entrada e saida da memoria de instruções
memd : inout std_logic_vector(0 to 1023); -- 1024bits -> 128bytes -- entrada e saida da memoria de dados
datain : in std_logic_vector(39 downto 0); -- dados a serem gravados
dataout : out std_logic_vector(39 downto 0) -- dados lidos
);
end biu;
architecture biu of biu is
signal datai : std_logic_vector(39 downto 0);
signal posi : integer;
signal posf : integer;
begin
gen : process(clock,reset)
begin
if (reset = '1') then
datai <= (others=>'X');
posi <= 0;
posf <= 0;
elsif(clock'event and clock='1') then
case mtype is
when '0' => -- memoria de instruções
if mode='0' then -- leitura
posi <= CONV_INTEGER(addr);
posf <= CONV_INTEGER(addr) + 39;
datai <= memc(posi to posf);
elsif mode='1' then -- escrita
posi <= CONV_INTEGER(addr);
posf <= CONV_INTEGER(addr) + 39;
memc(posi to posf) <= datain;
end if;
when '1' => -- memoria de dados
if mode='0' then -- leitura
posi <= CONV_INTEGER(addr);
posf <= CONV_INTEGER(addr) + 39;
datai <= memd(posi to posf);
elsif mode='1' then -- escrita
posi <= CONV_INTEGER(addr);
posf <= CONV_INTEGER(addr) + 39;
memd(posi to posf) <= datain;
end if;
when others =>
datai <= (others=>'X');
end case;
end if;
end process;
dataout<= datai;
end biu;
--------------------------------
-- Chip
--------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use work.p_intel_8086.all;
entity chip is
port( clock, reset : in std_logic;
memc : inout std_logic_vector(0 to 1023); -- 1024bits -> 128bytes -- entrada e saida da memoria de instruções
memd : inout std_logic_vector(0 to 1023) -- 1024bits -> 128bytes -- entrada e saida da memoria de dados
);
end chip;
architecture chip of chip is
signal IP,addr: std_logic_vector(19 downto 0) := (others=>'0');
signal mode,mtype,wrb,walu,enablerb: std_logic := 'X';
signal datain,dataout,ir: std_logic_vector(39 downto 0) := (others=>'X');
signal uins: microinstruction;
signal opalu: instructions;
signal RD,R1,R2,op1,op2,dest : std_logic_vector(15 downto 0);
signal param : std_logic_vector(31 downto 0);
signal RsCode, RdCode : std_logic_vector(2 downto 0);
begin
biu: entity work.biu port map(addr=>addr, clock=>clock, reset=>reset, mode=>mode, mtype=>mtype, memc=>memc, memd=>memd,datain=>datain,dataout=>dataout);
ctrl: entity work.control_unit port map(clock=>clock, reset=>reset, uins=>uins, ir=>ir);
alu: entity work.alu port map(op1=>op1, op2=>op2, param=>param, dest=>dest, opalu=>opalu, w=>walu);
rb: entity work.reg_bank port map(clock=>clock, reset=>reset, enable=>enablerb, w=>wrb, RsCode=>RsCode, RdCode=>RdCode, RD=>RD, R1=>R1,R2=>R2);
--entity regpl is
-- port( clock, reset, enable : in std_logic;
-- D : in STD_LOGIC_VECTOR (83 downto 0);
-- I : in instructions;
-- O : out instructions;
-- Q : out STD_LOGIC_VECTOR (83 downto 0)
-- );
end chip; | gpl-3.0 |
Kinxil/VHDL_Projects | Mandelbrot/Iterator.vhd | 1 | 1948 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Iterator is
Port ( go : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC;
x0 : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
y0 : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
itermax : in std_logic_vector(ITER_RANGE-1 downto 0);
iters : out STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
done : out STD_LOGIC);
end Iterator;
architecture Behavioral of Iterator is
component Calc is
Port( y0 : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
x0 : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
yi : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
xi : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
yi1 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
xi1 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0));
end component;
signal xi1 : STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
signal yi1 : STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
signal xi : STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
signal yi : STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
signal cptiters : unsigned(ITER_RANGE-1 downto 0);
signal donestate : STD_LOGIC;
begin
fCalc : Calc
port map(y0=>y0,x0=>x0,yi=>yi,xi=>xi,yi1=>yi1,xi1=>xi1);
process(clock, reset, go, itermax)
begin
if reset='1' then
donestate<='1';
xi<=(others=>'0');
yi<=(others=>'0');
cptiters<=(others=>'0');
elsif rising_edge(clock) then
if ((go='1') and (donestate='1')) then --Start iteration
donestate<='0';
cptiters<=(others=>'0');
xi<=(others=>'0');
yi<=(others=>'0');
elsif((cptiters < unsigned(itermax)) and (SIGNED(mult(xi,xi,FIXED)) + SIGNED(mult(yi,yi,FIXED)) < QUATRE)) then --Still <4
xi<=xi1; --Updating values
yi<=yi1;
cptiters <= cptiters + 1;
else --computing done
donestate <= '1';
end if;
end if;
end process;
iters<=std_logic_vector(cptiters);
done<=donestate;
end Behavioral; | gpl-3.0 |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_2_CACHE_WORDS.vhd | 1 | 24067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 1;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_SubInteger.vhd | 1 | 23421 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 11;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 1;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant FADD_DELAY : integer := 11;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 4;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 |
viccuad/fpga-thingies | cronometer/debouncer.vhd | 1 | 2643 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY debouncer IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
x: IN std_logic;
xDeb: OUT std_logic;
xDebFallingEdge: OUT std_logic;
xDebRisingEdge: OUT std_logic
);
END debouncer;
ARCHITECTURE debouncerArch of debouncer is
SIGNAL xSync: std_logic;
SIGNAL startTimer, timerEnd: std_logic;
BEGIN
synchronizer:
PROCESS (rst, clk)
VARIABLE aux1: std_logic;
BEGIN
IF (rst='0') THEN
aux1 := '1';
xSync <= '1';
ELSIF (clk'EVENT AND clk='1') THEN
xSync <= aux1;
aux1 := x;
END IF;
END PROCESS synchronizer;
timer:
-- espera 50 ms para un reloj a 12.5 MHz
PROCESS (rst, clk)
CONSTANT timeOut: std_logic_vector (21 DOWNTO 0) := "1001100010010110100000";
VARIABLE count: std_logic_vector (21 DOWNTO 0);
BEGIN
IF (count=timeOut) THEN
timerEnd <= '1';
ELSE
timerEnd <= '0';
END IF;
IF (rst='0') THEN
count := timeOut;
ELSIF (clk'EVENT AND clk='1') THEN
IF (startTimer='1') THEN
count := (OTHERS=>'0');
ELSIF (timerEnd='0') THEN
count := count + 1;
END IF;
END IF;
END PROCESS timer;
controller:
PROCESS (xSync, rst, clk)
TYPE states IS (waitingPression, pressionDebouncing, waitingDepression, depressionDebouncing);
VARIABLE state: states;
BEGIN
xDeb <= '1';
xDebFallingEdge <= '0';
xDebRisingEdge <= '0';
startTimer <= '0';
CASE state IS
WHEN waitingPression =>
IF (xSync='0') THEN
xDebFallingEdge <= '1';
startTimer <= '1';
END IF;
WHEN pressionDebouncing =>
xDeb <= '0';
WHEN waitingDepression =>
xDeb <= '0';
IF (xSync='1') THEN
xDebRisingEdge <= '1';
startTimer <= '1';
END IF;
WHEN depressionDebouncing =>
NULL;
END CASE;
IF (rst='0') THEN
state := waitingPression;
ELSIF (clk'EVENT AND clk='1') THEN
CASE state IS
WHEN waitingPression =>
IF (xSync='0') THEN
state := pressionDebouncing;
END IF;
WHEN pressionDebouncing =>
IF (timerEnd='1') THEN
state := waitingDepression;
END IF;
WHEN waitingDepression =>
IF (xSync='1') THEN
state := depressionDebouncing;
END IF;
WHEN depressionDebouncing =>
IF (timerEnd='1') THEN
state := waitingPression;
END IF;
END CASE;
END IF;
END PROCESS controller;
END debouncerArch;
| gpl-3.0 |
malkadi/FGPU | RTL/cache.vhd | 1 | 12075 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
---------------------------------------------------------------------------------------------------------}}}
entity cache is -- {{{
port(
-- port a
wea : in std_logic_vector(CACHE_N_BANKS*DATA_W/8-1 downto 0);
ena : in std_logic;
addra : in unsigned(M+L-1 downto 0);
dia : in std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
doa : out std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0) := (others=>'0');
-- port b
enb, enb_be : in std_logic;
wr_fifo_rqst_addr : in cache_addr_array(N_WR_FIFOS-1 downto 0);
rd_fifo_rqst_addr : in cache_addr_array(N_AXI-1 downto 0);
wr_fifo_dout : in cache_word_array(N_WR_FIFOS-1 downto 0);
rd_fifo_din_v : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
dob : out std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0) := (others=>'0');
-- ticket signals
ticket_rqst_wr : in std_logic_vector(N_WR_FIFOS-1 downto 0);
ticket_ack_wr_fifo : out std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0');
ticket_rqst_rd : in std_logic_vector(N_AXI-1 downto 0);
ticket_ack_rd_fifo : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
-- be signals
be_rdData : out std_logic_vector (DATA_W/8*2**N-1 downto 0) := (others=>'0');
clk, nrst : in std_logic
);
end cache; -- }}}
architecture Behavioral of cache is
-- internal signals definitions {{{
signal ticket_ack_wr_fifo_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0');
signal ticket_ack_rd_fifo_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal ticket_ack_wr_fifo_i : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0');
signal ticket_ack_rd_fifo_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
-- }}}
-- constants and functions {{{
CONSTANT COL_W : natural := 8;
CONSTANT N_COL : natural := 4*2**N;
--}}}
-- cache definition {{{
type cache_bank_type is array(0 to 2**(M+L)-1) of std_logic_vector(N_COL*COL_W-1 downto 0);
shared variable cache : cache_bank_type := (others=>(others=>'0'));
-- }}}
-- port b signals & ticketing system {{{
signal addrb, addrb_n : unsigned((M+L)-1 downto 0) := (others=>'0');
signal dib, doa_n, dob_n : std_logic_vector((2**N)*DATA_W-1 downto 0) := (others=>'0');
signal web : std_logic_vector((2**N)*DATA_W/8-1 downto 0) := (others=>'0');
signal rd_fifo_din_v_p0 : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal rd_fifo_din_v_p1 : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal rd_fifo_rqst_addr_inc : unsigned((M+L)-1 downto 0) := (others=>'0');
signal rd_fifo_rqst_addr_inc_n : unsigned((M+L)-1 downto 0) := (others=>'0');
signal wr_fifo_dout_d0 : cache_word_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0'));
signal ticket_ack_vec : std_logic_vector(2**BURST_WORDS_W/CACHE_N_BANKS-1 downto 0) := (others=>'0');
signal ticket_ack_wr_vec : std_logic_vector(2**BURST_WORDS_W/CACHE_N_BANKS-1 downto 0) := (others=>'0');
signal ticket_ack_rd_vec : std_logic_vector(2**BURST_WORDS_W/CACHE_N_BANKS-1 downto 0) := (others=>'0');
signal ticket_ack_vec_d0 : std_logic_vector(2**BURST_WORDS_W/CACHE_N_BANKS-1 downto 0) := (others=>'0');
signal ticket_ack_wr_vec_d0 : std_logic_vector(2**BURST_WORDS_W/CACHE_N_BANKS-1 downto 0) := (others=>'0');
signal ticket_ack_rd_vec_d0 : std_logic_vector(2**BURST_WORDS_W/CACHE_N_BANKS-1 downto 0) := (others=>'0');
signal ticket_ack_vec_n : std_logic := '0';
signal ticket_ack_wr_vec_n : std_logic := '0';
signal ticket_ack_rd_vec_n : std_logic := '0';
signal wr_fifo_ack_indx_n : integer range 0 to N_WR_FIFOS-1 := 0;
signal wr_fifo_ack_indx : integer range 0 to N_WR_FIFOS-1 := 0;
signal wr_fifo_ack_indx_d0 : integer range 0 to N_WR_FIFOS-1 := 0;
signal rd_fifo_ack_indx_n : integer range 0 to N_AXI-1 := 0;
signal rd_fifo_ack_indx : integer range 0 to N_AXI-1 := 0;
signal rd_fifo_ack_indx_d0 : integer range 0 to N_AXI-1 := 0;
signal wr_fifo_rqst_addr_d0 : cache_addr_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0'));
signal rd_fifo_rqst_addr_d0 : cache_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
-- }}}
-- be signals{{{
type be_mem_type is array(0 to 2**(M+L)-1) of std_logic_vector(2**N*DATA_W/8-1 downto 0);
shared variable be : be_mem_type := (others=>(others=>'0'));
signal be_we : std_logic := '0';
attribute max_fanout of wr_fifo_ack_indx_d0 : signal is 60;
signal be_rdData_n : std_logic_vector (DATA_W/8*2**N-1 downto 0) := (others=>'0');
---}}}
begin
-- internal signals assignments -------------------------------------------------------------------------{{{
ticket_ack_wr_fifo <= ticket_ack_wr_fifo_i;
ticket_ack_rd_fifo <= ticket_ack_rd_fifo_i;
---------------------------------------------------------------------------------------------------------}}}
-- error handling -------------------------------------------------------------------------------------------{{{
-- assert(addra(7 downto 0) /= X"B7" or addra(8) /= '0' or wea(7 downto 4) /= X"F");
---------------------------------------------------------------------------------------------------------}}}
-- be -------------------------------------------------------------------------------------------{{{
process(clk)
begin
if rising_edge(clk) then
if ena = '1' then
-- if to_integer(addra) = 11 and wea /= (wea'range => '0') then
-- report "Address B written";
-- end if;
for j in 0 to 2**N*DATA_W/8-1 loop
if wea(j) = '1' then
be(to_integer(addra))(j) := '1';
end if;
end loop;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
be_rdData_n <= be(to_integer(addrb));
if be_we = '1' then
be(to_integer(addrb)) := (others=>'0');
end if;
if enb_be = '1' then
be_rdData <= be_rdData_n;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- cache port b control -------------------------------------------------------------------------------------------{{{
assert(ticket_ack_rd_vec = (ticket_ack_rd_vec'reverse_range=>'0') or ticket_ack_wr_vec = (ticket_ack_wr_vec'reverse_range=>'0'));
process(clk)
begin
if rising_edge(clk) then
ticket_ack_wr_fifo_i <= ticket_ack_wr_fifo_n;
ticket_ack_rd_fifo_i <= ticket_ack_rd_fifo_n;
wr_fifo_dout_d0 <= wr_fifo_dout;
ticket_ack_vec(ticket_ack_vec'high-1 downto 0) <= ticket_ack_vec(ticket_ack_vec'high downto 1);
ticket_ack_vec(ticket_ack_vec'high) <= ticket_ack_vec_n;
ticket_ack_vec_d0 <= ticket_ack_vec;
ticket_ack_wr_vec(ticket_ack_wr_vec'high-1 downto 0) <= ticket_ack_wr_vec(ticket_ack_wr_vec'high downto 1);
ticket_ack_wr_vec(ticket_ack_wr_vec'high) <= ticket_ack_wr_vec_n;
ticket_ack_wr_vec_d0 <= ticket_ack_wr_vec;
ticket_ack_rd_vec(ticket_ack_rd_vec'high-1 downto 0) <= ticket_ack_rd_vec(ticket_ack_rd_vec'high downto 1);
ticket_ack_rd_vec(ticket_ack_rd_vec'high) <= ticket_ack_rd_vec_n;
ticket_ack_rd_vec_d0 <= ticket_ack_rd_vec;
wr_fifo_ack_indx <= wr_fifo_ack_indx_n;
rd_fifo_ack_indx <= rd_fifo_ack_indx_n;
wr_fifo_ack_indx_d0 <= wr_fifo_ack_indx;
rd_fifo_ack_indx_d0 <= rd_fifo_ack_indx;
wr_fifo_rqst_addr_d0 <= wr_fifo_rqst_addr;
rd_fifo_rqst_addr_d0 <= rd_fifo_rqst_addr;
-- write path
web <= (others=>'0');
dib <= wr_fifo_dout_d0(wr_fifo_ack_indx_d0);
if ticket_ack_wr_vec_d0 /= (ticket_ack_wr_vec_d0'reverse_range => '0') then
addrb <= wr_fifo_rqst_addr_d0(wr_fifo_ack_indx_d0);
web <= (others=>'1');
end if;
-- read path
be_we <= '0';
rd_fifo_din_v_p1 <= (others=>'0');
if ticket_ack_rd_vec_d0 /= (ticket_ack_rd_vec_d0'reverse_range => '0') then
addrb <= rd_fifo_rqst_addr_inc;
rd_fifo_din_v_p1(rd_fifo_ack_indx_d0) <= '1';
be_we <= '1';
end if;
rd_fifo_din_v_p0 <= rd_fifo_din_v_p1;
rd_fifo_din_v <= rd_fifo_din_v_p0;
if nrst = '0' then
rd_fifo_rqst_addr_inc <= (others=>'0');
else
rd_fifo_rqst_addr_inc <= rd_fifo_rqst_addr_inc_n;
end if;
end if;
end process;
process(ticket_rqst_wr, ticket_rqst_rd, ticket_ack_vec, wr_fifo_ack_indx, rd_fifo_ack_indx, rd_fifo_rqst_addr_inc, rd_fifo_rqst_addr_d0, ticket_ack_rd_vec_d0)
variable wr_served: boolean := false;
begin
ticket_ack_wr_fifo_n <= (others=>'0');
ticket_ack_rd_fifo_n <= (others=>'0');
ticket_ack_vec_n <= '0';
ticket_ack_wr_vec_n <= '0';
ticket_ack_rd_vec_n <= '0';
wr_fifo_ack_indx_n <= wr_fifo_ack_indx;
rd_fifo_ack_indx_n <= rd_fifo_ack_indx;
rd_fifo_rqst_addr_inc_n <= rd_fifo_rqst_addr_inc;
if ticket_ack_rd_vec_d0(ticket_ack_rd_vec_d0'high downto 1) /= (0 to ticket_ack_rd_vec_d0'high-1 =>'0') then
rd_fifo_rqst_addr_inc_n <= rd_fifo_rqst_addr_inc + 1;
else
rd_fifo_rqst_addr_inc_n <= rd_fifo_rqst_addr_d0(rd_fifo_ack_indx);
end if;
wr_served := false;
for i in 0 to N_WR_FIFOS-1 loop
-- if ticket_rqst_wr(i) = '1' and ticket_ack_vec = (ticket_ack_vec'range=>'0') then
if ticket_rqst_wr(i) = '1' and ticket_ack_vec(ticket_ack_vec'high downto 1) = (0 to ticket_ack_vec'high-1 =>'0') then
ticket_ack_wr_fifo_n(i) <= '1';
wr_served := true;
ticket_ack_vec_n <= '1';
ticket_ack_wr_vec_n <= '1';
wr_fifo_ack_indx_n <= i;
exit;
end if;
end loop;
if wr_served = false then
for i in 0 to N_AXI-1 loop
if ticket_rqst_rd(i) = '1' and ticket_ack_vec(ticket_ack_vec'high downto 1) = (0 to ticket_ack_vec'high-1 =>'0') then
ticket_ack_rd_fifo_n(i) <= '1';
ticket_ack_vec_n <= '1';
ticket_ack_rd_vec_n <= '1';
rd_fifo_ack_indx_n <= i;
-- rd_fifo_rqst_addr_inc_n <= rd_fifo_rqst_addr(i);
exit;
end if;
end loop;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- cache mems -------------------------------------------------------------------------------------------{{{
process(clk)
begin
if rising_edge(clk) then
doa_n <= cache(to_integer(addra));
for j in 0 to N_COL-1 loop
if wea(j) = '1' then
cache(to_integer(addra))((j+1)*COL_W-1 downto j*COL_W) := dia((j+1)*COL_W-1 downto j*COL_W);
end if;
end loop;
if ena = '1' then
doa <= doa_n;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if enb = '1' then
dob <= dob_n;
end if;
dob_n <= cache(to_integer(addrb));
-- assert(web = (web'range => '0') or dib /= (dib'range => '0')) severity failure;
for j in 0 to N_COL-1 loop
if web(j) = '1' then
cache(to_integer(addrb))((j+1)*COL_W-1 downto j*COL_W) := dib((j+1)*COL_W-1 downto j*COL_W);
end if;
end loop;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
end Behavioral;
| gpl-3.0 |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_fsqrt_uitofp.vhd | 1 | 24067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 3;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd.vhd | 1 | 24067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 |
joalcava/sparcv8-monocicle | register_file.vhd | 1 | 1081 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity register_file is
Port( Wren : in STD_LOGIC;
rst : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
data : in STD_LOGIC_VECTOR (31 downto 0);
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0);
crd : out STD_LOGIC_VECTOR (31 downto 0)
);
end register_file;
architecture ArqRegFile of register_file is
type ram_type is array (0 to 39) of std_logic_vector (31 downto 0);
signal reg : ram_type := (others => x"00000000");
begin
process(rst, rs1, rs2, rd,data)
begin
if (rst = '0') then
crs1 <= reg(conv_integer(rs1 ));
crs2 <= reg(conv_integer(rs2 ));
crd <= reg(conv_integer(rd ));
if(rd /= "00000" and Wren ='1') then
reg(conv_integer(rd)) <= data;
end if;
elsif (rst='1') then
crs1 <= x"00000000";
crs2 <= x"00000000";
reg <= (others => x"00000000");
end if;
end process;
end ArqRegFile;
| gpl-3.0 |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fadd_fslt_2AXI.vhd | 1 | 24067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_fadd_fmul_fdiv_fsqrt_8_2_1_2.vhd | 1 | 24067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 8;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 1;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 |
joalcava/sparcv8-monocicle | alu.vhd | 1 | 1616 | library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
Port( carry: in STD_LOGIC;
aluop : in STD_LOGIC_VECTOR (5 downto 0);
crs1 : in STD_LOGIC_VECTOR (31 downto 0);
crs2 : in STD_LOGIC_VECTOR (31 downto 0);
r : out STD_LOGIC_VECTOR (31 downto 0)
);
end alu;
architecture ArqAlu of alu is
begin
process(aluop, crs1, crs2,carry)
begin
if (aluop="000000") or (aluop="001000") then --Add Operations
r <= crs1 + crs2;
elsif (aluop="001010") or (aluop="001011") then --AddX Operations
r<=crs1 +crs2 + carry;
elsif (aluop="000001") or (aluop="001001") then --Sub Operations
r <= crs1 - crs2 ;
elsif (aluop="001100") or (aluop="001101") then --SubX Operations
r<=crs1 - crs2 - carry;
elsif (aluop="000010") or (aluop="001110") then --Or Operations
r <= crs1 or crs2;
elsif (aluop="000011") or (aluop="001111") then --And Operations
r <= crs1 and crs2;
elsif (aluop="000101") or (aluop="010010") then --OrN Operations
r <= crs1 or not(crs2);
elsif (aluop="000100") or (aluop="010000") then --Xor Operations
r <= crs1 xor crs2;
elsif (aluop="000110") or (aluop="010001") then --AndN Operations
r <= crs1 and not(crs2);
elsif (aluop="000111") or (aluop="010011") then --Xnor Operations
r <= crs1 xnor crs2;
elsif (aluop="010100")then --SLL
r<= to_stdlogicvector(to_bitvector(crs1) SLL conv_integer(crs2));
elsif (aluop="010101")then --SRL
r<= to_stdlogicvector(to_bitvector(crs1) SRL conv_integer(crs2));
else
r<=x"00000000";
end if;
end process;
end ArqAlu;
| gpl-3.0 |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_max.vhd | 1 | 23540 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 11;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 1;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 8;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 1;
-- implement global atomic operations
constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant MAX_FPU_DELAY : integer := FSQRT_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 4;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 |
viccuad/fpga-thingies | cronometer/cronometer.vhd | 1 | 9479 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cronometer is
port (
startStop: IN std_logic;
puesta0: IN std_logic;
clk: IN std_logic;
reset: IN std_logic; --reset activo a baja!
ampliacion: IN std_logic;
rightSegs: OUT std_logic_vector(6 downto 0);
leftSegs: OUT std_logic_vector(6 downto 0);
upSegs: OUT std_logic_vector(6 downto 0);
puntoSegs1: OUT std_logic;
puntoSegs2: OUT std_logic;
puntoSegs3: OUT std_logic
);
end cronometer;
architecture Behavioral of cronometer is
component debouncer
port ( rst: IN std_logic; --reset a 1!
clk: IN std_logic;
x: IN std_logic;
xDeb: OUT std_logic;
xDebFallingEdge: OUT std_logic;
xDebRisingEdge: OUT std_logic
);
end component;
signal startStop2: std_logic;
signal puesta02: std_logic;
signal start: std_logic; -- biestable T: 1 cuando cuente, 0 cuando no cuente
signal cuentacont1: STD_LOGIC_VECTOR(23 downto 0); --contador1decima
signal fin_cuenta1: STD_LOGIC;
signal cuentacont2: STD_LOGIC_VECTOR(3 downto 0); --contador decimas de segundo
signal fin_cuenta2: STD_LOGIC;
signal cuentacont3: STD_LOGIC_VECTOR(3 downto 0); --contador unidades de segundo
signal fin_cuenta3: STD_LOGIC;
signal cuentacont4: STD_LOGIC_VECTOR(3 downto 0); --contador decenas de segundo
signal fin_cuenta4: STD_LOGIC;
signal cuentacont5: STD_LOGIC_VECTOR(3 downto 0); --contador unidades de minuto
signal fin_cuenta5: STD_LOGIC;
signal cuentacont6: STD_LOGIC_VECTOR(3 downto 0); --contador decenas de minuto
signal fin_cuenta6: STD_LOGIC;
signal senialpunto: STD_LOGIC;
signal cuenta_segs_right: STD_LOGIC_VECTOR(3 downto 0);
signal cuenta_segs_left: STD_LOGIC_VECTOR(3 downto 0);
begin
norebotes1: debouncer port map ( rst => reset,
clk => clk,
x => startStop,
xDeb => open,
xDebFallingEdge => startStop2,
xDebRisingEdge => open
);
norebotes2: debouncer port map ( rst => reset,
clk => clk,
x => puesta0,
xDeb => open,
xDebFallingEdge => puesta02,
xDebRisingEdge => open
);
contador1decima: process(reset,clk,startStop2,puesta02) --contador mod 10.000.000 (de 0 a 9.999.999)
begin
if(reset = '0')then
cuentacont1 <= (others => '0');
fin_cuenta1 <= '0';
start <= '0';
senialpunto <= '0';
elsif(clk'event and clk = '1') then
if (startStop2 = '1') then --biestable T
start <= not start;
end if;
if (puesta02 = '1') then
cuentacont1 <= (others => '0');
fin_cuenta1 <= '0';
elsif (start = '1' and cuentacont1 /= "100110001001011001111111") then
cuentacont1 <= cuentacont1 + 1;
fin_cuenta1 <= '0';
elsif (start = '1' and cuentacont1 = "100110001001011001111111") then
fin_cuenta1 <= '1';
senialpunto <= not senialpunto;
puntoSegs1 <= senialpunto;
puntoSegs2 <= senialpunto;
puntoSegs3 <= senialpunto;
cuentacont1 <= (others => '0');
end if;
if (fin_cuenta1 = '1') then
fin_cuenta1 <= '0';
end if;
end if;
end process contador1decima;
contador_decimas: process(reset,clk,puesta02,fin_cuenta1) --contador mod 10 (de 0 a 9)
begin
if(reset = '0')then
cuentacont2 <= (others => '0');
fin_cuenta2 <= '0';
elsif(clk'event and clk = '1') then
if (puesta02 = '1') then
cuentacont2 <= (others => '0');
fin_cuenta2 <= '0';
elsif (fin_cuenta1 = '1' and cuentacont2 /= "1001") then
cuentacont2 <= cuentacont2 + 1;
fin_cuenta2 <= '0';
elsif (fin_cuenta1 = '1' and cuentacont2 = "1001") then
fin_cuenta2 <= '1';
cuentacont2 <= (others => '0');
end if;
if (fin_cuenta2 = '1') then
fin_cuenta2 <= '0';
end if;
end if;
end process contador_decimas;
contador_uds_seg: process(reset,clk,puesta02,fin_cuenta2) --contador mod 10 (de 0 a 9)
begin
if(reset = '0')then
cuentacont3 <= (others => '0');
fin_cuenta3 <= '0';
elsif(clk'event and clk = '1') then
if (puesta02 = '1') then
cuentacont3 <= (others => '0');
fin_cuenta3 <= '0';
elsif (fin_cuenta2 = '1' and cuentacont3 /= "1001") then
cuentacont3 <= cuentacont3 + 1;
fin_cuenta3 <= '0';
elsif (fin_cuenta2 = '1' and cuentacont3 = "1001") then
fin_cuenta3 <= '1';
cuentacont3 <= (others => '0');
end if;
if (fin_cuenta3 = '1') then
fin_cuenta3 <= '0';
end if;
end if;
end process contador_uds_seg;
contador_decenas_seg: process(reset,clk,puesta02,fin_cuenta3) --contador mod 6 (de 0 a 5)
begin
if(reset = '0')then
cuentacont4 <= (others => '0');
fin_cuenta4 <= '0';
elsif(clk'event and clk = '1') then
if (puesta02 = '1') then
cuentacont4 <= (others => '0');
fin_cuenta4 <= '0';
elsif (fin_cuenta3 = '1' and cuentacont4 /= "0101") then
cuentacont4 <= cuentacont4 + '1';
fin_cuenta4 <= '0';
elsif (fin_cuenta3 = '1' and cuentacont4 = "0101") then
fin_cuenta4 <= '1';
cuentacont4 <= (others => '0');
end if;
if (fin_cuenta4 = '1') then
fin_cuenta4 <= '0';
end if;
end if;
end process contador_decenas_seg;
contador_uds_minuto: process(reset,clk,puesta02,fin_cuenta4) --contador mod 10 (de 0 a 9)
begin
if(reset = '0')then
cuentacont5 <= (others => '0');
fin_cuenta5 <= '0';
elsif(clk'event and clk = '1') then
if (puesta02 = '1') then
cuentacont5 <= (others => '0');
fin_cuenta5 <= '0';
elsif (fin_cuenta4 = '1' and cuentacont5 /= "1001") then
cuentacont5 <= cuentacont5 + '1';
fin_cuenta5 <= '0';
elsif (fin_cuenta4 = '1' and cuentacont5 = "1001") then
fin_cuenta5 <= '1';
cuentacont5 <= (others => '0');
end if;
if (fin_cuenta5 = '1') then
fin_cuenta5 <= '0';
end if;
end if;
end process contador_uds_minuto;
contador_decenas_minuto: process(reset,clk,puesta02,fin_cuenta5) --contador mod 6 (de 0 a 5)
begin
if(reset = '0')then
cuentacont6 <= (others => '0');
fin_cuenta6 <= '0';
elsif(clk'event and clk = '1') then
if (puesta02 = '1') then
cuentacont6 <= (others => '0');
fin_cuenta6 <= '0';
elsif (fin_cuenta5 = '1' and cuentacont6 /= "0101") then
cuentacont6 <= cuentacont6 + '1';
fin_cuenta6 <= '0';
elsif (fin_cuenta5 = '1' and cuentacont6 = "0101") then
fin_cuenta6 <= '1';
cuentacont6 <= (others => '0');
end if;
if (fin_cuenta6 = '1') then
fin_cuenta6 <= '0';
end if;
end if;
end process contador_decenas_minuto;
conv7segRight: process(cuenta_segs_right)
begin
case cuenta_segs_right is
-- gfedcba
when "0000" => rightSegs <= "0111111";
when "0001" => rightSegs <= "0000110";
when "0010" => rightSegs <= "1011011";
when "0011" => rightSegs <= "1001111";
when "0100" => rightSegs <= "1100110";
when "0101" => rightSegs <= "1101101";
when "0110" => rightSegs <= "1111101";
when "0111" => rightSegs <= "0000111";
when "1000" => rightSegs <= "1111111";
when "1001" => rightSegs <= "1100111";
when "1010" => rightSegs <= "1110111";
when "1011" => rightSegs <= "1111100";
when "1100" => rightSegs <= "0111001";
when "1101" => rightSegs <= "1011110";
when "1110" => rightSegs <= "1111001";
when "1111" => rightSegs <= "1110001";
when OTHERS => rightSegs <= "1111001"; -- error
end case;
end process;
conv7segLeft: process(cuenta_segs_left)
begin
case cuenta_segs_left is
-- gfedcba
when "0000" => leftSegs <= "0111111";
when "0001" => leftSegs <= "0000110";
when "0010" => leftSegs <= "1011011";
when "0011" => leftSegs <= "1001111";
when "0100" => leftSegs <= "1100110";
when "0101" => leftSegs <= "1101101";
when "0110" => leftSegs <= "1111101";
when "0111" => leftSegs <= "0000111";
when "1000" => leftSegs <= "1111111";
when "1001" => leftSegs <= "1100111";
when "1010" => leftSegs <= "1110111";
when "1011" => leftSegs <= "1111100";
when "1100" => leftSegs <= "0111001";
when "1101" => leftSegs <= "1011110";
when "1110" => leftSegs <= "1111001";
when "1111" => leftSegs <= "1110001";
when OTHERS => leftSegs <= "1111001"; -- error
end case;
end process;
conv7segUp: process(cuentacont2)
begin
case cuentacont2 is
-- gfedcba
when "0000" => upSegs <= "0111111";
when "0001" => upSegs <= "0000110";
when "0010" => upSegs <= "1011011";
when "0011" => upSegs <= "1001111";
when "0100" => upSegs <= "1100110";
when "0101" => upSegs <= "1101101";
when "0110" => upSegs <= "1111101";
when "0111" => upSegs <= "0000111";
when "1000" => upSegs <= "1111111";
when "1001" => upSegs <= "1100111";
when "1010" => upSegs <= "1110111";
when "1011" => upSegs <= "1111100";
when "1100" => upSegs <= "0111001";
when "1101" => upSegs <= "1011110";
when "1110" => upSegs <= "1111001";
when "1111" => upSegs <= "1110001";
when OTHERS => upSegs <= "1111001"; -- error
end case;
end process;
segunda_parte: process(ampliacion)
begin
if (ampliacion = '0') then
cuenta_segs_right <= cuentacont3;
cuenta_segs_left <= cuentacont4;
else
cuenta_segs_right <= cuentacont5;
cuenta_segs_left <= cuentacont6;
end if;
end process;
end Behavioral;
| gpl-3.0 |
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| gpl-3.0 |
viccuad/fpga-thingies | tron/tron.vhd | 1 | 25208 | -- hecho para ser visto con tab size = 3
library IEEE;
library UNISIM;
use UNISIM.vcomponents.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tron is
port (
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
clk: IN std_logic;
reset: IN std_logic; --reset activo a baja!
hSync: OUT std_logic;
Vsync: OUT std_logic;
colisionOUT: OUT std_logic;
DI2: OUT std_logic_vector(0 downto 0);
DI1: OUT std_logic_vector(0 downto 0);
segs: OUT std_logic_vector (6 downto 0);
R: OUT std_logic_vector (2 downto 0); -- alconversor D/A
G: OUT std_logic_vector (2 downto 0); -- alconversor D/A
B: OUT std_logic_vector (2 downto 0) -- alconversor D/A
);
end tron;
architecture Behavioral of tron is
component ps2KeyboardInterface
port ( clk: IN std_logic;
rst: IN std_logic;
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
data: OUT std_logic_vector (7 DOWNTO 0);
newData: OUT std_logic;
newDataAck: IN std_logic
);
end component;
--señales maquina de estados
type fsmEstados is (pulsadas, despulsadas);
signal estado: fsmEstados;
type fsmEstados2 is (jugando, parado, reseteo);
signal estado2: fsmEstados2;
--señales PS2
signal newData, newDataAck: std_logic;
signal scancode: std_logic_vector (7 downto 0);
--señales VGA
signal senialHSync, senialVSync: std_logic;
signal finPixelCont: std_logic;
signal cuentaPixelCont: std_logic_vector (10 downto 0);
signal cuentaLineCont: std_logic_vector (9 downto 0);
signal comp1, comp2, comp3, comp4, comp5, comp6: std_logic;
signal Rcoche1,Rcoche2,Restela: std_logic_vector (2 downto 0);
signal Gcoche1,Gcoche2,Gestela: std_logic_vector (2 downto 0);
signal Bcoche1,Bcoche2,Bestela: std_logic_vector (2 downto 0);
--señales juego
signal pixelCoche1Hor,pixelCoche2Hor: std_logic_vector (7 downto 0); --153 pixeles (10011001)
signal pixelCoche1Ver,pixelCoche2Ver: std_logic_vector (6 downto 0); --102 pixeles
signal movCoche1,movCoche2: std_logic_vector (1 downto 0); -- 00 = arriba , 01 = derecha , 10 = abajo , 11 = izquierda
signal ldMov1,ldMov2: std_logic;
signal moverCoches: std_logic;
signal cuenta1dec: STD_LOGIC_VECTOR(19 downto 0); --contador1decima
signal finCuenta1Dec: STD_LOGIC;
signal cuentacontReseteo: std_logic_vector(14 downto 0);
signal finCuentaContReseteo,enableContReseteo,hayColision: std_logic;
signal coche1SeMueve, coche2SeMueve,coche1SeMueve2, coche2SeMueve2: std_logic;
--señales teclas
signal teclaSPC: std_logic;
signal clTeclaSPC: std_logic;
signal ldTeclaSPC: std_logic;
--seniales memorias
signal estelaCoche1MenosSig,estelaCoche2MenosSig,estelaCoche1MasSig,estelaCoche2MasSig,DOBcoche1MenosSig,DOBcoche1MasSig,DOBcoche2MenosSig,DOBcoche2MasSig: std_logic_vector(0 downto 0);
signal selPixelPantalla: std_logic_vector (14 downto 0); -- pixeles logicos hor (120) concatenado con pixeles logicos ver (153): cuentaPixelCont(10 downto 3)++cuentaLineCont(8 downto 2)
signal selPixelCoche1,selPixelCoche2: std_logic_vector (14 downto 0); --pixelCoche1/2Hor concatenado pixelCoche1/2Ver
signal estelaMem: std_logic_vector (1 downto 0);
signal WEBmenosSig1, WEBmasSig,WEBmenosSig2, WEBmasSig2,WEcoche1,WEcoche2,senialWEA: std_logic;
signal DIBcoche1,DIBcoche2,DOBcoche1,DOBcoche2: std_logic_vector(0 downto 0);
--señales de depuracion
signal st : std_logic_vector (1 downto 0);
begin
--------------------------- RAM ------------------------------------------------
colisionOUT <= hayColision;
DI1 <= DIBcoche1;
DI2 <= DIBcoche2;
selPixelCoche1(14 downto 7) <= pixelCoche1Hor;
selPixelCoche1(6 downto 0) <= pixelCoche1Ver;
selPixelCoche2(14 downto 7) <= pixelCoche2Hor;
selPixelCoche2(6 downto 0) <= pixelCoche2Ver;
selPixelPantalla(14 downto 7) <= cuentaPixelCont(10 downto 3);
selPixelPantalla(6 downto 0) <= cuentaLineCont(8 downto 2);
--http://www.xilinx.com/itp/xilinx10/books/docs/spartan3_hdl/spartan3_hdl.pdf
rojoMenosSignif: RAMB16_S1_S1
generic map(
WRITE_MODE_B => "READ_FIRST"
)
port map (
DOA => estelaCoche1MenosSig, -- Port A 1-bit Data Output
DOB => DOBcoche1MenosSig, -- Port B 1-bit Data Output
ADDRA => selPixelPantalla(13 downto 0), -- Port A 14-bit Address Input
ADDRB => selPixelCoche1(13 downto 0), -- Port B 14-bit Address Input
CLKA => clk, -- Port A Clock
CLKB => clk, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => DIBcoche1, -- Port B 1-bit Data Input --pintamos rojo
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => senialWEA, -- Port A Write Enable Input
WEB => WEBmenosSig1 -- Port B Write Enable Input
);
rojoMasSignif: RAMB16_S1_S1
generic map(
WRITE_MODE_B => "READ_FIRST"
)
port map (
DOA => estelaCoche1MasSig, -- Port A 1-bit Data Output
DOB => DOBcoche1MasSig, -- Port B 1-bit Data Output
ADDRA => selPixelPantalla(13 downto 0), -- Port A 14-bit Address Input
ADDRB => selPixelCoche1(13 downto 0), -- Port B 14-bit Address Input
CLKA => clk, -- Port A Clock
CLKB => clk, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => DIBcoche1, -- Port B 1-bit Data Input --pintamos rojo
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => senialWEA, -- Port A Write Enable Input
WEB =>WEBmasSig -- Port B Write Enable Input
);
azulMenosSignif: RAMB16_S1_S1
generic map(
WRITE_MODE_B => "READ_FIRST"
)
port map (
DOA => estelaCoche2MenosSig, -- Port A 1-bit Data Output
DOB => DOBcoche2MenosSig, -- Port B 2-bit Data Output
ADDRA => selPixelPantalla(13 downto 0), -- Port A 14-bit Address Input
ADDRB => selPixelCoche2(13 downto 0), -- Port B 14-bit Address Input
CLKA => clk, -- Port A Clock
CLKB => clk, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => DIBcoche2, -- Port B 1-bit Data Input --pintamos azul
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => senialWEA, -- Port A Write Enable Input
WEB => WEBmenosSig2 -- Port B Write Enable Input
);
azulMasSignif: RAMB16_S1_S1
generic map(
WRITE_MODE_B => "READ_FIRST"
)
port map (
DOA => estelaCoche2MasSig, -- Port A 1-bit Data Output
DOB => DOBcoche2MasSig, -- Port B 1-bit Data Output
ADDRA => selPixelPantalla(13 downto 0), -- Port A 14-bit Address Input
ADDRB => selPixelCoche2(13 downto 0), -- Port B 14-bit Address Input
CLKA => clk, -- Port A Clock
CLKB => clk, -- Port B Clock
DIA => "0", -- Port A 1-bit Data Input
DIB => DIBcoche2, -- Port B 1-bit Data Input --pintamos azul
ENA => '1', -- Port A RAM Enable Input
ENB => '1', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => senialWEA, -- Port A Write Enable Input
WEB => WEBmasSig2 -- Port B Write Enable Input
);
WEB_MasSig2
interfazPS2: ps2KeyboardInterface port map (
rst => reset,
clk => clk,
ps2Clk => ps2Clk,
ps2Data => ps2Data,
data => scancode,
newData => newData,
newDataAck => newDataAck
);
decoSalida: process(selPixelCoche1,selPixelCoche2,selPixelPantalla,DOBcoche1MenosSig,
DOBcoche1MasSig,DOBcoche2MenosSig,DOBcoche2MasSig,WEcoche1,
WEcoche2,estelaCoche1MenosSig,estelaCoche1MasSig,estelaCoche2MenosSig,
estelaCoche2MasSig)
begin
if (selPixelPantalla(14) = '0') then
--direccionar a las menos signif
estelaMem(1 downto 1) <= estelaCoche1MenosSig;
estelaMem(0 downto 0) <= estelaCoche2MenosSig;
else
--direccionar a las mas signif
estelaMem(1 downto 1) <= estelaCoche1MasSig;
estelaMem(0 downto 0) <= estelaCoche2MasSig;
end if;
if (selPixelCoche1(14) = '0') then
--direccionar a las menos signif
WEBmenosSig1 <= WEcoche1;
WEBmasSig <= '0';
DOBcoche1 <= DOBcoche1MenosSig;
else
--direccionar a las mas signif
WEBmenosSig1 <= '0';
WEBmasSig <= WEcoche1;
DOBcoche1 <= DOBcoche1MasSig;
end if;
if (selPixelCoche2(14) = '0') then
--direccionar a las menos signif
WEBmenosSig2 <= WEcoche2;
WEBmasSig2 <= '0';
DOBcoche2 <= DOBcoche2MenosSig;
else
--direccionar a las mas signif
WEBmenosSig2 <= '0';
WEBmasSig2 <= WEcoche2;
DOBcoche2 <= DOBcoche2MasSig;
end if;
end process decoSalida;
--------------------------- PANTALLA -------------------------------------------
hSync <= senialHSync;
vSync <= senialVSync;
pantalla: process(clk, reset,cuentaPixelCont,cuentaLineCont,Rcoche1,Rcoche2,
Gcoche1,Gcoche2,Bcoche1,Bcoche2,Restela,Gestela,Bestela)
begin
--cont mod 1589 (pixelCont para sincronismo horizontal)
if (cuentaPixelCont = "11000110100") then
finPixelCont <= '1';
else
finPixelCont <= '0';
end if;
if(reset = '0')then
cuentaPixelCont <= (others => '0');
finPixelCont <= '0';
elsif(clk'event and clk = '1') then
if (cuentaPixelCont /= "11000110100") then --1588
cuentaPixelCont <= cuentaPixelCont + '1';
elsif (cuentaPixelCont = "11000110100") then
cuentaPixelCont <= (others => '0');
end if;
end if;
--cont mod 528 (lineCont para sincronismo vertical)
if(reset = '0')then
cuentaLineCont <= (others => '0');
elsif(clk'event and clk = '1') then
if (finPixelCont = '1' and cuentaLineCont /= "1000001111") then --527
cuentaLineCont <= cuentaLineCont + '1';
elsif (finPixelCont = '1' and cuentaLineCont = "1000001111") then
cuentaLineCont <= (others => '0');
end if;
end if;
--comparaciones
if (cuentaPixelCont > 1257) then comp1 <= '1'; else comp1 <= '0'; end if;
if (cuentaPixelCont > 1304) then comp2 <= '1'; else comp2 <= '0'; end if;
if (cuentaPixelCont <= 1493) then comp3 <= '1'; else comp3 <= '0'; end if;
if (cuentaLineCont > 479) then comp4 <= '1'; else comp4 <= '0'; end if;
if (cuentaLineCont > 493) then comp5 <= '1'; else comp5 <= '0'; end if;
if (cuentaLineCont <= 495) then comp6 <= '1'; else comp6 <= '0'; end if;
senialHSync <= comp2 nand comp3;
senialVSync <= comp5 nand comp6;
if (senialHSync = '0' or senialVSync = '0') then --no pinta
R <= "000";
G <= "000";
B <= "000";
else
R(2) <= ( (not (comp1 or comp4)) and (Rcoche1(2) or Rcoche2(2) or Restela(2)) );
R(1) <= ( (not (comp1 or comp4)) and (Rcoche1(1) or Rcoche2(1) or Restela(1)) );
R(0) <= ( (not (comp1 or comp4)) and (Rcoche1(0) or Rcoche2(0) or Restela(0)) );
G(2) <= ( (not (comp1 or comp4)) and (Gcoche1(2) or Gcoche2(2) or Gestela(2)) );
G(1) <= ( (not (comp1 or comp4)) and (Gcoche1(1) or Gcoche2(1) or Gestela(1)) );
G(0) <= ( (not (comp1 or comp4)) and (Gcoche1(0) or Gcoche2(0) or Gestela(0)) );
B(2) <= ( (not (comp1 or comp4)) and (Bcoche1(2) or Bcoche2(2) or Bestela(2)) );
B(1) <= ( (not (comp1 or comp4)) and (Bcoche1(1) or Bcoche2(1) or Bestela(1)) );
B(0) <= ( (not (comp1 or comp4)) and (Bcoche1(0) or Bcoche2(0) or Bestela(0)) );
end if;
end process;
------------------------------- PINTAR JUEGO ----------------------------------
-- vertical: 479 limite de pixeles visibles
-- 120 pixeles -> 479 x= (479*1)/120 = 3.99 = aprox 4
-- 1 pixeles -> x
-- horizontal: 1257 limite de pixeles visibles
-- 153 pixeles -> 1257 x= (1257*1)/153 = 8.21 = aprox 8
-- 1 pixeles -> x
pintarCoche1: process(cuentaLineCont,cuentaPixelCont,pixelCoche1Ver,pixelCoche1Hor)
begin
-- inicializacion
Rcoche1 <= "000";
Gcoche1 <= "000";
Bcoche1 <= "000";
--pintar
if ((cuentaLineCont(9 downto 2) >= pixelCoche1Ver-1 and
cuentaLineCont(9 downto 2) <= pixelCoche1Ver+1) and
(cuentaPixelCont(10 downto 3) >= pixelCoche1Hor-1 and
cuentaPixelCont(10 downto 3) <= pixelCoche1Hor+1)) then
Rcoche1 <= "111";--coche rojo
Gcoche1 <= "000";
Bcoche1 <= "000";
end if;
end process pintarCoche1;
pintarCoche2: process(cuentaLineCont,cuentaPixelCont,pixelCoche2Ver,pixelCoche2Hor)
begin
-- inicializacion
Rcoche2 <= "000";
Gcoche2 <= "000";
Bcoche2 <= "000";
--pintar
if ((cuentaLineCont(9 downto 2) >= pixelCoche2Ver-1 and
cuentaLineCont(9 downto 2) <= pixelCoche2Ver+1) and
(cuentaPixelCont(10 downto 3) >= pixelCoche2Hor-1 and
cuentaPixelCont(10 downto 3) <= pixelCoche2Hor+1)) then
Rcoche2 <= "000";
Gcoche2 <= "000";
Bcoche2 <= "111";--coche azul
end if;
end process pintarCoche2;
pintarEstelas: process(cuentaLineCont,cuentaPixelCont,estelaMem)
begin
-- inicializacion
Restela <= "000";
Gestela <= "000";
Bestela <= "000";
--pintar
case estelaMem is
when "01" => Restela <= "000"; --pintamos estela azul
Gestela <= "000";
Bestela <= "111";
when "10" => Restela <= "111"; --pintamos estela rojo
Gestela <= "000";
Bestela <= "000";
when "11" => Restela <= "111"; --las estelas se superponen
Gestela <= "000";
Bestela <= "111";
when others => Restela <= "000"; --no hay estela
Gestela <= "000";
Bestela <= "000";
end case;
end process pintarEstelas;
--#################### CONTROL JUEGO ###########################################
contadorMediaDecima: process(reset,clk,cuenta1dec) --contador mod 5.000.000 (de 0 a 4.999.999)
begin
if (cuenta1dec = "11110100001000111111") then
finCuenta1Dec <= '1';
else
finCuenta1Dec <= '0';
end if;
if(reset = '0')then
cuenta1dec <= (others => '0');
finCuenta1Dec <= '0';
elsif(clk'event and clk = '1') then
if (cuenta1dec /= "11110100001000111111") then
cuenta1dec <= cuenta1dec + 1;
elsif (cuenta1dec = "11110100001000111111") then
cuenta1dec <= (others => '0');
end if;
end if;
end process contadorMediaDecima;
coche1: process(moverCoches,finCuenta1Dec,clk,reset,movCoche1,pixelCoche1Hor,pixelCoche1Ver)
begin
coche1SeMueve <= '1';
if(finCuenta1Dec = '1' and moverCoches = '1') then
coche1SeMueve <= '1';
else
coche1SeMueve <= '0';
end if;
--vertical: cont mod 102 y horizontal: cont mod 153
if (reset = '0')then --pos inicial coche1
pixelCoche1Ver <= "0001000"; --en 9
pixelCoche1Hor <= "00000000"; --en 1
coche1SeMueve <= '0';
elsif (clk'event and clk = '1') then
if(finCuenta1Dec = '1' and moverCoches = '1') then
case movCoche1 is
when "00" => if (pixelCoche1Ver = 0) then --va hacia arriba
pixelCoche1Ver <= "1110111";
else
pixelCoche1Ver <= pixelCoche1Ver - '1';
end if;
when "10" => if (pixelCoche1Ver = 120) then --va hacia abajo
pixelCoche1Ver <= "0000000";
else
pixelCoche1Ver <= pixelCoche1Ver + '1';
end if;
when "11" => if ( pixelCoche1Hor = 0) then --va hacia izquierda
pixelCoche1Hor <= "10011000";
else
pixelCoche1Hor <= pixelCoche1Hor - '1';
end if;
when "01" => if (pixelCoche1Hor = 153) then --va hacia derecha
pixelCoche1Hor <= "00000000";
else
pixelCoche1Hor <= pixelCoche1Hor + '1';
end if;
when others => null;
end case;
end if;
if (teclaSPC = '1') then
pixelCoche1Ver <= "0001000"; --en 9
pixelCoche1Hor <= "00000000"; --en 1
end if;
end if;
end process coche1;
coche2: process(finCuenta1Dec,moverCoches,clk,reset,movCoche2,pixelCoche2Hor,pixelCoche2Ver)
begin
coche2SeMueve <= '0';
if(finCuenta1Dec = '1' and moverCoches = '1') then
coche2SeMueve <= '1';
else
coche2SeMueve <= '0';
end if;
--vertical: cont mod 102 y horizontal: cont mod 153
if (reset = '0')then --pos inicial coche2
pixelCoche2Ver <= "1101110"; --en 110
pixelCoche2Hor <= "10011000"; --en 152
coche2SeMueve <= '0';
elsif (clk'event and clk = '1') then
if(finCuenta1Dec = '1' and moverCoches = '1') then
case movCoche2 is
when "00" => if (pixelCoche2Ver = 0) then --va hacia arriba
pixelCoche2Ver <= "1110111";
else
pixelCoche2Ver <= pixelCoche2Ver - '1';
end if;
when "10" => if (pixelCoche2Ver = 120) then --va hacia abajo
pixelCoche2Ver <= "0000000";
else
pixelCoche2Ver <= pixelCoche2Ver + '1';
end if;
when "11" => if ( pixelCoche2Hor = 0) then --va hacia izquierda
pixelCoche2Hor <= "10011000";
else
pixelCoche2Hor <= pixelCoche2Hor - '1';
end if;
when "01" => if (pixelCoche2Hor = 153) then --va hacia derecha
pixelCoche2Hor <= "00000000";
else
pixelCoche2Hor <= pixelCoche2Hor + '1';
end if;
when others => null;
end case;
end if;
if (teclaSPC = '1') then
pixelCoche2Ver <= "1101110"; --en 110
pixelCoche2Hor <= "10011000"; --en 152
end if;
end if;
end process coche2;
colision: process(estelaMem,DOBcoche1,DOBcoche2,coche1SeMueve,coche2SeMueve,WEcoche1,WEcoche2)
begin
hayColision <= '0';
if (estelaMem = "11" or --chocan entre ellos
(DOBcoche1 = "1" and WEcoche1 = '1') or (DOBcoche2 = "1" and WEcoche2 = '1') --chocan consigo mismo
)then
hayColision <= '1';
else
hayColision <= '0';
end if;
end process colision;
------maquina de estados con registros de flags---------------------------------
controladorEstados: process (clk, reset, newData, scancode)
begin
if(reset = '0') then
estado <= pulsadas;
elsif (clk'event and clk = '1') then
estado <= pulsadas; -- estado por defecto, puede ser sobreescrito luego
case estado is
when pulsadas =>
estado <= pulsadas;
if (newData = '1' and scancode = "11110000") then --11110000: F0
estado <= despulsadas;
end if;
when despulsadas =>
estado <= despulsadas;
if (newData = '1') then
estado <= pulsadas;
end if;
end case;
end if;
end process;
generadorSalidaMealy: process (reset,newDataAck, scancode, estado, newData)
begin
newDataAck <= '0';
clTeclaSPC <= '0';
ldTeclaSPC <= '0';
case estado is
when pulsadas =>
if (newData = '1') then --11110000: F0
case scancode is --registros de flags:
when "00010101" => ldMov1 <= '1' ; --Q=15 arriba
when "00011100" => ldMov1 <= '1' ; --A=1C abajo
when "00011010" => ldMov1 <= '1' ; --Z=1A izq
when "00100010" => ldMov1 <= '1' ; --X=22 der
when "01001101" => ldMov2 <= '1' ; --P=4D arriba
when "01001011" => ldMov2 <= '1' ; --L=4B abajo
when "00110001" => ldMov2 <= '1' ; --N=31 izq
when "00111010" => ldMov2 <= '1' ; --M=3A der
when "00101001" => ldTeclaSPC <= '1'; clTeclaSPC <= '0'; --SPC=29
when others => null;
end case;
newDataAck <= '1';
end if;
when despulsadas =>
if (newData = '1') then
case scancode is --registros de flags:
when "00101001" => ldTeclaSPC <= '0'; clTeclaSPC <= '1'; --SPC=29
when others => null;
end case;
newDataAck <= '1';
end if;
when others => null;
end case;
end process;
--------------------------------------------------------------------------------
biestableDteclaSPC: process(reset,clk,ldTeclaSPC,clTeclaSPC)
begin
if(reset = '0')then
teclaSPC <= '0';
elsif(clk'event and clk = '1' ) then
if (clTeclaSPC = '1') then
teclaSPC <= '0';
elsif (ldTeclaSPC = '1') then
teclaSPC <= '1';
end if;
end if;
end process biestableDteclaSPC;
registroMovCoche1: process(reset,clk,ldMov1,teclaSPC,scancode)
begin
if(reset = '0')then
movCoche1 <= "01"; --hacia der
elsif(clk'event and clk = '1' ) then
if (teclaSPC = '1') then
movCoche1 <= "01"; --hacia der
elsif (ldMov1 = '1') then
case scancode is
when "00010101" => movCoche1 <= "00"; --Q=15 arriba
when "00011100" => movCoche1 <= "10"; --A=1C abajo
when "00011010" => movCoche1 <= "11"; --Z=1A izq
when "00100010" => movCoche1 <= "01"; --X=22 der
when others => null;
end case;
end if;
end if;
end process registroMovCoche1;
registroMovCoche2: process(reset,clk,ldMov2,teclaSPC,scancode)
begin
if(reset = '0')then
movCoche2 <= "11"; --hacia der
elsif(clk'event and clk = '1' ) then
if (teclaSPC = '1') then
movCoche2 <= "11"; --hacia der
elsif (ldMov2 = '1') then
case scancode is
when "01001101" => movCoche2 <= "00"; --P=4D arriba
when "01001011" => movCoche2 <= "10"; --L=4B abajo
when "00110001" => movCoche2 <= "11"; --N=31 izq
when "00111010" => movCoche2 <= "01"; --M=3A der
when others => null;
end case;
end if;
end if;
end process registroMovCoche2;
-----maquina de estados del juego ----------------------------------------------
controladorEstados2: process (clk, reset, finCuentaContReseteo, hayColision, teclaSPC, finCuenta1Dec)
begin
if(reset = '0') then
estado2 <= jugando;
elsif (clk'event and clk = '1') then
estado2 <= jugando; -- estado por defecto, puede ser sobreescrito luego
case estado2 is
when jugando =>
estado2 <= jugando;
if (hayColision = '1') then
estado2 <= parado;
elsif (teclaSPC = '1') then
estado2 <= reseteo;
end if;
when parado =>
estado2 <= parado;
if (teclaSPC = '1') then
estado2 <= reseteo;
end if;
when reseteo =>
estado2 <= reseteo;
if (finCuentaContReseteo = '1') then
estado2 <= jugando;
end if;
end case;
end if;
end process;
generadorSalidaMoore2: process (estado2)
begin
DIBcoche1 <= "1";
DIBcoche2 <= "1";
enableContReseteo <= '0';
moverCoches <= '1';
st <= "00";
senialWEA <= '0';
case estado2 is
when jugando =>
DIBcoche1 <= "1";
DIBcoche2 <= "1";
enableContReseteo <= '0';
moverCoches <= '1';
st <= "00";
senialWEA <= '0';
when parado =>
DIBcoche1 <= "0";
DIBcoche2 <= "0";
enableContReseteo <= '0';
moverCoches <= '0';
st <= "01";
senialWEA <= '0';
when reseteo =>
DIBcoche1 <= "0";
DIBcoche2 <= "0";
enableContReseteo <= '1';
moverCoches <= '0';
st <= "10";
senialWEA <= '1';
when others => null;
end case;
end process;
conversor7seg: process(st)
begin
case st is
--gfedcba
when "00" => segs <= "0111111";
when "01" => segs <= "0000110";
when "10" => segs <= "1011011";
when OTHERS => segs <= "1111001"; -- error
end case;
end process;
--------------------------------------------------------------------------------
contReseteo: process(reset,clk,cuentacontReseteo,enableContReseteo) --contador mod 2^15=32768 (120 x 153 pixeles)
begin
if (cuentacontReseteo = "111111111111111") then
finCuentaContReseteo <= '1';
else
finCuentaContReseteo <= '0';
end if;
if(reset = '0')then
cuentacontReseteo <= (others => '0');
finCuentaContReseteo <= '0';
elsif(clk'event and clk = '1') then
if(enableContReseteo = '1') then
if (cuentacontReseteo /= "111111111111111") then
cuentacontReseteo <= cuentacontReseteo + 1;
end if;
elsif (enableContReseteo = '0') then
cuentacontReseteo <= (others => '0');
end if;
end if;
end process contReseteo;
biestableDcoche1SeMueveRetrasa1ciclo: process(reset,clk,coche1SeMueve) --con estos biestablesD conseguimos escribir sólo una vez en memoria por cada movimiento de coche
begin
if(reset = '0')then
coche1SeMueve2 <= '0';
elsif(clk'event and clk = '1' ) then
coche1SeMueve2 <= coche1SeMueve;
end if;
end process biestableDcoche1SeMueveRetrasa1ciclo;
biestableDcoche2SeMueveRetrasa1ciclo: process(reset,clk,coche2SeMueve)
begin
if(reset = '0')then
coche2SeMueve2 <= '0';
elsif(clk'event and clk = '1' ) then
coche2SeMueve2 <= coche2SeMueve;
end if;
end process biestableDcoche2SeMueveRetrasa1ciclo;
biestableDWEcoche1: process(reset,clk,coche1SeMueve2) --con estos biestablesD conseguimos escribir sólo una vez en memoria por cada movimiento de coche
begin
if(reset = '0')then
WEcoche1 <= '0';
elsif(clk'event and clk = '1' ) then
WEcoche1 <= coche1SeMueve2;
end if;
end process biestableDWEcoche1;
biestableDWEcoche2: process(reset,clk,coche2SeMueve2)
begin
if(reset = '0')then
WEcoche2 <= '0';
elsif(clk'event and clk = '1' ) then
WEcoche2 <= coche2SeMueve2;
end if;
end process biestableDWEcoche2;
end Behavioral;
| gpl-3.0 |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_8CUs_fslt_4CACHE_WORDS.vhd | 1 | 24067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 2;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 |
Kinxil/VHDL_Projects | Mandelbrot/Zoom.vhd | 1 | 1975 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Zoom is
Port ( bleft : in STD_LOGIC;
bright : in STD_LOGIC;
bup : in STD_LOGIC;
bdwn : in STD_LOGIC;
bctr : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC;
ce_param : in std_logic;
x_start : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0);
y_start : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0);
step : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0));
end Zoom;
architecture Behavioral of Zoom is
signal s_xstart, s_ystart, s_step : signed(XY_RANGE-1 downto 0);
begin
process(clock, ce_param, reset, bup, bdwn, bleft, bright, bctr)
begin
if reset = '1' then
s_xstart <= x"E0000000";
s_ystart <= x"F0000000";
s_step <= x"00111111"; --Mandelbrot -2 1 x -1 1 sur 640x480
elsif ((rising_edge(clock)) and (ce_param='1')) then -- TODO : Centrer le zoom
if bctr = '1' then
if bup = '1' then
s_xstart <= s_xstart + (mult(s_step srl 2,x"28000000",FIXED) sll 8);
s_ystart <= s_ystart + (mult(s_step srl 2,x"1E000000",FIXED) sll 8);
s_step <= s_step srl 1; --Zoom x2> réduction du step
elsif bdwn = '1' then
s_xstart <= s_xstart + not (mult(s_step srl 1,x"28000000",FIXED) sll 8) + 1;
s_ystart <= s_ystart + not (mult(s_step srl 1,x"1E000000",FIXED) sll 8) +1;
s_step <= s_step sll 1; --Dezoom x0.5> augmentation du step
end if;
elsif bup = '1' then
s_ystart <= s_ystart + (s_step sll 7);
elsif bdwn = '1' then
s_ystart <= s_ystart - (s_step sll 7);
end if;
if bleft = '1' then
s_xstart <= s_xstart + (s_step sll 7);
elsif bright = '1' then
s_xstart <= s_xstart - (s_step sll 7);
end if;
end if;
end process;
x_start <= STD_LOGIC_VECTOR(s_xstart);
y_start <= STD_LOGIC_VECTOR(s_ystart);
step <= STD_LOGIC_VECTOR(s_step);
end Behavioral;
| gpl-3.0 |
joalcava/sparcv8-monocicle | TBSP8.vhd | 1 | 2126 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:40:11 11/09/2016
-- Design Name:
-- Module Name: C:/Users/Personal/Downloads/sparcv8-monocicle-master/TBSP8.vhd
-- Project Name: monocicle-sparcv8
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Sparcv8Monocicle
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TBSP8 IS
END TBSP8;
ARCHITECTURE behavior OF TBSP8 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Sparcv8Monocicle
PORT(
CLK : IN std_logic;
RST : IN std_logic;
R : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal R : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Sparcv8Monocicle PORT MAP (
CLK => CLK,
RST => RST,
R => R
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RST <= '1';
wait for CLK_period;
RST <= '0';
wait ;
wait;
end process;
END;
| gpl-3.0 |
malkadi/FGPU | bitstreams/settings_and_utilization/V2_4CUs_area_estimation.vhd | 2 | 24067 | -- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
| gpl-3.0 |
malkadi/FGPU | RTL/CV.vhd | 1 | 34021 | -- libraries -------------------------------------------------------------------------------------------{{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
---------------------------------------------------------------------------------------------------------}}}
entity CV is -- {{{
port(
-- CU Scheduler signals
instr : in std_logic_vector(DATA_W-1 downto 0); -- level 0.
wf_indx, wf_indx_in_wg : in natural range 0 to N_WF_CU-1; -- level 0.
phase : in unsigned(PHASE_W-1 downto 0); -- level 0.
alu_en_divStack : in std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 2.
-- RTM signals
rdAddr_alu_en : out unsigned(N_WF_CU_W+PHASE_W-1 downto 0) := (others=>'0'); -- level 2.
rdData_alu_en : in std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 4.
rtm_rdAddr : out unsigned(RTM_ADDR_W-1 downto 0) := (others => '0'); -- level 13.
rtm_rdData : in unsigned(RTM_DATA_W-1 downto 0); -- level 15.
-- gmem signals
gmem_re, gmem_we : out std_logic := '0'; -- level 17.
mem_op_type : out std_logic_vector(2 downto 0) := (others=>'0'); --level 17.
mem_addr : out GMEM_ADDR_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- level 17.
mem_rd_addr : out unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); -- level 17.
mem_wrData : out SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); --level 17.
alu_en : out std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 17.
alu_en_pri_enc : out integer range 0 to CV_SIZE-1 := 0; -- level 17.
lmem_rqst, lmem_we : out std_logic := '0'; -- level 17.
gmem_atomic : out std_logic := '0'; -- level 17.
--branch
wf_is_branching : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); -- level 18.
alu_branch : out std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 18.
mem_regFile_wrAddr : in unsigned(REG_FILE_W-1 downto 0); -- stage -1 (stable for 3 clock cycles)
mem_regFile_we : in std_logic_vector(CV_SIZE-1 downto 0); -- stage 0 (stable for 2 clock cycles) (level 20. for loads from lmem)
mem_regFile_wrData : in SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- stage 0 (stabel for 2 clock cycles)
lmem_regFile_we_p0 : in std_logic := '0'; -- level 19.
clk : in std_logic
);
attribute max_fanout of wf_indx : signal is 10;
end CV; -- }}}
architecture Behavioral of CV is
-- signals definitions -------------------------------------------------------------------------------------- {{{
----------------- RTM & Initial ALU enable
type rtm_rdAddr_vec_type is array (natural range <>) of unsigned(RTM_ADDR_W-1 downto 0);
signal rtm_rdAddr_vec : rtm_rdAddr_vec_type(9 downto 0) := (others=>(others=>'0'));
signal rdData_alu_en_vec : alu_en_vec_type(MAX_FPU_DELAY+6 downto 0) := (others=>(others=>'0'));
signal rtm_rdData_d0 : unsigned(RTM_DATA_W-1 downto 0);
signal alu_en_divStack_vec : alu_en_vec_type(2 downto 0) := (others=>(others=>'0'));
signal rdAddr_alu_en_p0 : unsigned(N_WF_CU_W+PHASE_W-1 downto 0) := (others=>'0');
----------------- global use
signal phase_d0, phase_d1 : unsigned( PHASE_W-1 downto 0) := (others=>'0');
signal op_arith_shift, op_arith_shift_n : op_arith_shift_type := op_add;
------------------ decoding
signal family : std_logic_vector(FAMILY_W-1 downto 0) := (others=>'0');
signal code : std_logic_vector(CODE_W-1 downto 0) := (others=>'0');
signal inst_rd_addr, inst_rs_addr : std_logic_vector(WI_REG_ADDR_W-1 downto 0) := (others=>'0');
signal inst_rt_addr : std_logic_vector(WI_REG_ADDR_W-1 downto 0) := (others=>'0');
type dim_vec_type is array (natural range <>) of std_logic_vector(1 downto 0);
signal dim_vec : dim_vec_type(1 downto 0) := (others=>(others=>'0'));
signal dim : std_logic_vector(1 downto 0) := (others=>'0');
type params_vec_type is array (natural range <>) of std_logic_vector(N_PARAMS_W-1 downto 0);
signal params_vec : params_vec_type(1 downto 0) := (others=>(others=>'0'));
signal params : std_logic_vector(N_PARAMS_W-1 downto 0) := (others=>'0');
type family_vec_type is array(natural range <>) of std_logic_vector(FAMILY_W-1 downto 0);
signal family_vec : family_vec_type(MAX_FPU_DELAY+10 downto 0) := (others=>(others=>'0'));
signal family_vec_at_16 : std_logic_vector(FAMILY_W-1 downto 0) := (others=>'0'); -- this signal is extracted out of family_vec to dcrease the fanout @family_vec(..@16)
attribute max_fanout of family_vec_at_16: signal is 40;
signal branch_on_zero : std_logic := '0';
signal branch_on_not_zero : std_logic := '0';
signal wf_is_branching_p0 : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0');
signal code_vec : code_vec_type(15 downto 0) := (others=>(others=>'0'));
type immediate_vec_type is array(natural range <>) of std_logic_vector(IMM_W-1 downto 0);
signal immediate_vec : immediate_vec_type(5 downto 0) := (others=>(others=>'0'));
type wf_indx_array is array (natural range <>) of natural range 0 to N_WF_CU-1;
signal wf_indx_vec : wf_indx_array(15 downto 0) := (others=>0);
signal wf_indx_in_wg_vec : wf_indx_array(1 downto 0) := (others=>0);
------------------ register file
signal rs_addr, rt_addr, rd_addr : unsigned(REG_FILE_BLOCK_W-1 downto 0) := (others=>'0');
type op_arith_shift_vec_type is array(natural range <>) of op_arith_shift_type;
signal op_arith_shift_vec : op_arith_shift_vec_type(4 downto 0) := (others => op_add);
signal op_logical_v : std_logic := '0';
signal regBlock_re : std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0');
-- attribute max_fanout of regBlock_re : signal is 10;
signal regBlocK_re_n : std_logic := '0';
signal reg_we_alu, reg_we_alu_n : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0');
signal reg_we_float : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0');
signal res_alu : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
type rd_out_vec_type is array (natural range <>) of slv32_array(CV_SIZE-1 downto 0);
signal rd_out_vec : rd_out_vec_type(6 downto 0) := (others=>(others=>(others=>'0')));
------------------ global memory
signal gmem_re_p0, gmem_we_p0 : std_logic := '0';
signal gmem_ato_p0 : std_logic := '0';
-------------------------------------------------------------------------------------}}}
-- write back into regFiles {{{
type regBlock_we_vec_type is array(natural range <>) of std_logic_vector(N_REG_BLOCKS-1 downto 0);
signal regBlock_we : regBlock_we_vec_type(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal regBlock_we_alu : std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0');
attribute max_fanout of regBlock_we_alu : signal is 50;
signal regBlock_we_mem : std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0');
signal wrAddr_regFile_vec : reg_addr_array(MAX_FPU_DELAY+12 downto 0) := (others=>(others=>'0'));
signal regBlock_wrAddr : reg_file_block_array(N_REG_BLOCKS-1 downto 0) := (others=>(others=>'0'));
signal wrData_alu : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
type regBlock_wrData_type is array(natural range <>) of slv32_array(N_REG_BLOCKS-1 downto 0);
signal regBlock_wrData : regBlock_wrData_type(CV_SIZE-1 downto 0) := (others=>(others=>(others=>'0')));
signal rtm_rdData_nlid_vec : std_logic_vector(3 downto 0) := (others=>'0');
signal res_low : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal res_alu_clk2x_d0 : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal res_high : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal reg_we_mov_vec : alu_en_vec_type(6 downto 0) := (others=>(others=>'0'));
signal mem_regFile_wrAddr_d0 : unsigned(REG_FILE_W-1 downto 0);
signal lmem_regFile_we : std_logic := '0';
-- }}}
-- floating point {{{
signal float_a, float_b : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal res_float : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal res_float_d0 : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal res_float_d1 : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0'));
signal regBlock_we_float_vec : regBlock_we_vec_type(MAX_FPU_DELAY-7 downto 0) := (others=>(others=>'0'));
signal regBlock_we_float : std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0');
attribute max_fanout of regBlock_we_float : signal is 50;
-- }}}
begin
-- internal signals and asserts -------------------------------------------------------------------------{{{
---------------------------------------------------------------------------------------------------------}}}
-- RTM contorl & ALU enable -------------------------------------------------------------------- {{{
process(clk)
begin
if rising_edge(clk) then
-- rtm {{{
rtm_rdData_d0 <= rtm_rdData; -- @ 16.
if family_vec(family_vec'high-1) = RTM_FAMILY then -- level 2.
case code_vec(code_vec'high-1) is -- level 2.
when LID =>
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '0'; -- @ 3.
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= unsigned(dim_vec(dim_vec'high-1)); --dimension
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= to_unsigned(wf_indx_in_wg_vec(wf_indx_in_wg_vec'high-1), N_WF_CU_W);
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1 downto 0) <= phase_d1;
when WGOFF =>
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3.
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= unsigned(dim_vec(dim_vec'high-1)); --dimension
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= to_unsigned(wf_indx_vec(wf_indx_vec'high-1), N_WF_CU_W);
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1 downto 0) <= (others=>'0');
when SIZE =>
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3.
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= (others=>'1');
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'0', others=>'1');
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1) <= '0';
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-2 downto 0) <= unsigned(dim_vec(dim_vec'high-1));
when WGID =>
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3.
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= (others=>'1');
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0');
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1) <= '0';
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-2 downto 0) <= unsigned(dim_vec(dim_vec'high-1));
when WGSIZE =>
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3.
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= (others=>'1');
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0');
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1) <= '0';
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-2 downto 0) <= unsigned(dim_vec(dim_vec'high-1));
when LP =>
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3.
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; --dimension
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto N_PARAMS_W) <= (others=>'0'); -- wf_indx is zero, except its LSB,
rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_PARAMS_W-1 downto 0) <= unsigned(params_vec(params_vec'high-1)); -- @ 2.
when others =>
end case;
end if;
rtm_rdAddr_vec(rtm_rdAddr_vec'high-1 downto 0) <= rtm_rdAddr_vec(rtm_rdAddr_vec'high downto 1); -- @ 4.->12.
rtm_rdAddr <= rtm_rdAddr_vec(0); -- @ 13.
rtm_rdData_nlid_vec(rtm_rdData_nlid_vec'high-1 downto 0) <= rtm_rdData_nlid_vec(rtm_rdData_nlid_vec'high downto 1); -- @ 14.->16.
rtm_rdData_nlid_vec(rtm_rdData_nlid_vec'high) <= rtm_rdAddr_vec(0)(RTM_ADDR_W-1); -- @ 13.
-- }}}
-- ALU enable {{{
rdAddr_alu_en_p0(PHASE_W-1 downto 0) <= phase; --@ 1.
rdAddr_alu_en_p0(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= to_unsigned(wf_indx_in_wg, N_WF_CU_W); --@ 1.
rdAddr_alu_en <= rdAddr_alu_en_p0; -- @ 2.
alu_en_divStack_vec(alu_en_divStack_vec'high) <= alu_en_divStack; -- @ 3.
alu_en_divStack_vec(alu_en_divStack_vec'high-1 downto 0) <= alu_en_divStack_vec(alu_en_divStack_vec'high downto 1); -- @ 4.->5.
rdData_alu_en_vec(rdData_alu_en_vec'high) <= rdData_alu_en; -- @ 5.
rdData_alu_en_vec(rdData_alu_en_vec'high-1) <= rdData_alu_en_vec(rdData_alu_en_vec'high) and not alu_en_divStack_vec(0); -- @ 6.
rdData_alu_en_vec(rdData_alu_en_vec'high-2 downto 0) <= rdData_alu_en_vec(rdData_alu_en_vec'high-1 downto 1); -- @ 7.->7+MAX_FPU_DELAY+4.
-- for gmem operations
alu_en <= rdData_alu_en_vec(rdData_alu_en_vec'high-11); -- @ 17.
alu_en_pri_enc <= 0; -- @ 17.
for i in CV_SIZE-1 downto 0 loop
if rdData_alu_en_vec(rdData_alu_en_vec'high-11)(i) = '1' then -- level 16.
alu_en_pri_enc <= i; -- @ 17.
end if;
end loop;
-- }}}
end if;
end process;
----------------------------------------------------------------------------------------------}}}
-- decoding logic --------------------------------------------------------------------{{{
family <= instr(FAMILY_POS+FAMILY_W-1 downto FAMILY_POS); -- alias
code <= instr(CODE_POS+CODE_W-1 downto CODE_POS); -- alias
inst_rd_addr <= instr(RD_POS+WI_REG_ADDR_W-1 downto RD_POS); -- alias
inst_rs_addr <= instr(RS_POS+WI_REG_ADDR_W-1 downto RS_POS); -- alias
inst_rt_addr <= instr(RT_POS+WI_REG_ADDR_W-1 downto RT_POS); -- alias
dim <= instr(DIM_POS+1 downto DIM_POS);
params <= instr(PARAM_POS+N_PARAMS_W-1 downto PARAM_POS);
process(clk)
begin
if rising_edge(clk) then
-- pipes {{{
family_vec(family_vec'high-1 downto 0) <= family_vec(family_vec'high downto 1); -- @ 2.->2+MAX_FPU_DELAY+9.
family_vec(family_vec'high) <= family; -- @ 1.
family_vec_at_16 <= family_vec(family_vec'high-14); -- @ 16.
dim_vec(dim_vec'high-1 downto 0) <= dim_vec(dim_vec'high downto 1); -- @ 2
dim_vec(dim_vec'high) <= dim; -- @ 1.
code_vec(code_vec'high-1 downto 0) <= code_vec(code_vec'high downto 1); -- @ 2.->16.
code_vec(code_vec'high) <= code; -- @ 1.
params_vec(params_vec'high-1 downto 0) <= params_vec(params_vec'high downto 1); -- @ 2.->2.
params_vec(params_vec'high) <= params; -- @ 1.
immediate_vec(immediate_vec'high-1 downto 0) <= immediate_vec(immediate_vec'high downto 1); -- @ 2.->6.
immediate_vec(immediate_vec'high)(IMM_ARITH_W-1 downto 0) <= instr(IMM_POS+IMM_ARITH_W-1 downto IMM_POS); -- @ 1.
immediate_vec(immediate_vec'high)(IMM_W-1 downto IMM_ARITH_W) <= instr(RS_POS+IMM_W-IMM_ARITH_W-1 downto RS_POS); -- @ 1.
wf_indx_vec(wf_indx_vec'high-1 downto 0) <= wf_indx_vec(wf_indx_vec'high downto 1); -- @ 2.->16.
wf_indx_vec(wf_indx_vec'high) <= wf_indx; -- @ 1.
wf_indx_in_wg_vec(wf_indx_in_wg_vec'high-1 downto 0) <= wf_indx_in_wg_vec(wf_indx_in_wg_vec'high downto 1); -- @ 2.->2.
wf_indx_in_wg_vec(wf_indx_in_wg_vec'high) <= wf_indx_in_wg; -- @ 1.
regBlock_re(0) <= regBlock_re_n; -- @ 1.
regBlock_re(regBlock_re'high downto 1) <= regBlock_re(regBlock_re'high-1 downto 0); -- @ 2.->4.
op_arith_shift <= op_arith_shift_n; -- @ 1.
op_arith_shift_vec(op_arith_shift_vec'high-1 downto 0) <= op_arith_shift_vec(op_arith_shift_vec'high downto 1); -- @ 3.->6.
op_arith_shift_vec(op_arith_shift_vec'high) <= op_arith_shift; -- @ 2.
phase_d0 <= phase; -- @ 1.
phase_d1 <= phase_d0; -- @ 2.
-- }}}
-- Rs, Rt & Rd addresses {{{
rs_addr(REG_FILE_BLOCK_W-1) <= phase(PHASE_W-1); -- @1.
rs_addr(WI_REG_ADDR_W+N_WF_CU_W-1 downto WI_REG_ADDR_W) <= to_unsigned(wf_indx, N_WF_CU_W); -- @1.
if family = ADD_FAMILY and code(3) = '1'then -- level 0.
rs_addr(WI_REG_ADDR_W-1 downto 0) <= (others=>'0'); -- @1. -- for li & lui
else
rs_addr(WI_REG_ADDR_W-1 downto 0) <= unsigned(inst_rs_addr); -- @1.
end if;
rt_addr(REG_FILE_BLOCK_W-1) <= phase(PHASE_W-1); -- @1.
rt_addr(WI_REG_ADDR_W+N_WF_CU_W-1 downto WI_REG_ADDR_W) <= to_unsigned(wf_indx, N_WF_CU_W); -- @1.
rt_addr(WI_REG_ADDR_W-1 downto 0) <= unsigned(inst_rt_addr); -- @1.
rd_addr <= wrAddr_regFile_vec(wrAddr_regFile_vec'high)(REG_FILE_BLOCK_W-1 downto 0); -- @1.
-- }}}
-- set operation type {{{
op_logical_v <= '0'; -- @ 14.
if family_vec(family_vec'high-12) = LGK_FAMILY then -- level 13.
op_logical_v <= '1'; -- @ 14.
end if;
-- }}}
end if;
end process;
-- memory accesses {{{
process(clk)
begin
if rising_edge(clk) then
-- pipes {{{
rd_out_vec(rd_out_vec'high-1 downto 0) <= rd_out_vec(rd_out_vec'high downto 1); -- @ 11.->16.
-- }}}
-- @ 16 {{{
gmem_re_p0 <= '0'; -- @ 16.
gmem_we_p0 <= '0'; -- @ 16.
if family_vec(family_vec'high-14) = GLS_FAMILY then -- level 15.
if code_vec(1)(3) = '1' then -- level 15.
gmem_re_p0 <= '0'; -- store @ 16.
gmem_we_p0 <= '1';
else
gmem_re_p0 <= '1'; -- load @ 16.
gmem_we_p0 <= '0';
end if;
end if;
if ATOMIC_IMPLEMENT /= 0 then
gmem_ato_p0 <= '0';
if family_vec(family_vec'high-14) = ATO_FAMILY then -- level 15.
gmem_ato_p0 <= '1'; -- @ 16.
end if;
end if;
-- }}}
-- @ 17 {{{
gmem_we <= gmem_we_p0; -- @ 17.
gmem_re <= gmem_re_p0; -- @ 17.
if ATOMIC_IMPLEMENT /= 0 then
gmem_atomic <= gmem_ato_p0; -- @ 17.
end if;
if LMEM_IMPLEMENT /= 0 then
lmem_rqst <= '0'; -- @ 17.
lmem_we <= '0'; -- @ 17.
if family_vec(family_vec'high-15) = LSI_FAMILY then -- level 16.
lmem_rqst <= '1'; -- @ 17.
if code_vec(0)(3) = '1' then -- level 16.
lmem_we <= '1'; -- @ 17.
else
lmem_we <= '0'; -- @ 17.
end if;
end if;
end if;
mem_wrData <= rd_out_vec(0); -- @ 17.
mem_rd_addr <= wrAddr_regFile_vec(wrAddr_regFile_vec'high-16); -- @ 17.
for i in 0 to CV_SIZE-1 loop
mem_addr(i) <= unsigned(res_low(i)(GMEM_ADDR_W-1 downto 0)); -- @ 17.
end loop;
mem_op_type <= code_vec(0)(2 downto 0); -- @ 17.
-- }}}
end if;
end process;
-- }}}
------------------------------------------------------------------------------------------------}}}
-- ALUs ----------------------------------------------------------------------------------------- {{{
ALUs: for i in 0 to CV_SIZE-1 generate
begin
-- the calculation begins @ level 3 in the pipeline
alu_inst: entity ALU port map(
rs_addr => rs_addr, --level 1.
rt_addr => rt_addr, -- level 1.
rd_addr => rd_addr, -- level 1.
family => family_vec(family_vec'high), -- level 1.
regBlock_re => regBlock_re, -- level 1.
op_arith_shift => op_arith_shift_vec(0), -- level 6.
code => code_vec(code_vec'high-5), -- level 6.
immediate => immediate_vec(0), -- level 6.
rd_out => rd_out_vec(rd_out_vec'high)(i), -- level 10.
reg_we_mov => reg_we_mov_vec(reg_we_mov_vec'high)(i), -- level 10.
float_a => float_a(i), -- level 9.
float_b => float_b(i), -- level 9.
op_logical_v => op_logical_v, -- level 14.
res_low => res_low(i), -- level 16.
res_high => res_high(i), -- level 16.
reg_wrData => regBlock_wrData(i), -- level 18. (level 21. for loads from lmem) (level 24. for float results)
reg_wrAddr => regBlock_wrAddr, -- level 18. (level 21. for loads from lmem) (level 24. for float results)
reg_we => regBlock_we(i), -- level 18. (level 21. for loads from lmem) (level 24. for float results)
clk => clk
);
end generate;
-- set register files read enables {{{
set_register_re:process(phase(0), family) -- this process executes in level 0.
begin
regBlock_re_n <= '0'; -- level 0.
case family is -- level 0.
when ADD_FAMILY | MUL_FAMILY | BRA_FAMILY | SHF_FAMILY | LGK_FAMILY | CND_FAMILY | MOV_FAMILY | LSI_FAMILY | FLT_FAMILY | GLS_FAMILY | ATO_FAMILY=>
if phase(PHASE_W-2 downto 0) = (0 to PHASE_W-2=>'0') then -- phase = 0 or 4
regBlock_re_n <= '1';
end if;
when others =>
end case; -- }}}
-- set opertion type {{{
op_arith_shift_n <= op_add; -- level 0.
case family is -- level 0.
when ADD_FAMILY =>
op_arith_shift_n <= op_add;
when MUL_FAMILY =>
op_arith_shift_n <= op_mult;
when GLS_FAMILY =>
op_arith_shift_n <= op_lw;
when LSI_FAMILY =>
op_arith_shift_n <= op_lmem;
when ATO_FAMILY =>
op_arith_shift_n <= op_ato;
when BRA_FAMILY =>
op_arith_shift_n <= op_bra;
when SHF_FAMILY =>
op_arith_shift_n <= op_shift;
when CND_FAMILY =>
op_arith_shift_n <= op_slt;
when MOV_FAMILY =>
op_arith_shift_n <= op_mov;
when others =>
end case;
end process;
-- }}}
---------------------------------------------------------------------------------------}}}
-- floating point ---------------------------------------------------------------------------------------{{{
float_units_inst: if FLOAT_IMPLEMENT /= 0 generate
float_inst: entity float_units port map(
float_a => float_a, -- level 9.
float_b => float_b, -- level 9.
fsub => code_vec(7)(CODE_W-1), -- level 9.
code => code_vec(0), -- level 16.
res_float => res_float, -- level MAX_FPU_DELAY+10. (38 if fdiv, 21 if fadd)
clk => clk
);
process(clk)
begin
if rising_edge(clk) then
res_float_d0 <= res_float; -- @ MAX_FPU_DELAY+11 (39 if fdiv, 22 if fadd)
res_float_d1 <= res_float_d0; -- @ MAX_FPU_DELAY+12 (40 if fdiv, 23 if fadd)
-- float_ce <= '0';
-- for i in 0 to N_REG_BLOCKS-1 loop
-- if regBlock_re_vec(1)(i) = '1' then
-- float_ce <= '1';
-- end if;
-- end loop;
end if;
end process;
end generate;
---------------------------------------------------------------------------------------------------------}}}
-- branch control ---------------------------------------------------------------------------------------{{{
process(clk)
begin
if rising_edge(clk) then
-- @ 17 {{{
res_alu <= res_low; -- @ 17.
branch_on_zero <= '0'; -- @ 17.
branch_on_not_zero <= '0'; -- @ 17.
wf_is_branching_p0 <= (others=>'0');
if family_vec(family_vec'high-15) = BRA_FAMILY then -- level 16.
wf_is_branching_p0(wf_indx_vec(0)) <= '1'; -- @ 17.
case code_vec(0) is -- level 16.
when BEQ =>
branch_on_zero <= '1'; -- @ 17.
when BNE =>
branch_on_not_zero <= '1'; -- @ 17.
when others=>
end case;
end if;
-- }}}
-- @ 18 {{{
wf_is_branching <= wf_is_branching_p0; -- @ 18.
alu_branch <= (others=>'0'); -- @ 18.
for i in 0 to CV_SIZE-1 loop
if res_alu(i) = (res_alu(i)'reverse_range=>'0') then -- level 17.
if branch_on_zero = '1' then -- level 17.
alu_branch(i) <= '1'; -- @ 18.
end if;
else
if branch_on_not_zero = '1' then -- level 17.
alu_branch(i) <= '1'; -- @ 18.
end if;
end if;
end loop;
-- }}}
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- write back into regFiles ----------------------------------------------------------------------------------{{{
-- register file -----------------------------------------------------------------------
-- bits 10:9 8 7:5 4:0
-- phase(1:0) phase(2) wf_indx instr_rd_addr
wrAddr_regFile_vec(wrAddr_regFile_vec'high)(REG_FILE_W-1 downto REG_FILE_W-2) <= phase(1 downto 0); -- level 0.
wrAddr_regFile_vec(wrAddr_regFile_vec'high)(REG_FILE_W-3) <= phase(PHASE_W-1); -- level 0.
wrAddr_regFile_vec(wrAddr_regFile_vec'high)(WI_REG_ADDR_W+N_WF_CU_W-1 downto WI_REG_ADDR_W) <= to_unsigned(wf_indx, N_WF_CU_W); -- level 0.
wrAddr_regFile_vec(wrAddr_regFile_vec'high)(WI_REG_ADDR_W-1 downto 0) <= unsigned(inst_rd_addr); -- level 0.
write_alu_res_back: process(family_vec(family_vec'high-15), rdData_alu_en_vec(rdData_alu_en_vec'high-11), reg_we_mov_vec(0))
begin
reg_we_alu_n <= (others=>'0'); -- level 16.
case family_vec(family_vec'high-15) is -- level 16.
when RTM_FAMILY | ADD_FAMILY | MUL_FAMILY | SHF_FAMILY | LGK_FAMILY | CND_FAMILY =>
reg_we_alu_n <= rdData_alu_en_vec(rdData_alu_en_vec'high-11); -- level 16.
when MOV_FAMILY =>
reg_we_alu_n <= rdData_alu_en_vec(rdData_alu_en_vec'high-11) and reg_we_mov_vec(0); -- level 16.
when others=>
end case;
end process;
process(clk)
begin
if rising_edge(clk) then
wrAddr_regFile_vec(wrAddr_regFile_vec'high-1 downto 0) <= wrAddr_regFile_vec(wrAddr_regFile_vec'high downto 1); -- @ 1.->MAX_FPU_DELAY+12.
reg_we_mov_vec(reg_we_mov_vec'high-1 downto 0) <= reg_we_mov_vec(reg_we_mov_vec'high downto 1); -- @ 11.->16.
lmem_regFile_we <= lmem_regFile_we_p0;
reg_we_alu <= reg_we_alu_n; -- @ 17.
reg_we_float <= (others=>'0'); -- @ 23.
case MAX_FPU_DELAY is
when FDIV_DELAY => -- fsqrt of fdiv has the maximum delay
if family_vec(1) = FLT_FAMILY then -- level 38. if fdiv
reg_we_float <= rdData_alu_en_vec(1); -- @ 39. if fdiv
end if;
when others => -- fadd has the maximum delay
if family_vec(0) = FLT_FAMILY then -- level 22. if fadd
reg_we_float <= rdData_alu_en_vec(0); -- @ 23. if fadd
end if;
end case;
wrData_alu <= (others=>(others=>'0')); -- @ 17.
case family_vec_at_16 is -- level 16.
when RTM_FAMILY =>
if rtm_rdData_nlid_vec(0) = '0' then -- level 16.
for i in 0 to CV_SIZE-1 loop
wrData_alu(i)(WG_SIZE_W-1 downto 0) <= std_logic_vector(rtm_rdData_d0((i+1)*WG_SIZE_W-1 downto i*WG_SIZE_W)); -- @ 17.
end loop;
else
for i in 0 to CV_SIZE-1 loop
wrData_alu(i) <= std_logic_vector(rtm_rdData_d0(DATA_W-1 downto 0)); -- @ 17.
end loop;
end if;
when ADD_FAMILY | MUL_FAMILY | CND_FAMILY | MOV_FAMILY =>
wrData_alu <= res_low; -- @ 17.
when SHF_FAMILY =>
if code_vec(0)(CODE_W-1) = '0' then -- level 16.
wrData_alu <= res_low; -- @ 17.
else
wrData_alu <= res_high;
end if;
when LGK_FAMILY =>
wrData_alu <= res_low; -- @ 17.
when GLS_FAMILY =>
when others =>
end case;
regBlock_we_alu <= (others=>'0'); -- @ 17.
regBlock_we_alu(to_integer(wrAddr_regFile_vec(wrAddr_regFile_vec'high-16)(REG_FILE_W-1 downto REG_FILE_BLOCK_W))) <= '1'; -- @ 17.+N_REG_BLOCKS*i
-- regBlock_we_float {{{
regBlock_we_float_vec(regBlock_we_float_vec'high) <= regBlock_we_alu; -- @ 18.+N_REG_BLOCKS*i
regBlock_we_float_vec(regBlock_we_float_vec'high-1 downto 0) <=
regBlock_we_float_vec(regBlock_we_float_vec'high downto 1); -- @ 19.->19+MAX_FPU_DELAY-7-1 (39. if fdiv, 22. if fadd)
case MAX_FPU_DELAY is
when FDIV_DELAY => -- fsqrt of fdiv has the maximum delay
regBlock_we_float <= regBlock_we_float_vec(1); -- @ MAX_FPU_DELAY+11 (39. if fadd)
when others => -- fadd has the maximum delay
regBlock_we_float <= regBlock_we_float_vec(0); -- @ MAX_FPU_DELAY+12 (23. if fadd)
end case;
-- }}}
-- the register block that will be written from global and local memory reads will be selected {{{
if LMEM_IMPLEMENT = 0 or lmem_regFile_we_p0 = '0' then
-- if no read of lmem content is comming, prepare the we of the register block according to the current address sent from CU_mem_cntrl
regBlock_we_mem <= (others=>'0'); -- stage 0
regBlock_we_mem(to_integer(mem_regFile_wrAddr(REG_FILE_W-1 downto REG_FILE_BLOCK_W))) <= '1'; -- (@ 22. for lmem reads)
elsif lmem_regFile_we = '0' or regBlock_we_mem(N_REG_BLOCKS-1) = '1' then
-- there will be a read from lmem or a half of the read data burst is over. Set the we of the first register block!
regBlock_we_mem(N_REG_BLOCKS-1 downto 1) <= (others=>'0'); -- stage 0
regBlock_we_mem(0) <= '1';
else -- lmem is being read. Shift left for regBlock_we_mem!
regBlock_we_mem(N_REG_BLOCKS-1 downto 1) <= regBlock_we_mem(N_REG_BLOCKS-2 downto 0);
regBlock_we_mem(0) <= '0';
end if;
mem_regFile_wrAddr_d0 <= mem_regFile_wrAddr; -- stage 1
-- }}}
-- regBlock_wrAddr {{{
for j in 0 to N_REG_BLOCKS-1 loop
if regBlock_we_alu(j) = '1' then -- level 17.+j
regBlock_wrAddr(j) <= wrAddr_regFile_vec(wrAddr_regFile_vec'high-17)(REG_FILE_BLOCK_W-1 downto 0); -- @ 18.+j
elsif FLOAT_IMPLEMENT /= 0 and regBlock_we_float(j) = '1' then -- level 23.+j if add, 39.+j if fdiv
case MAX_FPU_DELAY is
when FDIV_DELAY => -- fsqrt of fdiv has the maximum delay
regBlock_wrAddr(j) <= wrAddr_regFile_vec(1)(REG_FILE_BLOCK_W-1 downto 0); -- @ 40.+j if fdiv
when others => -- fadd has the maximum delay
regBlock_wrAddr(j) <= wrAddr_regFile_vec(0)(REG_FILE_BLOCK_W-1 downto 0); -- @ 24.+j if fadd
end case;
else
regBlock_wrAddr(j) <= mem_regFile_wrAddr(REG_FILE_BLOCK_W-1 downto 0); -- stage 1. or 2.
end if;
end loop;
-- }}}
for i in 0 to CV_SIZE-1 loop
for j in 0 to N_REG_BLOCKS-1 loop
-- regBlock_wrData {{{
if regBlock_we_alu(j) = '1' then -- level 17.
-- write by alu operations
regBlock_wrData(i)(j) <= wrData_alu(i); -- @ 18.
elsif FLOAT_IMPLEMENT /= 0 and regBlock_we_float(j) = '1' then -- level 23. if fadd, 39. if fdiv
-- write by floating point units
case MAX_FPU_DELAY is
when FDIV_DELAY => -- fsqrt of fdiv has the maximum delay
regBlock_wrData(i)(j) <= res_float_d0(i); -- @ 40.+j
when others => -- fadd has the maximum delay
regBlock_wrData(i)(j) <= res_float_d1(i); -- @ 24.+j
end case;
else
-- write by memory reads
regBlock_wrData(i)(j) <= mem_regFile_wrData(i); -- @ 1. or 2.
end if;
-- }}}
-- regBlock_we {{{
if regBlock_we_alu(j) = '1' then -- level 17.+j
regBlock_we(i)(j) <= reg_we_alu(i); -- @ 18.+j
elsif FLOAT_IMPLEMENT /= 0 and regBlock_we_float(j) = '1' then -- level 23.+j if fadd, 39.+j uf fdiv
regBlock_we(i)(j) <= reg_we_float(i); -- @ 24.+j if fadd, 40.+j if fdiv
elsif regBlock_we_mem(j) = '1' then -- (level 22 for lmem reads; no conflict with 17+N_REG_BLOCKS*i)
regBlock_we(i)(j) <= mem_regFile_we(i); -- @ 1. or 2. (@23. for loads from lmem)
else
regBlock_we(i)(j) <= '0';
end if;
-- }}}
end loop;
end loop;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
end Behavioral;
| gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/14-MESA-IA/asap-alap-random/mesaia_alap.vhd | 1 | 7147 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.13:54:59)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesaia_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31, input32, input33, input34, input35, input36, input37, input38, input39, input40, input41, input42, input43, input44, input45, input46, input47, input48: IN unsigned(0 TO 30);
output1, output2, output3, output4: OUT unsigned(0 TO 31));
END mesaia_alap_entity;
ARCHITECTURE mesaia_alap_description OF mesaia_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register9: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register10: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register11: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register12: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register13: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register14: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register15: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register16: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register17: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register18: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 + 3;
register4 := input4 * 4;
register5 := input5 + 5;
register6 := input6 * 6;
register7 := input7 + 7;
register8 := input8 * 8;
register9 := input9 + 9;
register10 := input10 * 10;
register11 := input11 + 11;
register12 := input12 * 12;
register13 := input13 + 13;
register14 := input14 * 14;
register15 := input15 + 15;
register16 := input16 * 16;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := input17 * 17;
register3 := register4 + register3;
register4 := input18 * 18;
register5 := register6 + register5;
register6 := input19 * 19;
register7 := register8 + register7;
register8 := input20 * 20;
register9 := register10 + register9;
register10 := input21 * 21;
register11 := register12 + register11;
register12 := input22 * 22;
register13 := register14 + register13;
register14 := input23 * 23;
register15 := register16 + register15;
register16 := input24 * 24;
WHEN "00000011" =>
register1 := register2 + register1;
register2 := register4 + register3;
register3 := input25 + 25;
register4 := input26 * 26;
register5 := register6 + register5;
register6 := register8 + register7;
register7 := input27 + 27;
register8 := input28 * 28;
register9 := register10 + register9;
register10 := register12 + register11;
register11 := input29 + 29;
register12 := input30 * 30;
register13 := register14 + register13;
register14 := register16 + register15;
register15 := input31 + 31;
register16 := input32 * 32;
WHEN "00000100" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := ((NOT register2) + 1) XOR register2;
register3 := register4 + register3;
register4 := input33 * 37;
register5 := ((NOT register5) + 1) XOR register5;
register6 := ((NOT register6) + 1) XOR register6;
register7 := register8 + register7;
register8 := input34 * 42;
register9 := ((NOT register9) + 1) XOR register9;
register10 := ((NOT register10) + 1) XOR register10;
register11 := register12 + register11;
register12 := input35 * 47;
register13 := ((NOT register13) + 1) XOR register13;
register14 := ((NOT register14) + 1) XOR register14;
register15 := register16 + register15;
register16 := input36 * 52;
register17 := input37 + 53;
register18 := input38 * 54;
WHEN "00000101" =>
register1 := register2 - register1;
register2 := register4 + register3;
register3 := input39 + 55;
register4 := input40 * 56;
register5 := register6 - register5;
register6 := register8 + register7;
register7 := input41 + 57;
register8 := input42 * 58;
register9 := register10 - register9;
register10 := register12 + register11;
register11 := input43 + 59;
register12 := input44 * 60;
register13 := register14 - register13;
register14 := register16 + register15;
register15 := register18 + register17;
register16 := input45 * 61;
WHEN "00000110" =>
register1 := register1 * 63;
register2 := ((NOT register2) + 1) XOR register2;
register3 := register4 + register3;
register4 := input46 * 66;
register5 := register5 * 68;
register6 := ((NOT register6) + 1) XOR register6;
register7 := register8 + register7;
register8 := input47 * 71;
register9 := register9 * 73;
register10 := ((NOT register10) + 1) XOR register10;
register11 := register12 + register11;
register12 := input48 * 76;
register13 := register13 * 78;
register14 := ((NOT register14) + 1) XOR register14;
register15 := register16 + register15;
WHEN "00000111" =>
register1 := register2 + register1;
register2 := register4 + register3;
register3 := register6 + register5;
register4 := register8 + register7;
register5 := register10 + register9;
register6 := register12 + register11;
register7 := register14 + register13;
WHEN "00001000" =>
output1 <= register1(0 TO 14) & register15(0 TO 15);
output2 <= register3(0 TO 14) & register2(0 TO 15);
output3 <= register5(0 TO 14) & register4(0 TO 15);
output4 <= register7(0 TO 14) & register6(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesaia_alap_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/5-EWF/asap-alap-random/ewf_random.vhd | 1 | 3164 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.08:47:50)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
END ewf_random_entity;
ARCHITECTURE ewf_random_description OF ewf_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register2 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register1 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
register6 := register4 * 10;
WHEN "00000110" =>
register5 := register3 + register5;
WHEN "00000111" =>
register4 := register4 + register5;
register6 := register1 + register6;
register3 := register3 + register5;
WHEN "00001000" =>
register1 := register1 + register6;
register3 := register3 * 12;
WHEN "00001001" =>
register1 := register1 * 14;
WHEN "00001010" =>
register1 := register1 + 16;
register3 := register2 + register3;
WHEN "00001011" =>
register7 := register6 + register1;
register2 := register2 + register3;
WHEN "00001100" =>
register7 := register7 + 18;
register5 := register5 + register3;
WHEN "00001101" =>
register8 := register7 * 20;
output1 <= register6 + register4;
WHEN "00001110" =>
register4 := register8 + 23;
register6 := register1 + 25;
register2 := register2 * 27;
WHEN "00001111" =>
register6 := register6 * 29;
output2 <= register7 + register4;
register4 := register5 + 32;
register2 := register2 + 34;
WHEN "00010000" =>
output3 <= register3 + register2;
output4 <= register1 + register6;
register1 := register4 * 38;
WHEN "00010001" =>
register1 := register1 + 40;
WHEN "00010010" =>
output5 <= register4 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_random_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/7-FIR1/metaheurísticas/fir1_ibea.vhd | 1 | 3615 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:31:57)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir1_ibea_entity;
ARCHITECTURE fir1_ibea_description OF fir1_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 and input1;
register2 := input2 and input2;
register3 := input3 and input3;
register4 := input4 and input4;
WHEN "00000010" =>
register1 := register1 * register2;
register2 := input5 and input5;
register5 := input6 and input6;
register6 := input7 and input7;
register7 := input8 and input8;
register8 := input9 and input9;
register9 := input10 and input10;
register10 := input11 and input11;
register3 := register4 * register3;
WHEN "00000011" =>
register4 := register5 * register10;
register5 := input12 and input12;
register10 := input13 and input13;
register6 := register9 * register6;
WHEN "00000100" =>
register2 := register10 * register2;
register9 := input14 and input14;
register1 := register1 + register6;
register6 := input15 and input15;
register7 := register7 * register8;
register3 := register3 + register4;
register4 := input16 and input16;
register8 := input17 and input17;
WHEN "00000101" =>
register5 := register8 * register5;
register8 := input18 and input18;
WHEN "00000110" =>
register6 := register6 * register8;
WHEN "00000111" =>
register1 := register1 + register6;
register6 := input19 and input19;
WHEN "00001000" =>
register4 := register6 * register4;
register6 := input20 and input20;
register8 := input21 and input21;
register1 := register5 + register1;
WHEN "00001001" =>
register5 := register9 * register8;
register2 := register4 + register2;
register4 := input22 and input22;
WHEN "00001010" =>
register1 := register2 + register1;
register2 := register6 * register4;
WHEN "00001011" =>
register1 := register1 + register5;
WHEN "00001100" =>
register1 := register3 + register1;
WHEN "00001101" =>
register1 := register1 + register2;
WHEN "00001110" =>
register1 := register7 + register1;
WHEN "00001111" =>
output1 <= register1 and register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir1_ibea_description; | gpl-3.0 |
jouyang3/FMCW | DSP/Radar_DSP/FPGA/Individual Modules/Ram_example/Ram_example/simulation/modelsim/work/tb_memory/_primary.vhd | 1 | 78 | library verilog;
use verilog.vl_types.all;
entity tb_memory is
end tb_memory;
| gpl-3.0 |
rcls/sdr | vhdl/sinrom.vhd | 1 | 18981 | library IEEE;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.defs.all;
package sincos is
function sinoffset(sinent : unsigned18; lowbits : unsigned2) return unsigned3;
constant sinrom : sinrom_t := (
"11"&x"c001", "11"&x"c009", "11"&x"c011", "11"&x"c019",
"11"&x"c021", "11"&x"c029", "11"&x"c031", "11"&x"c039",
"11"&x"c041", "11"&x"c049", "11"&x"c051", "11"&x"c059",
"11"&x"c061", "11"&x"c069", "11"&x"c071", "11"&x"c079",
"11"&x"c081", "11"&x"c089", "11"&x"c091", "11"&x"c099",
"11"&x"c0a1", "11"&x"c0a9", "11"&x"c0b1", "11"&x"c0b9",
"11"&x"c0c1", "11"&x"c0c9", "11"&x"c0d1", "11"&x"c0d9",
"11"&x"c0e1", "11"&x"c0e9", "11"&x"c0f1", "11"&x"c0f9",
"11"&x"c101", "11"&x"c109", "11"&x"c111", "11"&x"c119",
"11"&x"c121", "11"&x"c129", "11"&x"c131", "11"&x"c139",
"11"&x"c141", "11"&x"c149", "11"&x"c151", "11"&x"c159",
"11"&x"c161", "11"&x"c169", "11"&x"c171", "11"&x"c179",
"11"&x"c181", "11"&x"c189", "11"&x"c191", "11"&x"c199",
"11"&x"c1a1", "11"&x"c1a9", "11"&x"81b1", "11"&x"c1b8",
"11"&x"c1c0", "11"&x"c1c8", "11"&x"c1d0", "11"&x"c1d8",
"11"&x"c1e0", "11"&x"c1e8", "11"&x"c1f0", "11"&x"c1f8",
"11"&x"c200", "11"&x"c208", "11"&x"c210", "11"&x"c218",
"11"&x"c220", "11"&x"c228", "11"&x"c230", "11"&x"c238",
"11"&x"c240", "11"&x"c248", "11"&x"c250", "11"&x"c258",
"11"&x"c260", "11"&x"c268", "11"&x"8270", "11"&x"c277",
"11"&x"c27f", "11"&x"c287", "11"&x"c28f", "11"&x"c297",
"11"&x"c29f", "11"&x"c2a7", "11"&x"c2af", "11"&x"c2b7",
"11"&x"c2bf", "11"&x"c2c7", "11"&x"c2cf", "11"&x"c2d7",
"10"&x"c2df", "11"&x"c2e6", "11"&x"c2ee", "11"&x"c2f6",
"11"&x"c2fe", "11"&x"c306", "11"&x"c30e", "11"&x"c316",
"11"&x"c31e", "11"&x"c326", "11"&x"c32e", "10"&x"c336",
"11"&x"c33d", "11"&x"c345", "11"&x"c34d", "11"&x"c355",
"11"&x"c35d", "11"&x"c365", "11"&x"c36d", "11"&x"c375",
"10"&x"c37d", "11"&x"c384", "11"&x"c38c", "11"&x"c394",
"11"&x"c39c", "11"&x"c3a4", "11"&x"c3ac", "11"&x"c3b4",
"10"&x"c3bc", "11"&x"c3c3", "11"&x"c3cb", "11"&x"c3d3",
"11"&x"c3db", "11"&x"c3e3", "11"&x"c3eb", "11"&x"43f3",
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"01"&x"5413", "00"&x"9414", "00"&x"5415", "01"&x"5417",
"00"&x"9418", "00"&x"5419", "01"&x"541b", "01"&x"541c",
"00"&x"941d", "00"&x"541e", "01"&x"5420", "01"&x"5421",
"00"&x"9422", "00"&x"5423", "00"&x"1425", "01"&x"5426",
"01"&x"5427", "00"&x"9428", "00"&x"9429", "00"&x"542a",
"00"&x"542b", "00"&x"142d", "01"&x"542e", "01"&x"542f",
"01"&x"5430", "01"&x"5431", "00"&x"9432", "00"&x"9433",
"00"&x"9434", "00"&x"9435", "00"&x"9436", "00"&x"9437",
"00"&x"9438", "00"&x"9439", "01"&x"543a", "01"&x"543b",
"01"&x"543c", "01"&x"543d", "00"&x"143e", "00"&x"143f",
"00"&x"1440", "00"&x"5440", "00"&x"9441", "00"&x"9442",
"01"&x"5443", "00"&x"1444", "00"&x"1445", "00"&x"5445",
"00"&x"9446", "01"&x"5447", "00"&x"1448", "00"&x"5448",
"00"&x"9449", "00"&x"144a", "00"&x"144b", "00"&x"544b",
"01"&x"544c", "00"&x"144d", "00"&x"544d", "01"&x"544e",
"00"&x"144f", "00"&x"944f", "00"&x"1450", "00"&x"1451",
"01"&x"5451", "00"&x"1452", "00"&x"9452", "00"&x"1453",
"00"&x"5453", "00"&x"1454", "00"&x"5454", "00"&x"1455",
"00"&x"5455", "00"&x"1456", "00"&x"5456", "00"&x"1457",
"00"&x"9457", "00"&x"1458", "00"&x"1458", "00"&x"1459",
"00"&x"1459", "00"&x"9459", "00"&x"145a", "00"&x"145a",
"00"&x"545a", "00"&x"145b", "00"&x"145b", "00"&x"945b",
"00"&x"145c", "00"&x"145c", "00"&x"145c", "00"&x"145d",
"00"&x"145d", "00"&x"145d", "00"&x"145d", "00"&x"945d",
"00"&x"145e", "00"&x"145e", "00"&x"145e", "00"&x"145e",
"00"&x"145e", "00"&x"945e", "00"&x"145f", "00"&x"145f",
"00"&x"145f", "00"&x"145f", "00"&x"145f", "00"&x"145f",
"00"&x"145f", "00"&x"145f", "00"&x"145f", "00"&x"145f");
-- Used bitmask: ffef
end sincos;
package body sincos is
function sinoffset(sinent : unsigned18; lowbits : unsigned2) return unsigned3 is
begin
case lowbits & sinent(17 downto 14) is
when "00" & x"1" => return "000"; -- 001 1110
when "00" & x"2" => return "000"; -- 010 1100
when "00" & x"3" => return "000"; -- 011 2210
when "00" & x"4" => return "000"; -- 012 3320
when "00" & x"5" => return "000"; -- 100 1000
when "00" & x"6" => return "000"; -- 101 2110
when "00" & x"7" => return "000"; -- 110 2100
when "00" & x"8" => return "000"; -- 111 3210
when "00" & x"9" => return "000"; -- 112 4320
when "00" & x"a" => return "000"; -- 121 4310
when "00" & x"b" => return "000"; -- 122 5420
when "00" & x"c" => return "000"; -- 211 4210
when "00" & x"d" => return "000"; -- 212 5320
when "00" & x"e" => return "000"; -- 221 5310
when "00" & x"f" => return "000"; -- 222 6420
when "01" & x"0" => return "000"; -- 000 0000
when "01" & x"1" => return "001"; -- 001 1110
when "01" & x"2" => return "000"; -- 010 1100
when "01" & x"3" => return "001"; -- 011 2210
when "01" & x"4" => return "010"; -- 012 3320
when "01" & x"5" => return "000"; -- 100 1000
when "01" & x"6" => return "001"; -- 101 2110
when "01" & x"7" => return "000"; -- 110 2100
when "01" & x"8" => return "001"; -- 111 3210
when "01" & x"9" => return "010"; -- 112 4320
when "01" & x"a" => return "001"; -- 121 4310
when "01" & x"b" => return "010"; -- 122 5420
when "01" & x"c" => return "001"; -- 211 4210
when "01" & x"d" => return "010"; -- 212 5320
when "01" & x"e" => return "001"; -- 221 5310
when "01" & x"f" => return "010"; -- 222 6420
when "10" & x"0" => return "000"; -- 000 0000
when "10" & x"1" => return "001"; -- 001 1110
when "10" & x"2" => return "001"; -- 010 1100
when "10" & x"3" => return "010"; -- 011 2210
when "10" & x"4" => return "011"; -- 012 3320
when "10" & x"5" => return "000"; -- 100 1000
when "10" & x"6" => return "001"; -- 101 2110
when "10" & x"7" => return "001"; -- 110 2100
when "10" & x"8" => return "010"; -- 111 3210
when "10" & x"9" => return "011"; -- 112 4320
when "10" & x"a" => return "011"; -- 121 4310
when "10" & x"b" => return "100"; -- 122 5420
when "10" & x"c" => return "010"; -- 211 4210
when "10" & x"d" => return "011"; -- 212 5320
when "10" & x"e" => return "011"; -- 221 5310
when "10" & x"f" => return "100"; -- 222 6420
when "11" & x"0" => return "000"; -- 000 0000
when "11" & x"1" => return "001"; -- 001 1110
when "11" & x"2" => return "001"; -- 010 1100
when "11" & x"3" => return "010"; -- 011 2210
when "11" & x"4" => return "011"; -- 012 3320
when "11" & x"5" => return "001"; -- 100 1000
when "11" & x"6" => return "010"; -- 101 2110
when "11" & x"7" => return "010"; -- 110 2100
when "11" & x"8" => return "011"; -- 111 3210
when "11" & x"9" => return "100"; -- 112 4320
when "11" & x"a" => return "100"; -- 121 4310
when "11" & x"b" => return "101"; -- 122 5420
when "11" & x"c" => return "100"; -- 211 4210
when "11" & x"d" => return "101"; -- 212 5320
when "11" & x"e" => return "101"; -- 221 5310
when "11" & x"f" => return "110"; -- 222 6420
when others => return "000";
end case;
end sinoffset;
end sincos;
| gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/5-EWF/metaheurísticas/ewf_spea2.vhd | 1 | 3121 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:40)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
END ewf_spea2_entity;
ARCHITECTURE ewf_spea2_description OF ewf_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register1 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register2 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
WHEN "00000110" =>
register5 := register3 + register5;
WHEN "00000111" =>
register3 := register3 + register5;
register6 := register4 * 10;
WHEN "00001000" =>
register3 := register3 * 12;
register6 := register2 + register6;
register4 := register4 + register5;
WHEN "00001001" =>
output1 <= register6 + register4;
register2 := register2 + register6;
WHEN "00001010" =>
register2 := register2 * 15;
register3 := register1 + register3;
WHEN "00001011" =>
register1 := register1 + register3;
WHEN "00001100" =>
register1 := register1 * 17;
WHEN "00001101" =>
register1 := register1 + 19;
register4 := register5 + register3;
WHEN "00001110" =>
output2 <= register3 + register1;
register1 := register4 + 22;
WHEN "00001111" =>
register3 := register1 * 24;
WHEN "00010000" =>
register3 := register3 + 26;
WHEN "00010001" =>
output3 <= register1 + register3;
register1 := register2 + 29;
WHEN "00010010" =>
register2 := register1 + 31;
WHEN "00010011" =>
register2 := register2 * 33;
WHEN "00010100" =>
output4 <= register1 + register2;
register1 := register6 + register1;
WHEN "00010101" =>
register1 := register1 + 36;
WHEN "00010110" =>
register2 := register1 * 38;
WHEN "00010111" =>
register2 := register2 + 40;
WHEN "00011000" =>
output5 <= register1 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_spea2_description; | gpl-3.0 |
rcls/sdr | vhdl/quadcheby.vhd | 1 | 5391 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
use work.sincos.all;
entity quadcheby is
port (D : in mf_signed;
Q : out signed36;
last_in : in std_logic;
last_out : out std_logic;
clk : in std_logic);
end quadcheby;
architecture quadcheby of quadcheby is
-- We implement:
-- d/dt U = - D - alpha U - beta I
-- d/dt I = U + V
-- d/dt V = - alpha V - beta I
-- Q = 2 alpha V
-- Letting A = U+V, we have
-- d/dt I = A,
-- d/dt A = -D - alpha A - 2 beta I
-- (d/dt)^2 A + alpha d/dt A + 2 beta A + d/dt D = 0.
-- Letting B = U - V, we have
-- d/dt B = -D - alpha B
-- In s-domain,
-- A = -s / (s^2 + alpha s + 2 beta) D
-- B = -1 / (s + alpha) D
-- Q = alpha(A - B) = alpha [ 1/(s+alpha) - s/(s^2 + alpha s + 2beta)] D
-- = 2 alpha beta / (s + alpha)(s^2 + alpha s + 2 beta) D
-- For reference:
-- V = beta / (s + alpha)(s^2 + alpha s + 2 beta) D
-- U = (A + B)/2 = [ 1/(s + alpha) + s/(s^2 + alpha s + 2beta ] D / 2
-- = D (s^2 + alpha s + beta) / (s+alpha)(s^2 + alpha s + 2 beta)
-- = D [1 - beta / (s + alpha s + 2 beta)] / (s + alpha)
-- I = -1 / (s^2 + alpha s + 2 beta) D
-- We have 4 channels TDMd over 16 cycles.
-- We want an overall bandwidth of around 200kHz = 1/1250 f_clk.
-- With beta=4alpha^2, the bandwidth is about pi*alpha rads/clk
-- = alpha/2 f_clk.
-- Remembering that f_clk is 250MHz / 16, take alpha = 1/32.
constant alpha_b : integer := 5;
-- Split beta into two parts; one applied going into I, one coming out.
constant beta1_b : integer := alpha_b;
constant beta2_b : integer := alpha_b - 1;
constant iwidth : integer := maximum(37, mf_width + alpha_b);
constant itop : integer := iwidth - alpha_b;
subtype acc_t is signed(iwidth - 1 downto 0);
signal U, U_a, U_b, U_c, U_d : acc_t := (others => '0');
signal V, V_a, V_b, V_c, V_d : acc_t := (others => '0');
signal I, I_a, I_b, I_c, I_d : acc_t := (others => '0');
signal Uaddend : acc_t := (others => '0');
signal Uc, Vc, Ic : std_logic := '0';
signal phase : unsigned2 := "00";
signal strobe0 : std_logic := '1';
signal strobe1 : std_logic := '0';
attribute keep_hierarchy : string;
attribute keep_hierarchy of quadcheby : architecture is "soft";
begin
process
variable U1, U2, V2, I2 : acc_t;
begin
wait until rising_edge(clk);
strobe0 <= phase(0) and phase(1);
strobe1 <= strobe0;
if strobe0 = '1' then
V_a <= V;
V_b <= V_a;
V_c <= V_b;
V_d <= V_c;
I_a <= I;
I_b <= I_a;
I_c <= I_b;
I_d <= I_c;
U_a <= U;
U_b <= U_a;
U_c <= U_b;
U_d <= U_c;
end if;
case phase is
when "01" =>
Uaddend <= resize(U_d(iwidth - 1 downto alpha_b), iwidth);
Uc <= not U_d(alpha_b - 1);
when "10" =>
Uaddend <= resize(I_d(iwidth - 1 downto beta2_b), iwidth);
Uc <= not I_d(beta2_b - 1);
when others =>
Uaddend <= (others => 'X');
Uc <= '1';
end case;
if strobe1 = '1' then
U1 := U_d;
U2 := resize(D, iwidth) sll (itop - mf_width);
last_out <= last_in;
Q <= V_d(itop + alpha_b - 2 downto itop + alpha_b - 37);
else
U1 := U;
U2 := Uaddend;
end if;
U <= U1 + (not U2) + ("0" & Uc);
if phase = "01" then
Vc <= not V_d(alpha_b - 1);
Ic <= U_d(beta1_b - 1);
elsif phase = "10" then
Vc <= not I_d(beta2_b - 1);
Ic <= V_d(beta1_b - 1);
else
Vc <= '0';
Ic <= '0';
end if;
case phase is
when "10" =>
V2 := not resize(V_d(iwidth - 1 downto alpha_b), iwidth);
I2 := resize(U_d(iwidth - 1 downto beta1_b), iwidth);
when "11" =>
V2 := not resize(I_d(iwidth - 1 downto beta2_b), iwidth);
I2 := resize(V_d(iwidth - 1 downto beta1_b), iwidth);
when others =>
V2 := V_d;
I2 := I_d;
end case;
V <= V + V2 + ("0" & Vc);
I <= I + I2 + ("0" & Ic);
if strobe0 = '1' then
V <= (others => '0');
I <= (others => '0');
end if;
phase <= phase + 1;
end process;
end quadcheby;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
entity test_quadcheby is
port (clk : out std_logic;
Q : out signed(35 downto 0);
last_out : out std_logic);
end test_quadcheby;
architecture test_quadcheby of test_quadcheby is
signal clk_main : std_logic := '0';
signal count : unsigned(10 downto 0) := (others => '0');
signal D : mf_signed := (others => '0');
signal last_in : std_logic := '0';
begin
uut : entity work.quadcheby port map(D, Q, last_in, last_out, clk_main);
clk <= clk_main;
process
begin
wait for 2ns;
clk_main <= not clk_main;
end process;
process(clk_main)
begin
if clk_main'event and clk_main = '1' then
count <= count + 1;
if count(1 downto 0) = "00" then
last_in <= '0';
--D <= (others => '0');
end if;
if count(3 downto 0) = "1100" then
last_in <= '1';
end if;
if count(3 downto 0) = "0000" then
if count(10) = '1' then
D <= to_signed(262144, mf_width);
else
D <= to_signed(-262144, mf_width);
end if;
end if;
end if;
end process;
end test_quadcheby;
| gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/4-MPEG-MV/metaheurísticas/mpegmv_wsga.vhd | 1 | 2861 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.09:04:32)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END mpegmv_wsga_entity;
ARCHITECTURE mpegmv_wsga_description OF mpegmv_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
WHEN "00000010" =>
register4 := register4 + 6;
register5 := input5 * 7;
register6 := input6 * 8;
register3 := register3 + 10;
register2 := register2 + 12;
WHEN "00000011" =>
register1 := register1 + register2;
register2 := register6 + register3;
register3 := input7 * 13;
register4 := register5 + register4;
register5 := input8 * 14;
WHEN "00000100" =>
register1 := register5 + register1;
register5 := input9 * 15;
register2 := register3 + register2;
register3 := input10 * 16;
WHEN "00000101" =>
register1 := ((NOT register1) + 1) XOR register1;
register6 := input11 * 19;
register3 := register3 + 21;
WHEN "00000110" =>
output1 <= register5 + register3;
register3 := input12 * 23;
register5 := register6 + 25;
WHEN "00000111" =>
register3 := register3 + register5;
register5 := input13 * 26;
output2 <= register1(0 TO 15) & register2(0 TO 15);
WHEN "00001000" =>
register1 := register5 + register3;
register2 := input14 * 28;
WHEN "00001001" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := register2 + register4;
WHEN "00001010" =>
output3 <= register1(0 TO 15) & register2(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_wsga_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/4-MPEG-MV/asap-alap-random/mpegmv_random.vhd | 1 | 3504 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:37:23)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END mpegmv_random_entity;
ARCHITECTURE mpegmv_random_description OF mpegmv_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register9: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register10: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register11: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register12: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register13: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
register6 := input6 * 6;
register7 := input7 * 7;
register8 := input8 * 8;
register9 := input9 * 9;
WHEN "00000010" =>
register10 := input10 * 10;
WHEN "00000011" =>
register10 := register10 + 12;
WHEN "00000100" =>
register9 := register9 + register10;
register10 := input11 * 13;
register11 := input12 * 14;
register12 := input13 * 15;
WHEN "00000101" =>
register11 := register11 + 17;
register3 := register3 + 19;
register4 := register4 + 21;
register13 := input14 * 22;
register6 := register6 + register9;
WHEN "00000110" =>
register2 := register2 + register11;
register4 := register10 + register4;
WHEN "00000111" =>
register2 := register5 + register2;
register5 := register12 + 24;
register1 := register1 + register4;
register3 := register7 + register3;
WHEN "00001000" =>
output1 <= register13 + register5;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001001" =>
output2 <= register1(0 TO 15) & register6(0 TO 15);
register1 := register8 + register3;
WHEN "00001010" =>
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001011" =>
output3 <= register1(0 TO 15) & register2(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_random_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/5-EWF/metaheurísticas/ewf_hype.vhd | 1 | 3138 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:21)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 30);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 31));
END ewf_hype_entity;
ARCHITECTURE ewf_hype_description OF ewf_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
WHEN "00000010" =>
register2 := register1 + 3;
register3 := input2 + 4;
WHEN "00000011" =>
register4 := register2 + 6;
WHEN "00000100" =>
register4 := register3 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
register6 := register4 * 10;
WHEN "00000110" =>
register5 := register2 + register5;
WHEN "00000111" =>
register2 := register2 + register5;
WHEN "00001000" =>
register2 := register2 * 12;
WHEN "00001001" =>
register2 := register1 + register2;
WHEN "00001010" =>
register1 := register1 + register2;
WHEN "00001011" =>
register1 := register1 * 14;
WHEN "00001100" =>
register1 := register1 + 16;
WHEN "00001101" =>
output1 <= register2 + register1;
register1 := register5 + register2;
register2 := register4 + register5;
WHEN "00001110" =>
register4 := register3 + register6;
WHEN "00001111" =>
register3 := register3 + register4;
output2 <= register4 + register2;
register1 := register1 + 20;
WHEN "00010000" =>
register2 := register1 * 22;
WHEN "00010001" =>
register2 := register2 + 24;
WHEN "00010010" =>
output3 <= register1 + register2;
register1 := register3 * 27;
WHEN "00010011" =>
register1 := register1 + 29;
WHEN "00010100" =>
register2 := register4 + register1;
register3 := register1 + 31;
WHEN "00010101" =>
register3 := register3 * 33;
WHEN "00010110" =>
output4 <= register1 + register3;
register1 := register2 + 36;
WHEN "00010111" =>
register2 := register1 * 38;
WHEN "00011000" =>
register2 := register2 + 40;
WHEN "00011001" =>
output5 <= register1 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_hype_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/9-MESA-FP/asap-alap-random/mesafp_random.vhd | 1 | 4525 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.16:15:41)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesafp_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END mesafp_random_entity;
ARCHITECTURE mesafp_random_description OF mesafp_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register17: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 * 3;
WHEN "00000010" =>
register2 := register2 + 5;
register4 := input4 * 6;
register5 := input5 * 7;
WHEN "00000011" =>
register4 := register4 + 9;
register6 := input6 * 10;
register7 := input7 + 11;
register8 := input8 * 12;
register9 := input9 * 13;
register10 := input10 + 14;
register11 := input11 + 15;
register12 := input12 * 16;
WHEN "00000100" =>
register8 := register8 + 18;
register13 := input13 * 19;
register11 := register12 + register11;
register12 := input14 + 20;
register14 := input15 + 21;
register15 := input16 + 22;
register16 := input17 * 23;
WHEN "00000101" =>
register12 := register12 + 25;
register17 := input18 * 26;
register10 := register13 + register10;
WHEN "00000110" =>
register13 := register17 + register15;
register15 := input19 * 27;
register5 := register5 + 29;
register17 := input20 * 30;
register6 := register6 + register10;
register10 := input21 * 31;
register9 := register9 + register14;
register11 := register16 + register11;
WHEN "00000111" =>
register11 := ((NOT register11) + 1) XOR register11;
WHEN "00001000" =>
output1 <= register11(0 TO 1) & register8(0 TO 2);
register7 := register10 + register7;
register8 := register15 + register13;
WHEN "00001001" =>
register7 := register17 + register7;
register6 := ((NOT register6) + 1) XOR register6;
register3 := register3 + register9;
WHEN "00001010" =>
register7 := ((NOT register7) + 1) XOR register7;
register6 := register6 / 2;
register3 := ((NOT register3) + 1) XOR register3;
register8 := ((NOT register8) + 1) XOR register8;
WHEN "00001011" =>
register7 := register6 * register7;
WHEN "00001100" =>
output2 <= register7(0 TO 1) & register5(0 TO 2);
register5 := register6 * register8;
register7 := ((NOT register12) + 1) XOR register12;
WHEN "00001101" =>
output3 <= register5(0 TO 1) & register4(0 TO 2);
register3 := register6 * register3;
WHEN "00001110" =>
output4 <= register3(0 TO 1) & register2(0 TO 2);
register1 := register1 + 51;
WHEN "00001111" =>
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00010000" =>
IF (register7 = 54 or register1 = 54) THEN
output5 <= register7;
ELSE
output5 <= "10110";
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesafp_random_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/14-MESA-IA/asap-alap-random/mesaia_alap.vhd | 1 | 6651 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.13:54:59)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesaia_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31, input32, input33, input34, input35, input36, input37, input38, input39, input40, input41, input42, input43, input44, input45, input46, input47, input48: IN unsigned(0 TO 3);
output1, output2, output3, output4: OUT unsigned(0 TO 4));
END mesaia_alap_entity;
ARCHITECTURE mesaia_alap_description OF mesaia_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register17: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register18: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 + 3;
register4 := input4 * 4;
register5 := input5 + 5;
register6 := input6 * 6;
register7 := input7 + 7;
register8 := input8 * 8;
register9 := input9 + 9;
register10 := input10 * 10;
register11 := input11 + 11;
register12 := input12 * 12;
register13 := input13 + 13;
register14 := input14 * 14;
register15 := input15 + 15;
register16 := input16 * 16;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := input17 * 17;
register3 := register4 + register3;
register4 := input18 * 18;
register5 := register6 + register5;
register6 := input19 * 19;
register7 := register8 + register7;
register8 := input20 * 20;
register9 := register10 + register9;
register10 := input21 * 21;
register11 := register12 + register11;
register12 := input22 * 22;
register13 := register14 + register13;
register14 := input23 * 23;
register15 := register16 + register15;
register16 := input24 * 24;
WHEN "00000011" =>
register1 := register2 + register1;
register2 := register4 + register3;
register3 := input25 + 25;
register4 := input26 * 26;
register5 := register6 + register5;
register6 := register8 + register7;
register7 := input27 + 27;
register8 := input28 * 28;
register9 := register10 + register9;
register10 := register12 + register11;
register11 := input29 + 29;
register12 := input30 * 30;
register13 := register14 + register13;
register14 := register16 + register15;
register15 := input31 + 31;
register16 := input32 * 32;
WHEN "00000100" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := ((NOT register2) + 1) XOR register2;
register3 := register4 + register3;
register4 := input33 * 37;
register5 := ((NOT register5) + 1) XOR register5;
register6 := ((NOT register6) + 1) XOR register6;
register7 := register8 + register7;
register8 := input34 * 42;
register9 := ((NOT register9) + 1) XOR register9;
register10 := ((NOT register10) + 1) XOR register10;
register11 := register12 + register11;
register12 := input35 * 47;
register13 := ((NOT register13) + 1) XOR register13;
register14 := ((NOT register14) + 1) XOR register14;
register15 := register16 + register15;
register16 := input36 * 52;
register17 := input37 + 53;
register18 := input38 * 54;
WHEN "00000101" =>
register1 := register2 - register1;
register2 := register4 + register3;
register3 := input39 + 55;
register4 := input40 * 56;
register5 := register6 - register5;
register6 := register8 + register7;
register7 := input41 + 57;
register8 := input42 * 58;
register9 := register10 - register9;
register10 := register12 + register11;
register11 := input43 + 59;
register12 := input44 * 60;
register13 := register14 - register13;
register14 := register16 + register15;
register15 := register18 + register17;
register16 := input45 * 61;
WHEN "00000110" =>
register1 := register1 * 63;
register2 := ((NOT register2) + 1) XOR register2;
register3 := register4 + register3;
register4 := input46 * 66;
register5 := register5 * 68;
register6 := ((NOT register6) + 1) XOR register6;
register7 := register8 + register7;
register8 := input47 * 71;
register9 := register9 * 73;
register10 := ((NOT register10) + 1) XOR register10;
register11 := register12 + register11;
register12 := input48 * 76;
register13 := register13 * 78;
register14 := ((NOT register14) + 1) XOR register14;
register15 := register16 + register15;
WHEN "00000111" =>
register1 := register2 + register1;
register2 := register4 + register3;
register3 := register6 + register5;
register4 := register8 + register7;
register5 := register10 + register9;
register6 := register12 + register11;
register7 := register14 + register13;
WHEN "00001000" =>
output1 <= register1(0 TO 1) & register15(0 TO 2);
output2 <= register3(0 TO 1) & register2(0 TO 2);
output3 <= register5(0 TO 1) & register4(0 TO 2);
output4 <= register7(0 TO 1) & register6(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesaia_alap_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/LEKO_LEKU/leku/LEKU-CD'/25_13.vhd | 1 | 57555 | Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_13x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A74: buffer std_logic
);
end x25_13x;
architecture x25_13x_behav of x25_13x is
signal a1a,a2a,a3a,a4a,a5a,a6a,a7a,a8a,a9a,a10a,a11a,a12a,a13a,a14a,a15a,a16a,a17a,a18a,a19a,a20a,a21a,a22a,a23a,a24a,a25a,a26a,a27a,a28a,a29a,a30a,a31a,a32a,a33a,a34a,a35a,a36a,a37a,a38a,a39a,a40a,a41a,a42a,a43a,a44a,a45a,a46a,a47a,a48a,a49a,a50a,a51a,a52a,a53a,a54a,a55a,a56a,a57a,a58a,a59a,a60a,a61a,a62a,a63a,a64a,a65a,a66a,a67a,a68a,a69a,a70a,a71a,a72a,a73a,a74a,a75a,a76a,a77a,a78a,a79a,a80a,a81a,a82a,a83a,a84a,a85a,a86a,a87a,a88a,a89a,a90a,a91a,a92a,a93a,a94a,a95a,a96a,a97a,a98a,a99a,a100a,a101a,a102a,a103a,a104a,a105a,a106a,a107a,a108a,a109a,a110a,a111a,a112a,a113a,a114a,a115a,a116a,a117a,a118a,a119a,a120a,a121a,a122a,a123a,a124a,a125a,a126a,a127a,a128a,a129a,a130a,a131a,a132a,a133a,a134a,a135a,a136a,a137a,a138a,a139a,a140a,a141a,a142a,a143a,a144a,a145a,a146a,a147a,a148a,a149a,a150a,a151a,a152a,a153a,a154a,a155a,a156a,a157a,a158a,a159a,a160a,a161a,a162a,a163a,a164a,a165a,a166a,a167a,a168a,a169a,a170a,a171a,a172a,a173a,a174a,a175a,a176a,a177a,a178a,a179a,a180a,a181a,a182a,a183a,a184a,a185a,a186a,a187a,a188a,a189a,a190a,a191a,a192a,a193a,a194a,a195a,a196a,a197a,a198a,a199a,a200a,a201a,a202a,a203a,a204a,a209a,a210a,a214a,a215a,a216a,a220a,a221a,a225a,a226a,a227a,a228a,a232a,a233a,a237a,a238a,a239a,a243a,a244a,a247a,a250a,a251a,a252a,a253a,a254a,a258a,a259a,a263a,a264a,a265a,a269a,a270a,a273a,a276a,a277a,a278a,a279a,a283a,a284a,a288a,a289a,a290a,a294a,a295a,a298a,a301a,a302a,a303a,a304a,a305a,a306a,a310a,a311a,a315a,a316a,a317a,a321a,a322a,a326a,a327a,a328a,a329a,a333a,a334a,a338a,a339a,a340a,a344a,a345a,a348a,a351a,a352a,a353a,a354a,a355a,a359a,a360a,a364a,a365a,a366a,a370a,a371a,a374a,a377a,a378a,a379a,a380a,a384a,a385a,a389a,a390a,a391a,a395a,a396a,a399a,a402a,a403a,a404a,a405a,a406a,a407a,a408a,a412a,a413a,a417a,a418a,a419a,a423a,a424a,a428a,a429a,a430a,a431a,a435a,a436a,a440a,a441a,a442a,a446a,a447a,a450a,a453a,a454a,a455a,a456a,a457a,a461a,a462a,a466a,a467a,a468a,a472a,a473a,a476a,a479a,a480a,a481a,a482a,a486a,a487a,a491a,a492a,a493a,a497a,a498a,a501a,a504a,a505a,a506a,a507a,a508a,a509a,a513a,a514a,a518a,a519a,a520a,a524a,a525a,a528a,a531a,a532a,a533a,a534a,a538a,a539a,a543a,a544a,a545a,a549a,a550a,a553a,a556a,a557a,a558a,a559a,a560a,a564a,a565a,a569a,a570a,a571a,a575a,a576a,a579a,a582a,a583a,a584a,a585a,a589a,a590a,a594a,a595a,a596a,a600a,a601a,a604a,a607a,a608a,a609a,a610a,a611a,a612a,a613a,a625a,a629a,a633a,a637a,a641a,a645a,a649a,a653a,a657a,a661a,a664a,a667a,a670a,a673a,a676a,a679a,a682a,a685a,a688a,a691a,a694a,a697a,a700a,a703a,a706a,a709a,a712a,a715a,a718a,a721a,a724a,a727a,a730a,a733a,a736a,a739a,a742a,a745a,a748a,a751a,a754a,a757a,a760a,a764a,a765a,a768a,a772a,a773a,a776a,a780a,a781a,a784a,a788a,a789a,a792a,a796a,a797a,a800a,a804a,a805a,a808a,a812a,a813a,a816a,a820a,a821a,a824a,a828a,a829a,a832a,a836a,a837a,a840a,a844a,a845a,a848a,a852a,a853a,a856a,a860a,a861a,a864a,a868a,a869a,a872a,a876a,a877a,a880a,a884a,a885a,a888a,a892a,a893a,a896a,a900a,a901a,a904a,a908a,a909a,a912a,a916a,a917a,a921a,a922a,a926a,a927a,a931a,a932a,a936a,a937a,a941a,a942a,a946a,a947a,a951a,a952a,a956a,a957a,a961a,a962a,a966a,a967a,a971a,a972a,a976a,a977a,a981a,a982a,a986a,a987a,a991a,a992a,a996a,a997a,a1001a,a1002a,a1006a,a1007a,a1011a,a1012a,a1016a,a1017a,a1021a,a1022a,a1026a,a1027a,a1031a,a1032a,a1036a,a1037a,a1041a,a1042a,a1046a,a1047a,a1051a,a1052a,a1056a,a1057a,a1061a,a1062a,a1066a,a1067a,a1071a,a1072a,a1076a,a1077a,a1081a,a1082a,a1086a,a1087a,a1091a,a1092a,a1096a,a1097a,a1101a,a1102a,a1106a,a1107a,a1111a,a1112a,a1116a,a1117a,a1121a,a1122a,a1126a,a1127a,a1131a,a1132a,a1136a,a1137a,a1141a,a1142a,a1146a,a1147a,a1151a,a1152a,a1156a,a1157a,a1161a,a1162a,a1166a,a1167a,a1171a,a1172a,a1176a,a1177a,a1181a,a1182a,a1185a,a1188a,a1189a,a1193a,a1194a,a1197a,a1200a,a1201a,a1205a,a1206a,a1209a,a1212a,a1213a,a1217a,a1218a,a1221a,a1224a,a1225a,a1229a,a1230a,a1233a,a1236a,a1237a,a1241a,a1242a,a1245a,a1248a,a1249a,a1253a,a1254a,a1257a,a1260a,a1261a,a1265a,a1266a,a1269a,a1272a,a1273a,a1277a,a1278a,a1281a,a1284a,a1285a,a1289a,a1290a,a1293a,a1296a,a1297a,a1301a,a1302a,a1305a,a1308a,a1309a,a1313a,a1314a,a1317a,a1320a,a1321a,a1325a,a1326a,a1329a,a1332a,a1333a,a1337a,a1338a,a1341a,a1344a,a1345a,a1349a,a1350a,a1353a,a1356a,a1357a,a1361a,a1362a,a1365a,a1368a,a1369a,a1373a,a1374a,a1377a,a1380a,a1381a,a1385a,a1386a,a1389a,a1392a,a1393a,a1397a,a1398a,a1401a,a1404a,a1405a,a1409a,a1410a,a1413a,a1416a,a1417a,a1421a,a1422a,a1425a,a1428a,a1429a,a1433a,a1434a,a1437a,a1440a,a1441a,a1445a,a1446a,a1449a,a1452a,a1453a,a1457a,a1458a,a1461a,a1464a,a1465a,a1469a,a1470a,a1473a,a1476a,a1477a,a1481a,a1482a,a1485a,a1488a,a1489a,a1493a,a1494a,a1497a,a1500a,a1501a,a1505a,a1506a,a1509a,a1512a,a1513a,a1517a,a1518a,a1521a,a1524a,a1525a,a1529a,a1530a,a1533a,a1536a,a1537a,a1541a,a1542a,a1545a,a1548a,a1549a,a1553a,a1554a,a1557a,a1560a,a1561a,a1565a,a1566a,a1569a,a1572a,a1573a,a1577a,a1578a,a1581a,a1584a,a1585a,a1589a,a1590a,a1593a,a1596a,a1597a,a1601a,a1602a,a1605a,a1608a,a1609a,a1613a,a1614a,a1617a,a1620a,a1621a,a1625a,a1626a,a1629a,a1632a,a1633a,a1637a,a1638a,a1641a,a1644a,a1645a,a1649a,a1650a,a1653a,a1656a,a1657a,a1660a,a1663a,a1664a,a1667a,a1670a,a1671a,a1674a,a1677a,a1678a,a1681a,a1684a,a1685a,a1688a,a1691a,a1692a,a1695a,a1698a,a1699a,a1702a,a1705a,a1706a,a1709a,a1712a,a1713a,a1716a,a1719a,a1720a,a1723a,a1726a,a1727a,a1730a,a1733a,a1734a,a1737a,a1740a,a1741a,a1744a,a1747a,a1748a,a1751a,a1754a,a1755a,a1758a,a1761a,a1762a,a1765a,a1768a,a1769a,a1772a,a1775a,a1776a,a1779a,a1782a,a1783a,a1786a,a1789a,a1790a,a1793a,a1796a,a1797a,a1800a,a1803a,a1804a,a1807a,a1810a,a1811a,a1814a,a1817a,a1818a,a1821a,a1824a,a1825a,a1828a,a1831a,a1832a,a1835a,a1838a,a1839a,a1842a,a1845a,a1846a,a1849a,a1852a,a1853a,a1856a,a1859a,a1860a,a1863a,a1866a,a1867a,a1870a,a1873a,a1874a,a1877a,a1880a,a1881a,a1884a,a1887a,a1888a,a1891a,a1894a,a1895a,a1898a,a1901a,a1902a,a1905a,a1908a,a1909a,a1912a,a1915a,a1916a,a1919a,a1922a,a1923a,a1926a,a1929a,a1930a,a1933a,a1936a,a1937a,a1940a,a1943a,a1944a,a1947a,a1950a,a1951a,a1954a,a1957a,a1958a,a1961a,a1964a,a1965a,a1968a,a1971a,a1972a,a1975a,a1978a,a1979a,a1982a,a1985a,a1986a,a1989a,a1992a,a1993a,a1996a,a1999a,a2000a,a2003a,a2006a,a2007a,a2010a,a2013a,a2014a,a2017a,a2020a,a2021a,a2024a,a2027a,a2028a,a2031a,a2034a,a2035a,a2038a,a2041a,a2042a,a2045a,a2048a,a2049a,a2052a,a2055a,a2056a,a2059a,a2062a,a2063a,a2066a,a2069a,a2070a,a2073a,a2076a,a2077a,a2080a,a2083a,a2084a,a2087a,a2090a,a2091a,a2094a,a2097a,a2098a,a2101a,a2104a,a2105a,a2108a,a2111a,a2112a,a2115a,a2118a,a2119a,a2122a,a2125a,a2126a,a2129a,a2132a,a2133a,a2136a,a2139a,a2140a,a2143a,a2146a,a2147a,a2150a,a2153a,a2154a,a2157a,a2160a,a2161a,a2164a,a2167a,a2168a,a2171a,a2174a,a2175a,a2178a,a2181a,a2182a,a2185a,a2188a,a2189a,a2192a,a2195a,a2196a,a2199a,a2202a,a2203a,a2206a,a2209a,a2210a,a2213a,a2216a,a2217a,a2220a,a2223a,a2224a,a2227a,a2230a,a2231a,a2234a,a2237a,a2238a,a2241a,a2244a,a2245a,a2248a,a2251a,a2252a,a2255a,a2258a,a2259a,a2262a,a2265a,a2266a,a2269a,a2272a,a2273a,a2276a,a2279a,a2280a,a2283a,a2286a,a2287a,a2290a,a2293a,a2294a,a2297a,a2300a,a2301a,a2304a,a2307a,a2308a,a2311a,a2314a,a2315a,a2318a,a2321a,a2322a,a2325a,a2328a,a2329a,a2332a,a2335a,a2336a,a2339a,a2343a,a2344a,a2345a,a2348a,a2351a,a2352a,a2355a,a2359a,a2360a,a2361a,a2364a,a2367a,a2368a,a2371a,a2375a,a2376a,a2377a,a2380a,a2383a,a2384a,a2387a,a2391a,a2392a,a2393a,a2396a,a2399a,a2400a,a2403a,a2407a,a2408a,a2409a,a2412a,a2415a,a2416a,a2419a,a2423a,a2424a,a2425a,a2428a,a2431a,a2432a,a2435a,a2439a,a2440a,a2441a,a2444a,a2447a,a2448a,a2451a,a2455a,a2456a,a2457a,a2460a,a2463a,a2464a,a2467a,a2471a,a2472a,a2473a,a2476a,a2479a,a2480a,a2483a,a2487a,a2488a,a2489a,a2492a,a2495a,a2496a,a2499a,a2503a,a2504a,a2505a,a2508a,a2511a,a2512a,a2515a,a2519a,a2520a,a2521a,a2524a,a2527a,a2528a,a2531a,a2535a,a2536a,a2537a,a2540a,a2543a,a2544a,a2547a,a2551a,a2552a,a2553a,a2556a,a2559a,a2560a,a2563a,a2567a,a2568a,a2569a,a2572a,a2575a,a2576a,a2579a,a2583a,a2584a,a2585a,a2588a,a2591a,a2592a,a2595a,a2599a,a2600a,a2601a,a2604a,a2607a,a2608a,a2611a,a2615a,a2616a,a2617a,a2620a,a2623a,a2624a,a2627a,a2631a,a2632a,a2633a,a2636a,a2639a,a2640a,a2643a,a2647a,a2648a,a2649a,a2652a,a2655a,a2656a,a2659a,a2663a,a2664a,a2665a,a2668a,a2671a,a2672a,a2675a,a2679a,a2680a,a2681a,a2684a,a2687a,a2688a,a2691a,a2695a,a2696a,a2697a,a2700a,a2703a,a2704a,a2707a,a2711a,a2712a,a2713a,a2716a,a2719a,a2720a,a2723a,a2727a,a2728a,a2729a,a2732a,a2735a,a2736a,a2739a,a2743a,a2744a,a2745a,a2748a,a2751a,a2752a,a2755a,a2759a,a2760a,a2761a,a2764a,a2767a,a2768a,a2771a,a2775a,a2776a,a2777a,a2780a,a2783a,a2784a,a2787a,a2791a,a2792a,a2793a,a2796a,a2799a,a2800a,a2803a,a2807a,a2808a,a2809a,a2812a,a2815a,a2816a,a2819a,a2823a,a2824a,a2825a,a2828a,a2831a,a2832a,a2835a,a2839a,a2840a,a2841a,a2844a,a2848a,a2849a,a2850a,a2853a,a2857a,a2858a,a2859a,a2862a,a2866a,a2867a,a2868a,a2871a,a2875a,a2876a,a2877a,a2880a,a2884a,a2885a,a2886a,a2889a,a2893a,a2894a,a2895a,a2898a,a2902a,a2903a,a2904a,a2907a,a2911a,a2912a,a2913a,a2916a,a2920a,a2921a,a2922a,a2925a,a2929a,a2930a,a2931a,a2934a,a2938a,a2939a,a2940a,a2943a,a2947a,a2948a,a2949a,a2952a,a2956a,a2957a,a2958a,a2961a,a2965a,a2966a,a2967a,a2970a,a2974a,a2975a,a2976a,a2979a,a2983a,a2984a,a2985a: std_logic;
begin
A74 <=( a613a ) or ( a408a );
a1a <=( a2985a and a2976a );
a2a <=( a2967a and a2958a );
a3a <=( a2949a and a2940a );
a4a <=( a2931a and a2922a );
a5a <=( a2913a and a2904a );
a6a <=( a2895a and a2886a );
a7a <=( a2877a and a2868a );
a8a <=( a2859a and a2850a );
a9a <=( a2841a and a2832a );
a10a <=( a2825a and a2816a );
a11a <=( a2809a and a2800a );
a12a <=( a2793a and a2784a );
a13a <=( a2777a and a2768a );
a14a <=( a2761a and a2752a );
a15a <=( a2745a and a2736a );
a16a <=( a2729a and a2720a );
a17a <=( a2713a and a2704a );
a18a <=( a2697a and a2688a );
a19a <=( a2681a and a2672a );
a20a <=( a2665a and a2656a );
a21a <=( a2649a and a2640a );
a22a <=( a2633a and a2624a );
a23a <=( a2617a and a2608a );
a24a <=( a2601a and a2592a );
a25a <=( a2585a and a2576a );
a26a <=( a2569a and a2560a );
a27a <=( a2553a and a2544a );
a28a <=( a2537a and a2528a );
a29a <=( a2521a and a2512a );
a30a <=( a2505a and a2496a );
a31a <=( a2489a and a2480a );
a32a <=( a2473a and a2464a );
a33a <=( a2457a and a2448a );
a34a <=( a2441a and a2432a );
a35a <=( a2425a and a2416a );
a36a <=( a2409a and a2400a );
a37a <=( a2393a and a2384a );
a38a <=( a2377a and a2368a );
a39a <=( a2361a and a2352a );
a40a <=( a2345a and a2336a );
a41a <=( a2329a and a2322a );
a42a <=( a2315a and a2308a );
a43a <=( a2301a and a2294a );
a44a <=( a2287a and a2280a );
a45a <=( a2273a and a2266a );
a46a <=( a2259a and a2252a );
a47a <=( a2245a and a2238a );
a48a <=( a2231a and a2224a );
a49a <=( a2217a and a2210a );
a50a <=( a2203a and a2196a );
a51a <=( a2189a and a2182a );
a52a <=( a2175a and a2168a );
a53a <=( a2161a and a2154a );
a54a <=( a2147a and a2140a );
a55a <=( a2133a and a2126a );
a56a <=( a2119a and a2112a );
a57a <=( a2105a and a2098a );
a58a <=( a2091a and a2084a );
a59a <=( a2077a and a2070a );
a60a <=( a2063a and a2056a );
a61a <=( a2049a and a2042a );
a62a <=( a2035a and a2028a );
a63a <=( a2021a and a2014a );
a64a <=( a2007a and a2000a );
a65a <=( a1993a and a1986a );
a66a <=( a1979a and a1972a );
a67a <=( a1965a and a1958a );
a68a <=( a1951a and a1944a );
a69a <=( a1937a and a1930a );
a70a <=( a1923a and a1916a );
a71a <=( a1909a and a1902a );
a72a <=( a1895a and a1888a );
a73a <=( a1881a and a1874a );
a74a <=( a1867a and a1860a );
a75a <=( a1853a and a1846a );
a76a <=( a1839a and a1832a );
a77a <=( a1825a and a1818a );
a78a <=( a1811a and a1804a );
a79a <=( a1797a and a1790a );
a80a <=( a1783a and a1776a );
a81a <=( a1769a and a1762a );
a82a <=( a1755a and a1748a );
a83a <=( a1741a and a1734a );
a84a <=( a1727a and a1720a );
a85a <=( a1713a and a1706a );
a86a <=( a1699a and a1692a );
a87a <=( a1685a and a1678a );
a88a <=( a1671a and a1664a );
a89a <=( a1657a and a1650a );
a90a <=( a1645a and a1638a );
a91a <=( a1633a and a1626a );
a92a <=( a1621a and a1614a );
a93a <=( a1609a and a1602a );
a94a <=( a1597a and a1590a );
a95a <=( a1585a and a1578a );
a96a <=( a1573a and a1566a );
a97a <=( a1561a and a1554a );
a98a <=( a1549a and a1542a );
a99a <=( a1537a and a1530a );
a100a <=( a1525a and a1518a );
a101a <=( a1513a and a1506a );
a102a <=( a1501a and a1494a );
a103a <=( a1489a and a1482a );
a104a <=( a1477a and a1470a );
a105a <=( a1465a and a1458a );
a106a <=( a1453a and a1446a );
a107a <=( a1441a and a1434a );
a108a <=( a1429a and a1422a );
a109a <=( a1417a and a1410a );
a110a <=( a1405a and a1398a );
a111a <=( a1393a and a1386a );
a112a <=( a1381a and a1374a );
a113a <=( a1369a and a1362a );
a114a <=( a1357a and a1350a );
a115a <=( a1345a and a1338a );
a116a <=( a1333a and a1326a );
a117a <=( a1321a and a1314a );
a118a <=( a1309a and a1302a );
a119a <=( a1297a and a1290a );
a120a <=( a1285a and a1278a );
a121a <=( a1273a and a1266a );
a122a <=( a1261a and a1254a );
a123a <=( a1249a and a1242a );
a124a <=( a1237a and a1230a );
a125a <=( a1225a and a1218a );
a126a <=( a1213a and a1206a );
a127a <=( a1201a and a1194a );
a128a <=( a1189a and a1182a );
a129a <=( a1177a and a1172a );
a130a <=( a1167a and a1162a );
a131a <=( a1157a and a1152a );
a132a <=( a1147a and a1142a );
a133a <=( a1137a and a1132a );
a134a <=( a1127a and a1122a );
a135a <=( a1117a and a1112a );
a136a <=( a1107a and a1102a );
a137a <=( a1097a and a1092a );
a138a <=( a1087a and a1082a );
a139a <=( a1077a and a1072a );
a140a <=( a1067a and a1062a );
a141a <=( a1057a and a1052a );
a142a <=( a1047a and a1042a );
a143a <=( a1037a and a1032a );
a144a <=( a1027a and a1022a );
a145a <=( a1017a and a1012a );
a146a <=( a1007a and a1002a );
a147a <=( a997a and a992a );
a148a <=( a987a and a982a );
a149a <=( a977a and a972a );
a150a <=( a967a and a962a );
a151a <=( a957a and a952a );
a152a <=( a947a and a942a );
a153a <=( a937a and a932a );
a154a <=( a927a and a922a );
a155a <=( a917a and a912a );
a156a <=( a909a and a904a );
a157a <=( a901a and a896a );
a158a <=( a893a and a888a );
a159a <=( a885a and a880a );
a160a <=( a877a and a872a );
a161a <=( a869a and a864a );
a162a <=( a861a and a856a );
a163a <=( a853a and a848a );
a164a <=( a845a and a840a );
a165a <=( a837a and a832a );
a166a <=( a829a and a824a );
a167a <=( a821a and a816a );
a168a <=( a813a and a808a );
a169a <=( a805a and a800a );
a170a <=( a797a and a792a );
a171a <=( a789a and a784a );
a172a <=( a781a and a776a );
a173a <=( a773a and a768a );
a174a <=( a765a and a760a );
a175a <=( a757a and a754a );
a176a <=( a751a and a748a );
a177a <=( a745a and a742a );
a178a <=( a739a and a736a );
a179a <=( a733a and a730a );
a180a <=( a727a and a724a );
a181a <=( a721a and a718a );
a182a <=( a715a and a712a );
a183a <=( a709a and a706a );
a184a <=( a703a and a700a );
a185a <=( a697a and a694a );
a186a <=( a691a and a688a );
a187a <=( a685a and a682a );
a188a <=( a679a and a676a );
a189a <=( a673a and a670a );
a190a <=( a667a and a664a );
a191a <=( A169 and a661a );
a192a <=( A169 and a657a );
a193a <=( A168 and a653a );
a194a <=( A168 and a649a );
a195a <=( A200 and a645a );
a196a <=( A199 and a641a );
a197a <=( A202 and a637a );
a198a <=( A202 and a633a );
a199a <=( A265 and a629a );
a200a <=( (not A265) and a625a );
a201a <=( A235 and A169 );
a202a <=( A235 and A202 );
a203a <=( A267 and A266 );
a204a <=( A267 and A265 );
a209a <=( a203a ) or ( a204a );
a210a <=( A268 ) or ( a209a );
a214a <=( a200a ) or ( a201a );
a215a <=( a202a ) or ( a214a );
a216a <=( a215a ) or ( a210a );
a220a <=( a197a ) or ( a198a );
a221a <=( a199a ) or ( a220a );
a225a <=( a194a ) or ( a195a );
a226a <=( a196a ) or ( a225a );
a227a <=( a226a ) or ( a221a );
a228a <=( a227a ) or ( a216a );
a232a <=( a191a ) or ( a192a );
a233a <=( a193a ) or ( a232a );
a237a <=( a188a ) or ( a189a );
a238a <=( a190a ) or ( a237a );
a239a <=( a238a ) or ( a233a );
a243a <=( a185a ) or ( a186a );
a244a <=( a187a ) or ( a243a );
a247a <=( a183a ) or ( a184a );
a250a <=( a181a ) or ( a182a );
a251a <=( a250a ) or ( a247a );
a252a <=( a251a ) or ( a244a );
a253a <=( a252a ) or ( a239a );
a254a <=( a253a ) or ( a228a );
a258a <=( a178a ) or ( a179a );
a259a <=( a180a ) or ( a258a );
a263a <=( a175a ) or ( a176a );
a264a <=( a177a ) or ( a263a );
a265a <=( a264a ) or ( a259a );
a269a <=( a172a ) or ( a173a );
a270a <=( a174a ) or ( a269a );
a273a <=( a170a ) or ( a171a );
a276a <=( a168a ) or ( a169a );
a277a <=( a276a ) or ( a273a );
a278a <=( a277a ) or ( a270a );
a279a <=( a278a ) or ( a265a );
a283a <=( a165a ) or ( a166a );
a284a <=( a167a ) or ( a283a );
a288a <=( a162a ) or ( a163a );
a289a <=( a164a ) or ( a288a );
a290a <=( a289a ) or ( a284a );
a294a <=( a159a ) or ( a160a );
a295a <=( a161a ) or ( a294a );
a298a <=( a157a ) or ( a158a );
a301a <=( a155a ) or ( a156a );
a302a <=( a301a ) or ( a298a );
a303a <=( a302a ) or ( a295a );
a304a <=( a303a ) or ( a290a );
a305a <=( a304a ) or ( a279a );
a306a <=( a305a ) or ( a254a );
a310a <=( a152a ) or ( a153a );
a311a <=( a154a ) or ( a310a );
a315a <=( a149a ) or ( a150a );
a316a <=( a151a ) or ( a315a );
a317a <=( a316a ) or ( a311a );
a321a <=( a146a ) or ( a147a );
a322a <=( a148a ) or ( a321a );
a326a <=( a143a ) or ( a144a );
a327a <=( a145a ) or ( a326a );
a328a <=( a327a ) or ( a322a );
a329a <=( a328a ) or ( a317a );
a333a <=( a140a ) or ( a141a );
a334a <=( a142a ) or ( a333a );
a338a <=( a137a ) or ( a138a );
a339a <=( a139a ) or ( a338a );
a340a <=( a339a ) or ( a334a );
a344a <=( a134a ) or ( a135a );
a345a <=( a136a ) or ( a344a );
a348a <=( a132a ) or ( a133a );
a351a <=( a130a ) or ( a131a );
a352a <=( a351a ) or ( a348a );
a353a <=( a352a ) or ( a345a );
a354a <=( a353a ) or ( a340a );
a355a <=( a354a ) or ( a329a );
a359a <=( a127a ) or ( a128a );
a360a <=( a129a ) or ( a359a );
a364a <=( a124a ) or ( a125a );
a365a <=( a126a ) or ( a364a );
a366a <=( a365a ) or ( a360a );
a370a <=( a121a ) or ( a122a );
a371a <=( a123a ) or ( a370a );
a374a <=( a119a ) or ( a120a );
a377a <=( a117a ) or ( a118a );
a378a <=( a377a ) or ( a374a );
a379a <=( a378a ) or ( a371a );
a380a <=( a379a ) or ( a366a );
a384a <=( a114a ) or ( a115a );
a385a <=( a116a ) or ( a384a );
a389a <=( a111a ) or ( a112a );
a390a <=( a113a ) or ( a389a );
a391a <=( a390a ) or ( a385a );
a395a <=( a108a ) or ( a109a );
a396a <=( a110a ) or ( a395a );
a399a <=( a106a ) or ( a107a );
a402a <=( a104a ) or ( a105a );
a403a <=( a402a ) or ( a399a );
a404a <=( a403a ) or ( a396a );
a405a <=( a404a ) or ( a391a );
a406a <=( a405a ) or ( a380a );
a407a <=( a406a ) or ( a355a );
a408a <=( a407a ) or ( a306a );
a412a <=( a101a ) or ( a102a );
a413a <=( a103a ) or ( a412a );
a417a <=( a98a ) or ( a99a );
a418a <=( a100a ) or ( a417a );
a419a <=( a418a ) or ( a413a );
a423a <=( a95a ) or ( a96a );
a424a <=( a97a ) or ( a423a );
a428a <=( a92a ) or ( a93a );
a429a <=( a94a ) or ( a428a );
a430a <=( a429a ) or ( a424a );
a431a <=( a430a ) or ( a419a );
a435a <=( a89a ) or ( a90a );
a436a <=( a91a ) or ( a435a );
a440a <=( a86a ) or ( a87a );
a441a <=( a88a ) or ( a440a );
a442a <=( a441a ) or ( a436a );
a446a <=( a83a ) or ( a84a );
a447a <=( a85a ) or ( a446a );
a450a <=( a81a ) or ( a82a );
a453a <=( a79a ) or ( a80a );
a454a <=( a453a ) or ( a450a );
a455a <=( a454a ) or ( a447a );
a456a <=( a455a ) or ( a442a );
a457a <=( a456a ) or ( a431a );
a461a <=( a76a ) or ( a77a );
a462a <=( a78a ) or ( a461a );
a466a <=( a73a ) or ( a74a );
a467a <=( a75a ) or ( a466a );
a468a <=( a467a ) or ( a462a );
a472a <=( a70a ) or ( a71a );
a473a <=( a72a ) or ( a472a );
a476a <=( a68a ) or ( a69a );
a479a <=( a66a ) or ( a67a );
a480a <=( a479a ) or ( a476a );
a481a <=( a480a ) or ( a473a );
a482a <=( a481a ) or ( a468a );
a486a <=( a63a ) or ( a64a );
a487a <=( a65a ) or ( a486a );
a491a <=( a60a ) or ( a61a );
a492a <=( a62a ) or ( a491a );
a493a <=( a492a ) or ( a487a );
a497a <=( a57a ) or ( a58a );
a498a <=( a59a ) or ( a497a );
a501a <=( a55a ) or ( a56a );
a504a <=( a53a ) or ( a54a );
a505a <=( a504a ) or ( a501a );
a506a <=( a505a ) or ( a498a );
a507a <=( a506a ) or ( a493a );
a508a <=( a507a ) or ( a482a );
a509a <=( a508a ) or ( a457a );
a513a <=( a50a ) or ( a51a );
a514a <=( a52a ) or ( a513a );
a518a <=( a47a ) or ( a48a );
a519a <=( a49a ) or ( a518a );
a520a <=( a519a ) or ( a514a );
a524a <=( a44a ) or ( a45a );
a525a <=( a46a ) or ( a524a );
a528a <=( a42a ) or ( a43a );
a531a <=( a40a ) or ( a41a );
a532a <=( a531a ) or ( a528a );
a533a <=( a532a ) or ( a525a );
a534a <=( a533a ) or ( a520a );
a538a <=( a37a ) or ( a38a );
a539a <=( a39a ) or ( a538a );
a543a <=( a34a ) or ( a35a );
a544a <=( a36a ) or ( a543a );
a545a <=( a544a ) or ( a539a );
a549a <=( a31a ) or ( a32a );
a550a <=( a33a ) or ( a549a );
a553a <=( a29a ) or ( a30a );
a556a <=( a27a ) or ( a28a );
a557a <=( a556a ) or ( a553a );
a558a <=( a557a ) or ( a550a );
a559a <=( a558a ) or ( a545a );
a560a <=( a559a ) or ( a534a );
a564a <=( a24a ) or ( a25a );
a565a <=( a26a ) or ( a564a );
a569a <=( a21a ) or ( a22a );
a570a <=( a23a ) or ( a569a );
a571a <=( a570a ) or ( a565a );
a575a <=( a18a ) or ( a19a );
a576a <=( a20a ) or ( a575a );
a579a <=( a16a ) or ( a17a );
a582a <=( a14a ) or ( a15a );
a583a <=( a582a ) or ( a579a );
a584a <=( a583a ) or ( a576a );
a585a <=( a584a ) or ( a571a );
a589a <=( a11a ) or ( a12a );
a590a <=( a13a ) or ( a589a );
a594a <=( a8a ) or ( a9a );
a595a <=( a10a ) or ( a594a );
a596a <=( a595a ) or ( a590a );
a600a <=( a5a ) or ( a6a );
a601a <=( a7a ) or ( a600a );
a604a <=( a3a ) or ( a4a );
a607a <=( a1a ) or ( a2a );
a608a <=( a607a ) or ( a604a );
a609a <=( a608a ) or ( a601a );
a610a <=( a609a ) or ( a596a );
a611a <=( a610a ) or ( a585a );
a612a <=( a611a ) or ( a560a );
a613a <=( a612a ) or ( a509a );
a625a <=( A269 and A266 );
a629a <=( A269 and (not A266) );
a633a <=( A234 and A232 );
a637a <=( A234 and A233 );
a641a <=( A235 and A201 );
a645a <=( A235 and A201 );
a649a <=( A235 and A166 );
a653a <=( A235 and A167 );
a657a <=( A234 and A232 );
a661a <=( A234 and A233 );
a664a <=( (not A232) and A202 );
a667a <=( A236 and A233 );
a670a <=( A232 and A202 );
a673a <=( A236 and (not A233) );
a676a <=( A201 and A199 );
a679a <=( A234 and A232 );
a682a <=( A201 and A199 );
a685a <=( A234 and A233 );
a688a <=( A201 and A200 );
a691a <=( A234 and A232 );
a694a <=( A201 and A200 );
a697a <=( A234 and A233 );
a700a <=( A200 and (not A199) );
a703a <=( A235 and A203 );
a706a <=( (not A200) and A199 );
a709a <=( A235 and A203 );
a712a <=( A166 and A168 );
a715a <=( A234 and A232 );
a718a <=( A166 and A168 );
a721a <=( A234 and A233 );
a724a <=( A167 and A168 );
a727a <=( A234 and A232 );
a730a <=( A167 and A168 );
a733a <=( A234 and A233 );
a736a <=( A167 and A170 );
a739a <=( A235 and (not A166) );
a742a <=( (not A167) and A170 );
a745a <=( A235 and A166 );
a748a <=( (not A232) and A169 );
a751a <=( A236 and A233 );
a754a <=( A232 and A169 );
a757a <=( A236 and (not A233) );
a760a <=( A201 and A199 );
a764a <=( A236 and A233 );
a765a <=( (not A232) and a764a );
a768a <=( A201 and A199 );
a772a <=( A236 and (not A233) );
a773a <=( A232 and a772a );
a776a <=( A201 and A200 );
a780a <=( A236 and A233 );
a781a <=( (not A232) and a780a );
a784a <=( A201 and A200 );
a788a <=( A236 and (not A233) );
a789a <=( A232 and a788a );
a792a <=( A200 and (not A199) );
a796a <=( A234 and A232 );
a797a <=( A203 and a796a );
a800a <=( A200 and (not A199) );
a804a <=( A234 and A233 );
a805a <=( A203 and a804a );
a808a <=( (not A200) and A199 );
a812a <=( A234 and A232 );
a813a <=( A203 and a812a );
a816a <=( (not A200) and A199 );
a820a <=( A234 and A233 );
a821a <=( A203 and a820a );
a824a <=( A166 and A168 );
a828a <=( A236 and A233 );
a829a <=( (not A232) and a828a );
a832a <=( A166 and A168 );
a836a <=( A236 and (not A233) );
a837a <=( A232 and a836a );
a840a <=( A167 and A168 );
a844a <=( A236 and A233 );
a845a <=( (not A232) and a844a );
a848a <=( A167 and A168 );
a852a <=( A236 and (not A233) );
a853a <=( A232 and a852a );
a856a <=( A167 and A170 );
a860a <=( A234 and A232 );
a861a <=( (not A166) and a860a );
a864a <=( A167 and A170 );
a868a <=( A234 and A233 );
a869a <=( (not A166) and a868a );
a872a <=( (not A167) and A170 );
a876a <=( A234 and A232 );
a877a <=( A166 and a876a );
a880a <=( (not A167) and A170 );
a884a <=( A234 and A233 );
a885a <=( A166 and a884a );
a888a <=( (not A201) and A169 );
a892a <=( A301 and (not A203) );
a893a <=( (not A202) and a892a );
a896a <=( (not A199) and A169 );
a900a <=( A301 and (not A202) );
a901a <=( (not A200) and a900a );
a904a <=( (not A167) and (not A169) );
a908a <=( A301 and A202 );
a909a <=( (not A166) and a908a );
a912a <=( (not A169) and (not A170) );
a916a <=( A301 and A202 );
a917a <=( (not A168) and a916a );
a921a <=( A203 and A200 );
a922a <=( (not A199) and a921a );
a926a <=( A236 and A233 );
a927a <=( (not A232) and a926a );
a931a <=( A203 and A200 );
a932a <=( (not A199) and a931a );
a936a <=( A236 and (not A233) );
a937a <=( A232 and a936a );
a941a <=( A203 and (not A200) );
a942a <=( A199 and a941a );
a946a <=( A236 and A233 );
a947a <=( (not A232) and a946a );
a951a <=( A203 and (not A200) );
a952a <=( A199 and a951a );
a956a <=( A236 and (not A233) );
a957a <=( A232 and a956a );
a961a <=( (not A201) and A166 );
a962a <=( A168 and a961a );
a966a <=( A301 and (not A203) );
a967a <=( (not A202) and a966a );
a971a <=( (not A199) and A166 );
a972a <=( A168 and a971a );
a976a <=( A301 and (not A202) );
a977a <=( (not A200) and a976a );
a981a <=( (not A201) and A167 );
a982a <=( A168 and a981a );
a986a <=( A301 and (not A203) );
a987a <=( (not A202) and a986a );
a991a <=( (not A199) and A167 );
a992a <=( A168 and a991a );
a996a <=( A301 and (not A202) );
a997a <=( (not A200) and a996a );
a1001a <=( (not A166) and A167 );
a1002a <=( A170 and a1001a );
a1006a <=( A236 and A233 );
a1007a <=( (not A232) and a1006a );
a1011a <=( (not A166) and A167 );
a1012a <=( A170 and a1011a );
a1016a <=( A236 and (not A233) );
a1017a <=( A232 and a1016a );
a1021a <=( A166 and (not A167) );
a1022a <=( A170 and a1021a );
a1026a <=( A236 and A233 );
a1027a <=( (not A232) and a1026a );
a1031a <=( A166 and (not A167) );
a1032a <=( A170 and a1031a );
a1036a <=( A236 and (not A233) );
a1037a <=( A232 and a1036a );
a1041a <=( (not A202) and (not A201) );
a1042a <=( A169 and a1041a );
a1046a <=( A300 and A299 );
a1047a <=( (not A203) and a1046a );
a1051a <=( (not A202) and (not A201) );
a1052a <=( A169 and a1051a );
a1056a <=( A300 and A298 );
a1057a <=( (not A203) and a1056a );
a1061a <=( A200 and A199 );
a1062a <=( A169 and a1061a );
a1066a <=( A301 and (not A202) );
a1067a <=( (not A201) and a1066a );
a1071a <=( (not A200) and (not A199) );
a1072a <=( A169 and a1071a );
a1076a <=( A300 and A299 );
a1077a <=( (not A202) and a1076a );
a1081a <=( (not A200) and (not A199) );
a1082a <=( A169 and a1081a );
a1086a <=( A300 and A298 );
a1087a <=( (not A202) and a1086a );
a1091a <=( (not A166) and (not A167) );
a1092a <=( (not A169) and a1091a );
a1096a <=( A300 and A299 );
a1097a <=( A202 and a1096a );
a1101a <=( (not A166) and (not A167) );
a1102a <=( (not A169) and a1101a );
a1106a <=( A300 and A298 );
a1107a <=( A202 and a1106a );
a1111a <=( (not A166) and (not A167) );
a1112a <=( (not A169) and a1111a );
a1116a <=( A301 and A201 );
a1117a <=( A199 and a1116a );
a1121a <=( (not A166) and (not A167) );
a1122a <=( (not A169) and a1121a );
a1126a <=( A301 and A201 );
a1127a <=( A200 and a1126a );
a1131a <=( A167 and (not A168) );
a1132a <=( (not A169) and a1131a );
a1136a <=( A301 and A202 );
a1137a <=( A166 and a1136a );
a1141a <=( (not A168) and (not A169) );
a1142a <=( (not A170) and a1141a );
a1146a <=( A300 and A299 );
a1147a <=( A202 and a1146a );
a1151a <=( (not A168) and (not A169) );
a1152a <=( (not A170) and a1151a );
a1156a <=( A300 and A298 );
a1157a <=( A202 and a1156a );
a1161a <=( (not A168) and (not A169) );
a1162a <=( (not A170) and a1161a );
a1166a <=( A301 and A201 );
a1167a <=( A199 and a1166a );
a1171a <=( (not A168) and (not A169) );
a1172a <=( (not A170) and a1171a );
a1176a <=( A301 and A201 );
a1177a <=( A200 and a1176a );
a1181a <=( (not A201) and A166 );
a1182a <=( A168 and a1181a );
a1185a <=( (not A203) and (not A202) );
a1188a <=( A300 and A299 );
a1189a <=( a1188a and a1185a );
a1193a <=( (not A201) and A166 );
a1194a <=( A168 and a1193a );
a1197a <=( (not A203) and (not A202) );
a1200a <=( A300 and A298 );
a1201a <=( a1200a and a1197a );
a1205a <=( A199 and A166 );
a1206a <=( A168 and a1205a );
a1209a <=( (not A201) and A200 );
a1212a <=( A301 and (not A202) );
a1213a <=( a1212a and a1209a );
a1217a <=( (not A199) and A166 );
a1218a <=( A168 and a1217a );
a1221a <=( (not A202) and (not A200) );
a1224a <=( A300 and A299 );
a1225a <=( a1224a and a1221a );
a1229a <=( (not A199) and A166 );
a1230a <=( A168 and a1229a );
a1233a <=( (not A202) and (not A200) );
a1236a <=( A300 and A298 );
a1237a <=( a1236a and a1233a );
a1241a <=( (not A201) and A167 );
a1242a <=( A168 and a1241a );
a1245a <=( (not A203) and (not A202) );
a1248a <=( A300 and A299 );
a1249a <=( a1248a and a1245a );
a1253a <=( (not A201) and A167 );
a1254a <=( A168 and a1253a );
a1257a <=( (not A203) and (not A202) );
a1260a <=( A300 and A298 );
a1261a <=( a1260a and a1257a );
a1265a <=( A199 and A167 );
a1266a <=( A168 and a1265a );
a1269a <=( (not A201) and A200 );
a1272a <=( A301 and (not A202) );
a1273a <=( a1272a and a1269a );
a1277a <=( (not A199) and A167 );
a1278a <=( A168 and a1277a );
a1281a <=( (not A202) and (not A200) );
a1284a <=( A300 and A299 );
a1285a <=( a1284a and a1281a );
a1289a <=( (not A199) and A167 );
a1290a <=( A168 and a1289a );
a1293a <=( (not A202) and (not A200) );
a1296a <=( A300 and A298 );
a1297a <=( a1296a and a1293a );
a1301a <=( (not A166) and A167 );
a1302a <=( A170 and a1301a );
a1305a <=( (not A202) and (not A201) );
a1308a <=( A301 and (not A203) );
a1309a <=( a1308a and a1305a );
a1313a <=( (not A166) and A167 );
a1314a <=( A170 and a1313a );
a1317a <=( (not A200) and (not A199) );
a1320a <=( A301 and (not A202) );
a1321a <=( a1320a and a1317a );
a1325a <=( A166 and (not A167) );
a1326a <=( A170 and a1325a );
a1329a <=( (not A202) and (not A201) );
a1332a <=( A301 and (not A203) );
a1333a <=( a1332a and a1329a );
a1337a <=( A166 and (not A167) );
a1338a <=( A170 and a1337a );
a1341a <=( (not A200) and (not A199) );
a1344a <=( A301 and (not A202) );
a1345a <=( a1344a and a1341a );
a1349a <=( (not A202) and (not A201) );
a1350a <=( A169 and a1349a );
a1353a <=( A298 and (not A203) );
a1356a <=( A302 and (not A299) );
a1357a <=( a1356a and a1353a );
a1361a <=( (not A202) and (not A201) );
a1362a <=( A169 and a1361a );
a1365a <=( (not A298) and (not A203) );
a1368a <=( A302 and A299 );
a1369a <=( a1368a and a1365a );
a1373a <=( A200 and A199 );
a1374a <=( A169 and a1373a );
a1377a <=( (not A202) and (not A201) );
a1380a <=( A300 and A299 );
a1381a <=( a1380a and a1377a );
a1385a <=( A200 and A199 );
a1386a <=( A169 and a1385a );
a1389a <=( (not A202) and (not A201) );
a1392a <=( A300 and A298 );
a1393a <=( a1392a and a1389a );
a1397a <=( (not A200) and (not A199) );
a1398a <=( A169 and a1397a );
a1401a <=( A298 and (not A202) );
a1404a <=( A302 and (not A299) );
a1405a <=( a1404a and a1401a );
a1409a <=( (not A200) and (not A199) );
a1410a <=( A169 and a1409a );
a1413a <=( (not A298) and (not A202) );
a1416a <=( A302 and A299 );
a1417a <=( a1416a and a1413a );
a1421a <=( (not A166) and (not A167) );
a1422a <=( (not A169) and a1421a );
a1425a <=( A298 and A202 );
a1428a <=( A302 and (not A299) );
a1429a <=( a1428a and a1425a );
a1433a <=( (not A166) and (not A167) );
a1434a <=( (not A169) and a1433a );
a1437a <=( (not A298) and A202 );
a1440a <=( A302 and A299 );
a1441a <=( a1440a and a1437a );
a1445a <=( (not A166) and (not A167) );
a1446a <=( (not A169) and a1445a );
a1449a <=( A201 and A199 );
a1452a <=( A300 and A299 );
a1453a <=( a1452a and a1449a );
a1457a <=( (not A166) and (not A167) );
a1458a <=( (not A169) and a1457a );
a1461a <=( A201 and A199 );
a1464a <=( A300 and A298 );
a1465a <=( a1464a and a1461a );
a1469a <=( (not A166) and (not A167) );
a1470a <=( (not A169) and a1469a );
a1473a <=( A201 and A200 );
a1476a <=( A300 and A299 );
a1477a <=( a1476a and a1473a );
a1481a <=( (not A166) and (not A167) );
a1482a <=( (not A169) and a1481a );
a1485a <=( A201 and A200 );
a1488a <=( A300 and A298 );
a1489a <=( a1488a and a1485a );
a1493a <=( (not A166) and (not A167) );
a1494a <=( (not A169) and a1493a );
a1497a <=( A200 and (not A199) );
a1500a <=( A301 and A203 );
a1501a <=( a1500a and a1497a );
a1505a <=( (not A166) and (not A167) );
a1506a <=( (not A169) and a1505a );
a1509a <=( (not A200) and A199 );
a1512a <=( A301 and A203 );
a1513a <=( a1512a and a1509a );
a1517a <=( A167 and (not A168) );
a1518a <=( (not A169) and a1517a );
a1521a <=( A202 and A166 );
a1524a <=( A300 and A299 );
a1525a <=( a1524a and a1521a );
a1529a <=( A167 and (not A168) );
a1530a <=( (not A169) and a1529a );
a1533a <=( A202 and A166 );
a1536a <=( A300 and A298 );
a1537a <=( a1536a and a1533a );
a1541a <=( A167 and (not A168) );
a1542a <=( (not A169) and a1541a );
a1545a <=( A199 and A166 );
a1548a <=( A301 and A201 );
a1549a <=( a1548a and a1545a );
a1553a <=( A167 and (not A168) );
a1554a <=( (not A169) and a1553a );
a1557a <=( A200 and A166 );
a1560a <=( A301 and A201 );
a1561a <=( a1560a and a1557a );
a1565a <=( (not A168) and (not A169) );
a1566a <=( (not A170) and a1565a );
a1569a <=( A298 and A202 );
a1572a <=( A302 and (not A299) );
a1573a <=( a1572a and a1569a );
a1577a <=( (not A168) and (not A169) );
a1578a <=( (not A170) and a1577a );
a1581a <=( (not A298) and A202 );
a1584a <=( A302 and A299 );
a1585a <=( a1584a and a1581a );
a1589a <=( (not A168) and (not A169) );
a1590a <=( (not A170) and a1589a );
a1593a <=( A201 and A199 );
a1596a <=( A300 and A299 );
a1597a <=( a1596a and a1593a );
a1601a <=( (not A168) and (not A169) );
a1602a <=( (not A170) and a1601a );
a1605a <=( A201 and A199 );
a1608a <=( A300 and A298 );
a1609a <=( a1608a and a1605a );
a1613a <=( (not A168) and (not A169) );
a1614a <=( (not A170) and a1613a );
a1617a <=( A201 and A200 );
a1620a <=( A300 and A299 );
a1621a <=( a1620a and a1617a );
a1625a <=( (not A168) and (not A169) );
a1626a <=( (not A170) and a1625a );
a1629a <=( A201 and A200 );
a1632a <=( A300 and A298 );
a1633a <=( a1632a and a1629a );
a1637a <=( (not A168) and (not A169) );
a1638a <=( (not A170) and a1637a );
a1641a <=( A200 and (not A199) );
a1644a <=( A301 and A203 );
a1645a <=( a1644a and a1641a );
a1649a <=( (not A168) and (not A169) );
a1650a <=( (not A170) and a1649a );
a1653a <=( (not A200) and A199 );
a1656a <=( A301 and A203 );
a1657a <=( a1656a and a1653a );
a1660a <=( A166 and A168 );
a1663a <=( (not A202) and (not A201) );
a1664a <=( a1663a and a1660a );
a1667a <=( A298 and (not A203) );
a1670a <=( A302 and (not A299) );
a1671a <=( a1670a and a1667a );
a1674a <=( A166 and A168 );
a1677a <=( (not A202) and (not A201) );
a1678a <=( a1677a and a1674a );
a1681a <=( (not A298) and (not A203) );
a1684a <=( A302 and A299 );
a1685a <=( a1684a and a1681a );
a1688a <=( A166 and A168 );
a1691a <=( A200 and A199 );
a1692a <=( a1691a and a1688a );
a1695a <=( (not A202) and (not A201) );
a1698a <=( A300 and A299 );
a1699a <=( a1698a and a1695a );
a1702a <=( A166 and A168 );
a1705a <=( A200 and A199 );
a1706a <=( a1705a and a1702a );
a1709a <=( (not A202) and (not A201) );
a1712a <=( A300 and A298 );
a1713a <=( a1712a and a1709a );
a1716a <=( A166 and A168 );
a1719a <=( (not A200) and (not A199) );
a1720a <=( a1719a and a1716a );
a1723a <=( A298 and (not A202) );
a1726a <=( A302 and (not A299) );
a1727a <=( a1726a and a1723a );
a1730a <=( A166 and A168 );
a1733a <=( (not A200) and (not A199) );
a1734a <=( a1733a and a1730a );
a1737a <=( (not A298) and (not A202) );
a1740a <=( A302 and A299 );
a1741a <=( a1740a and a1737a );
a1744a <=( A167 and A168 );
a1747a <=( (not A202) and (not A201) );
a1748a <=( a1747a and a1744a );
a1751a <=( A298 and (not A203) );
a1754a <=( A302 and (not A299) );
a1755a <=( a1754a and a1751a );
a1758a <=( A167 and A168 );
a1761a <=( (not A202) and (not A201) );
a1762a <=( a1761a and a1758a );
a1765a <=( (not A298) and (not A203) );
a1768a <=( A302 and A299 );
a1769a <=( a1768a and a1765a );
a1772a <=( A167 and A168 );
a1775a <=( A200 and A199 );
a1776a <=( a1775a and a1772a );
a1779a <=( (not A202) and (not A201) );
a1782a <=( A300 and A299 );
a1783a <=( a1782a and a1779a );
a1786a <=( A167 and A168 );
a1789a <=( A200 and A199 );
a1790a <=( a1789a and a1786a );
a1793a <=( (not A202) and (not A201) );
a1796a <=( A300 and A298 );
a1797a <=( a1796a and a1793a );
a1800a <=( A167 and A168 );
a1803a <=( (not A200) and (not A199) );
a1804a <=( a1803a and a1800a );
a1807a <=( A298 and (not A202) );
a1810a <=( A302 and (not A299) );
a1811a <=( a1810a and a1807a );
a1814a <=( A167 and A168 );
a1817a <=( (not A200) and (not A199) );
a1818a <=( a1817a and a1814a );
a1821a <=( (not A298) and (not A202) );
a1824a <=( A302 and A299 );
a1825a <=( a1824a and a1821a );
a1828a <=( A167 and A170 );
a1831a <=( (not A201) and (not A166) );
a1832a <=( a1831a and a1828a );
a1835a <=( (not A203) and (not A202) );
a1838a <=( A300 and A299 );
a1839a <=( a1838a and a1835a );
a1842a <=( A167 and A170 );
a1845a <=( (not A201) and (not A166) );
a1846a <=( a1845a and a1842a );
a1849a <=( (not A203) and (not A202) );
a1852a <=( A300 and A298 );
a1853a <=( a1852a and a1849a );
a1856a <=( A167 and A170 );
a1859a <=( A199 and (not A166) );
a1860a <=( a1859a and a1856a );
a1863a <=( (not A201) and A200 );
a1866a <=( A301 and (not A202) );
a1867a <=( a1866a and a1863a );
a1870a <=( A167 and A170 );
a1873a <=( (not A199) and (not A166) );
a1874a <=( a1873a and a1870a );
a1877a <=( (not A202) and (not A200) );
a1880a <=( A300 and A299 );
a1881a <=( a1880a and a1877a );
a1884a <=( A167 and A170 );
a1887a <=( (not A199) and (not A166) );
a1888a <=( a1887a and a1884a );
a1891a <=( (not A202) and (not A200) );
a1894a <=( A300 and A298 );
a1895a <=( a1894a and a1891a );
a1898a <=( (not A167) and A170 );
a1901a <=( (not A201) and A166 );
a1902a <=( a1901a and a1898a );
a1905a <=( (not A203) and (not A202) );
a1908a <=( A300 and A299 );
a1909a <=( a1908a and a1905a );
a1912a <=( (not A167) and A170 );
a1915a <=( (not A201) and A166 );
a1916a <=( a1915a and a1912a );
a1919a <=( (not A203) and (not A202) );
a1922a <=( A300 and A298 );
a1923a <=( a1922a and a1919a );
a1926a <=( (not A167) and A170 );
a1929a <=( A199 and A166 );
a1930a <=( a1929a and a1926a );
a1933a <=( (not A201) and A200 );
a1936a <=( A301 and (not A202) );
a1937a <=( a1936a and a1933a );
a1940a <=( (not A167) and A170 );
a1943a <=( (not A199) and A166 );
a1944a <=( a1943a and a1940a );
a1947a <=( (not A202) and (not A200) );
a1950a <=( A300 and A299 );
a1951a <=( a1950a and a1947a );
a1954a <=( (not A167) and A170 );
a1957a <=( (not A199) and A166 );
a1958a <=( a1957a and a1954a );
a1961a <=( (not A202) and (not A200) );
a1964a <=( A300 and A298 );
a1965a <=( a1964a and a1961a );
a1968a <=( A199 and A169 );
a1971a <=( (not A201) and A200 );
a1972a <=( a1971a and a1968a );
a1975a <=( A298 and (not A202) );
a1978a <=( A302 and (not A299) );
a1979a <=( a1978a and a1975a );
a1982a <=( A199 and A169 );
a1985a <=( (not A201) and A200 );
a1986a <=( a1985a and a1982a );
a1989a <=( (not A298) and (not A202) );
a1992a <=( A302 and A299 );
a1993a <=( a1992a and a1989a );
a1996a <=( (not A167) and (not A169) );
a1999a <=( A199 and (not A166) );
a2000a <=( a1999a and a1996a );
a2003a <=( A298 and A201 );
a2006a <=( A302 and (not A299) );
a2007a <=( a2006a and a2003a );
a2010a <=( (not A167) and (not A169) );
a2013a <=( A199 and (not A166) );
a2014a <=( a2013a and a2010a );
a2017a <=( (not A298) and A201 );
a2020a <=( A302 and A299 );
a2021a <=( a2020a and a2017a );
a2024a <=( (not A167) and (not A169) );
a2027a <=( A200 and (not A166) );
a2028a <=( a2027a and a2024a );
a2031a <=( A298 and A201 );
a2034a <=( A302 and (not A299) );
a2035a <=( a2034a and a2031a );
a2038a <=( (not A167) and (not A169) );
a2041a <=( A200 and (not A166) );
a2042a <=( a2041a and a2038a );
a2045a <=( (not A298) and A201 );
a2048a <=( A302 and A299 );
a2049a <=( a2048a and a2045a );
a2052a <=( (not A167) and (not A169) );
a2055a <=( (not A199) and (not A166) );
a2056a <=( a2055a and a2052a );
a2059a <=( A203 and A200 );
a2062a <=( A300 and A299 );
a2063a <=( a2062a and a2059a );
a2066a <=( (not A167) and (not A169) );
a2069a <=( (not A199) and (not A166) );
a2070a <=( a2069a and a2066a );
a2073a <=( A203 and A200 );
a2076a <=( A300 and A298 );
a2077a <=( a2076a and a2073a );
a2080a <=( (not A167) and (not A169) );
a2083a <=( A199 and (not A166) );
a2084a <=( a2083a and a2080a );
a2087a <=( A203 and (not A200) );
a2090a <=( A300 and A299 );
a2091a <=( a2090a and a2087a );
a2094a <=( (not A167) and (not A169) );
a2097a <=( A199 and (not A166) );
a2098a <=( a2097a and a2094a );
a2101a <=( A203 and (not A200) );
a2104a <=( A300 and A298 );
a2105a <=( a2104a and a2101a );
a2108a <=( (not A168) and (not A169) );
a2111a <=( A166 and A167 );
a2112a <=( a2111a and a2108a );
a2115a <=( A298 and A202 );
a2118a <=( A302 and (not A299) );
a2119a <=( a2118a and a2115a );
a2122a <=( (not A168) and (not A169) );
a2125a <=( A166 and A167 );
a2126a <=( a2125a and a2122a );
a2129a <=( (not A298) and A202 );
a2132a <=( A302 and A299 );
a2133a <=( a2132a and a2129a );
a2136a <=( (not A168) and (not A169) );
a2139a <=( A166 and A167 );
a2140a <=( a2139a and a2136a );
a2143a <=( A201 and A199 );
a2146a <=( A300 and A299 );
a2147a <=( a2146a and a2143a );
a2150a <=( (not A168) and (not A169) );
a2153a <=( A166 and A167 );
a2154a <=( a2153a and a2150a );
a2157a <=( A201 and A199 );
a2160a <=( A300 and A298 );
a2161a <=( a2160a and a2157a );
a2164a <=( (not A168) and (not A169) );
a2167a <=( A166 and A167 );
a2168a <=( a2167a and a2164a );
a2171a <=( A201 and A200 );
a2174a <=( A300 and A299 );
a2175a <=( a2174a and a2171a );
a2178a <=( (not A168) and (not A169) );
a2181a <=( A166 and A167 );
a2182a <=( a2181a and a2178a );
a2185a <=( A201 and A200 );
a2188a <=( A300 and A298 );
a2189a <=( a2188a and a2185a );
a2192a <=( (not A168) and (not A169) );
a2195a <=( A166 and A167 );
a2196a <=( a2195a and a2192a );
a2199a <=( A200 and (not A199) );
a2202a <=( A301 and A203 );
a2203a <=( a2202a and a2199a );
a2206a <=( (not A168) and (not A169) );
a2209a <=( A166 and A167 );
a2210a <=( a2209a and a2206a );
a2213a <=( (not A200) and A199 );
a2216a <=( A301 and A203 );
a2217a <=( a2216a and a2213a );
a2220a <=( (not A169) and (not A170) );
a2223a <=( A199 and (not A168) );
a2224a <=( a2223a and a2220a );
a2227a <=( A298 and A201 );
a2230a <=( A302 and (not A299) );
a2231a <=( a2230a and a2227a );
a2234a <=( (not A169) and (not A170) );
a2237a <=( A199 and (not A168) );
a2238a <=( a2237a and a2234a );
a2241a <=( (not A298) and A201 );
a2244a <=( A302 and A299 );
a2245a <=( a2244a and a2241a );
a2248a <=( (not A169) and (not A170) );
a2251a <=( A200 and (not A168) );
a2252a <=( a2251a and a2248a );
a2255a <=( A298 and A201 );
a2258a <=( A302 and (not A299) );
a2259a <=( a2258a and a2255a );
a2262a <=( (not A169) and (not A170) );
a2265a <=( A200 and (not A168) );
a2266a <=( a2265a and a2262a );
a2269a <=( (not A298) and A201 );
a2272a <=( A302 and A299 );
a2273a <=( a2272a and a2269a );
a2276a <=( (not A169) and (not A170) );
a2279a <=( (not A199) and (not A168) );
a2280a <=( a2279a and a2276a );
a2283a <=( A203 and A200 );
a2286a <=( A300 and A299 );
a2287a <=( a2286a and a2283a );
a2290a <=( (not A169) and (not A170) );
a2293a <=( (not A199) and (not A168) );
a2294a <=( a2293a and a2290a );
a2297a <=( A203 and A200 );
a2300a <=( A300 and A298 );
a2301a <=( a2300a and a2297a );
a2304a <=( (not A169) and (not A170) );
a2307a <=( A199 and (not A168) );
a2308a <=( a2307a and a2304a );
a2311a <=( A203 and (not A200) );
a2314a <=( A300 and A299 );
a2315a <=( a2314a and a2311a );
a2318a <=( (not A169) and (not A170) );
a2321a <=( A199 and (not A168) );
a2322a <=( a2321a and a2318a );
a2325a <=( A203 and (not A200) );
a2328a <=( A300 and A298 );
a2329a <=( a2328a and a2325a );
a2332a <=( A166 and A168 );
a2335a <=( A200 and A199 );
a2336a <=( a2335a and a2332a );
a2339a <=( (not A202) and (not A201) );
a2343a <=( A302 and (not A299) );
a2344a <=( A298 and a2343a );
a2345a <=( a2344a and a2339a );
a2348a <=( A166 and A168 );
a2351a <=( A200 and A199 );
a2352a <=( a2351a and a2348a );
a2355a <=( (not A202) and (not A201) );
a2359a <=( A302 and A299 );
a2360a <=( (not A298) and a2359a );
a2361a <=( a2360a and a2355a );
a2364a <=( A167 and A168 );
a2367a <=( A200 and A199 );
a2368a <=( a2367a and a2364a );
a2371a <=( (not A202) and (not A201) );
a2375a <=( A302 and (not A299) );
a2376a <=( A298 and a2375a );
a2377a <=( a2376a and a2371a );
a2380a <=( A167 and A168 );
a2383a <=( A200 and A199 );
a2384a <=( a2383a and a2380a );
a2387a <=( (not A202) and (not A201) );
a2391a <=( A302 and A299 );
a2392a <=( (not A298) and a2391a );
a2393a <=( a2392a and a2387a );
a2396a <=( A167 and A170 );
a2399a <=( (not A201) and (not A166) );
a2400a <=( a2399a and a2396a );
a2403a <=( (not A203) and (not A202) );
a2407a <=( A302 and (not A299) );
a2408a <=( A298 and a2407a );
a2409a <=( a2408a and a2403a );
a2412a <=( A167 and A170 );
a2415a <=( (not A201) and (not A166) );
a2416a <=( a2415a and a2412a );
a2419a <=( (not A203) and (not A202) );
a2423a <=( A302 and A299 );
a2424a <=( (not A298) and a2423a );
a2425a <=( a2424a and a2419a );
a2428a <=( A167 and A170 );
a2431a <=( A199 and (not A166) );
a2432a <=( a2431a and a2428a );
a2435a <=( (not A201) and A200 );
a2439a <=( A300 and A299 );
a2440a <=( (not A202) and a2439a );
a2441a <=( a2440a and a2435a );
a2444a <=( A167 and A170 );
a2447a <=( A199 and (not A166) );
a2448a <=( a2447a and a2444a );
a2451a <=( (not A201) and A200 );
a2455a <=( A300 and A298 );
a2456a <=( (not A202) and a2455a );
a2457a <=( a2456a and a2451a );
a2460a <=( A167 and A170 );
a2463a <=( (not A199) and (not A166) );
a2464a <=( a2463a and a2460a );
a2467a <=( (not A202) and (not A200) );
a2471a <=( A302 and (not A299) );
a2472a <=( A298 and a2471a );
a2473a <=( a2472a and a2467a );
a2476a <=( A167 and A170 );
a2479a <=( (not A199) and (not A166) );
a2480a <=( a2479a and a2476a );
a2483a <=( (not A202) and (not A200) );
a2487a <=( A302 and A299 );
a2488a <=( (not A298) and a2487a );
a2489a <=( a2488a and a2483a );
a2492a <=( (not A167) and A170 );
a2495a <=( (not A201) and A166 );
a2496a <=( a2495a and a2492a );
a2499a <=( (not A203) and (not A202) );
a2503a <=( A302 and (not A299) );
a2504a <=( A298 and a2503a );
a2505a <=( a2504a and a2499a );
a2508a <=( (not A167) and A170 );
a2511a <=( (not A201) and A166 );
a2512a <=( a2511a and a2508a );
a2515a <=( (not A203) and (not A202) );
a2519a <=( A302 and A299 );
a2520a <=( (not A298) and a2519a );
a2521a <=( a2520a and a2515a );
a2524a <=( (not A167) and A170 );
a2527a <=( A199 and A166 );
a2528a <=( a2527a and a2524a );
a2531a <=( (not A201) and A200 );
a2535a <=( A300 and A299 );
a2536a <=( (not A202) and a2535a );
a2537a <=( a2536a and a2531a );
a2540a <=( (not A167) and A170 );
a2543a <=( A199 and A166 );
a2544a <=( a2543a and a2540a );
a2547a <=( (not A201) and A200 );
a2551a <=( A300 and A298 );
a2552a <=( (not A202) and a2551a );
a2553a <=( a2552a and a2547a );
a2556a <=( (not A167) and A170 );
a2559a <=( (not A199) and A166 );
a2560a <=( a2559a and a2556a );
a2563a <=( (not A202) and (not A200) );
a2567a <=( A302 and (not A299) );
a2568a <=( A298 and a2567a );
a2569a <=( a2568a and a2563a );
a2572a <=( (not A167) and A170 );
a2575a <=( (not A199) and A166 );
a2576a <=( a2575a and a2572a );
a2579a <=( (not A202) and (not A200) );
a2583a <=( A302 and A299 );
a2584a <=( (not A298) and a2583a );
a2585a <=( a2584a and a2579a );
a2588a <=( (not A167) and (not A169) );
a2591a <=( (not A199) and (not A166) );
a2592a <=( a2591a and a2588a );
a2595a <=( A203 and A200 );
a2599a <=( A302 and (not A299) );
a2600a <=( A298 and a2599a );
a2601a <=( a2600a and a2595a );
a2604a <=( (not A167) and (not A169) );
a2607a <=( (not A199) and (not A166) );
a2608a <=( a2607a and a2604a );
a2611a <=( A203 and A200 );
a2615a <=( A302 and A299 );
a2616a <=( (not A298) and a2615a );
a2617a <=( a2616a and a2611a );
a2620a <=( (not A167) and (not A169) );
a2623a <=( A199 and (not A166) );
a2624a <=( a2623a and a2620a );
a2627a <=( A203 and (not A200) );
a2631a <=( A302 and (not A299) );
a2632a <=( A298 and a2631a );
a2633a <=( a2632a and a2627a );
a2636a <=( (not A167) and (not A169) );
a2639a <=( A199 and (not A166) );
a2640a <=( a2639a and a2636a );
a2643a <=( A203 and (not A200) );
a2647a <=( A302 and A299 );
a2648a <=( (not A298) and a2647a );
a2649a <=( a2648a and a2643a );
a2652a <=( (not A168) and (not A169) );
a2655a <=( A166 and A167 );
a2656a <=( a2655a and a2652a );
a2659a <=( A201 and A199 );
a2663a <=( A302 and (not A299) );
a2664a <=( A298 and a2663a );
a2665a <=( a2664a and a2659a );
a2668a <=( (not A168) and (not A169) );
a2671a <=( A166 and A167 );
a2672a <=( a2671a and a2668a );
a2675a <=( A201 and A199 );
a2679a <=( A302 and A299 );
a2680a <=( (not A298) and a2679a );
a2681a <=( a2680a and a2675a );
a2684a <=( (not A168) and (not A169) );
a2687a <=( A166 and A167 );
a2688a <=( a2687a and a2684a );
a2691a <=( A201 and A200 );
a2695a <=( A302 and (not A299) );
a2696a <=( A298 and a2695a );
a2697a <=( a2696a and a2691a );
a2700a <=( (not A168) and (not A169) );
a2703a <=( A166 and A167 );
a2704a <=( a2703a and a2700a );
a2707a <=( A201 and A200 );
a2711a <=( A302 and A299 );
a2712a <=( (not A298) and a2711a );
a2713a <=( a2712a and a2707a );
a2716a <=( (not A168) and (not A169) );
a2719a <=( A166 and A167 );
a2720a <=( a2719a and a2716a );
a2723a <=( A200 and (not A199) );
a2727a <=( A300 and A299 );
a2728a <=( A203 and a2727a );
a2729a <=( a2728a and a2723a );
a2732a <=( (not A168) and (not A169) );
a2735a <=( A166 and A167 );
a2736a <=( a2735a and a2732a );
a2739a <=( A200 and (not A199) );
a2743a <=( A300 and A298 );
a2744a <=( A203 and a2743a );
a2745a <=( a2744a and a2739a );
a2748a <=( (not A168) and (not A169) );
a2751a <=( A166 and A167 );
a2752a <=( a2751a and a2748a );
a2755a <=( (not A200) and A199 );
a2759a <=( A300 and A299 );
a2760a <=( A203 and a2759a );
a2761a <=( a2760a and a2755a );
a2764a <=( (not A168) and (not A169) );
a2767a <=( A166 and A167 );
a2768a <=( a2767a and a2764a );
a2771a <=( (not A200) and A199 );
a2775a <=( A300 and A298 );
a2776a <=( A203 and a2775a );
a2777a <=( a2776a and a2771a );
a2780a <=( (not A169) and (not A170) );
a2783a <=( (not A199) and (not A168) );
a2784a <=( a2783a and a2780a );
a2787a <=( A203 and A200 );
a2791a <=( A302 and (not A299) );
a2792a <=( A298 and a2791a );
a2793a <=( a2792a and a2787a );
a2796a <=( (not A169) and (not A170) );
a2799a <=( (not A199) and (not A168) );
a2800a <=( a2799a and a2796a );
a2803a <=( A203 and A200 );
a2807a <=( A302 and A299 );
a2808a <=( (not A298) and a2807a );
a2809a <=( a2808a and a2803a );
a2812a <=( (not A169) and (not A170) );
a2815a <=( A199 and (not A168) );
a2816a <=( a2815a and a2812a );
a2819a <=( A203 and (not A200) );
a2823a <=( A302 and (not A299) );
a2824a <=( A298 and a2823a );
a2825a <=( a2824a and a2819a );
a2828a <=( (not A169) and (not A170) );
a2831a <=( A199 and (not A168) );
a2832a <=( a2831a and a2828a );
a2835a <=( A203 and (not A200) );
a2839a <=( A302 and A299 );
a2840a <=( (not A298) and a2839a );
a2841a <=( a2840a and a2835a );
a2844a <=( A167 and A170 );
a2848a <=( A200 and A199 );
a2849a <=( (not A166) and a2848a );
a2850a <=( a2849a and a2844a );
a2853a <=( (not A202) and (not A201) );
a2857a <=( A302 and (not A299) );
a2858a <=( A298 and a2857a );
a2859a <=( a2858a and a2853a );
a2862a <=( A167 and A170 );
a2866a <=( A200 and A199 );
a2867a <=( (not A166) and a2866a );
a2868a <=( a2867a and a2862a );
a2871a <=( (not A202) and (not A201) );
a2875a <=( A302 and A299 );
a2876a <=( (not A298) and a2875a );
a2877a <=( a2876a and a2871a );
a2880a <=( (not A167) and A170 );
a2884a <=( A200 and A199 );
a2885a <=( A166 and a2884a );
a2886a <=( a2885a and a2880a );
a2889a <=( (not A202) and (not A201) );
a2893a <=( A302 and (not A299) );
a2894a <=( A298 and a2893a );
a2895a <=( a2894a and a2889a );
a2898a <=( (not A167) and A170 );
a2902a <=( A200 and A199 );
a2903a <=( A166 and a2902a );
a2904a <=( a2903a and a2898a );
a2907a <=( (not A202) and (not A201) );
a2911a <=( A302 and A299 );
a2912a <=( (not A298) and a2911a );
a2913a <=( a2912a and a2907a );
a2916a <=( (not A168) and (not A169) );
a2920a <=( (not A199) and A166 );
a2921a <=( A167 and a2920a );
a2922a <=( a2921a and a2916a );
a2925a <=( A203 and A200 );
a2929a <=( A302 and (not A299) );
a2930a <=( A298 and a2929a );
a2931a <=( a2930a and a2925a );
a2934a <=( (not A168) and (not A169) );
a2938a <=( (not A199) and A166 );
a2939a <=( A167 and a2938a );
a2940a <=( a2939a and a2934a );
a2943a <=( A203 and A200 );
a2947a <=( A302 and A299 );
a2948a <=( (not A298) and a2947a );
a2949a <=( a2948a and a2943a );
a2952a <=( (not A168) and (not A169) );
a2956a <=( A199 and A166 );
a2957a <=( A167 and a2956a );
a2958a <=( a2957a and a2952a );
a2961a <=( A203 and (not A200) );
a2965a <=( A302 and (not A299) );
a2966a <=( A298 and a2965a );
a2967a <=( a2966a and a2961a );
a2970a <=( (not A168) and (not A169) );
a2974a <=( A199 and A166 );
a2975a <=( A167 and a2974a );
a2976a <=( a2975a and a2970a );
a2979a <=( A203 and (not A200) );
a2983a <=( A302 and A299 );
a2984a <=( (not A298) and a2983a );
a2985a <=( a2984a and a2979a );
end x25_13x_behav;
| gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/2-MESA-HB/metaheurísticas/mesahb_nsga2.vhd | 1 | 2056 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:16:14)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END mesahb_nsga2_entity;
ARCHITECTURE mesahb_nsga2_description OF mesahb_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
output1 <= input1 + 1;
register1 := input2 * 2;
WHEN "00000010" =>
register2 := input3 * 3;
register1 := register1 + 5;
WHEN "00000011" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := register2 + 9;
WHEN "00000100" =>
register2 := register2 * 11;
WHEN "00000101" =>
register3 := input4 * 12;
register2 := register2 + 14;
WHEN "00000110" =>
register2 := ((NOT register2) + 1) XOR register2;
register1 := register3 * register1;
WHEN "00000111" =>
register2 := register2 * 18;
WHEN "00001000" =>
register1 := register2 + register1;
register2 := input5 * 19;
WHEN "00001001" =>
register2 := register2 + 21;
WHEN "00001010" =>
register2 := register2 * 23;
WHEN "00001011" =>
register2 := register2 + 25;
WHEN "00001100" =>
output2 <= register1(0 TO 14) & register2(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_nsga2_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/1-HAL/metaheurísticas/hal_spea2.vhd | 1 | 1546 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.09:05:51)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END hal_spea2_entity;
ARCHITECTURE hal_spea2_description OF hal_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
WHEN "00000010" =>
output1 <= register2 + 3;
register2 := input3 * 4;
IF (register1 < 5) THEN
output2 <= register1;
ELSE
output2 <= "00101";
END IF;
register1 := input4 * 6;
WHEN "00000011" =>
register1 := register2 * register1;
WHEN "00000100" =>
register1 := register1 - 8;
register2 := input5 * 9;
WHEN "00000101" =>
register2 := register2 * 11;
WHEN "00000110" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_spea2_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/6-FIR2/metaheurísticas/fir2_femo.vhd | 1 | 3225 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:51:43)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir2_femo_entity;
ARCHITECTURE fir2_femo_description OF fir2_femo_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := not input1 or input1;
register2 := not input2 or input2;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := not input3 or input3;
register3 := not input4 or input4;
register4 := not input5 or input5;
WHEN "00000011" =>
register2 := register2 + register3;
register3 := not input6 or input6;
WHEN "00000100" =>
register2 := register2 * 8;
register1 := register1 * 10;
register5 := not input7 or input7;
register3 := register4 + register3;
register4 := not input8 or input8;
WHEN "00000101" =>
register4 := register4 + register5;
register5 := not input9 or input9;
register6 := not input10 or input10;
WHEN "00000110" =>
register5 := register6 + register5;
register6 := not input11 or input11;
register4 := register4 * 17;
WHEN "00000111" =>
register1 := register1 + register4;
register4 := not input12 or input12;
register5 := register5 * 20;
register3 := register3 * 22;
WHEN "00001000" =>
register4 := register4 + register6;
register6 := not input13 or input13;
register7 := not input14 or input14;
register1 := register3 + register1;
WHEN "00001001" =>
register1 := register2 + register1;
register2 := not input15 or input15;
register3 := register7 + register6;
register6 := not input16 or input16;
register4 := register4 * 28;
WHEN "00001010" =>
register1 := register4 + register1;
WHEN "00001011" =>
register1 := register5 + register1;
register3 := register3 * 30;
register2 := register6 + register2;
WHEN "00001100" =>
register2 := register2 * 32;
register1 := register3 + register1;
WHEN "00001101" =>
register1 := register2 + register1;
WHEN "00001110" =>
output1 <= to_unsigned(2 ** to_integer(register1), 4);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir2_femo_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/4-MPEG-MV/asap-alap-random/mpegmv_random.vhd | 1 | 3134 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:37:23)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END mpegmv_random_entity;
ARCHITECTURE mpegmv_random_description OF mpegmv_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
register6 := input6 * 6;
register7 := input7 * 7;
register8 := input8 * 8;
register9 := input9 * 9;
WHEN "00000010" =>
register10 := input10 * 10;
WHEN "00000011" =>
register10 := register10 + 12;
WHEN "00000100" =>
register9 := register9 + register10;
register10 := input11 * 13;
register11 := input12 * 14;
register12 := input13 * 15;
WHEN "00000101" =>
register11 := register11 + 17;
register3 := register3 + 19;
register4 := register4 + 21;
register13 := input14 * 22;
register6 := register6 + register9;
WHEN "00000110" =>
register2 := register2 + register11;
register4 := register10 + register4;
WHEN "00000111" =>
register2 := register5 + register2;
register5 := register12 + 24;
register1 := register1 + register4;
register3 := register7 + register3;
WHEN "00001000" =>
output1 <= register13 + register5;
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001001" =>
output2 <= register1(0 TO 1) & register6(0 TO 2);
register1 := register8 + register3;
WHEN "00001010" =>
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001011" =>
output3 <= register1(0 TO 1) & register2(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_random_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/3-ARF/asap-alap-random/arf_alap.vhd | 1 | 2483 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.14:37:37)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END arf_alap_entity;
ARCHITECTURE arf_alap_description OF arf_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := register4 + register3;
WHEN "00000011" =>
register1 := register1 + 6;
register2 := register2 + 8;
WHEN "00000100" =>
register3 := register1 * 10;
register4 := register2 * 12;
register1 := register1 * 14;
register2 := register2 * 16;
WHEN "00000101" =>
register3 := register4 + register3;
register1 := register2 + register1;
WHEN "00000110" =>
register2 := register3 * 18;
register4 := register1 * 20;
register5 := input5 * 21;
register6 := input6 * 22;
register3 := register3 * 24;
register1 := register1 * 26;
register7 := input7 * 27;
register8 := input8 * 28;
WHEN "00000111" =>
register2 := register4 + register2;
register4 := register6 + register5;
register1 := register1 + register3;
register3 := register8 + register7;
WHEN "00001000" =>
output1 <= register4 + register2;
output2 <= register3 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_alap_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/3-ARF/asap-alap-random/arf_asap.vhd | 1 | 2481 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.14:37:21)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END arf_asap_entity;
ARCHITECTURE arf_asap_description OF arf_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
register6 := input6 * 6;
register7 := input7 * 7;
register8 := input8 * 8;
WHEN "00000010" =>
register1 := register4 + register1;
register2 := register2 + register8;
register3 := register6 + register3;
register4 := register7 + register5;
WHEN "00000011" =>
register1 := register1 + 10;
register3 := register3 + 12;
WHEN "00000100" =>
register5 := register1 * 14;
register1 := register1 * 16;
register6 := register3 * 18;
register3 := register3 * 20;
WHEN "00000101" =>
register5 := register6 + register5;
register1 := register3 + register1;
WHEN "00000110" =>
register3 := register5 * 22;
register5 := register5 * 24;
register6 := register1 * 26;
register1 := register1 * 28;
WHEN "00000111" =>
register3 := register3 + register6;
register1 := register5 + register1;
WHEN "00001000" =>
output1 <= register4 + register3;
output2 <= register2 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_asap_description; | gpl-3.0 |
witoldo7/puc-2 | PUC/PUC_567/PUC_2/simulation/qsim/work/cw3_vlg_sample_tst/_primary.vhd | 1 | 284 | library verilog;
use verilog.vl_types.all;
entity cw3_vlg_sample_tst is
port(
clk : in vl_logic;
DOWN : in vl_logic;
UP : in vl_logic;
sampler_tx : out vl_logic
);
end cw3_vlg_sample_tst;
| gpl-3.0 |
rhexsel/xinu-cMIPS | vhdl/packageExcp.vhd | 2 | 8656 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_WIRES.all;
package p_EXCEPTION is
type exception_type is (exNOP,
exMTC0, exMFC0, -- 2
exERET, -- 3
exEI,exDI, -- 5
exBREAK, exTRAP, exSYSCALL, -- 8
exRESV_INSTR, exWAIT, -- 10
IFaddressError,MMaddressErrorLD,MMaddressErrorST,--13
exTLBrefillIF, exTLBrefillRD, exTLBrefillWR, -- 16
exTLBdblFaultIF,exTLBdblFaultRD,exTLBdblFaultWR,-- 19
exTLBinvalIF, exTLBinvalRD, exTLBinvalWR, -- 22
exTLBmod, exOvfl, -- 24
exLL,exSC, -- 25,26 instrns handled by COP0
exEHB, -- 27
exTLBP, exTLBR, exTLBWI, exTLBWR, -- 31
exDERET, -- 32
exIBE, exDBE, -- 34
exNMI, exInterr, -- 36
invalid_exception);
attribute enum_encoding of exception_type : type is
"000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101"; -- 100110";
-- Table 8-25 Cause Register ExcCode Field, pg 95
constant cop0code_Int : reg5 := b"00000"; -- 0, interrupt=00 (CAUSE lsB)
constant cop0code_Mod : reg5 := b"00001"; -- 1, TLBmodified=x04
constant cop0code_TLBL : reg5 := b"00010"; -- 2, TLBload if/ld=x08
constant cop0code_TLBS : reg5 := b"00011"; -- 3, TLBstore if/ld=x0c
constant cop0code_AdEL : reg5 := b"00100"; -- 4, AddrError if/ld=x10
constant cop0code_AdES : reg5 := b"00101"; -- 5, AddrError store=x14
constant cop0code_IBE : reg5 := b"00110"; -- 6, BusErrorExcp if=x18
constant cop0code_DBE : reg5 := b"00111"; -- 7, BusErrorExcp ld/st=x1c
constant cop0code_Sys : reg5 := b"01000"; -- 8, syscall=x20
constant cop0code_Bp : reg5 := b"01001"; -- 9, breakpoint=x24
constant cop0code_RI : reg5 := b"01010"; -- 10, reserved instruction=x28
constant cop0code_CpU : reg5 := b"01011"; -- 11, CopUnusable excp=x2c
constant cop0code_Ov : reg5 := b"01100"; -- 12, arithmetic overflow=x30
constant cop0code_Tr : reg5 := b"01101"; -- 13, trap=x34
constant cop0code_NULL : reg5 := b"11111"; -- 1f, (no exception)=x3c
-- Table 8-1 Coprocessor 0 Registers, pg 55
constant cop0reg_Index : reg5 := b"00000"; -- 0
constant cop0reg_Random : reg5 := b"00001"; -- 1
constant cop0reg_EntryLo0 : reg5 := b"00010"; -- 2
constant cop0reg_EntryLo1 : reg5 := b"00011"; -- 3
constant cop0reg_Context : reg5 := b"00100"; -- 4
constant cop0reg_PageMask : reg5 := b"00101"; -- 5
constant cop0reg_Wired : reg5 := b"00110"; -- 6
constant cop0reg_HWREna : reg5 := b"00111"; -- 7
constant cop0reg_BadVAddr : reg5 := b"01000"; -- 8
constant cop0reg_COUNT : reg5 := b"01001"; -- 9
constant cop0reg_EntryHi : reg5 := b"01010"; -- 10
constant cop0reg_COMPARE : reg5 := b"01011"; -- 11
constant cop0reg_STATUS : reg5 := b"01100"; -- 12
constant cop0reg_CAUSE : reg5 := b"01101"; -- 13
constant cop0reg_EPC : reg5 := b"01110"; -- 14
constant cop0reg_CONFIG : reg5 := b"10000"; -- 16
constant cop0reg_LLAddr : reg5 := b"10001"; -- 17
constant cop0reg_ErrorPC : reg5 := b"11110"; -- 30
-- at exception level, kernel mode, cop0, all else disabled
constant RESET_STATUS: std_logic_vector(31 downto 0) := x"10000002";
-- COUNTER disabled, special interr vector, exceptionCode = noException
constant RESET_CAUSE: std_logic_vector(31 downto 0) := x"0880007c";
-- Table 8-19 Status Register Field Descriptions, pg 79
constant STATUS_CU3: integer := 31; -- COP-1 absent=0 (always)
constant STATUS_CU2: integer := 30; -- COP-1 absent=0 (always)
constant STATUS_CU1: integer := 29; -- COP-1 absent=0 (always)
constant STATUS_CU0: integer := 28; -- COP-0 present=1 (always)
constant STATUS_RP: integer := 27; -- reduced power=0 (always)
constant STATUS_BEV: integer := 22; -- locationVect at bootstrap=1
constant STATUS_TS: integer := 21; -- TLBmatchesSeveral=1
constant STATUS_SR: integer := 20; -- softReset=1
constant STATUS_NMI: integer := 19; -- reset/softReset=0, NMI=1
constant STATUS_IM7: integer := 15; -- hw interrupt-7 req eabled=1
constant STATUS_IM6: integer := 14; -- hw interrupt-6 req eabled=1
constant STATUS_IM5: integer := 13; -- hw interrupt-5 req eabled=1
constant STATUS_IM4: integer := 12; -- hw interrupt-4 req eabled=1
constant STATUS_IM3: integer := 11; -- hw interrupt-3 req eabled=1
constant STATUS_IM2: integer := 10; -- hw interrupt-2 req eabled=1
constant STATUS_IM1: integer := 9; -- sw interrupt-1 req eabled=1
constant STATUS_IM0: integer := 8; -- sw interrupt-0 req eabled=1
constant STATUS_SUP: integer := 4; -- in supervisor mode=1 (not used)
constant STATUS_UM: integer := 3; -- in user mode=1
constant STATUS_ERL: integer := 2; -- at error level=1
constant STATUS_EXL: integer := 1; -- at exception level=1
constant STATUS_IE: integer := 0; -- interrupt enabled=1
-- Table 8-24 Cause Register Field Descriptions, pg 92
constant CAUSE_BD: integer := 31; -- exceptn in branch-delay-slot=1
constant CAUSE_TI: integer := 30; -- timer interrupt pending=1
constant CAUSE_CE1: integer := 29; -- COP # in COP-UnusableExcp
constant CAUSE_CE0: integer := 28; -- COP # in COP-UnusableExcp
constant CAUSE_DC: integer := 27; -- COUNT reg is disabled=1
constant CAUSE_PCI: integer := 26; -- perfCounter interr pndng=1
constant CAUSE_IV: integer := 23; -- use special interrVector=1
constant CAUSE_WP: integer := 22; -- watch deferred=1 (not used)
constant CAUSE_IP7: integer := 15; -- hw interrupt-7 pending=1
constant CAUSE_IP6: integer := 14; -- hw interrupt-6 pending=1
constant CAUSE_IP5: integer := 13; -- hw interrupt-5 pending=1
constant CAUSE_IP4: integer := 12; -- hw interrupt-4 pending=1
constant CAUSE_IP3: integer := 11; -- hw interrupt-3 pending=1
constant CAUSE_IP2: integer := 10; -- hw interrupt-2 pending=1
constant CAUSE_IP1: integer := 9; -- sw interrupt-1 pending=1
constant CAUSE_IP0: integer := 8; -- sw interrupt-0 pending=1
constant CAUSE_ExcCodehi: integer := 6; -- exception code
constant CAUSE_ExcCodelo: integer := 2; -- exception code
-- Sources of Exception Handler's addresses; signal excp_PCsel
constant PCsel_EXC_none : reg3 := b"000"; -- no exception
constant PCsel_EXC_EPC : reg3 := b"001"; -- ERET
constant PCsel_EXC_0000 : reg3 := b"010"; -- TLBmiss entry point
constant PCsel_EXC_0100 : reg3 := b"011"; -- Cache Error
constant PCsel_EXC_0180 : reg3 := b"100"; -- general exception handler
constant PCsel_EXC_0200 : reg3 := b"101"; -- separate interrupt handler
constant PCsel_EXC_BFC0 : reg3 := b"110"; -- NMI or soft-reset handler
-- Sources for EPC; signal EPC_source
constant EPC_src_PC : reg3 := b"000"; -- from PC
constant EPC_src_RF : reg3 := b"001"; -- from RF pipestage
constant EPC_src_EX : reg3 := b"010"; -- from EX pipestage
constant EPC_src_MM : reg3 := b"011"; -- from MM pipestage
constant EPC_src_WB : reg3 := b"100"; -- from WB pipestage
constant EPC_src_B : reg3 := b"101"; -- from B register
end p_EXCEPTION;
-- package body p_EXCEPTION is
-- end p_EXCEPTION;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 |
rhexsel/xinu-cMIPS | xinu/zSrc/rom.vhd | 1 | 13152 | -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous ROM; MIPS executable defined as constant, word-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity fpga_ROM is
generic (LOAD_FILE_NAME : string := "prog.bin"); -- not used with FPGA
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
rdy : out std_logic; -- active in '0'
strobe : in std_logic;
addr : in reg32;
data : out reg32);
constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
subtype rom_address is natural range 0 to ((INST_MEM_SZ / 4) - 1);
end entity fpga_ROM;
architecture rtl of fpga_ROM is
component wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component single_port_rom is
generic (N_WORDS : integer);
port (address : in rom_address;
clken : in std_logic;
clock : in std_logic;
q : out std_logic_vector);
end component single_port_rom;
signal instrn : reg32;
signal index : rom_address := 0;
signal waiting, clken : std_logic;
begin -- rtl
U_BUS_WAIT: wait_states generic map (ROM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
clken <= not(sel);
-- >>2 = /4: byte addressed but word indexed
index <= to_integer(unsigned(addr((INST_ADDRS_BITS-1) downto 2)));
U_ROM: single_port_rom generic map (INST_MEM_SZ / 4)
port map (index, clken, strobe, instrn);
U_ROM_ACCESS: process (strobe,instrn,sel)
begin
if sel = '0' then
data <= instrn;
assert (index >= 0) and (index < INST_MEM_SZ/4)
report "rom index out of bounds: " & natural'image(index)
severity failure;
-- assert false -- DEBUG
-- report "romRD["& natural'image(index) &"]="& SLV32HEX(data);
else
data <= (others => 'X');
end if;
end process U_ROM_ACCESS;
end rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Adapted from Altera's design for a ROM that may be synthesized
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.p_wires.all;
entity single_port_rom is
generic (N_WORDS : integer := 32);
port (address : in natural range 0 to (N_WORDS - 1);
clken : in std_logic;
clock : in std_logic;
q : out reg32);
end entity;
architecture rtl of single_port_rom is
-- Build a 2-D array type for the RoM
subtype word_t is std_logic_vector(31 downto 0);
type memory_t is array(0 to (N_WORDS-1)) of word_t;
-- assemble.sh -v mac_lcd.s |\
-- sed -e '1,6d' -e '/^$/d' -e '/^ /!d' -e 's:\t: :g' \
-- -e 's#\(^ *[a-f0-9]*:\) *\(........\) *\(.*\)$#x"\2", -- \1 \3#' \
-- -e '$s:,: :'
constant test_prog : memory_t := (
x"00000000", -- 0: nop
x"3c0f0f00", -- 4: lui $15,0xf00
x"35ef0120", -- 8: ori $15,$15,0x120
x"24100001", -- c: li $16,1
x"adf00000", -- 10: sw $16,0($15)
x"3c040009", -- 14: lui $4,0x9
x"34848968", -- 18: ori $4,$4,0x8968
x"0c0000b7", -- 1c: jal 2dc <delay>
x"00000000", -- 20: nop
x"3c1a0f00", -- 24: lui $26,0xf00
x"375a0160", -- 28: ori $26,$26,0x160
x"24130030", -- 2c: li $19,48
x"af530000", -- 30: sw $19,0($26)
x"24040177", -- 34: li $4,375
x"0c0000b7", -- 38: jal 2dc <delay>
x"00000000", -- 3c: nop
x"24130030", -- 40: li $19,48
x"af530000", -- 44: sw $19,0($26)
x"24040177", -- 48: li $4,375
x"0c0000b7", -- 4c: jal 2dc <delay>
x"00000000", -- 50: nop
x"24130039", -- 54: li $19,57
x"af530000", -- 58: sw $19,0($26)
x"24040177", -- 5c: li $4,375
x"0c0000b7", -- 60: jal 2dc <delay>
x"00000000", -- 64: nop
x"24130014", -- 68: li $19,20
x"af530000", -- 6c: sw $19,0($26)
x"24040177", -- 70: li $4,375
x"0c0000b7", -- 74: jal 2dc <delay>
x"00000000", -- 78: nop
x"24130070", -- 7c: li $19,112
x"af530000", -- 80: sw $19,0($26)
x"24040177", -- 84: li $4,375
x"0c0000b7", -- 88: jal 2dc <delay>
x"00000000", -- 8c: nop
x"24130056", -- 90: li $19,86
x"af530000", -- 94: sw $19,0($26)
x"24040177", -- 98: li $4,375
x"0c0000b7", -- 9c: jal 2dc <delay>
x"00000000", -- a0: nop
x"2413006d", -- a4: li $19,109
x"af530000", -- a8: sw $19,0($26)
x"24040177", -- ac: li $4,375
x"0c0000b7", -- b0: jal 2dc <delay>
x"00000000", -- b4: nop
x"24100002", -- b8: li $16,2
x"adf00000", -- bc: sw $16,0($15)
x"3c0400be", -- c0: lui $4,0xbe
x"3484bc20", -- c4: ori $4,$4,0xbc20
x"0c0000b7", -- c8: jal 2dc <delay>
x"00000000", -- cc: nop
x"3c040026", -- d0: lui $4,0x26
x"348425a0", -- d4: ori $4,$4,0x25a0
x"0c0000b7", -- d8: jal 2dc <delay>
x"00000000", -- dc: nop
x"24100003", -- e0: li $16,3
x"adf00000", -- e4: sw $16,0($15)
x"3c0400be", -- e8: lui $4,0xbe
x"3484bc20", -- ec: ori $4,$4,0xbc20
x"0c0000b7", -- f0: jal 2dc <delay>
x"00000000", -- f4: nop
x"3c1a0f00", -- f8: lui $26,0xf00
x"375a0160", -- fc: ori $26,$26,0x160
x"2413000f", -- 100: li $19,15
x"af530000", -- 104: sw $19,0($26)
x"24040177", -- 108: li $4,375
x"0c0000b7", -- 10c: jal 2dc <delay>
x"00000000", -- 110: nop
x"24130006", -- 114: li $19,6
x"af530000", -- 118: sw $19,0($26)
x"24040177", -- 11c: li $4,375
x"0c0000b7", -- 120: jal 2dc <delay>
x"00000000", -- 124: nop
x"24100004", -- 128: li $16,4
x"adf00000", -- 12c: sw $16,0($15)
x"3c0400be", -- 130: lui $4,0xbe
x"3484bc20", -- 134: ori $4,$4,0xbc20
x"0c0000b7", -- 138: jal 2dc <delay>
x"00000000", -- 13c: nop
x"24130001", -- 140: li $19,1
x"af530000", -- 144: sw $19,0($26)
x"24040177", -- 148: li $4,375
x"0c0000b7", -- 14c: jal 2dc <delay>
x"00000000", -- 150: nop
x"24130080", -- 154: li $19,128
x"af530000", -- 158: sw $19,0($26)
x"24040177", -- 15c: li $4,375
x"0c0000b7", -- 160: jal 2dc <delay>
x"00000000", -- 164: nop
x"24100005", -- 168: li $16,5
x"adf00000", -- 16c: sw $16,0($15)
x"3c0400be", -- 170: lui $4,0xbe
x"3484bc20", -- 174: ori $4,$4,0xbc20
x"0c0000b7", -- 178: jal 2dc <delay>
x"00000000", -- 17c: nop
x"8f530000", -- 180: lw $19,0($26)
x"00000000", -- 184: nop
x"32730080", -- 188: andi $19,$19,0x80
x"1660fffc", -- 18c: bnez $19,180 <check>
x"00000000", -- 190: nop
x"02608021", -- 194: move $16,$19
x"adf00000", -- 198: sw $16,0($15)
x"3c0400be", -- 19c: lui $4,0xbe
x"3484bc20", -- 1a0: ori $4,$4,0xbc20
x"0c0000b7", -- 1a4: jal 2dc <delay>
x"00000000", -- 1a8: nop
x"24130080", -- 1ac: li $19,128
x"af530000", -- 1b0: sw $19,0($26)
x"24040177", -- 1b4: li $4,375
x"0c0000b7", -- 1b8: jal 2dc <delay>
x"00000000", -- 1bc: nop
x"3c046c6c", -- 1c0: lui $4,0x6c6c
x"34846548", -- 1c4: ori $4,$4,0x6548
x"0c000097", -- 1c8: jal 25c <send>
x"00000000", -- 1cc: nop
x"3c046f77", -- 1d0: lui $4,0x6f77
x"3484206f", -- 1d4: ori $4,$4,0x206f
x"0c000097", -- 1d8: jal 25c <send>
x"00000000", -- 1dc: nop
x"3c042164", -- 1e0: lui $4,0x2164
x"34846c72", -- 1e4: ori $4,$4,0x6c72
x"0c000097", -- 1e8: jal 25c <send>
x"00000000", -- 1ec: nop
x"24100007", -- 1f0: li $16,7
x"adf00000", -- 1f4: sw $16,0($15)
x"3c0400be", -- 1f8: lui $4,0xbe
x"3484bc20", -- 1fc: ori $4,$4,0xbc20
x"0c0000b7", -- 200: jal 2dc <delay>
x"00000000", -- 204: nop
x"241300c0", -- 208: li $19,192
x"af530000", -- 20c: sw $19,0($26)
x"24040177", -- 210: li $4,375
x"0c0000b7", -- 214: jal 2dc <delay>
x"00000000", -- 218: nop
x"3c046961", -- 21c: lui $4,0x6961
x"34847320", -- 220: ori $4,$4,0x7320
x"0c000097", -- 224: jal 25c <send>
x"00000000", -- 228: nop
x"3c044d63", -- 22c: lui $4,0x4d63
x"34842064", -- 230: ori $4,$4,0x2064
x"0c000097", -- 234: jal 25c <send>
x"00000000", -- 238: nop
x"3c042053", -- 23c: lui $4,0x2053
x"34845049", -- 240: ori $4,$4,0x5049
x"0c000097", -- 244: jal 25c <send>
x"00000000", -- 248: nop
x"24100008", -- 24c: li $16,8
x"adf00000", -- 250: sw $16,0($15)
x"08000095", -- 254: j 254 <end>
x"00000000", -- 258: nop
x"3c1a0f00", -- 25c: lui $26,0xf00
x"375a0160", -- 260: ori $26,$26,0x160
x"af440004", -- 264: sw $4,4($26)
x"00042202", -- 268: srl $4,$4,0x8
x"240500fa", -- 26c: li $5,250
x"24a5ffff", -- 270: addiu $5,$5,-1
x"00000000", -- 274: nop
x"14a0fffd", -- 278: bnez $5,270 <delay0>
x"00000000", -- 27c: nop
x"af440004", -- 280: sw $4,4($26)
x"00042202", -- 284: srl $4,$4,0x8
x"240500fa", -- 288: li $5,250
x"24a5ffff", -- 28c: addiu $5,$5,-1
x"00000000", -- 290: nop
x"14a0fffd", -- 294: bnez $5,28c <delay1>
x"00000000", -- 298: nop
x"af440004", -- 29c: sw $4,4($26)
x"00042202", -- 2a0: srl $4,$4,0x8
x"240500fa", -- 2a4: li $5,250
x"24a5ffff", -- 2a8: addiu $5,$5,-1
x"00000000", -- 2ac: nop
x"14a0fffd", -- 2b0: bnez $5,2a8 <delay2>
x"00000000", -- 2b4: nop
x"af440004", -- 2b8: sw $4,4($26)
x"00000000", -- 2bc: nop
x"240500fa", -- 2c0: li $5,250
x"24a5ffff", -- 2c4: addiu $5,$5,-1
x"00000000", -- 2c8: nop
x"14a0fffd", -- 2cc: bnez $5,2c4 <delay3>
x"00000000", -- 2d0: nop
x"03e00008", -- 2d4: jr $31
x"00000000", -- 2d8: nop
x"2484ffff", -- 2dc: addiu $4,$4,-1
x"00000000", -- 2e0: nop
x"1480fffd", -- 2e4: bnez $4,2dc <delay>
x"00000000", -- 2e8: nop
x"03e00008", -- 2ec: jr $31
x"00000000", -- 2f0: nop
x"00000000", -- 2f4: nop
x"00000000", -- 2f8: nop
x"00000000", -- 2fc: nop
x"00000000", -- 300: nop
x"00000000", -- 304: nop
x"00000000", -- 308: nop
x"00000000", -- 30c: nop
x"00000000", -- 310: nop
x"00000000", -- 314: nop
x"00000000", -- 318: nop
x"00000000", -- 31c: nop
x"00000000", -- 320: nop
x"00000000", -- 324: nop
x"00000000", -- 328: nop
x"00000000", -- 32c: nop
x"00000000", -- 330: nop
x"00000000", -- 334: nop
x"00000000", -- 338: nop
x"00000000", -- 33c: nop
x"00000000", -- 340: nop
x"00000000", -- 344: nop
x"00000000", -- 348: nop
x"00000000", -- 34c: nop
x"00000000", -- 350: nop
x"00000000", -- 354: nop
x"00000000", -- 358: nop
x"00000000", -- 35c: nop
x"00000000", -- 360: nop
x"00000000", -- 364: nop
x"00000000", -- 368: nop
x"00000000", -- 36c: nop
x"00000000", -- 370: nop
x"00000000", -- 374: nop
x"00000000", -- 378: nop
x"00000000", -- 37c: nop
x"00000000", -- 380: nop
x"00000000", -- 384: nop
x"00000000", -- 388: nop
x"00000000", -- 38c: nop
x"00000000", -- 390: nop
x"00000000", -- 394: nop
x"00000000", -- 398: nop
x"00000000", -- 39c: nop
x"00000000", -- 3a0: nop
x"00000000", -- 3a4: nop
x"00000000", -- 3a8: nop
x"00000000", -- 3ac: nop
x"00000000", -- 3b0: nop
x"00000000", -- 3b4: nop
x"00000000", -- 3b8: nop
x"00000000", -- 3bc: nop
x"00000000", -- 3c0: nop
x"00000000", -- 3c4: nop
x"00000000", -- 3c8: nop
x"00000000", -- 3cc: nop
x"00000000", -- 3d0: nop
x"00000000", -- 3d4: nop
x"00000000", -- 3d8: nop
x"00000000", -- 3dc: nop
x"00000000", -- 3e0: nop
x"00000000", -- 3e4: nop
x"00000000", -- 3e8: nop
x"00000000", -- 3ec: nop
x"00000000", -- 3f0: nop
x"00000000", -- 3f4: nop
x"00000000", -- 3f8: nop
x"00000000" -- 3fc: nop
);
function init_rom
return memory_t is
variable tmp : memory_t := (others => (others => '0'));
variable i_addr : integer;
begin
for addr_pos in test_prog'range loop
tmp(addr_pos) := test_prog(addr_pos);
-- i_addr := addr_pos;
end loop;
for addr_pos in test_prog'high to (N_WORDS - 1) loop
tmp(addr_pos) := x"00000000"; -- nop
end loop;
return tmp;
end init_rom;
-- Declare the ROM signal and specify a default value. Quartus II
-- will create a memory initialization file (ROM.mif) based on the
-- default value.
signal rom : memory_t := init_rom;
begin
process(clock,clken)
begin
if(clken = '1' and rising_edge(clock)) then
q <= rom(address);
end if;
end process;
end rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/4-MPEG-MV/metaheurísticas/mpegmv_ibea.vhd | 1 | 2968 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.09:04:04)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END mpegmv_ibea_entity;
ARCHITECTURE mpegmv_ibea_description OF mpegmv_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register3 := input3 * 3;
register1 := register1 + 5;
register4 := input4 * 6;
register2 := register2 + 8;
WHEN "00000011" =>
register1 := register4 + register1;
register4 := input5 * 9;
WHEN "00000100" =>
register1 := register4 + register1;
register4 := input6 * 10;
register5 := input7 * 11;
register2 := register3 + register2;
WHEN "00000101" =>
register3 := input8 * 12;
register5 := register5 + 14;
register6 := input9 * 15;
register1 := ((NOT register1) + 1) XOR register1;
register2 := register4 + register2;
WHEN "00000110" =>
register3 := register3 + 19;
register4 := input10 * 20;
register7 := input11 * 21;
WHEN "00000111" =>
register4 := register4 + register5;
register5 := input12 * 22;
output1 <= register7 + register3;
WHEN "00001000" =>
register3 := register5 + 25;
register4 := register6 + register4;
register5 := input13 * 26;
register2 := ((NOT register2) + 1) XOR register2;
register6 := input14 * 29;
WHEN "00001001" =>
register3 := register6 + register3;
output2 <= register1(0 TO 15) & register4(0 TO 15);
WHEN "00001010" =>
register1 := register5 + register3;
WHEN "00001011" =>
output3 <= register2(0 TO 15) & register1(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_ibea_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/6-FIR2/metaheurísticas/fir2_hype.vhd | 1 | 3427 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.14:51:52)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir2_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir2_hype_entity;
ARCHITECTURE fir2_hype_description OF fir2_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := not input1 or input1;
register2 := not input2 or input2;
WHEN "00000010" =>
register3 := not input3 or input3;
WHEN "00000011" =>
register1 := register3 + register1;
register3 := not input4 or input4;
register4 := not input5 or input5;
WHEN "00000100" =>
register2 := register3 + register2;
register3 := not input6 or input6;
register1 := register1 * 8;
WHEN "00000101" =>
register3 := register4 + register3;
register4 := not input7 or input7;
register2 := register2 * 11;
register5 := not input8 or input8;
WHEN "00000110" =>
register6 := not input9 or input9;
register7 := not input10 or input10;
register4 := register5 + register4;
WHEN "00000111" =>
register5 := not input11 or input11;
register8 := not input12 or input12;
register6 := register7 + register6;
register4 := register4 * 18;
WHEN "00001000" =>
register7 := not input13 or input13;
register5 := register8 + register5;
register8 := not input14 or input14;
WHEN "00001001" =>
register5 := register5 * 22;
register9 := not input15 or input15;
register7 := register7 + register8;
WHEN "00001010" =>
register7 := register7 * 25;
WHEN "00001011" =>
register5 := register7 + register5;
register6 := register6 * 27;
WHEN "00001100" =>
register2 := register2 + register5;
register3 := register3 * 29;
register5 := not input16 or input16;
WHEN "00001101" =>
register2 := register4 + register2;
WHEN "00001110" =>
register2 := register6 + register2;
register4 := register9 + register5;
WHEN "00001111" =>
register1 := register1 + register2;
register2 := register4 * 32;
WHEN "00010000" =>
register1 := register2 + register1;
WHEN "00010001" =>
register1 := register3 + register1;
WHEN "00010010" =>
output1 <= to_unsigned(2 ** to_integer(register1), 4);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir2_hype_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/3-ARF/asap-alap-random/arf_random.vhd | 1 | 2566 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.14:37:51)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END arf_random_entity;
ARCHITECTURE arf_random_description OF arf_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
WHEN "00000010" =>
register1 := register4 + register1;
register4 := input6 * 6;
WHEN "00000011" =>
register2 := register4 + register2;
register4 := input7 * 7;
register6 := input8 * 8;
WHEN "00000100" =>
register5 := register6 + register5;
WHEN "00000101" =>
register5 := register5 + 10;
WHEN "00000110" =>
register6 := register5 * 12;
register2 := register2 + 14;
register5 := register5 * 16;
WHEN "00000111" =>
register7 := register2 * 18;
WHEN "00001000" =>
register5 := register7 + register5;
register3 := register3 + register4;
WHEN "00001001" =>
register4 := register5 * 20;
register5 := register5 * 22;
register2 := register2 * 24;
WHEN "00001010" =>
register2 := register2 + register6;
WHEN "00001011" =>
register6 := register2 * 26;
WHEN "00001100" =>
register4 := register6 + register4;
register2 := register2 * 28;
WHEN "00001101" =>
register2 := register2 + register5;
WHEN "00001110" =>
output1 <= register1 + register2;
output2 <= register3 + register4;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_random_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/3-ARF/metaheurísticas/arf_spea2.vhd | 1 | 2586 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:35:18)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END arf_spea2_entity;
ARCHITECTURE arf_spea2_description OF arf_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register3 := input3 * 3;
register4 := input4 * 4;
register1 := register2 + register1;
WHEN "00000011" =>
register2 := register3 + register4;
register1 := register1 + 6;
register3 := input5 * 7;
register4 := input6 * 8;
WHEN "00000100" =>
register3 := register3 + register4;
register4 := input7 * 9;
register5 := input8 * 10;
register2 := register2 + 12;
WHEN "00000101" =>
register6 := register1 * 14;
register4 := register5 + register4;
register5 := register2 * 16;
WHEN "00000110" =>
register2 := register2 * 18;
register1 := register1 * 20;
register5 := register5 + register6;
WHEN "00000111" =>
register1 := register2 + register1;
register2 := register5 * 22;
register5 := register5 * 24;
WHEN "00001000" =>
register6 := register1 * 26;
register1 := register1 * 28;
WHEN "00001001" =>
register1 := register1 + register2;
register2 := register6 + register5;
WHEN "00001010" =>
output1 <= register4 + register2;
output2 <= register3 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_spea2_description; | gpl-3.0 |
jc38x/X38-02FO16 | benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/7-FIR1/metaheurísticas/fir1_nsga2.vhd | 1 | 3854 | -- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:29:16)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir1_nsga2_entity;
ARCHITECTURE fir1_nsga2_description OF fir1_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 and input1;
register2 := input2 and input2;
WHEN "00000010" =>
register3 := input3 and input3;
register4 := input4 and input4;
register1 := register2 * register1;
WHEN "00000011" =>
register2 := input5 and input5;
register3 := register4 * register3;
register4 := input6 and input6;
WHEN "00000100" =>
register5 := input7 and input7;
register6 := input8 and input8;
WHEN "00000101" =>
register5 := register5 * register6;
register6 := input9 and input9;
register7 := input10 and input10;
WHEN "00000110" =>
register8 := input11 and input11;
register6 := register6 * register7;
WHEN "00000111" =>
register2 := register8 * register2;
register7 := input12 and input12;
register8 := input13 and input13;
WHEN "00001000" =>
register9 := input14 and input14;
register10 := input15 and input15;
WHEN "00001001" =>
register11 := input16 and input16;
register2 := register3 + register2;
register3 := register10 * register7;
register7 := input17 and input17;
WHEN "00001010" =>
register10 := input18 and input18;
register12 := input19 and input19;
register7 := register11 * register7;
WHEN "00001011" =>
register11 := input20 and input20;
register9 := register9 * register12;
WHEN "00001100" =>
register4 := register11 * register4;
register11 := input21 and input21;
register7 := register7 + register9;
WHEN "00001101" =>
register1 := register1 + register4;
register3 := register7 + register3;
register4 := register10 * register11;
register7 := input22 and input22;
WHEN "00001110" =>
register7 := register7 * register8;
register3 := register4 + register3;
WHEN "00001111" =>
register1 := register1 + register3;
WHEN "00010000" =>
register1 := register1 + register5;
WHEN "00010001" =>
register1 := register2 + register1;
WHEN "00010010" =>
register1 := register1 + register7;
WHEN "00010011" =>
register1 := register6 + register1;
WHEN "00010100" =>
output1 <= register1 and register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir1_nsga2_description; | gpl-3.0 |
witoldo7/puc-2 | PUC/PUC_567/PUC/mod10_1.vhd | 2 | 867 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity mod10_1 is
Port ( d : out std_logic_vector(3 downto 0);
dir: in std_logic;
clko: out std_logic;
clr: in std_logic;
clk : in std_logic);
end mod10_1;
architecture Behavioral of mod10_1 is
begin
process(clk)
variable temp:std_logic_vector(3 downto 0);
begin
if(clr='1') then temp:="0000";
elsif(clk'event and(clk = '1')) then
if(dir='1')then
temp:=temp+1;
elsif(dir='0') then
temp:=temp-1;
end if;
if(temp="1010") then temp:="0000";
clko<='0';
end if;
if(temp="1111") then temp:="1001";
clko<='1';
end if;
end if;
d<=temp;
end process;
end Behavioral; | gpl-3.0 |
KANGKANGABC/ArmRobot | crc16.vhd | 1 | 3303 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 2017/05/15 15:41:40
-- Design Name:
-- Module Name: crc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity crc is
port ( clk: in std_logic;
data_in: in std_logic_vector(7 downto 0);
crc_out: out std_logic_vector(15 downto 0)
);
end crc;
architecture crc_arch of crc is
function reverse_vector(v: in std_logic_vector)
return std_logic_vector is
variable result: std_logic_vector(v'RANGE);
alias vr: std_logic_vector(v'REVERSE_RANGE) is v;
begin
for i in vr'RANGE loop
result(i) := vr(i);
end loop;
return result;
end;
function crc16( data_i: in std_logic_vector(7 downto 0);
crc_i: in std_logic_vector(15 downto 0))
return std_logic_vector is
variable crc_o: std_logic_vector(15 downto 0);
begin
crc_o(15) := crc_i(7) xor crc_i(8) xor crc_i(9) xor crc_i(10) xor crc_i(11) xor crc_i(12) xor crc_i(13) xor crc_i(14) xor crc_i(15) xor
data_i(0) xor data_i(1) xor data_i(2) xor data_i(3) xor data_i(4) xor data_i(5) xor data_i(6) xor data_i(7);
crc_o(14) := crc_i(6);
crc_o(13) := crc_i(5);
crc_o(12) := crc_i(4);
crc_o(11) := crc_i(3);
crc_o(10) := crc_i(2);
crc_o(9) := crc_i(1) xor crc_i(15) xor data_i(7);
crc_o(8) := crc_i(0) xor crc_i(14) xor crc_i(15) xor data_i(6) xor data_i(7);
crc_o(7) := crc_i(13) xor crc_i(14) xor data_i(5) xor data_i(6);
crc_o(6) := crc_i(12) xor crc_i(13) xor data_i(4) xor data_i(5);
crc_o(5) := crc_i(11) xor crc_i(12) xor data_i(3) xor data_i(4);
crc_o(4) := crc_i(10) xor crc_i(11) xor data_i(2) xor data_i(3);
crc_o(3) := crc_i(9) xor crc_i(10) xor data_i(1) xor data_i(2);
crc_o(2) := crc_i(8) xor crc_i(9) xor data_i(0) xor data_i(1);
crc_o(1) := crc_i(9) xor crc_i(10) xor crc_i(11) xor crc_i(12) xor crc_i(13) xor crc_i(14) xor crc_i(15) xor
data_i(1) xor data_i(2) xor data_i(3) xor data_i(4) xor data_i(5) xor data_i(6) xor data_i(7);
crc_o(0) := crc_i(8) xor crc_i(9) xor crc_i(10) xor crc_i(11) xor crc_i(12) xor crc_i(13) xor crc_i(14) xor crc_i(15) xor
data_i(0) xor data_i(1) xor data_i(2) xor data_i(3) xor data_i(4) xor data_i(5) xor data_i(6) xor data_i(7);
return crc_o;
end;
begin
crc_out <= crc16(data_in, x"0000");
--crc_out <= reverse_vector(crc16(reverse_vector(data_in), x"0000"));
--crc_out <= not reverse_vector(crc16(reverse_vector(data_in), x"FFFF")) not-> XOR FFFF x"FFFF"->start FFFF
end architecture crc_arch;
| gpl-3.0 |
ECE492W2014G4/G4Capstone | vhdl_simulation/reverb_component_tb.vhd | 1 | 2155 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY reverb_component_tb IS
END reverb_component_tb;
ARCHITECTURE behavior OF reverb_component_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component reverb_component
Generic (
constant data_width : positive := 16;
constant fifo_depth : positive := 11025
);
port (
clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector(data_width - 1 downto 0);
write_en : in std_logic;
reverb_en : in std_logic;
data_out : out std_logic_vector(data_width - 1 downto 0)
);
end component;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal data_in : std_logic_vector(15 downto 0) := (others => '0');
signal reverb_en : std_logic := '0';
signal write_en : std_logic := '0';
--Outputs
signal data_out : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reverb_component
PORT MAP (
clk => clk,
reset => reset,
data_in => data_in,
write_en => write_en,
reverb_en => reverb_en,
data_out => data_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Reset process
reset_proc : process
begin
wait for clk_period * 5;
reset <= '1';
wait for clk_period;
reset <= '0';
wait;
end process;
-- Write process
wr_proc : process
variable counter : unsigned (7 downto 0) := (others => '0');
begin
wait for clk_period * 10;
write_en <= '1';
reverb_en <= '1';
for i in 1 to 32 loop
counter := counter + 1;
data_in <= "00000000"&std_logic_vector(counter);
wait for clk_period * 1;
end loop;
wait for clk_period * 20;
wait;
end process;
-- Read process
-- rd_proc : process
-- begin
-- wait for clk_period;
-- reverb_en <= '1';
-- --wait for clk_period * 5;
-- --reverb_en <= '0';
-- --wait for clk_period * 5;
-- --reverb_en <= '1';
-- wait;
-- end process;
END; | gpl-3.0 |
rhexsel/cmips | cMIPS/vhdl/SDcard.vhd | 2 | 42425 | --**********************************************************************
-- Copyright (c) 2012-2014 by XESS Corp <http://www.xess.com>.
-- All rights reserved.
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 3.0 of the License, or (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library. If not, see
-- <http://www.gnu.org/licenses/>.
--**********************************************************************
--*********************************************************************
-- SD MEMORY CARD INTERFACE
--
-- Reads/writes a single or multiple blocks of data to/from an SD Flash card.
--
-- Based on XESS by by Steven J. Merrifield, June 2008:
-- http : //stevenmerrifield.com/tools/sd.vhd
--
-- Most of what I learned about interfacing to SD/SDHC cards came from here:
-- http://elm-chan.org/docs/mmc/mmc_e.html
--
-- OPERATION
--
-- Set-up:
-- First of all, you have to give the controller a clock signal on the clk_i
-- input with a higher frequency than the serial clock sent to the SD card
-- through the sclk_o output. You can set generic parameters for the
-- controller to tell it the master clock frequency (100 MHz), the SCLK
-- frequency for initialization (400 KHz), the SCLK frequency for normal
-- operation (25MHz), the size of data sectors in the Flash memory (512bytes),
-- and the type of card (either SD or SDHC). I typically use a 100 MHz
-- clock if I'm running an SD card with a 25 Mbps serial data stream.
--
-- Initialize it:
-- Pulsing the reset_i input high and then bringing it low again will make
-- the controller initialize the SD card so it will XESS in SPI mode.
-- Basically, it sends the card the commands CMD0, CMD8 and then ACMD41 (which
-- is CMD55 followed by CMD41). The busy_o output will be high during the
-- initialization and will go low once it is done.
--
-- After the initialization command sequence, the SD card will send back an R1
-- response byte. If only the IDLE bit of the R1 response is set, then the
-- controller will repeatedly re-try the ACMD41 command while busy_o remains
-- high.
--
-- If any other bit of the R1 response is set, then an error occurred. The
-- controller will stall, lower busy_o, and output the R1 response code on the
-- error_o bus. You'll have to pulse reset_i to unfreeze the controller.
--
-- If the R1 response is all zeroes (i.e., no errors occurred during the
-- initialization), then the controller will lower busy_o and wait for a
-- read or write operation from the host. The controller will only accept new
-- operations when busy_o is low.
--
-- Write data:
-- To write a data block to the SD card, the address of a block is placed
-- on the addr_i input bus and the wr_i input is raised. The address and
-- write strobe can be removed once busy_o goes high to indicate the write
-- operation is underway. The data to be written to the SD card is passed as
-- follows:
--
-- 1. The controller requests a byte of data by raising the hndShk_o output.
-- 2. The host applies the next byte to the data_i input bus and raises the
-- hndShk_i input.
-- 3. The controller accepts the byte and lowers the hndShk_o output.
-- 4. The host lowers the hndShk_i input.
--
-- This sequence of steps is repeated until all BLOCK_SIZE_G bytes of the
-- data block are passed from the host to the controller. Once all the data
-- is passed, the sector on the SD card will be written and the busy_o output
-- will be lowered.
--
-- Read data:
-- To read a block of data from the SD card, the address of a block is
-- placed on the addr_i input bus and the rd_i input is raised. The address
-- and read strobe can be removed once busy_o goes high to indicate the read
-- operation is underway. The data read from the SD card is passed to the
-- host as follows:
--
-- 1. The controller raises the hndShk_o output when the next data byte
-- is available.
-- 2. The host reads the byte from the data_o output bus and raises the
-- hndShk_i input.
-- 3. The controller lowers the hndShk_o output.
-- 4. The host lowers the hndShk_i input.
--
-- This sequence of steps is repeated until all BLOCK_SIZE_G bytes of the
-- data block are passed from the controller to the host. Once all the data
-- is read, the busy_o output will be lowered.
--
-- Handle errors:
-- If an error is detected during either a read or write operation, then the
-- controller will stall, lower busy_o, and output an error code on the
-- error_o bus. You'll have to pulse reset_i to unfreeze the controller. That
-- may seem a bit excessive, but it does guarantee that you can't ignore any
-- errors that occur.
--
-- TODO:
--
-- * Implement multi-block read and write commands.
-- * Allow host to send/receive SPI commands/data directly to
-- the SD card through the controller.
-- *********************************************************************
------------------------------------------------------------------------------
-- Commonly-used functions and constants.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package CommonPckg is
-- constant YES : std_logic := '1';
-- constant NO : std_logic := '0';
-- constant HI : std_logic := '1';
-- constant LO : std_logic := '0';
-- constant ONE : std_logic := '1';
-- constant ZERO : std_logic := '0';
constant HIZ : std_logic := 'Z';
-- FPGA chip families.
type FpgaFamily_t is (SPARTAN3A_E, SPARTAN6_E);
-- XESS FPGA boards.
type XessBoard_t is (XULA_E, XULA2_E);
-- Convert a Boolean to a std_logic.
function BooleanToStdLogic(b : in boolean) return std_logic;
-- Find the base-2 logarithm of a number.
function Log2(v : in natural) return natural;
-- Select one of two integers based on a Boolean.
function IntSelect(s : in boolean; a : in integer; b : in integer) return integer;
-- Select one of two reals based on a Boolean.
function RealSelect(s : in boolean; a : in real; b : in real) return real;
-- Convert a binary number to a graycode number.
function BinaryToGray(b : in std_logic_vector) return std_logic_vector;
-- Convert a graycode number to a binary number.
function GrayToBinary(g : in std_logic_vector) return std_logic_vector;
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package body CommonPckg is
-- Convert a Boolean to a std_logic.
function BooleanToStdLogic(b : in boolean) return std_logic is
variable s : std_logic;
begin
if b then
s := '1';
else
s := '0';
end if;
return s;
end function BooleanToStdLogic;
-- Find the base 2 logarithm of a number.
function Log2(v : in natural) return natural is
variable n : natural;
variable logn : natural;
begin
n := 1;
for i in 0 to 128 loop
logn := i;
exit when (n >= v);
n := n * 2;
end loop;
return logn;
end function Log2;
-- Select one of two integers based on a Boolean.
function IntSelect(s : in boolean; a : in integer; b : in integer) return integer is
begin
if s then
return a;
else
return b;
end if;
return a;
end function IntSelect;
-- Select one of two reals based on a Boolean.
function RealSelect(s : in boolean; a : in real; b : in real) return real is
begin
if s then
return a;
else
return b;
end if;
return a;
end function RealSelect;
-- Convert a binary number to a graycode number.
function BinaryToGray(b : in std_logic_vector) return std_logic_vector is
variable g : std_logic_vector(b'range);
begin
for i in b'low to b'high-1 loop
g(i) := b(i) xor b(i+1);
end loop;
g(b'high) := b(b'high);
return g;
end function BinaryToGray;
-- Convert a graycode number to a binary number.
function GrayToBinary(g : in std_logic_vector) return std_logic_vector is
variable b : std_logic_vector(g'range);
begin
b(b'high) := g(b'high);
for i in g'high-1 downto g'low loop
b(i) := b(i+1) xor g(i);
end loop;
return b;
end function GrayToBinary;
-- Find the maximum of two integers.
function IntMax(a : in integer; b : in integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
return a;
end function IntMax;
end package body;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.CommonPckg.all;
use work.p_wires.all;
package SdCardPckg is
type CardType_t is (SD_CARD_E, SDHC_CARD_E); -- Define the different types of SD cards.
component SdCardCtrl is
generic (
FREQ_G : real := 100.0; -- Master clock frequency (MHz).
INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz).
SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz).
BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector.
CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller.
);
port (
-- Host-side interface signals.
clk_i : in std_logic; -- Master clock.
reset_i : in std_logic := NO; -- active-high, synchronous reset.
rd_i : in std_logic := NO; -- active-high read block request.
wr_i : in std_logic := NO; -- active-high write block request.
continue_i : in std_logic := NO; -- If true, inc address and continue R/W.
addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address.
data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block.
data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block.
busy_o : out std_logic; -- High when controller is busy performing some operation.
hndShk_i : in std_logic; -- High when host has data to give or has taken data.
hndShk_o : out std_logic; -- High when controller has taken data or has data to give.
error_o : out std_logic_vector(15 downto 0) := (others => NO);
-- I/O signals to the external SD card.
cs_bo : out std_logic := HI; -- Active-low chip-select.
sclk_o : out std_logic := LO; -- Serial clock to SD card.
mosi_o : out std_logic := HI; -- Serial data output to SD card.
miso_i : in std_logic := ZERO; -- Serial data input from SD card.
state : out std_logic_vector(4 downto 0) -- state debugging only
);
end component;
end package;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.math_real.all;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.CommonPckg.all;
use work.SdCardPckg.all;
use work.p_wires.all;
entity SdCardCtrl is
generic (
FREQ_G : real := 100.0; -- Master clock frequency (MHz).
INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz).
SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz).
BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector.
CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller.
);
port (
-- Host-side interface signals.
clk_i : in std_logic; -- Master clock.
reset_i : in std_logic := NO; -- active-high, synchronous reset.
rd_i : in std_logic := NO; -- active-high read block request.
wr_i : in std_logic := NO; -- active-high write block request.
continue_i : in std_logic := NO; -- If true, inc address and continue R/W.
addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address.
data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block.
data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block.
busy_o : out std_logic; -- High when controller is busy performing some operation.
hndShk_i : in std_logic; -- High when host has data to give or has taken data.
hndShk_o : out std_logic; -- High when controller has taken data or has data to give.
error_o : out std_logic_vector(15 downto 0) := (others => NO);
-- I/O signals to the external SD card.
cs_bo : out std_logic := HI; -- Active-low chip-select.
sclk_o : out std_logic := LO; -- Serial clock to SD card.
mosi_o : out std_logic := HI; -- Serial data output to SD card.
miso_i : in std_logic := ZERO; -- Serial data input from SD card.
state : out std_logic_vector(4 downto 0) -- state debugging only
);
end entity;
architecture rtl of SdCardCtrl is
signal sclk_r : std_logic := ZERO; -- Register output drives SD card clock.
signal hndShk_r : std_logic := NO; -- Register output drives handshake output to host.
signal sd_state_dbg : integer:= 0; -- debugging only
begin
process(clk_i) -- FSM process for the SD card controller.
type FsmState_t is ( -- States of the SD card controller FSM.
START_INIT, -- 0 Send initialization clock pulses to the deselected SD card.
SEND_CMD0, -- 1 Put the SD card in the IDLE state.
CHK_CMD0_RESPONSE, -- 2 Check card's R1 response to the CMD0.
SEND_CMD8, -- 3 This command is needed to initialize SDHC cards.
GET_CMD8_RESPONSE, -- 4 Get the R7 response to CMD8.
SEND_CMD55, -- 5 Send CMD55 to the SD card.
SEND_CMD41, -- 6 Send CMD41 to the SD card.
CHK_ACMD41_RESPONSE, -- 7 Check if the SD card has left the IDLE state.
WAIT_FOR_HOST_RW, -- 8 Wait for the host to issue a read or write command.
RD_BLK, -- 9 Read a block of data from the SD card.
WR_BLK, -- 10 Write a block of data to the SD card.
WR_WAIT, -- 11 Wait for SD card to finish writing the data block.
START_TX, -- 12 Start sending command/data.
TX_BITS, -- 13 Shift out remaining command/data bits.
GET_CMD_RESPONSE, -- 14 Get the R1 response of the SD card to a command.
RX_BITS, -- 15 Receive response/data from the SD card.
DESELECT, -- 16 De-select the SD card and send some clock pulses (Must enter with sclk at zero.)
PULSE_SCLK, -- 17 Issue some clock pulses. (Must enter with sclk at zero.)
REPORT_ERROR -- 18 Report error and stall until reset.
);
attribute SYN_ENCODING of FsmState_t : type is "safe";
variable state_v : FsmState_t := START_INIT; -- Current state of the FSM.
variable rtnState_v : FsmState_t; -- State FSM returns to when FSM subroutine completes.
-- Timing constants based on the master clock frequency and the SPI SCLK frequencies.
constant CLKS_PER_INIT_SCLK_C : real := FREQ_G / INIT_SPI_FREQ_G;
constant CLKS_PER_SCLK_C : real := FREQ_G / SPI_FREQ_G;
constant MAX_CLKS_PER_SCLK_C : real := realmax(CLKS_PER_INIT_SCLK_C, CLKS_PER_SCLK_C);
constant MAX_CLKS_PER_SCLK_PHASE_C : natural := integer(round(MAX_CLKS_PER_SCLK_C / 2.0));
constant INIT_SCLK_PHASE_PERIOD_C : natural := integer(round(CLKS_PER_INIT_SCLK_C / 2.0));
constant SCLK_PHASE_PERIOD_C : natural := integer(round(CLKS_PER_SCLK_C / 2.0));
constant DELAY_BETWEEN_BLOCK_RW_C : natural := SCLK_PHASE_PERIOD_C;
-- Registers for generating slow SPI SCLK from the faster master clock.
variable clkDivider_v : natural range 0 to MAX_CLKS_PER_SCLK_PHASE_C; -- Holds the SCLK period.
variable sclkPhaseTimer_v : natural range 0 to MAX_CLKS_PER_SCLK_PHASE_C; -- Counts down to zero, then SCLK toggles.
constant NUM_INIT_CLKS_C : natural := 160; -- Number of initialization clocks to SD card.
variable bitCnt_v : natural range 0 to NUM_INIT_CLKS_C; -- Tx/Rx bit counter.
constant CRC_SZ_C : natural := 2; -- Number of CRC bytes for read/write blocks.
-- When reading blocks of data, get 0xFE + [DATA_BLOCK] + [CRC].
constant RD_BLK_SZ_C : natural := 1 + BLOCK_SIZE_G + CRC_SZ_C;
-- When writing blocks of data, send 0xFF + 0xFE + [DATA BLOCK] + [CRC] then receive response byte.
constant WR_BLK_SZ_C : natural := 1 + 1 + BLOCK_SIZE_G + CRC_SZ_C + 1;
variable byteCnt_v : natural range 0 to IntMax(WR_BLK_SZ_C, RD_BLK_SZ_C); -- Tx/Rx byte counter.
-- Command bytes for various SD card operations.
subtype Cmd_t is std_logic_vector(7 downto 0);
constant CMD0_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 0, Cmd_t'length));
constant CMD8_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 8, Cmd_t'length));
constant CMD55_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 55, Cmd_t'length));
constant CMD41_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 41, Cmd_t'length));
constant READ_BLK_CMD_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 17, Cmd_t'length));
constant WRITE_BLK_CMD_C : Cmd_t := std_logic_vector(to_unsigned(16#40# + 24, Cmd_t'length));
-- Except for CMD0 and CMD8, SD card ops don't need a CRC, so use a fake one for that slot in the command.
constant FAKE_CRC_C : std_logic_vector(7 downto 0) := x"FF";
variable addr_v : unsigned(addr_i'range); -- Address of current block for R/W operations.
-- Maximum Tx to SD card consists of command + address + CRC. Data Tx is just a single byte.
variable tx_v : std_logic_vector(CMD0_C'length + addr_v'length + FAKE_CRC_C'length - 1 downto 0); -- Data/command to SD card.
alias txCmd_v is tx_v; -- Command transmission shift register.
alias txData_v is tx_v(tx_v'high downto tx_v'high - data_i'length + 1); -- Data byte transmission shift register.
variable rx_v : std_logic_vector(data_i'range); -- Data/response byte received from SD card.
-- Various response codes.
subtype Response_t is std_logic_vector(rx_v'range);
constant ACTIVE_NO_ERRORS_C : Response_t := "00000000"; -- Normal R1 code after initialization.
constant IDLE_NO_ERRORS_C : Response_t := "00000001"; -- Normal R1 code after CMD0.
constant DATA_ACCEPTED_C : Response_t := "---00101"; -- SD card accepts data block from host.
constant DATA_REJ_CRC_C : Response_t := "---01011"; -- SD card rejects data block from host due to CRC error.
constant DATA_REJ_WERR_C : Response_t := "---01101"; -- SD card rejects data block from host due to write error.
-- Various tokens.
subtype Token_t is std_logic_vector(rx_v'range);
constant NO_TOKEN_C : Token_t := x"FF"; -- Received before the SD card responds to a block read command.
constant START_TOKEN_C : Token_t := x"FE"; -- Starting byte preceding a data block.
-- Flags that are set/cleared to affect the operation of the FSM.
variable getCmdResponse_v : boolean; -- When true, get R1 response to command sent to SD card.
variable rtnData_v : boolean; -- When true, signal to host when a data byte arrives from SD card.
variable doDeselect_v : boolean; -- When true, de-select SD card after a command is issued.
begin
sd_state_dbg <= FsmState_t'pos(state_v); -- debugging only
state <= std_logic_vector(to_unsigned(sd_state_dbg, 5));
if rising_edge(clk_i) then
if reset_i = YES then -- Perform a reset.
state_v := START_INIT; -- Send the FSM to the initialization entry-point.
sclkPhaseTimer_v := 0; -- Don't delay the initialization right after reset.
busy_o <= YES; -- Busy while the SD card interface is being initialized.
elsif sclkPhaseTimer_v /= 0 then
-- Setting the clock phase timer to a non-zero value delays any further actions
-- and generates the slower SPI clock from the faster master clock.
sclkPhaseTimer_v := sclkPhaseTimer_v - 1;
-- Clock phase timer has reached zero, so check handshaking sync. between host and controller.
-- Handshaking lets the host control the flow of data to/from the SD card controller.
-- Handshaking between the SD card controller and the host proceeds as follows:
-- 1: Controller raises its handshake and waits.
-- 2: Host sees controller handshake and raises its handshake in acknowledgement.
-- 3: Controller sees host handshake acknowledgement and lowers its handshake.
-- 4: Host sees controller lower its handshake and removes its handshake.
--
-- Handshaking is bypassed when the controller FSM is initializing the SD card.
elsif state_v /= START_INIT and hndShk_r = HI and hndShk_i = LO then
null; -- Waiting for the host to acknowledge handshake.
elsif state_v /= START_INIT and hndShk_r = HI and hndShk_i = HI then
txData_v := data_i; -- Get any data passed from the host.
hndShk_r <= LO; -- The host acknowledged, so lower the controller handshake.
elsif state_v /= START_INIT and hndShk_r = LO and hndShk_i = HI then
null; -- Waiting for the host to lower its handshake.
elsif (state_v = START_INIT) or (hndShk_r = LO and hndShk_i = LO) then
-- Both handshakes are low, so the controller operations can proceed.
busy_o <= YES; -- Busy by default. Only false when waiting for R/W from host or stalled by error.
case state_v is
when START_INIT => -- Deselect the SD card and send it a bunch of clock pulses with MOSI high.
error_o <= (others => ZERO); -- Clear error flags.
clkDivider_v := INIT_SCLK_PHASE_PERIOD_C - 1; -- Use slow SPI clock freq during init.
sclkPhaseTimer_v := INIT_SCLK_PHASE_PERIOD_C - 1; -- and set the duration of the next clock phase.
sclk_r <= LO; -- Start with low clock to the SD card.
hndShk_r <= LO; -- Initialize handshake signal.
addr_v := (others => ZERO); -- Initialize address.
rtnData_v := false; -- No data is returned to host during initialization.
bitCnt_v := NUM_INIT_CLKS_C; -- Generate this many clock pulses.
state_v := DESELECT; -- De-select the SD card and pulse SCLK.
rtnState_v := SEND_CMD0; -- Then go to this state after the clock pulses are done.
when SEND_CMD0 => -- Put the SD card in the IDLE state.
cs_bo <= LO; -- Enable the SD card.
txCmd_v := CMD0_C & x"00000000" & x"95"; -- 0x95 is the correct CRC for this command.
bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command.
getCmdResponse_v := true; -- Sending a command that generates a response.
doDeselect_v := true; -- De-select SD card after this command finishes.
state_v := START_TX; -- Go to FSM subroutine to send the command.
rtnState_v := CHK_CMD0_RESPONSE; -- Then check the response to the command.
when CHK_CMD0_RESPONSE => -- Check card's R1 response to the CMD0.
if rx_v = IDLE_NO_ERRORS_C then
state_v := SEND_CMD8; -- Continue init if SD card is in IDLE state with no errors
else
state_v := SEND_CMD0; -- Otherwise, try CMD0 again.
end if;
when SEND_CMD8 => -- This command is needed to initialize SDHC cards.
cs_bo <= LO; -- Enable the SD card.
txCmd_v := CMD8_C & x"000001aa" & x"87"; -- 0x87 is the correct CRC for this command.
bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command.
getCmdResponse_v := true; -- Sending a command that generates a response.
doDeselect_v := false; -- Don't de-select, need to get the R7 response sent from the SD card.
state_v := START_TX; -- Go to FSM subroutine to send the command.
rtnState_v := GET_CMD8_RESPONSE; -- Then go to this state after the command is sent.
when GET_CMD8_RESPONSE => -- Get the R7 response to CMD8.
cs_bo <= LO; -- The SD card should already be enabled, but let's be explicit.
bitCnt_v := 31; -- Four bytes (32 bits) in R7 response.
getCmdResponse_v := false; -- Not sending a command that generates a response.
doDeselect_v := true; -- De-select card to end the command after getting the four bytes.
state_v := RX_BITS; -- Go to FSM subroutine to get the R7 response.
rtnState_v := SEND_CMD55; -- Then go here (we don't care what the actual R7 response is).
when SEND_CMD55 => -- Send CMD55 as preamble of ACMD41 initialization command.
cs_bo <= LO; -- Enable the SD card.
txCmd_v := CMD55_C & x"00000000" & FAKE_CRC_C;
bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command.
getCmdResponse_v := true; -- Sending a command that generates a response.
doDeselect_v := true; -- De-select SD card after this command finishes.
state_v := START_TX; -- Go to FSM subroutine to send the command.
rtnState_v := SEND_CMD41; -- Then go to this state after the command is sent.
when SEND_CMD41 => -- Send the SD card the initialization command.
cs_bo <= LO; -- Enable the SD card.
txCmd_v := CMD41_C & x"40000000" & FAKE_CRC_C;
bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command.
getCmdResponse_v := true; -- Sending a command that generates a response.
doDeselect_v := true; -- De-select SD card after this command finishes.
state_v := START_TX; -- Go to FSM subroutine to send the command.
rtnState_v := CHK_ACMD41_RESPONSE; -- Then check the response to the command.
when CHK_ACMD41_RESPONSE =>
-- The CMD55, CMD41 sequence should cause the SD card to leave the IDLE state
-- and become ready for SPI read/write operations. If still IDLE, then repeat the CMD55, CMD41 sequence.
-- If one of the R1 error flags is set, then report the error and stall.
if rx_v = ACTIVE_NO_ERRORS_C then -- Not IDLE, no errors.
state_v := WAIT_FOR_HOST_RW; -- Start processing R/W commands from the host.
elsif rx_v = IDLE_NO_ERRORS_C then -- Still IDLE but no errors.
state_v := SEND_CMD55; -- Repeat the CMD55, CMD41 sequence.
else -- Some error occurred.
state_v := REPORT_ERROR; -- Report the error and stall.
end if;
when WAIT_FOR_HOST_RW => -- Wait for the host to read or write a block of data from the SD card.
clkDivider_v := SCLK_PHASE_PERIOD_C - 1; -- Set SPI clock frequency for normal operation.
getCmdResponse_v := true; -- Get R1 response to any commands issued to the SD card.
if rd_i = YES then -- send READ command and address to the SD card.
cs_bo <= LO; -- Enable the SD card.
if continue_i = YES then -- Multi-block read. Use stored address.
if CARD_TYPE_G = SD_CARD_E then -- SD cards use byte-addressing,
addr_v := addr_v + BLOCK_SIZE_G; -- so add block-size to get next block address.
else -- SDHC cards use block-addressing,
addr_v := addr_v + 1; -- so just increment current block address.
end if;
txCmd_v := READ_BLK_CMD_C & std_logic_vector(addr_v) & FAKE_CRC_C;
else -- Single-block read.
txCmd_v := READ_BLK_CMD_C & addr_i & FAKE_CRC_C; -- Use address supplied by host.
addr_v := unsigned(addr_i); -- Store address for multi-block operations.
end if;
bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command.
byteCnt_v := RD_BLK_SZ_C;
state_v := START_TX; -- Go to FSM subroutine to send the command.
rtnState_v := RD_BLK; -- Then go to this state to read the data block.
elsif wr_i = YES then -- send WRITE command and address to the SD card.
cs_bo <= LO; -- Enable the SD card.
if continue_i = YES then -- Multi-block write. Use stored address.
if CARD_TYPE_G = SD_CARD_E then -- SD cards use byte-addressing,
addr_v := addr_v + BLOCK_SIZE_G; -- so add block-size to get next block address.
else -- SDHC cards use block-addressing,
addr_v := addr_v + 1; -- so just increment current block address.
end if;
txCmd_v := WRITE_BLK_CMD_C & std_logic_vector(addr_v) & FAKE_CRC_C;
else -- Single-block write.
txCmd_v := WRITE_BLK_CMD_C & addr_i & FAKE_CRC_C; -- Use address supplied by host.
addr_v := unsigned(addr_i); -- Store address for multi-block operations.
end if;
bitCnt_v := txCmd_v'length; -- Set bit counter to the size of the command.
byteCnt_v := WR_BLK_SZ_C; -- Set number of bytes to write.
state_v := START_TX; -- Go to this FSM subroutine to send the command
rtnState_v := WR_BLK; -- then go to this state to write the data block.
else -- Do nothing and wait for command from host.
cs_bo <= HI; -- Deselect the SD card.
busy_o <= NO; -- SD card interface is waiting for R/W from host, so it's not busy.
state_v := WAIT_FOR_HOST_RW; -- Keep waiting for command from host.
end if;
when RD_BLK => -- Read a block of data from the SD card.
-- Some default values for these...
rtnData_v := false; -- Data is only returned to host in one place.
bitCnt_v := rx_v'length - 1; -- Receiving byte-sized data.
state_v := RX_BITS; -- Call the bit receiver routine.
rtnState_v := RD_BLK; -- Return here when done receiving a byte.
if byteCnt_v = RD_BLK_SZ_C then -- Initial read to prime the pump.
byteCnt_v := byteCnt_v - 1;
elsif byteCnt_v = RD_BLK_SZ_C -1 then -- Then look for the data block start token.
if rx_v = NO_TOKEN_C then -- Receiving 0xFF means the card hasn't responded yet. Keep trying.
null;
elsif rx_v = START_TOKEN_C then
rtnData_v := true; -- Found the start token, so now start returning data byes to the host.
byteCnt_v := byteCnt_v - 1;
else -- Getting anything else means something strange has happened.
state_v := REPORT_ERROR;
end if;
elsif byteCnt_v >= 3 then -- Now bytes of data from the SD card are received.
rtnData_v := true; -- Return this data to the host.
byteCnt_v := byteCnt_v - 1;
elsif byteCnt_v = 2 then -- Receive the 1st CRC byte at the end of the data block.
byteCnt_v := byteCnt_v - 1;
elsif byteCnt_v = 1 then -- Receive the 2nd
byteCnt_v := byteCnt_v - 1;
else -- Reading is done, so deselect the SD card.
sclk_r <= LO;
bitCnt_v := 2;
state_v := DESELECT;
rtnState_v := WAIT_FOR_HOST_RW;
end if;
when WR_BLK => -- Write a block of data to the SD card.
-- Some default values for these...
getCmdResponse_v := false; -- Sending data bytes so there's no command response from SD card.
bitCnt_v := txData_v'length; -- Transmitting byte-sized data.
state_v := START_TX; -- Call the bit transmitter routine.
rtnState_v := WR_BLK; -- Return here when done transmitting a byte.
if byteCnt_v = WR_BLK_SZ_C then
txData_v := NO_TOKEN_C; -- Hold MOSI high for one byte before data block goes out.
elsif byteCnt_v = WR_BLK_SZ_C - 1 then -- Send start token.
txData_v := START_TOKEN_C; -- Starting token for data block.
elsif byteCnt_v >= 4 then -- Now send bytes in the data block.
hndShk_r <= HI; -- Signal host to provide data.
-- The transmit shift register is loaded with data from host in the handshaking section above.
elsif byteCnt_v = 3 or byteCnt_v = 2 then -- Send two phony CRC bytes at end of packet.
txData_v := FAKE_CRC_C;
elsif byteCnt_v = 1 then
bitCnt_v := rx_v'length - 1;
state_v := RX_BITS; -- Get response of SD card to the write operation.
rtnState_v := WR_WAIT;
else -- Check received response byte.
if std_match(rx_v, DATA_ACCEPTED_C) then -- Data block was accepted.
state_v := WR_WAIT; -- Wait for the SD card to finish writing the data into Flash.
else -- Data block was rejected.
error_o(15 downto 8) <= rx_v;
state_v := REPORT_ERROR; -- Report the error.
end if;
end if;
byteCnt_v := byteCnt_v - 1;
when WR_WAIT => -- Wait for SD card to finish writing the data block.
-- The SD card will pull MISO low while it is busy, and raise it when it is done.
sclk_r <= not sclk_r; -- Toggle the SPI clock...
sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase.
if sclk_r = HI and miso_i = HI then -- Data block has been written, so deselect the SD card.
bitCnt_v := 2;
state_v := DESELECT;
rtnState_v := WAIT_FOR_HOST_RW;
end if;
when START_TX =>
-- Start sending command/data by lowering SCLK and outputing MSB of command/data
-- so it has plenty of setup before the rising edge of SCLK.
sclk_r <= LO; -- Lower the SCLK (although it should already be low).
sclkPhaseTimer_v := clkDivider_v; -- Set the duration of the low SCLK.
mosi_o <= tx_v(tx_v'high); -- Output MSB of command/data.
tx_v := tx_v(tx_v'high-1 downto 0) & ONE; -- Shift command/data register by one bit.
bitCnt_v := bitCnt_v - 1; -- The first bit has been sent, so decrement bit counter.
state_v := TX_BITS; -- Go here to shift out the rest of the command/data bits.
when TX_BITS => -- Shift out remaining command/data bits and (possibly) get response from SD card.
sclk_r <= not sclk_r; -- Toggle the SPI clock...
sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase.
if sclk_r = HI then
-- SCLK is going to be flipped from high to low, so output the next command/data bit
-- so it can setup while SCLK is low.
if bitCnt_v /= 0 then -- Keep sending bits until the bit counter hits zero.
mosi_o <= tx_v(tx_v'high);
tx_v := tx_v(tx_v'high-1 downto 0) & ONE;
bitCnt_v := bitCnt_v - 1;
else
if getCmdResponse_v then
state_v := GET_CMD_RESPONSE; -- Get a response to the command from the SD card.
bitCnt_v := Response_t'length - 1; -- Length of the expected response.
else
state_v := rtnState_v; -- Return to calling state (no need to get a response).
sclkPhaseTimer_v := 0; -- Clear timer so next SPI op can begin ASAP with SCLK low.
end if;
end if;
end if;
when GET_CMD_RESPONSE => -- Get the response of the SD card to a command.
if sclk_r = HI and miso_i = LO then -- MISO will be held high by SD card until 1st bit
-- of R1 response, which is 0.
rx_v := rx_v(rx_v'high-1 downto 0) & miso_i; -- Shift in the MSB bit of the response.
bitCnt_v := bitCnt_v - 1;
state_v := RX_BITS; -- Now receive the reset of the response.
end if;
sclk_r <= not sclk_r; -- Toggle the SPI clock...
sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase.
when RX_BITS => -- Receive bits from the SD card.
if sclk_r = HI then -- Bits enter after the rising edge of SCLK.
rx_v := rx_v(rx_v'high-1 downto 0) & miso_i;
if bitCnt_v /= 0 then -- More bits left to receive.
bitCnt_v := bitCnt_v - 1;
else -- Last bit has been received.
if rtnData_v then -- Send the received data to the host.
data_o <= rx_v; -- Output received data to the host.
hndShk_r <= HI; -- Signal to the host that the data is ready.
end if;
if doDeselect_v then
bitCnt_v := 1;
state_v := DESELECT; -- De-select SD card before returning.
else
state_v := rtnState_v; -- Otherwise, return to calling state without de-selecting.
end if;
end if;
end if;
sclk_r <= not sclk_r; -- Toggle the SPI clock...
sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase.
when DESELECT => -- De-select the SD card and send some clock pulses (Must enter with sclk at zero.)
doDeselect_v := false; -- Once the de-select is done, clear the flag that caused it.
cs_bo <= HI; -- De-select the SD card.
mosi_o <= HI; -- Keep the data input of the SD card pulled high.
state_v := PULSE_SCLK; -- Pulse the clock so the SD card will see the de-select.
sclk_r <= LO; -- Clock is set low so the next rising edge will see the new CS and MOSI
sclkPhaseTimer_v := clkDivider_v; -- Set the duration of the next clock phase.
when PULSE_SCLK => -- Issue some clock pulses. (Must enter with sclk at zero.)
if sclk_r = HI then
if bitCnt_v /= 0 then
bitCnt_v := bitCnt_v - 1;
else -- Return to the calling routine when the pulse counter reaches zero.
state_v := rtnState_v;
end if;
end if;
sclk_r <= not sclk_r; -- Toggle the SPI clock...
sclkPhaseTimer_v := clkDivider_v; -- and set the duration of the next clock phase.
when REPORT_ERROR => -- Report the error code and stall here until a reset occurs.
error_o(rx_v'range) <= rx_v; -- Output the SD card response as the error code.
busy_o <= NO; -- Not busy.
when others =>
state_v := START_INIT;
end case;
end if;
end if;
end process;
sclk_o <= sclk_r; -- Output the generated SPI clock for the SD card.
hndShk_o <= hndShk_r; -- Output the generated handshake to the host.
end architecture rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of SdCardCtrl is
begin
data_o <= (others => 'X'); -- Data read from block.
busy_o <= LO; -- High when controller is busy performing some operation.
cs_bo <= HI; -- Active-low chip-select.
sclk_o <= LO; -- Serial clock to SD card.
mosi_o <= HI; -- Serial data output to SD card.
state <= (others => 'X'); -- state debugging only
end architecture fake;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/ifft_16_bit/TWDLMULT_SDNF1_3_block2.vhd | 1 | 13271 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLMULT_SDNF1_3_block2.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block2
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_6_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_6_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_8_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_8_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_vld : IN std_logic;
twdl_3_7_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_7_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_8_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_8_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_8_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_7_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_7_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_8_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_8_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_7_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block2;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block2 IS
-- Component Declarations
COMPONENT Complex3Multiply_block3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din1_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_vld_dly3 : IN std_logic;
twdl_3_7_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_7_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_7_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_7_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT Complex3Multiply_block4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din2_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din2_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
di2_vld_dly3 : IN std_logic;
twdl_3_8_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_8_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_8_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_8_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block3
USE ENTITY work.Complex3Multiply_block3(rtl);
FOR ALL : Complex3Multiply_block4
USE ENTITY work.Complex3Multiply_block4(rtl);
-- Signals
SIGNAL dout_6_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_6_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_vld_dly1 : std_logic;
SIGNAL din1_vld_dly2 : std_logic;
SIGNAL din1_vld_dly3 : std_logic;
SIGNAL twdlXdin_7_re_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin_7_im_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin1_vld : std_logic;
SIGNAL dout_8_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_8_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_8_re_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin_8_im_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
BEGIN
u_MUL3_1 : Complex3Multiply_block3
PORT MAP( clk => clk,
reset => reset,
enb => enb,
din1_re_dly3 => std_logic_vector(din1_re_dly3), -- sfix17
din1_im_dly3 => std_logic_vector(din1_im_dly3), -- sfix17
din1_vld_dly3 => din1_vld_dly3,
twdl_3_7_re => twdl_3_7_re, -- sfix17_En15
twdl_3_7_im => twdl_3_7_im, -- sfix17_En15
softReset => softReset,
twdlXdin_7_re => twdlXdin_7_re_tmp, -- sfix17
twdlXdin_7_im => twdlXdin_7_im_tmp, -- sfix17
twdlXdin1_vld => twdlXdin1_vld
);
u_MUL3_2 : Complex3Multiply_block4
PORT MAP( clk => clk,
reset => reset,
enb => enb,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix17
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix17
di2_vld_dly3 => di2_vld_dly3,
twdl_3_8_re => twdl_3_8_re, -- sfix17_En15
twdl_3_8_im => twdl_3_8_im, -- sfix17_En15
softReset => softReset,
twdlXdin_8_re => twdlXdin_8_re_tmp, -- sfix17
twdlXdin_8_im => twdlXdin_8_im_tmp, -- sfix17
twdlXdin2_vld => twdlXdin_7_vld
);
dout_6_re_signed <= signed(dout_6_re);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly1 <= dout_6_re_signed;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
dout_6_im_signed <= signed(dout_6_im);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly1 <= dout_6_im_signed;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly2 <= din1_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly3 <= din1_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_8_process;
dout_8_re_signed <= signed(dout_8_re);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly1 <= dout_8_re_signed;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
dout_8_im_signed <= signed(dout_8_im);
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly1 <= dout_8_im_signed;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_7_re <= twdlXdin_7_re_tmp;
twdlXdin_7_im <= twdlXdin_7_im_tmp;
twdlXdin_8_re <= twdlXdin_8_re_tmp;
twdlXdin_8_im <= twdlXdin_8_im_tmp;
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLROM_3_7.vhd | 1 | 14009 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLROM_3_7.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_7
-- Source Path: hdl_ofdm_tx/ifft/TWDLROM_3_7
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY TWDLROM_3_7 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_7_vld : OUT std_logic
);
END TWDLROM_3_7;
ARCHITECTURE rtl OF TWDLROM_3_7 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#4000#, 16), to_signed(16#3B21#, 16)); -- sfix16 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#0000#, 16), to_signed(-16#187E#, 16)); -- sfix16 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_7_re_tmp : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_7_im_tmp : signed(15 DOWNTO 0); -- sfix16_En14
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#1#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#2#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE addr_cast : unsigned(3 DOWNTO 0);
VARIABLE c : unsigned(1 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt;
Radix22TwdlMapping_phase_next <= Radix22TwdlMapping_phase;
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
c := unsigned'(Radix22TwdlMapping_cnt(0) & Radix22TwdlMapping_cnt(1));
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(c, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(c, 4) sll 1;
ELSE
addr_cast := resize(c, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (addr_cast sll 1) + addr_cast;
END IF;
IF dout_2_vld = '1' THEN
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000004#, 2);
END IF;
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(15 DOWNTO 0);
VARIABLE twdlIn_im : signed(15 DOWNTO 0);
VARIABLE cast : signed(16 DOWNTO 0);
VARIABLE cast_0 : signed(16 DOWNTO 0);
VARIABLE cast_1 : signed(16 DOWNTO 0);
VARIABLE cast_2 : signed(16 DOWNTO 0);
VARIABLE cast_3 : signed(16 DOWNTO 0);
VARIABLE cast_4 : signed(16 DOWNTO 0);
VARIABLE cast_5 : signed(16 DOWNTO 0);
VARIABLE cast_6 : signed(16 DOWNTO 0);
VARIABLE cast_7 : signed(16 DOWNTO 0);
VARIABLE cast_8 : signed(16 DOWNTO 0);
VARIABLE cast_9 : signed(16 DOWNTO 0);
VARIABLE cast_10 : signed(16 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "010" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "100" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(16#2D41#, 16);
WHEN OTHERS =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 17);
cast_0 := - (cast);
twdlIn_re := cast_0(15 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 17);
cast_6 := - (cast_5);
twdlIn_im := cast_6(15 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 17);
cast_8 := - (cast_7);
twdlIn_im := cast_8(15 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 17);
cast_2 := - (cast_1);
twdlIn_re := cast_2(15 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 17);
cast_4 := - (cast_3);
twdlIn_re := cast_4(15 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 17);
cast_10 := - (cast_9);
twdlIn_im := cast_10(15 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_7_re_tmp <= twdlIn_re;
twdl_3_7_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_7_re <= std_logic_vector(twdl_3_7_re_tmp);
twdl_3_7_im <= std_logic_vector(twdl_3_7_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_7_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl_3_7_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
| gpl-3.0 |
freecores/dds_synthesizer | vhdl/sine_lut/sine_lut_16_x_10.vhd | 2 | 702772 | -- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 16;
constant AMPL_WIDTH : integer := 10;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
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conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
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conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
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conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
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conv_std_logic_vector(431,AMPL_WIDTH),
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conv_std_logic_vector(431,AMPL_WIDTH),
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conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
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conv_std_logic_vector(432,AMPL_WIDTH),
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conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
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conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
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conv_std_logic_vector(433,AMPL_WIDTH),
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conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
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conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
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conv_std_logic_vector(434,AMPL_WIDTH),
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conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
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conv_std_logic_vector(434,AMPL_WIDTH),
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conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
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conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
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conv_std_logic_vector(436,AMPL_WIDTH),
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conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
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conv_std_logic_vector(437,AMPL_WIDTH),
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conv_std_logic_vector(438,AMPL_WIDTH),
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conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
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conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
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conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
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conv_std_logic_vector(457,AMPL_WIDTH),
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conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
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conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
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conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
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conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
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conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
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conv_std_logic_vector(458,AMPL_WIDTH),
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conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
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conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
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conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
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conv_std_logic_vector(462,AMPL_WIDTH),
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conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
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conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
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conv_std_logic_vector(463,AMPL_WIDTH),
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conv_std_logic_vector(463,AMPL_WIDTH),
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conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
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conv_std_logic_vector(465,AMPL_WIDTH),
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conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
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conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
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conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
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conv_std_logic_vector(466,AMPL_WIDTH),
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conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
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conv_std_logic_vector(466,AMPL_WIDTH),
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conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
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conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
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conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
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conv_std_logic_vector(471,AMPL_WIDTH),
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conv_std_logic_vector(473,AMPL_WIDTH),
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conv_std_logic_vector(473,AMPL_WIDTH),
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conv_std_logic_vector(474,AMPL_WIDTH),
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conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
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conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
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conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
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conv_std_logic_vector(486,AMPL_WIDTH),
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conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
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conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
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conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
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conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
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conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
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conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
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conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
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conv_std_logic_vector(491,AMPL_WIDTH),
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conv_std_logic_vector(491,AMPL_WIDTH),
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conv_std_logic_vector(491,AMPL_WIDTH),
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conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
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conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(493,AMPL_WIDTH),
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conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
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conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
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conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
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conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
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conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
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conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
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conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
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conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
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conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
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conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
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conv_std_logic_vector(500,AMPL_WIDTH),
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conv_std_logic_vector(500,AMPL_WIDTH),
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conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
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conv_std_logic_vector(500,AMPL_WIDTH),
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conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
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conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
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conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
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conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
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conv_std_logic_vector(504,AMPL_WIDTH),
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conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
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conv_std_logic_vector(508,AMPL_WIDTH),
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conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
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conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
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conv_std_logic_vector(510,AMPL_WIDTH),
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conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; | gpl-3.0 |
freecores/dds_synthesizer | vhdl/sine_lut/sine_lut_14_x_10.vhd | 2 | 176066 | -- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 14;
constant AMPL_WIDTH : integer := 10;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; | gpl-3.0 |
AloriumTechnology/XLR8Float | extras/rtl/xlr8_float/xlr8_float_mult2/dspba_library.vhd | 2 | 23572 | -- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
sync_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
async_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_mux2 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_mux2;
architecture mux2 of dspba_mux2 is
begin
mux2genclk: if depth = 1 generate
mux2proc: PROCESS (xin0, xin1, xinsel, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
CASE (xinsel) IS
WHEN "0" => xout <= xin0;
WHEN "1" => xout <= xin1;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end if;
end if;
END PROCESS mux2proc;
end generate mux2genclk;
mux2gencomb: if depth = 0 generate
mux2proc2: process(xin0, xin1, xinsel)
begin
CASE (xinsel) IS
WHEN "0" => xout <= xin0;
WHEN "1" => xout <= xin1;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end process mux2proc2;
end generate mux2gencomb;
end mux2;
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_mux3 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xin2 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_mux3;
architecture mux3 of dspba_mux3 is
begin
mux3genclk: if depth = 1 generate
mux3proc: PROCESS (xin0, xin1, xin2, xinsel, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
CASE (xinsel) IS
WHEN "00" => xout <= xin0;
WHEN "01" => xout <= xin1;
WHEN "10" => xout <= xin2;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end if;
end if;
END PROCESS mux3proc;
end generate mux3genclk;
mux3gencomb: if depth = 0 generate
mux3proc2: process(xin0, xin1, xin2, xinsel)
begin
CASE (xinsel) IS
WHEN "00" => xout <= xin0;
WHEN "01" => xout <= xin1;
WHEN "10" => xout <= xin2;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end process mux3proc2;
end generate mux3gencomb;
end mux3;
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_mux4 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xin2 : in std_logic_vector(width-1 downto 0);
xin3 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_mux4;
architecture mux4 of dspba_mux4 is
begin
mux4genclk: if depth = 1 generate
mux4proc: PROCESS (xin0, xin1, xin2, xin3, xinsel, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
CASE (xinsel) IS
WHEN "00" => xout <= xin0;
WHEN "01" => xout <= xin1;
WHEN "10" => xout <= xin2;
WHEN "11" => xout <= xin3;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end if;
end if;
END PROCESS mux4proc;
end generate mux4genclk;
mux4gencomb: if depth = 0 generate
mux4proc2: process(xin0, xin1, xin2, xin3, xinsel)
begin
CASE (xinsel) IS
WHEN "00" => xout <= xin0;
WHEN "01" => xout <= xin1;
WHEN "10" => xout <= xin2;
WHEN "11" => xout <= xin3;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end process mux4proc2;
end generate mux4gencomb;
end mux4;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intadd_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intadd_u;
architecture intadd_u of dspba_intadd_u is
begin
intadd_u_genclk: if depth = 1 generate
intadd_u_proc: PROCESS (xin0, xin1, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) + UNSIGNED(xin1));
end if;
end if;
END PROCESS intadd_u_proc;
end generate intadd_u_genclk;
intadd_u_gencomb: if depth = 0 generate
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) + UNSIGNED(xin1));
end generate intadd_u_gencomb;
end intadd_u;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intadd_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intadd_s;
architecture intadd_s of dspba_intadd_s is
begin
intadd_s_genclk: if depth = 1 generate
intadd_s_proc: PROCESS (xin0, xin1, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) + SIGNED(xin1));
end if;
end if;
END PROCESS intadd_s_proc;
end generate intadd_s_genclk;
intadd_s_gencomb: if depth = 0 generate
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) + SIGNED(xin1));
end generate intadd_s_gencomb;
end intadd_s;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intsub_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intsub_u;
architecture intsub_u of dspba_intsub_u is
begin
intsub_u_genclk: if depth = 1 generate
intsub_u_proc: PROCESS (xin0, xin1, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) - UNSIGNED(xin1));
end if;
end if;
END PROCESS intsub_u_proc;
end generate intsub_u_genclk;
intsub_u_gencomb: if depth = 0 generate
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) - UNSIGNED(xin1));
end generate intsub_u_gencomb;
end intsub_u;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intsub_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intsub_s;
architecture intsub_s of dspba_intsub_s is
begin
intsub_s_genclk: if depth = 1 generate
intsub_s_proc: PROCESS (xin0, xin1, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) - SIGNED(xin1));
end if;
end if;
END PROCESS intsub_s_proc;
end generate intsub_s_genclk;
intsub_s_gencomb: if depth = 0 generate
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) - SIGNED(xin1));
end generate intsub_s_gencomb;
end intsub_s;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intaddsub_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xins : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intaddsub_u;
architecture intaddsub_u of dspba_intaddsub_u is
begin
intaddsub_u_genclk: if depth = 1 generate
intaddsub_u_proc: PROCESS (xin0, xin1, xins, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
IF (xins = "1") THEN
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) + UNSIGNED(xin1));
ELSE
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) - UNSIGNED(xin1));
END IF;
end if;
end if;
END PROCESS intaddsub_u_proc;
end generate intaddsub_u_genclk;
intaddsub_u_gencomb: if depth = 0 generate
intaddsub_u_proc_comb: PROCESS (xin0, xin1, xins)
BEGIN
IF (xins = "1") THEN
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) + UNSIGNED(xin1));
ELSE
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) - UNSIGNED(xin1));
END IF;
END PROCESS;
end generate intaddsub_u_gencomb;
end intaddsub_u;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intaddsub_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xins : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intaddsub_s;
architecture intaddsub_s of dspba_intaddsub_s is
begin
intaddsub_s_genclk: if depth = 1 generate
intaddsub_s_proc: PROCESS (xin0, xin1, xins, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
IF (xins = "1") THEN
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) + SIGNED(xin1));
ELSE
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) - SIGNED(xin1));
END IF;
end if;
end if;
END PROCESS intaddsub_s_proc;
end generate intaddsub_s_genclk;
intaddsub_s_gencomb: if depth = 0 generate
intaddsub_s_proc_comb: PROCESS (xin0, xin1, xins)
BEGIN
IF (xins = "1") THEN
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) + SIGNED(xin1));
ELSE
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) - SIGNED(xin1));
END IF;
END PROCESS;
end generate intaddsub_s_gencomb;
end intaddsub_s;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
| gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/fft_16_bit/TWDLROM_3_12.vhd | 1 | 13835 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_12.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_12
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLROM_3_12
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.fft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_12 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_12_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_12_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_12_vld : OUT std_logic
);
END TWDLROM_3_12;
ARCHITECTURE rtl OF TWDLROM_3_12 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_12_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_12_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#2#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#2#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_12_re_tmp <= twdlIn_re;
twdl_3_12_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_12_re <= std_logic_vector(twdl_3_12_re_tmp);
twdl_3_12_im <= std_logic_vector(twdl_3_12_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_12_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_12_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_1.vhd | 1 | 6672 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_1.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_1_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_1_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_9_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_9_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1 IS
-- Signals
SIGNAL twdlXdin_1_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_1_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_9_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_9_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_1_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_1_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_2_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_2_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
twdlXdin_1_re_signed <= signed(twdlXdin_1_re);
twdlXdin_1_im_signed <= signed(twdlXdin_1_im);
twdlXdin_9_re_signed <= signed(twdlXdin_9_re);
twdlXdin_9_im_signed <= signed(twdlXdin_9_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_1_re_signed,
twdlXdin_1_im_signed, twdlXdin_9_re_signed, twdlXdin_9_im_signed,
twdlXdin_1_vld)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_1_re_signed, 18) + resize(twdlXdin_9_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_1_re_signed, 18) - resize(twdlXdin_9_re_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_1_im_signed, 18) + resize(twdlXdin_9_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_1_im_signed, 18) - resize(twdlXdin_9_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_1_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_1_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_2_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_2_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_1_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_1_re <= std_logic_vector(dout_1_re_tmp);
dout_1_im <= std_logic_vector(dout_1_im_tmp);
dout_2_re <= std_logic_vector(dout_2_re_tmp);
dout_2_im <= std_logic_vector(dout_2_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/ifft_16_bit/TWDLMULT_SDNF1_3_block4.vhd | 1 | 13308 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLMULT_SDNF1_3_block4.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block4
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_13_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_13_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_15_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_15_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_vld : IN std_logic;
twdl_3_11_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_11_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_12_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_12_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_12_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_11_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_11_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_12_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_12_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_11_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block4;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block4 IS
-- Component Declarations
COMPONENT Complex3Multiply_block6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din1_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_vld_dly3 : IN std_logic;
twdl_3_11_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_11_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_11_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_11_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT Complex3Multiply_block7
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din2_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din2_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
di2_vld_dly3 : IN std_logic;
twdl_3_12_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_12_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_12_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_12_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block6
USE ENTITY work.Complex3Multiply_block6(rtl);
FOR ALL : Complex3Multiply_block7
USE ENTITY work.Complex3Multiply_block7(rtl);
-- Signals
SIGNAL dout_13_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_13_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_vld_dly1 : std_logic;
SIGNAL din1_vld_dly2 : std_logic;
SIGNAL din1_vld_dly3 : std_logic;
SIGNAL twdlXdin_11_re_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin_11_im_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin1_vld : std_logic;
SIGNAL dout_15_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_15_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_12_re_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin_12_im_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
BEGIN
u_MUL3_1 : Complex3Multiply_block6
PORT MAP( clk => clk,
reset => reset,
enb => enb,
din1_re_dly3 => std_logic_vector(din1_re_dly3), -- sfix17
din1_im_dly3 => std_logic_vector(din1_im_dly3), -- sfix17
din1_vld_dly3 => din1_vld_dly3,
twdl_3_11_re => twdl_3_11_re, -- sfix17_En15
twdl_3_11_im => twdl_3_11_im, -- sfix17_En15
softReset => softReset,
twdlXdin_11_re => twdlXdin_11_re_tmp, -- sfix17
twdlXdin_11_im => twdlXdin_11_im_tmp, -- sfix17
twdlXdin1_vld => twdlXdin1_vld
);
u_MUL3_2 : Complex3Multiply_block7
PORT MAP( clk => clk,
reset => reset,
enb => enb,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix17
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix17
di2_vld_dly3 => di2_vld_dly3,
twdl_3_12_re => twdl_3_12_re, -- sfix17_En15
twdl_3_12_im => twdl_3_12_im, -- sfix17_En15
softReset => softReset,
twdlXdin_12_re => twdlXdin_12_re_tmp, -- sfix17
twdlXdin_12_im => twdlXdin_12_im_tmp, -- sfix17
twdlXdin2_vld => twdlXdin_11_vld
);
dout_13_re_signed <= signed(dout_13_re);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly1 <= dout_13_re_signed;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
dout_13_im_signed <= signed(dout_13_im);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly1 <= dout_13_im_signed;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly2 <= din1_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly3 <= din1_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_8_process;
dout_15_re_signed <= signed(dout_15_re);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly1 <= dout_15_re_signed;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
dout_15_im_signed <= signed(dout_15_im);
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly1 <= dout_15_im_signed;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_11_re <= twdlXdin_11_re_tmp;
twdlXdin_11_im <= twdlXdin_11_im_tmp;
twdlXdin_12_re <= twdlXdin_12_re_tmp;
twdlXdin_12_im <= twdlXdin_12_im_tmp;
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_4_block.vhd | 1 | 8528 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_4_block.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF2_4_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_3 : IN std_logic; -- ufix1
dout_3_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_3_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_11_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_11_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re_1 : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_3_im_1 : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_4_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_4_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block IS
-- Signals
SIGNAL dout_3_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_3_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_11_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_11_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL dout_3_re_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_3_im_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_4_re_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_4_im_tmp : signed(19 DOWNTO 0); -- sfix20_En13
BEGIN
dout_3_re_signed <= signed(dout_3_re);
din1_re <= resize(dout_3_re_signed, 20);
dout_3_im_signed <= signed(dout_3_im);
din1_im <= resize(dout_3_im_signed, 20);
dout_11_re_signed <= signed(dout_11_re);
din2_re <= resize(dout_11_re_signed, 20);
dout_11_im_signed <= signed(dout_11_im);
din2_im <= resize(dout_11_im_signed, 20);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#000000#, 21);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_3)
VARIABLE add_cast : signed(20 DOWNTO 0);
VARIABLE add_cast_0 : signed(20 DOWNTO 0);
VARIABLE add_cast_1 : signed(20 DOWNTO 0);
VARIABLE add_cast_2 : signed(20 DOWNTO 0);
VARIABLE sub_cast : signed(20 DOWNTO 0);
VARIABLE sub_cast_0 : signed(20 DOWNTO 0);
VARIABLE sub_cast_1 : signed(20 DOWNTO 0);
VARIABLE sub_cast_2 : signed(20 DOWNTO 0);
VARIABLE add_cast_3 : signed(20 DOWNTO 0);
VARIABLE add_cast_4 : signed(20 DOWNTO 0);
VARIABLE add_cast_5 : signed(20 DOWNTO 0);
VARIABLE add_cast_6 : signed(20 DOWNTO 0);
VARIABLE sub_cast_3 : signed(20 DOWNTO 0);
VARIABLE sub_cast_4 : signed(20 DOWNTO 0);
VARIABLE sub_cast_5 : signed(20 DOWNTO 0);
VARIABLE sub_cast_6 : signed(20 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_3 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(din1_re, 21);
add_cast_2 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(din1_re, 21);
sub_cast_2 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(din1_im, 21);
add_cast_6 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(din1_im, 21);
sub_cast_6 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(din1_re, 21);
add_cast_0 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(din1_re, 21);
sub_cast_0 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(din1_im, 21);
add_cast_4 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(din1_im, 21);
sub_cast_4 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
dout_3_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(19 DOWNTO 0);
dout_3_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(19 DOWNTO 0);
dout_4_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(19 DOWNTO 0);
dout_4_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(19 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_4_re <= std_logic_vector(dout_4_re_tmp);
dout_4_im <= std_logic_vector(dout_4_im_tmp);
dout_3_re_1 <= std_logic_vector(dout_3_re_tmp);
dout_3_im_1 <= std_logic_vector(dout_3_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | FFT_HDL/transceiver_hdl/OFDM_transmitter/Complex3Multiply_block1.vhd | 1 | 12764 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/Complex3Multiply_block1.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block1
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din2_re_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
din2_im_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
di2_vld_dly3 : IN std_logic;
twdl_3_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_4_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin2_vld : OUT std_logic
);
END Complex3Multiply_block1;
ARCHITECTURE rtl OF Complex3Multiply_block1 IS
-- Signals
SIGNAL din2_re_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din_re_reg : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_im_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din_im_reg : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL adder_add_cast : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL adder_add_cast_1 : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din_sum : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdl_3_4_re_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_re_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_4_im_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_im_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL adder_add_cast_2 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL adder_add_cast_3 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL twdl_sum : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(31 DOWNTO 0); -- sfix32
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(31 DOWNTO 0); -- sfix32
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL prodOfRe : signed(31 DOWNTO 0); -- sfix32_En27
SIGNAL prodOfIm : signed(31 DOWNTO 0); -- sfix32_En27
SIGNAL prodOfSum : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Add_multRes_re_reg1 : signed(32 DOWNTO 0); -- sfix33
SIGNAL Complex3Add_multRes_re_reg2 : signed(32 DOWNTO 0); -- sfix33
SIGNAL Complex3Add_multRes_im_reg : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Add_tmpResult_reg_next : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL Complex3Add_multRes_re_reg1_next : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL Complex3Add_multRes_re_reg2_next : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL Complex3Add_multRes_im_reg_next : signed(34 DOWNTO 0); -- sfix35_En27
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL multResFP_re : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL multResFP_im : signed(34 DOWNTO 0); -- sfix35_En27
SIGNAL twdlXdin_4_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_4_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
din2_re_dly3_signed <= signed(din2_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#0000#, 16);
ELSE
din_re_reg <= din2_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din2_im_dly3_signed <= signed(din2_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#0000#, 16);
ELSE
din_im_reg <= din2_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
adder_add_cast <= resize(din_re_reg, 17);
adder_add_cast_1 <= resize(din_im_reg, 17);
din_sum <= adder_add_cast + adder_add_cast_1;
twdl_3_4_re_signed <= signed(twdl_3_4_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSE
twdl_re_reg <= twdl_3_4_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_4_im_signed <= signed(twdl_3_4_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSE
twdl_im_reg <= twdl_3_4_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast_2 <= resize(twdl_re_reg, 17);
adder_add_cast_3 <= resize(twdl_im_reg, 17);
twdl_sum <= adder_add_cast_2 + adder_add_cast_3;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly1 <= di2_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 34);
Complex3Add_tmpResult_reg <= to_signed(0, 34);
Complex3Add_multRes_re_reg1 <= to_signed(0, 33);
Complex3Add_multRes_re_reg2 <= to_signed(0, 33);
Complex3Add_multRes_im_reg <= to_signed(0, 35);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(32 DOWNTO 0);
VARIABLE sub_cast_0 : signed(32 DOWNTO 0);
VARIABLE sub_cast_1 : signed(34 DOWNTO 0);
VARIABLE sub_cast_2 : signed(34 DOWNTO 0);
VARIABLE add_cast : signed(32 DOWNTO 0);
VARIABLE add_cast_0 : signed(32 DOWNTO 0);
VARIABLE add_temp : signed(32 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 33);
sub_cast_0 := resize(prodOfIm, 33);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 35);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 35);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 33);
add_cast_0 := resize(prodOfIm, 33);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 34);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin2_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_4_re_tmp <= multResFP_re(29 DOWNTO 14);
twdlXdin_4_re <= std_logic_vector(twdlXdin_4_re_tmp);
twdlXdin_4_im_tmp <= multResFP_im(29 DOWNTO 14);
twdlXdin_4_im <= std_logic_vector(twdlXdin_4_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | hdl_prj/hdlsrc/hdl_ofdm_tx/Complex3Multiply_block9.vhd | 1 | 12236 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/Complex3Multiply_block9.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block9
-- Source Path: hdl_ofdm_tx/ifft/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block9 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din1_re_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din1_im_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din1_vld_dly3 : IN std_logic;
twdl_3_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_15_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_15_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin1_vld : OUT std_logic
);
END Complex3Multiply_block9;
ARCHITECTURE rtl OF Complex3Multiply_block9 IS
-- Signals
SIGNAL din1_re_dly3_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din_re_reg : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly3_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din_im_reg : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL adder_add_cast : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL adder_add_cast_1 : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL din_sum : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL twdl_3_15_re_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_re_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_15_im_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_im_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL adder_add_cast_2 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL adder_add_cast_3 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL twdl_sum : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(18 DOWNTO 0) := to_signed(16#00000#, 19); -- sfix19
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(18 DOWNTO 0) := to_signed(16#00000#, 19); -- sfix19
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(19 DOWNTO 0) := to_signed(16#00000#, 20); -- sfix20
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(34 DOWNTO 0) := to_signed(0, 35); -- sfix35
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(34 DOWNTO 0) := to_signed(0, 35); -- sfix35
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(36 DOWNTO 0) := to_signed(0, 37); -- sfix37
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(15 DOWNTO 0) := to_signed(16#0000#, 16); -- sfix16
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(15 DOWNTO 0) := to_signed(16#0000#, 16); -- sfix16
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(16 DOWNTO 0) := to_signed(16#00000#, 17); -- sfix17
SIGNAL prodOfRe : signed(34 DOWNTO 0) := to_signed(0, 35); -- sfix35_En27
SIGNAL prodOfIm : signed(34 DOWNTO 0) := to_signed(0, 35); -- sfix35_En27
SIGNAL prodOfSum : signed(36 DOWNTO 0) := to_signed(0, 37); -- sfix37_En27
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Add_multRes_re_reg1 : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_multRes_re_reg2 : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_multRes_im_reg : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Add_tmpResult_reg_next : signed(36 DOWNTO 0); -- sfix37_En27
SIGNAL Complex3Add_multRes_re_reg1_next : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_multRes_re_reg2_next : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_multRes_im_reg_next : signed(37 DOWNTO 0); -- sfix38_En27
SIGNAL Complex3Add_sub_cast : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_sub_cast_1 : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_sub_cast_2 : signed(37 DOWNTO 0); -- sfix38_En27
SIGNAL Complex3Add_sub_cast_3 : signed(37 DOWNTO 0); -- sfix38_En27
SIGNAL Complex3Add_add_cast : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_add_cast_1 : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_add_temp : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL multResFP_re : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL multResFP_im : signed(37 DOWNTO 0); -- sfix38_En27
SIGNAL twdlXdin_15_re_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_15_im_tmp : signed(18 DOWNTO 0); -- sfix19_En13
BEGIN
din1_re_dly3_signed <= signed(din1_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 19);
ELSE
din_re_reg <= din1_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din1_im_dly3_signed <= signed(din1_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 19);
ELSE
din_im_reg <= din1_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
adder_add_cast <= resize(din_re_reg, 20);
adder_add_cast_1 <= resize(din_im_reg, 20);
din_sum <= adder_add_cast + adder_add_cast_1;
twdl_3_15_re_signed <= signed(twdl_3_15_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSE
twdl_re_reg <= twdl_3_15_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_15_im_signed <= signed(twdl_3_15_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSE
twdl_im_reg <= twdl_3_15_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast_2 <= resize(twdl_re_reg, 17);
adder_add_cast_3 <= resize(twdl_im_reg, 17);
twdl_sum <= adder_add_cast_2 + adder_add_cast_3;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly1 <= din1_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 37);
Complex3Add_tmpResult_reg <= to_signed(0, 37);
Complex3Add_multRes_re_reg1 <= to_signed(0, 36);
Complex3Add_multRes_re_reg2 <= to_signed(0, 36);
Complex3Add_multRes_im_reg <= to_signed(0, 38);
Complex3Add_prod_vld_reg1 <= '0';
twdlXdin1_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prodOfSum_reg <= prodOfSum;
twdlXdin1_vld <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1 <= prod_vld;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
Complex3Add_sub_cast <= resize(prodOfRe, 36);
Complex3Add_sub_cast_1 <= resize(prodOfIm, 36);
Complex3Add_multRes_re_reg1_next <= Complex3Add_sub_cast - Complex3Add_sub_cast_1;
Complex3Add_sub_cast_2 <= resize(Complex3Add_prodOfSum_reg, 38);
Complex3Add_sub_cast_3 <= resize(Complex3Add_tmpResult_reg, 38);
Complex3Add_multRes_im_reg_next <= Complex3Add_sub_cast_2 - Complex3Add_sub_cast_3;
Complex3Add_add_cast <= resize(prodOfRe, 36);
Complex3Add_add_cast_1 <= resize(prodOfIm, 36);
Complex3Add_add_temp <= Complex3Add_add_cast + Complex3Add_add_cast_1;
Complex3Add_tmpResult_reg_next <= resize(Complex3Add_add_temp, 37);
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin_15_re_tmp <= multResFP_re(32 DOWNTO 14);
twdlXdin_15_re <= std_logic_vector(twdlXdin_15_re_tmp);
twdlXdin_15_im_tmp <= multResFP_im(32 DOWNTO 14);
twdlXdin_15_im <= std_logic_vector(twdlXdin_15_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_3_block4.vhd | 1 | 6375 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_3_block4.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block4
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_10_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_10_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_12_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_12_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_11_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_12_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_12_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_11_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block4;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block4 IS
-- Signals
SIGNAL twdlXdin_10_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_10_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_12_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_12_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_11_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_11_im_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_12_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_12_im_tmp : signed(19 DOWNTO 0); -- sfix20
BEGIN
twdlXdin_10_re_signed <= signed(twdlXdin_10_re);
twdlXdin_10_im_signed <= signed(twdlXdin_10_im);
twdlXdin_12_re_signed <= signed(twdlXdin_12_re);
twdlXdin_12_im_signed <= signed(twdlXdin_12_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_10_re_signed,
twdlXdin_10_im_signed, twdlXdin_12_re_signed, twdlXdin_12_im_signed,
twdlXdin_1_vld)
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_10_re_signed, 21) + resize(twdlXdin_12_re_signed, 21);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_10_re_signed, 21) - resize(twdlXdin_12_re_signed, 21);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_10_im_signed, 21) + resize(twdlXdin_12_im_signed, 21);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_10_im_signed, 21) - resize(twdlXdin_12_im_signed, 21);
END IF;
dout_11_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(19 DOWNTO 0);
dout_11_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(19 DOWNTO 0);
dout_12_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(19 DOWNTO 0);
dout_12_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(19 DOWNTO 0);
dout_11_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_11_re <= std_logic_vector(dout_11_re_tmp);
dout_11_im <= std_logic_vector(dout_11_im_tmp);
dout_12_re <= std_logic_vector(dout_12_re_tmp);
dout_12_im <= std_logic_vector(dout_12_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_modulator/hdl_modulator_hdl_modulator.vhd | 1 | 5722 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_modulator/hdl_modulator_hdl_modulator.vhd
-- Created: 2018-02-27 13:25:15
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: hdl_modulator_hdl_modulator
-- Source Path: hdl_modulator
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY hdl_modulator_hdl_modulator IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
real_signal : IN std_logic_vector(19 DOWNTO 0); -- sfix20_En13
imag_signal : IN std_logic_vector(19 DOWNTO 0); -- sfix20_En13
baseband_mixed_signal : OUT std_logic_vector(36 DOWNTO 0) -- sfix37_En27
);
END hdl_modulator_hdl_modulator;
ARCHITECTURE rtl OF hdl_modulator_hdl_modulator IS
-- Component Declarations
COMPONENT hdl_modulator_wave_generator
PORT( u : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
x : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
y : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : hdl_modulator_wave_generator
USE ENTITY work.hdl_modulator_wave_generator(rtl);
-- Signals
SIGNAL real_signal_signed : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL counter_wave_genation_out1 : unsigned(15 DOWNTO 0); -- uint16
SIGNAL count_to_fix_converter_out1 : unsigned(31 DOWNTO 0); -- ufix32_En19
SIGNAL samples_per_period_out1 : signed(31 DOWNTO 0); -- sfix32_En5
SIGNAL count_scaler_out1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Sine : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL Cosine : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL Cosine_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Sine_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL real_signal_modulator_out1 : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL imag_signal_signed : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL imag_signal_modulator_out1 : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL tx_signal_adder_add_cast : signed(36 DOWNTO 0); -- sfix37_En27
SIGNAL tx_signal_adder_add_cast_1 : signed(36 DOWNTO 0); -- sfix37_En27
SIGNAL tx_signal_adder_out1 : signed(36 DOWNTO 0); -- sfix37_En27
BEGIN
u_wave_generator : hdl_modulator_wave_generator
PORT MAP( u => std_logic_vector(count_scaler_out1), -- sfix16_En14
x => Sine, -- sfix16_En14
y => Cosine -- sfix16_En14
);
real_signal_signed <= signed(real_signal);
-- Count limited, Unsigned Counter
-- initial value = 0
-- step value = 1
-- count to value = 511
counter_wave_genation_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
counter_wave_genation_out1 <= to_unsigned(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF counter_wave_genation_out1 >= to_unsigned(16#01FF#, 16) THEN
counter_wave_genation_out1 <= to_unsigned(16#0000#, 16);
ELSE
counter_wave_genation_out1 <= counter_wave_genation_out1 + to_unsigned(16#0001#, 16);
END IF;
END IF;
END IF;
END PROCESS counter_wave_genation_process;
count_to_fix_converter_out1 <= counter_wave_genation_out1(12 DOWNTO 0) & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0';
samples_per_period_out1 <= to_signed(16384, 32);
count_scaler_output : PROCESS (count_to_fix_converter_out1, samples_per_period_out1)
VARIABLE c : signed(31 DOWNTO 0);
VARIABLE div_temp : signed(32 DOWNTO 0);
VARIABLE cast : signed(32 DOWNTO 0);
BEGIN
IF samples_per_period_out1 = to_signed(0, 32) THEN
c := to_signed(2147483647, 32);
ELSE
cast := signed(resize(count_to_fix_converter_out1, 33));
div_temp := cast / samples_per_period_out1;
IF (div_temp(32) = '0') AND (div_temp(31) /= '0') THEN
c := X"7FFFFFFF";
ELSIF (div_temp(32) = '1') AND (div_temp(31) /= '1') THEN
c := X"80000000";
ELSE
c := div_temp(31 DOWNTO 0);
END IF;
END IF;
IF (c(31) = '0') AND (c(30 DOWNTO 15) /= X"0000") THEN
count_scaler_out1 <= X"7FFF";
ELSIF (c(31) = '1') AND (c(30 DOWNTO 15) /= X"FFFF") THEN
count_scaler_out1 <= X"8000";
ELSE
count_scaler_out1 <= c(15 DOWNTO 0);
END IF;
END PROCESS count_scaler_output;
Cosine_signed <= signed(Cosine);
Sine_signed <= signed(Sine);
real_signal_modulator_out1 <= real_signal_signed * Sine_signed;
imag_signal_signed <= signed(imag_signal);
imag_signal_modulator_out1 <= Cosine_signed * imag_signal_signed;
tx_signal_adder_add_cast <= resize(real_signal_modulator_out1, 37);
tx_signal_adder_add_cast_1 <= resize(imag_signal_modulator_out1, 37);
tx_signal_adder_out1 <= tx_signal_adder_add_cast + tx_signal_adder_add_cast_1;
baseband_mixed_signal <= std_logic_vector(tx_signal_adder_out1);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | FFT_HDL/transceiver_hdl/OFDM_transmitter/Complex3Multiply_block.vhd | 1 | 12760 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/Complex3Multiply_block.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din1_re_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
din1_im_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
din1_vld_dly3 : IN std_logic;
twdl_3_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_3_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_3_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin1_vld : OUT std_logic
);
END Complex3Multiply_block;
ARCHITECTURE rtl OF Complex3Multiply_block IS
-- Signals
SIGNAL din1_re_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din_re_reg : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din_im_reg : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL adder_add_cast : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL adder_add_cast_1 : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din_sum : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdl_3_3_re_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_re_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_3_im_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_im_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL adder_add_cast_2 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL adder_add_cast_3 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL twdl_sum : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(31 DOWNTO 0); -- sfix32
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(31 DOWNTO 0); -- sfix32
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL prodOfRe : signed(31 DOWNTO 0); -- sfix32_En27
SIGNAL prodOfIm : signed(31 DOWNTO 0); -- sfix32_En27
SIGNAL prodOfSum : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Add_multRes_re_reg1 : signed(32 DOWNTO 0); -- sfix33
SIGNAL Complex3Add_multRes_re_reg2 : signed(32 DOWNTO 0); -- sfix33
SIGNAL Complex3Add_multRes_im_reg : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Add_tmpResult_reg_next : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL Complex3Add_multRes_re_reg1_next : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL Complex3Add_multRes_re_reg2_next : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL Complex3Add_multRes_im_reg_next : signed(34 DOWNTO 0); -- sfix35_En27
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL multResFP_re : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL multResFP_im : signed(34 DOWNTO 0); -- sfix35_En27
SIGNAL twdlXdin_3_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_3_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
din1_re_dly3_signed <= signed(din1_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#0000#, 16);
ELSE
din_re_reg <= din1_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din1_im_dly3_signed <= signed(din1_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#0000#, 16);
ELSE
din_im_reg <= din1_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
adder_add_cast <= resize(din_re_reg, 17);
adder_add_cast_1 <= resize(din_im_reg, 17);
din_sum <= adder_add_cast + adder_add_cast_1;
twdl_3_3_re_signed <= signed(twdl_3_3_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSE
twdl_re_reg <= twdl_3_3_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_3_im_signed <= signed(twdl_3_3_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSE
twdl_im_reg <= twdl_3_3_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast_2 <= resize(twdl_re_reg, 17);
adder_add_cast_3 <= resize(twdl_im_reg, 17);
twdl_sum <= adder_add_cast_2 + adder_add_cast_3;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly1 <= din1_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 34);
Complex3Add_tmpResult_reg <= to_signed(0, 34);
Complex3Add_multRes_re_reg1 <= to_signed(0, 33);
Complex3Add_multRes_re_reg2 <= to_signed(0, 33);
Complex3Add_multRes_im_reg <= to_signed(0, 35);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(32 DOWNTO 0);
VARIABLE sub_cast_0 : signed(32 DOWNTO 0);
VARIABLE sub_cast_1 : signed(34 DOWNTO 0);
VARIABLE sub_cast_2 : signed(34 DOWNTO 0);
VARIABLE add_cast : signed(32 DOWNTO 0);
VARIABLE add_cast_0 : signed(32 DOWNTO 0);
VARIABLE add_temp : signed(32 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 33);
sub_cast_0 := resize(prodOfIm, 33);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 35);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 35);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 33);
add_cast_0 := resize(prodOfIm, 33);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 34);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin1_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_3_re_tmp <= multResFP_re(29 DOWNTO 14);
twdlXdin_3_re <= std_logic_vector(twdlXdin_3_re_tmp);
twdlXdin_3_im_tmp <= multResFP_im(29 DOWNTO 14);
twdlXdin_3_im <= std_logic_vector(twdlXdin_3_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | FFT_HDL/transceiver_hdl/OFDM_transmitter/Complex3Multiply_block8.vhd | 1 | 12776 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/Complex3Multiply_block8.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block8
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block8 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din2_re_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
din2_im_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
di2_vld_dly3 : IN std_logic;
twdl_3_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin2_vld : OUT std_logic
);
END Complex3Multiply_block8;
ARCHITECTURE rtl OF Complex3Multiply_block8 IS
-- Signals
SIGNAL din2_re_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din_re_reg : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_im_dly3_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din_im_reg : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL adder_add_cast : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL adder_add_cast_1 : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din_sum : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdl_3_14_re_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_re_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_14_im_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_im_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL adder_add_cast_2 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL adder_add_cast_3 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL twdl_sum : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(31 DOWNTO 0); -- sfix32
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(31 DOWNTO 0); -- sfix32
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(15 DOWNTO 0); -- sfix16
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL prodOfRe : signed(31 DOWNTO 0); -- sfix32_En27
SIGNAL prodOfIm : signed(31 DOWNTO 0); -- sfix32_En27
SIGNAL prodOfSum : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Add_multRes_re_reg1 : signed(32 DOWNTO 0); -- sfix33
SIGNAL Complex3Add_multRes_re_reg2 : signed(32 DOWNTO 0); -- sfix33
SIGNAL Complex3Add_multRes_im_reg : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Add_tmpResult_reg_next : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL Complex3Add_multRes_re_reg1_next : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL Complex3Add_multRes_re_reg2_next : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL Complex3Add_multRes_im_reg_next : signed(34 DOWNTO 0); -- sfix35_En27
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(33 DOWNTO 0); -- sfix34_En27
SIGNAL multResFP_re : signed(32 DOWNTO 0); -- sfix33_En27
SIGNAL multResFP_im : signed(34 DOWNTO 0); -- sfix35_En27
SIGNAL twdlXdin_14_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_14_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
din2_re_dly3_signed <= signed(din2_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#0000#, 16);
ELSE
din_re_reg <= din2_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din2_im_dly3_signed <= signed(din2_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#0000#, 16);
ELSE
din_im_reg <= din2_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
adder_add_cast <= resize(din_re_reg, 17);
adder_add_cast_1 <= resize(din_im_reg, 17);
din_sum <= adder_add_cast + adder_add_cast_1;
twdl_3_14_re_signed <= signed(twdl_3_14_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSE
twdl_re_reg <= twdl_3_14_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_14_im_signed <= signed(twdl_3_14_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSE
twdl_im_reg <= twdl_3_14_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast_2 <= resize(twdl_re_reg, 17);
adder_add_cast_3 <= resize(twdl_im_reg, 17);
twdl_sum <= adder_add_cast_2 + adder_add_cast_3;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly1 <= di2_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 34);
Complex3Add_tmpResult_reg <= to_signed(0, 34);
Complex3Add_multRes_re_reg1 <= to_signed(0, 33);
Complex3Add_multRes_re_reg2 <= to_signed(0, 33);
Complex3Add_multRes_im_reg <= to_signed(0, 35);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(32 DOWNTO 0);
VARIABLE sub_cast_0 : signed(32 DOWNTO 0);
VARIABLE sub_cast_1 : signed(34 DOWNTO 0);
VARIABLE sub_cast_2 : signed(34 DOWNTO 0);
VARIABLE add_cast : signed(32 DOWNTO 0);
VARIABLE add_cast_0 : signed(32 DOWNTO 0);
VARIABLE add_temp : signed(32 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 33);
sub_cast_0 := resize(prodOfIm, 33);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 35);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 35);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 33);
add_cast_0 := resize(prodOfIm, 33);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 34);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin2_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_14_re_tmp <= multResFP_re(29 DOWNTO 14);
twdlXdin_14_re <= std_logic_vector(twdlXdin_14_re_tmp);
twdlXdin_14_im_tmp <= multResFP_im(29 DOWNTO 14);
twdlXdin_14_im <= std_logic_vector(twdlXdin_14_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | FFT_HDL/transceiver_hdl/OFDM_transmitter/RADIX22FFT_SDNF2_4_block1.vhd | 1 | 8562 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF2_4_block1.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block1
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_5 : IN std_logic; -- ufix1
dout_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block1;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block1 IS
-- Signals
SIGNAL dout_5_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_5_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_7_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_7_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_5_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_5_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_6_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_6_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
dout_5_re_signed <= signed(dout_5_re);
dout_5_im_signed <= signed(dout_5_im);
dout_7_re_signed <= signed(dout_7_re);
dout_7_im_signed <= signed(dout_7_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_5_re_signed, dout_5_im_signed,
dout_7_re_signed, dout_7_im_signed, dout_1_vld, rotate_5)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE add_cast_3 : signed(16 DOWNTO 0);
VARIABLE add_cast_4 : signed(16 DOWNTO 0);
VARIABLE add_cast_5 : signed(16 DOWNTO 0);
VARIABLE add_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_3 : signed(16 DOWNTO 0);
VARIABLE sub_cast_4 : signed(16 DOWNTO 0);
VARIABLE sub_cast_5 : signed(16 DOWNTO 0);
VARIABLE sub_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_5 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(dout_5_re_signed, 17);
add_cast_2 := resize(dout_7_im_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(dout_5_re_signed, 17);
sub_cast_2 := resize(dout_7_im_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(dout_5_im_signed, 17);
add_cast_6 := resize(dout_7_re_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(dout_5_im_signed, 17);
sub_cast_6 := resize(dout_7_re_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(dout_5_re_signed, 17);
add_cast_0 := resize(dout_7_re_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(dout_5_re_signed, 17);
sub_cast_0 := resize(dout_7_re_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(dout_5_im_signed, 17);
add_cast_4 := resize(dout_7_im_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(dout_5_im_signed, 17);
sub_cast_4 := resize(dout_7_im_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_5_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_5_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_6_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_6_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_6_re <= std_logic_vector(dout_6_re_tmp);
dout_6_im <= std_logic_vector(dout_6_im_tmp);
dout_5_re_1 <= std_logic_vector(dout_5_re_tmp);
dout_5_im_1 <= std_logic_vector(dout_5_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | FFT_HDL/transceiver_hdl/OFDM_transmitter/TWDLMULT_SDNF1_3_block3.vhd | 1 | 15155 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/TWDLMULT_SDNF1_3_block3.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block3
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_9_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block3;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block3 IS
-- Component Declarations
COMPONENT Complex3Multiply_block5
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din2_re_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
din2_im_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
di2_vld_dly3 : IN std_logic;
twdl_3_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block5
USE ENTITY work.Complex3Multiply_block5(rtl);
-- Signals
SIGNAL dout_9_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly1 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly2 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly3 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly4 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly5 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly6 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly7 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly8 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly9 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_9_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly1 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly2 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly3 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly4 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly5 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly6 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly7 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly8 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly9 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_11_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_re_dly1 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_re_dly2 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_11_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_im_dly1 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_im_dly2 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_re_dly3 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_im_dly3 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_10_re_tmp : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_10_im_tmp : std_logic_vector(15 DOWNTO 0); -- ufix16
BEGIN
u_MUL3_2 : Complex3Multiply_block5
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix16_En13
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix16_En13
di2_vld_dly3 => di2_vld_dly3,
twdl_3_10_re => twdl_3_10_re, -- sfix16_En14
twdl_3_10_im => twdl_3_10_im, -- sfix16_En14
softReset => softReset,
twdlXdin_10_re => twdlXdin_10_re_tmp, -- sfix16_En13
twdlXdin_10_im => twdlXdin_10_im_tmp, -- sfix16_En13
twdlXdin2_vld => twdlXdin_9_vld
);
dout_9_re_signed <= signed(dout_9_re);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly1 <= dout_9_re_signed;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly4 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly4 <= din1_re_dly3;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly5 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly5 <= din1_re_dly4;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly6 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly6 <= din1_re_dly5;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly7 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly7 <= din1_re_dly6;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly8 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly8 <= din1_re_dly7;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly9 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly9 <= din1_re_dly8;
END IF;
END IF;
END PROCESS intdelay_8_process;
twdlXdin_9_re <= std_logic_vector(din1_re_dly9);
dout_9_im_signed <= signed(dout_9_im);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly1 <= dout_9_im_signed;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly4 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly4 <= din1_im_dly3;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly5 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly5 <= din1_im_dly4;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly6 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly6 <= din1_im_dly5;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly7 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly7 <= din1_im_dly6;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly8 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly8 <= din1_im_dly7;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly9 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly9 <= din1_im_dly8;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_9_im <= std_logic_vector(din1_im_dly9);
dout_11_re_signed <= signed(dout_11_re);
intdelay_18_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly1 <= dout_11_re_signed;
END IF;
END IF;
END PROCESS intdelay_18_process;
intdelay_19_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_19_process;
dout_11_im_signed <= signed(dout_11_im);
intdelay_20_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly1 <= dout_11_im_signed;
END IF;
END IF;
END PROCESS intdelay_20_process;
intdelay_21_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_21_process;
intdelay_22_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_22_process;
intdelay_23_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_23_process;
intdelay_24_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_24_process;
intdelay_25_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_25_process;
intdelay_26_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_26_process;
twdlXdin_10_re <= twdlXdin_10_re_tmp;
twdlXdin_10_im <= twdlXdin_10_im_tmp;
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLMULT_SDNF1_3_block4.vhd | 1 | 14121 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLMULT_SDNF1_3_block4.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block4
-- Source Path: hdl_ofdm_tx/ifft/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_10_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_10_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_12_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_12_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_2_vld : IN std_logic;
twdl_3_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_11_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_11_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_12_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_12_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_11_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block4;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block4 IS
-- Component Declarations
COMPONENT Complex3Multiply_block6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din1_re_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din1_im_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din1_vld_dly3 : IN std_logic;
twdl_3_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_11_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_11_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT Complex3Multiply_block7
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din2_re_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din2_im_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
di2_vld_dly3 : IN std_logic;
twdl_3_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_12_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_12_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block6
USE ENTITY work.Complex3Multiply_block6(rtl);
FOR ALL : Complex3Multiply_block7
USE ENTITY work.Complex3Multiply_block7(rtl);
-- Signals
SIGNAL dout_10_re_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_re : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_10_im_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_im : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_vld_dly1 : std_logic;
SIGNAL din1_vld_dly2 : std_logic;
SIGNAL din1_vld_dly3 : std_logic;
SIGNAL twdlXdin_11_re_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
SIGNAL twdlXdin_11_im_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
SIGNAL twdlXdin1_vld : std_logic;
SIGNAL dout_12_re_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_re_1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_12_im_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_im_1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_12_re_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
SIGNAL twdlXdin_12_im_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
BEGIN
u_MUL3_1 : Complex3Multiply_block6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
din1_re_dly3 => std_logic_vector(din1_re_dly3), -- sfix19_En13
din1_im_dly3 => std_logic_vector(din1_im_dly3), -- sfix19_En13
din1_vld_dly3 => din1_vld_dly3,
twdl_3_11_re => twdl_3_11_re, -- sfix16_En14
twdl_3_11_im => twdl_3_11_im, -- sfix16_En14
softReset => softReset,
twdlXdin_11_re => twdlXdin_11_re_tmp, -- sfix19_En13
twdlXdin_11_im => twdlXdin_11_im_tmp, -- sfix19_En13
twdlXdin1_vld => twdlXdin1_vld
);
u_MUL3_2 : Complex3Multiply_block7
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix19_En13
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix19_En13
di2_vld_dly3 => di2_vld_dly3,
twdl_3_12_re => twdl_3_12_re, -- sfix16_En14
twdl_3_12_im => twdl_3_12_im, -- sfix16_En14
softReset => softReset,
twdlXdin_12_re => twdlXdin_12_re_tmp, -- sfix19_En13
twdlXdin_12_im => twdlXdin_12_im_tmp, -- sfix19_En13
twdlXdin2_vld => twdlXdin_11_vld
);
dout_10_re_signed <= signed(dout_10_re);
din_re <= resize(dout_10_re_signed, 19);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly1 <= din_re;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
dout_10_im_signed <= signed(dout_10_im);
din_im <= resize(dout_10_im_signed, 19);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly1 <= din_im;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_vld_dly2 <= din1_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_vld_dly3 <= din1_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_8_process;
dout_12_re_signed <= signed(dout_12_re);
din_re_1 <= resize(dout_12_re_signed, 19);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly1 <= din_re_1;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
dout_12_im_signed <= signed(dout_12_im);
din_im_1 <= resize(dout_12_im_signed, 19);
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly1 <= din_im_1;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_11_re <= twdlXdin_11_re_tmp;
twdlXdin_11_im <= twdlXdin_11_im_tmp;
twdlXdin_12_re <= twdlXdin_12_re_tmp;
twdlXdin_12_im <= twdlXdin_12_im_tmp;
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_ofdm_tx_pkg.vhd | 1 | 834 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_ofdm_tx_pkg.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE hdl_ofdm_tx_pkg IS
TYPE vector_of_std_logic_vector16 IS ARRAY (NATURAL RANGE <>) OF std_logic_vector(15 DOWNTO 0);
TYPE vector_of_signed16 IS ARRAY (NATURAL RANGE <>) OF signed(15 DOWNTO 0);
TYPE vector_of_std_logic_vector20 IS ARRAY (NATURAL RANGE <>) OF std_logic_vector(19 DOWNTO 0);
TYPE vector_of_unsigned8 IS ARRAY (NATURAL RANGE <>) OF unsigned(7 DOWNTO 0);
TYPE vector_of_signed20 IS ARRAY (NATURAL RANGE <>) OF signed(19 DOWNTO 0);
END hdl_ofdm_tx_pkg;
| gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/ifft_16_bit/Complex3Multiply.vhd | 1 | 12356 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/Complex3Multiply.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din2_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din2_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
di2_vld_dly3 : IN std_logic;
twdl_3_2_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_2_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_2_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_2_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin2_vld : OUT std_logic
);
END Complex3Multiply;
ARCHITECTURE rtl OF Complex3Multiply IS
-- Signals
SIGNAL din2_re_dly3_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly3_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_sum : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdl_3_2_re_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_re_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_2_im_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_im_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL adder_add_cast : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL adder_add_cast_1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL twdl_sum : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL prodOfRe : signed(33 DOWNTO 0); -- sfix34_En15
SIGNAL prodOfIm : signed(33 DOWNTO 0); -- sfix34_En15
SIGNAL prodOfSum : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_multRes_re_reg1 : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_multRes_re_reg2 : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_multRes_im_reg : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_tmpResult_reg_next : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL Complex3Add_multRes_re_reg1_next : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL Complex3Add_multRes_re_reg2_next : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL Complex3Add_multRes_im_reg_next : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL multResFP_re : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL multResFP_im : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL twdlXdin_2_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_2_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
din2_re_dly3_signed <= signed(din2_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 17);
ELSE
din_re_reg <= din2_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din2_im_dly3_signed <= signed(din2_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 17);
ELSE
din_im_reg <= din2_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
din_sum <= resize(din_re_reg, 18) + resize(din_im_reg, 18);
twdl_3_2_re_signed <= signed(twdl_3_2_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSE
twdl_re_reg <= twdl_3_2_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_2_im_signed <= signed(twdl_3_2_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSE
twdl_im_reg <= twdl_3_2_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast <= resize(twdl_re_reg, 18);
adder_add_cast_1 <= resize(twdl_im_reg, 18);
twdl_sum <= adder_add_cast + adder_add_cast_1;
-- Complex3Multiply
Complex3Multiply_1_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_1_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly1 <= di2_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 36);
Complex3Add_tmpResult_reg <= to_signed(0, 36);
Complex3Add_multRes_re_reg1 <= to_signed(0, 35);
Complex3Add_multRes_re_reg2 <= to_signed(0, 35);
Complex3Add_multRes_im_reg <= to_signed(0, 37);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(34 DOWNTO 0);
VARIABLE sub_cast_0 : signed(34 DOWNTO 0);
VARIABLE sub_cast_1 : signed(36 DOWNTO 0);
VARIABLE sub_cast_2 : signed(36 DOWNTO 0);
VARIABLE add_cast : signed(34 DOWNTO 0);
VARIABLE add_cast_0 : signed(34 DOWNTO 0);
VARIABLE add_temp : signed(34 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 35);
sub_cast_0 := resize(prodOfIm, 35);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 37);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 37);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 35);
add_cast_0 := resize(prodOfIm, 35);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 36);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin2_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_2_re_tmp <= multResFP_re(31 DOWNTO 15);
twdlXdin_2_re <= std_logic_vector(twdlXdin_2_re_tmp);
twdlXdin_2_im_tmp <= multResFP_im(31 DOWNTO 15);
twdlXdin_2_im <= std_logic_vector(twdlXdin_2_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/ifft_16_bit/TWDLROM_3_8.vhd | 1 | 13825 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLROM_3_8.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_8
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLROM_3_8
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.ifft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_8 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_8_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_8_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_8_vld : OUT std_logic
);
END TWDLROM_3_8;
ARCHITECTURE rtl OF TWDLROM_3_8 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_8_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_8_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#1#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#1#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_8_re_tmp <= twdlIn_re;
twdl_3_8_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_8_re <= std_logic_vector(twdl_3_8_re_tmp);
twdl_3_8_im <= std_logic_vector(twdl_3_8_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_8_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_8_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | hdl_prj/hdlsrc/hdl_modulator/hdl_modulator.vhd | 1 | 6449 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_modulator/hdl_modulator.vhd
-- Created: 2018-02-20 12:01:50
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 0.0001
-- Target subsystem base rate: 0.0001
--
--
-- Clock Enable Sample Time
-- -------------------------------------------------------------
-- ce_out 0.0001
-- -------------------------------------------------------------
--
--
-- Output Signal Clock Enable Sample Time
-- -------------------------------------------------------------
-- baseband_mixed_signal ce_out 0.0001
-- -------------------------------------------------------------
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: hdl_modulator
-- Source Path: hdl_modulator
-- Hierarchy Level: 0
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY hdl_modulator IS
PORT( clk : IN std_logic;
reset_x : IN std_logic;
clk_enable : IN std_logic;
real_signal : IN std_logic_vector(19 DOWNTO 0); -- sfix20_En13
imag_signal : IN std_logic_vector(19 DOWNTO 0); -- sfix20_En13
ce_out : OUT std_logic;
baseband_mixed_signal : OUT std_logic_vector(36 DOWNTO 0) -- sfix37_En27
);
END hdl_modulator;
ARCHITECTURE rtl OF hdl_modulator IS
-- Component Declarations
COMPONENT wave_generator
PORT( u_u : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
x_x : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
y_y : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : wave_generator
USE ENTITY work.wave_generator(rtl);
-- Signals
SIGNAL enb : std_logic;
SIGNAL real_signal_signed : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL counter_wave_genation_out1 : unsigned(15 DOWNTO 0); -- uint16
SIGNAL count_to_fix_converter_out1 : unsigned(31 DOWNTO 0); -- ufix32_En19
SIGNAL samples_per_period_out1 : signed(31 DOWNTO 0); -- sfix32_En5
SIGNAL count_scaler_out1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Sine : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL Cosine : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL Cosine_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Sine_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL real_signal_modulator_out1 : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL imag_signal_signed : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL imag_signal_modulator_out1 : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL tx_signal_adder_add_cast : signed(36 DOWNTO 0); -- sfix37_En27
SIGNAL tx_signal_adder_add_cast_1 : signed(36 DOWNTO 0); -- sfix37_En27
SIGNAL tx_signal_adder_out1 : signed(36 DOWNTO 0); -- sfix37_En27
BEGIN
Uwave_generator_1 : wave_generator
PORT MAP( u_u => std_logic_vector(count_scaler_out1), -- sfix16_En14
x_x => Sine, -- sfix16_En14
y_y => Cosine -- sfix16_En14
);
real_signal_signed <= signed(real_signal);
enb <= clk_enable;
-- Count limited, Unsigned Counter
-- initial value = 0
-- step value = 1
-- count to value = 511
counter_wave_genation_process : PROCESS (clk, reset_x)
BEGIN
IF reset_x = '1' THEN
counter_wave_genation_out1 <= to_unsigned(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF counter_wave_genation_out1 >= to_unsigned(16#01FF#, 16) THEN
counter_wave_genation_out1 <= to_unsigned(16#0000#, 16);
ELSE
counter_wave_genation_out1 <= counter_wave_genation_out1 + to_unsigned(16#0001#, 16);
END IF;
END IF;
END IF;
END PROCESS counter_wave_genation_process;
count_to_fix_converter_out1 <= counter_wave_genation_out1(12 DOWNTO 0) & '0' & '0' & '0' & '0' & '0' & '0'
& '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0';
samples_per_period_out1 <= to_signed(16384, 32);
count_scaler_output : PROCESS (count_to_fix_converter_out1, samples_per_period_out1)
VARIABLE cc : signed(31 DOWNTO 0);
VARIABLE div_temp : signed(32 DOWNTO 0);
VARIABLE cast : signed(32 DOWNTO 0);
BEGIN
IF samples_per_period_out1 = to_signed(0, 32) THEN
cc := to_signed(2147483647, 32);
ELSE
cast := signed(resize(count_to_fix_converter_out1, 33));
div_temp := cast / samples_per_period_out1;
IF (div_temp(32) = '0') AND (div_temp(31) /= '0') THEN
cc := X"7FFFFFFF";
ELSIF (div_temp(32) = '1') AND (div_temp(31) /= '1') THEN
cc := X"80000000";
ELSE
cc := div_temp(31 DOWNTO 0);
END IF;
END IF;
IF (cc(31) = '0') AND (cc(30 DOWNTO 15) /= X"0000") THEN
count_scaler_out1 <= X"7FFF";
ELSIF (cc(31) = '1') AND (cc(30 DOWNTO 15) /= X"FFFF") THEN
count_scaler_out1 <= X"8000";
ELSE
count_scaler_out1 <= cc(15 DOWNTO 0);
END IF;
END PROCESS count_scaler_output;
Cosine_signed <= signed(Cosine);
Sine_signed <= signed(Sine);
real_signal_modulator_out1 <= real_signal_signed * Sine_signed;
imag_signal_signed <= signed(imag_signal);
imag_signal_modulator_out1 <= Cosine_signed * imag_signal_signed;
tx_signal_adder_add_cast <= resize(real_signal_modulator_out1, 37);
tx_signal_adder_add_cast_1 <= resize(imag_signal_modulator_out1, 37);
tx_signal_adder_out1 <= tx_signal_adder_add_cast + tx_signal_adder_add_cast_1;
baseband_mixed_signal <= std_logic_vector(tx_signal_adder_out1);
ce_out <= clk_enable;
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_2_block5.vhd | 1 | 7197 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_2_block5.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block5
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_2_block5 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_13 : IN std_logic; -- ufix1
dout_6_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_6_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_14_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_14_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_13_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_14_re_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_14_im_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block5;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block5 IS
-- Signals
SIGNAL dout_6_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_6_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_14_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_14_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_13_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_13_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_14_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_14_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
dout_6_re_signed <= signed(dout_6_re);
dout_6_im_signed <= signed(dout_6_im);
dout_14_re_signed <= signed(dout_14_re);
dout_14_im_signed <= signed(dout_14_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 18);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_6_re_signed, dout_6_im_signed,
dout_14_re_signed, dout_14_im_signed, dout_1_vld, rotate_13)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_13 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_6_re_signed, 18) + resize(dout_14_im_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_6_re_signed, 18) - resize(dout_14_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_6_im_signed, 18) + resize(dout_14_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_6_im_signed, 18) - resize(dout_14_re_signed, 18);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_6_re_signed, 18) + resize(dout_14_re_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_6_re_signed, 18) - resize(dout_14_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_6_im_signed, 18) + resize(dout_14_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_6_im_signed, 18) - resize(dout_14_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_13_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_13_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_14_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_14_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_13_re <= std_logic_vector(dout_13_re_tmp);
dout_13_im <= std_logic_vector(dout_13_im_tmp);
dout_14_re_1 <= std_logic_vector(dout_14_re_tmp);
dout_14_im_1 <= std_logic_vector(dout_14_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_4_block2.vhd | 1 | 7104 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_4_block2.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block2
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_7 : IN std_logic; -- ufix1
dout_6_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_6_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_8_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_8_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_7_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_8_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_8_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block2;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block2 IS
-- Signals
SIGNAL dout_6_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_6_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_8_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_re : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_8_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_im : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL dout_7_re_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_7_im_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_8_re_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_8_im_tmp : signed(20 DOWNTO 0); -- sfix21
BEGIN
dout_6_re_signed <= signed(dout_6_re);
din1_re <= resize(dout_6_re_signed, 21);
dout_6_im_signed <= signed(dout_6_im);
din1_im <= resize(dout_6_im_signed, 21);
dout_8_re_signed <= signed(dout_8_re);
din2_re <= resize(dout_8_re_signed, 21);
dout_8_im_signed <= signed(dout_8_im);
din2_im <= resize(dout_8_im_signed, 21);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#000000#, 22);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_7)
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_7 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 22) + resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 22) - resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 22) + resize(din2_re, 22);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 22) - resize(din2_re, 22);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 22) + resize(din2_re, 22);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 22) - resize(din2_re, 22);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 22) + resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 22) - resize(din2_im, 22);
END IF;
dout_7_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(20 DOWNTO 0);
dout_7_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(20 DOWNTO 0);
dout_8_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(20 DOWNTO 0);
dout_8_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(20 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_7_re <= std_logic_vector(dout_7_re_tmp);
dout_7_im <= std_logic_vector(dout_7_im_tmp);
dout_8_re_1 <= std_logic_vector(dout_8_re_tmp);
dout_8_im_1 <= std_logic_vector(dout_8_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_1_block1.vhd | 1 | 6348 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_1_block1.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block1
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_1_block1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_3_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_3_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_11_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_11_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_5_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_6_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_6_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18
dout_5_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block1;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block1 IS
-- Signals
SIGNAL twdlXdin_3_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_3_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_11_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdlXdin_11_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_5_re_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_5_im_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_6_re_tmp : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_6_im_tmp : signed(17 DOWNTO 0); -- sfix18
BEGIN
twdlXdin_3_re_signed <= signed(twdlXdin_3_re);
twdlXdin_3_im_signed <= signed(twdlXdin_3_im);
twdlXdin_11_re_signed <= signed(twdlXdin_11_re);
twdlXdin_11_im_signed <= signed(twdlXdin_11_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_3_re_signed,
twdlXdin_3_im_signed, twdlXdin_11_re_signed, twdlXdin_11_im_signed,
twdlXdin_1_vld)
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_3_re_signed, 19) + resize(twdlXdin_11_re_signed, 19);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_3_re_signed, 19) - resize(twdlXdin_11_re_signed, 19);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_3_im_signed, 19) + resize(twdlXdin_11_im_signed, 19);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_3_im_signed, 19) - resize(twdlXdin_11_im_signed, 19);
END IF;
dout_5_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(17 DOWNTO 0);
dout_5_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(17 DOWNTO 0);
dout_6_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(17 DOWNTO 0);
dout_6_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(17 DOWNTO 0);
dout_5_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_5_re <= std_logic_vector(dout_5_re_tmp);
dout_5_im <= std_logic_vector(dout_5_im_tmp);
dout_6_re <= std_logic_vector(dout_6_re_tmp);
dout_6_im <= std_logic_vector(dout_6_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | FFT_HDL/transceiver_hdl/OFDM_transmitter/RADIX22FFT_SDNF1_3_block4.vhd | 1 | 7485 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_3_block4.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block4
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block4;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block4 IS
-- Signals
SIGNAL twdlXdin_10_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_10_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_12_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_12_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_11_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_11_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_12_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_12_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
twdlXdin_10_re_signed <= signed(twdlXdin_10_re);
twdlXdin_10_im_signed <= signed(twdlXdin_10_im);
twdlXdin_12_re_signed <= signed(twdlXdin_12_re);
twdlXdin_12_im_signed <= signed(twdlXdin_12_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_10_re_signed,
twdlXdin_10_im_signed, twdlXdin_12_re_signed, twdlXdin_12_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_10_re_signed, 17);
add_cast_0 := resize(twdlXdin_12_re_signed, 17);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_10_re_signed, 17);
sub_cast_0 := resize(twdlXdin_12_re_signed, 17);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_10_im_signed, 17);
add_cast_2 := resize(twdlXdin_12_im_signed, 17);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_10_im_signed, 17);
sub_cast_2 := resize(twdlXdin_12_im_signed, 17);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_11_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_11_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_12_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_12_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_11_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_11_re <= std_logic_vector(dout_11_re_tmp);
dout_11_im <= std_logic_vector(dout_11_im_tmp);
dout_12_re <= std_logic_vector(dout_12_re_tmp);
dout_12_im <= std_logic_vector(dout_12_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/ifft_16_bit/TWDLROM_3_16.vhd | 1 | 13839 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLROM_3_16.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_16
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLROM_3_16
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.ifft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_16 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_16_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_vld : OUT std_logic
);
END TWDLROM_3_16;
ARCHITECTURE rtl OF TWDLROM_3_16 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_16_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_16_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#3#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_16_re_tmp <= twdlIn_re;
twdl_3_16_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_16_re <= std_logic_vector(twdl_3_16_re_tmp);
twdl_3_16_im <= std_logic_vector(twdl_3_16_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_16_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_16_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
| gpl-3.0 |
freecores/dds_synthesizer | vhdl/sine_lut/sine_lut_8_x_14.vhd | 2 | 3307 | -- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 8;
constant AMPL_WIDTH : integer := 14;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(603,AMPL_WIDTH),
conv_std_logic_vector(803,AMPL_WIDTH),
conv_std_logic_vector(1003,AMPL_WIDTH),
conv_std_logic_vector(1202,AMPL_WIDTH),
conv_std_logic_vector(1400,AMPL_WIDTH),
conv_std_logic_vector(1598,AMPL_WIDTH),
conv_std_logic_vector(1795,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(2185,AMPL_WIDTH),
conv_std_logic_vector(2378,AMPL_WIDTH),
conv_std_logic_vector(2569,AMPL_WIDTH),
conv_std_logic_vector(2759,AMPL_WIDTH),
conv_std_logic_vector(2948,AMPL_WIDTH),
conv_std_logic_vector(3135,AMPL_WIDTH),
conv_std_logic_vector(3319,AMPL_WIDTH),
conv_std_logic_vector(3502,AMPL_WIDTH),
conv_std_logic_vector(3683,AMPL_WIDTH),
conv_std_logic_vector(3861,AMPL_WIDTH),
conv_std_logic_vector(4037,AMPL_WIDTH),
conv_std_logic_vector(4211,AMPL_WIDTH),
conv_std_logic_vector(4382,AMPL_WIDTH),
conv_std_logic_vector(4551,AMPL_WIDTH),
conv_std_logic_vector(4716,AMPL_WIDTH),
conv_std_logic_vector(4879,AMPL_WIDTH),
conv_std_logic_vector(5039,AMPL_WIDTH),
conv_std_logic_vector(5196,AMPL_WIDTH),
conv_std_logic_vector(5350,AMPL_WIDTH),
conv_std_logic_vector(5501,AMPL_WIDTH),
conv_std_logic_vector(5648,AMPL_WIDTH),
conv_std_logic_vector(5792,AMPL_WIDTH),
conv_std_logic_vector(5932,AMPL_WIDTH),
conv_std_logic_vector(6069,AMPL_WIDTH),
conv_std_logic_vector(6202,AMPL_WIDTH),
conv_std_logic_vector(6332,AMPL_WIDTH),
conv_std_logic_vector(6457,AMPL_WIDTH),
conv_std_logic_vector(6579,AMPL_WIDTH),
conv_std_logic_vector(6697,AMPL_WIDTH),
conv_std_logic_vector(6811,AMPL_WIDTH),
conv_std_logic_vector(6920,AMPL_WIDTH),
conv_std_logic_vector(7026,AMPL_WIDTH),
conv_std_logic_vector(7127,AMPL_WIDTH),
conv_std_logic_vector(7224,AMPL_WIDTH),
conv_std_logic_vector(7316,AMPL_WIDTH),
conv_std_logic_vector(7405,AMPL_WIDTH),
conv_std_logic_vector(7488,AMPL_WIDTH),
conv_std_logic_vector(7567,AMPL_WIDTH),
conv_std_logic_vector(7642,AMPL_WIDTH),
conv_std_logic_vector(7712,AMPL_WIDTH),
conv_std_logic_vector(7778,AMPL_WIDTH),
conv_std_logic_vector(7838,AMPL_WIDTH),
conv_std_logic_vector(7894,AMPL_WIDTH),
conv_std_logic_vector(7946,AMPL_WIDTH),
conv_std_logic_vector(7992,AMPL_WIDTH),
conv_std_logic_vector(8034,AMPL_WIDTH),
conv_std_logic_vector(8070,AMPL_WIDTH),
conv_std_logic_vector(8102,AMPL_WIDTH),
conv_std_logic_vector(8129,AMPL_WIDTH),
conv_std_logic_vector(8152,AMPL_WIDTH),
conv_std_logic_vector(8169,AMPL_WIDTH),
conv_std_logic_vector(8181,AMPL_WIDTH),
conv_std_logic_vector(8181,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; | gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_2_block.vhd | 1 | 7178 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_2_block.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_2_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_3 : IN std_logic; -- ufix1
dout_3_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_3_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_11_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_11_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_3_im_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block IS
-- Signals
SIGNAL dout_3_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_3_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_11_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_11_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_3_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_3_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_4_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_4_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
dout_3_re_signed <= signed(dout_3_re);
dout_3_im_signed <= signed(dout_3_im);
dout_11_re_signed <= signed(dout_11_re);
dout_11_im_signed <= signed(dout_11_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 18);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_3_re_signed, dout_3_im_signed,
dout_11_re_signed, dout_11_im_signed, dout_1_vld, rotate_3)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_3 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_3_re_signed, 18) + resize(dout_11_im_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_3_re_signed, 18) - resize(dout_11_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_3_im_signed, 18) + resize(dout_11_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_3_im_signed, 18) - resize(dout_11_re_signed, 18);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_3_re_signed, 18) + resize(dout_11_re_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_3_re_signed, 18) - resize(dout_11_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_3_im_signed, 18) + resize(dout_11_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_3_im_signed, 18) - resize(dout_11_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_3_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_3_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_4_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_4_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_4_re <= std_logic_vector(dout_4_re_tmp);
dout_4_im <= std_logic_vector(dout_4_im_tmp);
dout_3_re_1 <= std_logic_vector(dout_3_re_tmp);
dout_3_im_1 <= std_logic_vector(dout_3_im_tmp);
END rtl;
| gpl-3.0 |
freecores/dds_synthesizer | vhdl/sine_lut/sine_lut_8_x_12.vhd | 2 | 3290 | -- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 8;
constant AMPL_WIDTH : integer := 12;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(546,AMPL_WIDTH),
conv_std_logic_vector(594,AMPL_WIDTH),
conv_std_logic_vector(642,AMPL_WIDTH),
conv_std_logic_vector(690,AMPL_WIDTH),
conv_std_logic_vector(737,AMPL_WIDTH),
conv_std_logic_vector(783,AMPL_WIDTH),
conv_std_logic_vector(830,AMPL_WIDTH),
conv_std_logic_vector(875,AMPL_WIDTH),
conv_std_logic_vector(920,AMPL_WIDTH),
conv_std_logic_vector(965,AMPL_WIDTH),
conv_std_logic_vector(1009,AMPL_WIDTH),
conv_std_logic_vector(1052,AMPL_WIDTH),
conv_std_logic_vector(1095,AMPL_WIDTH),
conv_std_logic_vector(1137,AMPL_WIDTH),
conv_std_logic_vector(1179,AMPL_WIDTH),
conv_std_logic_vector(1219,AMPL_WIDTH),
conv_std_logic_vector(1259,AMPL_WIDTH),
conv_std_logic_vector(1299,AMPL_WIDTH),
conv_std_logic_vector(1337,AMPL_WIDTH),
conv_std_logic_vector(1375,AMPL_WIDTH),
conv_std_logic_vector(1411,AMPL_WIDTH),
conv_std_logic_vector(1447,AMPL_WIDTH),
conv_std_logic_vector(1483,AMPL_WIDTH),
conv_std_logic_vector(1517,AMPL_WIDTH),
conv_std_logic_vector(1550,AMPL_WIDTH),
conv_std_logic_vector(1582,AMPL_WIDTH),
conv_std_logic_vector(1614,AMPL_WIDTH),
conv_std_logic_vector(1644,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1756,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; | gpl-3.0 |
jmacneal/Design-Project | FFT_HDL/transceiver_hdl/OFDM_transmitter/TWDLROM_3_10.vhd | 1 | 13890 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/TWDLROM_3_10.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_10
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/TWDLROM_3_10
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.OFDM_transmitter_pkg.ALL;
ENTITY TWDLROM_3_10 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_vld : OUT std_logic
);
END TWDLROM_3_10;
ARCHITECTURE rtl OF TWDLROM_3_10 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#4000#, 16), to_signed(16#3B21#, 16)); -- sfix16 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#0000#, 16), to_signed(-16#187E#, 16)); -- sfix16 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_10_re_tmp : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_10_im_tmp : signed(15 DOWNTO 0); -- sfix16_En14
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#1#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#2#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#2#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(15 DOWNTO 0);
VARIABLE twdlIn_im : signed(15 DOWNTO 0);
VARIABLE cast : signed(16 DOWNTO 0);
VARIABLE cast_0 : signed(16 DOWNTO 0);
VARIABLE cast_1 : signed(16 DOWNTO 0);
VARIABLE cast_2 : signed(16 DOWNTO 0);
VARIABLE cast_3 : signed(16 DOWNTO 0);
VARIABLE cast_4 : signed(16 DOWNTO 0);
VARIABLE cast_5 : signed(16 DOWNTO 0);
VARIABLE cast_6 : signed(16 DOWNTO 0);
VARIABLE cast_7 : signed(16 DOWNTO 0);
VARIABLE cast_8 : signed(16 DOWNTO 0);
VARIABLE cast_9 : signed(16 DOWNTO 0);
VARIABLE cast_10 : signed(16 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "010" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "100" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(16#2D41#, 16);
WHEN OTHERS =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 17);
cast_0 := - (cast);
twdlIn_re := cast_0(15 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 17);
cast_6 := - (cast_5);
twdlIn_im := cast_6(15 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 17);
cast_8 := - (cast_7);
twdlIn_im := cast_8(15 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 17);
cast_2 := - (cast_1);
twdlIn_re := cast_2(15 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 17);
cast_4 := - (cast_3);
twdlIn_re := cast_4(15 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 17);
cast_10 := - (cast_9);
twdlIn_im := cast_10(15 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_10_re_tmp <= twdlIn_re;
twdl_3_10_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_10_re <= std_logic_vector(twdl_3_10_re_tmp);
twdl_3_10_im <= std_logic_vector(twdl_3_10_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_10_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl_3_10_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
| gpl-3.0 |
freecores/dds_synthesizer | vhdl/sine_lut/sine_lut_12_x_8.vhd | 2 | 43894 | -- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 12;
constant AMPL_WIDTH : integer := 8;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; | gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_2_block6.vhd | 1 | 7120 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_2_block6.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block6
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_2_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_15 : IN std_logic; -- ufix1
dout_8_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_8_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_16_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_16_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_15_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_16_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_16_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block6;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block6 IS
-- Signals
SIGNAL dout_8_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din1_re : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_8_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din1_im : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_16_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din2_re : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_16_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din2_im : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_15_re_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_15_im_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_16_re_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_16_im_tmp : signed(18 DOWNTO 0); -- sfix19
BEGIN
dout_8_re_signed <= signed(dout_8_re);
din1_re <= resize(dout_8_re_signed, 19);
dout_8_im_signed <= signed(dout_8_im);
din1_im <= resize(dout_8_im_signed, 19);
dout_16_re_signed <= signed(dout_16_re);
din2_re <= resize(dout_16_re_signed, 19);
dout_16_im_signed <= signed(dout_16_im);
din2_im <= resize(dout_16_im_signed, 19);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_15)
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_15 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 20) + resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 20) - resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 20) + resize(din2_re, 20);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 20) - resize(din2_re, 20);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 20) + resize(din2_re, 20);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 20) - resize(din2_re, 20);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 20) + resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 20) - resize(din2_im, 20);
END IF;
dout_15_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(18 DOWNTO 0);
dout_15_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(18 DOWNTO 0);
dout_16_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(18 DOWNTO 0);
dout_16_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(18 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_15_re <= std_logic_vector(dout_15_re_tmp);
dout_15_im <= std_logic_vector(dout_15_im_tmp);
dout_16_re_1 <= std_logic_vector(dout_16_re_tmp);
dout_16_im_1 <= std_logic_vector(dout_16_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_4_block6.vhd | 1 | 7211 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_4_block6.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block6
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_15 : IN std_logic; -- ufix1
dout_14_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_14_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_16_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_16_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_15_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_16_re_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_16_im_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block6;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block6 IS
-- Signals
SIGNAL dout_14_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_14_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_16_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_16_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_15_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_15_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_16_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_16_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
dout_14_re_signed <= signed(dout_14_re);
dout_14_im_signed <= signed(dout_14_im);
dout_16_re_signed <= signed(dout_16_re);
dout_16_im_signed <= signed(dout_16_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 18);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_14_re_signed, dout_14_im_signed,
dout_16_re_signed, dout_16_im_signed, dout_1_vld, rotate_15)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_15 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_14_re_signed, 18) + resize(dout_16_im_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_14_re_signed, 18) - resize(dout_16_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_14_im_signed, 18) + resize(dout_16_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_14_im_signed, 18) - resize(dout_16_re_signed, 18);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_14_re_signed, 18) + resize(dout_16_re_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_14_re_signed, 18) - resize(dout_16_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_14_im_signed, 18) + resize(dout_16_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_14_im_signed, 18) - resize(dout_16_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_15_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_15_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_16_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_16_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_15_re <= std_logic_vector(dout_15_re_tmp);
dout_15_im <= std_logic_vector(dout_15_im_tmp);
dout_16_re_1 <= std_logic_vector(dout_16_re_tmp);
dout_16_im_1 <= std_logic_vector(dout_16_im_tmp);
END rtl;
| gpl-3.0 |
jmacneal/Design-Project | Display/hdlsrc/fft_16_bit/Complex3Multiply_block4.vhd | 1 | 12384 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply_block4.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block4
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din2_re_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din2_im_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
di2_vld_dly3 : IN std_logic;
twdl_3_8_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_8_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_8_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_8_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin2_vld : OUT std_logic
);
END Complex3Multiply_block4;
ARCHITECTURE rtl OF Complex3Multiply_block4 IS
-- Signals
SIGNAL din2_re_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_im_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_sum : signed(20 DOWNTO 0); -- sfix21
SIGNAL twdl_3_8_re_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_re_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_8_im_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_im_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL adder_add_cast : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL adder_add_cast_1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL twdl_sum : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(20 DOWNTO 0); -- sfix21
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL prodOfRe : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfIm : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfSum : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_multRes_re_reg1 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_re_reg2 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_im_reg : signed(39 DOWNTO 0); -- sfix40
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_tmpResult_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL Complex3Add_multRes_re_reg1_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_re_reg2_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_im_reg_next : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL multResFP_re : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL multResFP_im : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL twdlXdin_8_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_8_im_tmp : signed(19 DOWNTO 0); -- sfix20
BEGIN
din2_re_dly3_signed <= signed(din2_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSE
din_re_reg <= din2_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din2_im_dly3_signed <= signed(din2_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSE
din_im_reg <= din2_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
din_sum <= resize(din_re_reg, 21) + resize(din_im_reg, 21);
twdl_3_8_re_signed <= signed(twdl_3_8_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSE
twdl_re_reg <= twdl_3_8_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_8_im_signed <= signed(twdl_3_8_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSE
twdl_im_reg <= twdl_3_8_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast <= resize(twdl_re_reg, 18);
adder_add_cast_1 <= resize(twdl_im_reg, 18);
twdl_sum <= adder_add_cast + adder_add_cast_1;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly1 <= di2_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 39);
Complex3Add_tmpResult_reg <= to_signed(0, 39);
Complex3Add_multRes_re_reg1 <= to_signed(0, 38);
Complex3Add_multRes_re_reg2 <= to_signed(0, 38);
Complex3Add_multRes_im_reg <= to_signed(0, 40);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(37 DOWNTO 0);
VARIABLE sub_cast_0 : signed(37 DOWNTO 0);
VARIABLE sub_cast_1 : signed(39 DOWNTO 0);
VARIABLE sub_cast_2 : signed(39 DOWNTO 0);
VARIABLE add_cast : signed(37 DOWNTO 0);
VARIABLE add_cast_0 : signed(37 DOWNTO 0);
VARIABLE add_temp : signed(37 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 38);
sub_cast_0 := resize(prodOfIm, 38);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 40);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 40);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 38);
add_cast_0 := resize(prodOfIm, 38);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 39);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin2_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_8_re_tmp <= multResFP_re(34 DOWNTO 15);
twdlXdin_8_re <= std_logic_vector(twdlXdin_8_re_tmp);
twdlXdin_8_im_tmp <= multResFP_im(34 DOWNTO 15);
twdlXdin_8_im <= std_logic_vector(twdlXdin_8_im_tmp);
END rtl;
| gpl-3.0 |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/example_design/rtl/mcb_soft_calibration.vhd | 10 | 90302 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
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-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for MCB Soft
-- Calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working
-- correctly)
-- 1.2: 2/12/09: Many other changes.
-- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within
-- STATE
-- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE
-- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock.
-- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT.
-- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets
-- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" *) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to
-- RST_DELAY.
-- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least
-- 16 clocks. Added PNSKEW option.
-- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing.
-- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg.
-- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced
-- with 8bit TARGET_DQS_DELAY which
-- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL.
-- Changed DQS_COUNT* to DQS_DELAY*.
-- Changed MCB_SYSRST port back to wire (from reg).
-- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG)
-- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing.
-- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic;
-- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1)
-- 3.4: 03/04/10: Recoded the RST_Reg logic.
-- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16)
-- 3.6 03/10/10: Improvements to Reset logic.
-- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
-- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL).
-- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz.
-- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic.
-- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity.
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic ;
MCB_UIDQLOWERINC : out std_logic ;
MCB_UIDQUPPERDEC : out std_logic ;
MCB_UIDQUPPERINC : out std_logic ;
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end entity mcb_soft_calibration;
architecture trans of mcb_soft_calibration is
constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1');
constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0');
constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1');
constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0');
constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1');
constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0');
constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1');
constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0');
constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1');
constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0');
constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1');
constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0');
constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1');
constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0');
constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1');
constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0');
constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1');
constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0');
constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1');
constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0');
constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1');
constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0');
constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1');
constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0');
constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1');
constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0');
constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1');
constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0');
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1');
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0');
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1');
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0');
constant START : std_logic_vector(5 downto 0) := "000000";
constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001";
constant WAIT1 : std_logic_vector(5 downto 0) := "000010";
constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011";
constant WAIT2 : std_logic_vector(5 downto 0) := "000100";
constant INC_PTERM : std_logic_vector(5 downto 0) := "000101";
constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110";
constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111";
constant WAIT3 : std_logic_vector(5 downto 0) := "001000";
constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001";
constant WAIT4 : std_logic_vector(5 downto 0) := "001010";
constant INC_NTERM : std_logic_vector(5 downto 0) := "001011";
constant SKEW : std_logic_vector(5 downto 0) := "001100";
constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101";
constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110";
constant WAIT5 : std_logic_vector(5 downto 0) := "001111";
constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000";
constant WAIT6 : std_logic_vector(5 downto 0) := "010001";
constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010";
constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011";
constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100";
constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101";
constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110";
constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111";
constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000";
constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001";
constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010";
constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011";
constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100";
constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101";
constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110";
constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111";
constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000";
constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001";
constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010";
constant WAIT7 : std_logic_vector(5 downto 0) := "100011";
constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100";
constant WAIT8 : std_logic_vector(5 downto 0) := "100101";
constant RST_DELAY : std_logic_vector(5 downto 0) := "100110";
constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111";
constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000";
constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001";
constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010";
constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011";
constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100";
constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101";
constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110";
constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111";
constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000";
constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001";
constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010";
constant WAIT9 : std_logic_vector(5 downto 0) := "110011";
constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100";
constant WAIT10 : std_logic_vector(5 downto 0) := "110101";
constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110";
constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111";
constant INCREMENT : std_logic_vector(5 downto 0) := "111000";
constant DECREMENT : std_logic_vector(5 downto 0) := "111001";
constant DONE : std_logic_vector(5 downto 0) := "111010";
--constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011";
constant RZQ : std_logic_vector(1 downto 0) := "00";
constant ZIO : std_logic_vector(1 downto 0) := "01";
constant MCB_PORT : std_logic_vector(1 downto 0) := "11";
constant WRITE_MODE : std_logic := '0';
constant READ_MODE : std_logic := '1';
-- IOI Registers
constant NoOp : std_logic_vector(7 downto 0) := "00000000";
constant DelayControl : std_logic_vector(7 downto 0) := "00000001";
constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010";
constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011";
constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100";
constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101";
constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110";
constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111";
constant MaxValue : std_logic_vector(7 downto 0) := "00001000";
-- IOB Registers
constant PDrive : std_logic_vector(7 downto 0) := "10000000";
constant PTerm : std_logic_vector(7 downto 0) := "10000001";
constant NDrive : std_logic_vector(7 downto 0) := "10000010";
constant NTerm : std_logic_vector(7 downto 0) := "10000011";
constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100";
constant LVDSControl : std_logic_vector(7 downto 0) := "10000101";
constant MiscControl : std_logic_vector(7 downto 0) := "10000110";
constant InputControl : std_logic_vector(7 downto 0) := "10000111";
constant TestReadback : std_logic_vector(7 downto 0) := "10001000";
-- No multi/divide is required when a 55 ohm resister is used on RZQ
-- localparam MULT = 1;
-- localparam DIV = 1;
-- use 7/4 scaling factor when the 100 ohm RZQ is used
constant MULT : integer := 7;
constant DIV : integer := 4;
constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required
constant PNSKEWDQS : std_logic := '1';
constant MULT_S : integer := 9;
constant DIV_S : integer := 8;
constant MULT_W : integer := 7;
constant DIV_W : integer := 8;
constant DQS_NUMERATOR : integer := 3;
constant DQS_DENOMINATOR : integer := 8;
constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03";
-- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter,
-- 3 for three eighths
constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000";
constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := C_MEM_TZQINIT_MAXCNT + RST_CNT;
constant IN_TERM_PASS : std_logic := '0';
constant DYN_CAL_PASS : std_logic := '1';
component iodrp_mcb_controller is
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end component;
component iodrp_controller is
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic
);
end component;
signal P_Term : std_logic_vector(5 downto 0) := "000000";
signal N_Term : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_s : std_logic_vector(5 downto 0) := "000000";
signal N_Term_s : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_w : std_logic_vector(5 downto 0) := "000000";
signal N_Term_w : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000";
signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000";
signal STATE : std_logic_vector(5 downto 0);
signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0);
signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0);
signal Active_IODRP : std_logic_vector(1 downto 0);
signal IODRPCTRLR_R_WB : std_logic := '0';
signal IODRPCTRLR_CMD_VALID : std_logic := '0';
signal IODRPCTRLR_USE_BKST : std_logic := '0';
signal MCB_CMD_VALID : std_logic := '0';
signal MCB_USE_BKST : std_logic := '0';
signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's
-- SYSRST pin (MCB_SYSRST)
signal IODRP_SDO : std_logic;
signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000";
signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit
signal counter_en : std_logic := '0'; -- counter enable for "count"
signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done
signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance -
-- state machine will wait for this to be high
signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000";
signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays
signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if
-- the Max Value changes by more than the threshold
signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with
-- latency on UOREFRSHFLAG)
signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with
-- latency on UOREFRSHFLAG)
signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0);
signal IODRPCTRLR_RDY_BUSY_N : std_logic;
signal IODRP_CS : std_logic;
signal MCB_READ_DATA : std_logic_vector(7 downto 0);
signal RST_reg : std_logic;
signal Block_Reset : std_logic;
signal MCB_UODATAVALID_U : std_logic;
signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place
signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read
signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up
signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read
signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn
signal RstCounter : std_logic_vector(9 downto 0) := (others => '0');
signal rst_tmp : std_logic;
signal LastPass_DynCal : std_logic;
signal First_In_Term_Done : std_logic;
signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay
signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay
signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE
-- parameter = "CALIBRATION"
signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays
signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays
signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the
-- one-time or dynamic parameters are 1
signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either
-- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
signal Quarter_Max_Value : std_logic_vector(7 downto 0);
signal Half_Max_Value : std_logic_vector(7 downto 0);
signal PLL_LOCK_R1 : std_logic;
signal PLL_LOCK_R2 : std_logic;
signal MCB_RDY_BUSY_N : std_logic;
signal SELFREFRESH_REQ_R1 : std_logic;
signal SELFREFRESH_REQ_R2 : std_logic;
signal SELFREFRESH_REQ_R3 : std_logic;
signal SELFREFRESH_MCB_MODE_R1 : std_logic;
signal SELFREFRESH_MCB_MODE_R2 : std_logic;
signal SELFREFRESH_MCB_MODE_R3 : std_logic;
signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic;
signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic;
signal START_DYN_CAL_STATE_R1 : std_logic;
signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic;
-- Declare intermediate signals for referenced outputs
signal IODRP_ADD_xilinx0 : std_logic;
signal IODRP_SDI_xilinx1 : std_logic;
signal MCB_UIADD_xilinx2 : std_logic;
signal MCB_UISDI_xilinx11 : std_logic;
signal MCB_UICS_xilinx6 : std_logic;
signal MCB_UIBROADCAST_xilinx4 : std_logic;
signal MCB_UIADDR_int : std_logic_vector(4 downto 0);
signal MCB_UIDONECAL_xilinx7 : std_logic;
signal MCB_UIREAD_xilinx10 : std_logic;
signal SELFREFRESH_MODE_xilinx11 : std_logic;
signal Max_Value_int : std_logic_vector(7 downto 0);
signal Rst_condition1 : std_logic;
--signal Rst_condition2 : std_logic;
signal non_violating_rst : std_logic;
signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0);
signal WaitTimer : std_logic_vector(7 downto 0);
signal WarmEnough : std_logic;
signal WaitCountEnable : std_logic;
signal State_Start_DynCal_R1 : std_logic;
signal State_Start_DynCal : std_logic;
-- This function multiplies by a constant MULT and then divides by the DIV constant
function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is
variable Result : integer := 0;
variable temp : std_logic_vector(14 downto 0) := "000000000000000";
begin
for count in 0 to (MULT-1) loop
temp := temp + ("0000000" & Input);
end loop;
Result := (to_integer(unsigned(temp))) / (DIV);
temp := std_logic_vector(to_unsigned(Result,15));
return temp(7 downto 0);
end function Mult_Divide;
attribute syn_preserve : boolean;
attribute syn_preserve of P_Term : signal is TRUE;
attribute syn_preserve of N_Term : signal is TRUE;
attribute syn_preserve of P_Term_s : signal is TRUE;
attribute syn_preserve of N_Term_s : signal is TRUE;
attribute syn_preserve of P_Term_w : signal is TRUE;
attribute syn_preserve of N_Term_w : signal is TRUE;
attribute syn_preserve of P_Term_Prev : signal is TRUE;
attribute syn_preserve of N_Term_Prev : signal is TRUE;
attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE;
attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE;
attribute syn_preserve of Max_Value_Previous : signal is TRUE;
attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE;
attribute iob : string;
attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE";
begin
-- move the default assignment here to make FORMALITY happy.
START_BROADCAST <= '1';
MCB_RECAL <= '0';
MCB_UIDQLOWERDEC <= '0';
MCB_UIADDR <= MCB_UIADDR_int;
MCB_UIDQLOWERINC <= '0';
MCB_UIDQUPPERDEC <= '0';
MCB_UIDQUPPERINC <= '0';
Max_Value <= Max_Value_int;
-- Drive referenced outputs
IODRP_ADD <= IODRP_ADD_xilinx0;
IODRP_SDI <= IODRP_SDI_xilinx1;
MCB_UIADD <= MCB_UIADD_xilinx2;
MCB_UISDI <= MCB_UISDI_xilinx11;
MCB_UICS <= MCB_UICS_xilinx6;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7;
MCB_UIREAD <= MCB_UIREAD_xilinx10;
SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11;
Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG);
Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous;
Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1));
Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int;
Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1));
CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1
Half_Max_Value <= ('0' & Max_Value_int(7 downto 1));
Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2));
DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here
DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here
SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0';
-- skip dynamic input termination if either the one-time or dynamic parameters are 1
SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0';
-- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then
DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high
else
DONE_SOFTANDHARD_CAL <= '0';
end if;
end if;
end process;
iodrp_controller_inst : iodrp_controller
port map (
memcell_address => IODRPCTRLR_MEMCELL_ADDR,
write_data => IODRPCTRLR_WRITE_DATA,
read_data => IODRPCTRLR_READ_DATA,
rd_not_write => IODRPCTRLR_R_WB,
cmd_valid => IODRPCTRLR_CMD_VALID,
rdy_busy_n => IODRPCTRLR_RDY_BUSY_N,
use_broadcast => '0',
sync_rst => RST_reg,
DRP_CLK => UI_CLK,
DRP_CS => IODRP_CS,
DRP_SDI => IODRP_SDI_xilinx1,
DRP_ADD => IODRP_ADD_xilinx0,
DRP_SDO => IODRP_SDO,
DRP_BKST => open
);
iodrp_mcb_controller_inst : iodrp_mcb_controller
port map (
memcell_address => IODRPCTRLR_MEMCELL_ADDR,
write_data => IODRPCTRLR_WRITE_DATA,
read_data => MCB_READ_DATA,
rd_not_write => IODRPCTRLR_R_WB,
cmd_valid => MCB_CMD_VALID,
rdy_busy_n => MCB_RDY_BUSY_N,
use_broadcast => MCB_USE_BKST,
drp_ioi_addr => MCB_UIADDR_int,
sync_rst => RST_reg,
DRP_CLK => UI_CLK,
DRP_CS => MCB_UICS_xilinx6,
DRP_SDI => MCB_UISDI_xilinx11,
DRP_ADD => MCB_UIADD_xilinx2,
DRP_BKST => MCB_UIBROADCAST_xilinx4,
DRP_SDO => MCB_UOSDO,
MCB_UIREAD => MCB_UIREAD_xilinx10
);
process (UI_CLK, RST) begin
if (RST = '1') then
if (C_SIMULATION = "TRUE") then
WAIT_200us_COUNTER <= X"7FF0";
else
WAIT_200us_COUNTER <= (others => '0');
end if;
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '1') then
WAIT_200us_COUNTER <= WAIT_200us_COUNTER;
else
WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1';
end if;
end if;
end process;
-- init_sequence_skip: if (C_SIMULATION = "TRUE") generate
-- WAIT_200us_COUNTER <= X"FFFF";
-- process
-- begin
-- report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
-- wait;
-- end process;
-- end generate;
gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate
process (UI_CLK, RST) begin
if (RST = '1') then
CKE_Train <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then
CKE_Train <= '0';
elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then
CKE_Train <= '1';
else
CKE_Train <= '0';
end if;
end if;
end process;
end generate ;
gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
CKE_Train <= '0';
end if;
end process;
end generate ;
--********************************************
-- PLL_LOCK and RST signals
--********************************************
--MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's
-- SYSRST pin (MCB_SYSRST)
rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND
process (UI_CLK, RST) begin
if (RST = '1') then
--Block_Reset <= '0';
--RstCounter <= (others => '0');
--elsif (UI_CLK'event and UI_CLK = '1') then
-- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3)
Block_Reset <= '0';
RstCounter <= (others => '0');
elsif (UI_CLK'event and UI_CLK = '1') then
Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state
if (Pre_SYSRST = '1') then
RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10
else
if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute
Block_Reset <= '1'; -- STATE won't exit RST_DELAY state
RstCounter <= RstCounter + "1"; -- and Rst_Counter increments
end if;
end if;
end if;
--end if;
end process;
-- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT
non_violating_rst <= RST and Rst_condition1;
MCB_SYSRST <= Pre_SYSRST;
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
if (RstCounter >= TZQINIT_MAXCNT) then
Rst_condition1 <= '1';
else
Rst_condition1 <= '0';
end if;
end if;
end process;
-- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3)
-- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process.
-- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which
-- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which
-- will cause MCB to reset and reinitialize the memory afterwards.
-- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at
-- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module
-- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration
-- state machine will not reset during SUSPEND.
-- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to
-- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST.
-- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT
-- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration.
--process (UI_CLK) begin
-- if (UI_CLK'event and UI_CLK = '1') then
--
-- if (RstCounter < RST_CNT) then
-- Rst_condition2 <= '1';
-- else
-- Rst_condition2 <= '0';
-- end if;
-- end if;
--end process;
process (UI_CLK, non_violating_rst) begin
if (non_violating_rst = '1') then
RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '0') then
RST_reg <= '1';
else
--RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long
RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long
end if;
end if;
end process;
--********************************************
-- SUSPEND Logic
--********************************************
process (UI_CLK,RST)
begin
if (RST = '1') then
SELFREFRESH_MCB_MODE_R1 <= '0';
SELFREFRESH_MCB_MODE_R2 <= '0';
SELFREFRESH_MCB_MODE_R3 <= '0';
SELFREFRESH_REQ_R1 <= '0';
SELFREFRESH_REQ_R2 <= '0';
SELFREFRESH_REQ_R3 <= '0';
PLL_LOCK_R1 <= '0';
PLL_LOCK_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
-- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180
SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE;
SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1;
SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2;
-- SELFREFRESH_REQ is clocked by user's application clock
SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ;
SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1;
SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2;
PLL_LOCK_R1 <= PLL_LOCK;
PLL_LOCK_R2 <= PLL_LOCK_R1;
end if;
end process;
-- SELFREFRESH should only be deasserted after PLL_LOCK is asserted.
-- This is to make sure MCB get a locked sys_2x_clk before exiting
-- SELFREFRESH mode.
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
SELFREFRESH_MCB_REQ <= '0';
elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then
SELFREFRESH_MCB_REQ <= '0';
elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then
SELFREFRESH_MCB_REQ <= '1';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1';
elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then
-- START_DYN_CAL is next state
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
end if;
end if;
end process;
-- Need to detect when SM entering START_DYN_CAL
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
START_DYN_CAL_STATE_R1 <= '0';
else
-- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH;
if (STATE = START_DYN_CAL) then
START_DYN_CAL_STATE_R1 <= '1';
else
START_DYN_CAL_STATE_R1 <= '0';
end if;
if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1';
elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
end if;
end if;
end if;
end process;
-- SELFREFRESH_MCB_MODE deasserted status is hold off
-- until Soft_Calib has at least done one loop of DQS update.
-- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before
-- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before
-- user logic sending new commands to MCB.
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
SELFREFRESH_MODE_xilinx11 <= '0';
elsif (SELFREFRESH_MCB_MODE_R2 = '1') then
SELFREFRESH_MODE_xilinx11 <= '1';
elsif (WarmEnough = '1') then
SELFREFRESH_MODE_xilinx11 <= '0';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WaitCountEnable <= '0';
elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then
WaitCountEnable <= '0';
elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then
WaitCountEnable <= '1';
else
WaitCountEnable <= WaitCountEnable;
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
State_Start_DynCal <= '0';
elsif (STATE = START_DYN_CAL) then
State_Start_DynCal <= '1';
else
State_Start_DynCal <= '0';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
State_Start_DynCal_R1 <= '0';
else
State_Start_DynCal_R1 <= State_Start_DynCal;
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WaitTimer <= (others => '0');
WarmEnough <= '1';
elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then
WaitTimer <= (others => '0');
WarmEnough <= '0';
elsif (WaitTimer = X"04") then
WaitTimer <= WaitTimer ;
WarmEnough <= '1';
elsif (WaitCountEnable = '1') then
WaitTimer <= WaitTimer + '1';
else
WaitTimer <= WaitTimer ;
end if;
end if;
end process;
--********************************************
--Comparitor for Dynamic Calibration circuit
--********************************************
Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0';
Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0';
--*********************************************************************************************
--Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal
--*********************************************************************************************
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST_reg = '1') then
count <= "000000";
elsif (counter_en = '1') then
count <= count + "000001";
else
count <= "000000";
end if;
end if;
end process;
--*********************************************************************************************
-- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide
--*********************************************************************************************
process (UI_CLK, MCB_UODATAVALID)
begin
if(MCB_UODATAVALID = '1') then
MCB_UODATAVALID_U <= '1';
elsif(UI_CLK'event and UI_CLK = '1') then
MCB_UODATAVALID_U <= MCB_UODATAVALID;
end if;
end process;
--**************************************************************************************************************
--Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs)
--**************************************************************************************************************
process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO)
begin
case Active_IODRP is
when RZQ =>
RZQ_IODRP_CS <= IODRP_CS;
ZIO_IODRP_CS <= '0';
IODRP_SDO <= RZQ_IODRP_SDO;
when ZIO =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= IODRP_CS;
IODRP_SDO <= ZIO_IODRP_SDO;
when MCB_PORT =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= '0';
IODRP_SDO <= '0';
when others =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= '0';
IODRP_SDO <= '0';
end case;
end process;
--******************************************************************
--State Machine's Always block / Case statement for Next State Logic
--
--The WAIT1,2,etc states were required after every state where the
--DRP controller was used to do a write to the IODRPs - this is because
--there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller
--sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added
--soley for the purpose of reducing power, particularly on RZQ as
--that pin is expected to have a permanent external resistor to gnd.
--******************************************************************
NEXT_STATE_LOGIC: process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST_reg = '1') then -- Synchronous reset
MCB_CMD_VALID <= '0';
MCB_UIADDR_int <= "00000"; -- take control of UI/UO port
MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal.
MCB_UIDONECAL_xilinx7 <= '0';
MCB_USE_BKST <= '0';
MCB_UIDRPUPDATE <= '1';
Pre_SYSRST <= '1'; -- keeps MCB in reset
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= NoOp;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_USE_BKST <= '0';
P_Term <= "000000";
N_Term <= "0000000";
P_Term_s <= "000000";
N_Term_w <= "0000000";
P_Term_w <= "000000";
N_Term_s <= "0000000";
P_Term_Prev <= "000000";
N_Term_Prev <= "0000000";
Active_IODRP <= RZQ;
MCB_UILDQSINC <= '0'; --no inc or dec
MCB_UIUDQSINC <= '0'; --no inc or dec
MCB_UILDQSDEC <= '0'; --no inc or dec
MCB_UIUDQSDEC <= '0';
counter_en <= '0'; --flag that the First Dynamic Calibration completed
First_Dyn_Cal_Done <= '0';
Max_Value_int <= "00000000";
Max_Value_Previous <= "00000000";
STATE <= START;
DQS_DELAY <= "00000000";
DQS_DELAY_INITIAL <= "00000000";
TARGET_DQS_DELAY <= "00000000";
LastPass_DynCal <= IN_TERM_PASS;
First_In_Term_Done <= '0';
MCB_UICMD <= '0';
MCB_UICMDIN <= '0';
MCB_UIDQCOUNT <= "0000";
counter_inc <= "00000000";
counter_dec <= "00000000";
else
counter_en <= '0';
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= NoOp;
IODRPCTRLR_R_WB <= READ_MODE;
IODRPCTRLR_USE_BKST <= '0';
MCB_CMD_VALID <= '0'; --no inc or dec
MCB_UILDQSINC <= '0'; --no inc or dec
MCB_UIUDQSINC <= '0'; --no inc or dec
MCB_UILDQSDEC <= '0'; --no inc or dec
MCB_UIUDQSDEC <= '0';
MCB_USE_BKST <= '0';
MCB_UICMDIN <= '0';
DQS_DELAY <= DQS_DELAY;
TARGET_DQS_DELAY <= TARGET_DQS_DELAY;
case STATE is
when START => --h00
MCB_UICMDEN <= '1'; -- take control of UI/UO port
MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal.
P_Term <= "000000";
N_Term <= "0000000";
Pre_SYSRST <= '1'; -- keeps MCB in reset
LastPass_DynCal <= IN_TERM_PASS;
if (SKIP_IN_TERM_CAL = 1) then
STATE <= WRITE_CALIBRATE;
elsif (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_NTERM;
else
STATE <= START;
end if;
--***************************
-- IOB INPUT TERMINATION CAL
--***************************
when LOAD_RZQ_NTERM => --h01
Active_IODRP <= RZQ;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_NTERM;
else
STATE <= WAIT1;
end if;
when WAIT1 => --h02
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT1;
else
STATE <= LOAD_RZQ_PTERM;
end if;
when LOAD_RZQ_PTERM => --h03
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_PTERM;
else
STATE <= WAIT2;
end if;
when WAIT2 => --h04
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT2;
elsif ((RZQ_IN = '1') or (P_Term = "111111")) then
STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM
else
STATE <= INC_PTERM;
end if;
when INC_PTERM => --h05
P_Term <= P_Term + "000001";
STATE <= LOAD_RZQ_PTERM;
when MULTIPLY_DIVIDE => -- h06
-- 13/4/2011 compensate the added sync FF
P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0);
STATE <= LOAD_ZIO_PTERM;
when LOAD_ZIO_PTERM => --h07
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_ZIO_PTERM;
else
STATE <= WAIT3;
end if;
when WAIT3 => --h08
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT3;
else
STATE <= LOAD_ZIO_NTERM;
end if;
when LOAD_ZIO_NTERM => --h09
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_ZIO_NTERM;
else
STATE <= WAIT4;
end if;
when WAIT4 => --h0A
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT4;
elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then
if (PNSKEW = '1') then
STATE <= SKEW;
else
STATE <= WAIT_FOR_START_BROADCAST;
end if;
else
STATE <= INC_NTERM;
end if;
when INC_NTERM => --h0B
N_Term <= N_Term + "0000001";
STATE <= LOAD_ZIO_NTERM;
when SKEW => -- h0C
P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0);
P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0);
N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0);
P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0);
STATE <= WAIT_FOR_START_BROADCAST;
when WAIT_FOR_START_BROADCAST => --h0D
Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while
-- keeping the MCB in calibration mode
Active_IODRP <= MCB_PORT;
if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then
if (P_Term /= P_Term_Prev) then
STATE <= BROADCAST_PTERM;
P_Term_Prev <= P_Term;
elsif (N_Term /= N_Term_Prev) then
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
else
STATE <= OFF_RZQ_PTERM;
end if;
else
STATE <= WAIT_FOR_START_BROADCAST;
end if;
when BROADCAST_PTERM => --h0E
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
MCB_CMD_VALID <= '1';
MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through
MCB_USE_BKST <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= BROADCAST_PTERM;
else
STATE <= WAIT5;
end if;
when WAIT5 => --h0F
if ((not(MCB_RDY_BUSY_N)) = '1') then
STATE <= WAIT5;
elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
if (MCB_UOREFRSHFLAG = '1')then
MCB_UIDRPUPDATE <= '1';
if (N_Term /= N_Term_Prev) then
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
else
STATE <= OFF_RZQ_PTERM;
end if;
else
STATE <= WAIT5; -- wait for a Refresh cycle
end if;
else
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
end if;
when BROADCAST_NTERM => -- h10
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ("0" & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
MCB_CMD_VALID <= '1';
MCB_USE_BKST <= '1';
MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
if (MCB_RDY_BUSY_N = '1') then
STATE <= BROADCAST_NTERM;
else
STATE <= WAIT6;
end if;
when WAIT6 => -- h11
if (MCB_RDY_BUSY_N = '0') then
STATE <= WAIT6;
elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
if (MCB_UOREFRSHFLAG = '1')then
MCB_UIDRPUPDATE <= '1';
STATE <= OFF_RZQ_PTERM;
else
STATE <= WAIT6; -- wait for a Refresh cycle
end if;
else
-- if (PNSKEWDQS = '1') then
STATE <= LDQS_CLK_WRITE_P_TERM;
-- else
-- STATE <= OFF_RZQ_PTERM;
-- end if;
end if;
-- *********************
when LDQS_CLK_WRITE_P_TERM => -- h12
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_CLK_WRITE_P_TERM;
else
STATE <= LDQS_CLK_P_TERM_WAIT;
end if;
when LDQS_CLK_P_TERM_WAIT => --7'h13
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_CLK_P_TERM_WAIT;
else
STATE <= LDQS_CLK_WRITE_N_TERM;
end if;
when LDQS_CLK_WRITE_N_TERM => --7'h14
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_CLK_WRITE_N_TERM;
else
STATE <= LDQS_CLK_N_TERM_WAIT;
end if;
--**
when LDQS_CLK_N_TERM_WAIT => --7'h15
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_CLK_N_TERM_WAIT;
else
STATE <= LDQS_PIN_WRITE_P_TERM;
end if;
when LDQS_PIN_WRITE_P_TERM => --7'h16
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s;
MCB_UIADDR_int <= IOI_LDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_PIN_WRITE_P_TERM;
else
STATE <= LDQS_PIN_P_TERM_WAIT;
end if;
when LDQS_PIN_P_TERM_WAIT => --7'h17
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_PIN_P_TERM_WAIT;
else
STATE <= LDQS_PIN_WRITE_N_TERM;
end if;
when LDQS_PIN_WRITE_N_TERM => --7'h18
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w;
MCB_UIADDR_int <= IOI_LDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_PIN_WRITE_N_TERM;
else
STATE <= LDQS_PIN_N_TERM_WAIT;
end if;
when LDQS_PIN_N_TERM_WAIT => --7'h19
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_PIN_N_TERM_WAIT;
else
STATE <= UDQS_CLK_WRITE_P_TERM;
end if;
when UDQS_CLK_WRITE_P_TERM => --7'h1A
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_CLK_WRITE_P_TERM;
else
STATE <= UDQS_CLK_P_TERM_WAIT;
end if;
when UDQS_CLK_P_TERM_WAIT => --7'h1B
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_CLK_P_TERM_WAIT;
else
STATE <= UDQS_CLK_WRITE_N_TERM;
end if;
when UDQS_CLK_WRITE_N_TERM => --7'h1C
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_CLK_WRITE_N_TERM;
else
STATE <= UDQS_CLK_N_TERM_WAIT;
end if;
when UDQS_CLK_N_TERM_WAIT => --7'h1D
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_CLK_N_TERM_WAIT;
else
STATE <= UDQS_PIN_WRITE_P_TERM;
end if;
when UDQS_PIN_WRITE_P_TERM => --7'h1E
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s;
MCB_UIADDR_int <= IOI_UDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_PIN_WRITE_P_TERM;
else
STATE <= UDQS_PIN_P_TERM_WAIT;
end if;
when UDQS_PIN_P_TERM_WAIT => --7'h1F
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_PIN_P_TERM_WAIT;
else
STATE <= UDQS_PIN_WRITE_N_TERM;
end if;
when UDQS_PIN_WRITE_N_TERM => --7'h20
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w;
MCB_UIADDR_int <= IOI_UDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_PIN_WRITE_N_TERM;
else
STATE <= UDQS_PIN_N_TERM_WAIT;
end if;
when UDQS_PIN_N_TERM_WAIT => --7'h21
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_PIN_N_TERM_WAIT;
else
STATE <= OFF_RZQ_PTERM;
end if;
-- *********************
when OFF_RZQ_PTERM => -- h22
Active_IODRP <= RZQ;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
P_Term <= "000000";
N_Term <= "0000000";
MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= OFF_RZQ_PTERM;
else
STATE <= WAIT7;
end if;
when WAIT7 => -- h23
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT7;
else
STATE <= OFF_ZIO_NTERM;
end if;
when OFF_ZIO_NTERM => -- h24
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= OFF_ZIO_NTERM;
else
STATE <= WAIT8;
end if;
when WAIT8 => -- h25
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT8;
else
if (First_In_Term_Done = '1') then
STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning
else
STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ
end if;
end if;
when RST_DELAY => -- h26
MCB_UICMDEN <= '0'; -- release control of UI/UO port
if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ???
STATE <= RST_DELAY;
else
STATE <= START_DYN_CAL_PRE;
end if;
--***************************
--DYNAMIC CALIBRATION PORTION
--***************************
when START_DYN_CAL_PRE => -- h27
LastPass_DynCal <= IN_TERM_PASS;
MCB_UICMDEN <= '0'; -- release UICMDEN
MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
Pre_SYSRST <= '1'; -- SYSRST pulse
if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION
STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually
else
STATE <= WAIT_FOR_UODONE;
end if;
when WAIT_FOR_UODONE => -- h28
Pre_SYSRST <= '0'; -- SYSRST pulse
if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
MCB_UICMDEN <= '1'; -- grab UICMDEN
DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
STATE <= LDQS_WRITE_POS_INDELAY;
else
STATE <= WAIT_FOR_UODONE;
end if;
when LDQS_WRITE_POS_INDELAY => -- h29
IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_WRITE_POS_INDELAY;
else
STATE <= LDQS_WAIT1;
end if;
when LDQS_WAIT1 => -- h2A
if (MCB_RDY_BUSY_N = '0')then
STATE <= LDQS_WAIT1;
else
STATE <= LDQS_WRITE_NEG_INDELAY;
end if;
when LDQS_WRITE_NEG_INDELAY => -- h2B
IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= LDQS_WRITE_NEG_INDELAY;
else
STATE <= LDQS_WAIT2;
end if;
when LDQS_WAIT2 => -- 7'h2C
if(MCB_RDY_BUSY_N = '0')then
STATE <= LDQS_WAIT2;
else
STATE <= UDQS_WRITE_POS_INDELAY;
end if;
when UDQS_WRITE_POS_INDELAY => -- 7'h2D
IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= UDQS_WRITE_POS_INDELAY;
else
STATE <= UDQS_WAIT1;
end if;
when UDQS_WAIT1 => -- 7'h2E
if (MCB_RDY_BUSY_N = '0')then
STATE <= UDQS_WAIT1;
else
STATE <= UDQS_WRITE_NEG_INDELAY;
end if;
when UDQS_WRITE_NEG_INDELAY => -- 7'h2F
IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= UDQS_WRITE_NEG_INDELAY;
else
STATE <= UDQS_WAIT2;
end if;
when UDQS_WAIT2 => -- 7'h30
if (MCB_RDY_BUSY_N = '0')then
STATE <= UDQS_WAIT2;
else
DQS_DELAY <= DQS_DELAY_INITIAL;
TARGET_DQS_DELAY <= DQS_DELAY_INITIAL;
STATE <= START_DYN_CAL;
end if;
when START_DYN_CAL => -- h31
Pre_SYSRST <= '0'; -- SYSRST not driven
counter_inc <= (others => '0');
counter_dec <= (others => '0');
if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then
STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE
elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then
--IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
-- Alternate between Dynamic Input Termination and Dynamic Tuning routines
if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then
LastPass_DynCal <= IN_TERM_PASS;
STATE <= LOAD_RZQ_NTERM;
else
LastPass_DynCal <= DYN_CAL_PASS;
STATE <= WRITE_CALIBRATE;
end if;
else
STATE <= START_DYN_CAL;
end if;
when WRITE_CALIBRATE => -- h32
Pre_SYSRST <= '0';
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= DelayControl;
IODRPCTRLR_WRITE_DATA <= "00100000";
IODRPCTRLR_R_WB <= WRITE_MODE;
Active_IODRP <= RZQ;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= WRITE_CALIBRATE;
else
STATE <= WAIT9;
end if;
when WAIT9 => -- h33
counter_en <= '1';
if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE
STATE <= WAIT9;
else
STATE <= READ_MAX_VALUE;
end if;
when READ_MAX_VALUE => -- h34
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= MaxValue;
IODRPCTRLR_R_WB <= READ_MODE;
Max_Value_Previous <= Max_Value_int;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= READ_MAX_VALUE;
else
STATE <= WAIT10;
end if;
when WAIT10 => -- h35
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT10;
else
Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller
if (First_In_Term_Done = '0') then
STATE <= RST_DELAY;
First_In_Term_Done <= '1';
else
STATE <= ANALYZE_MAX_VALUE;
end if;
end if;
when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle.
if (First_Dyn_Cal_Done = '0')then
STATE <= FIRST_DYN_CAL;
elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then
STATE <= DECREMENT; -- May need to Decrement
TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
-- DQS_COUNT_VIRTUAL updated (could be negative value)
elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then
STATE <= INCREMENT; -- May need to Increment
TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
else
Max_Value_int <= Max_Value_Previous;
STATE <= START_DYN_CAL;
end if;
when FIRST_DYN_CAL => -- h37
First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed
STATE <= START_DYN_CAL;
when INCREMENT => -- h38
STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH
MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
when "101" =>
counter_inc <= counter_inc + '1';
STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle
if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then
-- if not at the upper limit yet, and you've waited 4 clks, increment
MCB_UILDQSINC <= '1';
MCB_UIUDQSINC <= '1';
DQS_DELAY <= DQS_DELAY + '1';
end if;
when "100" =>
if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then
STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH
end if;
when others =>
STATE <= START_DYN_CAL;
end case;
when DECREMENT => -- h39
STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH
MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
if (DQS_DELAY /= "00000000") then
case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
when "011" =>
counter_dec <= counter_dec + '1';
STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle
if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then
-- if not at the lower limit, and you've waited 4 clks, decrement
MCB_UILDQSDEC <= '1'; -- decrement
MCB_UIUDQSDEC <= '1'; -- decrement
DQS_DELAY <= DQS_DELAY - '1'; -- SBS
end if;
when "010" =>
if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement
STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH
end if;
when others =>
STATE <= START_DYN_CAL;
end case;
end if;
when DONE => -- h3A
Pre_SYSRST <= '0'; -- SYSRST cleared
MCB_UICMDEN <= '0'; -- release UICMDEN
STATE <= DONE;
when others =>
MCB_UICMDEN <= '0'; -- release UICMDEN
MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
Pre_SYSRST <= '0'; -- SYSRST not driven
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= "00000000";
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= '0';
IODRPCTRLR_USE_BKST <= '0';
P_Term <= "000000";
N_Term <= "0000000";
Active_IODRP <= ZIO;
Max_Value_Previous <= "00000000";
MCB_UILDQSINC <= '0'; -- no inc or dec
MCB_UIUDQSINC <= '0'; -- no inc or dec
MCB_UILDQSDEC <= '0'; -- no inc or dec
MCB_UIUDQSDEC <= '0'; -- no inc or dec
counter_en <= '0';
First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed
Max_Value_int <= Max_Value_int;
STATE <= START;
end case;
end if;
end if;
end process;
end architecture trans;
| gpl-3.0 |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/sim/mcb_flow_control.vhd | 20 | 18501 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_flow_control.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module is the main flow control between cmd_gen.v,
-- write_data_path and read_data_path modules.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mcb_flow_control IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full : IN STD_LOGIC;
cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_o : OUT STD_LOGIC;
last_word_wr_i : IN STD_LOGIC;
wdp_rdy_i : IN STD_LOGIC;
wdp_valid_o : OUT STD_LOGIC;
wdp_validB_o : OUT STD_LOGIC;
wdp_validC_o : OUT STD_LOGIC;
wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
last_word_rd_i : IN STD_LOGIC;
rdp_rdy_i : IN STD_LOGIC;
rdp_valid_o : OUT STD_LOGIC;
rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END mcb_flow_control;
ARCHITECTURE trans OF mcb_flow_control IS
constant READY : std_logic_vector(4 downto 0) := "00001";
constant READ : std_logic_vector(4 downto 0) := "00010";
constant WRITE : std_logic_vector(4 downto 0) := "00100";
constant CMD_WAIT : std_logic_vector(4 downto 0) := "01000";
constant REFRESH_ST : std_logic_vector(4 downto 0) := "10000";
constant RD : std_logic_vector(2 downto 0) := "001";
constant RDP : std_logic_vector(2 downto 0) := "011";
constant WR : std_logic_vector(2 downto 0) := "000";
constant WRP : std_logic_vector(2 downto 0) := "010";
constant REFRESH : std_logic_vector(2 downto 0) := "100";
constant NOP : std_logic_vector(2 downto 0) := "101";
SIGNAL cmd_fifo_rdy : STD_LOGIC;
SIGNAL cmd_rd : STD_LOGIC;
SIGNAL cmd_wr : STD_LOGIC;
SIGNAL cmd_others : STD_LOGIC;
SIGNAL push_cmd : STD_LOGIC;
SIGNAL xfer_cmd : STD_LOGIC;
SIGNAL rd_vld : STD_LOGIC;
SIGNAL wr_vld : STD_LOGIC;
SIGNAL cmd_rdy : STD_LOGIC;
SIGNAL cmd_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL addr_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rdp_valid : STD_LOGIC;
SIGNAL wdp_valid : STD_LOGIC;
SIGNAL wdp_validB : STD_LOGIC;
SIGNAL wdp_validC : STD_LOGIC;
SIGNAL current_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL next_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL tstpointA : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL push_cmd_r : STD_LOGIC;
SIGNAL wait_done : STD_LOGIC;
SIGNAL cmd_en_r1 : STD_LOGIC;
SIGNAL wr_in_progress : STD_LOGIC;
SIGNAL tst_cmd_rdy_o : STD_LOGIC;
SIGNAL cmd_wr_pending_r1 : STD_LOGIC;
SIGNAL cmd_rd_pending_r1 : STD_LOGIC;
-- Declare intermediate signals for referenced outputs
SIGNAL cmd_rdy_o_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
cmd_en_o <= cmd_en_r1;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_rdy_o_xhdl0 <= cmd_rdy;
tst_cmd_rdy_o <= cmd_rdy;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
cmd_en_r1 <= '0' ;
ELSIF (xfer_cmd = '1') THEN
cmd_en_r1 <= '1' ;
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_en_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
cmd_fifo_rdy <= '1';
ELSIF (xfer_cmd = '1') THEN
cmd_fifo_rdy <= '0';
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_fifo_rdy <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
addr_o <= (others => '0');
cmd_o <= (others => '0');
bl_o <= (others => '0');
ELSIF (xfer_cmd = '1') THEN
addr_o <= addr_reg;
IF (FAMILY = "SPARTAN6") THEN
cmd_o <= cmd_reg;
ELSE
cmd_o <= ("00" & cmd_reg(0));
END IF;
bl_o <= bl_reg;
END IF;
END IF;
END PROCESS;
wr_addr_o <= addr_i;
rd_addr_o <= addr_i;
rd_bl_o <= bl_i;
wr_bl_o <= bl_i;
wdp_valid_o <= wdp_valid;
wdp_validB_o <= wdp_validB;
wdp_validC_o <= wdp_validC;
rdp_valid_o <= rdp_valid;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
wait_done <= '1' ;
ELSIF (push_cmd_r = '1') THEN
wait_done <= '1' ;
ELSIF ((cmd_rdy_o_xhdl0 AND cmd_valid_i) = '1' AND FAMILY = "SPARTAN6") THEN
wait_done <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
push_cmd_r <= push_cmd ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (push_cmd = '1') THEN
cmd_reg <= cmd_i ;
addr_reg <= addr_i ;
bl_reg <= bl_i - "000001" ;
END IF;
END IF;
END PROCESS;
cmd_wr <= '1' WHEN (((cmd_i = WR) OR (cmd_i = WRP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_rd <= '1' WHEN (((cmd_i = RD) OR (cmd_i = RDP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_others <= '1' WHEN ((cmd_i(2) = '1') AND (cmd_valid_i = '1') AND (FAMILY = "SPARTAN6")) ELSE
'0';
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
cmd_wr_pending_r1 <= '0' ;
ELSIF (last_word_wr_i = '1') THEN
cmd_wr_pending_r1 <= '1' ;
ELSIF (push_cmd = '1') THEN
cmd_wr_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((cmd_rd AND push_cmd) = '1') THEN
cmd_rd_pending_r1 <= '1' ;
ELSIF (xfer_cmd = '1') THEN
cmd_rd_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
wr_in_progress <= '0';
ELSIF (last_word_wr_i = '1') THEN
wr_in_progress <= '0';
ELSIF (current_state = WRITE) THEN
wr_in_progress <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
current_state <= "00001" ;
ELSE
current_state <= next_state ;
END IF;
END IF;
END PROCESS;
PROCESS (current_state, rdp_rdy_i, cmd_rd, cmd_fifo_rdy, wdp_rdy_i, cmd_wr, last_word_rd_i, cmd_others, last_word_wr_i, cmd_valid_i, wait_done, wr_in_progress, cmd_wr_pending_r1)
BEGIN
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
cmd_rdy <= '0';
next_state <= current_state;
CASE current_state IS
WHEN READY =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '0';
rdp_valid <= '1';
ELSIF ((wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '0';
ELSE
next_state <= READY;
push_cmd <= '0';
END IF;
IF (cmd_fifo_rdy = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN REFRESH_ST =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_fifo_rdy and cmd_others) = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSIF ((not(cmd_fifo_rdy)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((cmd_fifo_rdy AND ((rdp_rdy_i AND cmd_rd) OR (wdp_rdy_i AND cmd_wr) OR (cmd_others))) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN READ =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
tstpointA <= "0101";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
tstpointA <= "0110";
ELSIF ((NOT(rdp_rdy_i)) = '1') THEN
next_state <= READ;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0111";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((last_word_rd_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
tstpointA <= "1000";
ELSIF ((NOT(cmd_fifo_rdy) OR NOT(wdp_rdy_i)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((((rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i) OR cmd_others) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done; --'1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN WRITE =>
IF ((cmd_fifo_rdy AND cmd_rd AND rdp_rdy_i AND last_word_wr_i) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
rdp_valid <= '1';
tstpointA <= "0000";
ELSIF ((NOT(wdp_rdy_i) OR (wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy AND last_word_wr_i)) = '1') THEN
next_state <= WRITE;
tstpointA <= "0001";
IF ((cmd_wr AND last_word_wr_i) = '1') THEN
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSE
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
END IF;
IF (last_word_wr_i = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSE
push_cmd <= '0';
xfer_cmd <= '0';
END IF;
ELSIF ((last_word_wr_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "0010";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((((NOT(cmd_fifo_rdy)) AND last_word_wr_i) OR (NOT(rdp_rdy_i)) OR (NOT(cmd_valid_i) AND wait_done)) = '1') THEN
next_state <= CMD_WAIT;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0011";
ELSE
next_state <= WRITE;
tstpointA <= "0100";
END IF;
IF ((last_word_wr_i AND (cmd_others OR (rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i)) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done;
ELSE
cmd_rdy <= '0';
END IF;
WHEN CMD_WAIT =>
IF ((NOT(cmd_fifo_rdy) OR wr_in_progress) = '1') THEN
next_state <= CMD_WAIT;
cmd_rdy <= '0';
tstpointA <= "1010";
ELSIF ((cmd_fifo_rdy AND rdp_rdy_i AND cmd_rd) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
cmd_rdy <= '1';
rdp_valid <= '1';
tstpointA <= "1011";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND (wait_done OR cmd_wr_pending_r1)) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
cmd_rdy <= '1';
tstpointA <= "1100";
ELSIF ((cmd_fifo_rdy AND cmd_others) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "1101";
cmd_rdy <= '1';
ELSE
next_state <= CMD_WAIT;
tstpointA <= "1110";
IF (((wdp_rdy_i AND rdp_rdy_i)) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
END IF;
WHEN OTHERS =>
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
next_state <= READY;
END CASE;
END PROCESS;
END trans;
| gpl-3.0 |
Pinwino/dbg_ohwr | debugger_gw/wb_debugger.vhd | 1 | 13867 | -------------------------------------------------------------------------------
-- Title : Wishbone Debugger component
-- Project : FMC DEL 1ns 4cha-stand-alone application (fmc-delay-1ns-4cha-sa)
-------------------------------------------------------------------------------
-- File : wb_debugger.vhd
-- Author : Jose Jimenez <[email protected]>
-- Company : University of Granada
-- Created : 2014-06-08
-- Last update: 2014-07-31
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-06-08 1.0 jjimenez Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.wb_irq_pkg.all;
use work.debugger_pkg.all;
use work.synthesis_descriptor.all;
entity wb_debugger is
generic(
g_dbg_dpram_size : integer;
g_dbg_init_file : string;
g_reset_vector : t_wishbone_address := x"00000000"; -- if wb_irq_lm32 from general-cores::proposed-master
g_msi_queues : natural := 1;
g_profile : string := "medium_icache_debug";
g_internal_time_ref : boolean := true;
g_timers : integer := 1;
g_slave_interface_mode: t_wishbone_interface_mode := PIPELINED;
g_slave_granularity : t_wishbone_address_granularity := BYTE);
port(
clk_sys : in std_logic;
reset_n : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
wrpc_uart_rxd_i : inout std_logic;
wrpc_uart_txd_o : inout std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
dbg_indicator : out std_logic;
dbg_control_select : in std_logic);
end wb_debugger;
architecture Behavioral of wb_debugger is
function f_check_if_lm32_firmware_necessary return boolean is
begin
if(g_dbg_init_file /= "") then
return true;
else
return false;
end if;
end function;
function f_generate_irq_timer return integer is
begin
if(g_timers /= 0) then
return 1;
else
return 0;
end if;
end function;
function f_generate_time_ref return integer is
begin
if(g_internal_time_ref) then
return 1;
else
return 0;
end if;
end function;
function f_choose_lm32_firmware_file return string is
begin
if(g_dbg_init_file = "debugger") then
report "[Dbg Core] Using debugging firmware." severity note;
return "../../dbg.ram";
elsif (g_dbg_init_file = "FD_node") then
report "[Dbg Core] Using FMC Delay stand alone node firmware." severity note;
return "../../fd_std.ram";
else
report "[Dbg Core] Using user provided firmware." severity note;
return g_dbg_init_file;
end if;
end function;
function f_select_dpram_size return integer is
begin
if(g_dbg_init_file = "debugger") then
report "[Dbg Core] Using a 40960 Bytes size RAM." severity note;
return 40960/4;
elsif (g_dbg_init_file = "FD_node") then
report "[Dbg Core] Using a 94208 Bytes RAM." severity note;
return 94208/4;
else
report "[Dbg Core] Using user specifie size RAM size." severity note;
return g_dbg_dpram_size;
end if;
end function;
-- constant c_NUM_WB_MASTERS : integer := 6 + f_generate_irq_timer + f_generate_time_ref;
constant c_NUM_WB_MASTERS : integer := 4 + f_generate_irq_timer + f_generate_time_ref;
constant c_NUM_WB_SLAVES : integer := 3;
constant c_MASTER_LM32 : integer := 0;
constant c_MASTER_ADAPT : integer := 2;
constant c_EXT_BRIDGE : integer := 0;
constant c_SLAVE_DPRAM : integer := 1;
constant c_SLAVE_UART : integer := 2;
constant c_SLAVE_IRQ_CTRL : integer := 3;
constant c_SLAVE_TICS : integer := c_SLAVE_IRQ_CTRL + f_generate_time_ref;
constant c_SLAVE_TIMER_IRQ: integer := c_SLAVE_TICS + f_generate_irq_timer;
constant c_EXT_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"000effff", x"00000000");
constant c_FREQ_DIVIDER : integer := 62500; -- LM32 clk = 62.5 Mhz
function f_generate_c_interconection_layout(
num_wb_masters : integer;
last_mandatory_slave : integer
)
return t_sdb_record_array is
variable interconnect_layout : t_sdb_record_array(NUM_WB_MASTERS-1 downto 0);
variable offset : integer range last_mandatory_slave to NUM_WB_MASTERS-1 := last_mandatory_slave;
variable adr_off: unsigned (c_wishbone_address_width-1 downto 0);
begin
-- Vader is Coming Look Busy
interconnect_layout (offset downto 0):=
(c_EXT_BRIDGE => f_sdb_embed_bridge(c_EXT_BRIDGE_SDB, x"00100000"),
c_SLAVE_DPRAM => f_sdb_embed_device(f_xwb_dbg_dpram(f_select_dpram_size), x"00000000"),
c_SLAVE_UART => f_sdb_embed_device(c_dbg_uart_sdb, x"00020100"),
c_SLAVE_IRQ_CTRL => f_sdb_embed_device(c_dbg_irq_ctrl_sdb, x"00020200"));
adr_off := x"00020300";
if (f_generate_time_ref /= 0) then
offset := offset + f_generate_time_ref;
interconnect_layout (offset) := f_sdb_embed_device(c_xwb_dbg_tics_sdb, t_wishbone_address(adr_off));
adr_off := adr_off + x"100";
end if;
if (f_generate_irq_timer /= 0) then
offset := offset + f_generate_irq_timer;
interconnect_layout (offset) := f_sdb_embed_device(c_dbg_irq_timer_sdb, t_wishbone_address(adr_off));
adr_off := adr_off + x"100";
end if;
--interconnect_layout (offset+1) := f_sdb_embed_synthesis(c_sdb_synthesis_info);
--interconnect_layout (offset+2) := f_sdb_embed_repo_url(c_sdb_repo_url);
return interconnect_layout;
end function;
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array := f_generate_c_interconection_layout (c_NUM_WB_MASTERS, c_SLAVE_IRQ_CTRL);
constant c_SDB_ADDRESS : t_wishbone_address := x"00020800";
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array (c_NUM_WB_MASTERS-1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array (c_NUM_WB_SLAVES-1 downto 0);
signal dummy_debugger_ram_wbb_i : t_wishbone_slave_in;
signal forced_lm32_reset_n : std_logic := '1';
signal irq_slave_i : t_wishbone_slave_in_array(g_msi_queues-1 to 0);
signal irq_slave_o : t_wishbone_slave_out_array(g_msi_queues-1 to 0);
signal local_counter : unsigned (63 downto 0);
signal uart_dummy_i : std_logic;
signal uart_dummy_o : std_logic;
signal dbg_uart_rxd_i : std_logic;
signal dbg_uart_txd_o : std_logic;
signal use_dbg_uart : std_logic := '1';
signal state_control : unsigned (39 downto 0) := x"0000000000";
begin
dbg_indicator <= forced_lm32_reset_n;
master_o <= cnx_master_out(c_EXT_BRIDGE);
cnx_master_in(c_EXT_BRIDGE) <= master_i;
--------------------------------------
-- UART Selector & Reset controller
--------------------------------------
controller : process (clk_sys)
begin
if (rising_edge(clk_sys)) then
if (dbg_control_select = '0') then
if (state_control /= x"ffffffffff") then
state_control <= state_control + 1;
end if;
else
if ((state_control /= x"0000000000") and (state_control <= x"3B9ACA0")) then --0.5s
forced_lm32_reset_n <= not forced_lm32_reset_n;
elsif (state_control > x"3B9ACA0") then
use_dbg_uart <= not use_dbg_uart;
end if;
state_control <= x"0000000000";
end if;
end if;
end process;
--------------------------------------
-- UART
--------------------------------------
uart_txd_o <= dbg_uart_txd_o when use_dbg_uart ='1' else wrpc_uart_txd_o;
dbg_uart_rxd_i <= uart_rxd_i when use_dbg_uart ='1' else '1';
wrpc_uart_rxd_i <= uart_rxd_i when use_dbg_uart ='0' else '1';
DBG_UART : xwb_simple_uart
generic map(
g_with_virtual_uart => true,
g_with_physical_uart => true,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => reset_n,
slave_i => cnx_master_out(c_SLAVE_UART),
slave_o => cnx_master_in(c_SLAVE_UART),
desc_o => open,
uart_rxd_i => dbg_uart_rxd_i,
uart_txd_o => dbg_uart_txd_o
);
-----------------------------------------------------------------------------
-- LM32, with MSI interface
-----------------------------------------------------------------------------
DBG_IRQ_LM32_CORE : wb_irq_lm32
generic map(
g_msi_queues => g_msi_queues,
g_profile => g_profile
)
port map(
clk_sys_i => clk_sys,
rst_n_i => forced_lm32_reset_n,
dwb_o => cnx_slave_in(c_MASTER_LM32),
dwb_i => cnx_slave_out(c_MASTER_LM32),
iwb_o => cnx_slave_in(c_MASTER_LM32+1),
iwb_i => cnx_slave_out(c_MASTER_LM32+1),
irq_slave_o => irq_slave_o, -- wb msi interface
irq_slave_i => irq_slave_i,
ctrl_slave_o => cnx_master_in(c_SLAVE_IRQ_CTRL), -- ctrl interface for LM32 irq processing
ctrl_slave_i => cnx_master_out(c_SLAVE_IRQ_CTRL)
);
---------------------------------------------------------------------------
-- Dual-port RAM
-----------------------------------------------------------------------------
DBG_DPRAM : xwb_dpram
generic map(
g_size => f_select_dpram_size, --in 32-bit words
-- g_size => g_dbg_dpram_size, --in 32-bit words
g_init_file => f_choose_lm32_firmware_file,
g_must_have_init_file => f_check_if_lm32_firmware_necessary,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => WORD
)
port map(
clk_sys_i => clk_sys,
rst_n_i => reset_n,
slave1_i => cnx_master_out(c_SLAVE_DPRAM),
slave1_o => cnx_master_in(c_SLAVE_DPRAM),
slave2_i => dummy_debugger_ram_wbb_i,
slave2_o => open
);
---------------------------------------------------------------------------
-- TIMER
---------------------------------------------------------------------------
gen_time_ref : if (f_generate_time_ref /= 0) generate
begin
DBG_TIME_REF : xwb_tics
generic map(
g_period => c_FREQ_DIVIDER
)
port map(
clk_sys_i => clk_sys,
rst_n_i => reset_n,
-- Wishbone
slave_i => cnx_master_out(c_SLAVE_TICS),
slave_o => cnx_master_in(c_SLAVE_TICS),
desc_o => open
);
end generate gen_time_ref;
gen_timer : if (g_timers > 0) generate
begin
process(clk_sys)
begin
if (clk_sys'event and clk_sys = '1') then
if (reset_n = '0') then
local_counter <= (others => '0');
else
local_counter <= local_counter + 1;
end if;
end if;
end process;
DBG_IRQ_TIMER : wb_irq_timer
generic map(
g_timers => g_timers
)
port map(
clk_sys_i => clk_sys,
rst_sys_n_i => forced_lm32_reset_n,
tm_tai8ns_i => std_logic_vector(local_counter),
ctrl_slave_o => cnx_master_in(c_SLAVE_TIMER_IRQ), -- ctrl interface for LM32 irq processing
ctrl_slave_i => cnx_master_out(c_SLAVE_TIMER_IRQ),
irq_master_o => irq_slave_i(g_timers-1), -- wb msi interface
irq_master_i => irq_slave_o(g_timers-1)
);
end generate gen_timer;
---------------------------------------------------------------------------
-- Crossbar
---------------------------------------------------------------------------
DBG_MAIN_INTERCON : xwb_sdb_crossbar
generic map (
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS
)
port map (
clk_sys_i => clk_sys,
rst_n_i => reset_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out
);
---------------------------------------------------------------------------
-- Adatper
---------------------------------------------------------------------------
DBG_SALVE_ADAPTER : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => g_slave_interface_mode,
g_master_granularity => BYTE,
g_slave_use_struct => false,
g_slave_mode => g_slave_interface_mode,
g_slave_granularity => g_slave_granularity)
port map (
clk_sys_i => clk_sys,
rst_n_i => reset_n,
master_i => cnx_slave_out(c_MASTER_ADAPT),
master_o => cnx_slave_in(c_MASTER_ADAPT),
-- Slave interface 0x0 to 0x3ffff
sl_adr_i(c_wishbone_address_width-1 downto 18) => (others => '0'),
sl_adr_i(17 downto 0) => slave_i.adr(17 downto 0),
sl_dat_i => slave_i.dat,
sl_sel_i => slave_i.sel,
sl_cyc_i => slave_i.cyc,
sl_stb_i => slave_i.stb,
sl_we_i => slave_i.we,
sl_dat_o => slave_o.dat,
sl_ack_o => slave_o.ack,
sl_err_o => slave_o.err,
sl_rty_o => slave_o.rty,
sl_stall_o => slave_o.stall
);
end Behavioral;
| gpl-3.0 |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/functional/sys_clk_gen.vhd | 1 | 3296 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : sys_clk_gen.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity sys_clk_gen is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk : out std_logic
);
end sys_clk_gen;
architecture sim of sys_clk_gen is
constant HALFCYCLE_INT : time := HALFCYCLE * 1 ps;
constant OFFSET_INT : time := OFFSET * 1 ps;
signal sys_clk_c : std_logic := '0';
begin
clk_gen : process
begin
wait for OFFSET_INT;
while true loop
wait for HALFCYCLE_INT;
sys_clk_c <= not sys_clk_c;
end loop;
end process clk_gen;
sys_clk <= sys_clk_c;
end; -- sys_clk_gen
| gpl-3.0 |
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