repo_name
stringlengths 6
79
| path
stringlengths 5
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stringlengths 0
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|---|---|---|---|---|---|
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/example_design/PIO_EP_MEM_ACCESS.vhd | 1 | 15616 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : PIO_EP_MEM_ACCESS.vhd
-- Description: Endpoint Memory Access Unit. This module provides access
-- functions to the Endpoint memory aperture.
--
-- Read Access: Module returns data for the specifed address and
-- byte enables selected.
--
-- Write Access: Module accepts data, byte enables and updates
-- data when write enable is asserted. Modules signals write busy
-- when data write is in progress.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity PIO_EP_MEM_ACCESS is
port (
clk : in std_logic;
rst_n : in std_logic;
-- Read Port
rd_addr_i : in std_logic_vector(10 downto 0);
rd_be_i : in std_logic_vector(3 downto 0);
rd_data_o : out std_logic_vector(31 downto 0);
-- Write Port
wr_addr_i : in std_logic_vector(10 downto 0);
wr_be_i : in std_logic_vector(7 downto 0);
wr_data_i : in std_logic_vector(31 downto 0);
wr_en_i : in std_logic;
wr_busy_o : out std_logic
);
end PIO_EP_MEM_ACCESS;
architecture rtl of PIO_EP_MEM_ACCESS is
constant TCQ : time := 1 ns;
type state_type is (PIO_MEM_ACCESS_WR_RST,
PIO_MEM_ACCESS_WR_WAIT,
PIO_MEM_ACCESS_WR_READ,
PIO_MEM_ACCESS_WR_WRITE
);
component PIO_EP_MEM port (
clk_i : in std_logic;
a_rd_a_i_0 : in std_logic_vector(8 downto 0);
a_rd_d_o_0 : out std_logic_vector(31 downto 0);
a_rd_en_i_0 : in std_logic;
b_wr_a_i_0 : in std_logic_vector(8 downto 0);
b_wr_d_i_0 : in std_logic_vector(31 downto 0);
b_wr_en_i_0 : in std_logic;
b_rd_d_o_0 : out std_logic_vector(31 downto 0);
b_rd_en_i_0 : in std_logic;
a_rd_a_i_1 : in std_logic_vector(8 downto 0);
a_rd_d_o_1 : out std_logic_vector(31 downto 0);
a_rd_en_i_1 : in std_logic;
b_wr_a_i_1 : in std_logic_vector(8 downto 0);
b_wr_d_i_1 : in std_logic_vector(31 downto 0);
b_wr_en_i_1 : in std_logic;
b_rd_d_o_1 : out std_logic_vector(31 downto 0);
b_rd_en_i_1 : in std_logic;
a_rd_a_i_2 : in std_logic_vector(8 downto 0);
a_rd_d_o_2 : out std_logic_vector(31 downto 0);
a_rd_en_i_2 : in std_logic;
b_wr_a_i_2 : in std_logic_vector(8 downto 0);
b_wr_d_i_2 : in std_logic_vector(31 downto 0);
b_wr_en_i_2 : in std_logic;
b_rd_d_o_2 : out std_logic_vector(31 downto 0);
b_rd_en_i_2 : in std_logic;
a_rd_a_i_3 : in std_logic_vector(8 downto 0);
a_rd_d_o_3 : out std_logic_vector(31 downto 0);
a_rd_en_i_3 : in std_logic;
b_wr_a_i_3 : in std_logic_vector(8 downto 0);
b_wr_d_i_3 : in std_logic_vector(31 downto 0);
b_wr_en_i_3 : in std_logic;
b_rd_d_o_3 : out std_logic_vector(31 downto 0);
b_rd_en_i_3 : in std_logic
);
end component;
signal rd_data_raw_o : std_logic_vector(31 downto 0);
signal rd_data0_o : std_logic_vector(31 downto 0);
signal rd_data1_o : std_logic_vector(31 downto 0);
signal rd_data2_o : std_logic_vector(31 downto 0);
signal rd_data3_o : std_logic_vector(31 downto 0);
signal write_en : std_logic;
signal post_wr_data : std_logic_vector(31 downto 0);
signal w_pre_wr_data : std_logic_vector(31 downto 0);
signal wr_mem_state : state_type;
signal pre_wr_data : std_logic_vector(31 downto 0);
signal w_pre_wr_data0 : std_logic_vector(31 downto 0);
signal w_pre_wr_data1 : std_logic_vector(31 downto 0);
signal w_pre_wr_data2 : std_logic_vector(31 downto 0);
signal w_pre_wr_data3 : std_logic_vector(31 downto 0);
--
-- Memory Write Process
--
--
-- Extract current data bytes. These need to be swizzled
-- BRAM storage format :
-- data[31:0] = { byte[3], byte[2], byte[1], byte[0] (lowest addr) }
--
signal w_pre_wr_data_b3 : std_logic_vector(7 downto 0);
signal w_pre_wr_data_b2 : std_logic_vector(7 downto 0);
signal w_pre_wr_data_b1 : std_logic_vector(7 downto 0);
signal w_pre_wr_data_b0 : std_logic_vector(7 downto 0);
--
-- Extract new data bytes from payload
-- TLP Payload format :
-- data[31:0] = { byte[0] (lowest addr), byte[2], byte[1], byte[3] }
--
signal w_wr_data_b3 : std_logic_vector(7 downto 0);
signal w_wr_data_b2 : std_logic_vector(7 downto 0);
signal w_wr_data_b1 : std_logic_vector(7 downto 0);
signal w_wr_data_b0 : std_logic_vector(7 downto 0);
signal w_wr_data0_int : std_logic_vector(7 downto 0);
signal w_wr_data1_int : std_logic_vector(7 downto 0);
signal w_wr_data2_int : std_logic_vector(7 downto 0);
signal w_wr_data3_int : std_logic_vector(7 downto 0);
signal rd_data0_en : std_logic;
signal rd_data1_en : std_logic;
signal rd_data2_en : std_logic;
signal rd_data3_en : std_logic;
signal rd_data_raw_int0 : std_logic_vector(7 downto 0);
signal rd_data_raw_int1 : std_logic_vector(7 downto 0);
signal rd_data_raw_int2 : std_logic_vector(7 downto 0);
signal rd_data_raw_int3 : std_logic_vector(7 downto 0);
signal b_wr_en_0 : std_logic;
signal b_wr_en_1 : std_logic;
signal b_wr_en_2 : std_logic;
signal b_wr_en_3 : std_logic;
signal wr_addr_0 : std_logic;
signal wr_addr_1 : std_logic;
signal wr_addr_2 : std_logic;
signal wr_addr_3 : std_logic;
begin
--
-- Extract current data bytes. These need to be swizzled
-- BRAM storage format :
-- data[31:0] = { byte[3], byte[2], byte[1], byte[0] (lowest addr) }
--
w_pre_wr_data_b3 <= pre_wr_data(31 downto 24);
w_pre_wr_data_b2 <= pre_wr_data(23 downto 16);
w_pre_wr_data_b1 <= pre_wr_data(15 downto 08);
w_pre_wr_data_b0 <= pre_wr_data(07 downto 00);
--
-- Extract new data bytes from payload
-- TLP Payload format :
-- data[31:0] = { byte[0] (lowest addr), byte[2], byte[1], byte[3] }
--
w_wr_data_b3 <= wr_data_i(7 downto 0);
w_wr_data_b2 <= wr_data_i(15 downto 8);
w_wr_data_b1 <= wr_data_i(23 downto 16);
w_wr_data_b0 <= wr_data_i(31 downto 24);
w_wr_data3_int <= w_wr_data_b3 when (wr_be_i(3) = '1') else w_pre_wr_data_b3;
w_wr_data2_int <= w_wr_data_b2 when (wr_be_i(2) = '1') else w_pre_wr_data_b2;
w_wr_data1_int <= w_wr_data_b1 when (wr_be_i(1) = '1') else w_pre_wr_data_b1;
w_wr_data0_int <= w_wr_data_b0 when (wr_be_i(0) = '1') else w_pre_wr_data_b0;
process begin
wait until rising_edge(clk);
if (rst_n = '0') then
write_en <= '0';
pre_wr_data <= (OTHERS => '0') after TCQ;
post_wr_data <= (OTHERS => '0') after TCQ;
pre_wr_data <= (OTHERS => '0') after TCQ;
wr_mem_state <= PIO_MEM_ACCESS_WR_RST after TCQ;
else
case (wr_mem_state) is
when PIO_MEM_ACCESS_WR_RST =>
if (wr_en_i = '1') then -- read state
-- Pipelining happens in RAM's internal output reg
wr_mem_state <= PIO_MEM_ACCESS_WR_WAIT after TCQ;
else
write_en <= '0' after TCQ;
wr_mem_state <= PIO_MEM_ACCESS_WR_RST after TCQ;
end if;
when PIO_MEM_ACCESS_WR_WAIT =>
--
-- Pipeline B port data before processing. Block RAMs
-- have internal output register enabled
--
write_en <= '0' after TCQ;
wr_mem_state <= PIO_MEM_ACCESS_WR_READ after TCQ;
when PIO_MEM_ACCESS_WR_READ =>
--
-- Now save the selected BRAM B port data out
--
pre_wr_data <= w_pre_wr_data after TCQ;
write_en <= '0' after TCQ;
wr_mem_state <= PIO_MEM_ACCESS_WR_WRITE after TCQ;
when PIO_MEM_ACCESS_WR_WRITE =>
--
-- Merge new enabled data and write target BlockRAM location
--
post_wr_data <= w_wr_data3_int &
w_wr_data2_int &
w_wr_data1_int &
w_wr_data0_int after TCQ;
write_en <= '1' after TCQ;
wr_mem_state <= PIO_MEM_ACCESS_WR_RST after TCQ;
when others => null;
wr_mem_state <= PIO_MEM_ACCESS_WR_RST after TCQ;
end case;
end if;
end process;
--
-- Write controller busy
--
wr_busy_o <= '1' when ((wr_mem_state /= PIO_MEM_ACCESS_WR_RST) or wr_en_i = '1') else '0';
--
-- Select BlockRAM output based on higher 2 address bits
--
process (wr_addr_i, w_pre_wr_data0, w_pre_wr_data1, w_pre_wr_data2,
w_pre_wr_data3) begin
case (wr_addr_i(10 downto 9)) is
when "00" => w_pre_wr_data <= w_pre_wr_data0;
when "01" => w_pre_wr_data <= w_pre_wr_data1;
when "10" => w_pre_wr_data <= w_pre_wr_data2;
when "11" => w_pre_wr_data <= w_pre_wr_data3;
when others => null;
end case;
end process;
--
-- Memory Read Controller
--
rd_data0_en <= '1' when (rd_addr_i(10 downto 9) = "00") else '0';
rd_data1_en <= '1' when (rd_addr_i(10 downto 9) = "01") else '0';
rd_data2_en <= '1' when (rd_addr_i(10 downto 9) = "10") else '0';
rd_data3_en <= '1' when (rd_addr_i(10 downto 9) = "11") else '0';
process(rd_addr_i, rd_data0_o, rd_data1_o,
rd_data2_o, rd_data3_o) begin
case (rd_addr_i(10 downto 9)) is
when "00" => rd_data_raw_o <= rd_data0_o;
when "01" => rd_data_raw_o <= rd_data1_o;
when "10" => rd_data_raw_o <= rd_data2_o;
when "11" => rd_data_raw_o <= rd_data3_o;
when others => null;
end case;
end process;
-- Handle Read byte enables --
rd_data_raw_int0 <= rd_data_raw_o(7 downto 0) when (rd_be_i(0) = '1')
else (others => '0');
rd_data_raw_int1 <= rd_data_raw_o(15 downto 8) when (rd_be_i(1) = '1')
else (others => '0');
rd_data_raw_int2 <= rd_data_raw_o(23 downto 16) when (rd_be_i(2) = '1')
else (others => '0');
rd_data_raw_int3 <= rd_data_raw_o (31 downto 24) when (rd_be_i(3) = '1')
else (others => '0');
rd_data_o <= rd_data_raw_int0 &
rd_data_raw_int1 &
rd_data_raw_int2 &
rd_data_raw_int3 ;
b_wr_en_0 <= write_en when (wr_addr_i(10 downto 9) = "00") else '0';
b_wr_en_1 <= write_en when (wr_addr_i(10 downto 9) = "01") else '0';
b_wr_en_2 <= write_en when (wr_addr_i(10 downto 9) = "10") else '0';
b_wr_en_3 <= write_en when (wr_addr_i(10 downto 9) = "11") else '0';
wr_addr_0 <= '1' when (wr_addr_i(10 downto 9) = "00") else '0';
wr_addr_1 <= '1' when (wr_addr_i(10 downto 9) = "01") else '0';
wr_addr_2 <= '1' when (wr_addr_i(10 downto 9) = "10") else '0';
wr_addr_3 <= '1' when (wr_addr_i(10 downto 9) = "11") else '0';
PIO_EP_MEM_inst : PIO_EP_MEM
port map (
clk_i => clk,
a_rd_a_i_0 => rd_addr_i(8 downto 0), -- I [8:0]
a_rd_en_i_0 => rd_data0_en, -- I [1:0]
a_rd_d_o_0 => rd_data0_o, -- O [31:0]
b_wr_a_i_0 => wr_addr_i(8 downto 0), -- I [8:0]
b_wr_d_i_0 => post_wr_data, -- I [31:0]
b_wr_en_i_0 => b_wr_en_0, -- I
b_rd_d_o_0 => w_pre_wr_data0(31 downto 0), -- O [31:0]
b_rd_en_i_0 => wr_addr_0, -- I
a_rd_a_i_1 => rd_addr_i(8 downto 0), -- I [8:0]
a_rd_en_i_1 => rd_data1_en, -- I [1:0]
a_rd_d_o_1 => rd_data1_o, -- O [31:0]
b_wr_a_i_1 => wr_addr_i(8 downto 0), -- I [8:0]
b_wr_d_i_1 => post_wr_data, -- I [31:0]
b_wr_en_i_1 => b_wr_en_1, -- I
b_rd_d_o_1 => w_pre_wr_data1(31 downto 0), -- O [31:0]
b_rd_en_i_1 => wr_addr_1, -- I
a_rd_a_i_2 => rd_addr_i(8 downto 0), -- I [8:0]
a_rd_en_i_2 => rd_data2_en, -- I [1:0]
a_rd_d_o_2 => rd_data2_o, -- O [31:0]
b_wr_a_i_2 => wr_addr_i(8 downto 0), -- I [8:0]
b_wr_d_i_2 => post_wr_data, -- I [31:0]
b_wr_en_i_2 => b_wr_en_2, -- I
b_rd_d_o_2 => w_pre_wr_data2(31 downto 0), -- I [31:0]
b_rd_en_i_2 => wr_addr_2, -- I
a_rd_a_i_3 => rd_addr_i(8 downto 0), -- I [8:0]
a_rd_en_i_3 => rd_data3_en, -- I [1:0]
a_rd_d_o_3 => rd_data3_o, -- O [31:0]
b_wr_a_i_3 => wr_addr_i(8 downto 0), -- I [8:0]
b_wr_d_i_3 => post_wr_data, -- I [31:0]
b_wr_en_i_3 => b_wr_en_3, -- I
b_rd_d_o_3 => w_pre_wr_data3(31 downto 0), -- I [31:0]
b_rd_en_i_3 => wr_addr_3 -- I
);
end rtl;
| gpl-3.0 |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/sim/sp6_data_gen.vhd | 20 | 37259 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: sp6_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Spartan 6 family.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity sp6_data_gen is
generic (
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic; --
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
user_burst_cnt : in std_logic_vector(6 downto 0); -- generated burst length for control the burst data
fifo_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_o : out std_logic_vector(DWIDTH - 1 downto 0) -- generated data pattern
);
end entity sp6_data_gen;
architecture trans of sp6_data_gen is
COMPONENT data_prbs_gen IS
GENERIC (
EYE_TEST : STRING := "FALSE";
PRBS_WIDTH : INTEGER := 32;
SEED_WIDTH : INTEGER := 32
);
PORT (
clk_i : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
prbs_seed_init : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
--
signal prbs_data : std_logic_vector(31 downto 0);
signal adata : std_logic_vector(31 downto 0);
signal hdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata : std_logic_vector(DWIDTH - 1 downto 0);
signal w1data : std_logic_vector(DWIDTH - 1 downto 0);
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal i : integer;
signal j : integer;
signal user_bl : std_logic_vector(BL_WIDTH - 1 downto 0);
signal BLANK : std_logic_vector(7 downto 0);
signal SHIFT_0 : std_logic_vector(7 downto 0);
signal SHIFT_1 : std_logic_vector(7 downto 0);
signal SHIFT_2 : std_logic_vector(7 downto 0);
signal SHIFT_3 : std_logic_vector(7 downto 0);
signal SHIFT_4 : std_logic_vector(7 downto 0);
signal SHIFT_5 : std_logic_vector(7 downto 0);
signal SHIFT_6 : std_logic_vector(7 downto 0);
signal SHIFT_7 : std_logic_vector(7 downto 0);
signal SHIFTB_0 : std_logic_vector(31 downto 0);
signal SHIFTB_1 : std_logic_vector(31 downto 0);
signal SHIFTB_2 : std_logic_vector(31 downto 0);
signal SHIFTB_3 : std_logic_vector(31 downto 0);
signal SHIFTB_4 : std_logic_vector(31 downto 0);
signal SHIFTB_5 : std_logic_vector(31 downto 0);
signal SHIFTB_6 : std_logic_vector(31 downto 0);
signal SHIFTB_7 : std_logic_vector(31 downto 0);
signal TSTB : std_logic_vector(3 downto 0);
--*********************************************************************************************
-- 4'b0000: data = 32'b0; //bram
-- 4'b0001: data = 32'b0; // fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
-- WALKING ONES:
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
signal tmpdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata_rising : std_logic;
signal shift_en : std_logic;
signal data_clk_en : std_logic;
SIGNAL ZEROS : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0) ;--:= (others => '0');
begin
ZEROS <= (others => '0');
data_o <= data;
xhdl0 : if (DWIDTH = 32) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0001" =>
data <= fixed_data_i;
when "0010" =>
data <= adata;
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
data <= prbs_data;
WHEN OTHERS =>
data <= (others => '0');
END CASE;
END PROCESS;
end generate;
xhdl1 : if (DWIDTH = 64) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata)(31 downto 0);
data <= (adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data);
when others =>
data <= (others => '0');
end case;
end process;
end generate;
xhdl2 : if (DWIDTH = 128) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata & adata & adata)(31 downto 0);
data <= (adata & adata & adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data & prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data & prbs_data & prbs_data);
when others =>
data <= (others => '0');--"00000000000000000000000000000000";
end case;
end process;
end generate;
xhdl3 : if ((DWIDTH = 64) or (DWIDTH = 128)) generate
process (data_mode_i)
begin
if (data_mode_i = "0101" or data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0110") then
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
else
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
end if;
end process;
end generate;
process (data_mode_i)
begin
if (data_mode_i = "0101") then
SHIFTB_0 <= "00000000000000100000000000000001";
SHIFTB_1 <= "00000000000010000000000000000100";
SHIFTB_2 <= "00000000001000000000000000010000";
SHIFTB_3 <= "00000000100000000000000001000000";
SHIFTB_4 <= "00000010000000000000000100000000";
SHIFTB_5 <= "00001000000000000000010000000000";
SHIFTB_6 <= "00100000000000000001000000000000";
SHIFTB_7 <= "10000000000000000100000000000000";
elsif (data_mode_i = "0100") then
SHIFTB_0 <= "00000000000000000000000000000001";
SHIFTB_1 <= "00000000000000000000000000000010";
SHIFTB_2 <= "00000000000000000000000000000100";
SHIFTB_3 <= "00000000000000000000000000001000";
SHIFTB_4 <= "00000000000000000000000000010000";
SHIFTB_5 <= "00000000000000000000000000100000";
SHIFTB_6 <= "00000000000000000000000001000000";
SHIFTB_7 <= "00000000000000000000000010000000";
else
SHIFTB_0 <= "11111111111111011111111111111110";
SHIFTB_1 <= "11111111111101111111111111111011";
SHIFTB_2 <= "11111111110111111111111111101111";
SHIFTB_3 <= "11111111011111111111111110111111";
SHIFTB_4 <= "11111101111111111111111011111111";
SHIFTB_5 <= "11110111111111111111101111111111";
SHIFTB_6 <= "11011111111111111110111111111111";
SHIFTB_7 <= "01111111111111111011111111111111";
end if;
end process;
xhdl4 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
ndata_rising <= '1';
shift_en <= '0';
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 2) is
when "000" =>
w1data <= SHIFTB_0;
when "001" =>
w1data <= SHIFTB_1;
when "010" =>
w1data <= SHIFTB_2;
when "011" =>
w1data <= SHIFTB_3;
when "100" =>
w1data <= SHIFTB_4;
when "101" =>
w1data <= SHIFTB_5;
when "110" =>
w1data <= SHIFTB_6;
when "111" =>
w1data <= SHIFTB_7;
when others =>
w1data <= SHIFTB_0;
end case;
ndata_rising <= '0'; --(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
elsif (data_mode_i = "0100") then
w1data <= ("0000000000000000" & w1data(14 downto 0) & w1data(15));
else
w1data <= (w1data(29 downto 16) & w1data(31 downto 30) & w1data(13 downto 0) & w1data(15 downto 14)); --(DQ_PINS == 16
end if;
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
case addr_i(2) is
when '0' =>
w1data <= SHIFTB_0;
when '1' =>
w1data <= SHIFTB_1;
when others =>
w1data <= SHIFTB_0;
end case;
else
-- (cmd_startC)
-- Shifting
-- need neigbour pattern ********************
w1data <= (w1data(27 downto 24) & w1data(31 downto 28) & w1data(19 downto 16) & w1data(23 downto 20) & w1data(11 downto 8) & w1data(15 downto 12) & w1data(3 downto 0) & w1data(7 downto 4)); --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
-- need neigbour pattern ********************
if (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001"; -- (NUM_DQ_PINS_4
end if;
end if;
end if;
end if;
end process;
-- <outdent> -- DWIDTH == 32
end generate;
xhdl5 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 3) is
-- 7:0
when "00" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
when "01" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
when "10" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
when "11" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= (ZEROS(DWIDTH-1 downto 8) & BLANK);
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(45 downto 32) & w1data(47 downto 46));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(13 downto 0) & w1data(15 downto 14));
else
-- w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) & w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) & w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) & w1data(1 * DWIDTH / 4 - 5 to 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4))(31 downto 0);
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) &
w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) &
w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) &
w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) &
w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) &
w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) &
w1data(1 * DWIDTH / 4 - 5 downto 1 * DWIDTH / 4 - 16) &
w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
case addr_i(3) is
when '0' =>
w1data <= (BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
when '1' =>
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4);
--15:8
when others =>
w1data <= (others => '0');--"00000000000000000000000000000000";
end case;
else
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
end if;
-- Shifting
elsif (data_mode_i = "0100") then
w1data(63 downto 56) <= "00000000";
w1data(55 downto 48) <= (w1data(51 downto 48) & w1data(55 downto 52));
w1data(47 downto 40) <= "00000000";
w1data(39 downto 32) <= (w1data(35 downto 32) & w1data(39 downto 36));
w1data(31 downto 24) <= "00000000";
w1data(23 downto 16) <= (w1data(19 downto 16) & w1data(23 downto 20));
w1data(15 downto 8) <= "00000000";
w1data(7 downto 0) <= (w1data(3 downto 0) & w1data(7 downto 4));
else
w1data <= w1data; --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
if (data_mode_i = "0100") then
w1data <= "0000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "1000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end if;
end process;
end generate;
xhdl6 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4) is
-- 32
when '0' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
-- 32
when '1' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= ZEROS(DWIDTH-1 downto 8) & BLANK;
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(127 downto 112) <= "0000000000000000";
w1data(111 downto 96) <= (w1data(107 downto 96) & w1data(111 downto 108));
w1data(95 downto 80) <= "0000000000000000";
w1data(79 downto 64) <= (w1data(75 downto 64) & w1data(79 downto 76));
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(43 downto 32) & w1data(47 downto 44));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(11 downto 0) & w1data(15 downto 12));
else
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 9 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 8) & w1data(4 * DWIDTH / 4 - 25 downto 4 * DWIDTH / 4 - 32) & w1data(4 * DWIDTH / 4 - 17 downto 4 * DWIDTH / 4 - 24) & w1data(3 * DWIDTH / 4 - 9 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 8) & w1data(3 * DWIDTH / 4 - 25 downto 3 * DWIDTH / 4 - 32) & w1data(3 * DWIDTH / 4 - 17 downto 3 * DWIDTH / 4 - 24) & w1data(2 * DWIDTH / 4 - 9 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 8) & w1data(2 * DWIDTH / 4 - 25 downto 2 * DWIDTH / 4 - 32) & w1data(2 * DWIDTH / 4 - 17 downto 2 * DWIDTH / 4 - 24) & w1data(1 * DWIDTH / 4 - 9 downto 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 8) & w1data(1 * DWIDTH / 4 - 25 downto 1 * DWIDTH / 4 - 32) & w1data(1 * DWIDTH / 4 - 17 downto 1 * DWIDTH / 4 - 24));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4 & BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
else
w1data <= (SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0 & SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0); -- (cmd_startC)
end if;
else
-- Shifting
--{w1data[96:64], w1data[127:97],w1data[31:0], w1data[63:32]};
w1data <= w1data; -- else
end if;
--(NUM_DQ_PINS == 8)
elsif (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001000010000000010000000010000000010000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001100001000010000110000100001000011000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end process;
end generate;
-- HAMMER_PATTERN: Alternating 1s and 0s on DQ pins
-- => the rsing data pattern will be 32'b11111111_11111111_11111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
xhdl7 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
-- elsif ((fifo_rdy_i = '1' and user_burst_cnt(5 downto 0) /= "000000") or cmd_startC = '1') then
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111"; -- NUM_DQ_PINS == 4
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl8 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "0000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "0000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "0000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl9 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
process (w1data, hdata)
begin
for i in 0 to DWIDTH - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
-- HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine
-- the position of the pin driving oppsite polarity
-- addr_i[6:2] = 5'h0f ; 32 bit data port
-- => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
-- ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
-- => the 1st data pattern : 32'h12345678
-- => the 2nd data pattern : 32'h12345679
-- => the 3rd data pattern : 32'h1234567a
-- => the 4th data pattern : 32'h1234567b
--data_rdy_i
xhdl10 : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
--data_o logic
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
adata <= addr_i;
elsif ((fifo_rdy_i and data_rdy_i) = '1' and user_burst_cnt > "0000001") then
if (DWIDTH = 128) then
adata <= adata + "00000000000000000000000000010000";
elsif (DWIDTH = 64) then
adata <= adata + "00000000000000000000000000001000"; -- DWIDTH == 32
else
adata <= adata + "00000000000000000000000000000100";
end if;
end if;
end if;
end process;
end generate;
-- PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
--
xhdl11 : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
-- data_clk_en <= fifo_rdy_i and data_rdy_i and to_stdlogicvector(user_burst_cnt > "0000001", 7)(0);
data_clk_en <= (fifo_rdy_i AND data_rdy_i) when (user_burst_cnt > "0000001") ELSE '0';
data_prbs_gen_inst : data_prbs_gen
generic map (
prbs_width => 32,
seed_width => 32
)
port map (
clk_i => clk_i,
clk_en => data_clk_en,
rst_i => rst_i,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => addr_i(31 downto 0),
prbs_o => prbs_data
);
end generate;
end architecture trans;
| gpl-3.0 |
adelapie/noekeon_loop | tb_pi_2.vhd | 5 | 2708 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_pi_2 IS
END tb_pi_2;
ARCHITECTURE behavior OF tb_pi_2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pi_2
PORT(
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pi_2 PORT MAP (
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
a_1_in <= X"43575679";
a_2_in <= X"465647e0";
a_3_in <= X"c002aeef";
wait for clk_period;
assert a_1_out = X"a1abab3c"
report "PI1 ERROR (a_0)" severity FAILURE;
assert a_2_out = X"0232b23f"
report "PI1 ERROR (a_1)" severity FAILURE;
assert a_3_out = X"f000abbb"
report "PI1 ERROR (a_2)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/example_design/rtl/traffic_gen/data_prbs_gen.vhd | 20 | 4942 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: data_prbs_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:39 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module is used LFSR to generate random data for memory
-- data write or memory data read comparison.The first data is
-- seeded by the input prbs_seed_i which is connected to memory address.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY data_prbs_gen IS
GENERIC (
EYE_TEST : STRING := "FALSE";
PRBS_WIDTH : INTEGER := 32;
SEED_WIDTH : INTEGER := 32
-- TAPS : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0) := "10000000001000000000000001100010"
);
PORT (
clk_i : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
prbs_seed_init : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
);
END data_prbs_gen;
ARCHITECTURE trans OF data_prbs_gen IS
SIGNAL prbs : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
SIGNAL i : INTEGER;
BEGIN
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (((prbs_seed_init = '1') AND (EYE_TEST = "FALSE")) OR (rst_i = '1')) THEN
lfsr_q <= prbs_seed_i + prbs_fseed_i(31 DOWNTO 0) + "01010101010101010101010101010101";
ELSIF (clk_en = '1') THEN
lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8);
lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7);
lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6);
lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3);
lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2);
lfsr_q(2) <= lfsr_q(1);
lfsr_q(1) <= lfsr_q(32);
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(PRBS_WIDTH DOWNTO 1))
BEGIN
prbs <= lfsr_q(PRBS_WIDTH DOWNTO 1);
END PROCESS;
prbs_o <= prbs;
END trans;
| gpl-3.0 |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pci_exp_usrapp_pl.vhd | 1 | 4756 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pci_exp_usrapp_pl.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pci_exp_usrapp_pl is
generic (
LINK_CAP_MAX_LINK_SPEED : integer := 1);
port (
pl_initial_link_width : in std_logic_vector(2 downto 0);
pl_lane_reversal_mode : in std_logic_vector(1 downto 0);
pl_link_gen2_capable : in std_logic;
pl_link_partner_gen2_supported : in std_logic;
pl_link_upcfg_capable : in std_logic;
pl_ltssm_state : in std_logic_vector(5 downto 0);
pl_received_hot_rst : in std_logic;
pl_sel_link_rate : in std_logic;
pl_sel_link_width : in std_logic_vector(1 downto 0);
pl_directed_link_auton : out std_logic;
pl_directed_link_change : out std_logic_vector(1 downto 0);
pl_directed_link_speed : out std_logic;
pl_directed_link_width : out std_logic_vector(1 downto 0);
pl_upstream_prefer_deemph : out std_logic;
speed_change_done_n : out std_logic;
trn_lnk_up_n : in std_logic;
trn_clk : in std_logic;
trn_reset_n : in std_logic
);
end pci_exp_usrapp_pl;
architecture rtl of pci_exp_usrapp_pl is
constant Tcq : integer := 1;
begin
process
begin
pl_directed_link_auton <= '0';
pl_directed_link_change <= "00";
pl_directed_link_speed <= '0';
pl_directed_link_width <= "00";
pl_upstream_prefer_deemph <= '0';
speed_change_done_n <= '1';
if (LINK_CAP_MAX_LINK_SPEED = 2) then
wait until trn_lnk_up_n = '0';
pl_directed_link_speed <= '1';
pl_directed_link_change <= "10";
wait until pl_ltssm_state = "100000";
pl_directed_link_speed <= '0';
pl_directed_link_change <= "00";
wait until pl_sel_link_rate = '1';
speed_change_done_n <= '0';
end if;
wait;
end process;
end rtl;
-- pci_exp_usrapp_pl
| gpl-3.0 |
Pinwino/dbg_ohwr | debugger_gw/debugger_pkg.vhd | 1 | 7628 | -------------------------------------------------------------------------------
-- Title : Wishbone Debugger package
-- Project : FMC DEL 1ns 4cha-stand-alone application (fmc-delay-1ns-4cha-sa)
-------------------------------------------------------------------------------
-- File : debugger_pkg.vhd
-- Author : Jose Jimenez <[email protected]>
-- Company : University of Granada
-- Created : 2014-06-08
-- Last update: 2014-07-31
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Wihsbone master with slave configuration interface for gateware
-- debuggin porpuses. Also provides a framework for stand alone
-- operation.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-06-08 1.0 jjimenez Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
----use work.gn4124_core_pkg.all;
--use work.gencores_pkg.all;
--use work.wrcore_pkg.all;
----use work.wr_fabric_pkg.all;
--use work.wishbone_pkg.all;
----use work.fine_delay_pkg.all;
----use work.etherbone_pkg.all;
----use work.wr_xilinx_pkg.all;
--use work.genram_pkg.all;
--use work.wb_irq_pkg.all;
----use work.gencores_pkg.all;
use work.wishbone_pkg.all;
--use work.genram_pkg.all;
--use work.wb_irq_pkg.all;
--use work.debugger_pkg.all;
--
--use work.synthesis_descriptor.all;
package debugger_pkg is
------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant c_dbg_uart_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"0deafbee", -- she didn't listen & cames & goes
version => x"00000001",
date => x"20120305",
name => "WB-UART-Debugger ")));
constant c_dbg_irq_ctrl_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"e1fb1ade", -- balanced, perfect grip, absolute control
version => x"00000001",
date => x"20120308",
name => "IRQ_CTRL-Debugger ")));
constant c_xwb_dbg_tics_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000000",
product => (
vendor_id => x"000000000000CE42", -- GSIx
device_id => x"fade1eaf", -- Time is always ticking!
version => x"00000001",
date => x"20111004",
name => "WB-Tics-Debugger ")));
constant c_dbg_irq_timer_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"deadface", -- eventully "the dead line" is going to arrive
version => x"00000001",
date => x"20120308",
name => "IRQ_TIMER-Debugger ")));
constant c_xwb_dbg_slave_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000003ffff",
product => (
vendor_id => x"a1eBEEFc0ffeeBED", -- Jose Jimenez Motel. Open 24/7. Next exit.
device_id => x"c0a110de", -- obvious (sadly)
version => x"00000001",
date => x"20140704",
name => "Debugger-Slave ")));
------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
function f_xwb_dbg_dpram(g_size : natural) return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := x"0001"; -- RAM device
result.abi_ver_major := x"01";
result.abi_ver_minor := x"00";
result.wbd_width := x"7"; -- 32/16/8-bit supported
result.wbd_endian := c_sdb_endian_big;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := std_logic_vector(to_unsigned(g_size*4-1, 64));
result.sdb_component.product.vendor_id := x"000000000000CE42"; -- CERN
result.sdb_component.product.device_id := x"deafbeef"; -- she didn't listen & is as essential as protein
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120305";
result.sdb_component.product.name := "BlockRAM-Debugger ";
return result;
end f_xwb_dbg_dpram;
------------------------------------------------------------------------------
-- Components declaration
-------------------------------------------------------------------------------
component wb_debugger is
generic (
g_dbg_dpram_size : integer := 40960/4;
g_dbg_init_file : string;
g_reset_vector : t_wishbone_address := x"00000000";
g_msi_queues : natural := 1;
g_profile : string := "medium_icache_debug";
g_internal_time_ref : boolean := true;
g_timers : integer := 1;
g_slave_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_slave_granularity : t_wishbone_address_granularity := BYTE
);
port (
clk_sys : in std_logic;
reset_n : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
wrpc_uart_rxd_i : inout std_logic;
wrpc_uart_txd_o : inout std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
dbg_indicator : out std_logic;
dbg_control_select : in std_logic
);
end component;
end debugger_pkg;
package body debugger_pkg is
-- Notihg to include right now!!!
end debugger_pkg;
| gpl-3.0 |
timofonic/PHDL | misc/projects/Old.v1.0-projects/FMC_DAC/fmc_dac_fpga/top.vhd | 1 | 2858 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is Port (
db1_p : out STD_LOGIC_VECTOR (13 downto 0);
db1_n : out STD_LOGIC_VECTOR (13 downto 0);
db0_p : out STD_LOGIC_VECTOR (13 downto 0);
db0_n : out STD_LOGIC_VECTOR (13 downto 0);
sync_out_p : out STD_LOGIC;
sync_out_n : out STD_LOGIC;
sync_in_p : in STD_LOGIC;
sync_in_n : in STD_LOGIC;
dco_p : out STD_LOGIC;
dco_n : out STD_LOGIC;
dci_p : in STD_LOGIC;
dci_n : in STD_LOGIC;
spi_sdi : in STD_LOGIC;
spi_sdo : out STD_LOGIC;
spi_cs : out STD_LOGIC;
spi_sclk : out STD_LOGIC;
reset : out STD_LOGIC);
end top;
architecture Behavioral of top is
signal dci, dco, sync_in, sync_out, spi_sdi_reg : std_logic;
signal sync_vec : std_logic_vector( 1 downto 0);
signal db0, db1 : std_logic_vector(13 downto 0);
signal count : std_logic_vector(63 downto 0);
begin
IBUFGDS_dci: IBUFGDS port map(O=>dci, I=>dci_p, IB=>dci_n);
IBUFDS_sync_in : IBUFDS port map(O=>sync_in, I=>sync_in_p, IB=>sync_in_n);
IDDR_sync_in : IDDR generic map(DDR_CLK_EDGE=>"SAME_EDGE") port map(Q1=>sync_vec(0), Q2=>sync_vec(1), C=>dci, CE=>'1', D=>sync_in, R=>'0', S=>'0');
ODDR_sync_out : ODDR generic map(DDR_CLK_EDGE=>"SAME_EDGE") port map(Q=>sync_out, C=>dci, CE=>'1', D1=>sync_vec(0), D2=>sync_vec(1), R=>'0', S=>'0');
OBUFDS_sync_out : OBUFDS port map(O=>sync_out_p, OB=>sync_out_n, I=>sync_out);
ODDR_dco : ODDR generic map(DDR_CLK_EDGE=>"SAME_EDGE") port map(Q=>dco, C=>dci, CE=>'1', D1=>'0', D2=>'1', R=>'0', S=>'0');
OBUFDS_dco : OBUFDS port map(O=>dco_p, OB=>dco_n, I=>dco);
dbx_gen: for i in db0_p'range generate begin
ODDR_db0 : ODDR generic map(DDR_CLK_EDGE=>"SAME_EDGE") port map(Q=>db0(i), C=>dci, CE=>'1', D1=>count(i+0), D2=>count(i+14), R=>'0', S=>'0');
ODDR_db1 : ODDR generic map(DDR_CLK_EDGE=>"SAME_EDGE") port map(Q=>db1(i), C=>dci, CE=>'1', D1=>count(i+28), D2=>count(i+42), R=>'0', S=>'0');
OBUFDS_db0 : OBUFDS port map(O=>db0_p(i), OB=>db0_n(i), I=>db0(i));
OBUFDS_db1 : OBUFDS port map(O=>db1_p(i), OB=>db1_n(i), I=>db1(i));
end generate;
count_proc:process
begin
wait until rising_edge(dci);
count <= std_logic_vector(unsigned(count)+1);
end process;
spi_regs_proc:process
begin
wait until rising_edge(dci);
spi_sdi_reg <= spi_sdi;
spi_sdo <= spi_sdi_reg;
spi_cs <= count(56);
reset <= count(57);
spi_sclk <= count(58);
end process;
end Behavioral;
| gpl-3.0 |
adelapie/noekeon_loop | tb_rc_shr.vhd | 1 | 2249 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:34:02 02/24/2015
-- Design Name:
-- Module Name: C:/Users/vmr/Desktop/noekeon_loop/noekeon_loop/tb_rc_shr.vhd
-- Project Name: noekeon_loop
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: rc_shr
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_rc_shr IS
END tb_rc_shr;
ARCHITECTURE behavior OF tb_rc_shr IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rc_shr
PORT(
clk : IN std_logic;
rst : IN std_logic;
rc_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal rc_out : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rc_shr PORT MAP (
clk => clk,
rst => rst,
rc_out => rc_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period;
rst <= '1';
wait for clk_period;
rst <= '0';
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/example_design/rtl/memc1_wrapper.vhd | 2 | 46755 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc1_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created :
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc1_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
-- memory interface signals
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb1_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
-- mcb1_dram_odt : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_dram_udm : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc1_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000001";
constant C_PORT_CONFIG : string := "B32_B32_R32_R32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
constant C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_9_ddr3_s6, Coregen 13.3";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb1_ddr3_s6,mig_v3_9,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=2, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR3_SDRAM, CLK_PERIOD=2500, MEMORY_PART=mt41j128m16xx-15e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=DIV6, RTT_NOM=DIV4, AUTO_SR=ENABLED, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Differential}";
begin
memc1_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb1_dram_a,
mcbx_dram_ba => mcb1_dram_ba,
mcbx_dram_ras_n => mcb1_dram_ras_n,
mcbx_dram_cas_n => mcb1_dram_cas_n,
mcbx_dram_we_n => mcb1_dram_we_n,
mcbx_dram_cke => mcb1_dram_cke,
mcbx_dram_clk => mcb1_dram_ck,
mcbx_dram_clk_n => mcb1_dram_ck_n,
mcbx_dram_dq => mcb1_dram_dq,
mcbx_dram_odt => mcb1_dram_odt,
mcbx_dram_ldm => mcb1_dram_dm,
mcbx_dram_udm => mcb1_dram_udm,
mcbx_dram_dqs => mcb1_dram_dqs,
mcbx_dram_dqs_n => mcb1_dram_dqs_n,
mcbx_dram_udqs => mcb1_dram_udqs,
mcbx_dram_udqs_n => mcb1_dram_udqs_n,
mcbx_dram_ddr3_rst => mcb1_dram_reset_n,
calib_recal => '0',
rzq => mcb1_rzq,
zio => mcb1_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '0',
p2_cmd_clk => '0',
p2_cmd_en => '0',
p2_cmd_instr => (others => '0'),
p2_cmd_bl => (others => '0'),
p2_cmd_byte_addr => (others => '0'),
p2_cmd_empty => open,
p2_cmd_full => open,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
| gpl-3.0 |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/example_design/PIO_EP.vhd | 1 | 13056 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : PIO_EP.vhd
-- Description: Endpoint Programmed I/O module.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity PIO_EP is
port (
-- Common
clk : in std_logic;
rst_n : in std_logic;
-- LocalLink Tx
trn_td : out std_logic_vector(31 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tdst_dsc_n : in std_logic;
trn_tdst_rdy_n : in std_logic;
-- LocalLink Rx
trn_rd : in std_logic_vector(31 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector(6 downto 0);
trn_rdst_rdy_n : out std_logic;
-- Turn-off signaling
req_compl_o : out std_logic;
compl_done_o : out std_logic;
-- Configuration
cfg_completer_id : in std_logic_vector(15 downto 0);
cfg_bus_mstr_enable : in std_logic
);
end PIO_EP;
architecture rtl of PIO_EP is
-- Local signals
signal rd_addr : std_logic_vector(10 downto 0);
signal rd_be : std_logic_vector(3 downto 0);
signal rd_data : std_logic_vector(31 downto 0);
signal wr_addr : std_logic_vector(10 downto 0);
signal wr_be : std_logic_vector(7 downto 0);
signal wr_data : std_logic_vector(31 downto 0);
signal wr_en : std_logic;
signal wr_busy : std_logic;
signal req_compl : std_logic;
signal req_compl_with_data : std_logic;
signal compl_done : std_logic;
signal req_tc : std_logic_vector(2 downto 0);
signal req_td : std_logic;
signal req_ep : std_logic;
signal req_attr : std_logic_vector(1 downto 0);
signal req_len : std_logic_vector(9 downto 0);
signal req_rid : std_logic_vector(15 downto 0);
signal req_tag : std_logic_vector(7 downto 0);
signal req_be : std_logic_vector(7 downto 0);
signal req_addr : std_logic_vector(12 downto 0);
component PIO_32_RX_ENGINE is
port (
clk : in std_logic;
rst_n : in std_logic;
trn_rd : in std_logic_vector(31 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector(6 downto 0);
trn_rdst_rdy_n : out std_logic;
req_compl_o : out std_logic;
req_compl_with_data_o : out std_logic;
compl_done_i : in std_logic;
req_tc_o : out std_logic_vector(2 downto 0); -- Memory Read TC
req_td_o : out std_logic; -- Memory Read TD
req_ep_o : out std_logic; -- Memory Read EP
req_attr_o : out std_logic_vector(1 downto 0); -- Memory Read Attribute
req_len_o : out std_logic_vector(9 downto 0); -- Memory Read Length (1DW)
req_rid_o : out std_logic_vector(15 downto 0); -- Memory Read Requestor ID
req_tag_o : out std_logic_vector(7 downto 0); -- Memory Read Tag
req_be_o : out std_logic_vector(7 downto 0); -- Memory Read Byte Enables
req_addr_o : out std_logic_vector(12 downto 0); -- Memory Read Address
wr_addr_o : out std_logic_vector(10 downto 0); -- Memory Write Address
wr_be_o : out std_logic_vector(7 downto 0); -- Memory Write Byte Enable
wr_data_o : out std_logic_vector(31 downto 0); -- Memory Write Data
wr_en_o : out std_logic; -- Memory Write Enable
wr_busy_i : in std_logic -- Memory Write Busy
);
end component;
component PIO_32_TX_ENGINE is
port (
clk : in std_logic;
rst_n : in std_logic;
trn_td : out std_logic_vector(31 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_tdst_rdy_n : in std_logic;
trn_tdst_dsc_n : in std_logic;
req_compl_i : in std_logic;
req_compl_with_data_i : in std_logic;
compl_done_o : out std_logic;
req_tc_i : in std_logic_vector(2 downto 0);
req_td_i : in std_logic;
req_ep_i : in std_logic;
req_attr_i : in std_logic_vector(1 downto 0);
req_len_i : in std_logic_vector(9 downto 0);
req_rid_i : in std_logic_vector(15 downto 0);
req_tag_i : in std_logic_vector(7 downto 0);
req_be_i : in std_logic_vector(7 downto 0);
req_addr_i : in std_logic_vector(12 downto 0);
rd_addr_o : out std_logic_vector(10 downto 0);
rd_be_o : out std_logic_vector(3 downto 0);
rd_data_i : in std_logic_vector(31 downto 0);
completer_id_i : in std_logic_vector(15 downto 0);
cfg_bus_mstr_enable_i : in std_logic
);
end component;
component PIO_EP_MEM_ACCESS is
port (
clk : in std_logic;
rst_n : in std_logic;
-- Read Port
rd_addr_i : in std_logic_vector(10 downto 0);
rd_be_i : in std_logic_vector(3 downto 0);
rd_data_o : out std_logic_vector(31 downto 0);
-- Write Port
wr_addr_i : in std_logic_vector(10 downto 0);
wr_be_i : in std_logic_vector(7 downto 0);
wr_data_i : in std_logic_vector(31 downto 0);
wr_en_i : in std_logic;
wr_busy_o : out std_logic
);
end component;
signal trn_td_int : std_logic_vector(31 downto 0);
begin
trn_td <= trn_td_int;
req_compl_o <= req_compl;
compl_done_o <= compl_done;
--
-- ENDPOINT MEMORY : 8KB memory aperture implemented in FPGA BlockRAM(*)
--
EP_MEM : PIO_EP_MEM_ACCESS
port map (
clk => clk, -- I
rst_n => rst_n, -- I
-- Read Port
rd_addr_i => rd_addr, -- I [10:0]
rd_be_i => rd_be, -- I [3:0]
rd_data_o => rd_data, -- O [31:0]
-- Write Port
wr_addr_i => wr_addr, -- I [10:0]
wr_be_i => wr_be, -- I [7:0]
wr_data_i => wr_data, -- I [31:0]
wr_en_i => wr_en, -- I
wr_busy_o => wr_busy -- O
);
--
-- Local-Link Receive Controller
--
EP_RX : PIO_32_RX_ENGINE
port map (
clk => clk, -- I
rst_n => rst_n, -- I
-- LocalLink Rx
trn_rd => trn_rd, -- I [31:0]
trn_rsof_n => trn_rsof_n, -- I
trn_reof_n => trn_reof_n, -- I
trn_rsrc_rdy_n => trn_rsrc_rdy_n, -- I
trn_rsrc_dsc_n => trn_rsrc_dsc_n, -- I
trn_rbar_hit_n => trn_rbar_hit_n, -- I [6:0]
trn_rdst_rdy_n => trn_rdst_rdy_n, -- O
-- Handshake with Tx engine
req_compl_o => req_compl, -- O
req_compl_with_data_o => req_compl_with_data, -- O
compl_done_i => compl_done, -- I
req_tc_o => req_tc, -- O [2:0]
req_td_o => req_td, -- O
req_ep_o => req_ep, -- O
req_attr_o => req_attr, -- O [1:0]
req_len_o => req_len, -- O [9:0]
req_rid_o => req_rid, -- O [15:0]
req_tag_o => req_tag, -- O [7:0]
req_be_o => req_be, -- O [7:0]
req_addr_o => req_addr, -- O [12:0]
-- Memory Write Port
wr_addr_o => wr_addr, -- O [10:0]
wr_be_o => wr_be, -- O [7:0]
wr_data_o => wr_data, -- O [31:0]
wr_en_o => wr_en, -- O
wr_busy_i => wr_busy -- I
);
--
-- Local-Link Transmit Controller
--
EP_TX : PIO_32_TX_ENGINE
port map (
clk => clk, -- I
rst_n => rst_n, -- I
-- LocalLink Tx
trn_td => trn_td_int, -- O [31:0]
trn_tsof_n => trn_tsof_n, -- O
trn_teof_n => trn_teof_n, -- O
trn_tsrc_dsc_n => trn_tsrc_dsc_n, -- O
trn_tsrc_rdy_n => trn_tsrc_rdy_n, -- O
trn_tdst_dsc_n => trn_tdst_dsc_n, -- I
trn_tdst_rdy_n => trn_tdst_rdy_n, -- I
-- Handshake with Rx engine
req_compl_i => req_compl, -- I
req_compl_with_data_i => req_compl_with_data, -- I
compl_done_o => compl_done, -- 0
req_tc_i => req_tc, -- I [2:0]
req_td_i => req_td, -- I
req_ep_i => req_ep, -- I
req_attr_i => req_attr, -- I [1:0]
req_len_i => req_len, -- I [9:0]
req_rid_i => req_rid, -- I [15:0]
req_tag_i => req_tag, -- I [7:0]
req_be_i => req_be, -- I [7:0]
req_addr_i => req_addr, -- I [12:0]
-- Read Port
rd_addr_o => rd_addr, -- O [10:0]
rd_be_o => rd_be, -- O [3:0]
rd_data_i => rd_data, -- I [31:0]
completer_id_i => cfg_completer_id, -- I [15:0]
cfg_bus_mstr_enable_i => cfg_bus_mstr_enable -- I
);
end rtl;
| gpl-3.0 |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/sim/write_data_path.vhd | 20 | 9135 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
| gpl-3.0 |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/top.vhd | 1 | 9085 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
generic(
C1_P0_MASK_SIZE : integer := 4;
C1_P0_DATA_PORT_SIZE : integer := 32;
C1_P1_MASK_SIZE : integer := 4;
C1_P1_DATA_PORT_SIZE : integer := 32;
C1_MEMCLK_PERIOD : integer := 2500; -- Memory data transfer clock period.
C1_RST_ACT_LOW : integer := 0; -- # = 1 for active low reset,# = 0 for active high reset.
C1_INPUT_CLK_TYPE : string := "DIFFERENTIAL"; -- input clock type DIFFERENTIAL or SINGLE_ENDED.
C1_CALIB_SOFT_IP : string := "TRUE"; -- # = TRUE, Enables the soft calibration logic, # = FALSE, Disables the soft calibration logic.
C1_SIMULATION : string := "FALSE"; -- # = TRUE, Simulating the design. Useful to reduce the simulation time, # = FALSE, Implementing the design.
C1_HW_TESTING : string := "FALSE"; -- Determines the address space accessed by the traffic generator, # = FALSE, Smaller address space, # = TRUE, Large address space.
DEBUG_EN : integer := 0; -- # = 1, Enable debug signals/controls, = 0, Disable debug signals/controls.
C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- The order in which user address is provided to the memory controller, ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C1_NUM_DQ_PINS : integer := 16; -- External memory data width.
C1_MEM_ADDR_WIDTH : integer := 14; -- External memory address width.
C1_MEM_BANKADDR_WIDTH : integer := 3; -- External memory bank address width.
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 2500; -- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0; -- # = 1 for active low reset, # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "DIFFERENTIAL"; -- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE"; -- # = TRUE, Enables the soft calibration logic,# = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE"; -- # = TRUE, Simulating the design. Useful to reduce the simulation time, # = FALSE, Implementing the design.
C3_HW_TESTING : string := "FALSE"; -- Determines the address space accessed by the traffic generator, # = FALSE, Smaller address space, # = TRUE, Large address space.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- The order in which user address is provided to the memory controller, ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16; -- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 14; -- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3); -- External memory bank address width.
port (
calib_done : out std_logic;
error : out std_logic;
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
mcb1_dram_udm : out std_logic;
mcb1_c1_sys_clk_p : in std_logic;
mcb1_c1_sys_clk_n : in std_logic;
mcb1_c1_sys_rst_i : in std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_c3_sys_clk_p : in std_logic;
mcb3_c3_sys_clk_n : in std_logic;
mcb3_c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
pcie_txp : out std_logic;
pcie_txn : out std_logic;
pcie_rxp : in std_logic;
pcie_rxn : in std_logic;
pcie_sys_clk_p : in std_logic;
pcie_sys_clk_n : in std_logic;
pcie_sys_reset_n : in std_logic;
led : out std_logic_vector(2 downto 0));
end top;
architecture Behavioral of top is
begin
ddr3_inst: entity work.example_top port map(
calib_done => calib_done,
error => error,
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_odt => mcb1_dram_odt,
mcb1_dram_reset_n => mcb1_dram_reset_n,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_dm => mcb1_dram_dm,
mcb1_dram_udqs => mcb1_dram_udqs,
mcb1_dram_udqs_n => mcb1_dram_udqs_n,
mcb1_rzq => mcb1_rzq,
mcb1_zio => mcb1_zio,
mcb1_dram_udm => mcb1_dram_udm,
c1_sys_clk_p => mcb1_c1_sys_clk_p,
c1_sys_clk_n => mcb1_c1_sys_clk_n,
c1_sys_rst_i => mcb1_c1_sys_rst_i,
mcb1_dram_dqs => mcb1_dram_dqs,
mcb1_dram_dqs_n => mcb1_dram_dqs_n,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
c3_sys_clk_p => mcb3_c3_sys_clk_p,
c3_sys_clk_n => mcb3_c3_sys_clk_n,
c3_sys_rst_i => mcb3_c3_sys_rst_i,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n);
pcie_inst: entity work.xilinx_pcie_1_1_ep_s6
generic map (FAST_TRAIN => FALSE)
port map (
pci_exp_txp => pcie_txp,
pci_exp_txn => pcie_txn,
pci_exp_rxp => pcie_rxp,
pci_exp_rxn => pcie_rxn,
sys_clk_p => pcie_sys_clk_p,
sys_clk_n => pcie_sys_clk_n,
sys_reset_n => pcie_sys_reset_n,
led_0 => led(0),
led_1 => led(1),
led_2 => led(2));
end Behavioral;
| gpl-3.0 |
timofonic/PHDL | misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_pipe_v6.vhd | 1 | 62379 | -------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_pipe_v6.vhd
-- Description: PIPE module for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pcie_pipe_v6 is
generic (
NO_OF_LANES : integer := 8;
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
);
port (
-- Pipe Per-Link Signals
pipe_tx_rcvr_det_i : in std_logic;
pipe_tx_reset_i : in std_logic;
pipe_tx_rate_i : in std_logic;
pipe_tx_deemph_i : in std_logic;
pipe_tx_margin_i : in std_logic_vector(2 downto 0);
pipe_tx_swing_i : in std_logic;
pipe_tx_rcvr_det_o : out std_logic;
pipe_tx_reset_o : out std_logic;
pipe_tx_rate_o : out std_logic;
pipe_tx_deemph_o : out std_logic;
pipe_tx_margin_o : out std_logic_vector(2 downto 0);
pipe_tx_swing_o : out std_logic;
-- Pipe Per-Lane Signals - Lane 0
pipe_rx0_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx0_data_o : out std_logic_vector(15 downto 0);
pipe_rx0_valid_o : out std_logic;
pipe_rx0_chanisaligned_o : out std_logic;
pipe_rx0_status_o : out std_logic_vector(2 downto 0);
pipe_rx0_phy_status_o : out std_logic;
pipe_rx0_elec_idle_o : out std_logic;
pipe_rx0_polarity_i : in std_logic;
pipe_tx0_compliance_i : in std_logic;
pipe_tx0_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx0_data_i : in std_logic_vector(15 downto 0);
pipe_tx0_elec_idle_i : in std_logic;
pipe_tx0_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx0_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx0_data_i : in std_logic_vector(15 downto 0);
pipe_rx0_valid_i : in std_logic;
pipe_rx0_chanisaligned_i : in std_logic;
pipe_rx0_status_i : in std_logic_vector(2 downto 0);
pipe_rx0_phy_status_i : in std_logic;
pipe_rx0_elec_idle_i : in std_logic;
pipe_rx0_polarity_o : out std_logic;
pipe_tx0_compliance_o : out std_logic;
pipe_tx0_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx0_data_o : out std_logic_vector(15 downto 0);
pipe_tx0_elec_idle_o : out std_logic;
pipe_tx0_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 1
pipe_rx1_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx1_data_o : out std_logic_vector(15 downto 0);
pipe_rx1_valid_o : out std_logic;
pipe_rx1_chanisaligned_o : out std_logic;
pipe_rx1_status_o : out std_logic_vector(2 downto 0);
pipe_rx1_phy_status_o : out std_logic;
pipe_rx1_elec_idle_o : out std_logic;
pipe_rx1_polarity_i : in std_logic;
pipe_tx1_compliance_i : in std_logic;
pipe_tx1_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx1_data_i : in std_logic_vector(15 downto 0);
pipe_tx1_elec_idle_i : in std_logic;
pipe_tx1_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx1_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx1_data_i : in std_logic_vector(15 downto 0);
pipe_rx1_valid_i : in std_logic;
pipe_rx1_chanisaligned_i : in std_logic;
pipe_rx1_status_i : in std_logic_vector(2 downto 0);
pipe_rx1_phy_status_i : in std_logic;
pipe_rx1_elec_idle_i : in std_logic;
pipe_rx1_polarity_o : out std_logic;
pipe_tx1_compliance_o : out std_logic;
pipe_tx1_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx1_data_o : out std_logic_vector(15 downto 0);
pipe_tx1_elec_idle_o : out std_logic;
pipe_tx1_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 2
pipe_rx2_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx2_data_o : out std_logic_vector(15 downto 0);
pipe_rx2_valid_o : out std_logic;
pipe_rx2_chanisaligned_o : out std_logic;
pipe_rx2_status_o : out std_logic_vector(2 downto 0);
pipe_rx2_phy_status_o : out std_logic;
pipe_rx2_elec_idle_o : out std_logic;
pipe_rx2_polarity_i : in std_logic;
pipe_tx2_compliance_i : in std_logic;
pipe_tx2_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx2_data_i : in std_logic_vector(15 downto 0);
pipe_tx2_elec_idle_i : in std_logic;
pipe_tx2_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx2_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx2_data_i : in std_logic_vector(15 downto 0);
pipe_rx2_valid_i : in std_logic;
pipe_rx2_chanisaligned_i : in std_logic;
pipe_rx2_status_i : in std_logic_vector(2 downto 0);
pipe_rx2_phy_status_i : in std_logic;
pipe_rx2_elec_idle_i : in std_logic;
pipe_rx2_polarity_o : out std_logic;
pipe_tx2_compliance_o : out std_logic;
pipe_tx2_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx2_data_o : out std_logic_vector(15 downto 0);
pipe_tx2_elec_idle_o : out std_logic;
pipe_tx2_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 3
pipe_rx3_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx3_data_o : out std_logic_vector(15 downto 0);
pipe_rx3_valid_o : out std_logic;
pipe_rx3_chanisaligned_o : out std_logic;
pipe_rx3_status_o : out std_logic_vector(2 downto 0);
pipe_rx3_phy_status_o : out std_logic;
pipe_rx3_elec_idle_o : out std_logic;
pipe_rx3_polarity_i : in std_logic;
pipe_tx3_compliance_i : in std_logic;
pipe_tx3_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx3_data_i : in std_logic_vector(15 downto 0);
pipe_tx3_elec_idle_i : in std_logic;
pipe_tx3_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx3_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx3_data_i : in std_logic_vector(15 downto 0);
pipe_rx3_valid_i : in std_logic;
pipe_rx3_chanisaligned_i : in std_logic;
pipe_rx3_status_i : in std_logic_vector(2 downto 0);
pipe_rx3_phy_status_i : in std_logic;
pipe_rx3_elec_idle_i : in std_logic;
pipe_rx3_polarity_o : out std_logic;
pipe_tx3_compliance_o : out std_logic;
pipe_tx3_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx3_data_o : out std_logic_vector(15 downto 0);
pipe_tx3_elec_idle_o : out std_logic;
pipe_tx3_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 4
pipe_rx4_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx4_data_o : out std_logic_vector(15 downto 0);
pipe_rx4_valid_o : out std_logic;
pipe_rx4_chanisaligned_o : out std_logic;
pipe_rx4_status_o : out std_logic_vector(2 downto 0);
pipe_rx4_phy_status_o : out std_logic;
pipe_rx4_elec_idle_o : out std_logic;
pipe_rx4_polarity_i : in std_logic;
pipe_tx4_compliance_i : in std_logic;
pipe_tx4_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx4_data_i : in std_logic_vector(15 downto 0);
pipe_tx4_elec_idle_i : in std_logic;
pipe_tx4_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx4_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx4_data_i : in std_logic_vector(15 downto 0);
pipe_rx4_valid_i : in std_logic;
pipe_rx4_chanisaligned_i : in std_logic;
pipe_rx4_status_i : in std_logic_vector(2 downto 0);
pipe_rx4_phy_status_i : in std_logic;
pipe_rx4_elec_idle_i : in std_logic;
pipe_rx4_polarity_o : out std_logic;
pipe_tx4_compliance_o : out std_logic;
pipe_tx4_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx4_data_o : out std_logic_vector(15 downto 0);
pipe_tx4_elec_idle_o : out std_logic;
pipe_tx4_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 5
pipe_rx5_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx5_data_o : out std_logic_vector(15 downto 0);
pipe_rx5_valid_o : out std_logic;
pipe_rx5_chanisaligned_o : out std_logic;
pipe_rx5_status_o : out std_logic_vector(2 downto 0);
pipe_rx5_phy_status_o : out std_logic;
pipe_rx5_elec_idle_o : out std_logic;
pipe_rx5_polarity_i : in std_logic;
pipe_tx5_compliance_i : in std_logic;
pipe_tx5_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx5_data_i : in std_logic_vector(15 downto 0);
pipe_tx5_elec_idle_i : in std_logic;
pipe_tx5_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx5_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx5_data_i : in std_logic_vector(15 downto 0);
pipe_rx5_valid_i : in std_logic;
pipe_rx5_chanisaligned_i : in std_logic;
pipe_rx5_status_i : in std_logic_vector(2 downto 0);
pipe_rx5_phy_status_i : in std_logic;
pipe_rx5_elec_idle_i : in std_logic;
pipe_rx5_polarity_o : out std_logic;
pipe_tx5_compliance_o : out std_logic;
pipe_tx5_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx5_data_o : out std_logic_vector(15 downto 0);
pipe_tx5_elec_idle_o : out std_logic;
pipe_tx5_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 6
pipe_rx6_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx6_data_o : out std_logic_vector(15 downto 0);
pipe_rx6_valid_o : out std_logic;
pipe_rx6_chanisaligned_o : out std_logic;
pipe_rx6_status_o : out std_logic_vector(2 downto 0);
pipe_rx6_phy_status_o : out std_logic;
pipe_rx6_elec_idle_o : out std_logic;
pipe_rx6_polarity_i : in std_logic;
pipe_tx6_compliance_i : in std_logic;
pipe_tx6_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx6_data_i : in std_logic_vector(15 downto 0);
pipe_tx6_elec_idle_i : in std_logic;
pipe_tx6_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx6_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx6_data_i : in std_logic_vector(15 downto 0);
pipe_rx6_valid_i : in std_logic;
pipe_rx6_chanisaligned_i : in std_logic;
pipe_rx6_status_i : in std_logic_vector(2 downto 0);
pipe_rx6_phy_status_i : in std_logic;
pipe_rx6_elec_idle_i : in std_logic;
pipe_rx6_polarity_o : out std_logic;
pipe_tx6_compliance_o : out std_logic;
pipe_tx6_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx6_data_o : out std_logic_vector(15 downto 0);
pipe_tx6_elec_idle_o : out std_logic;
pipe_tx6_powerdown_o : out std_logic_vector(1 downto 0);
-- Pipe Per-Lane Signals - Lane 7
pipe_rx7_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx7_data_o : out std_logic_vector(15 downto 0);
pipe_rx7_valid_o : out std_logic;
pipe_rx7_chanisaligned_o : out std_logic;
pipe_rx7_status_o : out std_logic_vector(2 downto 0);
pipe_rx7_phy_status_o : out std_logic;
pipe_rx7_elec_idle_o : out std_logic;
pipe_rx7_polarity_i : in std_logic;
pipe_tx7_compliance_i : in std_logic;
pipe_tx7_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx7_data_i : in std_logic_vector(15 downto 0);
pipe_tx7_elec_idle_i : in std_logic;
pipe_tx7_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx7_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx7_data_i : in std_logic_vector(15 downto 0);
pipe_rx7_valid_i : in std_logic;
pipe_rx7_chanisaligned_i : in std_logic;
pipe_rx7_status_i : in std_logic_vector(2 downto 0);
pipe_rx7_phy_status_i : in std_logic;
pipe_rx7_elec_idle_i : in std_logic;
pipe_rx7_polarity_o : out std_logic;
pipe_tx7_compliance_o : out std_logic;
pipe_tx7_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx7_data_o : out std_logic_vector(15 downto 0);
pipe_tx7_elec_idle_o : out std_logic;
pipe_tx7_powerdown_o : out std_logic_vector(1 downto 0);
-- Non PIPE signals
pl_ltssm_state : in std_logic_vector(5 downto 0);
pipe_clk : in std_logic;
rst_n : in std_logic
);
end pcie_pipe_v6;
architecture v6_pcie of pcie_pipe_v6 is
component pcie_pipe_lane_v6 is
generic (
PIPE_PIPELINE_STAGES : integer := 0
);
port (
pipe_rx_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx_data_o : out std_logic_vector(15 downto 0);
pipe_rx_valid_o : out std_logic;
pipe_rx_chanisaligned_o : out std_logic;
pipe_rx_status_o : out std_logic_vector(2 downto 0);
pipe_rx_phy_status_o : out std_logic;
pipe_rx_elec_idle_o : out std_logic;
pipe_rx_polarity_i : in std_logic;
pipe_tx_compliance_i : in std_logic;
pipe_tx_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx_data_i : in std_logic_vector(15 downto 0);
pipe_tx_elec_idle_i : in std_logic;
pipe_tx_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx_data_i : in std_logic_vector(15 downto 0);
pipe_rx_valid_i : in std_logic;
pipe_rx_chanisaligned_i : in std_logic;
pipe_rx_status_i : in std_logic_vector(2 downto 0);
pipe_rx_phy_status_i : in std_logic;
pipe_rx_elec_idle_i : in std_logic;
pipe_rx_polarity_o : out std_logic;
pipe_tx_compliance_o : out std_logic;
pipe_tx_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx_data_o : out std_logic_vector(15 downto 0);
pipe_tx_elec_idle_o : out std_logic;
pipe_tx_powerdown_o : out std_logic_vector(1 downto 0);
pipe_clk : in std_logic;
rst_n : in std_logic
);
end component;
component pcie_pipe_misc_v6 is
generic (
PIPE_PIPELINE_STAGES : integer := 0
);
port (
pipe_tx_rcvr_det_i : in std_logic;
pipe_tx_reset_i : in std_logic;
pipe_tx_rate_i : in std_logic;
pipe_tx_deemph_i : in std_logic;
pipe_tx_margin_i : in std_logic_vector(2 downto 0);
pipe_tx_swing_i : in std_logic;
pipe_tx_rcvr_det_o : out std_logic;
pipe_tx_reset_o : out std_logic;
pipe_tx_rate_o : out std_logic;
pipe_tx_deemph_o : out std_logic;
pipe_tx_margin_o : out std_logic_vector(2 downto 0);
pipe_tx_swing_o : out std_logic;
pipe_clk : in std_logic;
rst_n : in std_logic
);
end component;
--******************************************************************//
-- Reality check. //
--******************************************************************//
constant Tc2o : integer := 1; -- clock to out delay model
signal pipe_rx0_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx0_data_q : std_logic_vector(15 downto 0);
signal pipe_rx1_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx1_data_q : std_logic_vector(15 downto 0);
signal pipe_rx2_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx2_data_q : std_logic_vector(15 downto 0);
signal pipe_rx3_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx3_data_q : std_logic_vector(15 downto 0);
signal pipe_rx4_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx4_data_q : std_logic_vector(15 downto 0);
signal pipe_rx5_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx5_data_q : std_logic_vector(15 downto 0);
signal pipe_rx6_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx6_data_q : std_logic_vector(15 downto 0);
signal pipe_rx7_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx7_data_q : std_logic_vector(15 downto 0);
-- Declare intermediate signals for referenced outputs
signal pipe_tx_rcvr_det_o_v6pcie91 : std_logic;
signal pipe_tx_reset_o_v6pcie92 : std_logic;
signal pipe_tx_rate_o_v6pcie90 : std_logic;
signal pipe_tx_deemph_o_v6pcie88 : std_logic;
signal pipe_tx_margin_o_v6pcie89 : std_logic_vector(2 downto 0);
signal pipe_tx_swing_o_v6pcie93 : std_logic;
signal pipe_rx0_valid_o_v6pcie5 : std_logic;
signal pipe_rx0_chanisaligned_o_v6pcie0 : std_logic;
signal pipe_rx0_status_o_v6pcie4 : std_logic_vector(2 downto 0);
signal pipe_rx0_phy_status_o_v6pcie2 : std_logic;
signal pipe_rx0_elec_idle_o_v6pcie1 : std_logic;
signal pipe_rx0_polarity_o_v6pcie3 : std_logic;
signal pipe_tx0_compliance_o_v6pcie49 : std_logic;
signal pipe_tx0_char_is_k_o_v6pcie48 : std_logic_vector(1 downto 0);
signal pipe_tx0_data_o_v6pcie50 : std_logic_vector(15 downto 0);
signal pipe_tx0_elec_idle_o_v6pcie51 : std_logic;
signal pipe_tx0_powerdown_o_v6pcie52 : std_logic_vector(1 downto 0);
signal pipe_rx1_valid_o_v6pcie11 : std_logic;
signal pipe_rx1_chanisaligned_o_v6pcie6 : std_logic;
signal pipe_rx1_status_o_v6pcie10 : std_logic_vector(2 downto 0);
signal pipe_rx1_phy_status_o_v6pcie8 : std_logic;
signal pipe_rx1_elec_idle_o_v6pcie7 : std_logic;
signal pipe_rx1_polarity_o_v6pcie9 : std_logic;
signal pipe_tx1_compliance_o_v6pcie54 : std_logic;
signal pipe_tx1_char_is_k_o_v6pcie53 : std_logic_vector(1 downto 0);
signal pipe_tx1_data_o_v6pcie55 : std_logic_vector(15 downto 0);
signal pipe_tx1_elec_idle_o_v6pcie56 : std_logic;
signal pipe_tx1_powerdown_o_v6pcie57 : std_logic_vector(1 downto 0);
signal pipe_rx2_valid_o_v6pcie17 : std_logic;
signal pipe_rx2_chanisaligned_o_v6pcie12 : std_logic;
signal pipe_rx2_status_o_v6pcie16 : std_logic_vector(2 downto 0);
signal pipe_rx2_phy_status_o_v6pcie14 : std_logic;
signal pipe_rx2_elec_idle_o_v6pcie13 : std_logic;
signal pipe_rx2_polarity_o_v6pcie15 : std_logic;
signal pipe_tx2_compliance_o_v6pcie59 : std_logic;
signal pipe_tx2_char_is_k_o_v6pcie58 : std_logic_vector(1 downto 0);
signal pipe_tx2_data_o_v6pcie60 : std_logic_vector(15 downto 0);
signal pipe_tx2_elec_idle_o_v6pcie61 : std_logic;
signal pipe_tx2_powerdown_o_v6pcie62 : std_logic_vector(1 downto 0);
signal pipe_rx3_valid_o_v6pcie23 : std_logic;
signal pipe_rx3_chanisaligned_o_v6pcie18 : std_logic;
signal pipe_rx3_status_o_v6pcie22 : std_logic_vector(2 downto 0);
signal pipe_rx3_phy_status_o_v6pcie20 : std_logic;
signal pipe_rx3_elec_idle_o_v6pcie19 : std_logic;
signal pipe_rx3_polarity_o_v6pcie21 : std_logic;
signal pipe_tx3_compliance_o_v6pcie64 : std_logic;
signal pipe_tx3_char_is_k_o_v6pcie63 : std_logic_vector(1 downto 0);
signal pipe_tx3_data_o_v6pcie65 : std_logic_vector(15 downto 0);
signal pipe_tx3_elec_idle_o_v6pcie66 : std_logic;
signal pipe_tx3_powerdown_o_v6pcie67 : std_logic_vector(1 downto 0);
signal pipe_rx4_valid_o_v6pcie29 : std_logic;
signal pipe_rx4_chanisaligned_o_v6pcie24 : std_logic;
signal pipe_rx4_status_o_v6pcie28 : std_logic_vector(2 downto 0);
signal pipe_rx4_phy_status_o_v6pcie26 : std_logic;
signal pipe_rx4_elec_idle_o_v6pcie25 : std_logic;
signal pipe_rx4_polarity_o_v6pcie27 : std_logic;
signal pipe_tx4_compliance_o_v6pcie69 : std_logic;
signal pipe_tx4_char_is_k_o_v6pcie68 : std_logic_vector(1 downto 0);
signal pipe_tx4_data_o_v6pcie70 : std_logic_vector(15 downto 0);
signal pipe_tx4_elec_idle_o_v6pcie71 : std_logic;
signal pipe_tx4_powerdown_o_v6pcie72 : std_logic_vector(1 downto 0);
signal pipe_rx5_valid_o_v6pcie35 : std_logic;
signal pipe_rx5_chanisaligned_o_v6pcie30 : std_logic;
signal pipe_rx5_status_o_v6pcie34 : std_logic_vector(2 downto 0);
signal pipe_rx5_phy_status_o_v6pcie32 : std_logic;
signal pipe_rx5_elec_idle_o_v6pcie31 : std_logic;
signal pipe_rx5_polarity_o_v6pcie33 : std_logic;
signal pipe_tx5_compliance_o_v6pcie74 : std_logic;
signal pipe_tx5_char_is_k_o_v6pcie73 : std_logic_vector(1 downto 0);
signal pipe_tx5_data_o_v6pcie75 : std_logic_vector(15 downto 0);
signal pipe_tx5_elec_idle_o_v6pcie76 : std_logic;
signal pipe_tx5_powerdown_o_v6pcie77 : std_logic_vector(1 downto 0);
signal pipe_rx6_valid_o_v6pcie41 : std_logic;
signal pipe_rx6_chanisaligned_o_v6pcie36 : std_logic;
signal pipe_rx6_status_o_v6pcie40 : std_logic_vector(2 downto 0);
signal pipe_rx6_phy_status_o_v6pcie38 : std_logic;
signal pipe_rx6_elec_idle_o_v6pcie37 : std_logic;
signal pipe_rx6_polarity_o_v6pcie39 : std_logic;
signal pipe_tx6_compliance_o_v6pcie79 : std_logic;
signal pipe_tx6_char_is_k_o_v6pcie78 : std_logic_vector(1 downto 0);
signal pipe_tx6_data_o_v6pcie80 : std_logic_vector(15 downto 0);
signal pipe_tx6_elec_idle_o_v6pcie81 : std_logic;
signal pipe_tx6_powerdown_o_v6pcie82 : std_logic_vector(1 downto 0);
signal pipe_rx7_valid_o_v6pcie47 : std_logic;
signal pipe_rx7_chanisaligned_o_v6pcie42 : std_logic;
signal pipe_rx7_status_o_v6pcie46 : std_logic_vector(2 downto 0);
signal pipe_rx7_phy_status_o_v6pcie44 : std_logic;
signal pipe_rx7_elec_idle_o_v6pcie43 : std_logic;
signal pipe_rx7_polarity_o_v6pcie45 : std_logic;
signal pipe_tx7_compliance_o_v6pcie84 : std_logic;
signal pipe_tx7_char_is_k_o_v6pcie83 : std_logic_vector(1 downto 0);
signal pipe_tx7_data_o_v6pcie85 : std_logic_vector(15 downto 0);
signal pipe_tx7_elec_idle_o_v6pcie86 : std_logic;
signal pipe_tx7_powerdown_o_v6pcie87 : std_logic_vector(1 downto 0);
begin
-- Drive referenced outputs
pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_o_v6pcie91;
pipe_tx_reset_o <= pipe_tx_reset_o_v6pcie92;
pipe_tx_rate_o <= pipe_tx_rate_o_v6pcie90;
pipe_tx_deemph_o <= pipe_tx_deemph_o_v6pcie88;
pipe_tx_margin_o <= pipe_tx_margin_o_v6pcie89;
pipe_tx_swing_o <= pipe_tx_swing_o_v6pcie93;
pipe_rx0_valid_o <= pipe_rx0_valid_o_v6pcie5;
pipe_rx0_chanisaligned_o <= pipe_rx0_chanisaligned_o_v6pcie0;
pipe_rx0_status_o <= pipe_rx0_status_o_v6pcie4;
pipe_rx0_phy_status_o <= pipe_rx0_phy_status_o_v6pcie2;
pipe_rx0_elec_idle_o <= pipe_rx0_elec_idle_o_v6pcie1;
pipe_rx0_polarity_o <= pipe_rx0_polarity_o_v6pcie3;
pipe_tx0_compliance_o <= pipe_tx0_compliance_o_v6pcie49;
pipe_tx0_char_is_k_o <= pipe_tx0_char_is_k_o_v6pcie48;
pipe_tx0_data_o <= pipe_tx0_data_o_v6pcie50;
pipe_tx0_elec_idle_o <= pipe_tx0_elec_idle_o_v6pcie51;
pipe_tx0_powerdown_o <= pipe_tx0_powerdown_o_v6pcie52;
pipe_rx1_valid_o <= pipe_rx1_valid_o_v6pcie11;
pipe_rx1_chanisaligned_o <= pipe_rx1_chanisaligned_o_v6pcie6;
pipe_rx1_status_o <= pipe_rx1_status_o_v6pcie10;
pipe_rx1_phy_status_o <= pipe_rx1_phy_status_o_v6pcie8;
pipe_rx1_elec_idle_o <= pipe_rx1_elec_idle_o_v6pcie7;
pipe_rx1_polarity_o <= pipe_rx1_polarity_o_v6pcie9;
pipe_tx1_compliance_o <= pipe_tx1_compliance_o_v6pcie54;
pipe_tx1_char_is_k_o <= pipe_tx1_char_is_k_o_v6pcie53;
pipe_tx1_data_o <= pipe_tx1_data_o_v6pcie55;
pipe_tx1_elec_idle_o <= pipe_tx1_elec_idle_o_v6pcie56;
pipe_tx1_powerdown_o <= pipe_tx1_powerdown_o_v6pcie57;
pipe_rx2_valid_o <= pipe_rx2_valid_o_v6pcie17;
pipe_rx2_chanisaligned_o <= pipe_rx2_chanisaligned_o_v6pcie12;
pipe_rx2_status_o <= pipe_rx2_status_o_v6pcie16;
pipe_rx2_phy_status_o <= pipe_rx2_phy_status_o_v6pcie14;
pipe_rx2_elec_idle_o <= pipe_rx2_elec_idle_o_v6pcie13;
pipe_rx2_polarity_o <= pipe_rx2_polarity_o_v6pcie15;
pipe_tx2_compliance_o <= pipe_tx2_compliance_o_v6pcie59;
pipe_tx2_char_is_k_o <= pipe_tx2_char_is_k_o_v6pcie58;
pipe_tx2_data_o <= pipe_tx2_data_o_v6pcie60;
pipe_tx2_elec_idle_o <= pipe_tx2_elec_idle_o_v6pcie61;
pipe_tx2_powerdown_o <= pipe_tx2_powerdown_o_v6pcie62;
pipe_rx3_valid_o <= pipe_rx3_valid_o_v6pcie23;
pipe_rx3_chanisaligned_o <= pipe_rx3_chanisaligned_o_v6pcie18;
pipe_rx3_status_o <= pipe_rx3_status_o_v6pcie22;
pipe_rx3_phy_status_o <= pipe_rx3_phy_status_o_v6pcie20;
pipe_rx3_elec_idle_o <= pipe_rx3_elec_idle_o_v6pcie19;
pipe_rx3_polarity_o <= pipe_rx3_polarity_o_v6pcie21;
pipe_tx3_compliance_o <= pipe_tx3_compliance_o_v6pcie64;
pipe_tx3_char_is_k_o <= pipe_tx3_char_is_k_o_v6pcie63;
pipe_tx3_data_o <= pipe_tx3_data_o_v6pcie65;
pipe_tx3_elec_idle_o <= pipe_tx3_elec_idle_o_v6pcie66;
pipe_tx3_powerdown_o <= pipe_tx3_powerdown_o_v6pcie67;
pipe_rx4_valid_o <= pipe_rx4_valid_o_v6pcie29;
pipe_rx4_chanisaligned_o <= pipe_rx4_chanisaligned_o_v6pcie24;
pipe_rx4_status_o <= pipe_rx4_status_o_v6pcie28;
pipe_rx4_phy_status_o <= pipe_rx4_phy_status_o_v6pcie26;
pipe_rx4_elec_idle_o <= pipe_rx4_elec_idle_o_v6pcie25;
pipe_rx4_polarity_o <= pipe_rx4_polarity_o_v6pcie27;
pipe_tx4_compliance_o <= pipe_tx4_compliance_o_v6pcie69;
pipe_tx4_char_is_k_o <= pipe_tx4_char_is_k_o_v6pcie68;
pipe_tx4_data_o <= pipe_tx4_data_o_v6pcie70;
pipe_tx4_elec_idle_o <= pipe_tx4_elec_idle_o_v6pcie71;
pipe_tx4_powerdown_o <= pipe_tx4_powerdown_o_v6pcie72;
pipe_rx5_valid_o <= pipe_rx5_valid_o_v6pcie35;
pipe_rx5_chanisaligned_o <= pipe_rx5_chanisaligned_o_v6pcie30;
pipe_rx5_status_o <= pipe_rx5_status_o_v6pcie34;
pipe_rx5_phy_status_o <= pipe_rx5_phy_status_o_v6pcie32;
pipe_rx5_elec_idle_o <= pipe_rx5_elec_idle_o_v6pcie31;
pipe_rx5_polarity_o <= pipe_rx5_polarity_o_v6pcie33;
pipe_tx5_compliance_o <= pipe_tx5_compliance_o_v6pcie74;
pipe_tx5_char_is_k_o <= pipe_tx5_char_is_k_o_v6pcie73;
pipe_tx5_data_o <= pipe_tx5_data_o_v6pcie75;
pipe_tx5_elec_idle_o <= pipe_tx5_elec_idle_o_v6pcie76;
pipe_tx5_powerdown_o <= pipe_tx5_powerdown_o_v6pcie77;
pipe_rx6_valid_o <= pipe_rx6_valid_o_v6pcie41;
pipe_rx6_chanisaligned_o <= pipe_rx6_chanisaligned_o_v6pcie36;
pipe_rx6_status_o <= pipe_rx6_status_o_v6pcie40;
pipe_rx6_phy_status_o <= pipe_rx6_phy_status_o_v6pcie38;
pipe_rx6_elec_idle_o <= pipe_rx6_elec_idle_o_v6pcie37;
pipe_rx6_polarity_o <= pipe_rx6_polarity_o_v6pcie39;
pipe_tx6_compliance_o <= pipe_tx6_compliance_o_v6pcie79;
pipe_tx6_char_is_k_o <= pipe_tx6_char_is_k_o_v6pcie78;
pipe_tx6_data_o <= pipe_tx6_data_o_v6pcie80;
pipe_tx6_elec_idle_o <= pipe_tx6_elec_idle_o_v6pcie81;
pipe_tx6_powerdown_o <= pipe_tx6_powerdown_o_v6pcie82;
pipe_rx7_valid_o <= pipe_rx7_valid_o_v6pcie47;
pipe_rx7_chanisaligned_o <= pipe_rx7_chanisaligned_o_v6pcie42;
pipe_rx7_status_o <= pipe_rx7_status_o_v6pcie46;
pipe_rx7_phy_status_o <= pipe_rx7_phy_status_o_v6pcie44;
pipe_rx7_elec_idle_o <= pipe_rx7_elec_idle_o_v6pcie43;
pipe_rx7_polarity_o <= pipe_rx7_polarity_o_v6pcie45;
pipe_tx7_compliance_o <= pipe_tx7_compliance_o_v6pcie84;
pipe_tx7_char_is_k_o <= pipe_tx7_char_is_k_o_v6pcie83;
pipe_tx7_data_o <= pipe_tx7_data_o_v6pcie85;
pipe_tx7_elec_idle_o <= pipe_tx7_elec_idle_o_v6pcie86;
pipe_tx7_powerdown_o <= pipe_tx7_powerdown_o_v6pcie87;
--synthesis translate_off
-- initial begin
-- $display("[%t] %m NO_OF_LANES %0d PIPE_PIPELINE_STAGES %0d", $time, NO_OF_LANES, PIPE_PIPELINE_STAGES);
-- end
--synthesis translate_on
pipe_misc_i : pcie_pipe_misc_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_tx_rcvr_det_i => pipe_tx_rcvr_det_i,
pipe_tx_reset_i => pipe_tx_reset_i,
pipe_tx_rate_i => pipe_tx_rate_i,
pipe_tx_deemph_i => pipe_tx_deemph_i,
pipe_tx_margin_i => pipe_tx_margin_i,
pipe_tx_swing_i => pipe_tx_swing_i,
pipe_tx_rcvr_det_o => pipe_tx_rcvr_det_o_v6pcie91,
pipe_tx_reset_o => pipe_tx_reset_o_v6pcie92,
pipe_tx_rate_o => pipe_tx_rate_o_v6pcie90,
pipe_tx_deemph_o => pipe_tx_deemph_o_v6pcie88,
pipe_tx_margin_o => pipe_tx_margin_o_v6pcie89,
pipe_tx_swing_o => pipe_tx_swing_o_v6pcie93,
pipe_clk => pipe_clk,
rst_n => rst_n
);
pipe_lane_0_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx0_char_is_k_q,
pipe_rx_data_o => pipe_rx0_data_q,
pipe_rx_valid_o => pipe_rx0_valid_o_v6pcie5,
pipe_rx_chanisaligned_o => pipe_rx0_chanisaligned_o_v6pcie0,
pipe_rx_status_o => pipe_rx0_status_o_v6pcie4,
pipe_rx_phy_status_o => pipe_rx0_phy_status_o_v6pcie2,
pipe_rx_elec_idle_o => pipe_rx0_elec_idle_o_v6pcie1,
pipe_rx_polarity_i => pipe_rx0_polarity_i,
pipe_tx_compliance_i => pipe_tx0_compliance_i,
pipe_tx_char_is_k_i => pipe_tx0_char_is_k_i,
pipe_tx_data_i => pipe_tx0_data_i,
pipe_tx_elec_idle_i => pipe_tx0_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx0_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx0_char_is_k_i,
pipe_rx_data_i => pipe_rx0_data_i,
pipe_rx_valid_i => pipe_rx0_valid_i,
pipe_rx_chanisaligned_i => pipe_rx0_chanisaligned_i,
pipe_rx_status_i => pipe_rx0_status_i,
pipe_rx_phy_status_i => pipe_rx0_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx0_elec_idle_i,
pipe_rx_polarity_o => pipe_rx0_polarity_o_v6pcie3,
pipe_tx_compliance_o => pipe_tx0_compliance_o_v6pcie49,
pipe_tx_char_is_k_o => pipe_tx0_char_is_k_o_v6pcie48,
pipe_tx_data_o => pipe_tx0_data_o_v6pcie50,
pipe_tx_elec_idle_o => pipe_tx0_elec_idle_o_v6pcie51,
pipe_tx_powerdown_o => pipe_tx0_powerdown_o_v6pcie52,
pipe_clk => pipe_clk,
rst_n => rst_n
);
v6pcie94 : if (NO_OF_LANES >= 2) generate
pipe_lane_1_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx1_char_is_k_q,
pipe_rx_data_o => pipe_rx1_data_q,
pipe_rx_valid_o => pipe_rx1_valid_o_v6pcie11,
pipe_rx_chanisaligned_o => pipe_rx1_chanisaligned_o_v6pcie6,
pipe_rx_status_o => pipe_rx1_status_o_v6pcie10,
pipe_rx_phy_status_o => pipe_rx1_phy_status_o_v6pcie8,
pipe_rx_elec_idle_o => pipe_rx1_elec_idle_o_v6pcie7,
pipe_rx_polarity_i => pipe_rx1_polarity_i,
pipe_tx_compliance_i => pipe_tx1_compliance_i,
pipe_tx_char_is_k_i => pipe_tx1_char_is_k_i,
pipe_tx_data_i => pipe_tx1_data_i,
pipe_tx_elec_idle_i => pipe_tx1_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx1_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx1_char_is_k_i,
pipe_rx_data_i => pipe_rx1_data_i,
pipe_rx_valid_i => pipe_rx1_valid_i,
pipe_rx_chanisaligned_i => pipe_rx1_chanisaligned_i,
pipe_rx_status_i => pipe_rx1_status_i,
pipe_rx_phy_status_i => pipe_rx1_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx1_elec_idle_i,
pipe_rx_polarity_o => pipe_rx1_polarity_o_v6pcie9,
pipe_tx_compliance_o => pipe_tx1_compliance_o_v6pcie54,
pipe_tx_char_is_k_o => pipe_tx1_char_is_k_o_v6pcie53,
pipe_tx_data_o => pipe_tx1_data_o_v6pcie55,
pipe_tx_elec_idle_o => pipe_tx1_elec_idle_o_v6pcie56,
pipe_tx_powerdown_o => pipe_tx1_powerdown_o_v6pcie57,
pipe_clk => pipe_clk,
rst_n => rst_n
);
end generate;
v6pcie95 : if (not(NO_OF_LANES >= 2)) generate
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
pipe_rx1_char_is_k_q <= "00";
pipe_rx1_data_q <= "0000000000000000";
pipe_rx1_valid_o_v6pcie11 <= '0';
pipe_rx1_chanisaligned_o_v6pcie6 <= '0';
pipe_rx1_status_o_v6pcie10 <= "000";
pipe_rx1_phy_status_o_v6pcie8 <= '0';
pipe_rx1_elec_idle_o_v6pcie7 <= '1';
pipe_rx1_polarity_o_v6pcie9 <= '0';
pipe_tx1_compliance_o_v6pcie54 <= '0';
pipe_tx1_char_is_k_o_v6pcie53 <= "00";
pipe_tx1_data_o_v6pcie55 <= "0000000000000000";
pipe_tx1_elec_idle_o_v6pcie56 <= '1';
pipe_tx1_powerdown_o_v6pcie57 <= "00";
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
end generate;
v6pcie96 : if (NO_OF_LANES >= 4) generate
pipe_lane_2_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx2_char_is_k_q,
pipe_rx_data_o => pipe_rx2_data_q,
pipe_rx_valid_o => pipe_rx2_valid_o_v6pcie17,
pipe_rx_chanisaligned_o => pipe_rx2_chanisaligned_o_v6pcie12,
pipe_rx_status_o => pipe_rx2_status_o_v6pcie16,
pipe_rx_phy_status_o => pipe_rx2_phy_status_o_v6pcie14,
pipe_rx_elec_idle_o => pipe_rx2_elec_idle_o_v6pcie13,
pipe_rx_polarity_i => pipe_rx2_polarity_i,
pipe_tx_compliance_i => pipe_tx2_compliance_i,
pipe_tx_char_is_k_i => pipe_tx2_char_is_k_i,
pipe_tx_data_i => pipe_tx2_data_i,
pipe_tx_elec_idle_i => pipe_tx2_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx2_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx2_char_is_k_i,
pipe_rx_data_i => pipe_rx2_data_i,
pipe_rx_valid_i => pipe_rx2_valid_i,
pipe_rx_chanisaligned_i => pipe_rx2_chanisaligned_i,
pipe_rx_status_i => pipe_rx2_status_i,
pipe_rx_phy_status_i => pipe_rx2_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx2_elec_idle_i,
pipe_rx_polarity_o => pipe_rx2_polarity_o_v6pcie15,
pipe_tx_compliance_o => pipe_tx2_compliance_o_v6pcie59,
pipe_tx_char_is_k_o => pipe_tx2_char_is_k_o_v6pcie58,
pipe_tx_data_o => pipe_tx2_data_o_v6pcie60,
pipe_tx_elec_idle_o => pipe_tx2_elec_idle_o_v6pcie61,
pipe_tx_powerdown_o => pipe_tx2_powerdown_o_v6pcie62,
pipe_clk => pipe_clk,
rst_n => rst_n
);
pipe_lane_3_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx3_char_is_k_q,
pipe_rx_data_o => pipe_rx3_data_q,
pipe_rx_valid_o => pipe_rx3_valid_o_v6pcie23,
pipe_rx_chanisaligned_o => pipe_rx3_chanisaligned_o_v6pcie18,
pipe_rx_status_o => pipe_rx3_status_o_v6pcie22,
pipe_rx_phy_status_o => pipe_rx3_phy_status_o_v6pcie20,
pipe_rx_elec_idle_o => pipe_rx3_elec_idle_o_v6pcie19,
pipe_rx_polarity_i => pipe_rx3_polarity_i,
pipe_tx_compliance_i => pipe_tx3_compliance_i,
pipe_tx_char_is_k_i => pipe_tx3_char_is_k_i,
pipe_tx_data_i => pipe_tx3_data_i,
pipe_tx_elec_idle_i => pipe_tx3_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx3_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx3_char_is_k_i,
pipe_rx_data_i => pipe_rx3_data_i,
pipe_rx_valid_i => pipe_rx3_valid_i,
pipe_rx_chanisaligned_i => pipe_rx3_chanisaligned_i,
pipe_rx_status_i => pipe_rx3_status_i,
pipe_rx_phy_status_i => pipe_rx3_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx3_elec_idle_i,
pipe_rx_polarity_o => pipe_rx3_polarity_o_v6pcie21,
pipe_tx_compliance_o => pipe_tx3_compliance_o_v6pcie64,
pipe_tx_char_is_k_o => pipe_tx3_char_is_k_o_v6pcie63,
pipe_tx_data_o => pipe_tx3_data_o_v6pcie65,
pipe_tx_elec_idle_o => pipe_tx3_elec_idle_o_v6pcie66,
pipe_tx_powerdown_o => pipe_tx3_powerdown_o_v6pcie67,
pipe_clk => pipe_clk,
rst_n => rst_n
);
end generate;
v6pcie97 : if (not(NO_OF_LANES >= 4)) generate
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
pipe_rx2_char_is_k_q <= "00";
pipe_rx2_data_q <= "0000000000000000";
pipe_rx2_valid_o_v6pcie17 <= '0';
pipe_rx2_chanisaligned_o_v6pcie12 <= '0';
pipe_rx2_status_o_v6pcie16 <= "000";
pipe_rx2_phy_status_o_v6pcie14 <= '0';
pipe_rx2_elec_idle_o_v6pcie13 <= '1';
pipe_rx2_polarity_o_v6pcie15 <= '0';
pipe_tx2_compliance_o_v6pcie59 <= '0';
pipe_tx2_char_is_k_o_v6pcie58 <= "00";
pipe_tx2_data_o_v6pcie60 <= "0000000000000000";
pipe_tx2_elec_idle_o_v6pcie61 <= '1';
pipe_tx2_powerdown_o_v6pcie62 <= "00";
pipe_rx3_char_is_k_q <= "00";
pipe_rx3_data_q <= "0000000000000000";
pipe_rx3_valid_o_v6pcie23 <= '0';
pipe_rx3_chanisaligned_o_v6pcie18 <= '0';
pipe_rx3_status_o_v6pcie22 <= "000";
pipe_rx3_phy_status_o_v6pcie20 <= '0';
pipe_rx3_elec_idle_o_v6pcie19 <= '1';
pipe_rx3_polarity_o_v6pcie21 <= '0';
pipe_tx3_compliance_o_v6pcie64 <= '0';
pipe_tx3_char_is_k_o_v6pcie63 <= "00";
pipe_tx3_data_o_v6pcie65 <= "0000000000000000";
pipe_tx3_elec_idle_o_v6pcie66 <= '1';
pipe_tx3_powerdown_o_v6pcie67 <= "00";
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
end generate;
v6pcie98 : if (NO_OF_LANES >= 8) generate
pipe_lane_4_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx4_char_is_k_q,
pipe_rx_data_o => pipe_rx4_data_q,
pipe_rx_valid_o => pipe_rx4_valid_o_v6pcie29,
pipe_rx_chanisaligned_o => pipe_rx4_chanisaligned_o_v6pcie24,
pipe_rx_status_o => pipe_rx4_status_o_v6pcie28,
pipe_rx_phy_status_o => pipe_rx4_phy_status_o_v6pcie26,
pipe_rx_elec_idle_o => pipe_rx4_elec_idle_o_v6pcie25,
pipe_rx_polarity_i => pipe_rx4_polarity_i,
pipe_tx_compliance_i => pipe_tx4_compliance_i,
pipe_tx_char_is_k_i => pipe_tx4_char_is_k_i,
pipe_tx_data_i => pipe_tx4_data_i,
pipe_tx_elec_idle_i => pipe_tx4_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx4_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx4_char_is_k_i,
pipe_rx_data_i => pipe_rx4_data_i,
pipe_rx_valid_i => pipe_rx4_valid_i,
pipe_rx_chanisaligned_i => pipe_rx4_chanisaligned_i,
pipe_rx_status_i => pipe_rx4_status_i,
pipe_rx_phy_status_i => pipe_rx4_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx4_elec_idle_i,
pipe_rx_polarity_o => pipe_rx4_polarity_o_v6pcie27,
pipe_tx_compliance_o => pipe_tx4_compliance_o_v6pcie69,
pipe_tx_char_is_k_o => pipe_tx4_char_is_k_o_v6pcie68,
pipe_tx_data_o => pipe_tx4_data_o_v6pcie70,
pipe_tx_elec_idle_o => pipe_tx4_elec_idle_o_v6pcie71,
pipe_tx_powerdown_o => pipe_tx4_powerdown_o_v6pcie72,
pipe_clk => pipe_clk,
rst_n => rst_n
);
pipe_lane_5_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx5_char_is_k_q,
pipe_rx_data_o => pipe_rx5_data_q,
pipe_rx_valid_o => pipe_rx5_valid_o_v6pcie35,
pipe_rx_chanisaligned_o => pipe_rx5_chanisaligned_o_v6pcie30,
pipe_rx_status_o => pipe_rx5_status_o_v6pcie34,
pipe_rx_phy_status_o => pipe_rx5_phy_status_o_v6pcie32,
pipe_rx_elec_idle_o => pipe_rx5_elec_idle_o_v6pcie31,
pipe_rx_polarity_i => pipe_rx5_polarity_i,
pipe_tx_compliance_i => pipe_tx5_compliance_i,
pipe_tx_char_is_k_i => pipe_tx5_char_is_k_i,
pipe_tx_data_i => pipe_tx5_data_i,
pipe_tx_elec_idle_i => pipe_tx5_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx5_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx5_char_is_k_i,
pipe_rx_data_i => pipe_rx5_data_i,
pipe_rx_valid_i => pipe_rx5_valid_i,
pipe_rx_chanisaligned_i => pipe_rx5_chanisaligned_i,
pipe_rx_status_i => pipe_rx5_status_i,
pipe_rx_phy_status_i => pipe_rx4_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx4_elec_idle_i,
pipe_rx_polarity_o => pipe_rx5_polarity_o_v6pcie33,
pipe_tx_compliance_o => pipe_tx5_compliance_o_v6pcie74,
pipe_tx_char_is_k_o => pipe_tx5_char_is_k_o_v6pcie73,
pipe_tx_data_o => pipe_tx5_data_o_v6pcie75,
pipe_tx_elec_idle_o => pipe_tx5_elec_idle_o_v6pcie76,
pipe_tx_powerdown_o => pipe_tx5_powerdown_o_v6pcie77,
pipe_clk => pipe_clk,
rst_n => rst_n
);
pipe_lane_6_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx6_char_is_k_q,
pipe_rx_data_o => pipe_rx6_data_q,
pipe_rx_valid_o => pipe_rx6_valid_o_v6pcie41,
pipe_rx_chanisaligned_o => pipe_rx6_chanisaligned_o_v6pcie36,
pipe_rx_status_o => pipe_rx6_status_o_v6pcie40,
pipe_rx_phy_status_o => pipe_rx6_phy_status_o_v6pcie38,
pipe_rx_elec_idle_o => pipe_rx6_elec_idle_o_v6pcie37,
pipe_rx_polarity_i => pipe_rx6_polarity_i,
pipe_tx_compliance_i => pipe_tx6_compliance_i,
pipe_tx_char_is_k_i => pipe_tx6_char_is_k_i,
pipe_tx_data_i => pipe_tx6_data_i,
pipe_tx_elec_idle_i => pipe_tx6_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx6_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx6_char_is_k_i,
pipe_rx_data_i => pipe_rx6_data_i,
pipe_rx_valid_i => pipe_rx6_valid_i,
pipe_rx_chanisaligned_i => pipe_rx6_chanisaligned_i,
pipe_rx_status_i => pipe_rx6_status_i,
pipe_rx_phy_status_i => pipe_rx4_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx6_elec_idle_i,
pipe_rx_polarity_o => pipe_rx6_polarity_o_v6pcie39,
pipe_tx_compliance_o => pipe_tx6_compliance_o_v6pcie79,
pipe_tx_char_is_k_o => pipe_tx6_char_is_k_o_v6pcie78,
pipe_tx_data_o => pipe_tx6_data_o_v6pcie80,
pipe_tx_elec_idle_o => pipe_tx6_elec_idle_o_v6pcie81,
pipe_tx_powerdown_o => pipe_tx6_powerdown_o_v6pcie82,
pipe_clk => pipe_clk,
rst_n => rst_n
);
pipe_lane_7_i : pcie_pipe_lane_v6
generic map (
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
)
port map (
pipe_rx_char_is_k_o => pipe_rx7_char_is_k_q,
pipe_rx_data_o => pipe_rx7_data_q,
pipe_rx_valid_o => pipe_rx7_valid_o_v6pcie47,
pipe_rx_chanisaligned_o => pipe_rx7_chanisaligned_o_v6pcie42,
pipe_rx_status_o => pipe_rx7_status_o_v6pcie46,
pipe_rx_phy_status_o => pipe_rx7_phy_status_o_v6pcie44,
pipe_rx_elec_idle_o => pipe_rx7_elec_idle_o_v6pcie43,
pipe_rx_polarity_i => pipe_rx7_polarity_i,
pipe_tx_compliance_i => pipe_tx7_compliance_i,
pipe_tx_char_is_k_i => pipe_tx7_char_is_k_i,
pipe_tx_data_i => pipe_tx7_data_i,
pipe_tx_elec_idle_i => pipe_tx7_elec_idle_i,
pipe_tx_powerdown_i => pipe_tx7_powerdown_i,
pipe_rx_char_is_k_i => pipe_rx7_char_is_k_i,
pipe_rx_data_i => pipe_rx7_data_i,
pipe_rx_valid_i => pipe_rx7_valid_i,
pipe_rx_chanisaligned_i => pipe_rx7_chanisaligned_i,
pipe_rx_status_i => pipe_rx7_status_i,
pipe_rx_phy_status_i => pipe_rx4_phy_status_i,
pipe_rx_elec_idle_i => pipe_rx7_elec_idle_i,
pipe_rx_polarity_o => pipe_rx7_polarity_o_v6pcie45,
pipe_tx_compliance_o => pipe_tx7_compliance_o_v6pcie84,
pipe_tx_char_is_k_o => pipe_tx7_char_is_k_o_v6pcie83,
pipe_tx_data_o => pipe_tx7_data_o_v6pcie85,
pipe_tx_elec_idle_o => pipe_tx7_elec_idle_o_v6pcie86,
pipe_tx_powerdown_o => pipe_tx7_powerdown_o_v6pcie87,
pipe_clk => pipe_clk,
rst_n => rst_n
);
end generate;
v6pcie99 : if (not(NO_OF_LANES >= 8)) generate
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
pipe_rx4_char_is_k_q <= "00";
pipe_rx4_data_q <= "0000000000000000";
pipe_rx4_valid_o_v6pcie29 <= '0';
pipe_rx4_chanisaligned_o_v6pcie24 <= '0';
pipe_rx4_status_o_v6pcie28 <= "000";
pipe_rx4_phy_status_o_v6pcie26 <= '0';
pipe_rx4_elec_idle_o_v6pcie25 <= '1';
pipe_rx4_polarity_o_v6pcie27 <= '0';
pipe_tx4_compliance_o_v6pcie69 <= '0';
pipe_tx4_char_is_k_o_v6pcie68 <= "00";
pipe_tx4_data_o_v6pcie70 <= "0000000000000000";
pipe_tx4_elec_idle_o_v6pcie71 <= '1';
pipe_tx4_powerdown_o_v6pcie72 <= "00";
pipe_rx5_char_is_k_q <= "00";
pipe_rx5_data_q <= "0000000000000000";
pipe_rx5_valid_o_v6pcie35 <= '0';
pipe_rx5_chanisaligned_o_v6pcie30 <= '0';
pipe_rx5_status_o_v6pcie34 <= "000";
pipe_rx5_phy_status_o_v6pcie32 <= '0';
pipe_rx5_elec_idle_o_v6pcie31 <= '1';
pipe_rx5_polarity_o_v6pcie33 <= '0';
pipe_tx5_compliance_o_v6pcie74 <= '0';
pipe_tx5_char_is_k_o_v6pcie73 <= "00";
pipe_tx5_data_o_v6pcie75 <= "0000000000000000";
pipe_tx5_elec_idle_o_v6pcie76 <= '1';
pipe_tx5_powerdown_o_v6pcie77 <= "00";
pipe_rx6_char_is_k_q <= "00";
pipe_rx6_data_q <= "0000000000000000";
pipe_rx6_valid_o_v6pcie41 <= '0';
pipe_rx6_chanisaligned_o_v6pcie36 <= '0';
pipe_rx6_status_o_v6pcie40 <= "000";
pipe_rx6_phy_status_o_v6pcie38 <= '0';
pipe_rx6_elec_idle_o_v6pcie37 <= '1';
pipe_rx6_polarity_o_v6pcie39 <= '0';
pipe_tx6_compliance_o_v6pcie79 <= '0';
pipe_tx6_char_is_k_o_v6pcie78 <= "00";
pipe_tx6_data_o_v6pcie80 <= "0000000000000000";
pipe_tx6_elec_idle_o_v6pcie81 <= '1';
pipe_tx6_powerdown_o_v6pcie82 <= "00";
pipe_rx7_char_is_k_q <= "00";
pipe_rx7_data_q <= "0000000000000000";
pipe_rx7_valid_o_v6pcie47 <= '0';
pipe_rx7_chanisaligned_o_v6pcie42 <= '0';
pipe_rx7_status_o_v6pcie46 <= "000";
pipe_rx7_phy_status_o_v6pcie44 <= '0';
pipe_rx7_elec_idle_o_v6pcie43 <= '1';
pipe_rx7_polarity_o_v6pcie45 <= '0';
pipe_tx7_compliance_o_v6pcie84 <= '0';
pipe_tx7_char_is_k_o_v6pcie83 <= "00";
pipe_tx7_data_o_v6pcie85 <= "0000000000000000";
pipe_tx7_elec_idle_o_v6pcie86 <= '1';
pipe_tx7_powerdown_o_v6pcie87 <= "00";
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
end generate;
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
pipe_rx0_char_is_k_o <= pipe_rx0_char_is_k_q;
pipe_rx0_data_o <= pipe_rx0_data_q;
pipe_rx1_char_is_k_o <= pipe_rx1_char_is_k_q;
pipe_rx1_data_o <= pipe_rx1_data_q;
pipe_rx2_char_is_k_o <= pipe_rx2_char_is_k_q;
pipe_rx2_data_o <= pipe_rx2_data_q;
pipe_rx3_char_is_k_o <= pipe_rx3_char_is_k_q;
pipe_rx3_data_o <= pipe_rx3_data_q;
pipe_rx4_char_is_k_o <= pipe_rx4_char_is_k_q;
pipe_rx4_data_o <= pipe_rx4_data_q;
pipe_rx5_char_is_k_o <= pipe_rx5_char_is_k_q;
pipe_rx5_data_o <= pipe_rx5_data_q;
pipe_rx6_char_is_k_o <= pipe_rx6_char_is_k_q;
pipe_rx6_data_o <= pipe_rx6_data_q;
pipe_rx7_char_is_k_o <= pipe_rx7_char_is_k_q;
pipe_rx7_data_o <= pipe_rx7_data_q;
end v6_pcie;
| gpl-3.0 |
vpereira/golden_unicorn | bin/fpga/ipcore_dir/mem0/user_design/rtl/mem0.vhd | 1 | 45416 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.5
-- \ \ Application : MIG
-- / / Filename : mem0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/05/18 11:08:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity mem0 is
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 2
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic;
c3_p4_cmd_clk : in std_logic;
c3_p4_cmd_en : in std_logic;
c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p4_cmd_empty : out std_logic;
c3_p4_cmd_full : out std_logic;
c3_p4_wr_clk : in std_logic;
c3_p4_wr_en : in std_logic;
c3_p4_wr_mask : in std_logic_vector(3 downto 0);
c3_p4_wr_data : in std_logic_vector(31 downto 0);
c3_p4_wr_full : out std_logic;
c3_p4_wr_empty : out std_logic;
c3_p4_wr_count : out std_logic_vector(6 downto 0);
c3_p4_wr_underrun : out std_logic;
c3_p4_wr_error : out std_logic;
c3_p5_cmd_clk : in std_logic;
c3_p5_cmd_en : in std_logic;
c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p5_cmd_empty : out std_logic;
c3_p5_cmd_full : out std_logic;
c3_p5_rd_clk : in std_logic;
c3_p5_rd_en : in std_logic;
c3_p5_rd_data : out std_logic_vector(31 downto 0);
c3_p5_rd_full : out std_logic;
c3_p5_rd_empty : out std_logic;
c3_p5_rd_count : out std_logic_vector(6 downto 0);
c3_p5_rd_overflow : out std_logic;
c3_p5_rd_error : out std_logic
);
end mem0;
architecture arc of mem0 is
component memc3_infrastructure is
generic (
C_MEMCLK_PERIOD : integer;
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_n : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 downto 0);
p2_wr_data : in std_logic_vector(31 downto 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 downto 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 downto 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 downto 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 downto 0);
p4_cmd_bl : in std_logic_vector(5 downto 0);
p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 downto 0);
p4_wr_data : in std_logic_vector(31 downto 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 downto 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 downto 0);
p5_cmd_bl : in std_logic_vector(5 downto 0);
p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 downto 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 downto 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
constant C3_CLKOUT0_DIVIDE : integer := 2;
constant C3_CLKOUT1_DIVIDE : integer := 2;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 4;
constant C3_DIVCLK_DIVIDE : integer := 1;
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := o"012345";
constant C3_ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := o"123450";
constant C3_ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := o"234501";
constant C3_ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := o"345012";
constant C3_ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := o"450123";
constant C3_ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := o"501234";
constant C3_ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := o"012345";
constant C3_ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := o"123450";
constant C3_ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := o"234501";
constant C3_ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := o"345012";
constant C3_ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := o"450123";
constant C3_ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := o"501234";
constant C3_MEM_TRAS : integer := 40000;
constant C3_MEM_TRCD : integer := 15000;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 70000;
constant C3_MEM_TRP : integer := 15000;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 2;
constant C3_MEM_TYPE : string := "DDR";
constant C3_MEM_DENSITY : string := "512Mb";
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_CAS_LATENCY : integer := 3;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV2";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 1;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_n => c3_sys_rst_n,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p0_cmd_clk => c3_p0_cmd_clk,
p0_cmd_en => c3_p0_cmd_en,
p0_cmd_instr => c3_p0_cmd_instr,
p0_cmd_bl => c3_p0_cmd_bl,
p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
p0_cmd_empty => c3_p0_cmd_empty,
p0_cmd_full => c3_p0_cmd_full,
p0_wr_clk => c3_p0_wr_clk,
p0_wr_en => c3_p0_wr_en,
p0_wr_mask => c3_p0_wr_mask,
p0_wr_data => c3_p0_wr_data,
p0_wr_full => c3_p0_wr_full,
p0_wr_empty => c3_p0_wr_empty,
p0_wr_count => c3_p0_wr_count,
p0_wr_underrun => c3_p0_wr_underrun,
p0_wr_error => c3_p0_wr_error,
p0_rd_clk => c3_p0_rd_clk,
p0_rd_en => c3_p0_rd_en,
p0_rd_data => c3_p0_rd_data,
p0_rd_full => c3_p0_rd_full,
p0_rd_empty => c3_p0_rd_empty,
p0_rd_count => c3_p0_rd_count,
p0_rd_overflow => c3_p0_rd_overflow,
p0_rd_error => c3_p0_rd_error,
p1_cmd_clk => c3_p1_cmd_clk,
p1_cmd_en => c3_p1_cmd_en,
p1_cmd_instr => c3_p1_cmd_instr,
p1_cmd_bl => c3_p1_cmd_bl,
p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
p1_cmd_empty => c3_p1_cmd_empty,
p1_cmd_full => c3_p1_cmd_full,
p1_wr_clk => c3_p1_wr_clk,
p1_wr_en => c3_p1_wr_en,
p1_wr_mask => c3_p1_wr_mask,
p1_wr_data => c3_p1_wr_data,
p1_wr_full => c3_p1_wr_full,
p1_wr_empty => c3_p1_wr_empty,
p1_wr_count => c3_p1_wr_count,
p1_wr_underrun => c3_p1_wr_underrun,
p1_wr_error => c3_p1_wr_error,
p1_rd_clk => c3_p1_rd_clk,
p1_rd_en => c3_p1_rd_en,
p1_rd_data => c3_p1_rd_data,
p1_rd_full => c3_p1_rd_full,
p1_rd_empty => c3_p1_rd_empty,
p1_rd_count => c3_p1_rd_count,
p1_rd_overflow => c3_p1_rd_overflow,
p1_rd_error => c3_p1_rd_error,
p2_cmd_clk => c3_p2_cmd_clk,
p2_cmd_en => c3_p2_cmd_en,
p2_cmd_instr => c3_p2_cmd_instr,
p2_cmd_bl => c3_p2_cmd_bl,
p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
p2_cmd_empty => c3_p2_cmd_empty,
p2_cmd_full => c3_p2_cmd_full,
p2_wr_clk => c3_p2_wr_clk,
p2_wr_en => c3_p2_wr_en,
p2_wr_mask => c3_p2_wr_mask,
p2_wr_data => c3_p2_wr_data,
p2_wr_full => c3_p2_wr_full,
p2_wr_empty => c3_p2_wr_empty,
p2_wr_count => c3_p2_wr_count,
p2_wr_underrun => c3_p2_wr_underrun,
p2_wr_error => c3_p2_wr_error,
p3_cmd_clk => c3_p3_cmd_clk,
p3_cmd_en => c3_p3_cmd_en,
p3_cmd_instr => c3_p3_cmd_instr,
p3_cmd_bl => c3_p3_cmd_bl,
p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
p3_cmd_empty => c3_p3_cmd_empty,
p3_cmd_full => c3_p3_cmd_full,
p3_rd_clk => c3_p3_rd_clk,
p3_rd_en => c3_p3_rd_en,
p3_rd_data => c3_p3_rd_data,
p3_rd_full => c3_p3_rd_full,
p3_rd_empty => c3_p3_rd_empty,
p3_rd_count => c3_p3_rd_count,
p3_rd_overflow => c3_p3_rd_overflow,
p3_rd_error => c3_p3_rd_error,
p4_cmd_clk => c3_p4_cmd_clk,
p4_cmd_en => c3_p4_cmd_en,
p4_cmd_instr => c3_p4_cmd_instr,
p4_cmd_bl => c3_p4_cmd_bl,
p4_cmd_byte_addr => c3_p4_cmd_byte_addr,
p4_cmd_empty => c3_p4_cmd_empty,
p4_cmd_full => c3_p4_cmd_full,
p4_wr_clk => c3_p4_wr_clk,
p4_wr_en => c3_p4_wr_en,
p4_wr_mask => c3_p4_wr_mask,
p4_wr_data => c3_p4_wr_data,
p4_wr_full => c3_p4_wr_full,
p4_wr_empty => c3_p4_wr_empty,
p4_wr_count => c3_p4_wr_count,
p4_wr_underrun => c3_p4_wr_underrun,
p4_wr_error => c3_p4_wr_error,
p5_cmd_clk => c3_p5_cmd_clk,
p5_cmd_en => c3_p5_cmd_en,
p5_cmd_instr => c3_p5_cmd_instr,
p5_cmd_bl => c3_p5_cmd_bl,
p5_cmd_byte_addr => c3_p5_cmd_byte_addr,
p5_cmd_empty => c3_p5_cmd_empty,
p5_cmd_full => c3_p5_cmd_full,
p5_rd_clk => c3_p5_rd_clk,
p5_rd_en => c3_p5_rd_en,
p5_rd_data => c3_p5_rd_data,
p5_rd_full => c3_p5_rd_full,
p5_rd_empty => c3_p5_rd_empty,
p5_rd_count => c3_p5_rd_count,
p5_rd_overflow => c3_p5_rd_overflow,
p5_rd_error => c3_p5_rd_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
end arc;
| gpl-3.0 |
karthikb351/OpenCAD | public/assets/js/ace/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| gpl-3.0 |
vpereira/golden_unicorn | bin/fpga/intraffic.vhd | 42 | 1939 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity intraffic is
port(
RESET : in std_logic;
CONT : in std_logic;
IFCLK : in std_logic;
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic
);
end intraffic;
architecture RTL of intraffic is
----------------------------
-- test pattern generator --
----------------------------
-- 30 bit counter
signal GEN_CNT : std_logic_vector(29 downto 0);
signal INT_CNT : std_logic_vector(6 downto 0);
signal FIFO_WORD : std_logic;
begin
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1'; -- no data alignment
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
INT_CNT <= ( others => '0' );
FIFO_WORD <= '0';
SLWR <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
if CONT = '1' or FLAGB = '1'
then
if FIFO_WORD = '0'
then
FD(14 downto 0) <= GEN_CNT(14 downto 0);
else
FD(14 downto 0) <= GEN_CNT(29 downto 15);
end if;
FD(15) <= FIFO_WORD;
if FIFO_WORD = '1'
then
GEN_CNT <= GEN_CNT + '1';
if INT_CNT = conv_std_logic_vector(99,7)
then
INT_CNT <= ( others => '0' );
else
INT_CNT <= INT_CNT + '1';
end if;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
if ( INT_CNT >= conv_std_logic_vector(90,7) ) and ( CONT = '0' )
then
SLWR <= '1';
else
SLWR <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
| gpl-3.0 |
jpendlum/crash | fpga/src/common/debounce.vhd | 2 | 3388 | -------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: debounce.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Debounces input by sampling the input single twice
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity debounce is
generic (
CLOCK_FREQ : integer := 100e6; -- Clock frequency (Hz)
SAMPLE_TIME : integer := 10); -- Time between debounce samples (millseconds)
port (
clk : in std_logic; -- Clock
reset : in std_logic; -- Active high reset
input_async : in std_logic; -- Asynchronous input to debounce
input_sync : out std_logic); -- Debounced synchronous input
end entity;
architecture RTL of debounce is
-----------------------------------------------------------------------------
-- Constants Declaration
-----------------------------------------------------------------------------
constant DEBOUNCE_PERIOD : integer := integer((real(SAMPLE_TIME)/(1.0/real(CLOCK_FREQ)))/1.0e3);
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
signal debounce_cnt : integer range 0 to DEBOUNCE_PERIOD-1;
signal input_async_meta1 : std_logic;
signal input_async_meta2 : std_logic;
signal input_async_samp1 : std_logic;
signal input_async_samp2 : std_logic;
begin
proc_debounce : process(clk,reset)
begin
if (reset = '1') then
debounce_cnt <= 0;
input_async_meta1 <= '0';
input_async_meta2 <= '0';
input_async_samp1 <= '0';
input_async_samp2 <= '0';
input_sync <= '0';
else
if rising_edge(clk) then
-- Synchronizer
input_async_meta1 <= input_async;
input_async_meta2 <= input_async_meta1;
-- Debounce sampling
if (debounce_cnt = DEBOUNCE_PERIOD-1) then
input_async_samp1 <= input_async_meta2;
input_async_samp2 <= input_async_samp1;
debounce_cnt <= 0;
else
debounce_cnt <= debounce_cnt + 1;
end if;
-- Only update output on stable input
if (input_async_samp1 = '1' AND input_async_samp2 = '1') then
input_sync <= '1';
elsif (input_async_samp1 = '0' AND input_async_samp2 = '0') then
input_sync <= '0';
end if;
end if;
end if;
end process;
end architecture; | gpl-3.0 |
quicky2000/top_test_rom | testbench/testbench_top_test_rom.vhd | 1 | 2841 | --
-- This file is part of top_test_rom
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testbench_top_test_rom IS
END testbench_top_test_rom;
ARCHITECTURE behavior OF testbench_top_test_rom IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top_test_rom
PORT(
clk : IN std_logic;
w1a : INOUT std_logic_vector(15 downto 0);
w1b : INOUT std_logic_vector(15 downto 0);
w2c : INOUT std_logic_vector(15 downto 0);
rx : IN std_logic;
tx : INOUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rx : std_logic := '0';
--BiDirs
signal w1a : std_logic_vector(15 downto 0);
signal w1b : std_logic_vector(15 downto 0);
signal w2c : std_logic_vector(15 downto 0);
signal tx : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top_test_rom PORT MAP (
clk => clk,
w1a => w1a,
w1b => w1b,
w2c => w2c,
rx => rx,
tx => tx
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
jpendlum/crash | fpga/src/toplevel/zc702.vhd | 2 | 63731 | -------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: zc706.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Toplevel file for ZC702.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity zc702 is
port (
-- ARM Connections
MIO : inout std_logic_vector(53 downto 0);
PS_SRSTB : in std_logic;
PS_CLK : in std_logic;
PS_PORB : in std_logic;
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_CAS_n : inout std_logic;
DDR_WEB_pin : out std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_ODT : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_VRP : inout std_logic;
DDR_VRN : inout std_logic;
-- USRP DDR Interface
RX_DATA_CLK_N : in std_logic;
RX_DATA_CLK_P : in std_logic;
RX_DATA_N : in std_logic_vector(6 downto 0);
RX_DATA_P : in std_logic_vector(6 downto 0);
TX_DATA_N : out std_logic_vector(7 downto 0);
TX_DATA_P : out std_logic_vector(7 downto 0);
SPARE : out std_logic;
UART_TX : out std_logic);
end entity;
architecture RTL of zc702 is
-------------------------------------------------------------------------------
-- Component Declaration
-------------------------------------------------------------------------------
component zc702_ps is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_ext_slave_conn_0_M_AXI_AWADDR_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_AWVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_AWREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_WDATA_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_WSTRB_pin : out std_logic_vector(3 downto 0);
axi_ext_slave_conn_0_M_AXI_WVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_WREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_BRESP_pin : in std_logic_vector(1 downto 0);
axi_ext_slave_conn_0_M_AXI_BVALID_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_BREADY_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_ARADDR_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_ARVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_ARREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_RDATA_pin : in std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_RRESP_pin : in std_logic_vector(1 downto 0);
axi_ext_slave_conn_0_M_AXI_RVALID_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_RREADY_pin : out std_logic;
processing_system7_0_IRQ_F2P_pin : in std_logic_vector(15 downto 0);
processing_system7_0_FCLK_CLK0_pin : out std_logic;
processing_system7_0_FCLK_RESET0_N_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_AWADDR_pin : in std_logic_vector(31 downto 0);
axi_ext_master_conn_0_S_AXI_AWLEN_pin : in std_logic_vector(7 downto 0);
axi_ext_master_conn_0_S_AXI_AWSIZE_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_AWBURST_pin : in std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_AWCACHE_pin : in std_logic_vector(3 downto 0);
axi_ext_master_conn_0_S_AXI_AWPROT_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_AWVALID_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_AWREADY_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_WDATA_pin : in std_logic_vector(63 downto 0);
axi_ext_master_conn_0_S_AXI_WSTRB_pin : in std_logic_vector(7 downto 0);
axi_ext_master_conn_0_S_AXI_WLAST_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_WVALID_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_WREADY_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_BRESP_pin : out std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_BVALID_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_BREADY_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_ARADDR_pin : in std_logic_vector(31 downto 0);
axi_ext_master_conn_0_S_AXI_ARLEN_pin : in std_logic_vector(7 downto 0);
axi_ext_master_conn_0_S_AXI_ARSIZE_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_ARBURST_pin : in std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_ARCACHE_pin : in std_logic_vector(3 downto 0);
axi_ext_master_conn_0_S_AXI_ARPROT_pin : in std_logic_vector(2 downto 0);
axi_ext_master_conn_0_S_AXI_ARVALID_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_ARREADY_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_RDATA_pin : out std_logic_vector(63 downto 0);
axi_ext_master_conn_0_S_AXI_RRESP_pin : out std_logic_vector(1 downto 0);
axi_ext_master_conn_0_S_AXI_RLAST_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_RVALID_pin : out std_logic;
axi_ext_master_conn_0_S_AXI_RREADY_pin : in std_logic;
axi_ext_master_conn_0_S_AXI_AWUSER_pin : in std_logic_vector(4 downto 0);
axi_ext_master_conn_0_S_AXI_ARUSER_pin : in std_logic_vector(4 downto 0));
end component;
component ps_pl_interface is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := x"40000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := x"4001ffff");
port (
-- AXIS Stream Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- AXI-Lite Slave bus for access to control & status registers
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI ACP Bus to interface with processor system
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
-- Interrupt on successfully completed AXI ACP writes
irq : out std_logic;
-- Global reset for all accelerators
rst_glb_n : out std_logic;
-- Accelerator interfaces
-- Note: Master & Slave 0 are not listed as the Datamover componeent
-- uses both.
-- Accelerator 1
-- Accelerator 1
axis_master_1_tvalid : in std_logic;
axis_master_1_tready : out std_logic;
axis_master_1_tdata : in std_logic_vector(63 downto 0);
axis_master_1_tdest : in std_logic_vector(2 downto 0);
axis_master_1_tlast : in std_logic;
axis_master_1_irq : in std_logic;
axis_slave_1_tvalid : out std_logic;
axis_slave_1_tready : in std_logic;
axis_slave_1_tdata : out std_logic_vector(63 downto 0);
axis_slave_1_tid : out std_logic_vector(2 downto 0);
axis_slave_1_tlast : out std_logic;
axis_slave_1_irq : in std_logic;
status_1_addr : out std_logic_vector(7 downto 0);
status_1_data : in std_logic_vector(31 downto 0);
status_1_stb : out std_logic;
ctrl_1_addr : out std_logic_vector(7 downto 0);
ctrl_1_data : out std_logic_vector(31 downto 0);
ctrl_1_stb : out std_logic;
-- Accelerator 2
axis_master_2_tvalid : in std_logic;
axis_master_2_tready : out std_logic;
axis_master_2_tdata : in std_logic_vector(63 downto 0);
axis_master_2_tdest : in std_logic_vector(2 downto 0);
axis_master_2_tlast : in std_logic;
axis_master_2_irq : in std_logic;
axis_slave_2_tvalid : out std_logic;
axis_slave_2_tready : in std_logic;
axis_slave_2_tdata : out std_logic_vector(63 downto 0);
axis_slave_2_tid : out std_logic_vector(2 downto 0);
axis_slave_2_tlast : out std_logic;
axis_slave_2_irq : in std_logic;
status_2_addr : out std_logic_vector(7 downto 0);
status_2_data : in std_logic_vector(31 downto 0);
status_2_stb : out std_logic;
ctrl_2_addr : out std_logic_vector(7 downto 0);
ctrl_2_data : out std_logic_vector(31 downto 0);
ctrl_2_stb : out std_logic;
-- Accelerator 3
axis_master_3_tvalid : in std_logic;
axis_master_3_tready : out std_logic;
axis_master_3_tdata : in std_logic_vector(63 downto 0);
axis_master_3_tdest : in std_logic_vector(2 downto 0);
axis_master_3_tlast : in std_logic;
axis_master_3_irq : in std_logic;
axis_slave_3_tvalid : out std_logic;
axis_slave_3_tready : in std_logic;
axis_slave_3_tdata : out std_logic_vector(63 downto 0);
axis_slave_3_tid : out std_logic_vector(2 downto 0);
axis_slave_3_tlast : out std_logic;
axis_slave_3_irq : in std_logic;
status_3_addr : out std_logic_vector(7 downto 0);
status_3_data : in std_logic_vector(31 downto 0);
status_3_stb : out std_logic;
ctrl_3_addr : out std_logic_vector(7 downto 0);
ctrl_3_data : out std_logic_vector(31 downto 0);
ctrl_3_stb : out std_logic;
-- Accelerator 4
axis_master_4_tvalid : in std_logic;
axis_master_4_tready : out std_logic;
axis_master_4_tdata : in std_logic_vector(63 downto 0);
axis_master_4_tdest : in std_logic_vector(2 downto 0);
axis_master_4_tlast : in std_logic;
axis_master_4_irq : in std_logic;
axis_slave_4_tvalid : out std_logic;
axis_slave_4_tready : in std_logic;
axis_slave_4_tdata : out std_logic_vector(63 downto 0);
axis_slave_4_tid : out std_logic_vector(2 downto 0);
axis_slave_4_tlast : out std_logic;
axis_slave_4_irq : in std_logic;
status_4_addr : out std_logic_vector(7 downto 0);
status_4_data : in std_logic_vector(31 downto 0);
status_4_stb : out std_logic;
ctrl_4_addr : out std_logic_vector(7 downto 0);
ctrl_4_data : out std_logic_vector(31 downto 0);
ctrl_4_stb : out std_logic;
-- Accelerator 5
axis_master_5_tvalid : in std_logic;
axis_master_5_tready : out std_logic;
axis_master_5_tdata : in std_logic_vector(63 downto 0);
axis_master_5_tdest : in std_logic_vector(2 downto 0);
axis_master_5_tlast : in std_logic;
axis_master_5_irq : in std_logic;
axis_slave_5_tvalid : out std_logic;
axis_slave_5_tready : in std_logic;
axis_slave_5_tdata : out std_logic_vector(63 downto 0);
axis_slave_5_tid : out std_logic_vector(2 downto 0);
axis_slave_5_tlast : out std_logic;
axis_slave_5_irq : in std_logic;
status_5_addr : out std_logic_vector(7 downto 0);
status_5_data : in std_logic_vector(31 downto 0);
status_5_stb : out std_logic;
ctrl_5_addr : out std_logic_vector(7 downto 0);
ctrl_5_data : out std_logic_vector(31 downto 0);
ctrl_5_stb : out std_logic;
-- Accelerator 6
axis_master_6_tvalid : in std_logic;
axis_master_6_tready : out std_logic;
axis_master_6_tdata : in std_logic_vector(63 downto 0);
axis_master_6_tdest : in std_logic_vector(2 downto 0);
axis_master_6_tlast : in std_logic;
axis_master_6_irq : in std_logic;
axis_slave_6_tvalid : out std_logic;
axis_slave_6_tready : in std_logic;
axis_slave_6_tdata : out std_logic_vector(63 downto 0);
axis_slave_6_tid : out std_logic_vector(2 downto 0);
axis_slave_6_tlast : out std_logic;
axis_slave_6_irq : in std_logic;
status_6_addr : out std_logic_vector(7 downto 0);
status_6_data : in std_logic_vector(31 downto 0);
status_6_stb : out std_logic;
ctrl_6_addr : out std_logic_vector(7 downto 0);
ctrl_6_data : out std_logic_vector(31 downto 0);
ctrl_6_stb : out std_logic;
-- Accelerator 7
axis_master_7_tvalid : in std_logic;
axis_master_7_tready : out std_logic;
axis_master_7_tdata : in std_logic_vector(63 downto 0);
axis_master_7_tdest : in std_logic_vector(2 downto 0);
axis_master_7_tlast : in std_logic;
axis_master_7_irq : in std_logic;
axis_slave_7_tvalid : out std_logic;
axis_slave_7_tready : in std_logic;
axis_slave_7_tdata : out std_logic_vector(63 downto 0);
axis_slave_7_tid : out std_logic_vector(2 downto 0);
axis_slave_7_tlast : out std_logic;
axis_slave_7_irq : in std_logic;
status_7_addr : out std_logic_vector(7 downto 0);
status_7_data : in std_logic_vector(31 downto 0);
status_7_stb : out std_logic;
ctrl_7_addr : out std_logic_vector(7 downto 0);
ctrl_7_data : out std_logic_vector(31 downto 0);
ctrl_7_stb : out std_logic);
end component;
component usrp_ddr_intf_axis is
generic (
DDR_CLOCK_FREQ : integer := 100e6; -- Clock rate of DDR interface
BAUD : integer := 115200); -- UART baud rate
port (
-- USRP Interface
UART_TX : out std_logic; -- UART
RX_DATA_CLK_N : in std_logic; -- Receive data clock (N)
RX_DATA_CLK_P : in std_logic; -- Receive data clock (P)
RX_DATA_N : in std_logic_vector(6 downto 0); -- Receive data (N)
RX_DATA_P : in std_logic_vector(6 downto 0); -- Receive data (N)
TX_DATA_N : out std_logic_vector(7 downto 0); -- Transmit data (N)
TX_DATA_P : out std_logic_vector(7 downto 0); -- Transmit data (P)
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (DAC / TX Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (ADC / RX Data)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
rx_enable_aux : in std_logic;
tx_enable_aux : in std_logic);
end component;
component spectrum_sense is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Time Domain / FFT Input)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (Frequency Domain / FFT Output)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Strobes when threshold exceeded
-- Sideband signals
threshold_not_exceeded : out std_logic;
threshold_not_exceeded_stb : out std_logic;
threshold_exceeded : out std_logic;
threshold_exceeded_stb : out std_logic);
end component;
component bpsk_mod is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Binary Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used (TODO: maybe use for near empty input FIFO?)
-- AXIS Stream Master Interface (Modulated complex samples)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
trigger_stb : in std_logic);
end component;
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
signal clk : std_logic;
signal rst_n : std_logic;
signal S_AXI_AWADDR : std_logic_vector(31 downto 0);
signal S_AXI_AWVALID : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WDATA : std_logic_vector(31 downto 0);
signal S_AXI_WSTRB : std_logic_vector(3 downto 0);
signal S_AXI_WVALID : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BRESP : std_logic_vector(1 downto 0);
signal S_AXI_BVALID : std_logic;
signal S_AXI_BREADY : std_logic;
signal S_AXI_ARADDR : std_logic_vector(31 downto 0);
signal S_AXI_ARVALID : std_logic;
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RDATA : std_logic_vector(31 downto 0);
signal S_AXI_RRESP : std_logic_vector(1 downto 0);
signal S_AXI_RVALID : std_logic;
signal S_AXI_RREADY : std_logic;
signal M_AXI_AWADDR : std_logic_vector(31 downto 0);
signal M_AXI_AWPROT : std_logic_vector(2 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_AWREADY : std_logic;
signal M_AXI_WDATA : std_logic_vector(63 downto 0);
signal M_AXI_WSTRB : std_logic_vector(7 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_WREADY : std_logic;
signal M_AXI_BRESP : std_logic_vector(1 downto 0);
signal M_AXI_BVALID : std_logic;
signal M_AXI_BREADY : std_logic;
signal M_AXI_AWLEN : std_logic_vector(7 downto 0);
signal M_AXI_AWSIZE : std_logic_vector(2 downto 0);
signal M_AXI_AWBURST : std_logic_vector(1 downto 0);
signal M_AXI_AWCACHE : std_logic_vector(3 downto 0);
signal M_AXI_AWUSER : std_logic_vector(4 downto 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_ARADDR : std_logic_vector(31 downto 0);
signal M_AXI_ARPROT : std_logic_vector(2 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_ARREADY : std_logic;
signal M_AXI_RDATA : std_logic_vector(63 downto 0);
signal M_AXI_RRESP : std_logic_vector(1 downto 0);
signal M_AXI_RVALID : std_logic;
signal M_AXI_RREADY : std_logic;
signal M_AXI_RLAST : std_logic;
signal M_AXI_ARCACHE : std_logic_vector(3 downto 0);
signal M_AXI_ARUSER : std_logic_vector(4 downto 0);
signal M_AXI_ARLEN : std_logic_vector(7 downto 0);
signal M_AXI_ARBURST : std_logic_vector(1 downto 0);
signal M_AXI_ARSIZE : std_logic_vector(2 downto 0);
signal processing_system7_0_IRQ_F2P_pin : std_logic_vector(15 downto 0);
signal irq : std_logic;
signal rst_glb_n : std_logic;
signal axis_master_1_tvalid : std_logic;
signal axis_master_1_tready : std_logic;
signal axis_master_1_tdata : std_logic_vector(63 downto 0);
signal axis_master_1_tdest : std_logic_vector(2 downto 0);
signal axis_master_1_tlast : std_logic;
signal axis_master_1_irq : std_logic;
signal axis_slave_1_tvalid : std_logic;
signal axis_slave_1_tready : std_logic;
signal axis_slave_1_tdata : std_logic_vector(63 downto 0);
signal axis_slave_1_tid : std_logic_vector(2 downto 0);
signal axis_slave_1_tlast : std_logic;
signal axis_slave_1_irq : std_logic;
signal status_1_addr : std_logic_vector(7 downto 0);
signal status_1_data : std_logic_vector(31 downto 0);
signal status_1_stb : std_logic;
signal ctrl_1_addr : std_logic_vector(7 downto 0);
signal ctrl_1_data : std_logic_vector(31 downto 0);
signal ctrl_1_stb : std_logic;
signal axis_master_2_tvalid : std_logic;
signal axis_master_2_tready : std_logic;
signal axis_master_2_tdata : std_logic_vector(63 downto 0);
signal axis_master_2_tdest : std_logic_vector(2 downto 0);
signal axis_master_2_tlast : std_logic;
signal axis_master_2_irq : std_logic;
signal axis_slave_2_tvalid : std_logic;
signal axis_slave_2_tready : std_logic;
signal axis_slave_2_tdata : std_logic_vector(63 downto 0);
signal axis_slave_2_tid : std_logic_vector(2 downto 0);
signal axis_slave_2_tlast : std_logic;
signal axis_slave_2_irq : std_logic;
signal status_2_addr : std_logic_vector(7 downto 0);
signal status_2_data : std_logic_vector(31 downto 0);
signal status_2_stb : std_logic;
signal ctrl_2_addr : std_logic_vector(7 downto 0);
signal ctrl_2_data : std_logic_vector(31 downto 0);
signal ctrl_2_stb : std_logic;
signal axis_master_3_tvalid : std_logic;
signal axis_master_3_tready : std_logic;
signal axis_master_3_tdata : std_logic_vector(63 downto 0);
signal axis_master_3_tdest : std_logic_vector(2 downto 0);
signal axis_master_3_tlast : std_logic;
signal axis_master_3_irq : std_logic;
signal axis_slave_3_tvalid : std_logic;
signal axis_slave_3_tready : std_logic;
signal axis_slave_3_tdata : std_logic_vector(63 downto 0);
signal axis_slave_3_tid : std_logic_vector(2 downto 0);
signal axis_slave_3_tlast : std_logic;
signal axis_slave_3_irq : std_logic;
signal status_3_addr : std_logic_vector(7 downto 0);
signal status_3_data : std_logic_vector(31 downto 0);
signal status_3_stb : std_logic;
signal ctrl_3_addr : std_logic_vector(7 downto 0);
signal ctrl_3_data : std_logic_vector(31 downto 0);
signal ctrl_3_stb : std_logic;
signal axis_master_4_tvalid : std_logic;
signal axis_master_4_tready : std_logic;
signal axis_master_4_tdata : std_logic_vector(63 downto 0);
signal axis_master_4_tdest : std_logic_vector(2 downto 0);
signal axis_master_4_tlast : std_logic;
signal axis_master_4_irq : std_logic;
signal axis_slave_4_tvalid : std_logic;
signal axis_slave_4_tready : std_logic;
signal axis_slave_4_tdata : std_logic_vector(63 downto 0);
signal axis_slave_4_tid : std_logic_vector(2 downto 0);
signal axis_slave_4_tlast : std_logic;
signal axis_slave_4_irq : std_logic;
signal status_4_addr : std_logic_vector(7 downto 0);
signal status_4_data : std_logic_vector(31 downto 0);
signal status_4_stb : std_logic;
signal ctrl_4_addr : std_logic_vector(7 downto 0);
signal ctrl_4_data : std_logic_vector(31 downto 0);
signal ctrl_4_stb : std_logic;
signal axis_master_5_tvalid : std_logic;
signal axis_master_5_tready : std_logic;
signal axis_master_5_tdata : std_logic_vector(63 downto 0);
signal axis_master_5_tdest : std_logic_vector(2 downto 0);
signal axis_master_5_tlast : std_logic;
signal axis_master_5_irq : std_logic;
signal axis_slave_5_tvalid : std_logic;
signal axis_slave_5_tready : std_logic;
signal axis_slave_5_tdata : std_logic_vector(63 downto 0);
signal axis_slave_5_tid : std_logic_vector(2 downto 0);
signal axis_slave_5_tlast : std_logic;
signal axis_slave_5_irq : std_logic;
signal status_5_addr : std_logic_vector(7 downto 0);
signal status_5_data : std_logic_vector(31 downto 0);
signal status_5_stb : std_logic;
signal ctrl_5_addr : std_logic_vector(7 downto 0);
signal ctrl_5_data : std_logic_vector(31 downto 0);
signal ctrl_5_stb : std_logic;
signal axis_master_6_tvalid : std_logic;
signal axis_master_6_tready : std_logic;
signal axis_master_6_tdata : std_logic_vector(63 downto 0);
signal axis_master_6_tdest : std_logic_vector(2 downto 0);
signal axis_master_6_tlast : std_logic;
signal axis_master_6_irq : std_logic;
signal axis_slave_6_tvalid : std_logic;
signal axis_slave_6_tready : std_logic;
signal axis_slave_6_tdata : std_logic_vector(63 downto 0);
signal axis_slave_6_tid : std_logic_vector(2 downto 0);
signal axis_slave_6_tlast : std_logic;
signal axis_slave_6_irq : std_logic;
signal status_6_addr : std_logic_vector(7 downto 0);
signal status_6_data : std_logic_vector(31 downto 0);
signal status_6_stb : std_logic;
signal ctrl_6_addr : std_logic_vector(7 downto 0);
signal ctrl_6_data : std_logic_vector(31 downto 0);
signal ctrl_6_stb : std_logic;
signal axis_master_7_tvalid : std_logic;
signal axis_master_7_tready : std_logic;
signal axis_master_7_tdata : std_logic_vector(63 downto 0);
signal axis_master_7_tdest : std_logic_vector(2 downto 0);
signal axis_master_7_tlast : std_logic;
signal axis_master_7_irq : std_logic;
signal axis_slave_7_tvalid : std_logic;
signal axis_slave_7_tready : std_logic;
signal axis_slave_7_tdata : std_logic_vector(63 downto 0);
signal axis_slave_7_tid : std_logic_vector(2 downto 0);
signal axis_slave_7_tlast : std_logic;
signal axis_slave_7_irq : std_logic;
signal status_7_addr : std_logic_vector(7 downto 0);
signal status_7_data : std_logic_vector(31 downto 0);
signal status_7_stb : std_logic;
signal ctrl_7_addr : std_logic_vector(7 downto 0);
signal ctrl_7_data : std_logic_vector(31 downto 0);
signal ctrl_7_stb : std_logic;
signal rx_enable_aux : std_logic;
signal tx_enable_aux : std_logic;
signal threshold_not_exceeded : std_logic;
signal threshold_not_exceeded_stb : std_logic;
signal threshold_exceeded : std_logic;
signal threshold_exceeded_stb : std_logic;
signal trigger_stb : std_logic;
begin
inst_zc702_ps : zc702_ps
port map (
processing_system7_0_MIO => MIO,
processing_system7_0_PS_SRSTB_pin => PS_SRSTB,
processing_system7_0_PS_CLK_pin => PS_CLK,
processing_system7_0_PS_PORB_pin => PS_PORB,
processing_system7_0_DDR_Clk => DDR_Clk,
processing_system7_0_DDR_Clk_n => DDR_Clk_n,
processing_system7_0_DDR_CKE => DDR_CKE,
processing_system7_0_DDR_CS_n => DDR_CS_n,
processing_system7_0_DDR_RAS_n => DDR_RAS_n,
processing_system7_0_DDR_CAS_n => DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => DDR_BankAddr,
processing_system7_0_DDR_Addr => DDR_Addr,
processing_system7_0_DDR_ODT => DDR_ODT,
processing_system7_0_DDR_DRSTB => DDR_DRSTB,
processing_system7_0_DDR_DQ => DDR_DQ,
processing_system7_0_DDR_DM => DDR_DM,
processing_system7_0_DDR_DQS => DDR_DQS,
processing_system7_0_DDR_DQS_n => DDR_DQS_n,
processing_system7_0_DDR_VRN => DDR_VRN,
processing_system7_0_DDR_VRP => DDR_VRP,
axi_ext_slave_conn_0_M_AXI_AWADDR_pin => S_AXI_AWADDR,
axi_ext_slave_conn_0_M_AXI_AWVALID_pin => S_AXI_AWVALID,
axi_ext_slave_conn_0_M_AXI_AWREADY_pin => S_AXI_AWREADY,
axi_ext_slave_conn_0_M_AXI_WDATA_pin => S_AXI_WDATA,
axi_ext_slave_conn_0_M_AXI_WSTRB_pin => S_AXI_WSTRB,
axi_ext_slave_conn_0_M_AXI_WVALID_pin => S_AXI_WVALID,
axi_ext_slave_conn_0_M_AXI_WREADY_pin => S_AXI_WREADY,
axi_ext_slave_conn_0_M_AXI_BRESP_pin => S_AXI_BRESP,
axi_ext_slave_conn_0_M_AXI_BVALID_pin => S_AXI_BVALID,
axi_ext_slave_conn_0_M_AXI_BREADY_pin => S_AXI_BREADY,
axi_ext_slave_conn_0_M_AXI_ARADDR_pin => S_AXI_ARADDR,
axi_ext_slave_conn_0_M_AXI_ARVALID_pin => S_AXI_ARVALID,
axi_ext_slave_conn_0_M_AXI_ARREADY_pin => S_AXI_ARREADY,
axi_ext_slave_conn_0_M_AXI_RDATA_pin => S_AXI_RDATA,
axi_ext_slave_conn_0_M_AXI_RRESP_pin => S_AXI_RRESP,
axi_ext_slave_conn_0_M_AXI_RVALID_pin => S_AXI_RVALID,
axi_ext_slave_conn_0_M_AXI_RREADY_pin => S_AXI_RREADY,
processing_system7_0_IRQ_F2P_pin => processing_system7_0_IRQ_F2P_pin,
processing_system7_0_FCLK_CLK0_pin => clk,
processing_system7_0_FCLK_RESET0_N_pin => rst_n,
axi_ext_master_conn_0_S_AXI_AWADDR_pin => M_AXI_AWADDR,
axi_ext_master_conn_0_S_AXI_AWLEN_pin => M_AXI_AWLEN,
axi_ext_master_conn_0_S_AXI_AWSIZE_pin => M_AXI_AWSIZE,
axi_ext_master_conn_0_S_AXI_AWBURST_pin => M_AXI_AWBURST,
axi_ext_master_conn_0_S_AXI_AWCACHE_pin => M_AXI_AWCACHE,
axi_ext_master_conn_0_S_AXI_AWPROT_pin => M_AXI_AWPROT,
axi_ext_master_conn_0_S_AXI_AWVALID_pin => M_AXI_AWVALID,
axi_ext_master_conn_0_S_AXI_AWREADY_pin => M_AXI_AWREADY,
axi_ext_master_conn_0_S_AXI_WDATA_pin => M_AXI_WDATA,
axi_ext_master_conn_0_S_AXI_WSTRB_pin => M_AXI_WSTRB,
axi_ext_master_conn_0_S_AXI_WLAST_pin => M_AXI_WLAST,
axi_ext_master_conn_0_S_AXI_WVALID_pin => M_AXI_WVALID,
axi_ext_master_conn_0_S_AXI_WREADY_pin => M_AXI_WREADY,
axi_ext_master_conn_0_S_AXI_BRESP_pin => M_AXI_BRESP,
axi_ext_master_conn_0_S_AXI_BVALID_pin => M_AXI_BVALID,
axi_ext_master_conn_0_S_AXI_BREADY_pin => M_AXI_BREADY,
axi_ext_master_conn_0_S_AXI_ARADDR_pin => M_AXI_ARADDR,
axi_ext_master_conn_0_S_AXI_ARLEN_pin => M_AXI_ARLEN,
axi_ext_master_conn_0_S_AXI_ARSIZE_pin => M_AXI_ARSIZE,
axi_ext_master_conn_0_S_AXI_ARBURST_pin => M_AXI_ARBURST,
axi_ext_master_conn_0_S_AXI_ARCACHE_pin => M_AXI_ARCACHE,
axi_ext_master_conn_0_S_AXI_ARPROT_pin => M_AXI_ARPROT,
axi_ext_master_conn_0_S_AXI_ARVALID_pin => M_AXI_ARVALID,
axi_ext_master_conn_0_S_AXI_ARREADY_pin => M_AXI_ARREADY,
axi_ext_master_conn_0_S_AXI_RDATA_pin => M_AXI_RDATA,
axi_ext_master_conn_0_S_AXI_RRESP_pin => M_AXI_RRESP,
axi_ext_master_conn_0_S_AXI_RLAST_pin => M_AXI_RLAST,
axi_ext_master_conn_0_S_AXI_RVALID_pin => M_AXI_RVALID,
axi_ext_master_conn_0_S_AXI_RREADY_pin => M_AXI_RREADY,
axi_ext_master_conn_0_S_AXI_AWUSER_pin => M_AXI_AWUSER,
axi_ext_master_conn_0_S_AXI_ARUSER_pin => M_AXI_ARUSER);
processing_system7_0_IRQ_F2P_pin(15) <= irq;
inst_ps_pl_interface : ps_pl_interface
generic map (
C_BASEADDR => x"40000000",
C_HIGHADDR => x"4001ffff")
port map (
clk => clk,
rst_n => rst_n,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWUSER => M_AXI_AWUSER,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARUSER => M_AXI_ARUSER,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARSIZE => M_AXI_ARSIZE,
irq => irq,
rst_glb_n => rst_glb_n,
-- Note: Master 0 & Slave 0 interfaces are occupied by the
-- datamover component internally.
axis_master_1_tvalid => axis_master_1_tvalid,
axis_master_1_tready => axis_master_1_tready,
axis_master_1_tdata => axis_master_1_tdata,
axis_master_1_tdest => axis_master_1_tdest,
axis_master_1_tlast => axis_master_1_tlast,
axis_master_1_irq => axis_master_1_irq,
axis_slave_1_tvalid => axis_slave_1_tvalid,
axis_slave_1_tready => axis_slave_1_tready,
axis_slave_1_tdata => axis_slave_1_tdata,
axis_slave_1_tid => axis_slave_1_tid,
axis_slave_1_tlast => axis_slave_1_tlast,
axis_slave_1_irq => axis_slave_1_irq,
status_1_addr => status_1_addr,
status_1_data => status_1_data,
status_1_stb => status_1_stb,
ctrl_1_addr => ctrl_1_addr,
ctrl_1_data => ctrl_1_data,
ctrl_1_stb => ctrl_1_stb,
axis_master_2_tvalid => axis_master_2_tvalid,
axis_master_2_tready => axis_master_2_tready,
axis_master_2_tdata => axis_master_2_tdata,
axis_master_2_tdest => axis_master_2_tdest,
axis_master_2_tlast => axis_master_2_tlast,
axis_master_2_irq => axis_master_2_irq,
axis_slave_2_tvalid => axis_slave_2_tvalid,
axis_slave_2_tready => axis_slave_2_tready,
axis_slave_2_tdata => axis_slave_2_tdata,
axis_slave_2_tid => axis_slave_2_tid,
axis_slave_2_tlast => axis_slave_2_tlast,
axis_slave_2_irq => axis_slave_2_irq,
status_2_addr => status_2_addr,
status_2_data => status_2_data,
status_2_stb => status_2_stb,
ctrl_2_addr => ctrl_2_addr,
ctrl_2_data => ctrl_2_data,
ctrl_2_stb => ctrl_2_stb,
axis_master_3_tvalid => axis_master_3_tvalid,
axis_master_3_tready => axis_master_3_tready,
axis_master_3_tdata => axis_master_3_tdata,
axis_master_3_tdest => axis_master_3_tdest,
axis_master_3_tlast => axis_master_3_tlast,
axis_master_3_irq => axis_master_3_irq,
axis_slave_3_tvalid => axis_slave_3_tvalid,
axis_slave_3_tready => axis_slave_3_tready,
axis_slave_3_tdata => axis_slave_3_tdata,
axis_slave_3_tid => axis_slave_3_tid,
axis_slave_3_tlast => axis_slave_3_tlast,
axis_slave_3_irq => axis_slave_3_irq,
status_3_addr => status_3_addr,
status_3_data => status_3_data,
status_3_stb => status_3_stb,
ctrl_3_addr => ctrl_3_addr,
ctrl_3_data => ctrl_3_data,
ctrl_3_stb => ctrl_3_stb,
axis_master_4_tvalid => axis_master_4_tvalid,
axis_master_4_tready => axis_master_4_tready,
axis_master_4_tdata => axis_master_4_tdata,
axis_master_4_tdest => axis_master_4_tdest,
axis_master_4_tlast => axis_master_4_tlast,
axis_master_4_irq => axis_master_4_irq,
axis_slave_4_tvalid => axis_slave_4_tvalid,
axis_slave_4_tready => axis_slave_4_tready,
axis_slave_4_tdata => axis_slave_4_tdata,
axis_slave_4_tid => axis_slave_4_tid,
axis_slave_4_tlast => axis_slave_4_tlast,
axis_slave_4_irq => axis_slave_4_irq,
status_4_addr => status_4_addr,
status_4_data => status_4_data,
status_4_stb => status_4_stb,
ctrl_4_addr => ctrl_4_addr,
ctrl_4_data => ctrl_4_data,
ctrl_4_stb => ctrl_4_stb,
axis_master_5_tvalid => axis_master_5_tvalid,
axis_master_5_tready => axis_master_5_tready,
axis_master_5_tdata => axis_master_5_tdata,
axis_master_5_tdest => axis_master_5_tdest,
axis_master_5_tlast => axis_master_5_tlast,
axis_master_5_irq => axis_master_5_irq,
axis_slave_5_tvalid => axis_slave_5_tvalid,
axis_slave_5_tready => axis_slave_5_tready,
axis_slave_5_tdata => axis_slave_5_tdata,
axis_slave_5_tid => axis_slave_5_tid,
axis_slave_5_tlast => axis_slave_5_tlast,
axis_slave_5_irq => axis_slave_5_irq,
status_5_addr => status_5_addr,
status_5_data => status_5_data,
status_5_stb => status_5_stb,
ctrl_5_addr => ctrl_5_addr,
ctrl_5_data => ctrl_5_data,
ctrl_5_stb => ctrl_5_stb,
axis_master_6_tvalid => axis_master_6_tvalid,
axis_master_6_tready => axis_master_6_tready,
axis_master_6_tdata => axis_master_6_tdata,
axis_master_6_tdest => axis_master_6_tdest,
axis_master_6_tlast => axis_master_6_tlast,
axis_master_6_irq => axis_master_6_irq,
axis_slave_6_tvalid => axis_slave_6_tvalid,
axis_slave_6_tready => axis_slave_6_tready,
axis_slave_6_tdata => axis_slave_6_tdata,
axis_slave_6_tid => axis_slave_6_tid,
axis_slave_6_tlast => axis_slave_6_tlast,
axis_slave_6_irq => axis_slave_6_irq,
status_6_addr => status_6_addr,
status_6_data => status_6_data,
status_6_stb => status_6_stb,
ctrl_6_addr => ctrl_6_addr,
ctrl_6_data => ctrl_6_data,
ctrl_6_stb => ctrl_6_stb,
axis_master_7_tvalid => axis_master_7_tvalid,
axis_master_7_tready => axis_master_7_tready,
axis_master_7_tdata => axis_master_7_tdata,
axis_master_7_tdest => axis_master_7_tdest,
axis_master_7_tlast => axis_master_7_tlast,
axis_master_7_irq => axis_master_7_irq,
axis_slave_7_tvalid => axis_slave_7_tvalid,
axis_slave_7_tready => axis_slave_7_tready,
axis_slave_7_tdata => axis_slave_7_tdata,
axis_slave_7_tid => axis_slave_7_tid,
axis_slave_7_tlast => axis_slave_7_tlast,
axis_slave_7_irq => axis_slave_7_irq,
status_7_addr => status_7_addr,
status_7_data => status_7_data,
status_7_stb => status_7_stb,
ctrl_7_addr => ctrl_7_addr,
ctrl_7_data => ctrl_7_data,
ctrl_7_stb => ctrl_7_stb);
-- Accelerator 1
inst_usrp_ddr_intf_axis : usrp_ddr_intf_axis
generic map (
DDR_CLOCK_FREQ => 100e6,
BAUD => 115200)
port map (
UART_TX => UART_TX,
RX_DATA_CLK_N => RX_DATA_CLK_N,
RX_DATA_CLK_P => RX_DATA_CLK_P,
RX_DATA_N => RX_DATA_N,
RX_DATA_P => RX_DATA_P,
TX_DATA_N => TX_DATA_N,
TX_DATA_P => TX_DATA_P,
clk => clk,
rst_n => rst_glb_n,
status_addr => status_1_addr,
status_data => status_1_data,
status_stb => status_1_stb,
ctrl_addr => ctrl_1_addr,
ctrl_data => ctrl_1_data,
ctrl_stb => ctrl_1_stb,
axis_slave_tvalid => axis_slave_1_tvalid,
axis_slave_tready => axis_slave_1_tready,
axis_slave_tdata => axis_slave_1_tdata,
axis_slave_tid => axis_slave_1_tid,
axis_slave_tlast => axis_slave_1_tlast,
axis_slave_irq => axis_slave_1_irq,
axis_master_tvalid => axis_master_1_tvalid,
axis_master_tready => axis_master_1_tready,
axis_master_tdata => axis_master_1_tdata,
axis_master_tdest => axis_master_1_tdest,
axis_master_tlast => axis_master_1_tlast,
axis_master_irq => axis_master_1_irq,
rx_enable_aux => rx_enable_aux,
tx_enable_aux => tx_enable_aux);
rx_enable_aux <= '0';
tx_enable_aux <= threshold_exceeded OR threshold_not_exceeded;
-- Accelerator 2
inst_spectrum_sense : spectrum_sense
port map (
clk => clk,
rst_n => rst_glb_n,
status_addr => status_2_addr,
status_data => status_2_data,
status_stb => status_2_stb,
ctrl_addr => ctrl_2_addr,
ctrl_data => ctrl_2_data,
ctrl_stb => ctrl_2_stb,
axis_slave_tvalid => axis_slave_2_tvalid,
axis_slave_tready => axis_slave_2_tready,
axis_slave_tdata => axis_slave_2_tdata,
axis_slave_tid => axis_slave_2_tid,
axis_slave_tlast => axis_slave_2_tlast,
axis_slave_irq => axis_slave_2_irq,
axis_master_tvalid => axis_master_2_tvalid,
axis_master_tready => axis_master_2_tready,
axis_master_tdata => axis_master_2_tdata,
axis_master_tdest => axis_master_2_tdest,
axis_master_tlast => axis_master_2_tlast,
axis_master_irq => axis_master_2_irq,
threshold_not_exceeded => threshold_not_exceeded,
threshold_not_exceeded_stb => threshold_not_exceeded_stb,
threshold_exceeded => threshold_exceeded,
threshold_exceeded_stb => threshold_exceeded_stb);
-- Accelerator 3
inst_bpsk_mod : bpsk_mod
port map (
clk => clk,
rst_n => rst_glb_n,
status_addr => status_3_addr,
status_data => status_3_data,
status_stb => status_3_stb,
ctrl_addr => ctrl_3_addr,
ctrl_data => ctrl_3_data,
ctrl_stb => ctrl_3_stb,
axis_slave_tvalid => axis_slave_3_tvalid,
axis_slave_tready => axis_slave_3_tready,
axis_slave_tdata => axis_slave_3_tdata,
axis_slave_tid => axis_slave_3_tid,
axis_slave_tlast => axis_slave_3_tlast,
axis_slave_irq => axis_slave_3_irq,
axis_master_tvalid => axis_master_3_tvalid,
axis_master_tready => axis_master_3_tready,
axis_master_tdata => axis_master_3_tdata,
axis_master_tdest => axis_master_3_tdest,
axis_master_tlast => axis_master_3_tlast,
axis_master_irq => axis_master_3_irq,
trigger_stb => trigger_stb);
-- The output of either threshold trigger is controlled by control registers, so ORing them is
-- not an issue as only one should be active at a time.
trigger_stb <= threshold_exceeded_stb OR threshold_not_exceeded_stb;
-- Unused Accelerators
axis_slave_4_tready <= '0';
axis_slave_4_irq <= '0';
axis_master_4_tvalid <= '0';
axis_master_4_tdata <= x"0000000000000000";
axis_master_4_tdest <= "000";
axis_master_4_tlast <= '0';
axis_master_4_irq <= '0';
status_4_data <= x"00000000";
axis_slave_5_tready <= '0';
axis_slave_5_irq <= '0';
axis_master_5_tvalid <= '0';
axis_master_5_tdata <= x"0000000000000000";
axis_master_5_tdest <= "000";
axis_master_5_tlast <= '0';
axis_master_5_irq <= '0';
status_5_data <= x"00000000";
axis_slave_6_tready <= '0';
axis_slave_6_irq <= '0';
axis_master_6_tvalid <= '0';
axis_master_6_tdata <= x"0000000000000000";
axis_master_6_tdest <= "000";
axis_master_6_tlast <= '0';
axis_master_6_irq <= '0';
status_6_data <= x"00000000";
axis_slave_7_tready <= '0';
axis_slave_7_irq <= '0';
axis_master_7_tvalid <= '0';
axis_master_7_tdata <= x"0000000000000000";
axis_master_7_tdest <= "000";
axis_master_7_tlast <= '0';
axis_master_7_irq <= '0';
status_7_data <= x"00000000";
SPARE <= 'Z';
end architecture; | gpl-3.0 |
aylons/sp601_spi_test | hdl/modules/chipscope/chipscope_ila.vhd | 1 | 1050 | -------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_ila.vhd
-- /___/ /\ Timestamp : Thu Oct 30 16:23:18 BRST 2014
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_ila IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(63 downto 0);
TRIG0: in std_logic_vector(7 downto 0));
END chipscope_ila;
ARCHITECTURE chipscope_ila_a OF chipscope_ila IS
BEGIN
END chipscope_ila_a;
| gpl-3.0 |
aylons/sp601_spi_test | hdl/modules/spi/spi_loopback.vhd | 2 | 6078 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:44:37 05/17/2011
-- Design Name:
-- Module Name: spi_loopback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is a simple wrapper for the 'spi_master' and 'spi_slave' cores, to synthesize the 2 cores and
-- test them in the simulator.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;
entity spi_loopback is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 5 -- for a 100MHz sclk_i, yields a 10MHz SCK
);
Port(
----------------MASTER-----------------------
m_clk_i : IN std_logic;
m_rst_i : IN std_logic;
m_spi_ssel_o : OUT std_logic;
m_spi_sck_o : OUT std_logic;
m_spi_mosi_o : OUT std_logic;
m_spi_miso_i : IN std_logic;
m_di_req_o : OUT std_logic;
m_di_i : IN std_logic_vector(N-1 downto 0);
m_wren_i : IN std_logic;
m_do_valid_o : OUT std_logic;
m_do_o : OUT std_logic_vector(N-1 downto 0);
----- debug -----
m_do_transfer_o : OUT std_logic;
m_wren_o : OUT std_logic;
m_wren_ack_o : OUT std_logic;
m_rx_bit_reg_o : OUT std_logic;
m_state_dbg_o : OUT std_logic_vector(5 downto 0);
m_core_clk_o : OUT std_logic;
m_core_n_clk_o : OUT std_logic;
m_sh_reg_dbg_o : OUT std_logic_vector(N-1 downto 0);
----------------SLAVE-----------------------
s_clk_i : IN std_logic;
s_spi_ssel_i : IN std_logic;
s_spi_sck_i : IN std_logic;
s_spi_mosi_i : IN std_logic;
s_spi_miso_o : OUT std_logic;
s_di_req_o : OUT std_logic; -- preload lookahead data request line
s_di_i : IN std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i)
s_wren_i : IN std_logic := 'X'; -- user data write enable
s_do_valid_o : OUT std_logic; -- do_o data valid strobe, valid during one clk_i rising edge.
s_do_o : OUT std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i)
----- debug -----
s_do_transfer_o : OUT std_logic; -- debug: internal transfer driver
s_wren_o : OUT std_logic;
s_wren_ack_o : OUT std_logic;
s_rx_bit_reg_o : OUT std_logic;
s_state_dbg_o : OUT std_logic_vector (5 downto 0) -- debug: internal state register
-- s_sh_reg_dbg_o : OUT std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_loopback;
architecture Structural of spi_loopback is
begin
--=============================================================================================
-- Component instantiation for the SPI master port
--=============================================================================================
Inst_spi_master: entity work.spi_master(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
port map(
sclk_i => m_clk_i, -- system clock is used for serial and parallel ports
pclk_i => m_clk_i,
rst_i => m_rst_i,
spi_ssel_o => m_spi_ssel_o,
spi_sck_o => m_spi_sck_o,
spi_mosi_o => m_spi_mosi_o,
spi_miso_i => m_spi_miso_i,
di_req_o => m_di_req_o,
di_i => m_di_i,
wren_i => m_wren_i,
do_valid_o => m_do_valid_o,
do_o => m_do_o,
----- debug -----
do_transfer_o => m_do_transfer_o,
wren_o => m_wren_o,
wren_ack_o => m_wren_ack_o,
rx_bit_reg_o => m_rx_bit_reg_o,
state_dbg_o => m_state_dbg_o,
core_clk_o => m_core_clk_o,
core_n_clk_o => m_core_n_clk_o,
sh_reg_dbg_o => m_sh_reg_dbg_o
);
--=============================================================================================
-- Component instantiation for the SPI slave port
--=============================================================================================
Inst_spi_slave: entity work.spi_slave(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH)
port map(
clk_i => s_clk_i,
spi_ssel_i => s_spi_ssel_i,
spi_sck_i => s_spi_sck_i,
spi_mosi_i => s_spi_mosi_i,
spi_miso_o => s_spi_miso_o,
di_req_o => s_di_req_o,
di_i => s_di_i,
wren_i => s_wren_i,
do_valid_o => s_do_valid_o,
do_o => s_do_o,
----- debug -----
do_transfer_o => s_do_transfer_o,
wren_o => s_wren_o,
wren_ack_o => s_wren_ack_o,
rx_bit_reg_o => s_rx_bit_reg_o,
state_dbg_o => s_state_dbg_o
-- sh_reg_dbg_o => s_sh_reg_dbg_o
);
end Structural;
| gpl-3.0 |
ASP-SoC/ASP-SoC | libASP/grpAudioCodec/unitAudioCodecAvalon/hdl/AudioCodecAvalon-e.vhd | 1 | 1322 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AudioCodecAvalon is
generic (
gDataWidth : natural := 24; -- Avalon ST interface Datawidth
gDataWidthLen : natural := 5 -- Number of bits to represent gDataWidth
);
port (
-- clk and reset
csi_clk : in std_logic; -- clk
rsi_reset_n : in std_logic; -- low active reset
-- audio codec interface
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : in std_logic;
AUD_BCLK : in std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : in std_logic;
-- Avalon ST sink left and right channel
asi_left_data : in std_logic_vector(gDataWidth-1 downto 0); -- data
asi_left_valid : in std_logic; -- valid
asi_right_data : in std_logic_vector(gDataWidth-1 downto 0); -- data
asi_right_valid : in std_logic; -- valid
-- Avalon ST source left and right channel
aso_left_data : out std_logic_vector(gDataWidth-1 downto 0); -- data
aso_left_valid : out std_logic; -- valid
aso_right_data : out std_logic_vector(gDataWidth-1 downto 0); -- data
aso_right_valid : out std_logic -- valid
);
end entity;
| gpl-3.0 |
ASP-SoC/ASP-SoC | libASP/grpPrimitives/unitMultiply/hdl/tbMultiply-Bhv-ea.vhd | 1 | 4573 | -------------------------------------------------------------------------------
-- Title : Multiply
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : Unit Multiply multiplies L and R channel with a factor
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_pkg.all;
use work.Global.all;
use work.sin_4096.all;
entity tbMultiply is
end entity tbMultiply;
architecture bhv of tbMultiply is
--constant strobe_time : time := 1 sec/real(44117);
constant strobe_time : time := 200 ns;
constant data_width_g : natural := 24;
constant left_fact : real := 0.5;
constant right_fact : real := 0.5;
subtype audio_data_t is u_sfixed(0 downto -(data_width_g-1));
signal csi_clk : std_logic := '1';
signal rsi_reset_n : std_logic;
signal avs_s0_write : std_logic;
signal avs_s0_address : std_logic;
signal avs_s0_writedata : std_logic_vector(31 downto 0) := (others => '0');
signal asi_left_data : std_logic_vector(data_width_g-1 downto 0);
signal asi_left_valid : std_logic;
signal asi_right_data : std_logic_vector(data_width_g-1 downto 0);
signal asi_right_valid : std_logic;
signal aso_left_data : std_logic_vector(data_width_g-1 downto 0);
signal aso_left_valid : std_logic;
signal aso_right_data : std_logic_vector(data_width_g-1 downto 0);
signal aso_right_valid : std_logic;
signal left_data : audio_data_t;
signal right_data : audio_data_t;
-- test time
constant test_time_c : time := 20 ns;
-- audio data
signal sample_strobe, strobe2 : std_ulogic := '0';
signal audio_data : u_sfixed(0 downto -(data_width_g-1)) := (others => '0');
begin
DUT : entity work.Multiply
generic map (
data_width_g => data_width_g)
port map (
csi_clk => csi_clk,
rsi_reset_n => rsi_reset_n,
avs_s0_write => avs_s0_write,
avs_s0_address => avs_s0_address,
avs_s0_writedata => avs_s0_writedata,
asi_left_data => asi_left_data,
asi_left_valid => asi_left_valid,
asi_right_data => asi_right_data,
asi_right_valid => asi_right_valid,
aso_left_data => aso_left_data,
aso_left_valid => aso_left_valid,
aso_right_data => aso_right_data,
aso_right_valid => aso_right_valid);
left_data <= to_sfixed(aso_left_data, 0, -(data_width_g-1));
right_data <= to_sfixed(aso_right_data, 0, -(data_width_g-1));
-- clk generation
csi_clk <= not csi_clk after 10 ns;
-- sample strobe generation
strobe : process is
begin -- process
wait for strobe_time;
wait until rising_edge(csi_clk);
sample_strobe <= '1';
wait until rising_edge(csi_clk);
sample_strobe <= '0';
end process;
strobe_2 : process is
begin
wait until sample_strobe = '1';
wait until rising_edge(csi_clk);
strobe2 <= '1';
wait until rising_edge(csi_clk);
strobe2 <= '0';
end process strobe_2;
-- sinus as audio data
aud_data : process is
begin -- process
for idx in 0 to sin_table_c'length-1 loop
wait until rising_edge(sample_strobe);
audio_data <= to_sfixed(sin_table_c(idx), 0, -(data_width_g-1));
end loop; -- idx
end process aud_data;
-- channel left and right with sinus
--asi_right_data <= to_slv(to_sfixed(real(0.5), 0, -(data_width_g-1)));
asi_right_data <= to_slv(audio_data);
asi_left_data <= to_slv(audio_data);
asi_right_valid <= sample_strobe;
asi_left_valid <= sample_strobe;
test_process : process is
begin -- process
rsi_reset_n <= '0' after 0 ns,
'1' after 40 ns;
avs_s0_write <= '0';
wait for 100 ns;
-- write factors
-- left
avs_s0_address <= '0';
avs_s0_writedata(data_width_g-1 downto 0) <= to_slv(to_sfixed(left_fact, 0, -(data_width_g-1)));
avs_s0_write <= '1';
wait for 20 ns;
avs_s0_write <= '0';
wait for 20 ns;
-- right
avs_s0_address <= '1';
avs_s0_writedata(data_width_g-1 downto 0) <= to_slv(to_sfixed(right_fact, 0, -(data_width_g-1)));
avs_s0_write <= '1';
wait for 20 ns;
avs_s0_write <= '0';
wait;
end process;
end architecture bhv;
| gpl-3.0 |
ASP-SoC/ASP-SoC | libASP/grpDsp/unitAddChannels/hdl/AddChannels-ea.vhd | 1 | 4089 | -------------------------------------------------------------------------------
-- Title : Add Channels
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : Scale Channels with an factor and add
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use work.Global.all;
entity AddChannels is
generic (
-- audio data width
data_width_g : natural := 24;
-- scale factor, because the additon can cause an overflow
fact_a_g : real := 0.5;
fact_b_g : real := 0.5
);
port (
-- clk and reset
csi_clk : in std_logic;
rsi_reset_n : in std_logic;
-- Avalon MM Slave Port s0 - used for config parameters
-- config register width = 2 bit
-- "00" pass channel a
-- "01" pass channel b
-- "10" sum of channel a + channel b
-- "11" mute
avs_s0_write : in std_logic;
avs_s0_writedata : in std_logic_vector(31 downto 0);
-- Avalon ST sink left and right channel
asi_a_data : in std_logic_vector(data_width_g-1 downto 0);
asi_a_valid : in std_logic;
asi_b_data : in std_logic_vector(data_width_g-1 downto 0);
asi_b_valid : in std_logic;
-- Avalon ST source a, b, a+b or mute
aso_data : out std_logic_vector(data_width_g-1 downto 0);
aso_valid : out std_logic
);
end entity AddChannels;
architecture Rtl of AddChannels is
subtype audio_data_t is u_sfixed(0 downto -(data_width_g-1));
subtype result_t is u_sfixed(1 downto 2*(-(data_width_g-1)));
-- channel a and b
signal ch_a, ch_b : audio_data_t;
signal res : audio_data_t;
-- config register
subtype config_t is std_ulogic_vector(1 downto 0);
signal config : config_t;
constant pass_a_c : config_t := "00";
constant pass_b_c : config_t := "01";
constant sum_a_b_c : config_t := "10";
constant mute_c : config_t := "11";
begin -- architecture Rtl
-- MM INTERFACE for configuration
SetConfigReg : process (csi_clk, rsi_reset_n) is
begin
if rsi_reset_n = not('1') then -- low active reset
config <= (others => '0');
elsif rising_edge(csi_clk) then -- rising
if avs_s0_write = '1' then
config <= to_stdulogicvector(avs_s0_writedata(config'range));
end if;
end if;
end process;
-- convert avalon stream to sfixed format
ch_b <= to_sfixed(asi_b_data, ch_b);
-- store channel a in an register
store_ch_a : process (csi_clk, rsi_reset_n) is
begin -- process store_ch_a
if rsi_reset_n = '0' then -- asynchronous reset (active low)
ch_a <= (others => '0');
elsif rising_edge(csi_clk) then -- rising clock edge
if asi_a_valid = '1' then -- channel a valid
-- convert avalon stream to sfixed format
ch_a <= to_sfixed(asi_a_data, ch_a);
end if;
end if;
end process store_ch_a;
-- scale channels and add when channel b is valid
scale_add : process (ch_a, ch_b) is
variable a_scaled, b_scaled : result_t := (others => '0');
begin -- process
a_scaled := ch_a * fact_a_g;
b_scaled := ch_b * fact_b_g;
res <= resize(a_scaled + b_scaled, 0, -(data_width_g-1));
end process;
-- convert result to avalon stream
out_mux : process (asi_a_data, asi_a_valid, asi_b_data, asi_b_valid, config,
res) is
begin -- process out_mux
case config is
when pass_a_c =>
aso_data <= asi_a_data;
aso_valid <= asi_a_valid;
when pass_b_c =>
aso_data <= asi_b_data;
aso_valid <= asi_b_valid;
when sum_a_b_c =>
aso_data <= to_slv(res);
aso_valid <= asi_b_valid;
when mute_c =>
aso_data <= to_slv(silence_c);
aso_valid <= asi_a_valid;
when others =>
aso_data <= (others => 'X');
aso_valid <= 'X';
end case;
end process out_mux;
end architecture Rtl;
| gpl-3.0 |
ASP-SoC/ASP-SoC | libASP/grpStream/unitChannelMux/hdl/tbChannelMux-Bhv-ea.vhd | 1 | 4980 | -------------------------------------------------------------------------------
-- Title : Channel Mux
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : Unit Mux left and right channel
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity tbChannelMux is
end entity tbChannelMux;
architecture bhv of tbChannelMux is
constant gDataWidth : natural := 4;
signal csi_clk : std_logic := '1';
signal rsi_reset_n : std_logic;
signal avs_s0_write : std_logic;
signal avs_s0_writedata : std_logic_vector(31 downto 0) := (others => '0');
signal asi_left_data : std_logic_vector(gDataWidth-1 downto 0);
signal asi_left_valid : std_logic;
signal asi_right_data : std_logic_vector(gDataWidth-1 downto 0);
signal asi_right_valid : std_logic;
signal aso_left_data : std_logic_vector(gDataWidth-1 downto 0);
signal aso_left_valid : std_logic;
signal aso_right_data : std_logic_vector(gDataWidth-1 downto 0);
signal aso_right_valid : std_logic;
-- test time
constant test_time_c : time := 20 ns;
-- testcases
type testcase_t is record
func : std_logic_vector(3 downto 0);
r_data : std_logic_vector(gDataWidth-1 downto 0);
l_data : std_logic_vector(gDataWidth-1 downto 0);
r_valid : std_logic;
l_valid : std_logic;
exp_r_d : std_logic_vector(gDataWidth-1 downto 0);
exp_l_d : std_logic_vector(gDataWidth-1 downto 0);
exp_r_val : std_logic;
exp_l_val : std_logic;
end record;
-- test vector
type test_array_t is array (natural range<>) of testcase_t;
constant testcases : test_array_t := (
-- straight
("0000", "0101", "1010", '1', '0', "0101", "1010", '1', '0'),
-- cross R and L
("0001", "0101", "1010", '1', '0', "1010", "0101", '0', '1'),
-- silence left and straight
("1000", "0101", "1010", '1', '0', "0101", "0000", '1', '0'),
-- silence right and straight
("0100", "0101", "1010", '1', '0', "0000", "1010", '1', '0'),
-- silence R and L and straight
("1100", "0101", "1010", '1', '0', "0000", "0000", '1', '0'),
-- silence R and L and cross
("1101", "0101", "1010", '1', '0', "0000", "0000", '0', '1'),
-- both L
("0010", "0101", "1010", '1', '0', "1010", "1010", '0', '0'),
-- both L and silence L
("1010", "0101", "1010", '1', '0', "0000", "0000", '0', '0'),
-- both R
("0011", "0101", "1010", '1', '0', "0101", "0101", '1', '1'),
-- both R and silence R
("0111", "0101", "1010", '1', '0', "0000", "0000", '1', '1')
);
begin
DUT : entity work.ChannelMux
generic map (
gDataWidth => gDataWidth)
port map (
csi_clk => csi_clk,
rsi_reset_n => rsi_reset_n,
avs_s0_write => avs_s0_write,
avs_s0_writedata => avs_s0_writedata,
asi_left_data => asi_left_data,
asi_left_valid => asi_left_valid,
asi_right_data => asi_right_data,
asi_right_valid => asi_right_valid,
aso_left_data => aso_left_data,
aso_left_valid => aso_left_valid,
aso_right_data => aso_right_data,
aso_right_valid => aso_right_valid);
-- clk generation
csi_clk <= not csi_clk after 10 ns;
test_process : process is
-- test function
procedure test (
constant testcase : in testcase_t;
variable error_count : inout natural) is
begin -- test
-- inputs
asi_left_data <= testcase.l_data;
asi_left_valid <= testcase.l_valid;
asi_right_data <= testcase.r_data;
asi_right_valid <= testcase.r_valid;
avs_s0_write <= '1';
avs_s0_writedata(3 downto 0) <= testcase.func;
wait for 20 ns;
avs_s0_write <= '0';
wait for test_time_c;
-- check outputs
if (aso_left_data /= testcase.exp_l_d)
or (aso_right_data /= testcase.exp_r_d)
or (aso_left_valid /= testcase.exp_l_val)
or (aso_right_valid /= testcase.exp_r_val)then
assert false report
"tbChannelMux : Output not as expected !"
severity error;
error_count := error_count + 1;
end if;
end test;
-- error count
variable error_count_v : natural := 0;
begin -- process
rsi_reset_n <= '0' after 0 ns,
'1' after 10 ns;
wait for 20 ns;
for i in testcases'range loop
test(testcases(i), error_count_v);
end loop;
if error_count_v = 0 then
assert false report "tbChannelMux: test completed without errors, ending without failure." severity failure;
else
assert false report "tbChannelMux: test failed with " & integer'image(error_count_v) & " errors!" severity failure;
end if;
wait;
end process;
end architecture bhv;
| gpl-3.0 |
ASP-SoC/ASP-SoC | libASP/grpStream/unitMMtoST/hdl/MMtoST-ea.vhd | 1 | 13228 | -------------------------------------------------------------------------------
-- Title : Avalon MM to Avalon ST
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : Memory Mapped Slave to Avalon Streaming with Left and Right Channel
-- Used to stream audio data from the soc linux to the fpga
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MMtoST is
generic (
data_width_g : natural := 24;
fifo_depth_g : natural := 128;
fifo_adr_width_g : natural := 8 -- log2(fifo_depth_g) , at least 4
);
port (
csi_clk : in std_logic;
rsi_reset_n : in std_logic;
-- memory mapped interface s0
avs_s0_chipselect : in std_logic;
avs_s0_write : in std_logic;
avs_s0_read : in std_logic;
avs_s0_address : in std_logic_vector(1 downto 0);
avs_s0_writedata : in std_logic_vector(31 downto 0);
avs_s0_readdata : out std_logic_vector(31 downto 0);
-- interrupt sender
irs_irq : out std_logic;
-- avalon streaming left and right channel
asi_left_valid : in std_logic;
asi_left_data : in std_logic_vector(data_width_g-1 downto 0);
asi_right_valid : in std_logic;
asi_right_data : in std_logic_vector(data_width_g-1 downto 0);
aso_left_valid : out std_logic;
aso_left_data : out std_logic_vector(data_width_g-1 downto 0);
aso_right_valid : out std_logic;
aso_right_data : out std_logic_vector(data_width_g-1 downto 0)
);
end entity MMtoST;
architecture Rtl of MMtoST is
-- audio in registers
signal read_interrupt_en : std_ulogic;
signal clear_read_fifos : std_ulogic;
signal read_interrupt : std_ulogic;
-- audio out registers
signal write_interrupt_en : std_ulogic;
signal clear_write_fifos : std_ulogic;
signal write_interrupt : std_ulogic;
-- fifospace registers
signal left_channel_read_available : unsigned(fifo_adr_width_g-1 downto 0);
signal right_channel_read_available : unsigned(fifo_adr_width_g-1 downto 0);
signal left_channel_write_space : unsigned(fifo_adr_width_g-1 downto 0);
signal right_channel_write_space : unsigned(fifo_adr_width_g-1 downto 0);
-- audio signal
signal new_left_channel_audio : std_logic_vector(data_width_g-1 downto 0);
signal new_right_channel_audio : std_logic_vector(data_width_g-1 downto 0);
-- read and write strobes
signal rd_left : std_ulogic;
signal rd_right : std_ulogic;
signal wr_left : std_ulogic;
signal wr_right : std_ulogic;
-- fifo read stdulogicvector
signal asi_left_fifo_data : std_ulogic_vector(data_width_g-1 downto 0);
signal asi_right_fifo_data : std_ulogic_vector(data_width_g-1 downto 0);
signal aso_left_fifo_data : std_ulogic_vector(data_width_g-1 downto 0);
signal aso_right_fifo_data : std_ulogic_vector(data_width_g-1 downto 0);
-- fifo empty and full signals
signal asi_left_fifo_empty : std_ulogic;
signal asi_right_fifo_empty : std_ulogic;
signal aso_left_fifo_empty : std_ulogic;
signal aso_right_fifo_empty : std_ulogic;
signal asi_left_fifo_full : std_ulogic;
signal asi_right_fifo_full : std_ulogic;
signal aso_left_fifo_full : std_ulogic;
signal aso_right_fifo_full : std_ulogic;
-- fifo space
signal aso_left_fifo_space : unsigned(fifo_adr_width_g-1 downto 0);
signal aso_right_fifo_space : unsigned(fifo_adr_width_g-1 downto 0);
-- address constants
constant control_c : std_logic_vector(1 downto 0) := "00";
constant fifospace_c : std_logic_vector(1 downto 0) := "01";
constant leftdata_c : std_logic_vector(1 downto 0) := "10";
constant rightdata_c : std_logic_vector(1 downto 0) := "11";
begin -- architecture Rtl
-- interrupt sender register
irq_reg : process (csi_clk, rsi_reset_n) is
begin -- process irq_reg
if rsi_reset_n = '0' then -- asynchronous reset (active low)
irs_irq <= '0';
elsif rising_edge(csi_clk) then -- rising clock edge
irs_irq <= read_interrupt or write_interrupt;
end if;
end process irq_reg;
-- memory mapped read
mm_read : process (csi_clk, rsi_reset_n) is
begin -- process mm_read
if rsi_reset_n = '0' then -- asynchronous reset (active low)
avs_s0_readdata <= (others => '0');
elsif rising_edge(csi_clk) then -- rising clock edge
if avs_s0_chipselect = '1' then
-- default
avs_s0_readdata <= (others => '0');
-- select address
case avs_s0_address is
when control_c =>
avs_s0_readdata(31 downto 10) <= (others => '-');
avs_s0_readdata(9) <= write_interrupt;
avs_s0_readdata(8) <= read_interrupt;
avs_s0_readdata(7 downto 4) <= (others => '-');
avs_s0_readdata(3) <= clear_write_fifos;
avs_s0_readdata(2) <= clear_read_fifos;
avs_s0_readdata(1) <= write_interrupt_en;
avs_s0_readdata(0) <= read_interrupt_en;
when fifospace_c =>
avs_s0_readdata(31 downto 24) <= std_logic_vector(left_channel_write_space);
avs_s0_readdata(23 downto 16) <= std_logic_vector(right_channel_write_space);
avs_s0_readdata(15 downto 8) <= std_logic_vector(left_channel_read_available);
avs_s0_readdata(7 downto 0) <= std_logic_vector(right_channel_read_available);
when leftdata_c =>
avs_s0_readdata(data_width_g-1 downto 0) <= new_left_channel_audio;
when rightdata_c =>
avs_s0_readdata(data_width_g-1 downto 0) <= new_right_channel_audio;
when others =>
avs_s0_readdata <= (others => 'X');
end case;
else
avs_s0_readdata <= (others => '0');
end if;
end if;
end process mm_read;
-- memory mapped write
mm_write : process (csi_clk, rsi_reset_n) is
begin -- process mm_write
if rsi_reset_n = '0' then -- asynchronous reset (active low)
read_interrupt_en <= '0';
write_interrupt_en <= '0';
clear_read_fifos <= '0';
clear_write_fifos <= '0';
elsif rising_edge(csi_clk) then -- rising clock edge
if avs_s0_chipselect = '1' and avs_s0_write = '1' then
case avs_s0_address is
when control_c =>
read_interrupt_en <= avs_s0_writedata(0);
write_interrupt_en <= avs_s0_writedata(1);
clear_read_fifos <= avs_s0_writedata(2);
clear_write_fifos <= avs_s0_writedata(3);
when leftdata_c =>
when rightdata_c =>
when others => null;
end case;
end if;
end if;
end process mm_write;
-- interrupt behavior
-- irq is set when the fifo is filled to 75% or more
-- when less it will be cleared
irq_bhv : process (csi_clk, rsi_reset_n) is
begin -- process irq_bhv
if rsi_reset_n = '0' then -- asynchronous reset (active low)
read_interrupt <= '0';
write_interrupt <= '0';
elsif rising_edge(csi_clk) then -- rising clock edge
-- read interrupt
if read_interrupt_en = '1' then
read_interrupt <= asi_left_fifo_full or asi_right_fifo_full
or left_channel_read_available(fifo_adr_width_g-1)
or (left_channel_read_available(fifo_adr_width_g-2) and left_channel_read_available(fifo_adr_width_g-3))
or right_channel_read_available(fifo_adr_width_g-1)
or (right_channel_read_available(fifo_adr_width_g-2) and right_channel_read_available(fifo_adr_width_g-3));
else
read_interrupt <= '0';
end if;
-- write interrupt
if write_interrupt_en = '1' then
write_interrupt <= aso_left_fifo_empty or aso_right_fifo_empty or
left_channel_write_space(fifo_adr_width_g-1)
or (left_channel_write_space(fifo_adr_width_g-2) and left_channel_write_space(fifo_adr_width_g-3))
or right_channel_write_space(fifo_adr_width_g-1)
or (right_channel_write_space(fifo_adr_width_g-2) and right_channel_write_space(fifo_adr_width_g-3));
else
write_interrupt <= '0';
end if;
end if;
end process irq_bhv;
-- combinatoric logic for read and write strobe
rd_wr_stb : process (avs_s0_address, avs_s0_chipselect, avs_s0_read, avs_s0_write) is
begin -- process rd_wr_stb
rd_left <= '0';
rd_right <= '0';
wr_left <= '0';
wr_right <= '0';
if avs_s0_chipselect = '1' then
case avs_s0_address is
when leftdata_c =>
if avs_s0_read = '1' then
rd_left <= '1';
end if;
if avs_s0_write = '1' then
wr_left <= '1';
end if;
when rightdata_c =>
if avs_s0_read = '1' then
rd_right <= '1';
end if;
if avs_s0_write = '1' then
wr_right <= '1';
end if;
when others => null;
end case;
end if;
end process rd_wr_stb;
-- st -> MM fifo
asi_left_fifo : entity work.FIFO
generic map (
data_width_g => data_width_g,
depth_g => fifo_depth_g,
adr_width_g => fifo_adr_width_g)
port map (
clk_i => csi_clk,
rst_i => rsi_reset_n,
wr_i => asi_left_valid,
rd_i => rd_left,
wr_data_i => to_StduLogicVector(asi_left_data),
rd_data_o => asi_left_fifo_data,
clear_i => clear_read_fifos,
full_o => asi_left_fifo_full,
empty_o => asi_left_fifo_empty,
space_o => left_channel_read_available);
new_left_channel_audio <= to_StdLogicVector(asi_left_fifo_data) when asi_left_fifo_empty = '0'
else (others => '0') when asi_left_fifo_empty = '1'
else (others => 'X');
-- st -> MM fifo
asi_right_fifo : entity work.FIFO
generic map (
data_width_g => data_width_g,
depth_g => fifo_depth_g,
adr_width_g => fifo_adr_width_g)
port map (
clk_i => csi_clk,
rst_i => rsi_reset_n,
wr_i => asi_right_valid,
rd_i => rd_right,
wr_data_i => to_StduLogicVector(asi_right_data),
rd_data_o => asi_right_fifo_data,
clear_i => clear_read_fifos,
full_o => asi_right_fifo_full,
empty_o => asi_right_fifo_empty,
space_o => right_channel_read_available);
new_right_channel_audio <= to_StdLogicVector(asi_right_fifo_data) when asi_right_fifo_empty = '0'
else (others => '0') when asi_right_fifo_empty = '1'
else (others => 'X');
-- MM -> st fifo
aso_left_fifo : entity work.FIFO
generic map (
data_width_g => data_width_g,
depth_g => fifo_depth_g,
adr_width_g => fifo_adr_width_g)
port map (
clk_i => csi_clk,
rst_i => rsi_reset_n,
wr_i => wr_left,
rd_i => asi_left_valid,
wr_data_i => to_stdulogicvector(avs_s0_writedata(data_width_g-1 downto 0)),
rd_data_o => aso_left_fifo_data,
clear_i => clear_write_fifos,
full_o => aso_left_fifo_full,
empty_o => aso_left_fifo_empty,
space_o => aso_left_fifo_space);
aso_left_data <= to_stdLogicVector(aso_left_fifo_data) when aso_left_fifo_empty = '0'
else (others => '0') when aso_left_fifo_empty = '1'
else (others => 'X');
-- calculate remaining space
left_channel_write_space <= fifo_depth_g - aso_left_fifo_space;
-- MM -> st fifo
aso_right_fifo : entity work.FIFO
generic map (
data_width_g => data_width_g,
depth_g => fifo_depth_g,
adr_width_g => fifo_adr_width_g)
port map (
clk_i => csi_clk,
rst_i => rsi_reset_n,
wr_i => wr_right,
rd_i => asi_right_valid,
wr_data_i => to_stdulogicvector(avs_s0_writedata(data_width_g-1 downto 0)),
rd_data_o => aso_right_fifo_data,
clear_i => clear_write_fifos,
full_o => aso_right_fifo_full,
empty_o => aso_right_fifo_empty,
space_o => aso_right_fifo_space);
aso_right_data <= to_stdLogicVector(aso_right_fifo_data) when aso_right_fifo_empty = '0'
else (others => '0') when aso_right_fifo_empty = '1'
else (others => 'X');
-- calculate remaining space
right_channel_write_space <= fifo_depth_g - aso_right_fifo_space;
-- delay valid with one clk cycle, because read needs one clk cycle
dly_valid : process (csi_clk, rsi_reset_n) is
begin -- process dly_valid
if rsi_reset_n = '0' then -- asynchronous reset (active low)
aso_left_valid <= '0';
aso_right_valid <= '0';
elsif rising_edge(csi_clk) then -- rising clock edge
aso_left_valid <= asi_left_valid;
aso_right_valid <= asi_right_valid;
end if;
end process dly_valid;
end architecture Rtl;
| gpl-3.0 |
ASP-SoC/ASP-SoC | libASP/grpPackages/pkgFixed/src/test_fixed_synth.vhdl | 2 | 16226 | -- Test vectors for the synthesis test for the fixed point math package
-- This test is designed to test fixed_synth and exercise much of the entity.
-- Created for vhdl-200x by David Bishop ([email protected])
-- --------------------------------------------------------------------
-- modification history : Last Modified $Date: 2006-06-08 10:55:54-04 $
-- Version $Id: test_fixed_synth.vhdl,v 1.1 2006-06-08 10:55:54-04 l435385 Exp $
-- --------------------------------------------------------------------
entity test_fixed_synth is
generic (
quiet : boolean := false); -- make the simulation quiet
end entity test_fixed_synth;
library ieee, ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_pkg.all;
architecture testbench of test_fixed_synth is
procedure report_error (
constant errmes : in string; -- error message
actual : in sfixed; -- data from algorithm
constant expected : in sfixed) is -- reference data
begin -- function report_error
assert actual = expected
report errmes & CR
& "Actual: " & to_string(actual)
& " (" & real'image(to_real(actual)) & ")" & CR
& " /= " & to_string(expected)
& " (" & real'image(to_real(expected)) & ")"
severity error;
return;
end procedure report_error;
-- Device under test. Note that all inputs and outputs are std_logic_vector.
-- This entity can be use both pre and post synthesis.
component fixed_synth is
port (
in1, in2 : in std_logic_vector (15 downto 0); -- inputs
out1 : out std_logic_vector (15 downto 0); -- output
cmd : in std_logic_vector (3 downto 0);
clk, rst_n : in std_ulogic); -- clk and reset
end component fixed_synth;
constant clock_period : time := 500 ns; -- clock period
subtype sfixed7 is sfixed (3 downto -3); -- 7 bit
subtype sfixed16 is sfixed (7 downto -8); -- 16 bit
signal stop_clock : boolean := false; -- stop the clock
signal clk, rst_n : std_ulogic; -- clk and reset
signal in1slv, in2slv, out1slv : std_logic_vector(15 downto 0);
signal in1, in2 : sfixed16; -- inputs
signal out1 : sfixed16; -- output
signal cmd : std_logic_vector (3 downto 0); -- command string
begin -- architecture testbench
-- From fixed point to Std_logic_vector
in1slv <= to_slv(in1);
in2slv <= to_slv(in2);
-- Std_logic_vector to fixed point.
out1 <= to_sfixed(out1slv, out1'high, out1'low);
DUT: fixed_synth
port map (
in1 => in1slv, -- [in std_logic_vector (15 downto 0)] inputs
in2 => in2slv, -- [in std_logic_vector (15 downto 0)] inputs
out1 => out1slv, -- [out std_logic_vector (15 downto 0)] output
cmd => cmd, -- [in std_logic_vector (2 downto 0)]
clk => clk, -- [in std_ulogic] clk and reset
rst_n => rst_n); -- [in std_ulogic] clk and reset
-- purpose: clock driver
clkprc: process is
begin -- process clkprc
if (not stop_clock) then
clk <= '0';
wait for clock_period/2.0;
clk <= '1';
wait for clock_period/2.0;
else
wait;
end if;
end process clkprc;
-- purpose: reset driver
reset_proc: process is
begin -- process reset_proc
rst_n <= '0';
wait for clock_period * 2.0;
rst_n <= '1';
wait;
end process reset_proc;
-- purpose: main test loop
tester: process is
begin -- process tester
cmd <= "0000"; -- add mode
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0001"; -- subtract mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0010"; -- multiply mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0011"; -- divide
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (-0.5, sfixed16'high, sfixed16'low); -- -0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
cmd <= "0100"; -- unsigned add
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0101"; -- subtract mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0110"; -- multiply mode
in1 <= "0000011010000000"; -- 6.5
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0100"; -- add mode
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);
in2 <= "0000001100000000"; -- 3
wait for clock_period;
cmd <= "0111"; -- divide
in1 <= "0000000010000000"; -- 0.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
in1 <= to_sfixed (6.5, sfixed16'high, sfixed16'low); -- 6.5
in2 <= "0000000010000000"; -- 0.5
wait for clock_period;
-- resize
cmd <= "1000";
in1 <= to_sfixed (5.25, in1);
in2 <= to_sfixed (-5.25, in2);
wait for clock_period;
in1 <= to_sfixed (21.125, in1);
in2 <= to_sfixed (21.125, in2);
wait for clock_period;
in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');
cmd <= "1001"; -- SIGNED
in1 <= to_sfixed (6.25, in1);
wait for clock_period;
in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');
cmd <= "1001"; -- UNSIGNED
in1 <= to_sfixed (7.25, in1);
wait for clock_period;
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
cmd <= "1001"; -- SIGNED
in1 <= to_sfixed (6.25, in1);
wait for clock_period;
in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');
cmd <= "1001"; -- UNSIGNED
in1 <= to_sfixed (7.25, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');
in1 <= to_sfixed (3, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');
in1 <= to_sfixed (5, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
in1 <= to_sfixed (-5.5, in1);
wait for clock_period;
cmd <= "1010";
in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');
in1 <= to_sfixed (7.25, in1);
wait for clock_period;
cmd <= "1010"; -- abs (mod)
in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');
in1 <= to_sfixed (-42, in1);
wait for clock_period;
cmd <= "1011"; -- mod
in1 <= to_sfixed (6.25, in1);
in2 <= to_sfixed (6, in2);
wait for clock_period;
cmd <= "1100"; -- REM
in1 <= to_sfixed (6.25, in1);
in2 <= to_sfixed (6, in2);
wait for clock_period;
cmd <= "1101"; -- srl
in1 <= to_sfixed (5.25, in1);
in2 <= to_sfixed (-1, in2);
wait for clock_period;
cmd <= "1110"; -- sra
in1 <= to_sfixed (-7.25, in1);
in2 <= to_sfixed (1, in2);
wait for clock_period;
cmd <= "1111"; -- compare
in1 <= to_sfixed (42, in1);
in2 <= to_sfixed (42, in1);
wait for clock_period;
in1 <= to_sfixed (45, in1);
in2 <= to_sfixed (90, in1);
wait for clock_period;
in1 <= to_sfixed (3.125, in1);
in2 <= (others => '0');
wait for clock_period;
in1 <= "0110111110101111";
in2 <= "1111111111111111";
wait for clock_period;
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
in1 <= "0000111000000000";
in2 <= "0000111000000000";
wait for clock_period;
in1 <= (others => '1');
in2 <= (others => '1');
wait for clock_period;
wait for clock_period;
wait for clock_period;
cmd <= "0000"; -- add mode
in1 <= (others => '0');
in2 <= (others => '0');
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait;
end process tester;
-- purpose: check the output of the tester
-- type : combinational
-- inputs :
-- outputs:
checktest: process is
constant fxzero : sfixed16 := (others => '0'); -- zero
variable chks16 : sfixed16; -- variable
variable sm1, sm2 : sfixed7; -- small fixed point
begin -- process checktest
wait for clock_period/2.0;
wait for clock_period;
wait for clock_period;
waitloop: while (out1 = fxzero) loop
wait for clock_period;
end loop waitloop;
chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);
report_error ( "3.0 + 6.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 - 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 * 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);
report_error ( "0.5 + 0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);
report_error ( "3.14 + 3 error",
out1,
chks16);
wait for clock_period;
chks16 := "0000000100000000";
report_error ( "0.5/0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (-1, sfixed16'high, sfixed16'low);
report_error ( "-0.5/0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);
report_error ( "3.0 + 6.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 - 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);
report_error ( "6.5 * 3.0 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);
report_error ( "0.5 + 0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);
report_error ( "3.14 + 3 error",
out1,
chks16);
wait for clock_period;
chks16 := "0000000100000000";
report_error ( "0.5/0.5 error",
out1,
chks16);
wait for clock_period;
chks16 := to_sfixed (13, sfixed16'high, sfixed16'low);
report_error ( "6.5/0.5 error",
out1,
chks16);
wait for clock_period;
-- resize test
sm1 := out1 (7 downto 1);
sm2 := to_sfixed (5.25, sm2);
report_error ( "resize 1 error", sm1, sm2);
sm1 := out1 (-1 downto -7);
sm2 := to_sfixed (-5.25, sm2);
report_error ( "resize 2 error", sm1, sm2);
wait for clock_period;
sm1 := out1 (7 downto 1);
sm2 := "0101001"; -- wrapped
-- sm2 := to_sfixed (21.125, sm2, 0, false, false); -- wrap, no round
report_error ( "resize 1 error", sm1, sm2);
sm1 := out1 (-1 downto -7);
sm2 := "0111111"; -- saturate
report_error ( "resize 2 error", sm1, sm2);
wait for clock_period;
-- to_signed and back
report_error ("to_signed(6.25)", out1, to_sfixed (6, out1));
wait for clock_period;
-- to_unsigned and back
report_error ("to_unsigned(7.25)", out1, to_sfixed (7, out1));
wait for clock_period;
-- to_integer and back
report_error ("to_signed(6.25)", out1, to_sfixed (6, out1));
wait for clock_period;
-- to_integer(ufixed) and back
report_error ("to_unsigned(7.25)", out1, to_sfixed (7, out1));
wait for clock_period;
report_error ("1/3", out1, to_sfixed (1.0/3.0, out1'high, -7));
wait for clock_period;
report_error ("unsigned 1/5", out1, to_sfixed (1.0/5.0, out1));
wait for clock_period;
report_error ("abs (-5.5)", out1, to_sfixed (5.5, out1));
wait for clock_period;
report_error ("-7.25", out1, to_sfixed (-7.25, out1));
wait for clock_period;
report_error ("abs(-42)", out1, to_sfixed (42, out1));
wait for clock_period;
report_error ("6.25 mod 6", out1, to_sfixed (0.25, out1));
wait for clock_period;
report_error ("6.25 rem 6", out1, to_sfixed (0.25, out1));
wait for clock_period;
chks16 := "0000101010000000";
report_error ("5.25 srl -1", out1, chks16);
wait for clock_period;
chks16 := "1111110001100000";
report_error ("-7.25 sra 1", out1, chks16);
wait for clock_period;
-- 7654321012345678
chks16 := "0111000000110001";
assert (std_match (out1, chks16))
report "42=42 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
chks16 := "------0001010110";
assert (std_match (out1, chks16))
report "45=90 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
chks16 := "------1010101010";
assert (std_match (out1, chks16))
report "3.125=0 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "0--1010000101010";
assert (std_match (out1, chks16))
report "pattern1 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "0001100000110001";
assert (std_match (out1, chks16))
report "zero = zero " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "1111000000110001";
assert (std_match (out1, chks16))
report "pattern2 compare " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
-- 7654321012345678
chks16 := "0111000000110001";
assert (std_match (out1, chks16))
report "-1 = -1 " & CR
& "Actual " & to_string(out1) & CR
& "Expected " & to_string(chks16) severity error;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
wait for clock_period;
assert (false) report "Testing complete" severity note;
stop_clock <= true;
wait;
end process checktest;
end architecture testbench;
| gpl-3.0 |
lvd2/ngs | fpga/current/dma/modelsim/T80_Pack.vhd | 7 | 8485 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;
| gpl-3.0 |
lvd2/ngs | fpga/obsolete/fpgaF_dma2/dma/sim_models/T80_Pack.vhd | 7 | 8485 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;
| gpl-3.0 |
lvd2/ngs | fpga/obsolete/fpgaF_dma2/dma/modelsim/t80.vhd | 7 | 31904 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed wait and halt
--
-- 0211 : Fixed Refresh addition and IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
--
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end T80;
architecture rtl of T80 is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_INRC : std_logic;
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
begin
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
TmpAddr <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
elsif CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= TmpAddr;
PC <= unsigned(TmpAddr);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= TmpAddr;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
end if;
when aDE =>
A <= RegBusC;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(TmpAddr) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
TmpAddr <= (others =>'0');
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusB <= "--------";
end case;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or
(MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
| gpl-3.0 |
abcsds/RS232 | RS232Write/RS232Write.vhd | 2 | 1440 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity RS232Write is
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
DATAWR : in std_logic_vector(7 downto 0);
NBaud : in std_logic_vector(3 downto 0);
EOT : out std_logic;
Tx : out std_logic
);
end RS232Write;
architecture moore of RS232Write is
signal CTRL : std_logic_vector(3 downto 0);
signal FBaud : std_logic;
component BaudRate
port(
RST : in std_logic;
CLK : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end component;
component RightShift
port(
RST : in std_logic;
CLK : in std_logic;
CTRL : in std_logic_vector(3 downto 0);
DATAWR : in std_logic_vector(7 downto 0);
Tx : out std_logic
);
end component;
component FsmWrite
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
FBaud : in std_logic;
EOT : out std_logic;
CTRL : out std_logic_vector(3 downto 0)
);
end component;
begin
U00 : BaudRate port map(RST,CLK,NBaud,FBaud);
U01 : RightShift port map(RST,CLK,CTRL,DATAWR,Tx);
U02 : FsmWrite port map(RST,CLK,STR,FBaud,EOT,CTRL);
end moore;
| gpl-3.0 |
ARC-Lab-UF/volunteer_files | fifo_vw_tb.vhd | 1 | 7609 | -- fifo_vw testbench
-- Greg Stitt
-- University of Florida
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
use work.tb_pkg.all;
entity fifo_vw_tb is
generic(
parallel_io : positive := 4;
data_width : positive := 8;
test_size : positive := 400;
input_delay_prob : real range 0.0 to 1.0 := 0.1;
min_input_delay : natural := 1;
max_input_delay : natural := 10;
output_delay_prob : real range 0.0 to 1.0 := 0.0;
min_output_delay : natural := 1;
max_output_delay : natural := 10
);
end fifo_vw_tb;
architecture TB of fifo_vw_tb is
-- ensure that that input size is a multiple of parallel_io. This will
-- round up test_size to the next multiple
constant adjusted_input_size : integer := integer(ceil(real(test_size) / real(parallel_io)))*parallel_io;
type data_array is array (0 to adjusted_input_size-1) of std_logic_vector(data_width-1 downto 0);
signal input_array : data_array;
signal output_array : data_array;
signal clk_en : std_logic := '1';
signal clk, rst, rd, wr : std_logic := '0';
signal empty, full : std_logic;
signal wr_amount : std_logic_vector(bitsNeeded(parallel_io)-1 downto 0) := (others => '0');
signal valid_count : std_logic_vector(bitsNeeded(parallel_io)-1 downto 0) := (others => '0');
signal input : std_logic_vector(parallel_io*data_width-1 downto 0) := (others => '0');
signal output : std_logic_vector(parallel_io*data_width-1 downto 0);
signal input_ready : std_logic := '0';
signal output_ready : std_logic := '0';
signal input_done : std_logic := '0';
signal all_outputs : boolean := false;
type count_array is array (0 to adjusted_input_size-1) of integer;
signal counts : count_array;
signal stall : std_logic := '0';
begin
U_FIFO_VW : entity work.fifo_vw
generic map(
data_width => data_width,
parallel_io => parallel_io)
port map(
clk => clk,
rst => rst,
rd => rd,
wr => wr,
valid_count => valid_count,
empty => empty,
full => full,
input => input,
output => output
);
clk <= not clk after 10 ns when clk_en = '1' else '0';
-- determine when to write
process(full, input_ready, rst, input_done)
begin
-- input_ready includes random delays
wr <= input_ready and not full and not rst and not input_done;
end process;
-- set the inputs during a write
process(clk, wr, rst)
variable input_count : integer := 0;
begin
if (rst = '1') then
input_count := 0;
for j in 0 to parallel_io-1 loop
input((parallel_io-j)*data_width-1 downto (parallel_io-j-1)*data_width) <= input_array(j);
end loop;
-- set the inputs for each write
elsif (rising_edge(clk) and wr = '1' and rst = '0') then
input_count := input_count + to_integer(unsigned(valid_count));
-- write valid_count elements into the fifo
for j in 0 to parallel_io-1 loop
if (input_count + j < adjusted_input_size) then
input((parallel_io-j)*data_width-1 downto (parallel_io-j-1)*data_width) <= input_array(input_count + j);
end if;
end loop;
if (input_count = adjusted_input_size) then
input_done <= '1';
end if;
end if;
end process;
-- randomly vary write timings
process
variable s1, s2 : positive; -- seeds for rand function
begin
input_ready <= '0';
wait until rst = '0';
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
while (input_done = '0') loop
input_ready <= '0';
--randomize a delay so that the fifo can drain and reads larger than whats in the buffer can be tested
randDelay(s1, s2, clk, input_delay_prob, min_input_delay, max_input_delay);
input_ready <= '1';
wait until rising_edge(clk);
end loop;
input_ready <= '0';
wait;
end process;
-- initialize the simulation
process
variable rand : integer; -- random inputs to be written to fifo
variable s1, s2 : positive; -- seeds for rand function
variable input_count : integer;
begin
-- initialize inputs
for i in 0 to adjusted_input_size-1 loop
-- randomInt(s1, s2, 0, 2**data_width-1, rand);
-- input_array(i) <= std_logic_vector(to_unsigned(rand, data_width));
input_array(i) <= std_logic_vector(to_unsigned(i, data_width));
end loop;
--Reset the entity and initialize the wr and input to zero
rst <= '1';
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
rst <= '0';
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
wait;
end process;
-- randomly vary read timings
vary_read_timing : process
variable s1, s2 : positive; -- seeds for rand function
begin
while (not all_outputs) loop
output_ready <= '0';
--randomize a delay so that the fifo can drain and reads larger than whats in the buffer can be tested
randDelay(s1, s2, clk, output_delay_prob, min_output_delay, max_output_delay);
output_ready <= '1';
wait until rising_edge(clk);
end loop;
wait;
end process;
-- determine when reads occur
process(empty, output_ready)
begin
rd <= not empty and output_ready;
end process;
-- set write amounts
write_amounts : process(clk, rst)
variable s1, s2 : positive;
variable wr_amount_v : integer;
begin
if (rst = '1') then
randomInt(s1, s2, 0, parallel_io+1, wr_amount_v);
valid_count <= std_logic_vector(to_unsigned(wr_amount_v, valid_count'length));
elsif (rising_edge(clk) and wr = '1') then
randomInt(s1, s2, 0, parallel_io+1, wr_amount_v);
valid_count <= std_logic_vector(to_unsigned(wr_amount_v, valid_count'length));
end if;
end process;
check_outputs : process(clk)
variable out_ind_count : integer := 0;
variable output_temp : std_logic_vector(data_width-1 downto 0) := (others => '0');
begin
-- if there is a valid output, verify it
if (rising_edge(clk) and rd = '1') then
-- check the outputs
for i in 0 to parallel_io-1 loop
output_temp := output((parallel_io-i)*data_width-1 downto (parallel_io-i-1)*data_width);
assert(output_temp = input_array(out_ind_count)) report "Output incorrect.";
out_ind_count := out_ind_count + 1;
end loop;
end if;
if (out_ind_count = adjusted_input_size) then
report "SIMULATION COMPLETE!!!";
clk_en <= '0';
end if;
end process;
end TB;
| gpl-3.0 |
abcsds/RS232 | RS232Write/BaudRate.vhd | 6 | 1850 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRate is
port(
RST : in std_logic;
CLK : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end BaudRate;
architecture simple of BaudRate is
signal Qp, Qn, NB : std_logic_vector(18 downto 0);
begin
COMB: process(NBaud,Qp)
begin
case NBaud is
when "0000"=>
NB<= "1101110111110010001"; -- 110 Bauds
when "0001"=>
NB<= "0101000101100001010"; -- 300 Bauds
when "0010"=>
NB<= "0010100010110000101"; -- 600 Bauds
when "0011"=>
NB<= "0001010001011000010"; -- 1200 Bauds
when "0100"=>
NB<= "0000101000101100001"; -- 2400 Bauds
when "0101"=>
NB<= "0000010100010110000"; -- 4800 Bauds
when "0110"=>
NB<= "0000001010001011000"; -- 9600 Bauds
when "0111"=>
NB<= "0000000110110010000"; -- 14400 Bauds
when "1000"=>
NB<= "0000000101000101100"; -- 19200 Bauds
when "1001"=>
NB<= "0000000010100010110"; -- 38400 Bauds
when "1010"=>
NB<= "0000000001101100100"; -- 57600 Bauds
when "1011"=>
NB<= "0000000000110110010"; -- 115200 Bauds
when "1100"=>
NB<= "0000000000110000110"; -- 128000 Bauds
when "1101"=>
NB<= "0000000000011000011"; -- 256000 Bauds
when others=>
NB<= "0000000000000000000"; -- 0 Bauds
end case;
if(Qp= "0000000000000000000")then
Qn<= NB;
FBaud<= '1';
else
Qn<= Qp-1;
FBaud<= '0';
end if;
end process COMB;
FF: process(RST,CLK)
begin
if(RST='0')then
Qp <= (others=>'0');
elsif(CLK'event and CLK='1') then
Qp <= Qn;
end if;
end process FF;
end simple;
| gpl-3.0 |
ARC-Lab-UF/volunteer_files | cache.vhd | 1 | 9725 | -- Greg Stitt
-- University of Florida
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
-------------------------------------------------------------------------------
-- Generics Description
-- num_sets : The number of sets in the cache.
-- word_width : The number of bits in a "word," where a word is the unit of
-- data read from and written to the cache.
-- words_per_block : The number of words in a block. (CURRENTLY NOT SUPPORTED)
-- addr_width : The number of bits in the address being looked up in the cache.
-- Must be >= clog2(num_blocks).
-- associativity : The number of blocks per set.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : Clock input
-- rst : Reset (active high)
-- en : Enable input (active high), stalls the pipeline when '0'
-- wr_addr : The address to write data to when handling a miss
-- wr_data : Input for providing data to the cache on a miss
-- wr_en : Assert to write wr_data to wr_addr in cache
-- rd_addr : The address to read from in the cache
-- rd_data : The output from the cache on a hit
-- rd_data_valid : Asserted when rd_data contains valid data. Will remain
-- asserted for 1 cycle unless en='0'
-- ready : Asserted (active high) when cache can accept new address requests.
-- When not asserted, all inputs are ignored.
-------------------------------------------------------------------------------
entity cache is
generic (
num_sets : positive := 16;
word_width : positive := 8;
words_per_block : positive := 1;
addr_width : positive := 16;
associativity : positive := 1);
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rd_addr : in std_logic_vector(addr_width-1 downto 0);
rd_en : in std_logic;
rd_data : out std_logic_vector(word_width-1 downto 0);
rd_data_valid : out std_logic;
ready : out std_logic;
-- Signals for handling misses
wr_addr : in std_logic_vector(addr_width-1 downto 0);
wr_data : in std_logic_vector(word_width*words_per_block-1 downto 0);
wr_way_id : in std_logic_vector(bitsNeeded(associativity)-1 downto 0);
wr_en : in std_logic;
miss : out std_logic;
miss_addr : out std_logic_vector(addr_width-1 downto 0);
miss_valid_ways : out std_logic_vector(associativity-1 downto 0)
);
end cache;
architecture default of cache is
constant DATA_WIDTH : positive := word_width*words_per_block;
constant TAG_WIDTH : positive := addr_width - bitsNeeded(num_sets);
subtype TAG_RANGE is natural range addr_width-1 downto addr_width-TAG_WIDTH;
constant BLOCK_WIDTH : positive := 1+TAG_WIDTH+DATA_WIDTH;
constant SET_WIDTH : positive := BLOCK_WIDTH*associativity;
--constant NUM_SETS : positive := integer(ceil(real(num_sets)/real(associativity)));
type block_array is array (associativity-1 downto 0) of std_logic_vector(BLOCK_WIDTH-1 downto 0);
signal ram_out : block_array;
signal way : block_array;
signal rd_addr_delayed : std_logic_vector(rd_addr'range);
signal rd_addr_r : std_logic_vector(rd_addr'range);
signal wr_data_complete : std_logic_vector(wr_data'length+TAG_WIDTH downto 0);
signal valid : std_logic_vector(associativity-1 downto 0);
signal way_tag_eq : std_logic_vector(associativity-1 downto 0);
signal way_hit : std_logic_vector(associativity-1 downto 0);
type way_data_array is array (associativity-1 downto 0) of std_logic_vector(data_width-1 downto 0);
signal way_data : way_data_array;
signal hit : std_logic;
signal request_valid : std_logic;
signal ready_s : std_logic;
signal miss_handled : std_logic;
signal data_ready : std_logic;
signal hit_r : std_logic;
signal hit_data : std_logic_vector(rd_data'range);
signal hit_data_r : std_logic_vector(rd_data'range);
signal way_wr_en : std_logic_vector(associativity-1 downto 0);
begin
assert(words_per_block = 1) severity failure;
-- Wwrite to the cache the valid bit, the tag, and the actual wr data
wr_data_complete <= '1' & wr_addr(TAG_RANGE) & wr_data;
-- RAM to implement each way of the cache
U_WAYS : for i in 0 to associativity-1 generate
way_wr_en(i) <= '1' when wr_en = '1' and wr_way_id = std_logic_vector(to_unsigned(i, wr_way_id'length)) else '0';
U_RAM : entity work.ram(SYNC_READ)
generic map(
num_words => NUM_SETS,
word_width => SET_WIDTH,
addr_width => bitsNeeded(NUM_SETS))
port map (
clk => clk,
wen => way_wr_en(i),
waddr => wr_addr(bitsNeeded(num_sets)-1 downto 0),
wdata => wr_data_complete,
raddr => rd_addr(bitsNeeded(num_sets)-1 downto 0),
rdata => ram_out(i));
end generate;
-- Register the RAM output for faster clock
process(clk, rst)
begin
if (rst = '1') then
for i in 0 to associativity-1 loop
way(i) <= (others => '0');
end loop;
elsif (rising_edge(clk)) then
if (ready_s = '1') then
for i in 0 to associativity-1 loop
way(i) <= ram_out(i);
end loop;
end if;
end if;
end process;
-- Delay the input addr by the latency of the memory
U_DELAY_ADDR : entity work.delay
generic map (
cycles => 2,
width => addr_width,
init => std_logic_vector(to_unsigned(0, addr_width)))
port map (
clk => clk,
rst => rst,
en => ready_s,
input => rd_addr,
output => rd_addr_delayed
);
-- Delay the input tag by the latency of the memory
U_DELAY_REQUEST : entity work.delay
generic map (
cycles => 2,
width => 1,
init => "0")
port map (
clk => clk,
rst => rst,
en => ready_s,
input(0) => rd_en,
output(0) => request_valid
);
-- Check all set ways for a hit
U_CHECK_TAG : for i in 0 to associativity-1 generate
constant TAG_LSB : positive := DATA_WIDTH;
constant TAG_MSB : positive := TAG_LSB + TAG_WIDTH - 1;
subtype WAY_TAG_RANGE is natural range TAG_MSB downto TAG_LSB;
constant WAY_VALID_INDEX : positive := TAG_MSB + 1;
constant DATA_LSB : natural := 0;
constant DATA_MSB : positive := DATA_LSB + DATA_WIDTH - 1;
subtype WAY_DATA_RANGE is natural range DATA_MSB downto DATA_LSB;
begin
way_tag_eq(i) <= '1' when way(i)(WAY_TAG_RANGE) = rd_addr_delayed(TAG_RANGE) else '0';
valid(i) <= way(i)(WAY_VALID_INDEX);
way_hit(i) <= way_tag_eq(i) and valid(i);
way_data(i) <= way(i)(WAY_DATA_RANGE);
end generate;
-- Or all the way hits together to determine an overall hit
-- NOTE: Will need to be pipelined for large associativities.
process(way_hit)
variable temp_hit : std_logic;
begin
temp_hit := way_hit(0);
for i in 0 to associativity-1 loop
temp_hit := temp_hit or way_hit(i);
end loop;
hit <= temp_hit;
end process;
-- Use a mux to select the right way for the output.
-- NOTE: Will need to be pipelined for large associativities.
process(way_hit, way_data)
begin
hit_data <= way_data(0);
for i in 0 to associativity-1 loop
if (way_hit(i) = '1') then
hit_data <= way_data(i);
end if;
end loop;
end process;
-------------------------------------------------------------------
-- Add an extra pipeline stage for handling misses
-- Registers for handling miss
process(clk, rst)
begin
if (rst = '1') then
hit_r <= '0';
hit_data_r <= (others => '0');
rd_addr_r <= (others => '0');
elsif (rising_edge(clk)) then
if (ready_s = '1') then
hit_r <= hit;
hit_data_r <= hit_data;
rd_addr_r <= rd_addr_delayed;
miss_valid_ways <= valid;
end if;
end if;
end process;
-- A miss has been handled when there is a write to the originally
-- requested address.
-- NOTE: might need to be pipelined
miss_handled <= '1' when wr_addr = rd_addr_r and wr_en = '1' else '0';
miss <= not hit_r;
miss_addr <= rd_addr_r;
-- Data is ready to be output when there was a hit, or when the miss has
-- been handled by an external write.
data_ready <= hit_r or miss_handled;
rd_data_valid <= data_ready;
-- Mux to select cache data (for a hit) or external data (for a miss)
rd_data <= hit_data_r when hit_r = '1' else wr_data;
-- The cache is ready when it is enabled and either there is not currently
-- a valid request, or the data is ready on a valid request.
ready_s <= en and (not request_valid or (data_ready and request_valid));
ready <= ready_s;
end default;
| gpl-3.0 |
chronos38/DSD-Projekt | Testbench/tb_prescaler.vhd | 1 | 809 | library IEEE;
use IEEE.std_logic_1164.all;
entity tb_prescaler is
end tb_prescaler;
-- Beim Testen den Prescaler anpassen
architecture sim of tb_prescaler is
component prescaler
port (
clk50 : in std_logic;
reset_n : in std_logic;
clk1 : out std_logic);
end component;
signal s_clk50 : std_logic := '0';
signal s_reset_n : std_logic := '0';
signal s_clk1 : std_logic := '0';
begin
i_prescaler : prescaler
port map (
clk50 => s_clk50,
reset_n => s_reset_n,
clk1 => s_clk1);
s_clk50 <= not s_clk50 after 1 ps;
p_test : process
begin
s_reset_n <= '0';
wait for 20 ps;
s_reset_n <= '1';
wait for 40000 ps;
end process;
end sim; | gpl-3.0 |
albertomg994/VHDL_Projects | AmgPacman/src/modulo1KHz.vhd | 1 | 4489 | -- ========== Copyright Header Begin =============================================
-- AmgPacman File: modulo1KHz.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity modulo1KHz is
Port ( clk_50MHz : in STD_LOGIC;
rst : in STD_LOGIC;
clk_1KHz : out STD_LOGIC;
pulso_1KHz : out STD_LOGIC);
end modulo1KHz;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of modulo1KHz is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal ena_aux: std_logic_vector(1 downto 0);
signal pulso_aux: std_logic;
signal force_rst: std_logic;
signal ff_startV3: std_logic;
-----------------------------------------------------------------------------
-- Declaracion de componentes
-----------------------------------------------------------------------------
COMPONENT cont255_V2
PORT(
clk : IN std_logic;
rst : IN std_logic;
ena: in std_logic;
fin : OUT std_logic
);
END COMPONENT;
COMPONENT cont255_V3
PORT(
clk : IN std_logic;
rst : IN std_logic;
ena : IN std_logic;
fin : OUT std_logic
);
END COMPONENT;
COMPONENT cont255_V4
PORT(
clk : IN std_logic;
rst : IN std_logic;
set_zero: in std_logic;
start : IN std_logic;
fin : OUT std_logic
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
pulso_1KHz <= pulso_aux;
force_rst <= rst or pulso_aux;
clk_1KHz <= pulso_aux;
-----------------------------------------------------------------------------
-- Instancia de componentes
-----------------------------------------------------------------------------
cont255_0: cont255_V2 port map(
clk => clk_50MHz,
rst => force_rst,
ena => '1',
fin => ena_aux(0)
);
cont255_153: cont255_V3 PORT MAP(
clk => clk_50MHz,
rst => force_rst,
ena => ena_aux(0),
fin => ena_aux(1)
);
cont255_2: cont255_V4 PORT MAP(
clk => clk_50MHz,
rst => rst,
set_zero => force_rst,
start => ff_startV3,
fin => pulso_aux
);
-----------------------------------------------------------------------------
-- Procesos
-----------------------------------------------------------------------------
p_ff_startV3: process(clk_50MHz, force_rst)
begin
if force_rst = '1' then
ff_startV3 <= '0';
elsif rising_edge(clk_50MHz) then
if ena_aux(1) = '1' then
ff_startV3 <= '1';
else
ff_startV3 <= ff_startV3;
end if;
end if;
end process p_ff_startV3;
end rtl;
| gpl-3.0 |
abcsds/RS232 | RS232Write_16/FsmWrite.vhd | 4 | 3940 | library IEEE;
use IEEE.std_logic_1164.all;
entity FsmWrite is
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
FBaud : in std_logic;
EOT : out std_logic;
CTRL : out std_logic_vector(3 downto 0)
);
end FsmWrite;
architecture simple of FsmWrite is
signal Qp, Qn : std_logic_vector(3 downto 0);
begin
COMB: process(Qp,STR,FBaud)
begin
case Qp is
when "0000" =>
CTRL<= "0000"; -- Hold
EOT<= '1';
if(STR= '0')then
Qn<= Qp;
else
Qn<= "0001";
end if;
when "0001" =>
CTRL<= "0000"; -- Hold
EOT<= '0';
if(FBaud= '1')then
Qn<= "0010";
else
Qn<= Qp;
end if;
when "0010" =>
CTRL<= "0001"; -- Start
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0011";
end if;
when "0011" =>
CTRL<= "0010"; -- Bit 0
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0100";
end if;
when "0100" =>
CTRL<= "0011"; -- Bit 1
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0101";
end if;
when "0101" =>
CTRL<= "0100"; -- Bit2
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0110";
end if;
when "0110" =>
CTRL<= "0101"; -- Bit 3
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0111";
end if;
when "0111" =>
CTRL<= "0110"; -- Bit 4
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1000";
end if;
when "1000" =>
CTRL<= "0111"; -- Bit 5
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1001";
end if;
when "1001" =>
CTRL<= "1000"; -- Bit 6
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1010";
end if;
when "1010" =>
CTRL<= "1001"; -- Bit 7
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1011";
end if;
when "1011" =>
CTRL<= "1010"; -- Stop
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1100";
end if;
when others =>
CTRL<= "0000";
EOT<= '1';
Qn<= "0000";
end case;
end process COMB;
FF: process(RST,CLK)
begin
if(RST='0')then
Qp<= "0000";
elsif(CLK'event and CLK='1')then
Qp<= Qn;
end if;
end process;
end simple; | gpl-3.0 |
abcsds/RS232 | RS232Write_16/RightShift.vhd | 4 | 1386 | library IEEE;
use IEEE.std_logic_1164.all;
entity RightShft is
port(
RST : in std_logic;
CLK : in std_logic;
CTRL : in std_logic_vector(3 downto 0);
DATAWR : in std_logic_vector(7 downto 0);
Tx : out std_logic
);
end RightShft;
architecture simple of RightShft is
signal Txn, Txp: std_logic;
begin
MUX: process(CTRL,DATAWR)
begin
case CTRL is
when "0000"=> Txn<= '1';-- Hold
when "0001"=> Txn<= '0';-- Start
when "0010"=> Txn<= DATAWR(0);-- DATARD(0)
when "0011"=> Txn<= DATAWR(1);-- DATARD(1)
when "0100"=> Txn<= DATAWR(2);-- DATARD(2)
when "0101"=> Txn<= DATAWR(3);-- DATARD(3)
when "0110"=> Txn<= DATAWR(4);-- DATARD(4)
when "0111"=> Txn<= DATAWR(5);-- DATARD(5)
when "1000"=> Txn<= DATAWR(6);-- DATARD(6)
when "1001"=> Txn<= DATAWR(7);-- DATARD(7)
when "1010"=> Txn<= '1';-- Stop
when others => Txn<= '1';
end case;
end process MUX;
FF: process(RST,CLK)
begin
if(RST='0')then
Txp<= '0';
elsif(CLK'event and CLK='1')then
Txp<= Txn;
end if;
end process FF;
Tx <= Txp;
end simple; | gpl-3.0 |
JosiCoder/CtLab | FPGA/FPGA SigGen/Source/PhaseGenerator.vhd | 1 | 3230 | --------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Provides a phase generator controlled by a phase accumulator. It is
-- recommended to use increments only up to the half of the accumulator´s
-- capacity (MSB=1, all others 0). This ensures a duty cycle of 50% in the MSB
-- of the phase when it is used as a frequency signal. The current phase might
-- be used for DDS signal generation.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PhaseGenerator is
generic
(
-- The width of the phase values.
phase_width: natural := 32
);
port
(
-- The system clock.
clk: in std_logic;
-- The increment to be added to the phase accumulator in each clock cycle.
phase_increment: in unsigned (phase_width-1 downto 0);
-- A signal used to reset the generator´s phase.
reset_phase: in std_logic;
-- The current phase value.
phase: out unsigned (phase_width-1 downto 0) := (others => '0')
);
end entity;
architecture stdarch of PhaseGenerator is
type reg_type is record
phase_accumulator: unsigned (phase_width-1 downto 0);
end record;
signal state, next_state: reg_type := (phase_accumulator => (others => '0'));
begin
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state.phase_accumulator <=
(next_state.phase_accumulator'range => '0') when reset_phase = '1'
else state.phase_accumulator + phase_increment;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
phase <= state.phase_accumulator;
end architecture;
| gpl-3.0 |
arthurbenemann/fpga-bits | undocumented/DCM_clock/ms_clock.vhd | 3 | 554 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ms_timer is
Port ( clk : in STD_LOGIC;
clk_1ms : out STD_LOGIC);
end ms_timer;
architecture Behavioral of ms_timer is
signal counter : STD_LOGIC_VECTOR(21 downto 0) := (others =>'0');
begin
clk_process: process(clk)
begin
if rising_edge(clk) then
if counter = ((32000000/1000)-1) then
counter <= (others =>'0');
clk_1ms <= '1';
else
counter <= counter +1;
clk_1ms <= '0';
end if;
end if;
end process;
end Behavioral; | gpl-3.0 |
aospan/NetUP_Dual_Universal_CI-fpga | dma_arbiter_0.vhd | 1 | 5354 | -- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- dma_arbiter_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dma_arbiter_0 is
port (
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
dma0_addr : in std_logic_vector(60 downto 0) := (others => '0'); -- conduit_end.export
dma0_wrdata : in std_logic_vector(63 downto 0) := (others => '0'); -- .export
dma0_size : in std_logic_vector(6 downto 0) := (others => '0'); -- .export
dma0_write : in std_logic := '0'; -- .export
dma0_wait : out std_logic; -- .export
dma1_addr : in std_logic_vector(60 downto 0) := (others => '0'); -- .export
dma1_size : in std_logic_vector(6 downto 0) := (others => '0'); -- .export
dma1_wrdata : in std_logic_vector(63 downto 0) := (others => '0'); -- .export
dma1_write : in std_logic := '0'; -- .export
dma1_wait : out std_logic; -- .export
dma0_byteen : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dma1_byteen : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
mem_addr : out std_logic_vector(30 downto 0); -- avalon_master.address
mem_size : out std_logic_vector(6 downto 0); -- .burstcount
mem_wrdata : out std_logic_vector(63 downto 0); -- .writedata
mem_write : out std_logic; -- .write
mem_waitreq : in std_logic := '0'; -- .waitrequest
mem_byteen : out std_logic_vector(7 downto 0) -- .byteenable
);
end entity dma_arbiter_0;
architecture rtl of dma_arbiter_0 is
component dma_arbiter is
generic (
MEM_ADDR_WIDTH : natural := 31
);
port (
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
dma0_addr : in std_logic_vector(60 downto 0) := (others => 'X'); -- export
dma0_wrdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- export
dma0_size : in std_logic_vector(6 downto 0) := (others => 'X'); -- export
dma0_write : in std_logic := 'X'; -- export
dma0_wait : out std_logic; -- export
dma1_addr : in std_logic_vector(60 downto 0) := (others => 'X'); -- export
dma1_size : in std_logic_vector(6 downto 0) := (others => 'X'); -- export
dma1_wrdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- export
dma1_write : in std_logic := 'X'; -- export
dma1_wait : out std_logic; -- export
dma0_byteen : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dma1_byteen : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
mem_addr : out std_logic_vector(30 downto 0); -- address
mem_size : out std_logic_vector(6 downto 0); -- burstcount
mem_wrdata : out std_logic_vector(63 downto 0); -- writedata
mem_write : out std_logic; -- write
mem_waitreq : in std_logic := 'X'; -- waitrequest
mem_byteen : out std_logic_vector(7 downto 0) -- byteenable
);
end component dma_arbiter;
begin
dma_arbiter_0 : component dma_arbiter
generic map (
MEM_ADDR_WIDTH => 31
)
port map (
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
dma0_addr => dma0_addr, -- conduit_end.export
dma0_wrdata => dma0_wrdata, -- .export
dma0_size => dma0_size, -- .export
dma0_write => dma0_write, -- .export
dma0_wait => dma0_wait, -- .export
dma1_addr => dma1_addr, -- .export
dma1_size => dma1_size, -- .export
dma1_wrdata => dma1_wrdata, -- .export
dma1_write => dma1_write, -- .export
dma1_wait => dma1_wait, -- .export
dma0_byteen => dma0_byteen, -- .export
dma1_byteen => dma1_byteen, -- .export
mem_addr => mem_addr, -- avalon_master.address
mem_size => mem_size, -- .burstcount
mem_wrdata => mem_wrdata, -- .writedata
mem_write => mem_write, -- .write
mem_waitreq => mem_waitreq, -- .waitrequest
mem_byteen => mem_byteen -- .byteenable
);
end architecture rtl; -- of dma_arbiter_0
| gpl-3.0 |
arthurbenemann/fpga-bits | mandelbrot/tb_iteration.vhd | 1 | 4355 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY tb_iteration IS
END tb_iteration;
ARCHITECTURE behavior OF tb_iteration IS
COMPONENT mandelbrot_iteration
PORT(
clk : IN std_logic;
ov_in : IN std_logic;
x : IN std_logic_vector(17 downto 0);
y : IN std_logic_vector(17 downto 0);
x0 : IN std_logic_vector(17 downto 0);
y0 : IN std_logic_vector(17 downto 0);
x_out : OUT std_logic_vector(17 downto 0);
y_out : OUT std_logic_vector(17 downto 0);
ov : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal ov_in : std_logic := '0';
signal x : std_logic_vector(17 downto 0) := (others => '0');
signal y : std_logic_vector(17 downto 0) := (others => '0');
signal x0 : std_logic_vector(17 downto 0) := (others => '0');
signal y0 : std_logic_vector(17 downto 0) := (others => '0');
--Outputs
signal x_out : std_logic_vector(17 downto 0);
signal y_out : std_logic_vector(17 downto 0);
signal ov : std_logic;
-- Clock period definitions
constant clk_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mandelbrot_iteration PORT MAP (
clk => clk,
ov_in => ov_in,
x => x,
y => y,
x0 => x0,
y0 => y0,
x_out => x_out,
y_out => y_out,
ov => ov
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*20.5;
-- insert stimulus here
-- x0<= std_logic_vector(to_signed(+1*(2**15),18));
-- y0<= std_logic_vector(to_signed(+1*(2**15),18));
--
-- x <= std_logic_vector(to_signed(+1*(2**15),18));
-- y <= std_logic_vector(to_signed(+0*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(-1*(2**15),18));
-- y <= std_logic_vector(to_signed(+0*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(+0*(2**15),18));
-- y <= std_logic_vector(to_signed(+1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(+0*(2**15),18));
-- y <= std_logic_vector(to_signed(-1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(+1*(2**15),18));
-- y <= std_logic_vector(to_signed(+1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(-1*(2**15),18));
-- y <= std_logic_vector(to_signed(-1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(+1*(2**15),18));
-- y <= std_logic_vector(to_signed(-1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(-1*(2**15),18));
-- y <= std_logic_vector(to_signed(1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(2*(2**15),18));
-- y <= std_logic_vector(to_signed(1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(2*(2**15),18));
-- y <= std_logic_vector(to_signed(2*(2**15),18));
-- wait for clk_period*20;
wait for clk_period*100;
x <= std_logic_vector(to_signed(2*(2**15),18));
y <= std_logic_vector(to_signed(2*(2**15),18));
wait for clk_period*1;
x <= std_logic_vector(to_signed(+1*(2**15),18));
y <= std_logic_vector(to_signed(+1*(2**15),18));
wait for clk_period*1;
x <= std_logic_vector(to_signed(+0*(2**15),18));
y <= std_logic_vector(to_signed(+0*(2**15),18));
wait for clk_period*1;
x <= std_logic_vector(to_signed(+1*(2**15),18));
y <= std_logic_vector(to_signed(+1*(2**15),18));
x0 <= std_logic_vector(to_signed(-1*(2**15),18));
y0 <= std_logic_vector(to_signed(+1*(2**15),18));
wait for clk_period*1;
x <= std_logic_vector(to_signed(+0*(2**15),18));
y <= std_logic_vector(to_signed(+0*(2**15),18));
x0 <= std_logic_vector(to_signed(-0*(2**15),18));
y0 <= std_logic_vector(to_signed(+0*(2**15),18));
wait for clk_period*1;
ov_in <= '1';
wait for clk_period*1;
ov_in <= '0';
wait for clk_period*100;
wait;
end process;
END;
| gpl-3.0 |
arthurbenemann/fpga-bits | undocumented/serial_out/tb_rx.vhd | 1 | 5156 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:34:16 02/23/2016
-- Design Name:
-- Module Name: C:/Users/Arthur/Documents/FPGA_temp/serial_out/tb_rx.vhd
-- Project Name: serial_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: uart_rx
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_rx IS
END tb_rx;
ARCHITECTURE behavior OF tb_rx IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT uart_rx
PORT(
clk : IN std_logic;
rx : IN std_logic;
rx_data : OUT std_logic_vector(7 downto 0);
rx_ready : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rx : std_logic := '1';
--Outputs
signal rx_data : std_logic_vector(7 downto 0);
signal rx_ready : std_logic;
-- Clock period definitions
constant clk_period : time := 31.25 ns;
constant bit_period : time := 8.68 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: uart_rx PORT MAP (
clk => clk,
rx => rx,
rx_data => rx_data,
rx_ready => rx_ready
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait for 10 us;
-- send '0000000'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period*8;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '11111111'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period*8;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '11110000'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '00001111'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '01010101'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
-- send '10101010'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
-- send '01010101'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 200 us;
end process;
END;
| gpl-3.0 |
JosiCoder/CtLab | FPGA/SPI Interface/Source/SPI_SlaveTransmitter.vhd | 1 | 4223 | --------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Provides an SPI slave transmitter consisting of an input selector, a single
-- transmitter buffer, and a transmitter serializer. The data width is fixed (see
-- data_width constant value in the Globals package).
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.globals.all;
-- Note: It's not possible to use generics for both the data width and the number
-- of buffers to be generated. This would need a signal that is an array of
-- unconstrained arrays which is not yet supported by VHDL. Thus, the data width
-- is fixed (see Globals package).
entity SPI_SlaveTransmitter is
generic
(
-- The width of the address.
address_width: positive
);
port
(
-- The system clock.
clk: in std_logic;
-- Controls when the data to be transmitted are read (input is passed
-- when enable is '1', synchronous to CLK).
buffer_enable: in std_logic;
-- The clock controlling the serial data transmission.
sclk: in std_logic;
-- The (active low) slave select.
ss: in std_logic;
-- The selected address to read the data to be transmitted from.
address: in unsigned(address_width-1 downto 0);
-- The parallel inputs used to get the data to be sent from.
data_x: in data_buffer_vector((2**address_width)-1 downto 0);
-- The serial output.
miso: out std_logic
);
end entity;
architecture stdarch of SPI_SlaveTransmitter is
constant number_of_data_buffers: positive := 2**address_width;
signal selected_data, transmitter_data: data_buffer;
begin
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
-- The input data buffer (transparent if the enable signal is '1'; synchronous
-- to clk).
data_buffer: entity work.SPI_SlaveDataBuffer
generic map
(
width => data_width,
edge_triggered => false
)
port map
(
clk => clk,
buffer_enable => buffer_enable,
data => selected_data,
buffered_data => transmitter_data,
ready => open
);
-- The slave transmitter serializer.
serializer: entity work.SPI_SlaveTransmitterSerializer
generic map
(
width => data_width
)
port map
(
sclk => sclk,
ss => ss,
data => transmitter_data,
miso => miso
);
--------------------------------------------------------------------------------
-- Input selection logic.
--------------------------------------------------------------------------------
-- The data buffer.
input_selector: process(address, data_x) is
begin
selected_data <= (others => '1');
for i in number_of_data_buffers-1 downto 0 loop
if (address = to_unsigned(i, address_width)) then
selected_data <= data_x(i);
end if;
end loop;
end process;
end architecture;
| gpl-3.0 |
arthurbenemann/fpga-bits | mandelbrot/ipcore_dir/multiplier.vhd | 1 | 5880 | --------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- Generated from component ID: xilinx.com:ip:cmpy:3.1
-- You must compile the wrapper file multiplier.vhd when simulating
-- the core, multiplier. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY multiplier IS
port (
ar: in std_logic_vector(17 downto 0);
ai: in std_logic_vector(17 downto 0);
br: in std_logic_vector(17 downto 0);
bi: in std_logic_vector(17 downto 0);
clk: in std_logic;
pr: out std_logic_vector(21 downto 0);
pi: out std_logic_vector(21 downto 0));
END multiplier;
ARCHITECTURE multiplier_a OF multiplier IS
-- synthesis translate_off
component wrapped_multiplier
port (
ar: in std_logic_vector(17 downto 0);
ai: in std_logic_vector(17 downto 0);
br: in std_logic_vector(17 downto 0);
bi: in std_logic_vector(17 downto 0);
clk: in std_logic;
pr: out std_logic_vector(21 downto 0);
pi: out std_logic_vector(21 downto 0));
end component;
-- Configuration specification
for all : wrapped_multiplier use entity XilinxCoreLib.cmpy_v3_1(behavioral)
generic map(
c_a_width => 18,
c_ce_overrides_sclr => 0,
has_negate => 0,
c_has_sclr => 0,
c_out_high => 36,
c_verbosity => 0,
c_mult_type => 1,
c_latency => 4,
c_xdevice => "xc6slx9",
c_has_ce => 0,
single_output => 0,
round => 0,
use_dsp_cascades => 1,
c_optimize_goal => 1,
c_xdevicefamily => "spartan6",
c_out_low => 15,
c_b_width => 18);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_multiplier
port map (
ar => ar,
ai => ai,
br => br,
bi => bi,
clk => clk,
pr => pr,
pi => pi);
-- synthesis translate_on
END multiplier_a;
| gpl-3.0 |
JosiCoder/CtLab | FPGA/FPGA SigGen/Source/GatedCounter.vhd | 1 | 6435 | --------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Provides a simple counter capable of counting a faster pulse signal using a
-- slower gate signal. Uses a freely running counter that is not cleared. When
-- the gate signal is '1', the counter´s value is stored. The measurement value
-- is determined by calculating the difference between the current and the
-- previous counter value. Overflow is detected and signalled.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library Common;
use work.Globals.all;
entity GatedCounter is
generic
(
-- The width of the measured frequency or period value.
counter_width: natural := 32
);
port
(
-- The pulse signal that drives the counter.
pulse_signal: in std_logic;
-- The signal that controls the counter. The rising pulse edges between
-- two consecutive gate '1' signals are counted. Note that the gate signal
-- is level-sensitive, not edge-sensitive.
gate_signal: in std_logic;
-- The measured frequency or period value.
value: out unsigned (counter_width-1 downto 0);
-- '1' if an overflow has occurred in the current measurement period.
overflow: out std_logic
);
end entity;
architecture stdarch of GatedCounter is
type reg_type is record
finished_counter_value, old_finished_counter_value: unsigned (counter_width-1 downto 0);
running_overflow, finished_overflow: std_logic;
end record;
signal state, next_state: reg_type :=
(
finished_counter_value => (others => '0'),
old_finished_counter_value => (others => '0'),
running_overflow => '0',
finished_overflow => '0'
);
signal running_counter_value: unsigned (counter_width-1 downto 0) := (others => '0');
begin
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
-- Counts the pulse signal continuously.
counter: entity Common.Counter
generic map
(
width => counter_width
)
port map
(
clk => pulse_signal,
clear => '0',
ce => '1',
value => running_counter_value
);
--------------------------------------------------------------------------------
-- State and data register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(pulse_signal);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, running_counter_value, gate_signal) is
begin
-- Defaults.
next_state <= state;
if (gate_signal = '1') then
-- An active ('1') gate signal has been detected. We finish the current
-- measurement cycle and start a new one.
-- Memorize the counter value and overflow status.
next_state.finished_counter_value <= running_counter_value;
next_state.old_finished_counter_value <= state.finished_counter_value;
next_state.finished_overflow <= state.running_overflow;
if (running_counter_value = state.finished_counter_value) then
-- There was an overflow at the very end of the measurement cycle(i.e. the counter
-- has wrapped around and reached the same value again). Set the finished counter
-- value´s overflow marker directly.
next_state.finished_overflow <= '1';
else
-- There was no overflow at the very end of the measurement cycle, we just keep
-- the overflows that have happened so far.
next_state.finished_overflow <= state.running_overflow;
end if;
-- Reset the running counter value´s overflow marker as we start a new measurement
-- cycle.
next_state.running_overflow <= '0';
elsif (running_counter_value = state.finished_counter_value) then
-- We´re not at the end of a measurement cycle but there was an overflow (i.e. the counter
-- has wrapped around and reached the same value again). This might occur even multiple
-- times per gate signal period, we capture the first occurrence.
next_state.running_overflow <= '1';
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
-- Calculate the number of pulse cycles between the last and the last but one
-- active gate signal. This works even if the freely running counter wraps around
-- as long as the last value stays below the last but one value.
value <= state.finished_counter_value - state.old_finished_counter_value;
overflow <= state.finished_overflow;
end architecture;
| gpl-3.0 |
JosiCoder/CtLab | FPGA/SPI Interface/Testbenches/SPI_SlaveAddressDecoderTester.vhd | 1 | 3807 | --------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests the SPI slave address decoder.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.TestTools.all;
entity SPI_SlaveAddressDecoder_Tester is
end entity;
architecture stdarch of SPI_SlaveAddressDecoder_Tester is
-- Constants
constant test_delay: time := 1ps;
constant address_width: positive := 3;
constant no_of_addresses: positive := 2**address_width;
-- Inputs
signal buffer_enable: std_logic := '1';
signal address: unsigned(address_width-1 downto 0) := (others => '0');
-- Outputs
signal buffer_enable_x: std_logic_vector(no_of_addresses-1 downto 0);
begin
--------------------------------------------------------------------------------
-- Instantiate the UUT(s).
--------------------------------------------------------------------------------
uut: entity work.SPI_SlaveAddressDecoder
generic map
(
address_width => address_width
)
port map
(
buffer_enable => buffer_enable,
address => address,
buffer_enable_x => buffer_enable_x
);
--------------------------------------------------------------------------------
-- Stimulate the UUT.
--------------------------------------------------------------------------------
stimulus: process is
variable expected_ss_x: std_logic_vector(buffer_enable_x'range);
begin
-- Wait for the UUT's initial output values to settle down and check them.
wait for test_delay;
assert (buffer_enable_x = (buffer_enable_x'range => '1'))
report "At least one buffer_enable_x unintentionally active."
severity error;
-- Enable the slave select.
buffer_enable <= '0';
-- Now provide consecutive addresses and check whether the buffer_enable_x signals
-- match them.
for i in 0 to no_of_addresses-1 loop
address <= to_unsigned(i, address_width);
wait for test_delay;
expected_ss_x := (buffer_enable_x'range => '1');
expected_ss_x(to_integer(address)) := '0';
assert (buffer_enable_x = expected_ss_x)
report "One or more buffer_enable_x not set correctly."
severity error;
end loop;
-- Disable the slave select again and check whether all buffer_enable_x signals
-- are deactivated.
buffer_enable <= '1';
wait for test_delay;
assert (buffer_enable_x = (buffer_enable_x'range => '1'))
report "At least one buffer_enable_x not deactivated."
severity error;
wait;
end process;
end architecture;
| gpl-3.0 |
arthurbenemann/fpga-bits | undocumented/VGA1/ipcore_dir/v_timer.vhd | 1 | 4041 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file v_timer.vhd when simulating
-- the core, v_timer. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY v_timer IS
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END v_timer;
ARCHITECTURE v_timer_a OF v_timer IS
-- synthesis translate_off
COMPONENT wrapped_v_timer
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_v_timer USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1000001100",
c_fb_latency => 0,
c_has_ce => 0,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 1,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 10,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_v_timer
PORT MAP (
clk => clk,
q => q
);
-- synthesis translate_on
END v_timer_a;
| gpl-3.0 |
aospan/NetUP_Dual_Universal_CI-fpga | testbench/dvb_dma_tb.vhd | 1 | 5451 | -- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity dvb_dma_tb is
end;
architecture sym of dvb_dma_tb is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal dvb0_clk : std_logic;
signal dvb0_strt : std_logic;
signal dvb0_dval : std_logic;
signal dvb0_data : std_logic_vector(7 downto 0);
signal dvb1_clk : std_logic;
signal dvb1_strt : std_logic;
signal dvb1_dval : std_logic;
signal dvb1_data : std_logic_vector(7 downto 0);
signal tsa_sop : std_logic;
signal tsa_data : std_logic_vector(7 downto 0);
signal tsa_dval : std_logic;
signal tsb_sop : std_logic;
signal tsb_data : std_logic_vector(7 downto 0);
signal tsb_dval : std_logic;
signal address : std_logic_vector(3 downto 0) := (others => '0');
signal byteenable : std_logic_vector(3 downto 0) := (others => '0');
signal writedata : std_logic_vector(31 downto 0) := (others => '0');
signal write : std_logic := '0';
signal readdata_0 : std_logic_vector(31 downto 0);
signal readdata_1 : std_logic_vector(31 downto 0);
signal interrupt_0 : std_logic;
signal interrupt_1 : std_logic;
signal mem0_addr : std_logic_vector(63 downto 3);
signal mem0_byteen : std_logic_vector(7 downto 0);
signal mem0_size : std_logic_vector(6 downto 0);
signal mem0_wrdata : std_logic_vector(63 downto 0);
signal mem0_write : std_logic;
signal mem0_waitreq : std_logic;
signal mem1_addr : std_logic_vector(63 downto 3);
signal mem1_byteen : std_logic_vector(7 downto 0);
signal mem1_size : std_logic_vector(6 downto 0);
signal mem1_wrdata : std_logic_vector(63 downto 0);
signal mem1_write : std_logic;
signal mem1_waitreq : std_logic;
signal mem_addr : std_logic_vector(30 downto 0);
signal mem_byteen : std_logic_vector(7 downto 0);
signal mem_size : std_logic_vector(6 downto 0);
signal mem_wrdata : std_logic_vector(63 downto 0);
signal mem_write : std_logic;
signal mem_waitreq : std_logic := '0';
begin
DVB_SRC_0 : entity work.dvb_source
generic map (
CLOCK_RATE_MHZ => 15,
INTERPACKET_GAP => 5,
INTEROCTET_GAP => 2
)
port map (
ts_clk => dvb0_clk,
ts_strt => dvb0_strt,
ts_dval => dvb0_dval,
ts_data => dvb0_data
);
DVB_SRC_1 : entity work.dvb_source
port map (
ts_clk => dvb1_clk,
ts_strt => dvb1_strt,
ts_dval => dvb1_dval,
ts_data => dvb1_data
);
DVB_TSIN_0 : entity work.dvb_ts_sync
port map (
ts_clk => dvb0_clk,
ts_strt => dvb0_strt,
ts_dval => dvb0_dval,
ts_data => dvb0_data,
--
rst => rst,
clk => clk,
--
strt => tsa_sop,
data => tsa_data,
dval => tsa_dval
);
DVB_TSIN_1 : entity work.dvb_ts_sync
port map (
ts_clk => dvb1_clk,
ts_strt => dvb1_strt,
ts_dval => dvb1_dval,
ts_data => dvb1_data,
--
rst => rst,
clk => clk,
--
strt => tsb_sop,
data => tsb_data,
dval => tsb_dval
);
DVB_DMA_0 : entity work.dvb_dma
port map (
rst => rst,
clk => clk,
address => address,
byteenable => byteenable,
writedata => writedata,
write => write,
readdata => readdata_0,
interrupt => interrupt_0,
dvb_sop => tsa_sop,
dvb_data => tsa_data,
dvb_dval => tsa_dval,
mem_addr => mem0_addr,
mem_byteen => mem0_byteen,
mem_size => mem0_size,
mem_wrdata => mem0_wrdata,
mem_write => mem0_write,
mem_waitreq => mem0_waitreq
);
DVB_DMA_1 : entity work.dvb_dma
port map (
rst => rst,
clk => clk,
address => address,
byteenable => byteenable,
writedata => writedata,
write => write,
readdata => readdata_1,
interrupt => interrupt_1,
dvb_sop => tsb_sop,
dvb_data => tsb_data,
dvb_dval => tsb_dval,
mem_addr => mem1_addr,
mem_byteen => mem1_byteen,
mem_size => mem1_size,
mem_wrdata => mem1_wrdata,
mem_write => mem1_write,
mem_waitreq => mem1_waitreq
);
ARB_0 : entity work.dma_arbiter
port map (
rst => rst,
clk => clk,
dma0_addr => mem0_addr,
dma0_byteen => mem0_byteen,
dma0_size => mem0_size,
dma0_wrdata => mem0_wrdata,
dma0_write => mem0_write,
dma0_wait => mem0_waitreq,
dma1_addr => mem1_addr,
dma1_byteen => mem1_byteen,
dma1_size => mem1_size,
dma1_wrdata => mem1_wrdata,
dma1_write => mem1_write,
dma1_wait => mem1_waitreq,
mem_addr => mem_addr,
mem_byteen => mem_byteen,
mem_size => mem_size,
mem_wrdata => mem_wrdata,
mem_write => mem_write,
mem_waitreq => mem_waitreq
);
process
begin
wait for 8 ns;
clk <= not clk;
end process;
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
byteenable <= "1111";
write <= '1';
address <= X"4";
writedata <= X"040008BC";
wait until rising_edge(clk);
address <= X"0";
writedata <= X"00000001";
wait until rising_edge(clk);
write <= '0';
loop
wait until interrupt_0 = '1';
-- wait for 225 us;
wait until rising_edge(clk);
address <= X"1";
write <= '1';
writedata <= X"00000200";
wait until rising_edge(clk);
write <= '0';
end loop;
--
wait;
end process;
process
begin
wait until rising_edge(clk);
mem_waitreq <= mem_waitreq xor mem_write;
end process;
end;
| gpl-3.0 |
wyvernSemi/vproc | test.vhd | 1 | 7646 | -- =============================================================
--
-- Top level demonstration test environment for VProc
--
-- Copyright (c) 2021 Simon Southwell. Confidential
--
-- This file is part of VProc.
--
-- VProc is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- VProc is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with VProc. If not, see <http://www.gnu.org/licenses/>.
--
-- $Id: test.vhd,v 1.1 2021/05/04 15:59:07 simon Exp $
-- $Source: /home/simon/CVS/src/HDL/VProc/test.vhd,v $
--
-- =============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.env.all;
entity test is
end entity;
architecture sim of test is
---------------------------------------------
-- Declarations
---------------------------------------------
type array_t is array (natural range <>) of std_logic_vector;
constant FREQ : real := 100.0e6;
constant ClkPeriod : time := 1 sec / FREQ;
constant StopCount : integer := 100;
signal Clk : std_logic := '1';
signal Count : integer := 0;
signal Interrupt0, Interrupt1 : std_logic_vector(2 downto 0) := "000";
signal notReset_H : std_logic := '0';
signal UpdateResponse : std_logic_vector(1 downto 0) := "11";
signal VPAddr0, VPDataOut0 : std_logic_vector(31 downto 0) := 32x"0";
signal VPAddr1, VPDataOut1 : std_logic_vector(31 downto 0) := 32x"0";
signal VPDataIn0, VPDataIn1 : std_logic_vector(31 downto 0) := 32x"0";
signal VPWE0, VPWE1 : std_logic;
signal VPRD0, VPRD1 : std_logic;
signal Update : std_logic_vector(1 downto 0);
signal notReset : std_logic;
signal ResetInt : std_logic := '0';
signal CS1 : std_logic;
signal Mem : array_t (0 to 1023)(31 downto 0) := (others => 32x"0");
begin
---------------------------------------------
-- Combinatorial logic
---------------------------------------------
notReset <= '1' when (Count > 5) else '0';
CS1 <= '1' when VPAddr1(31 downto 28) = 4x"a" else '0';
---------------------------------------------
-- VProc 0
---------------------------------------------
vp0 : entity work.VProc
port map (
Clk => Clk,
Addr => VPAddr0,
WE => VPWE0,
RD => VPRD0,
DataOut => VPDataOut0,
DataIn => VPDataIn0,
WRAck => VPWE0,
RDAck => VPRD0,
Interrupt => ResetInt & Interrupt0(1 downto 0),
Update => Update(0),
UpdateResponse => UpdateResponse(0),
Node => 4x"0"
);
---------------------------------------------
-- VProc 1
---------------------------------------------
vp1 : entity work.VProc
port map (
Clk => Clk,
Addr => VPAddr1,
WE => VPWE1,
RD => VPRD1,
DataOut => VPDataOut1,
DataIn => VPDataIn1,
WRAck => VPWE1,
RDAck => VPRD1,
Interrupt => Interrupt1,
Update => Update(1),
UpdateResponse => UpdateResponse(1),
Node => 4x"1"
);
---------------------------------------------
-- Response processes
---------------------------------------------
P_UPDT0 : process(Update(0))
begin
UpdateResponse(0) <= not UpdateResponse(0);
end process;
P_UPDT1 : process(Update(1))
begin
UpdateResponse(1) <= not UpdateResponse(1);
end process;
---------------------------------------------
-- Clock generation
---------------------------------------------
P_CLKGEN : process
begin
-- Generate a clock cycle
loop
Clk <= '1';
wait for ClkPeriod/2.0;
Clk <= '0';
wait for ClkPeriod/2.0;
end loop;
end process;
---------------------------------------------
-- Data generation
---------------------------------------------
P_GENDATA : process (Clk)
variable Seed1 : natural := 16#250864#;
variable Seed2 : natural := 16#468025#;
variable RandNumR : real;
variable RandNumI0 : natural;
variable RandNumI1 : natural;
begin
if Clk'event and Clk = '1' then
ResetInt <= notReset and not notReset_H;
if Count = StopCount then
stop(0);
end if;
notReset_H <= notReset;
Count <= Count + 1;
uniform(Seed1, Seed2, RandNumR);
RandNumI0 := natural(65536.0 * RandNumR);
uniform(Seed1, Seed2, RandNumR);
RandNumI1 := natural(65536.0 * RandNumR);
VPDataIn0 <= std_logic_vector(to_unsigned(RandNumI0, 16)) &
std_logic_vector(to_unsigned(RandNumI1, 16)) ;
uniform(Seed1, Seed2, RandNumR);
RandNumI0 := natural(16.0 * RandNumR);
if RandNumI0 = 0 then
Interrupt0 <= "001";
else
Interrupt0 <= "000";
end if;
uniform(Seed1, Seed2, RandNumR);
RandNumI0 := natural(16.0 * RandNumR);
if RandNumI0 = 0 then
Interrupt1 <= "001";
else
Interrupt1 <= "000";
end if;
end if;
end process;
---------------------------------------------
-- Memory model
---------------------------------------------
P_MEM : process (Clk, VPAddr1)
begin
-- Read memory
VPDataIn1 <= Mem(to_integer(unsigned(VPAddr1(9 downto 0))));
-- Write memory
if Clk'event and Clk = '1' then
if VPWE1 = '1' and CS1 = '1' then
Mem(to_integer(unsigned(VPAddr1(9 downto 0)))) <= VPDataOut1;
end if;
end if;
end process;
end sim;
| gpl-3.0 |
arthurbenemann/fpga-bits | mandelbrot/ipcore_dir/clock_manager.vhd | 1 | 6341 | -- file: clock_manager.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___200.000______0.000______50.0______210.548____196.077
-- CLK_OUT2____40.000______0.000______50.0______327.382____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock_manager is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_80 : out std_logic;
CLK_40 : out std_logic
);
end clock_manager;
architecture xilinx of clock_manager is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock_manager,clk_wiz_v3_6,{component_name=clock_manager,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 4,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 20,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_80,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_40,
I => clkout1);
end xilinx;
| gpl-3.0 |
arthurbenemann/fpga-bits | undocumented/flashyLights/ipcore_dir/memmory/simulation/addr_gen.vhd | 101 | 4409 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 |
UviDTE-UviSpace/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/raw2rgb/onchip_fifo.vhd | 2 | 6420 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: test_fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.2 Build 222 07/20/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY onchip_fifo IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END onchip_fifo;
ARCHITECTURE SYN OF onchip_fifo IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(11 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone V",
lpm_numwords => 2048,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 12,
lpm_widthu => 11,
overflow_checking => "OFF",
underflow_checking => "OFF",
use_eab => "ON"
)
PORT MAP (
aclr => aclr,
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "2048"
-- Retrieval info: PRIVATE: Empty NUMERIC "0"
-- Retrieval info: PRIVATE: Full NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "12"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "12"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL test_fifo_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 |
arthurbenemann/fpga-bits | undocumented/7SEG_CLOCK/tb_clock24h_bdc.vhd | 2 | 1348 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_clock24h_bdc IS
END tb_clock24h_bdc;
ARCHITECTURE behavior OF tb_clock24h_bdc IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT clock24h_bcd
PORT(
clk_1ms : IN std_logic;
hour_bcd : OUT std_logic_vector(7 downto 0);
minute_bcd : OUT std_logic_vector(7 downto 0);
clk_1s : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk_1ms : std_logic := '0';
--Outputs
signal hour_bcd : std_logic_vector(7 downto 0);
signal minute_bcd : std_logic_vector(7 downto 0);
signal clk_1s : std_logic;
-- Clock period definitions
constant clk_1ms_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: clock24h_bcd PORT MAP (
clk_1ms => clk_1ms,
hour_bcd => hour_bcd,
minute_bcd => minute_bcd,
clk_1s => clk_1s
);
-- Clock process definitions
clk_1ms_process :process
begin
clk_1ms <= '0';
wait for clk_1ms_period/2;
clk_1ms <= '1';
wait for clk_1ms_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_1ms_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 |
arthurbenemann/fpga-bits | undocumented/audioDac/ipcore_dir/rom_memory.vhd | 2 | 5412 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rom_memory.vhd when simulating
-- the core, rom_memory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rom_memory IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END rom_memory;
ARCHITECTURE rom_memory_a OF rom_memory IS
-- synthesis translate_off
COMPONENT wrapped_rom_memory
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rom_memory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 16,
c_addrb_width => 16,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "rom_memory.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 57775,
c_read_depth_b => 57775,
c_read_width_a => 9,
c_read_width_b => 9,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 57775,
c_write_depth_b => 57775,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 9,
c_write_width_b => 9,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rom_memory
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END rom_memory_a;
| gpl-3.0 |
aospan/NetUP_Dual_Universal_CI-fpga | dvb_ts_shaper.vhd | 1 | 5161 | -- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity dvb_ts_shaper is
generic (
FIFO_DEPTH : natural := 16384
);
port (
-- system domain
rst : in std_logic;
clk : in std_logic;
-- test
bypass_test : in std_logic;
--
clkdiv : in std_logic_vector(3 downto 0);
--
dvb_indrdy : out std_logic;
dvb_indata : in std_logic_vector(7 downto 0);
dvb_indsop : in std_logic;
dvb_indval : in std_logic;
-- stream domain
dvb_clk : in std_logic;
--
dvb_out_clk : out std_logic;
dvb_out_data : out std_logic_vector(7 downto 0);
dvb_out_dval : out std_logic;
dvb_out_dsop : out std_logic
);
end entity;
architecture rtl of dvb_ts_shaper is
attribute ramstyle : string;
type mem_t is array(0 to FIFO_DEPTH - 1) of std_logic_vector(8 downto 0);
constant RAM_ADDR_MSB : natural := ulen(FIFO_DEPTH - 1) - 1;
constant FIFO_PTR_MSB : natural := RAM_ADDR_MSB + 1;
signal fifo_ram : mem_t;
attribute ramstyle of fifo_ram : signal is "M9K, no_rw_check";
signal ram_wr_addr : unsigned(RAM_ADDR_MSB downto 0);
signal ram_rd_addr : unsigned(RAM_ADDR_MSB downto 0);
signal fifo_wr_ptr : std_logic_vector(ram_wr_addr'length downto 0);
signal fifo_rd_ptr : std_logic_vector(ram_rd_addr'length downto 0);
signal fifo_wr_ptr_sync : std_logic_vector(fifo_wr_ptr'range);
signal fifo_rd_ptr_sync : std_logic_vector(fifo_rd_ptr'range);
signal fifo_we : std_logic;
signal fifo_re : std_logic;
signal fifo_fill : unsigned(RAM_ADDR_MSB downto 0);
signal dvb_out_clk_edge : std_logic;
signal dvb_out_clk_cnt : signed(clkdiv'length downto 0);
signal fifo_ram_latch : std_logic_vector(8 downto 0);
signal fifo_ram_latch_valid : std_logic;
signal fifo_ram_latch_clk : std_logic;
signal fifo_ram_reg : std_logic_vector(8 downto 0);
signal fifo_ram_reg_valid : std_logic;
signal fifo_ram_reg_clk : std_logic;
signal dvb_out_clk_en : std_logic;
signal dvb_rst_meta : std_logic;
signal dvb_rst_sync : std_logic;
begin
assert (to_unsigned(FIFO_DEPTH, RAM_ADDR_MSB + 2) and to_unsigned(FIFO_DEPTH - 1, RAM_ADDR_MSB + 2)) = 0
report "FIFO_DEPTH must be power of two!";
WR_PTR : entity work.afifo_ptr
generic map (
PTR_WIDTH => ram_wr_addr'length + 1
)
port map (
rst => rst,
clk => clk,
clk_en => fifo_we,
--
ptr => fifo_wr_ptr,
addr => ram_wr_addr,
--
ptr_async => fifo_rd_ptr,
ptr_sync => fifo_rd_ptr_sync
);
RD_PTR : entity work.afifo_ptr
generic map (
PTR_WIDTH => ram_rd_addr'length + 1
)
port map (
rst => not dvb_rst_sync,
clk => dvb_clk,
clk_en => fifo_re,
--
ptr => fifo_rd_ptr,
addr => ram_rd_addr,
--
ptr_async => fifo_wr_ptr,
ptr_sync => fifo_wr_ptr_sync
);
fifo_we <= fifo_not_full(fifo_wr_ptr, fifo_rd_ptr_sync) and dvb_indval;
fifo_re <= fifo_not_empty(fifo_wr_ptr_sync, fifo_rd_ptr) and (fifo_ram_latch_clk and dvb_out_clk_edge) and not bypass_test;
fifo_fill <= fifo_water_level(fifo_wr_ptr, fifo_rd_ptr_sync);
process (rst, clk)
begin
if rising_edge(clk) then
if fifo_fill(fifo_fill'left) nor fifo_fill(fifo_fill'left - 1) then
dvb_indrdy <= '1';
elsif fifo_fill(fifo_fill'left) and fifo_fill(fifo_fill'left - 1) then
dvb_indrdy <= '0';
end if;
if fifo_we then
fifo_ram(to_integer(ram_wr_addr)) <= dvb_indsop & dvb_indata;
end if;
end if;
if rst then
dvb_indrdy <= '0';
end if;
end process;
process (rst, dvb_rst_sync, dvb_clk)
begin
if rising_edge(dvb_clk) then
dvb_rst_meta <= '1';
dvb_rst_sync <= dvb_rst_meta;
--
if dvb_out_clk_cnt = to_signed(-2, dvb_out_clk_cnt'length) then
dvb_out_clk_edge <= '1';
else
dvb_out_clk_edge <= '0';
end if;
if dvb_out_clk_edge then
dvb_out_clk_cnt <= signed('0' & clkdiv);
else
dvb_out_clk_cnt <= dvb_out_clk_cnt - 1;
end if;
--
fifo_ram_latch <= fifo_ram(to_integer(ram_rd_addr));
fifo_ram_latch_clk <= fifo_ram_latch_clk xor dvb_out_clk_edge;
fifo_ram_latch_valid <= fifo_re;
--
fifo_ram_reg <= fifo_ram_latch;
fifo_ram_reg_valid <= fifo_ram_latch_valid;
fifo_ram_reg_clk <= fifo_ram_latch_clk;
--
dvb_out_clk_en <= fifo_ram_reg_clk and not fifo_ram_latch_clk;
dvb_out_clk <= fifo_ram_reg_clk and not bypass_test;
if dvb_out_clk_en then
dvb_out_dval <= fifo_ram_reg_valid;
dvb_out_data <= fifo_ram_reg(7 downto 0);
dvb_out_dsop <= fifo_ram_reg(8);
end if;
end if;
if rst then
dvb_rst_meta <= '0';
dvb_rst_sync <= '0';
end if;
if not dvb_rst_sync then
dvb_out_clk_edge <= '0';
dvb_out_clk_cnt <= (others => '0');
--
fifo_ram_latch_clk <= '0';
fifo_ram_latch_valid <= '0';
--
fifo_ram_reg <= (others => '0');
fifo_ram_reg_valid <= '0';
fifo_ram_reg_clk <= '0';
--
dvb_out_clk_en <= '0';
dvb_out_clk <= '0';
dvb_out_dval <= '0';
dvb_out_data <= (others => '0');
dvb_out_dsop <= '0';
end if;
end process;
end architecture;
| gpl-3.0 |
arthurbenemann/fpga-bits | undocumented/DCM_clock/ipcore_dir/my_dcm/example_design/my_dcm_exdes.vhd | 1 | 5388 | -- file: my_dcm_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity my_dcm_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end my_dcm_exdes;
architecture xilinx of my_dcm_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal clk_n : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component my_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : my_dcm
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int);
clk_n <= not clk;
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(1),
C0 => clk,
C1 => clk_n,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
| gpl-3.0 |
aospan/NetUP_Dual_Universal_CI-fpga | afifo_ptr.vhd | 1 | 1968 | -- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity afifo_ptr is
generic (
PTR_WIDTH : natural range 3 to natural'high
);
port (
rst : in std_logic;
clk : in std_logic;
clk_en : in std_logic;
--
ptr : out std_logic_vector(PTR_WIDTH - 1 downto 0); -- FIFO pointer (use for crossing clock domains)
addr : out unsigned(PTR_WIDTH - 2 downto 0); -- FIFO ram address
--
ptr_async : in std_logic_vector(PTR_WIDTH - 1 downto 0);
ptr_sync : out std_logic_vector(PTR_WIDTH - 1 downto 0)
);
end entity;
architecture rtl of afifo_ptr is
signal gray_aux : std_logic;
signal gray_i : std_logic_vector(PTR_WIDTH - 1 downto 0);
signal addr_h : std_logic;
signal ptr_meta : std_logic_vector(PTR_WIDTH - 1 downto 0);
begin
process (rst, clk)
variable toggle : std_logic;
variable carry : std_logic;
variable nxtbt : std_logic;
begin
if rising_edge(clk) then
ptr_meta <= ptr_async;
ptr_sync <= ptr_meta;
--
if clk_en then
-- invert parity
gray_aux <= not gray_aux;
-- proceed with bits from 0 to PTR - 2
toggle := not gray_aux;
carry := gray_aux;
for i in 0 to PTR_WIDTH - 2 loop
nxtbt := gray_i(i) xor toggle;
toggle := carry and gray_i(i);
carry := carry and not gray_i(i);
gray_i(i) <= nxtbt;
end loop;
-- proceed with last bit
toggle := toggle or carry;
gray_i(PTR_WIDTH - 1) <= gray_i(PTR_WIDTH - 1) xor toggle;
addr_h <= nxtbt xor gray_i(PTR_WIDTH - 1) xor toggle;
end if;
end if;
if rst then
ptr_meta <= (others => '0');
ptr_sync <= (others => '0');
--
gray_aux <= '0';
gray_i <= (others => '0');
addr_h <= '0';
end if;
end process;
ptr <= gray_i;
addr <= unsigned(addr_h & gray_i(PTR_WIDTH - 3 downto 0));
end architecture;
| gpl-3.0 |
aospan/NetUP_Dual_Universal_CI-fpga | dvb_dma_fifo_ram.vhd | 1 | 9766 | -- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: dvb_dma_fifo_ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dvb_dma_fifo_ram IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
rdclock : IN STD_LOGIC ;
rdclocken : IN STD_LOGIC := '1';
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END dvb_dma_fifo_ram;
ARCHITECTURE SYN OF dvb_dma_fifo_ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (63 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_b : STRING;
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
clocken1 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock1 : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(63 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
intended_device_family => "Cyclone IV GX",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 128,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
widthad_a => 10,
widthad_b => 7,
width_a => 8,
width_b => 64,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => wrclock,
clocken1 => rdclocken,
data_a => data,
wren_a => wren,
address_b => rdaddress,
clock1 => rdclock,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "1"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "NORMAL"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 7 0 INPUT NODEFVAL "rdaddress[6..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: rdclocken 0 0 0 0 INPUT VCC "rdclocken"
-- Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 7 0 rdaddress 0 0 7 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @clocken1 0 0 0 0 rdclocken 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_dma_fifo_ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_dma_fifo_ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_dma_fifo_ram.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_dma_fifo_ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dvb_dma_fifo_ram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 |
aospan/NetUP_Dual_Universal_CI-fpga | ci_bridge.vhd | 1 | 13092 | -- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ci_bridge is
port (
clk : in std_logic;
rst : in std_logic;
-- CI control port (avalon-MM slave)
address : in std_logic_vector(1 downto 0);
byteenable : in std_logic_vector(1 downto 0);
writedata : in std_logic_vector(15 downto 0);
write : in std_logic;
readdata : out std_logic_vector(15 downto 0);
interrupt : out std_logic;
-- CI data port (avalon-MM slave)
cam_address : in std_logic_vector(17 downto 0);
cam_writedata : in std_logic_vector(7 downto 0);
cam_write : in std_logic;
cam_readdata : out std_logic_vector(7 downto 0);
cam_read : in std_logic;
cam_waitreq : out std_logic;
cam_interrupts : out std_logic_vector(1 downto 0);
-- conduit (CI bus)
cia_reset : out std_logic;
cib_reset : out std_logic;
cia_ce_n : out std_logic;
cib_ce_n : out std_logic;
ci_reg_n : out std_logic;
ci_a : out std_logic_vector(14 downto 0);
ci_d_out : out std_logic_vector(7 downto 0);
ci_d_in : in std_logic_vector(7 downto 0);
ci_d_en : out std_logic;
ci_we_n : out std_logic;
ci_oe_n : out std_logic;
ci_iowr_n : out std_logic;
ci_iord_n : out std_logic;
cia_wait_n : in std_logic;
cib_wait_n : in std_logic;
cia_ireq_n : in std_logic;
cib_ireq_n : in std_logic;
cia_cd_n : in std_logic_vector(1 downto 0);
cib_cd_n : in std_logic_vector(1 downto 0);
-- conduit (CI bus helpers)
cia_overcurrent_n : in std_logic;
cib_overcurrent_n : in std_logic;
cia_reset_buf_oe_n : out std_logic;
cib_reset_buf_oe_n : out std_logic;
cia_data_buf_oe_n : out std_logic;
cib_data_buf_oe_n : out std_logic;
ci_bus_dir : out std_logic;
-- conduit (CAM status)
cam0_ready : out std_logic;
cam0_fail : out std_logic;
cam0_bypass : out std_logic;
cam1_ready : out std_logic;
cam1_fail : out std_logic;
cam1_bypass : out std_logic
);
end entity;
architecture rtl of ci_bridge is
constant BIT_CAM0_STCHG : natural := 0;
constant BIT_CAM0_PRESENT : natural := 1;
constant BIT_CAM0_RESET : natural := 2;
constant BIT_CAM0_BYPASS : natural := 3;
constant BIT_CAM0_READY : natural := 4;
constant BIT_CAM0_ERROR : natural := 5;
constant BIT_CAM0_OVERCURR : natural := 6;
constant BIT_CAM0_BUSY : natural := 7;
constant BIT_CAM1_STCHG : natural := 8;
constant BIT_CAM1_PRESENT : natural := 9;
constant BIT_CAM1_RESET : natural := 10;
constant BIT_CAM1_BYPASS : natural := 11;
constant BIT_CAM1_READY : natural := 12;
constant BIT_CAM1_ERROR : natural := 13;
constant BIT_CAM1_OVERCURR : natural := 14;
constant BIT_CAM1_BUSY : natural := 15;
signal scratchpad_reg : std_logic_vector(15 downto 0);
signal status_reg : std_logic_vector(15 downto 0);
signal ci_timeout_cnt : unsigned(9 downto 0);
alias ci_access_cnt is ci_timeout_cnt(4 downto 0);
signal cia_ce_i : std_logic;
signal cib_ce_i : std_logic;
signal ci_iord_i : std_logic;
signal ci_iowr_i : std_logic;
signal ci_oe_i : std_logic;
signal ci_we_i : std_logic;
signal ci_d_latch : std_logic_vector(7 downto 0);
signal cia_data_buf_oe_i : std_logic;
signal cib_data_buf_oe_i : std_logic;
signal cam_ready : std_logic;
signal cia_wait_meta : std_logic;
signal cia_wait : std_logic;
signal cib_wait_meta : std_logic;
signal cib_wait : std_logic;
signal ci_access_io : std_logic;
signal ci_access_read : std_logic;
signal ci_state_idle_n : std_logic;
signal ci_state_access : std_logic;
signal ci_state_wait : std_logic;
signal ci_state_ack : std_logic;
signal ci_state_hold : std_logic;
signal ci_evt_error : std_logic;
signal ci_oe_start : std_logic;
signal ci_oe_end : std_logic;
signal ci_we_start : std_logic;
signal ci_we_end : std_logic;
signal ci_iord_start : std_logic;
signal ci_iord_end : std_logic;
signal ci_iowr_start : std_logic;
signal ci_iowr_end : std_logic;
signal bus_oe_start : std_logic;
signal cam0_soft_rst : std_logic;
signal cam0_stschg_ack : std_logic;
signal cia_timeout : std_logic;
signal cam1_soft_rst : std_logic;
signal cam1_stschg_ack : std_logic;
signal cib_timeout : std_logic;
signal cam0_stschg : std_logic;
signal cam0_present : std_logic;
signal cam0_reset : std_logic;
signal cam0_bypass_n : std_logic;
signal cam0_ready_i : std_logic;
signal cam0_error : std_logic;
signal cam0_ovcp : std_logic;
signal cam0_busy : std_logic;
signal cam1_stschg : std_logic;
signal cam1_present : std_logic;
signal cam1_reset : std_logic;
signal cam1_bypass_n : std_logic;
signal cam1_ready_i : std_logic;
signal cam1_error : std_logic;
signal cam1_ovcp : std_logic;
signal cam1_busy : std_logic;
begin
status_reg <= (
BIT_CAM0_STCHG => cam0_stschg,
BIT_CAM0_PRESENT => cam0_present,
BIT_CAM0_RESET => cam0_reset,
BIT_CAM0_BYPASS => not cam0_bypass_n,
BIT_CAM0_READY => cam0_ready_i,
BIT_CAM0_ERROR => cam0_error,
BIT_CAM0_OVERCURR => cam0_ovcp,
BIT_CAM0_BUSY => cam0_busy,
--
BIT_CAM1_STCHG => cam1_stschg,
BIT_CAM1_PRESENT => cam1_present,
BIT_CAM1_RESET => cam1_reset,
BIT_CAM1_BYPASS => not cam1_bypass_n,
BIT_CAM1_READY => cam1_ready_i,
BIT_CAM1_ERROR => cam1_error,
BIT_CAM1_OVERCURR => cam1_ovcp,
BIT_CAM1_BUSY => cam1_busy
);
readdata <= scratchpad_reg when address(1) else status_reg;
interrupt <= cam0_stschg or cam1_stschg;
cam_waitreq <= not cam_ready;
cam0_soft_rst <= write and byteenable(BIT_CAM0_RESET / 8) and writedata(BIT_CAM0_RESET) and (address(0) nor address(1));
cam0_stschg_ack <= write and byteenable(BIT_CAM0_STCHG / 8) and writedata(BIT_CAM0_STCHG) and address(0) and not address(1);
cia_timeout <= ci_evt_error and cia_ce_i;
cam1_soft_rst <= write and byteenable(BIT_CAM1_RESET / 8) and writedata(BIT_CAM1_RESET) and (address(0) nor address(1));
cam1_stschg_ack <= write and byteenable(BIT_CAM1_STCHG / 8) and writedata(BIT_CAM1_STCHG) and address(0) and not address(1);
cib_timeout <= ci_evt_error and cib_ce_i;
cam0_fail <= cam0_error or cam0_ovcp;
cam0_ready <= cam0_ready_i;
cam0_bypass <= not cam0_bypass_n;
cam1_fail <= cam1_error or cam1_ovcp;
cam1_ready <= cam1_ready_i;
cam1_bypass <= not cam1_bypass_n;
CI_CTRL_0 : entity work.ci_control
port map (
rst => rst,
clk => clk,
--
soft_reset => cam0_soft_rst,
stschg_ack => cam0_stschg_ack,
ci_timeout => cia_timeout,
--
ci_cd_n => cia_cd_n,
ci_reset => cia_reset,
ci_reset_oe_n => cia_reset_buf_oe_n,
ci_overcurrent_n => cia_overcurrent_n,
ci_ireq_n => cia_ireq_n,
--
cam_stschg => cam0_stschg,
cam_present => cam0_present,
cam_reset => cam0_reset,
cam_ready => cam0_ready_i,
cam_error => cam0_error,
cam_ovcp => cam0_ovcp,
cam_busy => cam0_busy,
cam_interrupt => cam_interrupts(0)
);
CI_CTRL_1 : entity work.ci_control
port map (
rst => rst,
clk => clk,
--
soft_reset => cam1_soft_rst,
stschg_ack => cam1_stschg_ack,
ci_timeout => cib_timeout,
--
ci_cd_n => cib_cd_n,
ci_reset => cib_reset,
ci_reset_oe_n => cib_reset_buf_oe_n,
ci_overcurrent_n => cib_overcurrent_n,
ci_ireq_n => cib_ireq_n,
--
cam_stschg => cam1_stschg,
cam_present => cam1_present,
cam_reset => cam1_reset,
cam_ready => cam1_ready_i,
cam_error => cam1_error,
cam_ovcp => cam1_ovcp,
cam_busy => cam1_busy,
cam_interrupt => cam_interrupts(1)
);
ci_oe_start <= not ci_state_access and not ci_access_io and ci_access_read when ci_access_cnt = 1 else '0';
ci_oe_end <= not ci_state_wait and ci_oe_i when ci_access_cnt = 16 else '0';
ci_we_start <= not ci_state_access and not ci_access_io and not ci_access_read when ci_access_cnt = 1 else '0';
ci_we_end <= not ci_state_wait and ci_we_i when ci_access_cnt = 11 else '0';
ci_iord_start <= not ci_state_access and ci_access_io and ci_access_read when ci_access_cnt = 4 else '0';
ci_iord_end <= not ci_state_wait and ci_iord_i when ci_access_cnt = 13 else '0';
ci_iowr_start <= not ci_state_access and ci_access_io and not ci_access_read when ci_access_cnt = 7 else '0';
ci_iowr_end <= not ci_state_wait and ci_iowr_i when ci_access_cnt = 16 else '0';
bus_oe_start <= ci_access_read when ci_access_cnt = 1 else not ci_access_read when ci_access_cnt = 3 else '0';
process (rst, clk)
begin
if rising_edge(clk) then
if write and address(1) then
if byteenable(0) then
scratchpad_reg(7 downto 0) <= writedata(7 downto 0);
end if;
if byteenable(1) then
scratchpad_reg(15 downto 8) <= writedata(15 downto 8);
end if;
end if;
if not cam0_present then
cam0_bypass_n <= '0';
elsif write and byteenable(BIT_CAM0_BYPASS / 8) and writedata(BIT_CAM0_BYPASS) and not address(1) then
cam0_bypass_n <= address(0);
end if;
if not cam1_present then
cam1_bypass_n <= '0';
elsif write and byteenable(BIT_CAM1_BYPASS / 8) and writedata(BIT_CAM1_BYPASS) and not address(1) then
cam1_bypass_n <= address(0);
end if;
--
ci_d_latch <= ci_d_in;
--
cia_wait_meta <= not cia_wait_n;
cia_wait <= cia_wait_meta;
cib_wait_meta <= not cib_wait_n;
cib_wait <= cib_wait_meta;
-- CI main timer
if not ci_state_idle_n then
ci_timeout_cnt <= (others => '0');
else
ci_timeout_cnt <= ci_timeout_cnt + 1;
end if;
-- CI events
if ci_timeout_cnt = 750 then
ci_evt_error <= '1';
else
ci_evt_error <= '0';
end if;
cam_ready <= (ci_state_ack or ci_evt_error) and not ci_state_hold;
-- state machine
if cam_ready then
ci_state_idle_n <= '0';
elsif not ci_state_idle_n then
ci_state_idle_n <= cam_read or cam_write;
end if;
if not ci_state_idle_n then
ci_state_access <= '0';
elsif ci_oe_start or ci_we_start or ci_iord_start or ci_iowr_start then
ci_state_access <= '1';
end if;
if not ci_state_idle_n then
ci_state_wait <= '0';
elsif ci_oe_end or ci_we_end or ci_iord_end or ci_iowr_end then
ci_state_wait <= '1';
end if;
if not ci_state_idle_n then
ci_state_ack <= '0';
elsif not ci_state_ack then
ci_state_ack <= ci_state_wait and ((cia_wait and cia_ce_i) nor (cib_wait and cib_ce_i));
end if;
if not ci_state_idle_n then
ci_state_hold <= '0';
elsif not ci_state_hold then
ci_state_hold <= ci_evt_error or ci_state_ack;
end if;
--
if not ci_state_idle_n then
cia_ce_i <= (cam_read or cam_write) and not cam_address(17);
cib_ce_i <= (cam_read or cam_write) and cam_address(17);
end if;
if not ci_state_idle_n and (cam_read or cam_write) then
ci_reg_n <= cam_address(16);
ci_a <= cam_address(14 downto 0);
ci_d_out <= cam_writedata;
ci_access_io <= cam_address(15) and not cam_address(16);
ci_access_read <= cam_read;
end if;
if not ci_state_idle_n then
cam_readdata <= (others => '1');
elsif ci_state_ack and not ci_state_hold then
cam_readdata <= ci_d_latch;
end if;
-- Data direction control
ci_d_en <= ci_state_idle_n and not ci_access_read;
ci_bus_dir <= ci_access_read;
cia_data_buf_oe_i <= ci_state_idle_n and cia_ce_i and (cia_data_buf_oe_i or bus_oe_start);
cib_data_buf_oe_i <= ci_state_idle_n and cib_ce_i and (cib_data_buf_oe_i or bus_oe_start);
--
if ci_oe_start then
ci_oe_i <= '1';
elsif ci_state_ack or ci_evt_error then
ci_oe_i <= '0';
end if;
if ci_we_start then
ci_we_i <= '1';
elsif ci_state_ack or ci_evt_error then
ci_we_i <= '0';
end if;
if ci_iord_start then
ci_iord_i <= '1';
elsif ci_state_ack or ci_evt_error then
ci_iord_i <= '0';
end if;
if ci_iowr_start then
ci_iowr_i <= '1';
elsif ci_state_ack or ci_evt_error then
ci_iowr_i <= '0';
end if;
end if;
if rst then
scratchpad_reg <= (others => '0');
cam0_bypass_n <= '0';
cam1_bypass_n <= '0';
--
ci_d_latch <= (others => '0');
cia_wait_meta <= '0';
cia_wait <= '0';
cib_wait_meta <= '0';
cib_wait <= '0';
--
ci_timeout_cnt <= (others => '0');
ci_access_io <= '0';
ci_access_read <= '0';
ci_evt_error <= '0';
--
ci_state_idle_n <= '0';
ci_state_access <= '0';
ci_state_wait <= '0';
ci_state_ack <= '0';
ci_state_hold <= '0';
--
cam_ready <= '0';
cam_readdata <= (others => '0');
--
cia_ce_i <= '0';
cib_ce_i <= '0';
ci_reg_n <= '0';
ci_a <= (others => '0');
ci_d_out <= (others => '0');
ci_d_en <= '0';
ci_bus_dir <= '0';
cia_data_buf_oe_i <= '0';
cib_data_buf_oe_i <= '0';
ci_oe_i <= '0';
ci_we_i <= '0';
ci_iord_i <= '0';
ci_iowr_i <= '0';
end if;
end process;
cia_ce_n <= not cia_ce_i;
cib_ce_n <= not cib_ce_i;
ci_oe_n <= not ci_oe_i;
ci_we_n <= not ci_we_i;
ci_iord_n <= not ci_iord_i;
ci_iowr_n <= not ci_iowr_i;
cia_data_buf_oe_n <= not cia_data_buf_oe_i;
cib_data_buf_oe_n <= not cib_data_buf_oe_i;
end architecture;
| gpl-3.0 |
aospan/NetUP_Dual_Universal_CI-fpga | dma_arbiter.vhd | 1 | 3136 | -- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_arbiter is
generic (
MEM_ADDR_WIDTH : natural := 31
);
port (
rst : in std_logic;
clk : in std_logic;
-- dma port #0
dma0_addr : in std_logic_vector(63 downto 3);
dma0_byteen : in std_logic_vector(7 downto 0);
dma0_size : in std_logic_vector(6 downto 0);
dma0_wrdata : in std_logic_vector(63 downto 0);
dma0_write : in std_logic;
dma0_wait : out std_logic;
-- dma port #1
dma1_addr : in std_logic_vector(63 downto 3);
dma1_byteen : in std_logic_vector(7 downto 0);
dma1_size : in std_logic_vector(6 downto 0);
dma1_wrdata : in std_logic_vector(63 downto 0);
dma1_write : in std_logic;
dma1_wait : out std_logic;
-- memory port
mem_addr : out std_logic_vector(MEM_ADDR_WIDTH - 1 downto 0);
mem_byteen : out std_logic_vector(7 downto 0);
mem_size : out std_logic_vector(6 downto 0);
mem_wrdata : out std_logic_vector(63 downto 0);
mem_write : out std_logic;
mem_waitreq : in std_logic
);
end;
architecture rtl of dma_arbiter is
signal burst_cnt : signed(mem_size'left + 1 downto 0);
signal mem_addr_i : std_logic_vector(63 downto 3);
signal secondary : std_logic;
signal dma0_grant : std_logic;
signal dma1_grant : std_logic;
alias burst : std_logic is burst_cnt(burst_cnt'left);
begin
dma0_grant <= burst and not secondary;
dma1_grant <= burst and secondary;
dma0_wait <= mem_waitreq or not dma0_grant;
dma1_wait <= mem_waitreq or not dma1_grant;
mem_wrdata <= (dma0_wrdata and (dma0_wrdata'range => dma0_grant)) or (dma1_wrdata and (dma1_wrdata'range => dma1_grant));
mem_write <= (dma0_write and dma0_grant) or (dma1_write and dma1_grant);
mem_size <= (dma0_size and (dma0_size'range => dma0_grant)) or (dma1_size and (dma1_size'range => dma1_grant));
mem_addr_i <= (dma0_addr and (dma0_addr'range => dma0_grant)) or (dma1_addr and (dma1_addr'range => dma1_grant));
mem_byteen <= (dma0_byteen and (dma0_byteen'range => dma0_grant)) or (dma1_byteen and (dma1_byteen'range => dma1_grant));
mem_addr <= mem_addr_i(mem_addr'left downto 3) & "000";
process (rst, clk)
variable burst_step : std_logic;
variable burst_en0 : std_logic;
variable burst_en1 : std_logic;
begin
if rising_edge(clk) then
burst_step := burst and ((dma0_write and not secondary) or (dma1_write and secondary)) and not mem_waitreq;
burst_en0 := not burst and dma0_write and (not dma1_write or secondary);
burst_en1 := not burst and dma1_write and (dma0_write nand secondary);
--
if burst_en0 then
burst_cnt <= signed('1' & not dma0_size) + 1;
elsif burst_en1 then
burst_cnt <= signed('1' & not dma1_size) + 1;
elsif burst_step then
burst_cnt <= burst_cnt + 1;
end if;
--
if burst_en1 then
secondary <= '1';
elsif burst_en0 then
secondary <= '0';
end if;
end if;
if rst then
burst_cnt <= (others => '0');
secondary <= '0';
end if;
end process;
end;
| gpl-3.0 |
UviDTE-UviSpace/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/avalon_write_bridge.vhd | 2 | 1655 | ---Avalon Bridge
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all; -- For using ceil and log2.
use IEEE.NUMERIC_STD.all; -- For using to_unsigned.
use ieee.std_logic_unsigned.all; -- Needed for the sum used in counter.
ENTITY avalon_write_bridge IS
GENERIC (
DATA_SIZE : integer := 32;
ADDRESS_SIZE : integer := 32;
BURSCOUNT_SIZE : integer := 7
);
PORT (
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
--avalon master
avm_write_address : OUT STD_LOGIC_VECTOR((ADDRESS_SIZE-1) downto 0);
avm_write_write : OUT STD_LOGIC;
avm_write_byteenable : OUT STD_LOGIC_VECTOR(((DATA_SIZE/8)-1) downto 0);
avm_write_writedata : OUT STD_LOGIC_VECTOR((DATA_SIZE-1) downto 0);
avm_write_waitrequest: IN STD_LOGIC;
avm_write_burstcount : OUT STD_LOGIC_VECTOR((BURSCOUNT_SIZE-1) downto 0);
--avalon slave
avs_write_address : IN STD_LOGIC_VECTOR((ADDRESS_SIZE-1) downto 0);
avs_write_write : IN STD_LOGIC;
avs_write_byteenable : IN STD_LOGIC_VECTOR(((DATA_SIZE/8)-1) downto 0);
avs_write_writedata : IN STD_LOGIC_VECTOR((DATA_SIZE-1) downto 0);
avs_write_waitrequest: OUT STD_LOGIC;
avs_write_burstcount : IN STD_LOGIC_VECTOR((BURSCOUNT_SIZE-1) downto 0)
);
END avalon_write_bridge;
ARCHITECTURE arch OF avalon_write_bridge IS
BEGIN
avm_write_address <= avs_write_address;
avm_write_write <= avs_write_write;
avm_write_byteenable <= avs_write_byteenable;
avm_write_writedata <= avs_write_writedata;
avs_write_waitrequest <= avm_write_waitrequest;
avm_write_burstcount <= avs_write_burstcount;
END arch; | gpl-3.0 |
JosiCoder/CtLab | FPGA/FPGA SigGen/Testbenches/PulseGenerator_Tester.vhd | 1 | 4383 | --------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests the pulse generator.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PulseGenerator_Tester is
end entity;
architecture stdarch of PulseGenerator_Tester is
--------------------
-- Constants
--------------------
constant counter_width: natural := 32;
constant clk_period: time := 5ns;
constant test_high_duration: unsigned(counter_width-1 downto 0) := to_unsigned(16, counter_width);
constant test_low_duration: unsigned(counter_width-1 downto 0) := to_unsigned(8, counter_width);
--------------------
-- Inputs
--------------------
signal clk: std_logic := '0';
signal high_duration: unsigned(counter_width-1 downto 0) := test_high_duration;
signal low_duration: unsigned(counter_width-1 downto 0) := test_low_duration;
--------------------
-- Outputs
--------------------
signal pulse_signal: std_logic;
--------------------
-- Internals
--------------------
signal run_test: boolean := true;
begin
--------------------------------------------------------------------------------
-- UUT instantiation.
--------------------------------------------------------------------------------
uut: entity work.PulseGenerator
generic map
(
counter_width => counter_width
)
port map
(
clk => clk,
high_duration => high_duration,
low_duration => low_duration,
pulse_signal => pulse_signal
);
--------------------------------------------------------------------------------
-- UUT stimulation.
--------------------------------------------------------------------------------
-- Generates the system clock.
clk <= not clk after clk_period/2 when run_test;
-- Stimulates and controls the UUT and the tests at all.
stimulus: process is
begin
-- Do the tests for the specified duration.
wait for 5 * (to_integer(test_high_duration) + to_integer(test_low_duration)) * clk_period;
-- Stop the tests.
run_test <= false;
wait;
end process;
--------------------------------------------------------------------------------
-- Specifications.
--------------------------------------------------------------------------------
-- Verifies proper frequency signal generation.
must_create_correct_pulse_signal: process is
variable startup: boolean := true;
begin
-- Wait for the pulse generator to settle down after powered up.
if startup then
wait until rising_edge(pulse_signal);
wait until falling_edge(pulse_signal);
startup := false;
end if;
-- Verify the correct duration of high and the low phase.
for i in 1 to to_integer(test_low_duration) loop
wait until falling_edge(clk);
assert (pulse_signal = '0') report "Signal not set or held to '0'." severity error;
end loop;
for i in 1 to to_integer(test_high_duration) loop
wait until falling_edge(clk);
assert (pulse_signal = '1') report "Signal not set or held to '1'." severity error;
end loop;
end process;
end architecture;
| gpl-3.0 |
josemonsalve2/cpeg324_calculator | vivado/hdl/InstructionsMemory/src/vhdl/new/InstructionsMemory.vhd | 1 | 6201 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/09/2016 02:23:00 PM
-- Design Name:
-- Module Name: InstructionsMemory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--RAM INITIALIZATION CODE TAKEN FROM THE
--XILINX XST User guide for Virtex-4 Virtex-5 Spartan-3 and Newer CPLD Devices
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all; --include package textio.vhd
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstructionsMemory is
generic ( INIT_BRAM_FILE: string );
Port ( clk : in STD_LOGIC;
PC : in STD_LOGIC_VECTOR (7 downto 0);
Instruction : out STD_LOGIC_VECTOR (7 downto 0):=(others => '0');
reset: in STD_LOGIC;
num_instructions: out STD_LOGIC_VECTOR (7 downto 0):= (others => '0')
);
end InstructionsMemory;
architecture Behavioral of InstructionsMemory is
COMPONENT blk_mem_gen_0
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
--- CODE FOR BRAM INITIALIZATION see reference above. Modified
type RamType is array(0 to 256) of bit_vector(7 downto 0);
impure function InitRamFromFile (RamFileName : in string) return RamType is
FILE RamFile : text open READ_MODE is RamFileName;
variable RamFileLine : line;
variable RAM : RamType;
variable I : integer := 0;
begin
while (not endfile(RamFile)) loop
readline ( RamFile, RamFileLine );
read ( RamFileLine, RAM(I) );
I:=I+1;
end loop;
return RAM;
end function;
impure function numInstructions (RamFileName : in string) return std_logic_vector(7 downto 0) is
FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable I : integer := 0;
begin
while (not endfile(RamFile)) loop
readline ( RamFile, RamFileLine );
I:=I+1;
end loop;
return std_logic_vector(to_unsigned(I,8));
end function;
-- Signal for telling the system we are initializing the ram
signal init_ram: STD_LOGIC := '1';
--Ram init state machine and used counters
type type_ram_init_states is (slow_start, writing, finished);
signal ram_init_state : type_ram_init_states := slow_start;
signal RAM_INIT_COUNTER : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal init_counter: unsigned(7 downto 0) := (others => '0');
--Read value from file
signal RAM : RamType := InitRamFromFile(INIT_BRAM_FILE);
-- Signals going to BRAM
signal init_address: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
--BRAM SIGNALS
signal write_enable : STD_LOGIC_VECTOR (0 downto 0) := (others => '1');
signal data_write : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal address : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
-- Other signals
signal s_numInstructions : STD_LOGIC_VECTOR (7 downto 0) := numInstructions(INIT_BRAM_FILE);
begin
--Connections
num_instructions <= s_numInstructions;
bram_0 : blk_mem_gen_0
PORT MAP (
clka => clk,
ena => '1',
wea => write_enable,
addra => address,
dina => data_write,
douta => Instruction
);
with init_ram select address <= PC when '0',
init_address when '1';
init_bram_process: process (clk,reset) is
begin
if (reset = '1') then
init_ram<='1';
ram_init_state <= slow_start;
end if;
if (rising_edge(clk) and init_ram = '1') then
write_enable(0) <= '1';
case ram_init_state is
when slow_start =>
init_counter <= init_counter + 1;
if (init_counter = x"02") then
ram_init_state <= writing;
init_counter <= (others => '0');
end if;
when writing =>
if (RAM_INIT_COUNTER = s_numInstructions) then
ram_init_state <= finished;
else
init_address <= RAM_INIT_COUNTER;
data_write <= to_stdLogicVector(RAM(to_integer(unsigned(RAM_INIT_COUNTER))));
init_counter <= (init_counter + 1);
if (init_counter = x"04") then
RAM_INIT_COUNTER <= RAM_INIT_COUNTER + 1;
init_counter <= (others => '0');
end if;
end if;
when finished =>
RAM_INIT_COUNTER <= (others => '0');
init_counter <= (others => '0');
write_enable(0) <= '0';
init_ram <= '0';
when others =>
end case;
end if;
end process;
instMem_proc: process (reset)
begin
end process;
end Behavioral;
| gpl-3.0 |
josemonsalve2/cpeg324_calculator | vivado/hdl/blk_mem_gen_0/sim/blk_mem_gen_0.vhd | 1 | 12421 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 256,
C_READ_DEPTH_A => 256,
C_ADDRA_WIDTH => 8,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 256,
C_READ_DEPTH_B => 256,
C_ADDRB_WIDTH => 8,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.54005 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| gpl-3.0 |
Dragonturtle/SHERPA | HDL/FPGALink/fx2_interface.vhdl | 1 | 9922 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fx2_interface is
port(
clk_in : in std_logic; -- 48MHz clock from FX2LP
reset_in : in std_logic; -- synchronous active-high reset input
reset_out : out std_logic; -- synchronous active-high reset output
-- FX2LP interface ---------------------------------------------------------------------------
fx2FifoSel_out : out std_logic; -- select FIFO: '0' for EP2OUT, '1' for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic; -- asserted (active-low) when a host read needs to be committed early
-- Channel read/write interface --------------------------------------------------------------
chanAddr_out : out std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
h2fData_out : out std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
h2fValid_out : out std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData_out"
h2fReady_in : in std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
f2hData_in : in std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
f2hValid_in : in std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
f2hReady_out : out std_logic -- '1' means "on the next clock rising edge, put your next byte of data on f2hData_in"
);
end entity;
architecture rtl of fx2_interface is
-- The read/write nomenclature here refers to the FPGA reading and writing the FX2LP FIFOs, and is therefore
-- of the opposite sense to the host's read and write. So host reads are fulfilled in the S_WRITE state, and
-- vice-versa. Apologies for the confusion.
type StateType is (
S_RESET, -- wait for gotData_in to go low when FX2LP enables FIFO mode
S_IDLE, -- wait for requst from host & register chanAddr & isWrite
S_GET_COUNT0, -- register most significant byte of message length
S_GET_COUNT1, -- register least significant byte of message length
S_BEGIN_WRITE, -- switch direction of FX2LP data bus
S_WRITE, -- write data to FX2LP EP6IN FIFO, one byte at a time
S_END_WRITE_ALIGNED, -- end an aligned write (do not assert fx2PktEnd_out)
S_END_WRITE_NONALIGNED, -- end a nonaligned write (assert fx2PktEnd_out)
S_READ -- read data from FX2LP EP2OUT FIFO, one byte at a time
);
constant FIFO_READ : std_logic_vector(1 downto 0) := "10"; -- assert fx2Read_out (active-low)
constant FIFO_WRITE : std_logic_vector(1 downto 0) := "01"; -- assert fx2Write_out (active-low)
constant FIFO_NOP : std_logic_vector(1 downto 0) := "11"; -- assert nothing
constant OUT_FIFO : std_logic := '0'; -- EP2OUT
constant IN_FIFO : std_logic := '1'; -- EP6IN
signal state, state_next : StateType := S_RESET;
signal fifoOp : std_logic_vector(1 downto 0) := "ZZ";
signal count, count_next : unsigned(16 downto 0) := (others => '0'); -- read/write count
signal chanAddr, chanAddr_next : std_logic_vector(6 downto 0) := (others => '0'); -- channel being accessed (0-127)
signal isWrite, isWrite_next : std_logic := '0'; -- is this FX2LP FIFO access a write or a read?
signal isAligned, isAligned_next : std_logic := '0'; -- is this FX2LP FIFO write block-aligned?
signal dataOut : std_logic_vector(7 downto 0); -- data to be driven on fx2Data_io
signal driveBus : std_logic := '0'; -- whether or not to drive fx2Data_io
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_RESET;
count <= (others => '0');
chanAddr <= (others => '0');
isWrite <= '0';
isAligned <= '0';
else
state <= state_next;
count <= count_next;
chanAddr <= chanAddr_next;
isWrite <= isWrite_next;
isAligned <= isAligned_next;
end if;
end if;
end process;
-- Next state logic
process(
state, fx2Data_io, fx2GotData_in, fx2GotRoom_in, count, isAligned, isWrite, chanAddr,
f2hData_in, f2hValid_in, h2fReady_in)
begin
state_next <= state;
count_next <= count;
chanAddr_next <= chanAddr;
isWrite_next <= isWrite; -- is the FPGA writing to the FX2LP?
isAligned_next <= isAligned; -- does this FIFO write end on a block (512-byte) boundary?
dataOut <= (others => '0');
driveBus <= '0'; -- don't drive fx2Data_io by default
fifoOp <= FIFO_READ; -- read the FX2LP FIFO by default
fx2PktEnd_out <= '1'; -- inactive: FPGA does not commit a short packet.
f2hReady_out <= '0';
h2fValid_out <= '0';
reset_out <= '0';
case state is
when S_GET_COUNT0 =>
fx2FifoSel_out <= OUT_FIFO; -- Reading from FX2LP
if ( fx2GotData_in = '1' ) then
-- The count high word high byte will be available on the next clock edge.
count_next(15 downto 8) <= unsigned(fx2Data_io);
state_next <= S_GET_COUNT1;
end if;
when S_GET_COUNT1 =>
fx2FifoSel_out <= OUT_FIFO; -- Reading from FX2LP
if ( fx2GotData_in = '1' ) then
-- The count high word low byte will be available on the next clock edge.
count_next(7 downto 0) <= unsigned(fx2Data_io);
if ( count(15 downto 8) = x"00" and fx2Data_io = x"00" ) then
count_next(16) <= '1';
else
count_next(16) <= '0';
end if;
if ( isWrite = '1' ) then
state_next <= S_BEGIN_WRITE;
else
state_next <= S_READ;
end if;
end if;
when S_BEGIN_WRITE =>
fx2FifoSel_out <= IN_FIFO; -- Writing to FX2LP
fifoOp <= FIFO_NOP;
if ( count(8 downto 0) = "000000000" ) then
isAligned_next <= '1';
else
isAligned_next <= '0';
end if;
state_next <= S_WRITE;
when S_WRITE =>
fx2FifoSel_out <= IN_FIFO; -- Writing to FX2LP
if ( fx2GotRoom_in = '1' ) then
f2hReady_out <= '1';
end if;
if ( fx2GotRoom_in = '1' and f2hValid_in = '1' ) then
fifoOp <= FIFO_WRITE;
dataOut <= f2hData_in;
driveBus <= '1';
count_next <= count - 1;
if ( count = 1 ) then
if ( isAligned = '1' ) then
state_next <= S_END_WRITE_ALIGNED; -- don't assert fx2PktEnd
else
state_next <= S_END_WRITE_NONALIGNED; -- assert fx2PktEnd to commit small packet
end if;
end if;
else
fifoOp <= FIFO_NOP;
end if;
when S_END_WRITE_ALIGNED =>
fx2FifoSel_out <= IN_FIFO; -- Writing to FX2LP
fifoOp <= FIFO_NOP;
state_next <= S_IDLE;
when S_END_WRITE_NONALIGNED =>
fx2FifoSel_out <= IN_FIFO; -- Writing to FX2LP
fifoOp <= FIFO_NOP;
fx2PktEnd_out <= '0'; -- Active: FPGA commits the packet early.
state_next <= S_IDLE;
when S_READ =>
fx2FifoSel_out <= OUT_FIFO; -- Reading from FX2LP
if ( fx2GotData_in = '1' and h2fReady_in = '1') then
-- A data byte will be available on the next clock edge
h2fValid_out <= '1';
count_next <= count - 1;
if ( count = 1 ) then
state_next <= S_IDLE;
end if;
else
fifoOp <= FIFO_NOP;
end if;
-- S_RESET - tri-state everything
when S_RESET =>
reset_out <= '1';
driveBus <= '0';
fifoOp <= "ZZ";
fx2FifoSel_out <= 'Z';
fx2PktEnd_out <= 'Z';
if ( fx2GotData_in = '0' ) then
state_next <= S_IDLE;
end if;
-- S_IDLE and others
when others =>
fx2FifoSel_out <= OUT_FIFO; -- Reading from FX2LP
if ( fx2GotData_in = '1' ) then
-- The read/write flag and a seven-bit channel address will be available on the
-- next clock edge.
chanAddr_next <= fx2Data_io(6 downto 0);
isWrite_next <= fx2Data_io(7);
state_next <= S_GET_COUNT0;
end if;
end case;
end process;
-- Drive stateless signals
fx2Read_out <= fifoOp(0);
fx2Write_out <= fifoOp(1);
chanAddr_out <= chanAddr;
h2fData_out <= fx2Data_io;
fx2Data_io <= dataOut when driveBus = '1' else (others => 'Z');
end architecture;
| gpl-3.0 |
josemonsalve2/cpeg324_calculator | vivado/hdl/blk_mem_gen_0/synth/blk_mem_gen_0.vhd | 1 | 14440 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=256,C_READ_DEPTH_A=256,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=256,C_READ_DEPTH_B=256,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.54005 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 256,
C_READ_DEPTH_A => 256,
C_ADDRA_WIDTH => 8,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 256,
C_READ_DEPTH_B => 256,
C_ADDRB_WIDTH => 8,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.54005 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| gpl-3.0 |
Dragonturtle/SHERPA | HDL/SHERPA/prn_code_generator.vhd | 1 | 2026 | library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all;
entity prn_code_generator is
generic (
idx1 : natural := 1;
idx2 : natural := 5
) ;
port (
enable_in : in std_logic ;
data_in : in std_logic ;
clock_in : in std_logic ;
I_out : out std_logic_vector(7 downto 0) ;
Q_out : out std_logic_vector(7 downto 0) := "00000000"
) ;
end entity ;
architecture arch of prn_code_generator is
alias ena : std_logic is enable_in;
alias clk : std_logic is clock_in;
begin
----------------------------
-- PRN Generation Process --
----------------------------
prncode : process( clk, ena )
variable G1 : bit_vector(14 downto 0) := "111111111111111";
variable G2 : bit_vector(14 downto 0) := "111111111111111";
variable data_q : bit := '0';
variable G1_q : bit := '0';
variable G2_q : bit := '0';
variable counter : natural range 0 to 32767 := 0 ;
begin
if( ena = '0' ) then
I_out <= "10000000" ; -- 0
Q_out <= "10000000" ; -- 0
G1 := "111111111111111";
G2 := "111111111111111";
data_q := '0';
G1_q := '0';
G2_q := '0';
counter := 0;
elsif( rising_edge( clk ) ) then
-------------------------
-- PRN Code Generation --
-------------------------
data_q := (G1(14) xor G2(idx1) xor G2(idx2) xor to_bit(data_in));
if ( data_q = '1' ) then
I_out <= "11111111"; -- 127
else
I_out <= "00000000"; -- -128
end if;
-- G1_q := G1(7) xor G1(4) xor G1(6) xor G1(14);
-- G2_q := G2(1) xor G2(2) xor G2(3) xor G2(5) xor G2(7) xor G2(9) xor G2(10) xor G2(11) xor G2(13) xor G2(14);
G1_q := G1(7) xor G1(14);
G2_q := G2(8) xor G2(10) xor G2(11) xor G2(12) xor G2(13) xor G2(14);
G1(14 downto 1) := G1(13 downto 0);-- sll 1;
G2(14 downto 1) := G2(13 downto 0);-- sll 1;
G1(0) := G1_q;
G2(0) := G2_q;
end if ;
end process ;
end architecture; | gpl-3.0 |
a3f/r3k.vhdl | vhdl/tb/ID_tb.vhdl | 1 | 4370 | -- InstructionDecode Testbench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.txt_utils.all;
-- A testbench has no ports.
entity ID_tb is
end ID_tb;
architecture behav of ID_tb is
component InstructionDecode is
port (instr : in instruction_t;
pc_plus_4 : in addr_t;
jump_addr : out addr_t;
regwrite, link, jumpreg, jumpdirect, branch : out ctrl_t;
memread : out ctrl_memwidth_t;
memtoreg, memsex : out ctrl_t;
memwrite : out ctrl_memwidth_t;
shift, alusrc : out ctrl_t;
aluop : out alu_op_t;
readreg1, readreg2, writereg : out reg_t;
zeroxed, sexed : out word_t;
clk : in std_logic;
rst : in std_logic);
end component;
signal instr : std_logic_vector(31 downto 0); -- instruction_t
signal regwrite, regdst, link, jumpreg, jumpdirect, branch : ctrl_t;
signal memread : ctrl_memwidth_t;
signal memtoreg, memsex : ctrl_t;
signal memwrite : ctrl_memwidth_t;
signal shift, alusrc : ctrl_t;
signal aluop : alu_op_t;
signal pc_plus_4, jump_addr : addr_t;
signal clk, rst : std_logic;
signal readreg1, readreg2 : reg_t;
signal writereg : reg_t;
signal zeroxed, sexed : word_t;
signal done : boolean := false;
constant RIGN : reg_t := "-----";
constant IMMIGN : word_t := "--------------------------------";
begin
ID : InstructionDecode port map(
instr => instr,
pc_plus_4 => pc_plus_4,
jump_addr => jump_addr,
regwrite => regwrite, link => link, jumpreg => jumpreg,
jumpdirect => jumpdirect, branch => branch,
memread => memread,
memtoreg => memtoreg, memsex => memsex,
memwrite => memwrite,
shift => shift, alusrc => alusrc,
aluop => aluop,
readreg1 => readreg1, readreg2 => readreg2,
writereg => writereg,
zeroxed => zeroxed, sexed => sexed,
clk => clk,
rst => rst
);
test: process
variable error : boolean := false;
variable error_count : natural := 0;
type testcase_t is record
instr : instruction_t;
AluOp : alu_op_t;
readreg1, readreg2, writereg : reg_t;
zeroxed, sexed : word_t;
end record;
type testcase_table_t is array (natural range <>) of testcase_t;
constant testcases : testcase_table_t := (
-- Easy arithmetic
(X"3421_ffff", ALU_OR, R1,R1, RIGN, IMMIGN, NEG_ONE), -- ori r1, r1, 0xffff
(X"3428_ffff", ALU_OR, R1,R8, RIGN, IMMIGN, NEG_ONE), -- ori r1, r8, 0xffff
(X"3421_0fff", ALU_OR, R1,R1, RIGN, IMMIGN, X"0000_0fff")
);
begin
for i in testcases'range loop
instr <= testcases(i).instr;
wait for 2 ns;
error := not (AluOp = testcases(i).AluOp
and std_match(readreg1, testcases(i).readreg1)
and std_match(readreg2, testcases(i).readreg2)
and std_match(writereg, testcases(i).writereg)
and std_match(zeroxed, testcases(i).zeroxed)
and std_match(sexed, testcases(i).sexed)
);
if error then
error_count := error_count + 1;
end if;
assert not error report
ANSI_GREEN & "Failure in testcase " & integer'image(i) & ": " &
to_hstring(testcases(i).instr)
& ANSI_NONE severity note;
end loop;
assert error_count /= 0 report
ANSI_GREEN & "Test's over." & ANSI_NONE
severity note;
assert error_count = 0 report
ANSI_RED & integer'image(error_count) & " testcase(s) failed." & ANSI_NONE
severity failure;
-- Wait forever; this will finish the simulation.
done <= true;
wait;
end process;
clkproc: process
begin
clk <= not clk;
wait for 1 ns;
if done then wait; end if;
end process;
end behav;
| gpl-3.0 |
a3f/r3k.vhdl | vhdl/tb/regFile_tb.vhdl | 1 | 3485 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.txt_utils.all;
use work.utils.all;
-- A testbench has no ports.
entity regFile_tb is
end regFile_tb;
architecture behav of regFile_tb is
component regFile is
port (
readreg1, readreg2 : in reg_t;
writereg: in reg_t;
writedata: in word_t;
readData1, readData2 : out word_t;
clk : in std_logic;
rst : in std_logic;
regWrite : in std_logic
);
end component;
signal readreg1, readreg2 : reg_t := R0;
signal writereg: reg_t := R0;
signal writedata: word_t := ZERO;
signal readData1, readData2 : word_t := ZERO;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal regWrite : std_logic := '0';
constant errormsg : string := ANSI_RED & "Testcase failed" & ANSI_NONE;
signal done : boolean := false;
begin
regFile1: regFile
port map(
readreg1 => readreg1, readreg2 => readreg2,
writereg => writereg, writedata => writedata,
readData1 => readData1, readData2 => readData2,
clk => clk, rst => rst,
regWrite => regWrite
);
test: process
begin
wait for 2 ns;
rst <= '1';
wait for 2 ns;
rst <= '0';
wait for 2 ns;
for i in 0 to 30 loop
readreg1 <= toreg(i);
readreg2 <= toreg(i+1);
wait for 2 ns;
assert readdata1 = ZERO and readdata2 = ZERO report
errormsg & ": 0 /= " & to_string(readdata1)
severity error;
end loop;
writereg <= R7;
writedata <= X"01234567";
regWrite <= '1';
wait for 2 ns;
regWrite <= '0';
wait for 2 ns;
readreg1 <= R7;
wait for 2 ns;
assert readdata1 = X"01234567" report
errormsg & to_string(readdata1)
severity error;
readreg1 <= R7;
wait for 2 ns;
assert readdata1 = X"01234567" report
errormsg & to_string(readdata1)
severity error;
writereg <= R0;
writedata <= X"01234567";
regWrite <= '1';
wait for 2 ns;
regWrite <= '0';
wait for 2 ns;
readreg1 <= R7;
wait for 2 ns;
assert readdata1 = X"01234567" report
errormsg & to_string(readdata1)
severity error;
readreg1 <= R0;
wait for 2 ns;
assert readdata1 = X"00000000" report
errormsg & to_string(readdata1)
severity error;
wait for 2 ns;
readreg1 <= R2;
wait for 2 ns;
assert readdata1 = ZERO report
errormsg &": "& to_hstring(readdata1)
severity error;
for i in 0 to 31 loop
writereg <= toreg(i);
writedata <= (31 downto 5 => '0') & toreg(i);
regWrite <= '1';
wait for 2 ns;
end loop;
for i in 0 to 31 loop
readreg1 <= toreg(i);
wait for 2 ns;
assert readData1 = (31 downto 5 => '0') & toreg(i) report
errormsg & ": " & to_string(readData1)
severity error;
end loop;
done <= true;
wait;
end process;
clkproc: process begin
clk <= not clk;
wait for 1 ns;
if done then wait; end if;
end process;
end behav;
| gpl-3.0 |
makestuff/dvr-connectors | conv-24to8/vhdl/conv_24to8.vhdl | 1 | 3150 | --
-- Copyright (C) 2013 Joel Pérez Izquierdo
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Modified from conv_16to8.vhdl by Chris McClelland
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_24to8 is
port(
-- System clock & reset
clk_in : in std_logic;
reset_in : in std_logic;
-- 24-bit data coming in
data24_in : in std_logic_vector(23 downto 0);
valid24_in : in std_logic;
ready24_out : out std_logic;
-- 8-bit data going out
data8_out : out std_logic_vector(7 downto 0);
valid8_out : out std_logic;
ready8_in : in std_logic
);
end entity;
architecture rtl of conv_24to8 is
type StateType is (
S_WRITE_MSB,
S_WRITE_MID,
S_WRITE_LSB
);
signal state : StateType := S_WRITE_MSB;
signal state_next : StateType;
signal lsb : std_logic_vector(7 downto 0) := (others => '0');
signal lsb_next : std_logic_vector(7 downto 0);
signal mid : std_logic_vector(7 downto 0) := (others => '0');
signal mid_next : std_logic_vector(7 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_WRITE_MSB;
lsb <= (others => '0');
mid <= (others => '0');
else
state <= state_next;
lsb <= lsb_next;
mid <= mid_next;
end if;
end if;
end process;
-- Next state logic
process(state, lsb, mid, data24_in, valid24_in, ready8_in)
begin
state_next <= state;
valid8_out <= '0';
lsb_next <= lsb;
mid_next <= mid;
case state is
-- Write the LSB and return to MSB:
when S_WRITE_LSB =>
ready24_out <= '0'; -- not ready for data from 24-bit side
data8_out <= lsb;
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE_MSB;
end if;
-- Write the mid byte and move on to LSB
when S_WRITE_MID =>
ready24_out <= '0'; -- not ready for data from 24-bit side
data8_out <= mid;
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE_LSB;
end if;
-- When a word arrives, write the MSB and move on to mid byte:
when others =>
ready24_out <= ready8_in; -- ready for data from 24-bit side
data8_out <= data24_in(23 downto 16);
valid8_out <= valid24_in;
if ( valid24_in = '1' and ready8_in = '1' ) then
mid_next <= data24_in(15 downto 8);
lsb_next <= data24_in(7 downto 0);
state_next <= S_WRITE_MID;
end if;
end case;
end process;
end architecture;
| gpl-3.0 |
makestuff/vga_test | vhdl/clk_gen/clk_gen_altera.vhdl | 1 | 1084 | --
-- Copyright (C) 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen_wrapper is
port(
clk_in : in std_logic;
clk_out : out std_logic;
locked_out : out std_logic
);
end entity;
architecture structural of clk_gen_wrapper is
begin
clk_gen : entity work.clk_gen
port map(
inclk0 => clk_in,
c0 => clk_out,
locked => locked_out
);
end architecture;
| gpl-3.0 |
a3f/r3k.vhdl | vhdl/io/uart/uart_tx.vhdl | 1 | 3753 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity uart_tx is
port (
clk : in std_logic;
reset : in std_logic;
tx_start : in std_logic;
baud_tick : in std_logic;
tx_data : in std_logic_vector( 7 downto 0 );
tx_done_tick : out std_logic;
tx : out std_logic
);
end entity;
architecture behav of uart_tx is
type STATE is (IDLE, START, DATA, STOP);
signal state_reg : STATE;
signal state_next : STATE;
signal baud_reg : std_logic_vector( 4 downto 0 );
signal baud_next : std_logic_vector( 4 downto 0 );
signal n_reg : std_logic_vector( 4 downto 0 );
signal n_next : std_logic_vector( 4 downto 0 );
signal d_reg : std_logic_vector( 7 downto 0 );
signal d_next : std_logic_vector( 7 downto 0 );
signal tx_reg : std_logic;
signal tx_next : std_logic;
begin
a: process (clk, reset) is
begin
if (reset = '1' ) then
state_reg <= IDLE;
baud_reg <= (others => '0');
n_reg <= (others => '0');
d_reg <= (others => '0');
tx_reg <= '1';
elsif (clk'EVENT and (clk = '1')) then
state_reg <= STATE_NEXT;
baud_reg <= baud_next;
n_reg <= n_next;
d_reg <= d_next;
tx_reg <= tx_next;
end if;
end process;
process
begin
wait ;
state_next <= state_reg;
tx_done_tick <= '0';
baud_next <= baud_reg;
n_next <= n_reg;
d_next <= d_reg;
tx_next <= tx_reg;
case ( state_reg ) is
when
IDLE =>
tx_next <= '1';
if ( tx_start = '1' ) then
state_next <= START;
baud_next <= "00000";
d_next <= tx_data;
end if;
when
START =>
tx_next <= '0';
if ( baud_tick = '1' ) then
baud_next <= vec_increment(baud_reg) ;
else
if ( ( baud_reg = X"10" ) ) then
state_next <= DATA;
baud_next <= "00000";
n_next <= "00000";
end if;
end if;
when
DATA =>
tx_next <= d_reg(0 );
if ( baud_tick = '1' ) then
baud_next <= vec_increment(baud_reg) ;
else
if ( ( baud_reg = X"10" ) ) then
d_next <= std_logic_vector(unsigned(d_reg) srl 1);
baud_next <= "00000";
n_next <= vec_increment(n_reg) ;
else
if ( ( n_reg = X"8" ) ) then
state_next <= STOP;
end if;
end if;
end if;
when
STOP =>
tx_next <= '1';
if ( baud_tick = '1' ) then
baud_next <= vec_increment(baud_reg) ;
else
if ( ( baud_reg = X"10" ) ) then
state_next <= IDLE;
tx_done_tick <= '1';
end if;
end if;
end case;
end process;
tx <= tx_reg;
end;
| gpl-3.0 |
makestuff/dvr-connectors | conv-24to8/vhdl/tb_unit/conv_24to8_tb.vhdl | 1 | 3246 | --
-- Copyright (C) 2012-2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity conv_24to8_tb is
end entity;
architecture behavioural of conv_24to8_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
-- 24-bit interface signals
signal data24 : std_logic_vector(23 downto 0);
signal valid24 : std_logic;
signal ready24 : std_logic;
-- 8-bit interface signals
signal data8 : std_logic_vector(7 downto 0);
signal valid8 : std_logic;
signal ready8 : std_logic;
begin
-- Instantiate the memory controller for testing
uut: entity work.conv_24to8
port map(
clk_in => sysClk,
reset_in => '0',
data24_in => data24,
valid24_in => valid24,
ready24_out => ready24,
data8_out => data8,
valid8_out => valid8,
ready8_in => ready8
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
begin
data24 <= (others => 'Z');
valid24 <= '0';
ready8 <= '0';
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
data24 <= to_4(inLine.all(1)) & to_4(inLine.all(2)) & to_4(inLine.all(3)) & to_4(inLine.all(4)) & to_4(inLine.all(5)) & to_4(inLine.all(6));
valid24 <= to_1(inLine.all(8));
ready8 <= to_1(inLine.all(10));
wait for 10 ns;
write(outLine, from_4(data8(7 downto 4)) & from_4(data8(3 downto 0)));
write(outLine, ' ');
write(outLine, valid8);
write(outLine, ' ');
write(outLine, ready24);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
data24 <= (others => 'Z');
valid24 <= '0';
ready8 <= '0';
wait;
end process;
end architecture;
| gpl-3.0 |
a3f/r3k.vhdl | vhdl/tb/cpu_no_bus_tb.vhdl | 1 | 8903 | -- SKIP because we need to buffer pipeline stages in registers first, I think
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
use work.memory_map.all;
entity cpu_no_bus_tb is
end;
architecture struct of cpu_no_bus_tb is
component regFile is
port (
readreg1, readreg2 : in reg_t;
writereg: in reg_t;
writedata: in word_t;
readData1, readData2 : out word_t;
clk : in std_logic;
rst : in std_logic;
regWrite : in std_logic
);
end component;
signal readreg1, readreg2 : reg_t := R0;
signal writereg: reg_t := R0;
signal regReadData1, regReadData2, regWriteData : word_t := ZERO;
signal regWrite : ctrl_t := '0';
component mem is
port (
addr : in addr_t;
din : in word_t;
dout : out word_t;
size : in ctrl_memwidth_t;
wr : in std_logic;
clk : in std_logic
);
end component;
component InstructionFetch is
generic(PC_ADD, CPI : natural; SINGLE_ADDRESS_SPACE : boolean);
port (
clk : in std_logic;
rst : in std_logic;
new_pc : in addr_t;
pc_plus_4 : out addr_t;
instr : out instruction_t;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t
);
end component;
component InstructionDecode is
port(
instr : in instruction_t;
pc_plus_4 : in addr_t;
jump_addr : out addr_t;
regwrite, link, jumpreg, jumpdirect, branch : out ctrl_t;
memread, memwrite : out ctrl_memwidth_t;
memtoreg, memsex : out ctrl_t;
shift, alusrc : out ctrl_t;
aluop : out alu_op_t;
readreg1, readreg2, writereg : out reg_t;
zeroxed, sexed : out word_t;
clk : in std_logic;
rst : in std_logic);
end component;
component Execute is
port (
pc_plus_4 : in addr_t;
regReadData1, regReadData2 : in word_t;
branch_addr : out addr_t;
branch_in : in ctrl_t;
shift_in, alusrc_in : in ctrl_t;
aluop_in : in alu_op_t;
zeroxed, sexed : in word_t;
takeBranch : out ctrl_t;
AluResult : out word_t;
clk : in std_logic;
rst : in std_logic
);
end component;
component MemoryAccess is
port(
-- inbound
Address_in : in addr_t;
WriteData_in : in word_t;
ReadData_in : out word_t;
MemRead_in, MemWrite_in : in ctrl_memwidth_t;
MemSex_in : in std_logic;
clk : in std_logic;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t);
end component;
component WriteBack is
port(
Link, JumpReg, JumpDir, MemToReg, TakeBranch : in ctrl_t;
pc_plus_4, branch_addr, jump_addr: in addr_t;
aluResult, memReadData, regReadData1 : in word_t;
regWriteData : out word_t;
new_pc : out addr_t);
end component;
-- control signals
signal Link, Branch, JumpReg, JumpDir, memToreg, TakeBranch, Shift, ALUSrc, MemSex : ctrl_t;
signal MemRead, MemWrite : ctrl_memwidth_t;
signal memReadData : word_t;
signal new_pc : addr_t;
signal pc_plus_4, jump_addr, branch_addr : addr_t;
signal instr : instruction_t;
signal zeroxed, sexed, aluResult: word_t;
signal aluop : alu_op_t;
signal cpuclk : std_logic := '0';
signal regclk : std_logic := '0';
signal halt_cpu : boolean := false;
signal cpurst : std_logic := '0';
signal regrst : std_logic := '0';
signal done : boolean := false;
constant ESC : Character := Character'val(27);
signal addr : addr_t;
signal din : word_t;
signal dout : word_t;
signal size : ctrl_memwidth_t;
signal wr : std_logic;
begin
regFile1: regFile
port map(
readreg1 => readreg1, readreg2 => readreg2,
writereg => writereg, writedata => regWriteData,
readData1 => regReadData1, readData2 => regReadData2,
clk => regclk, rst => regrst,
regWrite => regWrite
);
if1: InstructionFetch
generic map (PC_ADD => 4, CPI => 7, SINGLE_ADDRESS_SPACE => false)
port map(
clk => cpuclk,
rst => cpurst,
new_pc => new_pc,
pc_plus_4 => pc_plus_4,
instr => instr,
top_addr => addr,
top_dout => dout,
top_din => din,
top_size => size,
top_wr => wr
);
mem_bus: mem port map (
addr => addr,
din => din,
dout => dout,
size => size,
wr => wr,
clk => cpuclk
);
id1: InstructionDecode
port map(instr => instr,
pc_plus_4 => pc_plus_4,
jump_addr => jump_addr,
regwrite => regwrite, link => link, jumpreg => jumpreg, jumpdirect => jumpdir, branch => Branch,
memread => memread, memwrite => memwrite,
memtoreg => memtoreg, memsex => memsex,
shift => shift, alusrc => aluSrc,
aluop => aluOp,
readreg1 => readReg1, readreg2 => readReg2, writeReg => writeReg,
zeroxed => zeroxed, sexed => sexed,
clk => cpuclk,
rst => cpurst
);
ex1: Execute
port map(
pc_plus_4 => pc_plus_4,
regReadData1 => regReadData1, regReadData2 => regReadData2,
branch_addr => branch_addr,
branch_in => Branch,
shift_in => shift, alusrc_in => ALUSrc,
aluop_in => ALUOp,
zeroxed => zeroxed, sexed => sexed,
takeBranch => takeBranch,
ALUResult => ALUResult,
clk => cpuclk,
rst => cpurst
);
ma1: memoryAccess
port map(
-- inbound
Address_in => AluResult,
WriteData_in => regReadData2,
ReadData_in => memReadData,
MemRead_in => memRead, MemWrite_in => memWrite,
MemSex_in => memSex,
clk => cpuclk,
-- outbound to top level module
top_addr => addr,
top_dout => dout,
top_din => din,
top_size => size,
top_wr => wr);
wb1: WriteBack
port map(
Link => Link,
JumpReg => JumpReg,
JumpDir => JumpDir,
MemToReg => MemToReg,
TakeBranch => TakeBranch,
pc_plus_4 => pc_plus_4,
branch_addr => branch_addr,
jump_addr => jump_addr,
aluResult => aluResult,
memReadData => memReadData,
regReadData1 => regReadData1,
regWriteData => regWriteData,
new_pc => new_pc);
test : process
begin
-- This halt_cpu thing doesn't work yet
--halt_cpu <= true;
--regrst <= '0';
--wait for 2 ns;
--regrst <= '1';
--wait for 2 ns;
--regrst <= '0';
--wait for 20 ns;
--readreg1 <= R1;
--wait for 2 ns;
--assert regReadData1 = ZERO report
-- ANSI_RED "Failed to reset. 0 /= " & to_hstring(regReadData1) & ANSI_NONE
--severity error;
--halt_cpu <= false;
cpurst <= '0';
wait for 2 ns;
cpurst <= '1';
wait for 2 ns;
cpurst <= '0';
wait for 60 ns;
cpurst <= '0';
--halt_cpu <= true;
readreg1 <= R1;
wait for 8 ns;
assert regReadData1 = X"0000_F000" report
ANSI_RED & "Failed to ori. 0xF000 /= " & to_hstring(regReadData1) & ANSI_NONE
severity error;
readreg1 <= R1;
readreg2 <= R2;
wait for 8 ns;
assert regReadData2 = X"0000_FBAD" report
ANSI_RED & "Failed to ori. 0xFBAD /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
assert regReadData1 = X"0000_F000" report
ANSI_RED & "Failed to ori. 0xF000 /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
done <= true;
wait;
end process;
clkproc: process
begin
regclk <= not regclk;
if not halt_cpu then
cpuclk <= not cpuclk;
end if;
wait for 1 ns;
if done then wait; end if;
end process;
end struct;
| gpl-3.0 |
a3f/r3k.vhdl | vhdl/io/sysbus.vhdl | 1 | 529 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
entity sysbus is
port (
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE
);
end sysbus;
architecture behav of sysbus is
signal cs : std_logic_vector(1 downto 0);
begin
end behav;
| gpl-3.0 |
a3f/r3k.vhdl | vhdl/utils.vhdl | 1 | 2336 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package utils is
function vec_increment(vec: std_logic_vector) return std_logic_vector;
function high_if(cond : boolean) return std_logic;
function low_if(cond : boolean) return std_logic;
-- procedure signextend(signal data_out: out std_logic_vector; signal data_in : in std_logic_vector);
procedure zeroextend(signal data_out: out std_logic_vector; signal data_in : in std_logic_vector);
function isnonzero(vec: std_logic_vector) return boolean;
function vtoi(v : std_logic_vector) return integer;
function vtou(v : std_logic_vector) return natural;
function toreg(i : integer) return std_logic_vector;
function itow(i : integer) return std_logic_vector;
function utow(u : natural) return std_logic_vector;
end utils;
package body utils is
function vec_increment(vec: std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(unsigned(vec) + 1);
end vec_increment;
function high_if(cond : boolean) return std_logic is
begin
if cond then return '1'; else return '0'; end if;
end function;
function low_if(cond : boolean) return std_logic is
begin
if cond then return '0'; else return '1'; end if;
end function;
procedure zeroextend(signal data_out: out std_logic_vector; signal data_in : in std_logic_vector) is
begin
data_out <= std_logic_vector(resize(unsigned(data_in), data_out'length));
end zeroextend;
function isnonzero(vec: std_logic_vector) return boolean is
begin
return vec /= (vec'range => '0');
end isnonzero;
function vtoi(v : std_logic_vector) return integer is
begin
return to_integer(signed(v));
end;
function vtou(v : std_logic_vector) return natural is
begin
return to_integer(unsigned(v));
end;
function itow(i : integer) return std_logic_vector is
begin
return std_logic_vector(to_signed(i, 32));
end function;
function utow(u : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(u, 32));
end function;
function toreg(i : integer) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(i, 5));
end function;
end utils;
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/ray_tracer_v3/coproc_2.vhd | 1 | 3643 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.cam_pkg.all;
entity coproc_2 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_2 is
signal min_reg : unsigned(7 downto 0);
signal beta_reg : unsigned(15 downto 0);
signal beta_tmp : unsigned(15 downto 0);
signal min_tmp, max_tmp : unsigned(7 downto 0);
signal store_min_beta : std_logic;
signal a,b : unsigned(15 downto 0);
signal OUTPUT_1_tmp : std_logic_vector(31 downto 0);
begin
-------------------------------------------------------------------------
scaling_computation : process (INPUT_1, min_reg, beta_reg)
variable mini : UNSIGNED(7 downto 0);
variable data1, data2, data3, data4 : UNSIGNED(7 downto 0);
variable diff1, diff2, diff3, diff4 : UNSIGNED(7 downto 0);
variable mult1, mult2, mult3, mult4 : UNSIGNED(23 downto 0);
begin
-- data1 := UNSIGNED( INPUT_1(7 downto 0) );
-- data2 := UNSIGNED( INPUT_1(15 downto 8) );
-- data3 := UNSIGNED( INPUT_1(23 downto 16) );
-- data4 := UNSIGNED( INPUT_1(31 downto 24) );
-- diff1 := data1 - min_reg; -- 8
-- diff2 := data2 - min_reg; -- 8
-- diff3 := data3 - min_reg; -- 8
-- diff4 := data4 - min_reg; -- 8
-- mult1 := diff1 * beta_reg; -- 24
-- mult2 := diff2 * beta_reg; -- 24
-- mult3 := diff3 * beta_reg; -- 24
-- mult4 := diff4 * beta_reg; -- 24
-- OUTPUT_1_tmp(7 downto 0) <= std_logic_vector(mult1(15 downto 8));
-- OUTPUT_1_tmp(15 downto 8) <= std_logic_vector(mult2(15 downto 8));
-- OUTPUT_1_tmp(23 downto 16) <= std_logic_vector(mult3(15 downto 8));
-- OUTPUT_1_tmp(31 downto 24) <= std_logic_vector(mult4(15 downto 8));
end process;
-------------------------------------------------------------------------
max_tmp <= UNSIGNED(INPUT_1(7 downto 0));
min_tmp <= UNSIGNED(INPUT_1(15 downto 8));
b <= "00000000"&(max_tmp-min_tmp);
a <= TO_UNSIGNED( 255, 8)&"00000000";
--beta_tmp <= divide(TO_UNSIGNED( 255, 8), (max_tmp-min_tmp));
--beta_tmp <= divide(a,b); --(8,8)
--beta_tmp <= "00000000"&max_tmp-min_tmp;
beta_tmp <= (others => '0');
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
store_min_beta <= '1';
min_reg <= (others => '0');
beta_reg <= (others => '0');
OUTPUT_1 <= (others => '0');
ELSE
IF (INPUT_1_valid = '1' and store_min_beta ='1') THEN
store_min_beta <= '0';
min_reg <= UNSIGNED(INPUT_1(15 downto 8));
beta_reg <= beta_tmp;
OUTPUT_1 <= INPUT_1;
ELSIF (INPUT_1_valid = '1' and store_min_beta = '0') THEN
store_min_beta <= '0';
min_reg <= min_reg;
beta_reg <= beta_reg;
OUTPUT_1 <= OUTPUT_1_tmp;
--OUTPUT_1 <= "000000000000000000000000"&std_logic_vector(min_reg);
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/ray_tracer_v3/function_6.vhd | 5 | 1045 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_6 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_6 is
begin
-------------------------------------------------------------------------
OUTPUT_1 <= std_logic_vector(signed(INPUT_1)+signed(INPUT_2));
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/filtre/coproc_4.vhd | 2 | 1408 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_4 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_4 is
SIGNAL mem : UNSIGNED(31 downto 0);
begin
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
mem <= TO_UNSIGNED( 0, 32);
ELSE
IF INPUT_1_valid = '1' THEN
mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 4, 32);
ELSE
mem <= mem;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/simulation/pcie_out.vhd | 1 | 1010 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
library work;
use work.txt_util.all;
entity PCIE_OUT is
port(
clk : IN std_logic;
fifo_in_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_compteur : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_write_en : IN std_logic;
fifo_full : OUT std_logic;
fifo_valid : OUT std_logic
);
end;
architecture logic of PCIE_OUT is
begin
PROCESS
file ram_valid_file : TEXT open WRITE_MODE is "pcie_out.txt";
variable LineValid : string(1 to 32);
BEGIN
while( true ) LOOP
wait UNTIL rising_edge( clk );
if fifo_write_en = '1' then
LineValid := str( fifo_in_data );
print(ram_valid_file, LineValid);
end if;
end LOOP;
END PROCESS;
fifo_valid <= '0';
fifo_full <= '0';
fifo_compteur <= (OTHERS => '0');
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/GRAPHLAB/SEQ_SUM_8d_8b_6c.vhd | 1 | 24059 | -- This SEQ_SUM_8d_8b_6c file has been generated by the GraphLab tool
-- using the hls_GeneratedMooreArchitecture developped by Bertrand LE GAL
-- and Willy AUBRY for High-Level Synthesis design flow.
-- * Time and Date : 10:59 10/03/2011
-- * Module name :
-- * Module version : 0
-- * Module command :
-- * Author name :
-- * E-Mail :
-- * Company :
-- * Copyright :
-- * Design function :
--
--
-- Correspondence concerning GraphLab software and its modules
-- should be addressed as follows:
-- Bertrand LE GAL ([email protected])
-- Maitre de Conferences - ENSEIRB
-- Laboratoire IMS - ENSEIRB - UMR 5818
-- Universite de Bordeaux 1
-- 351, cours de la Liberation
-- F-33405 TALENCE Cedex
-- FRANCE
--
-- Or directly using its website :
-- http://uuu.enseirb.fr/~legal/wp_graphlab
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
library work;
use work.all;
ENTITY SEQ_SUM_8d_8b_6c IS
PORT (
rst : IN STD_LOGIC;
clock : IN STD_LOGIC;
start : IN STD_LOGIC;
flush : IN STD_LOGIC;
holdn : IN STD_LOGIC;
INPUT_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
INPUT_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ready : OUT STD_LOGIC;
nready : OUT STD_LOGIC;
icc : OUT STD_LOGIC_vector(3 downto 0);
OUTPUT_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END SEQ_SUM_8d_8b_6c;
ARCHITECTURE SEQ_SUM_8d_8b_6c_arch OF SEQ_SUM_8d_8b_6c IS
COMPONENT ADD_DYNAMIC
GENERIC(
C_SIGNED : NATURAL := 0;
INPUT_1_WIDTH : POSITIVE := 16;
INPUT_2_WIDTH : POSITIVE := 16;
OUTPUT_1_WIDTH : POSITIVE := 16
);
PORT(
INPUT_1 : IN STD_LOGIC_VECTOR(INPUT_1_WIDTH -1 DOWNTO 0);
INPUT_2 : IN STD_LOGIC_VECTOR(INPUT_2_WIDTH -1 DOWNTO 0);
OUTPUT_1 : OUT STD_LOGIC_VECTOR(OUTPUT_1_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
TYPE StateType IS (E0, E1, E2, E3, E4, E5, E6, E7, E8, E9);
SIGNAL CurrentState_GLOBAL : StateType;
--
-- DEFINITION DES REGISTRES
--
SIGNAL OPR_ADD_1_INPUT_1_REGISTER_0001 : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0002 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0003 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0004 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0005 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0006 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0007 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0008 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORT_9_REGISTER_0009 : STD_LOGIC_VECTOR(10 DOWNTO 0);
--
-- DEFINITION DES ENTREES DES REGISTRES (UTILISE POUR LES MULTIPLEXEURS)
--
SIGNAL OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORT_9_REGISTER_0009_INPUT : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_1 : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL OPR_ADD_1_INPUT_2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL OPR_ADD_1_OUTPUT_1 : STD_LOGIC_VECTOR(10 DOWNTO 0);
BEGIN
---------------------------------------------------------
-- Cluster name : OPR_ADD_1
-- * The cluster contains 1 possible execution paths
-- => The mode 1 required computation(s) : True (E1/E10=>10 states)
--
---------------------------------------------------------
PROC_ASYNC_OPR_ADD_1_INPUT_1 : PROCESS (CurrentState_GLOBAL, OPR_ADD_1_INPUT_1_REGISTER_0001)
BEGIN
CASE CurrentState_GLOBAL IS
-- MODE=1 CYCLE=2 OFFSET=0 => 2
WHEN E2 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 5 / mode = 1 / cycle = 2)
-- MODE=1 CYCLE=3 OFFSET=0 => 3
WHEN E3 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 8 / mode = 1 / cycle = 3)
-- MODE=1 CYCLE=4 OFFSET=0 => 4
WHEN E4 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 11 / mode = 1 / cycle = 4)
-- MODE=1 CYCLE=5 OFFSET=0 => 5
WHEN E5 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 14 / mode = 1 / cycle = 5)
-- MODE=1 CYCLE=6 OFFSET=0 => 6
WHEN E6 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 17 / mode = 1 / cycle = 6)
-- MODE=1 CYCLE=7 OFFSET=0 => 7
WHEN E7 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 20 / mode = 1 / cycle = 7)
-- MODE=1 CYCLE=8 OFFSET=0 => 8
WHEN E8 => OPR_ADD_1_INPUT_1 <= OPR_ADD_1_INPUT_1_REGISTER_0001; -- (+ / 23 / mode = 1 / cycle = 8)
WHEN OTHERS => OPR_ADD_1_INPUT_1 <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_ASYNC_OPR_ADD_1_INPUT_1;
---------------------------------------------------------
-- Cluster name : OPR_ADD_1
-- * The cluster contains 1 possible execution paths
-- => The mode 1 required computation(s) : True (E1/E10=>10 states)
--
---------------------------------------------------------
PROC_ASYNC_OPR_ADD_1_INPUT_2 : PROCESS (CurrentState_GLOBAL, OPR_ADD_1_INPUT_2_REGISTER_0002, OPR_ADD_1_INPUT_2_REGISTER_0003, OPR_ADD_1_INPUT_2_REGISTER_0004, OPR_ADD_1_INPUT_2_REGISTER_0005, OPR_ADD_1_INPUT_2_REGISTER_0006, OPR_ADD_1_INPUT_2_REGISTER_0007, OPR_ADD_1_INPUT_2_REGISTER_0008)
BEGIN
CASE CurrentState_GLOBAL IS
-- MODE=1 CYCLE=2 OFFSET=0 => 2
WHEN E2 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0002; -- (+ / 5 / mode = 1 / cycle = 2)
-- MODE=1 CYCLE=3 OFFSET=0 => 3
WHEN E3 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0003; -- (+ / 8 / mode = 1 / cycle = 3)
-- MODE=1 CYCLE=4 OFFSET=0 => 4
WHEN E4 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0004; -- (+ / 11 / mode = 1 / cycle = 4)
-- MODE=1 CYCLE=5 OFFSET=0 => 5
WHEN E5 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0005; -- (+ / 14 / mode = 1 / cycle = 5)
-- MODE=1 CYCLE=6 OFFSET=0 => 6
WHEN E6 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0006; -- (+ / 17 / mode = 1 / cycle = 6)
-- MODE=1 CYCLE=7 OFFSET=0 => 7
WHEN E7 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0007; -- (+ / 20 / mode = 1 / cycle = 7)
-- MODE=1 CYCLE=8 OFFSET=0 => 8
WHEN E8 => OPR_ADD_1_INPUT_2 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- (+ / 23 / mode = 1 / cycle = 8)
WHEN OTHERS => OPR_ADD_1_INPUT_2 <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_ASYNC_OPR_ADD_1_INPUT_2;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_1_REGISTER_0001
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_1_REGISTER_0001 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (a)
WHEN E2 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (temp0)
WHEN E3 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (temp1)
WHEN E4 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (temp2)
WHEN E5 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (temp3)
WHEN E6 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (temp4)
WHEN E7 => OPR_ADD_1_INPUT_1_REGISTER_0001 <= OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT; -- mode (1) :: Affectation d'une valeur (temp5)
WHEN OTHERS => OPR_ADD_1_INPUT_1_REGISTER_0001 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_1_REGISTER_0001;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0002
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0002 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0002 <= OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT; -- mode (1) :: Affectation d'une valeur (b)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0002 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0002;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0003
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0003 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0003 <= OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT; -- mode (1) :: Affectation d'une valeur (c)
WHEN E2 => OPR_ADD_1_INPUT_2_REGISTER_0003 <= OPR_ADD_1_INPUT_2_REGISTER_0003; -- mode (1) :: Maintient d'une valeur (c)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0003 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0003;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0004
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0004 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0004 <= OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT; -- mode (1) :: Affectation d'une valeur (d)
WHEN E2 => OPR_ADD_1_INPUT_2_REGISTER_0004 <= OPR_ADD_1_INPUT_2_REGISTER_0004; -- mode (1) :: Maintient d'une valeur (d)
WHEN E3 => OPR_ADD_1_INPUT_2_REGISTER_0004 <= OPR_ADD_1_INPUT_2_REGISTER_0004; -- mode (1) :: Maintient d'une valeur (d)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0004 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0004;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0005
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0005 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0005 <= OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT; -- mode (1) :: Affectation d'une valeur (e)
WHEN E2 => OPR_ADD_1_INPUT_2_REGISTER_0005 <= OPR_ADD_1_INPUT_2_REGISTER_0005; -- mode (1) :: Maintient d'une valeur (e)
WHEN E3 => OPR_ADD_1_INPUT_2_REGISTER_0005 <= OPR_ADD_1_INPUT_2_REGISTER_0005; -- mode (1) :: Maintient d'une valeur (e)
WHEN E4 => OPR_ADD_1_INPUT_2_REGISTER_0005 <= OPR_ADD_1_INPUT_2_REGISTER_0005; -- mode (1) :: Maintient d'une valeur (e)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0005 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0005;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0006
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0006 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0006 <= OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT; -- mode (1) :: Affectation d'une valeur (f)
WHEN E2 => OPR_ADD_1_INPUT_2_REGISTER_0006 <= OPR_ADD_1_INPUT_2_REGISTER_0006; -- mode (1) :: Maintient d'une valeur (f)
WHEN E3 => OPR_ADD_1_INPUT_2_REGISTER_0006 <= OPR_ADD_1_INPUT_2_REGISTER_0006; -- mode (1) :: Maintient d'une valeur (f)
WHEN E4 => OPR_ADD_1_INPUT_2_REGISTER_0006 <= OPR_ADD_1_INPUT_2_REGISTER_0006; -- mode (1) :: Maintient d'une valeur (f)
WHEN E5 => OPR_ADD_1_INPUT_2_REGISTER_0006 <= OPR_ADD_1_INPUT_2_REGISTER_0006; -- mode (1) :: Maintient d'une valeur (f)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0006 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0006;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0007
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0007 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0007 <= OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT; -- mode (1) :: Affectation d'une valeur (g)
WHEN E2 => OPR_ADD_1_INPUT_2_REGISTER_0007 <= OPR_ADD_1_INPUT_2_REGISTER_0007; -- mode (1) :: Maintient d'une valeur (g)
WHEN E3 => OPR_ADD_1_INPUT_2_REGISTER_0007 <= OPR_ADD_1_INPUT_2_REGISTER_0007; -- mode (1) :: Maintient d'une valeur (g)
WHEN E4 => OPR_ADD_1_INPUT_2_REGISTER_0007 <= OPR_ADD_1_INPUT_2_REGISTER_0007; -- mode (1) :: Maintient d'une valeur (g)
WHEN E5 => OPR_ADD_1_INPUT_2_REGISTER_0007 <= OPR_ADD_1_INPUT_2_REGISTER_0007; -- mode (1) :: Maintient d'une valeur (g)
WHEN E6 => OPR_ADD_1_INPUT_2_REGISTER_0007 <= OPR_ADD_1_INPUT_2_REGISTER_0007; -- mode (1) :: Maintient d'une valeur (g)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0007 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0007;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0008
--
PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0008 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT; -- mode (1) :: Affectation d'une valeur (h)
WHEN E2 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- mode (1) :: Maintient d'une valeur (h)
WHEN E3 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- mode (1) :: Maintient d'une valeur (h)
WHEN E4 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- mode (1) :: Maintient d'une valeur (h)
WHEN E5 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- mode (1) :: Maintient d'une valeur (h)
WHEN E6 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- mode (1) :: Maintient d'une valeur (h)
WHEN E7 => OPR_ADD_1_INPUT_2_REGISTER_0008 <= OPR_ADD_1_INPUT_2_REGISTER_0008; -- mode (1) :: Maintient d'une valeur (h)
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0008 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_OPR_ADD_1_INPUT_2_REGISTER_0008;
--
-- PROCESS DEFINED FOR DRIVING COMMAND SIGNALS TO PORT_9_REGISTER_0009
--
PROC_REGISTER_CONTROL_PORT_9_REGISTER_0009 : PROCESS (clock)
BEGIN
IF ( clock'event AND clock = '1' ) THEN
CASE CurrentState_GLOBAL IS
WHEN E8 => PORT_9_REGISTER_0009 <= PORT_9_REGISTER_0009_INPUT; -- mode (1) :: Affectation d'une valeur (z)
WHEN E9 => PORT_9_REGISTER_0009 <= PORT_9_REGISTER_0009; -- mode (1) :: Maintient d'une valeur (z)
WHEN OTHERS => PORT_9_REGISTER_0009 <= (OTHERS=>'X');
END CASE;
END IF; -- IF(clock...)
END PROCESS PROC_REGISTER_CONTROL_PORT_9_REGISTER_0009;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OUTPUT_1(31 downto 0)
--
PROCESS (PORT_9_REGISTER_0009)
BEGIN
OUTPUT_1(31 downto 0) <= STD_LOGIC_VECTOR( RESIZE( UNSIGNED(PORT_9_REGISTER_0009), 32) );
END PROCESS;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_1(7 downto 0), OPR_ADD_1_OUTPUT_1)
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= STD_LOGIC_VECTOR( RESIZE( UNSIGNED(INPUT_1(7 downto 0)), 11) );
WHEN E2 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN E3 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN E4 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN E5 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN E6 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN E7 => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN OTHERS => OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_1_REGISTER_0001_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_1(15 downto 8))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT <= INPUT_1(15 downto 8);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0002_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_1(23 downto 16))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT <= INPUT_1(23 downto 16);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0003_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_1(31 downto 24))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT <= INPUT_1(31 downto 24);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0004_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_2(7 downto 0))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT <= INPUT_2(7 downto 0);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0005_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_2(15 downto 8))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT <= INPUT_2(15 downto 8);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0006_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_2(23 downto 16))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT <= INPUT_2(23 downto 16);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0007_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT
--
PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT : PROCESS (CurrentState_GLOBAL, INPUT_2(31 downto 24))
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E1 => OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT <= INPUT_2(31 downto 24);
WHEN OTHERS => OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_OPR_ADD_1_INPUT_2_REGISTER_0008_INPUT;
--
-- PROCESS DEFINED FOR DRIVING SIGNALS TO PORT_9_REGISTER_0009_INPUT
--
PROC_MULTIPLEXER_PORT_9_REGISTER_0009_INPUT : PROCESS (CurrentState_GLOBAL, OPR_ADD_1_OUTPUT_1)
BEGIN
CASE CurrentState_GLOBAL IS
WHEN E8 => PORT_9_REGISTER_0009_INPUT <= OPR_ADD_1_OUTPUT_1;
WHEN OTHERS => PORT_9_REGISTER_0009_INPUT <= (OTHERS=>'X');
END CASE;
END PROCESS PROC_MULTIPLEXER_PORT_9_REGISTER_0009_INPUT;
--process(start)
--BEGIN
-- if (start = '1') then
-- REPORT "(GL) THE START SIGNAL IS UP !!!";
-- else
-- REPORT "(GL) THE START SIGNAL IS DOWN !!!";
-- end if;
--END PROCESS;
---------------------------------------------------------
PROC_CONTROLER_FSM : PROCESS (clock, rst)
variable sready : std_logic;
variable snready : std_logic;
BEGIN
sready := '0';
snready := '0';
IF rst = '0' THEN
CurrentState_GLOBAL <= E0;
ready <= sready;
nready <= snready;
--printmsg("(GL) THE DESIGN IS PROCESSING RESET !");
ELSIF clock'event and clock = '1' THEN
--if (start = '1') then
-- printmsg("(GL) THE START SIGNAL IS UP (3) !!!");
--end if;
IF( flush = '1' ) THEN
CurrentState_GLOBAL <= E0;
--printmsg("(GL) THE DESIGN IS PROCESSING FLUSH !");
ELSIF (holdn = '0') AND (CurrentState_GLOBAL /= E0) THEN
CurrentState_GLOBAL <= CurrentState_GLOBAL;
--printmsg("(GL) THE DESIGN IS PROCESSING HOLDN !");
ELSE
CASE CurrentState_GLOBAL IS
WHEN E0 =>
IF( start = '1' ) THEN
CurrentState_GLOBAL <= E1;
--REPORT "(GL) THE DESIGN IS STARTING !";
ELSE
CurrentState_GLOBAL <= E0;
--REPORT "(GL) THE DESIGN IS WAITING !";
END IF;
WHEN E1 => CurrentState_GLOBAL <= E2 ;
WHEN E2 => CurrentState_GLOBAL <= E3 ;
WHEN E3 => CurrentState_GLOBAL <= E4 ;
WHEN E4 => CurrentState_GLOBAL <= E5 ;
WHEN E5 => CurrentState_GLOBAL <= E6 ;
WHEN E6 => CurrentState_GLOBAL <= E7 ;
WHEN E7 => CurrentState_GLOBAL <= E8 ;
WHEN E8 => CurrentState_GLOBAL <= E9 ;
snready := '1'; -- LE CALCUL PRESQUE FINI...
--printmsg("(GL) SENDING THE READY SIGNAL !");
WHEN E9 =>
--printmsg("(GL) THE COMPUTATION IS FINISHED !");
CurrentState_GLOBAL <= E0 ;
WHEN OTHERS =>
CurrentState_GLOBAL <= E0;
END CASE;
END IF;
ready <= sready;
nready <= snready;
END IF;
END PROCESS PROC_CONTROLER_FSM;
---------------------------------------------------------
icc <= "0000";
OPR_ADD_1 : ADD_DYNAMIC
GENERIC MAP(
C_SIGNED => 0,
INPUT_1_WIDTH => 11,
INPUT_2_WIDTH => 8,
OUTPUT_1_WIDTH => 11
)
PORT MAP(
STD_LOGIC_VECTOR(OPR_ADD_1_INPUT_1),
STD_LOGIC_VECTOR(OPR_ADD_1_INPUT_2),
OPR_ADD_1_OUTPUT_1
);
END SEQ_SUM_8d_8b_6c_arch;
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/RESOURCE_CUSTOM_5.vhd | 1 | 653 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ims;
use ims.coprocessor.all;
entity RESOURCE_CUSTOM_5 is
port (
inp : in custom32_in_type;
outp : out custom32_out_type
);
end;
architecture rtl of RESOURCE_CUSTOM_5 is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
printmsg("(IMS) RESOURCE_CUSTOM_5 : ALLOCATION OK !");
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
computation : process (inp)
begin
end process;
end;
| gpl-3.0 |
makestuff/swled | fifo/vhdl/fifo_rtl.vhdl | 1 | 5834 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of swled is
-- Flags for display on the 7-seg decimal points
signal flags : std_logic_vector(3 downto 0);
-- FIFOs implementing the channels
signal fifoCount : std_logic_vector(15 downto 0); -- MSB=writeFifo, LSB=readFifo
-- Write FIFO:
signal writeFifoInputData : std_logic_vector(7 downto 0); -- producer: data
signal writeFifoInputValid : std_logic; -- valid flag
signal writeFifoInputReady : std_logic; -- ready flag
signal writeFifoOutputData : std_logic_vector(7 downto 0); -- consumer: data
signal writeFifoOutputValid : std_logic; -- valid flag
signal writeFifoOutputReady : std_logic; -- ready flag
-- Read FIFO:
signal readFifoInputData : std_logic_vector(7 downto 0); -- producer: data
signal readFifoInputValid : std_logic; -- valid flag
signal readFifoInputReady : std_logic; -- ready flag
signal readFifoOutputData : std_logic_vector(7 downto 0); -- consumer: data
signal readFifoOutputValid : std_logic; -- valid flag
signal readFifoOutputReady : std_logic; -- ready flag
-- Counter which endlessly puts items into the read FIFO for the host to read
signal count, count_next : std_logic_vector(7 downto 0) := (others => '0');
-- Producer and consumer timers
signal producerSpeed : std_logic_vector(3 downto 0);
signal consumerSpeed : std_logic_vector(3 downto 0);
begin --BEGIN_SNIPPET(fifos)
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
count <= (others => '0');
else
count <= count_next;
end if;
end if;
end process;
-- Wire up write FIFO to channel 0 writes:
-- flags(2) driven by writeFifoOutputValid
-- writeFifoOutputReady driven by consumer_timer
-- LEDs driven by writeFifoOutputData
writeFifoInputData <=
h2fData_in;
writeFifoInputValid <=
'1' when h2fValid_in = '1' and chanAddr_in = "0000000"
else '0';
h2fReady_out <=
'0' when writeFifoInputReady = '0' and chanAddr_in = "0000000"
else '1';
-- Wire up read FIFO to channel 0 reads:
-- readFifoInputValid driven by producer_timer
-- flags(0) driven by readFifoInputReady
count_next <=
std_logic_vector(unsigned(count) + 1) when readFifoInputValid = '1'
else count;
readFifoInputData <=
count;
f2hValid_out <=
'0' when readFifoOutputValid = '0' and chanAddr_in = "0000000"
else '1';
readFifoOutputReady <=
'1' when f2hReady_in = '1' and chanAddr_in = "0000000"
else '0';
-- Select values to return for each channel when the host is reading
with chanAddr_in select f2hData_out <=
readFifoOutputData when "0000000", -- get from read FIFO
fifoCount(15 downto 8) when "0000001", -- get depth of write FIFO
fifoCount(7 downto 0) when "0000010", -- get depth of read FIFO
x"00" when others; --END_SNIPPET(fifos)
-- Write FIFO: written by host, read by LEDs
write_fifo : entity work.fifo_wrapper
port map(
clk_in => clk_in,
depth_out => fifoCount(15 downto 8),
-- Production end
inputData_in => writeFifoInputData,
inputValid_in => writeFifoInputValid,
inputReady_out => writeFifoInputReady,
-- Consumption end
outputData_out => writeFifoOutputData,
outputValid_out => writeFifoOutputValid,
outputReady_in => writeFifoOutputReady
);
-- Read FIFO: written by counter, read by host
read_fifo : entity work.fifo_wrapper
port map(
clk_in => clk_in,
depth_out => fifoCount(7 downto 0),
-- Production end
inputData_in => readFifoInputData,
inputValid_in => readFifoInputValid,
inputReady_out => readFifoInputReady,
-- Consumption end
outputData_out => readFifoOutputData,
outputValid_out => readFifoOutputValid,
outputReady_in => readFifoOutputReady
);
-- Producer timer: how fast stuff is put into the read FIFO
producerSpeed <= not(sw_in(3 downto 0));
producer_timer : entity work.timer
port map(
clk_in => clk_in,
ceiling_in => producerSpeed,
tick_out => readFifoInputValid
);
-- Consumer timer: how fast stuff is drained from the write FIFO
consumerSpeed <= not(sw_in(7 downto 4));
consumer_timer : entity work.timer
port map(
clk_in => clk_in,
ceiling_in => consumerSpeed,
tick_out => writeFifoOutputReady
);
-- LEDs and 7-seg display
led_out <= writeFifoOutputData;
flags <= '0' & writeFifoOutputValid & '0' & readFifoInputReady;
seven_seg : entity work.seven_seg
port map(
clk_in => clk_in,
data_in => fifoCount,
dots_in => flags,
segs_out => sseg_out,
anodes_out => anode_out
);
end architecture;
| gpl-3.0 |
chibby0ne/vhdl-book | Chapter3/exercise3-12_dir/exercise3-12/bit_vector.vhd | 1 | 425 | library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity and_gate is
--generic declarations
port (
a: in bit_vector(3 downto 0) ;
b: in bit_vector(3 downto 0) ;
x: out bit_vector(3 downto 0));
end entity;
------------------------------
architecture circuit of and_gate is
--signals and declarations
begin
x <= a and b;
end architecture;
------------------------------
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/mandelbrot/function_7.vhd | 5 | 1334 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_7 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_7 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 7, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/ray_tracer_v3/function_7.vhd | 5 | 1334 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_7 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_7 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 7, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/pc_next.vhd | 1 | 2383 | ---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in, opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); -- pc_reg + 1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
-- BEGIN ENABLE_(J,JAL)
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
-- END ENABLE_(J,JAL)
-- BEGIN ENABLE_(BEQ,BNE,BLEZ,BGTZ,COP0,JR,JALR,REGIMM)
when FROM_BRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
-- END ENABLE_(BEQ,BNE,BLEZ,BGTZ,COP0)
when FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
| gpl-3.0 |
chibby0ne/vhdl-book | Chapter8/pkg_sync_counter_dir/pkg_sync_counter.vhd | 1 | 700 | --!
--! @file: pkg_sync_counter.vhd
--! @brief: synchronous component
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
package pkg_sync_counter is
component sync_counter is
port (
a, b, clk: in std_logic;
andq, q: out std_logic);
end component sync_counter;
end package pkg_sync_counter;
------------------------------
package body pkg_sync_counter is
--functionsdefinitions, deferredconstants. they need to have the full subprogram header exactly as it appears in package
end package body pkg_sync_counter;
| gpl-3.0 |
chibby0ne/vhdl-book | Chapter9/my_and_dir/my_and.vhd | 1 | 627 | --!
--! @file: exercise9_5.vhd
--! @brief: function my_not
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
library work;
use work.my_comps.all;
--------------------------------------
entity app_and is
--generic declarations
port (
a, b: in std_logic;
q: out std_logic);
end entity app_notand;
--------------------------------------
architecture circuit of app_notand is
--signals and declarations
begin
q <= my_and a;
end architecture circuit;
--------------------------------------
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/simulation/pcie_in.vhd | 1 | 3236 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.ALL;
--use work.mlite_pack.all;
-- The libraries ieee.std_logic_unsigned and std.textio will need to be included
LIBRARY work;
USE work.txt_util.ALL;
ENTITY PCIE_IN IS
PORT(
clk : IN STD_LOGIC;
fifo_out_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_compteur : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_read_en : IN STD_LOGIC;
fifo_full : OUT STD_LOGIC;
fifo_empty : OUT STD_LOGIC;
fifo_valid : OUT STD_LOGIC
);
END;
ARCHITECTURE logic OF PCIE_IN IS
BEGIN
PROCESS
FILE data_file : TEXT OPEN read_mode IS "pcie_in.txt";
VARIABLE data_line : STRING(1 TO 32);
BEGIN
REPORT "COUCOU" SEVERITY note;
--
-- ON REGARDE SI LE FICHIER EST FOURNI ...
--
IF NOT endfile(data_file) THEN
str_read(data_file, data_line);
fifo_out_data <= TO_STD_LOGIC_VECTOR(data_line(1 TO 32));
fifo_compteur <= STD_LOGIC_VECTOR(TO_UNSIGNED(1, 32));
fifo_full <= '0';
fifo_valid <= '1';
IF NOT endfile(data_file) THEN
fifo_empty <= '0';
ELSE
fifo_empty <= '1';
END IF;
ELSE
fifo_out_data <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
fifo_compteur <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32));
fifo_full <= '0';
fifo_valid <= '0';
fifo_empty <= '1';
END IF;
--
-- TANT QU'IL RESTE DES DONNEES DANS LE FICHIER, ON ATTEND QUE LE PROCESSEUR
-- VIENNE LES LIRE ...
--
WAIT UNTIL RISING_EDGE(CLK);
WHILE NOT endfile(data_file) LOOP
WAIT UNTIL RISING_EDGE(CLK);
IF fifo_read_en = '1' THEN
--
-- ON SOUHAITE LE PASSAGE A LA DONNEE SUIVANTE.
--
fifo_out_data <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
fifo_compteur <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32));
fifo_valid <= '0';
fifo_empty <= '1';
-- REPORT "Waiting N clock cycles" SEVERITY note;
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
-- WAIT UNTIL RISING_EDGE(CLK);
WAIT UNTIL RISING_EDGE(CLK);
IF NOT endfile(data_file) THEN
str_read(data_file, data_line);
fifo_out_data <= TO_STD_LOGIC_VECTOR(data_line(1 TO 32));
fifo_compteur <= STD_LOGIC_VECTOR(TO_UNSIGNED(1, 32));
fifo_valid <= '1';
fifo_empty <= '0';
ELSE
fifo_out_data <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
fifo_compteur <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32));
fifo_valid <= '0';
fifo_empty <= '1';
END IF;
END IF;
END LOOP;
WHILE endfile(data_file) LOOP
WAIT UNTIL RISING_EDGE(CLK);
IF fifo_read_en = '1' THEN
fifo_valid <= '0';
fifo_empty <= '1';
END IF;
END LOOP;
--
-- UNE FOIS QUE TOUTES LES DONNEES ONT ETE TRAITEES, ON SE "BLOQUE"
--
-- REPORT "## ON N'A PLUS DE DONNEES ##";
WHILE endfile(data_file) LOOP
WAIT UNTIL rising_edge(clk);
fifo_valid <= '0';
fifo_empty <= '1';
-- if fifo_write_en = '1' then
-- end if;
END LOOP;
END PROCESS;
--fifo_valid <= '0';
fifo_full <= '0';
--fifo_compteur <= (OTHERS => '0');
END; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/mandelbrot/function_17.vhd | 5 | 1887 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_17 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_17 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable vTemp1 : std_logic_vector(7 downto 0);
variable vTemp2 : std_logic_vector(7 downto 0);
variable vTemp3 : std_logic_vector(7 downto 0);
variable vTemp4 : std_logic_vector(7 downto 0);
begin
IF INPUT_2( 0 ) = '0' THEN
vTemp1 := INPUT_1( 7 downto 0);
ELSE
vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2( 7 downto 0)) );
END IF;
IF INPUT_2( 8 ) = '0' THEN
vTemp1 := INPUT_1(15 downto 8);
ELSE
vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(15 downto 8)) );
END IF;
IF INPUT_2( 16 ) = '0' THEN
vTemp1 := INPUT_1(23 downto 16);
ELSE
vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(23 downto 16)) );
END IF;
IF INPUT_2( 24 ) = '0' THEN
vTemp1 := INPUT_1(31 downto 24);
ELSE
vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(31 downto 24)) );
END IF;
OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1);
end process;
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/dma_engine - Copie.vhd | 2 | 11630 | ---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.conversion.all;
entity dma_engine is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
start_dma : in std_logic; --enable receive DMA
--
--
--
address : out std_logic_vector(31 downto 0); --to DDR
byte_we : out std_logic_vector( 3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
--
--
--
mem_address : in std_logic_vector(31 downto 0); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic
);
end; --entity eth_dma
architecture logic of dma_engine is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal struc_ptr : std_logic_vector(31 downto 0);
SIGNAL dma_type : std_logic_vector( 7 DOWNTO 0);
SIGNAL ptr_src : std_logic_vector(31 downto 0);
SIGNAL ptr_src_2 : std_logic_vector(31 downto 0);
SIGNAL ptr_src_3 : std_logic_vector(31 downto 0);
SIGNAL ptr_dst : std_logic_vector(31 downto 0);
SIGNAL nWords : std_logic_vector(15 downto 0);
TYPE STATE_TYPE IS (waiting, nextS, addr_dma_type, read_dma_type, read_ptr_src, read_ptr_src_2, read_ptr_src_3, read_ptr_dst, read_nb_words, select_type, cpy_init_data, cpy_read_data, cpy_write_data, init_write_data, wait_one_cycle);
SIGNAL dma_state : STATE_TYPE;
CONSTANT INC_1_WORD : UNSIGNED(31 downto 0) := TO_UNSIGNED(4, 32);
begin --architecture
-- mem_address : in std_logic_vector(31 downto 2); --from CPU
-- mem_byte_we : in std_logic_vector(3 downto 0);
-- data_w : in std_logic_vector(31 downto 0);
-- pause_out : out std_logic
-- DMA CLEAR (0x00)
-- DMA COPY (0x01)
-- DMA XOR (0x02)
-- DMA F (0x03)
-- DMA G (0x04)
dma : process(reset, clk)
BEGIN
IF reset = '1' THEN
dma_state <= waiting;
dma_type <= ZERO( 7 downto 0);
ptr_src <= ZERO;
ptr_dst <= ZERO;
nWords <= ZERO(15 downto 0);
pause_out <= '0';
address <= ZERO;
byte_we <= "0000";
data_write <= ZERO;
ELSE
if CLK'event and CLK = '1' then
CASE dma_state IS
WHEN waiting =>
struc_ptr <= data_w(31 DOWNTO 0);
IF start_dma = '1' THEN
-- REPORT "STARTING DMA = " & to_hex_str( data_w );
dma_state <= nextS;
pause_out <= '1';
ELSE
dma_state <= waiting;
pause_out <= '0';
END IF;
address <= data_w(31 DOWNTO 0); -- ON POSITIONNE L'ADRESSE MEMOIRE
WHEN nextS =>
dma_state <= addr_dma_type;
pause_out <= '1';
WHEN addr_dma_type =>
-- REPORT "WRITING STRUCTURE ADDRESS";
pause_out <= '1';
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
byte_we <= "0000"; -- DE LA STRUCTURE CONTENANT LA
dma_state <= read_dma_type; -- REQUETE DMA
WHEN read_dma_type =>
-- REPORT "READING DMA TYPE = " & to_hex_str( data_read );
pause_out <= '1';
dma_type <= data_read( 7 DOWNTO 0); -- ON MEMORISE LE
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
IF data_read(7 DOWNTO 0) = "00000000" THEN
dma_state <= read_ptr_dst; -- NEXT STATE
ELSE
dma_state <= read_ptr_src; -- NEXT STATE
END IF;
WHEN read_ptr_src =>
-- REPORT "READING SRC POINTER = " & to_hex_str( data_read );
ptr_src <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
IF data_read(7 DOWNTO 0) = "00000001" THEN
dma_state <= read_ptr_dst; -- NEXT STATE
ELSE
dma_state <= read_ptr_src_3; -- NEXT STATE
END IF;
WHEN read_ptr_src_2 =>
-- REPORT "READING SRC POINTER = " & to_hex_str( data_read );
ptr_src_2 <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
IF data_read(7 DOWNTO 0) = "00000010" THEN
dma_state <= read_ptr_dst; -- NEXT STATE
ELSE
dma_state <= read_ptr_src_3; -- NEXT STATE
END IF;
WHEN read_ptr_src_3 =>
-- REPORT "READING SRC POINTER = " & to_hex_str( data_read );
ptr_src_3 <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
dma_state <= read_ptr_dst; -- NEXT STATE
WHEN read_ptr_dst =>
-- REPORT "READING DST POINTER = " & to_hex_str( data_read );
ptr_dst <= data_read(31 DOWNTO 0); --
byte_we <= "0000"; -- TYPE DE LA REQUETE +
struc_ptr <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(struc_ptr) + INC_1_WORD); -- ON POSITIONNE L'ADRESSE MEMOIRE
dma_state <= read_nb_words; -- NEXT STATE
WHEN read_nb_words =>
-- REPORT "READING NB WORDS = " & to_hex_str( data_read );
nWords <= data_read(15 DOWNTO 0); --
byte_we <= "0000"; --
dma_state <= select_type; -- NEXT STATE
WHEN select_type =>
-- REPORT "SELECTING DMA OPERATION";
IF dma_type = "00000000" THEN
dma_state <= init_write_data;
ELSE
dma_state <= cpy_init_data;
END IF;
-----------------------------------------------------------
-- on demande la donnee 0
WHEN cpy_init_data =>
REPORT "PROCESSING cpy_init_data from " & to_hex_str( ptr_src ) & " data_read = " & to_hex_str( data_read );
ptr_src <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) ); -- ON POSITIONNE L'ADRESSE MEMOIRE
data_write <= ZERO;
byte_we <= "0000"; -- TYPE DE LA REQUETE +
dma_state <= cpy_read_data;
-- on demande la donnee 1
WHEN cpy_read_data =>
REPORT "PROCESSING cpy_read_data from " & to_hex_str( ptr_src ) & " data_read = " & to_hex_str( data_read );
ptr_src <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_src) );
data_write <= data_read;
byte_we <= "0000";
dma_state <= cpy_write_data;
-- on ecrit la donnee 0
WHEN cpy_write_data =>
REPORT "PROCESSING cpy_write_data to " & to_hex_str( ptr_dst ) & " data_read = " & to_hex_str( data_read );
ptr_dst <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) ); -- ON POSITIONNE L'ADRESSE MEMOIRE
-- data_write <= ZERO;
byte_we <= "1111"; -- TYPE DE LA REQUETE +
-- On decompte ...
nWords <= STD_LOGIC_VECTOR( UNSIGNED(nWords) - TO_UNSIGNED(1, 16));
if( UNSIGNED(nWords) = TO_UNSIGNED(1, 16) ) THEN
dma_state <= wait_one_cycle; -- NEXT STATE
ELSE
dma_state <= cpy_read_data; -- NEXT STATE
END IF;
-----------------------------------------------------------
WHEN init_write_data =>
-- REPORT "PROCESSING init_write_data " & to_hex_str( ptr_dst ) & " - " & to_hex_str( nWords );
ptr_dst <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) + INC_1_WORD); --
address <= STD_LOGIC_VECTOR( UNSIGNED(ptr_dst) ); -- ON POSITIONNE L'ADRESSE MEMOIRE
data_write <= ZERO;
nWords <= STD_LOGIC_VECTOR( UNSIGNED(nWords) - TO_UNSIGNED(1, 16));
byte_we <= "1111"; -- TYPE DE LA REQUETE +
pause_out <= '1';
if( UNSIGNED(nWords) = TO_UNSIGNED(1, 16) ) THEN
dma_state <= wait_one_cycle; -- NEXT STATE
ELSE
dma_state <= init_write_data; -- NEXT STATE
END IF;
WHEN wait_one_cycle =>
-- REPORT "PROCESSING wait_one_cycle";
byte_we <= "0000"; -- TYPE DE LA REQUETE +
pause_out <= '0';
dma_state <= waiting; -- NEXT STATE
END CASE;
END IF;
END IF;
END process;
end; --architecture logic
| gpl-3.0 |
chibby0ne/vhdl-book | Chapter11/example1_dir/vending_machine.vhd | 1 | 4382 | --
-- vending machine FSM
--
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity vending_machine is
--generic declarations
port (
clk, rst: in std_logic;
nickel_in, dime_in, quarter_in: in boolean;
candy_out, nickel_out, dime_out: out std_logic);
end entity vending_machine;
--------------------------------------
architecture circuit of vending_machine is
type state is (st0, st5, st10, st15, st20, st25, st30, st35, st40, st45);
signal pr_state, nx_state: state;
attribute enum_encoding: string;
attribute enum_encoding of state: type is "sequential";
begin
--------------------------------------
-- lower section of FSM (sequential part)
--------------------------------------
process (rst, clk)
--declarativepart
begin
if (rst = '1') then
pr_state <= st0;
elsif (clk'event and clk = '1') then
pr_state <= nx_state;
end if;
end process;
--------------------------------------
-- upper section of FSM (combinational part)
--------------------------------------
process (pr_state, nickel_in, dime_in, quarter_in)
--declarativepart
begin
case pr_state is
when st0 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st5;
elsif (dime_in) then
nx_state <= st10;
elsif (quarter_in) then
nx_state <= st25;
else
nx_state <= st0;
end if;
when st5 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st10;
elsif (dime_in) then
nx_state <= st15;
elsif (quarter_in) then
nx_state <= st30;
else
nx_state <= st5;
end if;
when st10 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st15;
elsif (dime_in) then
nx_state <= st20;
elsif (quarter_in) then
nx_state <= st35;
else
nx_state <= st10;
end if;
when st15 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st20;
elsif (dime_in) then
nx_state <= st25;
elsif (quarter_in) then
nx_state <= st40;
else
nx_state <= st15;
end if;
when st20 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st25;
elsif (dime_in) then
nx_state <= st30;
elsif (quarter_in) then
nx_state <= st45;
else
nx_state <= st20;
end if;
when st25 =>
candy_out <= '1';
nickel_out <= '0';
dime_out <= '0';
nx_state <= st0;
when st30 =>
candy_out <= '1';
nickel_out <= '1';
dime_out <= '0';
nx_state <= st0;
when st35 =>
candy_out <= '1';
nickel_out <= '0';
dime_out <= '0';
nx_state <= st0;
when st40 =>
candy_out <= '0';
nickel_out <= '1';
dime_out <= '0';
nx_state <= st35;
when st45 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '1';
nx_state <= st35;
end case;
end process;
end architecture circuit;
| gpl-3.0 |
chibby0ne/vhdl-book | Chapter8/exercise8_5b_dir/exercise8_5b.vhd | 1 | 1113 | --!
--! @file: exercise8_5b.vhd
--! @brief: synchronous counter using component
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
library work;
use work.pkg_sync_counter.all;
--------------------------------------
entity synchronous_counter is
port (
a, b, clk: in std_logic;
q: out std_logic_vector(2 downto 0));
end entity synchronous_counter;
--------------------------------------
architecture circuit of synchronous_counter is
signal andq: std_logic_vector(1 to 0);
begin
sync_cell0: sync_counter port map (
a => a
b => b,
clk => clk,
q => q(0),
andq => andq(0),
);
sync_cell1: sync_counter port map (
a => andq(0),
b => q(0),
clk => clk,
q => q(1)
);
sync_cell2: sync_counter port map (
a => andq(1)
b => q(1),
clk => clk,
q => q(2)
);
end architecture circuit;
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/RESOURCE_CUSTOM_4.vhd | 1 | 1198 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.stdlib.all;
--library gaisler;
--use gaisler.arith.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
entity RESOURCE_CUSTOM_4 is
port (
inp : in custom32_in_type;
outp : out custom32_out_type
);
end;
architecture rtl of RESOURCE_CUSTOM_4 is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
printmsg("(IMS) RESOURCE_CUSTOM_4 : ALLOCATION OK !");
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (inp.op1, inp.op2)
Variable A : SIGNED(31 downto 0);
Variable B : SIGNED(31 downto 0);
Variable C : SIGNED(31 downto 0);
begin
A := SIGNED( inp.op1(31 downto 0) );
B := SIGNED( inp.op2(31 downto 0) );
C := A + B + 1;
outp.result <= STD_LOGIC_VECTOR( C(31) & C(31 downto 1) );
end process;
-------------------------------------------------------------------------
end;
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/video/ASYNC_RGB_2_YUV.vhd | 1 | 7731 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
--use ims.conversion.all;
--
-- LES DONNEES ARRIVENT SOUS LA FORME (0x00 & B & G & R)
-- ET ELLES RESSORTENT SOUS LA FORME (0x00 & V & U & Y)
--
entity ASYNC_RGB_2_YUV is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
write_en : in std_logic;
in_full : out std_logic;
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0);
read_en : in std_logic;
out_empty : out std_logic;
Next_Empty : out std_logic
);
end ASYNC_RGB_2_YUV;
architecture rtl of ASYNC_RGB_2_YUV is
COMPONENT CUSTOM_FIFO
PORT(
rst : IN std_logic;
clk : IN std_logic;
flush : IN std_logic;
holdn : IN std_logic;
INPUT_1 : IN std_logic_vector(31 downto 0);
write_en : IN std_logic;
in_full : OUT std_logic;
OUTPUT_1 : OUT std_logic_vector(31 downto 0);
read_en : IN std_logic;
out_empty : OUT std_logic;
Next_Empty : OUT std_logic
);
END COMPONENT;
constant s_rgb_30 : UNSIGNED(24 downto 0) := "0010011001000101101000011";
constant s_rgb_59 : UNSIGNED(24 downto 0) := "0100101100100010110100001";
constant s_rgb_11 : UNSIGNED(24 downto 0) := "0000111010010111100011010";
constant s_rgb_17 : UNSIGNED(24 downto 0) := "0001010110011001010001011";
constant s_rgb_33 : UNSIGNED(24 downto 0) := "0010101001100110101110100";
constant s_rgb_50 : UNSIGNED(24 downto 0) := "0100000000000000000000000";
constant s_rgb_42 : UNSIGNED(24 downto 0) := "0011010110010111101000100";
constant s_rgb_08 : UNSIGNED(24 downto 0) := "0000101001101000010111011";
constant s_rgb_128 : UNSIGNED(31 downto 0) := "10000000000000000000000000000000"; -- TO_UNSIGNED(128, 32); --"10000000000000000000000000000000";
signal PIPE_START : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL INPUT_R : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_G : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_B : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_Y : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_U : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_V : STD_LOGIC_VECTOR(7 downto 0);
signal AFTER_FIFO : STD_LOGIC_VECTOR(31 downto 0);
signal READ_INP : STD_LOGIC;
signal INPUT_EMPTY : STD_LOGIC;
signal INPUT_nEMPTY : STD_LOGIC;
signal BEFORE_FIFO : STD_LOGIC_VECTOR(31 downto 0);
signal WRITE_OUTP : STD_LOGIC;
signal OUTPUT_FULL : STD_LOGIC;
signal START_COMPUTE : STD_LOGIC;
SIGNAL s_rgb_out_y : UNSIGNED(32 downto 0) := (others => '0');
SIGNAL s_rgb_out_cb : UNSIGNED(32 downto 0) := (others => '0');
SIGNAL s_rgb_out_cr : UNSIGNED(32 downto 0) := (others => '0');
SIGNAL rgb_in_r_reg_Y : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_g_reg_Y : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_b_reg_Y : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_r_reg_Cb : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_g_reg_Cb : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_b_reg_Cb : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_r_reg_Cr : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_g_reg_Cr : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_b_reg_Cr : UNSIGNED(32 downto 0):= (others => '0');
begin
inFifo: CUSTOM_FIFO PORT MAP (
rst => rst,
clk => clk,
flush => '0',
holdn => '0',
INPUT_1 => INPUT_1,
write_en => write_en,
in_full => in_full,
OUTPUT_1 => AFTER_FIFO,
read_en => READ_INP,
out_empty => INPUT_EMPTY,
Next_Empty => INPUT_nEMPTY
);
ouFIFO: CUSTOM_FIFO PORT MAP (
rst => rst,
clk => clk,
flush => '0',
holdn => '0',
INPUT_1 => BEFORE_FIFO,
write_en => WRITE_OUTP,
in_full => OUTPUT_FULL,
OUTPUT_1 => OUTPUT_1,
read_en => read_en,
out_empty => out_empty,
Next_Empty => Next_Empty
);
-- ON MAPPE LES E/S DU CIRCUIT SUR LES E/S DES FIFOS
INPUT_R <= AFTER_FIFO( 7 downto 0);
INPUT_G <= AFTER_FIFO(15 downto 8);
INPUT_B <= AFTER_FIFO(23 downto 16);
BEFORE_FIFO <= "00000000" & INPUT_V & INPUT_U & INPUT_Y;
WRITE_OUTP <= PIPE_START(2);
process(rst, clk)
begin
if rst = '0' then
--REPORT "RESET";
INPUT_Y <= (others => '0');
INPUT_U <= (others => '0');
INPUT_V <= (others => '0');
PIPE_START <= "0000";
START_COMPUTE <= '0';
READ_INP <= '0';
elsif clk'event and clk = '1' then
START_COMPUTE <= not INPUT_nEMPTY;
READ_INP <= not INPUT_nEMPTY; --START_COMPUTE;
PIPE_START <= PIPE_START(2 downto 0) & START_COMPUTE;
-- ON MULTIPLIE LES DONNEES ENTRANTES PAR LES CONSTANTES
-- CODEES EN VIRGULE FIXE
if START_COMPUTE = '1' then
--REPORT "RUNNING FIRST SLICE...";
--printmsg("(PGDC) ===> (001) DATA ARE (" & to_int_str(INPUT_B,6) & ", " & to_int_str(INPUT_G,6) & ", " & to_int_str(INPUT_R,6) & ")");
rgb_in_r_reg_Y <= s_rgb_30 * UNSIGNED(INPUT_R);
rgb_in_g_reg_Y <= s_rgb_59 * UNSIGNED(INPUT_G);
rgb_in_b_reg_Y <= s_rgb_11 * UNSIGNED(INPUT_B);
rgb_in_r_reg_Cb <= s_rgb_17 * UNSIGNED(INPUT_R);
rgb_in_g_reg_Cb <= s_rgb_33 * UNSIGNED(INPUT_G);
rgb_in_b_reg_Cb <= s_rgb_50 * UNSIGNED(INPUT_B);
rgb_in_r_reg_Cr <= s_rgb_50 * UNSIGNED(INPUT_R);
rgb_in_g_reg_Cr <= s_rgb_42 * UNSIGNED(INPUT_G);
rgb_in_b_reg_Cr <= s_rgb_08 * UNSIGNED(INPUT_B);
end if;
if PIPE_START(0) = '1' then
--REPORT "RUNNING SECOND SLICE...";
s_rgb_out_y <= rgb_in_r_reg_Y + (rgb_in_g_reg_Y + rgb_in_b_reg_Y);
s_rgb_out_cb <= (s_rgb_128 - rgb_in_r_reg_Cb) - (rgb_in_g_reg_Cb + rgb_in_b_reg_Cb);
s_rgb_out_cr <= (s_rgb_128 + rgb_in_r_reg_Cr) - (rgb_in_g_reg_Cr - rgb_in_b_reg_Cr);
end if;
if PIPE_START(1) = '1' then
--REPORT "RUNNING THIRD SLICE...";
if (s_rgb_out_y(23)='1') then
INPUT_Y <= STD_LOGIC_VECTOR(s_rgb_out_y(31 downto 24) + 1);
else
INPUT_Y <= STD_LOGIC_VECTOR(s_rgb_out_y(31 downto 24));
end if;
if (s_rgb_out_cb(23)='1') then
INPUT_U <= STD_LOGIC_VECTOR(s_rgb_out_cb(31 downto 24) + 1);
else
INPUT_U <= STD_LOGIC_VECTOR(s_rgb_out_cb(31 downto 24));
end if;
if (s_rgb_out_cr(23)='1') then
INPUT_V <= STD_LOGIC_VECTOR(s_rgb_out_cr(31 downto 24) + 1);
else
INPUT_V <= STD_LOGIC_VECTOR(s_rgb_out_cr(31 downto 24));
end if;
--printmsg("(PGDC) ===> (011) DATA Y = (" & to_int_str( STD_LOGIC_VECTOR(s_rgb_out_y (31 downto 24)),6) & ")");
--printmsg("(PGDC) ===> (011) DATA U = (" & to_int_str( STD_LOGIC_VECTOR(s_rgb_out_cb(31 downto 24)),6) & ")");
--printmsg("(PGDC) ===> (011) DATA V = (" & to_int_str( STD_LOGIC_VECTOR(s_rgb_out_cr(31 downto 24)),6) & ")");
else
INPUT_Y <= INPUT_Y;
INPUT_U <= INPUT_U;
INPUT_V <= INPUT_V;
end if;
end if;
end process;
--process(INPUT_Y, INPUT_U, INPUT_V)
--BEGIN
-- printmsg("(PGDC) ===> (111) DATA ARE (" & to_int_str(INPUT_V,6) & ", " & to_int_str(INPUT_U,6) & ", " & to_int_str(INPUT_Y,6) & ")");
--END PROCESS;
end rtl;
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/mandelbrot/function_14.vhd | 5 | 1336 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_14 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_14 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(14, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/COMPLEX/CPLX_SUB_16b.vhd | 5 | 1659 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ims;
use ims.coprocessor.all;
entity CPL_ADD_16b is
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of CPL_ADD_16b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
printmsg("(IMS) COMPLEX 16bis ADD RESSOURCE : ALLOCATION OK !");
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(15 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(15 downto 0);
begin
rTemp1 := STD_LOGIC_VECTOR( SIGNED(INPUT_1(15 downto 0)) + SIGNED(INPUT_2(15 downto 0)) );
rTemp2 := STD_LOGIC_VECTOR( SIGNED(INPUT_1(31 downto 16)) + SIGNED(INPUT_2(31 downto 16)) );
--if( rTemp1(16) = '1' ) then
-- rTemp1(7 downto 0) := "1111111111111111";
--end if;
--if( rTemp2(16) = '1' ) then
-- rTemp2(7 downto 0) := "1111111111111111";
--end if;
OUTPUT_1 <= (rTemp2 & rTemp1);
end process;
-------------------------------------------------------------------------
end;
| gpl-3.0 |
chibby0ne/vhdl-book | Chapter5/exercise5_14_dir/exercise5_14.vhd | 1 | 1365 | --!
--! @file: exercise5_14.vhd
--! @brief: Recommended Unsigned Adder/Substracter
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity unsigned_adder_substracter is
generic (N: integer := 5;);
port (
a, b: in std_logic_vector(N-1 downto 0); -- operands
cin: in std_logic; -- cin
sum, sub: out std_logic_vector(N downto 0)); -- result of sum of sub with their respectives cout
end entity unsigned_adder_substracter;
--------------------------------------
architecture circuit of unsigned_adder_substracter is
signal a_un: unsigned(N-1 downto 0);
signal b_un: unsigned(N-1 downto 0);
signal sum_un: unsigned(N downto 0);
signal sub_un: unsigned(N downto 0);
begin
--------------------------------------
a_un <= unsigned(a);
b_un <= unsigned(b);
--------------------------------------
sum_un <= ('0' & a_un) + ('0' & b_un) + ('0' & cin);
sub_un <= ('0' & a_un) - ('0' & b_un) + ('0' & cin);
--------------------------------------
sum <= std_logic_vector(sum_un);
sub <= std_logic_vector(sub_un);
--------------------------------------
end architecture circuit;
--------------------------------------
| gpl-3.0 |
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